From 8407eed06ff364ed7b70b9a11a3afc5376599f82 Mon Sep 17 00:00:00 2001 From: ShinyMiraidon Date: Tue, 7 Nov 2023 14:31:28 -0500 Subject: [PATCH 1/3] add(branch_manager.cpp, Branch_Manager.sv) --- dv/branch_manager.cpp | 23 +++++++++++++++++++++++ rtl/Branch_Manager.sv | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 dv/branch_manager.cpp create mode 100644 rtl/Branch_Manager.sv diff --git a/dv/branch_manager.cpp b/dv/branch_manager.cpp new file mode 100644 index 00000000..e85c8433 --- /dev/null +++ b/dv/branch_manager.cpp @@ -0,0 +1,23 @@ +#include +#include +#include +#include +#include + +TEST_CASE("") { + + VBranch_Manager model; + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn_h = 0; + model.eval(); + + + //Test Module + for (int i = 0; i < 1000; i++) { + + } +} \ No newline at end of file diff --git a/rtl/Branch_Manager.sv b/rtl/Branch_Manager.sv new file mode 100644 index 00000000..401fd5f6 --- /dev/null +++ b/rtl/Branch_Manager.sv @@ -0,0 +1,34 @@ +module Branch_Manager ( + input clk, rstn, pred_taken, act_taken + input [WordSize - 1:0] pred_pc, pred_addr + output logic flush + output logic [WordSize - 1:0] npc +); + +logic restart; + +always @ (posedge clk or negedge rstn_h) begin + if (!rstn) begin + restart <= 1; + flush <= 0; + npc <= 0; + end + else begin + if ((pred_taken != act_taken) && !restart) begin + flush <= 1; + case(act_taken) + 0: npc <= pred_pc + 4 + 1: npc <= pred_addr + endcase + end + else begin + flush <= 0; + case(pred_taken) + 0: npc <= pred_pc + 4 + 1: npc <= pred_addr + endcase + end + if (restart) restart <= 0; + end +end +endmodule \ No newline at end of file From 82e97690fdb51590af7ed1714d576048de0758ab Mon Sep 17 00:00:00 2001 From: ShinyMiraidon Date: Thu, 9 Nov 2023 11:51:45 -0500 Subject: [PATCH 2/3] test(branch_manager): Added more to test --- dv/branch_manager.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dv/branch_manager.cpp b/dv/branch_manager.cpp index e85c8433..6cc7391a 100644 --- a/dv/branch_manager.cpp +++ b/dv/branch_manager.cpp @@ -14,7 +14,7 @@ TEST_CASE("") { model.eval(); model.rstn_h = 0; model.eval(); - + //Test Module for (int i = 0; i < 1000; i++) { From fb1364b6f43a7d377fead5de0e648615332f3883 Mon Sep 17 00:00:00 2001 From: ShinyMiraidon Date: Tue, 14 Nov 2023 14:34:25 -0500 Subject: [PATCH 3/3] module(Branch Manager): Finished Tests --- dv/branch_manager.cpp | 132 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 2 deletions(-) diff --git a/dv/branch_manager.cpp b/dv/branch_manager.cpp index 6cc7391a..170f4bc9 100644 --- a/dv/branch_manager.cpp +++ b/dv/branch_manager.cpp @@ -4,7 +4,7 @@ #include #include -TEST_CASE("") { +TEST_CASE("Flush") { VBranch_Manager model; @@ -14,10 +14,138 @@ TEST_CASE("") { model.eval(); model.rstn_h = 0; model.eval(); + + //Move out of starting conditions + model.clk = 0; + model.eval(); + model.clk = 1; + model.rstn = 1; + model.eval(); + + bool pred_taken; + bool act_taken; + uint32_t pred_pc; + uint32_t pred_addr; + + //Test Module + for (int i = 0; i < 1000; i++) { + pred_taken = rand() % (int) (pow(2, 1) - 1); + act_taken = rand() % (int) (pow(2, 1) - 1); + pred_pc = rand() % (int) (pow(32, 1) - 1); + pred_addr = rand() % (int) (pow(32, 1) - 1); + + model.clk = 0; + model.eval(); + + model.clk = 1; + model.rstn = 1; + + model.pred_taken = pred_taken; + model.act_taken = act_taken; + model.pred_pc = pred_pc; + model.pred_addr = pred_addr; + model.eval(); + + REQUIRE((bool) model.flush == (bool) (pred_taken ^ act_taken)); + } +} + +TEST_CASE("Incorrect Prediction") { + + VBranch_Manager model; + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn_h = 0; + model.eval(); + + //Move out of starting conditions + model.clk = 0; + model.eval(); + model.clk = 1; + model.rstn = 1; + model.eval(); + + bool pred_taken; + bool act_taken; + uint32_t npc; + uint32_t pred_pc; + uint32_t pred_addr; + //Test Module + for (int i = 0; i < 1000; i++) { + pred_taken = rand() % (int) (pow(2, 1) - 1); + act_taken = ~pred_taken; + pred_pc = rand() % (int) (pow(32, 1) - 1); + pred_addr = rand() % (int) (pow(32, 1) - 1); + + model.clk = 0; + model.eval(); + + model.clk = 1; + model.rstn = 1; + + model.pred_taken = pred_taken; + model.act_taken = act_taken; + model.pred_pc = pred_pc; + model.pred_addr = pred_addr; + model.eval(); + + if (act_taken) npc = pred_pc; + else npc = pred_pc + 4; + + REQUIRE((uint32_t) model.npc == (uint32_t) (npc)); + } +} + +TEST_CASE("Correct Prediction") { + + VBranch_Manager model; + + //Initialize Module + model.rstn = 1; + model.clk = 0; + model.eval(); + model.rstn_h = 0; + model.eval(); + + //Move out of starting conditions + model.clk = 0; + model.eval(); + model.clk = 1; + model.rstn = 1; + model.eval(); + + bool pred_taken; + bool act_taken; + uint32_t npc; + uint32_t pred_pc; + uint32_t pred_addr; //Test Module for (int i = 0; i < 1000; i++) { + pred_taken = rand() % (int) (pow(2, 1) - 1); + act_taken = pred_taken; + pred_pc = rand() % (int) (pow(32, 1) - 1); + pred_addr = rand() % (int) (pow(32, 1) - 1); + model.clk = 0; + model.eval(); + + model.clk = 1; + model.rstn = 1; + + model.pred_taken = pred_taken; + model.act_taken = act_taken; + model.pred_pc = pred_pc; + model.pred_addr = pred_addr; + model.eval(); + + if (pred_taken) npc = pred_pc; + else npc = pred_pc + 4; + + REQUIRE((uint32_t) model.npc == (uint32_t) (npc)); } -} \ No newline at end of file +}