diff --git a/CHANGELOG.md b/CHANGELOG.md index 122a20ef3..8a10a078e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,25 @@ # Changelog All notable changes to this project are documented in this file. +## [1.6.0] - 2019-01-18 +### Added +- Added support for nRF52811. +- Added support for the legacy peripherals SPI, TWI, and UART in nRF52810. +- Added support for SAMPLERATE in nrf_saadc.h. +- Added clearing of the STOPPED event in the nrfx_saadc_init() function to prevent driver deadlock in some cases. +- Added HALs: BPROT, MPU, MWU. +- Added function for reading the pin input buffer configuration in the GPIO HAL. +- Implemented workaround for nRF9160 anomaly 1 in the I2S driver. + +### Changed +- Improved handling of hardware anomalies in the USBD driver. +- Updated MDK to version 8.23.1. + +### Fixed +- Fixed the condition in NRFX_WAIT_FOR in the nrfx_saadc_abort() function. The macro now correctly waits for a stop of the driver. +- Fixed the pending interrupt clearing in NVIC in the nrfx_usbd_stop() function. The driver now correctly handles power management. +- Fixed the case when nrfx_uarte_tx_in_progress() function would return an incorrect value. The driver now correctly updates the tx_buffer_length variable internally. + ## [1.5.0] - 2018-12-12 ### Added - Added support for nRF9160. diff --git a/LICENSE b/LICENSE index 67c8788b2..ed92c3b4f 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2017 - 2018, Nordic Semiconductor ASA +Copyright (c) 2017 - 2019, Nordic Semiconductor ASA All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/README.md b/README.md index adc127847..ab233c0ee 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,7 @@ SoCs, as well as startup and initialization files for them. * nRF51 Series * nRF52810 +* nRF52811 * nRF52832 * nRF52840 * nRF9160 diff --git a/doc/config_dox/nrfx_adc_dox_config.h b/doc/config_dox/nrfx_adc_dox_config.h index 2ced90cd4..a78308bd5 100644 --- a/doc/config_dox/nrfx_adc_dox_config.h +++ b/doc/config_dox/nrfx_adc_dox_config.h @@ -18,10 +18,6 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_clock_dox_config.h b/doc/config_dox/nrfx_clock_dox_config.h index fbf890c3a..4a772d631 100644 --- a/doc/config_dox/nrfx_clock_dox_config.h +++ b/doc/config_dox/nrfx_clock_dox_config.h @@ -37,10 +37,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_comp_dox_config.h b/doc/config_dox/nrfx_comp_dox_config.h index 896c44713..353e3b7d3 100644 --- a/doc/config_dox/nrfx_comp_dox_config.h +++ b/doc/config_dox/nrfx_comp_dox_config.h @@ -90,10 +90,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_gpiote_dox_config.h b/doc/config_dox/nrfx_gpiote_dox_config.h index 57b2e19d1..7eddaa90c 100644 --- a/doc/config_dox/nrfx_gpiote_dox_config.h +++ b/doc/config_dox/nrfx_gpiote_dox_config.h @@ -25,10 +25,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_i2s_dox_config.h b/doc/config_dox/nrfx_i2s_dox_config.h index 389a99667..de315e918 100644 --- a/doc/config_dox/nrfx_i2s_dox_config.h +++ b/doc/config_dox/nrfx_i2s_dox_config.h @@ -157,10 +157,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_lpcomp_dox_config.h b/doc/config_dox/nrfx_lpcomp_dox_config.h index fe17d42fc..f74c2bbee 100644 --- a/doc/config_dox/nrfx_lpcomp_dox_config.h +++ b/doc/config_dox/nrfx_lpcomp_dox_config.h @@ -78,10 +78,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_nfct_dox_config.h b/doc/config_dox/nrfx_nfct_dox_config.h index d484e5c1d..02464373a 100644 --- a/doc/config_dox/nrfx_nfct_dox_config.h +++ b/doc/config_dox/nrfx_nfct_dox_config.h @@ -19,10 +19,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_pdm_dox_config.h b/doc/config_dox/nrfx_pdm_dox_config.h index 3aa5da9cf..9e7e146b4 100644 --- a/doc/config_dox/nrfx_pdm_dox_config.h +++ b/doc/config_dox/nrfx_pdm_dox_config.h @@ -49,10 +49,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_power_dox_config.h b/doc/config_dox/nrfx_power_dox_config.h index c62f31a2a..4970e16b1 100644 --- a/doc/config_dox/nrfx_power_dox_config.h +++ b/doc/config_dox/nrfx_power_dox_config.h @@ -18,10 +18,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_pwm_dox_config.h b/doc/config_dox/nrfx_pwm_dox_config.h index 8fb46cfd6..9cd940371 100644 --- a/doc/config_dox/nrfx_pwm_dox_config.h +++ b/doc/config_dox/nrfx_pwm_dox_config.h @@ -141,10 +141,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_qdec_dox_config.h b/doc/config_dox/nrfx_qdec_dox_config.h index 24931cd0d..2a4363731 100644 --- a/doc/config_dox/nrfx_qdec_dox_config.h +++ b/doc/config_dox/nrfx_qdec_dox_config.h @@ -110,10 +110,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_qspi_dox_config.h b/doc/config_dox/nrfx_qspi_dox_config.h index b2401a183..f89126747 100644 --- a/doc/config_dox/nrfx_qspi_dox_config.h +++ b/doc/config_dox/nrfx_qspi_dox_config.h @@ -157,10 +157,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_rng_dox_config.h b/doc/config_dox/nrfx_rng_dox_config.h index ff7ed1b80..0fecf56b4 100644 --- a/doc/config_dox/nrfx_rng_dox_config.h +++ b/doc/config_dox/nrfx_rng_dox_config.h @@ -26,10 +26,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_rtc_dox_config.h b/doc/config_dox/nrfx_rtc_dox_config.h index 4a7ee14c7..ded1885b0 100644 --- a/doc/config_dox/nrfx_rtc_dox_config.h +++ b/doc/config_dox/nrfx_rtc_dox_config.h @@ -66,10 +66,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_saadc_dox_config.h b/doc/config_dox/nrfx_saadc_dox_config.h index c60f2ce78..39011f2c9 100644 --- a/doc/config_dox/nrfx_saadc_dox_config.h +++ b/doc/config_dox/nrfx_saadc_dox_config.h @@ -55,10 +55,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_spi_dox_config.h b/doc/config_dox/nrfx_spi_dox_config.h index b0625d36f..29b647d1a 100644 --- a/doc/config_dox/nrfx_spi_dox_config.h +++ b/doc/config_dox/nrfx_spi_dox_config.h @@ -53,10 +53,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_spim_dox_config.h b/doc/config_dox/nrfx_spim_dox_config.h index 2bea58178..0ff821057 100644 --- a/doc/config_dox/nrfx_spim_dox_config.h +++ b/doc/config_dox/nrfx_spim_dox_config.h @@ -69,10 +69,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_spis_dox_config.h b/doc/config_dox/nrfx_spis_dox_config.h index e824ad94a..df51d2bed 100644 --- a/doc/config_dox/nrfx_spis_dox_config.h +++ b/doc/config_dox/nrfx_spis_dox_config.h @@ -42,10 +42,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_timer_dox_config.h b/doc/config_dox/nrfx_timer_dox_config.h index f6d19cf6e..6d449eab0 100644 --- a/doc/config_dox/nrfx_timer_dox_config.h +++ b/doc/config_dox/nrfx_timer_dox_config.h @@ -98,10 +98,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_twi_dox_config.h b/doc/config_dox/nrfx_twi_dox_config.h index 5bd1b545d..40c13d110 100644 --- a/doc/config_dox/nrfx_twi_dox_config.h +++ b/doc/config_dox/nrfx_twi_dox_config.h @@ -53,10 +53,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_twim_dox_config.h b/doc/config_dox/nrfx_twim_dox_config.h index 713b490af..5cb662035 100644 --- a/doc/config_dox/nrfx_twim_dox_config.h +++ b/doc/config_dox/nrfx_twim_dox_config.h @@ -53,10 +53,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_twis_dox_config.h b/doc/config_dox/nrfx_twis_dox_config.h index 7b790a1c3..dca95b3e1 100644 --- a/doc/config_dox/nrfx_twis_dox_config.h +++ b/doc/config_dox/nrfx_twis_dox_config.h @@ -90,10 +90,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_uart_dox_config.h b/doc/config_dox/nrfx_uart_dox_config.h index 3b4f47912..d24bd8b8e 100644 --- a/doc/config_dox/nrfx_uart_dox_config.h +++ b/doc/config_dox/nrfx_uart_dox_config.h @@ -71,10 +71,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_uarte_dox_config.h b/doc/config_dox/nrfx_uarte_dox_config.h index 1d27c291c..08a3fc178 100644 --- a/doc/config_dox/nrfx_uarte_dox_config.h +++ b/doc/config_dox/nrfx_uarte_dox_config.h @@ -78,10 +78,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_usbd_dox_config.h b/doc/config_dox/nrfx_usbd_dox_config.h index 1aed3088e..29f4e4e44 100644 --- a/doc/config_dox/nrfx_usbd_dox_config.h +++ b/doc/config_dox/nrfx_usbd_dox_config.h @@ -18,10 +18,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 + * - 5 - 5 + * - 6 - 6 + * - 7 - 7 * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/config_dox/nrfx_wdt_dox_config.h b/doc/config_dox/nrfx_wdt_dox_config.h index e2600a211..5399a4c89 100644 --- a/doc/config_dox/nrfx_wdt_dox_config.h +++ b/doc/config_dox/nrfx_wdt_dox_config.h @@ -49,10 +49,10 @@ * - 1 - 1 * - 2 - 2 * - 3 - 3 - * - 4 - 4 (Software Component only) - * - 5 - 5 (Software Component only) - * - 6 - 6 (Software Component only) - * - 7 - 7 (Software Component only) + * - 4 - 4 (Not applicable for nRF51) + * - 5 - 5 (Not applicable for nRF51) + * - 6 - 6 (Not applicable for nRF51) + * - 7 - 7 (Not applicable for nRF51) * * @note This is an NRF_CONFIG macro. */ diff --git a/doc/drv_supp_matrix.dox b/doc/drv_supp_matrix.dox index 5160c5c75..ea32f3c34 100644 --- a/doc/drv_supp_matrix.dox +++ b/doc/drv_supp_matrix.dox @@ -3,48 +3,51 @@ The following matrix shows which drivers are supported by specific Nordic SoCs. @{ -Driver | nRF51 Series | nRF52810 | nRF52832 | nRF52840 | nRF9160 | ------------------|--------------|--------------| -------------| -------------| -------------| -@ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -@ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_comp |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | -@ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | -@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_nfct |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_pwm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spi |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | -@ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_swi_egu |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_twi |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_uart |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | -@ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +Driver | nRF51 Series | nRF52810/nRF52811 | nRF52832 | nRF52840 | nRF9160 | +-----------------|--------------|-------------------| -------------| -------------| -------------| +@ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +@ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +@ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +@ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_comp |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +@ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +@ref nrf_mwu |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_nfct |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_pwm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +@ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +@ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_swi_egu |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +@ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +@ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +@ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick | +@ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | @} */ diff --git a/doc/nrf51_series.dox b/doc/nrf51_series.dox index 808d265e0..2e9a50555 100644 --- a/doc/nrf51_series.dox +++ b/doc/nrf51_series.dox @@ -16,6 +16,8 @@ @ref nrf_lpcomp +@ref nrf_mpu + @ref nrf_nvmc @ref nrf_power diff --git a/doc/nrf52810.dox b/doc/nrf52810.dox index 965c4ff5c..ab6aaef00 100644 --- a/doc/nrf52810.dox +++ b/doc/nrf52810.dox @@ -1,7 +1,9 @@ /** -@page nrf52810_drivers nRF52810 Drivers +@page nrf52810_drivers nRF52810/nRF52811 Drivers @{ +@ref nrf_bprot + @ref nrf_ccm @ref nrf_clock @@ -34,6 +36,8 @@ @ref nrf_saadc +@ref nrf_spi + @ref nrf_spim @ref nrf_spis @@ -46,10 +50,14 @@ @ref nrf_timer +@ref nrf_twi + @ref nrf_twim @ref nrf_twis +@ref nrf_uart + @ref nrf_uarte @ref nrf_wdt diff --git a/doc/nrf52832.dox b/doc/nrf52832.dox index 10a51729a..5ddaea276 100644 --- a/doc/nrf52832.dox +++ b/doc/nrf52832.dox @@ -2,6 +2,8 @@ @page nrf52832_drivers nRF52832 Drivers @{ +@ref nrf_bprot + @ref nrf_ccm @ref nrf_clock @@ -18,6 +20,8 @@ @ref nrf_lpcomp +@ref nrf_mwu + @ref nrf_nfct @ref nrf_nvmc diff --git a/doc/nrf52840.dox b/doc/nrf52840.dox index 38f3cffea..a3595b0f7 100644 --- a/doc/nrf52840.dox +++ b/doc/nrf52840.dox @@ -20,6 +20,8 @@ @ref nrf_lpcomp +@ref nrf_mwu + @ref nrf_nfct @ref nrf_nvmc diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index d1b1978a7..da96b8108 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -33,7 +33,7 @@ PROJECT_NAME = "nrfx" # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = "1.5" +PROJECT_NUMBER = "1.6" ### EDIT THIS ### # Using the PROJECT_BRIEF tag one can provide an optional one line description diff --git a/doc/nrfx_api.dox b/doc/nrfx_api.dox index 9bd518951..0de2dcc89 100644 --- a/doc/nrfx_api.dox +++ b/doc/nrfx_api.dox @@ -6,6 +6,8 @@ @defgroup nrf_acl ACL +@defgroup nrf_bprot BPROT + @defgroup nrf_ccm CCM @defgroup nrf_clock CLOCK @@ -26,6 +28,10 @@ @defgroup nrf_lpcomp LPCOMP +@defgroup nrf_mpu MPU + +@defgroup nrf_mwu MWU + @defgroup nrf_nfct NFCT @defgroup nrf_nvmc NVMC diff --git a/drivers/include/nrf_bitmask.h b/drivers/include/nrf_bitmask.h index 229f88b8e..9b71271de 100644 --- a/drivers/include/nrf_bitmask.h +++ b/drivers/include/nrf_bitmask.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_adc.h b/drivers/include/nrfx_adc.h index a2361fd82..589fed724 100644 --- a/drivers/include/nrfx_adc.h +++ b/drivers/include/nrfx_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_clock.h b/drivers/include/nrfx_clock.h index 151d70f08..0e6cd9812 100644 --- a/drivers/include/nrfx_clock.h +++ b/drivers/include/nrfx_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_comp.h b/drivers/include/nrfx_comp.h index f7a5c13c6..1089d8393 100644 --- a/drivers/include/nrfx_comp.h +++ b/drivers/include/nrfx_comp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_dppi.h b/drivers/include/nrfx_dppi.h index 365a10867..d4dcbb5c6 100644 --- a/drivers/include/nrfx_dppi.h +++ b/drivers/include/nrfx_dppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_gpiote.h b/drivers/include/nrfx_gpiote.h index c0b1886cc..e94d1f31c 100644 --- a/drivers/include/nrfx_gpiote.h +++ b/drivers/include/nrfx_gpiote.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_i2s.h b/drivers/include/nrfx_i2s.h index ea4e4d0b3..2c4bf96f1 100644 --- a/drivers/include/nrfx_i2s.h +++ b/drivers/include/nrfx_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_lpcomp.h b/drivers/include/nrfx_lpcomp.h index fada3ae50..1f4a4a064 100644 --- a/drivers/include/nrfx_lpcomp.h +++ b/drivers/include/nrfx_lpcomp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_nfct.h b/drivers/include/nrfx_nfct.h index ceb5a340b..c90ca3dff 100644 --- a/drivers/include/nrfx_nfct.h +++ b/drivers/include/nrfx_nfct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_pdm.h b/drivers/include/nrfx_pdm.h index 49d5dbf7c..d7896dd14 100644 --- a/drivers/include/nrfx_pdm.h +++ b/drivers/include/nrfx_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_power.h b/drivers/include/nrfx_power.h index 3d12b27e8..ba87f29bc 100644 --- a/drivers/include/nrfx_power.h +++ b/drivers/include/nrfx_power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_power_clock.h b/drivers/include/nrfx_power_clock.h index 958d82d29..043b0e49b 100644 --- a/drivers/include/nrfx_power_clock.h +++ b/drivers/include/nrfx_power_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_ppi.h b/drivers/include/nrfx_ppi.h index 6db6adc6a..cbd26901d 100644 --- a/drivers/include/nrfx_ppi.h +++ b/drivers/include/nrfx_ppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_pwm.h b/drivers/include/nrfx_pwm.h index 6e72486be..ec05b42dd 100644 --- a/drivers/include/nrfx_pwm.h +++ b/drivers/include/nrfx_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_qdec.h b/drivers/include/nrfx_qdec.h index c8b3f6447..f1e5a85ef 100644 --- a/drivers/include/nrfx_qdec.h +++ b/drivers/include/nrfx_qdec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_qspi.h b/drivers/include/nrfx_qspi.h index 8e2de1693..36bb579ce 100644 --- a/drivers/include/nrfx_qspi.h +++ b/drivers/include/nrfx_qspi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_rng.h b/drivers/include/nrfx_rng.h index 2188b10dd..6add7f73a 100644 --- a/drivers/include/nrfx_rng.h +++ b/drivers/include/nrfx_rng.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_rtc.h b/drivers/include/nrfx_rtc.h index 1cc9eedaf..e41713b02 100644 --- a/drivers/include/nrfx_rtc.h +++ b/drivers/include/nrfx_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_saadc.h b/drivers/include/nrfx_saadc.h index db5687505..08135261b 100644 --- a/drivers/include/nrfx_saadc.h +++ b/drivers/include/nrfx_saadc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_spi.h b/drivers/include/nrfx_spi.h index 929a267ac..91d0b0a3d 100644 --- a/drivers/include/nrfx_spi.h +++ b/drivers/include/nrfx_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index cc9499145..241f95369 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_spis.h b/drivers/include/nrfx_spis.h index 35054e3f0..370e12412 100644 --- a/drivers/include/nrfx_spis.h +++ b/drivers/include/nrfx_spis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_swi.h b/drivers/include/nrfx_swi.h index 24bd12313..653c3e79d 100644 --- a/drivers/include/nrfx_swi.h +++ b/drivers/include/nrfx_swi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_systick.h b/drivers/include/nrfx_systick.h index 9e9678c54..0da2d6078 100644 --- a/drivers/include/nrfx_systick.h +++ b/drivers/include/nrfx_systick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_timer.h b/drivers/include/nrfx_timer.h index b6c648af5..447b98854 100644 --- a/drivers/include/nrfx_timer.h +++ b/drivers/include/nrfx_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_twi.h b/drivers/include/nrfx_twi.h index f7e2dff4f..512e2e357 100644 --- a/drivers/include/nrfx_twi.h +++ b/drivers/include/nrfx_twi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index 7d10ae568..73aa4451f 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_twis.h b/drivers/include/nrfx_twis.h index dae70e92a..a9ba5fbae 100644 --- a/drivers/include/nrfx_twis.h +++ b/drivers/include/nrfx_twis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_uart.h b/drivers/include/nrfx_uart.h index 855f1cc7e..adbb9d375 100644 --- a/drivers/include/nrfx_uart.h +++ b/drivers/include/nrfx_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_uarte.h b/drivers/include/nrfx_uarte.h index 4396e11e6..da767cd28 100644 --- a/drivers/include/nrfx_uarte.h +++ b/drivers/include/nrfx_uarte.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_usbd.h b/drivers/include/nrfx_usbd.h index 756d4e9e5..0b2aa3f60 100644 --- a/drivers/include/nrfx_usbd.h +++ b/drivers/include/nrfx_usbd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/include/nrfx_wdt.h b/drivers/include/nrfx_wdt.h index 7124763ce..023ae8b7d 100644 --- a/drivers/include/nrfx_wdt.h +++ b/drivers/include/nrfx_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index 9423ee2fd..e988a7de0 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -173,22 +173,32 @@ do { \ } while (--remaining_attempts); \ } while(0) +/** + * @brief Macro for getting the ID number of the specified peripheral. + * + * For peripherals in Nordic SoCs, there is a direct relationship between their + * ID numbers and their base addresses. See the chapter "Peripheral interface" + * (section "Peripheral ID") in the Product Specification. + * + * @param[in] base_addr Peripheral base address or pointer. + * + * @return ID number associated with the specified peripheral. + */ +#define NRFX_PERIPHERAL_ID_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12) + /** * @brief Macro for getting the interrupt number assigned to a specific * peripheral. * - * In Nordic SoCs the IRQ number assigned to a peripheral is equal to the ID - * of this peripheral, and there is a direct relationship between this ID and - * the peripheral base address, i.e. the address of a fixed block of 0x1000 - * bytes of address space assigned to this peripheral. - * See the chapter "Peripheral interface" (sections "Peripheral ID" and - * "Interrupts") in the product specification of a given SoC. + * For peripherals in Nordic SoCs, the IRQ number assigned to a peripheral is + * equal to its ID number. See the chapter "Peripheral interface" (sections + * "Peripheral ID" and "Interrupts") in the Product Specification. * * @param[in] base_addr Peripheral base address or pointer. * * @return Interrupt number associated with the specified peripheral. */ -#define NRFX_IRQ_NUMBER_GET(base_addr) (uint8_t)((uint32_t)(base_addr) >> 12) +#define NRFX_IRQ_NUMBER_GET(base_addr) NRFX_PERIPHERAL_ID_GET(base_addr) /** * @brief IRQ handler type. diff --git a/drivers/nrfx_errors.h b/drivers/nrfx_errors.h index 31062ce89..f50322701 100644 --- a/drivers/nrfx_errors.h +++ b/drivers/nrfx_errors.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_adc.c b/drivers/src/nrfx_adc.c index 4f74a7af8..59c2faebb 100644 --- a/drivers/src/nrfx_adc.c +++ b/drivers/src/nrfx_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index ddf30af04..46e38856d 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_comp.c b/drivers/src/nrfx_comp.c index b52af8501..801b4767b 100644 --- a/drivers/src/nrfx_comp.c +++ b/drivers/src/nrfx_comp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -133,8 +133,8 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, nrf_comp_input_select(p_config->input); - NRFX_IRQ_PRIORITY_SET(COMP_LPCOMP_IRQn, p_config->interrupt_priority); - NRFX_IRQ_ENABLE(COMP_LPCOMP_IRQn); + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_COMP), p_config->interrupt_priority); + NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_COMP)); m_state = NRFX_DRV_STATE_INITIALIZED; @@ -146,7 +146,7 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, void nrfx_comp_uninit(void) { NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_IRQ_DISABLE(COMP_LPCOMP_IRQn); + NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_COMP)); nrf_comp_disable(); #if NRFX_CHECK(NRFX_PRS_ENABLED) nrfx_prs_release(NRF_COMP); diff --git a/drivers/src/nrfx_dppi.c b/drivers/src/nrfx_dppi.c index 53dfd4446..b6b6380b6 100644 --- a/drivers/src/nrfx_dppi.c +++ b/drivers/src/nrfx_dppi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_gpiote.c b/drivers/src/nrfx_gpiote.c index 4de5d85e2..e68fdcb22 100644 --- a/drivers/src/nrfx_gpiote.c +++ b/drivers/src/nrfx_gpiote.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_i2s.c b/drivers/src/nrfx_i2s.c index 71d44b7f9..eed5f1ee8 100644 --- a/drivers/src/nrfx_i2s.c +++ b/drivers/src/nrfx_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,14 +45,12 @@ (event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : \ "UNKNOWN EVENT"))) -#if !defined(USE_WORKAROUND_FOR_ANOMALY_194) && \ - (defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ - defined(NRF52840_XXAA)) -// Enable workaround for nRF52832 and nRF52840 anomaly 194 (STOP task does not -// switch off all resources). -#define USE_WORKAROUND_FOR_ANOMALY_194 1 -#else -#define USE_WORKAROUND_FOR_ANOMALY_194 0 +#if !defined(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) && \ + (defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA) || \ + defined(NRF9160_XXAA)) +// Enable workaround for nRF52832 and nRF52840 anomaly 194 / nrf9160 anomaly 1 +// (STOP task does not switch off all resources). +#define USE_WORKAROUND_FOR_I2S_STOP_ANOMALY 1 #endif // Control block - driver instance local data. @@ -344,9 +342,9 @@ void nrfx_i2s_stop(void) NRF_I2S_INT_TXPTRUPD_MASK); nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP); -#if USE_WORKAROUND_FOR_ANOMALY_194 - *((volatile uint32_t *)0x40025038) = 1; - *((volatile uint32_t *)0x4002503C) = 1; +#if NRFX_CHECK(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) + *((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x38)) = 1; + *((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x3C)) = 1; #endif } diff --git a/drivers/src/nrfx_lpcomp.c b/drivers/src/nrfx_lpcomp.c index 7e60acc11..019513c86 100644 --- a/drivers/src/nrfx_lpcomp.c +++ b/drivers/src/nrfx_lpcomp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index b66411320..5b83becb7 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_pdm.c b/drivers/src/nrfx_pdm.c index 98eda0530..1789e4491 100644 --- a/drivers/src/nrfx_pdm.c +++ b/drivers/src/nrfx_pdm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_power.c b/drivers/src/nrfx_power.c index e3d5a83ce..a12a64e2c 100644 --- a/drivers/src/nrfx_power.c +++ b/drivers/src/nrfx_power.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_ppi.c b/drivers/src/nrfx_ppi.c index b3c2d3543..8c563ffbf 100644 --- a/drivers/src/nrfx_ppi.c +++ b/drivers/src/nrfx_ppi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_pwm.c b/drivers/src/nrfx_pwm.c index e57e48879..7fa811c12 100644 --- a/drivers/src/nrfx_pwm.c +++ b/drivers/src/nrfx_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index a86ff780b..78c88b9c6 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_qspi.c b/drivers/src/nrfx_qspi.c index feb4346b5..1b339bfb0 100644 --- a/drivers/src/nrfx_qspi.c +++ b/drivers/src/nrfx_qspi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_rng.c b/drivers/src/nrfx_rng.c index 5fc9d429f..cc6583c5c 100644 --- a/drivers/src/nrfx_rng.c +++ b/drivers/src/nrfx_rng.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_rtc.c b/drivers/src/nrfx_rtc.c index 8acb4dbd9..73cbdfd30 100644 --- a/drivers/src/nrfx_rtc.c +++ b/drivers/src/nrfx_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index a149c6b13..9c5474546 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -228,6 +228,7 @@ nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config, nrf_saadc_int_disable(NRF_SAADC_INT_ALL); nrf_saadc_event_clear(NRF_SAADC_EVENT_END); nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED); + nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED); NRFX_IRQ_PRIORITY_SET(SAADC_IRQn, p_config->interrupt_priority); NRFX_IRQ_ENABLE(SAADC_IRQn); nrf_saadc_int_enable(NRF_SAADC_INT_END); @@ -580,7 +581,7 @@ void nrfx_saadc_abort(void) { // Wait for ADC being stopped. bool result; - NRFX_WAIT_FOR((m_cb.adc_state != NRF_SAADC_STATE_IDLE), HW_TIMEOUT, 0, result); + NRFX_WAIT_FOR((m_cb.adc_state == NRF_SAADC_STATE_IDLE), HW_TIMEOUT, 0, result); NRFX_ASSERT(result); } diff --git a/drivers/src/nrfx_spi.c b/drivers/src/nrfx_spi.c index b9d3da6a6..8e9e15b60 100644 --- a/drivers/src/nrfx_spi.c +++ b/drivers/src/nrfx_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_spim.c b/drivers/src/nrfx_spim.c index 318fecb0b..ff1a835a4 100644 --- a/drivers/src/nrfx_spim.c +++ b/drivers/src/nrfx_spim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index cf396cb08..88963cee2 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2013 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_swi.c b/drivers/src/nrfx_swi.c index 5db4b7f00..035f981c9 100644 --- a/drivers/src/nrfx_swi.c +++ b/drivers/src/nrfx_swi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -155,10 +155,12 @@ static bool swi_is_available(nrfx_swi_t swi) static IRQn_Type swi_irq_number_get(nrfx_swi_t swi) { -#if defined(SWI_PRESENT) - return (IRQn_Type)((uint32_t)SWI0_IRQn + (uint32_t)swi); +#if defined(NRF_SWI) + return (IRQn_Type)(nrfx_get_irq_number(NRF_SWI) + swi); +#elif defined(NRF_SWI0) + return (IRQn_Type)(nrfx_get_irq_number(NRF_SWI0) + swi); #else - return (IRQn_Type)((uint32_t)EGU0_IRQn + (uint32_t)swi); + return (IRQn_Type)(nrfx_get_irq_number(NRF_EGU0) + swi); #endif } diff --git a/drivers/src/nrfx_systick.c b/drivers/src/nrfx_systick.c index 6854baffd..878c06842 100644 --- a/drivers/src/nrfx_systick.c +++ b/drivers/src/nrfx_systick.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_timer.c b/drivers/src/nrfx_timer.c index b49e9585f..077406307 100644 --- a/drivers/src/nrfx_timer.c +++ b/drivers/src/nrfx_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_twi.c b/drivers/src/nrfx_twi.c index 89d3a77bd..a4e85d8ea 100644 --- a/drivers/src/nrfx_twi.c +++ b/drivers/src/nrfx_twi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -209,8 +209,8 @@ void nrfx_twi_uninit(nrfx_twi_t const * p_instance) if (!p_cb->hold_bus_uninit) { - nrf_gpio_cfg_default(p_instance->p_twi->PSELSCL); - nrf_gpio_cfg_default(p_instance->p_twi->PSELSDA); + nrf_gpio_cfg_default(nrf_twi_scl_pin_get(p_instance->p_twi)); + nrf_gpio_cfg_default(nrf_twi_sda_pin_get(p_instance->p_twi)); } p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; diff --git a/drivers/src/nrfx_twim.c b/drivers/src/nrfx_twim.c index 75da22a3b..69f1974f5 100644 --- a/drivers/src/nrfx_twim.c +++ b/drivers/src/nrfx_twim.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_twis.c b/drivers/src/nrfx_twis.c index 848788606..09c875c4a 100644 --- a/drivers/src/nrfx_twis.c +++ b/drivers/src/nrfx_twis.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_uart.c b/drivers/src/nrfx_uart.c index 203fe3882..8e3c37715 100644 --- a/drivers/src/nrfx_uart.c +++ b/drivers/src/nrfx_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_uarte.c b/drivers/src/nrfx_uarte.c index a80f22ad1..a74ac6e48 100644 --- a/drivers/src/nrfx_uarte.c +++ b/drivers/src/nrfx_uarte.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/nrfx_usbd.c b/drivers/src/nrfx_usbd.c index 71a1e6921..302ae9b44 100644 --- a/drivers/src/nrfx_usbd.c +++ b/drivers/src/nrfx_usbd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -65,6 +65,10 @@ #endif #ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP +/* + * Respond to an IN token on ISO IN endpoint with ZLP when no data is ready. + * NOTE: This option does not work on Engineering A chip. + */ #define NRFX_USBD_CONFIG_ISO_IN_ZLP 0 #endif @@ -753,13 +757,11 @@ static inline void usbd_dma_start(nrfx_usbd_ep_t ep) void nrfx_usbd_isoinconfig_set(nrf_usbd_isoinconfig_t config) { - NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a()); nrf_usbd_isoinconfig_set(config); } nrf_usbd_isoinconfig_t nrfx_usbd_isoinconfig_get(void) { - NRFX_ASSERT(!nrfx_usbd_errata_type_52840_eng_a()); return nrf_usbd_isoinconfig_get(); } @@ -1657,12 +1659,6 @@ void nrfx_usbd_irq_handler(void) nrfx_err_t nrfx_usbd_init(nrfx_usbd_event_handler_t event_handler) { - NRFX_ASSERT((nrfx_usbd_errata_type_52840_eng_a() || - nrfx_usbd_errata_type_52840_eng_b() || - nrfx_usbd_errata_type_52840_eng_c() || - nrfx_usbd_errata_type_52840_eng_d()) - ); - NRFX_ASSERT(event_handler); if (m_drv_state != NRFX_DRV_STATE_UNINITIALIZED) @@ -1864,6 +1860,9 @@ void nrfx_usbd_stop(void) { NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_POWERED_ON); + /* Clear interrupt */ + NRFX_IRQ_PENDING_CLEAR(USBD_IRQn); + if (NRFX_IRQ_IS_ENABLED(USBD_IRQn)) { /* Abort transfers */ @@ -1914,20 +1913,6 @@ bool nrfx_usbd_suspend(void) else { suspended = true; - - if (nrfx_usbd_errata_171()) - { - if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) - { - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - } - else - { - *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; - } - } } } } diff --git a/drivers/src/nrfx_usbd_errata.h b/drivers/src/nrfx_usbd_errata.h index b95d780b3..fb2185253 100644 --- a/drivers/src/nrfx_usbd_errata.h +++ b/drivers/src/nrfx_usbd_errata.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -50,34 +50,34 @@ static inline bool nrfx_usbd_errata_type_52840(void) static inline bool nrfx_usbd_errata_type_52840_eng_a(void) { - return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x0UL)); + return nrfx_usbd_errata_type_52840(); } static inline bool nrfx_usbd_errata_type_52840_eng_b(void) { - return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x1UL)); + return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x1UL)); } static inline bool nrfx_usbd_errata_type_52840_eng_c(void) { - return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x2UL)); + return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x2UL)); } static inline bool nrfx_usbd_errata_type_52840_eng_d(void) { - return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL == 0x3UL)); + return (nrfx_usbd_errata_type_52840() && (*(uint32_t *)0x10000134UL >= 0x3UL)); } /* Errata: USBD: EPDATA event is not always generated. */ static inline bool nrfx_usbd_errata_104(void) { - return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a()); + return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b())); } /* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. */ static inline bool nrfx_usbd_errata_154(void) { - return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a()); + return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b())); } /* Errata: ISO double buffering not functional. */ @@ -95,11 +95,7 @@ static inline bool nrfx_usbd_errata_171(void) /* Errata: USB cannot be enabled. */ static inline bool nrfx_usbd_errata_187(void) { - return (NRFX_USBD_ERRATA_ENABLE && - (nrfx_usbd_errata_type_52840_eng_b() || - nrfx_usbd_errata_type_52840_eng_c() || - nrfx_usbd_errata_type_52840_eng_d()) - ); + return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_b()); } /* Errata: USBD cannot receive tasks during DMA. */ @@ -111,7 +107,7 @@ static inline bool nrfx_usbd_errata_199(void) /* Errata: SIZE.EPOUT not writable. */ static inline bool nrfx_usbd_errata_200(void) { - return (NRFX_USBD_ERRATA_ENABLE && nrfx_usbd_errata_type_52840_eng_a()); + return (NRFX_USBD_ERRATA_ENABLE && (!nrfx_usbd_errata_type_52840_eng_b())); } #endif // NRFX_USBD_ERRATA_H__ diff --git a/drivers/src/nrfx_wdt.c b/drivers/src/nrfx_wdt.c index db7c786ac..feb9a3c33 100644 --- a/drivers/src/nrfx_wdt.c +++ b/drivers/src/nrfx_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/prs/nrfx_prs.c b/drivers/src/prs/nrfx_prs.c index c5e4ba5db..4eaf178cc 100644 --- a/drivers/src/prs/nrfx_prs.c +++ b/drivers/src/prs/nrfx_prs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/drivers/src/prs/nrfx_prs.h b/drivers/src/prs/nrfx_prs.h index aac0375f3..33003c8af 100644 --- a/drivers/src/prs/nrfx_prs.h +++ b/drivers/src/prs/nrfx_prs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -52,10 +52,19 @@ extern "C" { // SPI1, SPIS1, TWI1 #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 #elif defined(NRF52810_XXAA) - // TWIM0, TWIS0 + // TWIM0, TWIS0, TWI0 #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 - // SPIM0, SPIS0 + // SPIM0, SPIS0, SPI0 #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UARTE0, UART0 + #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0 +#elif defined(NRF52811_XXAA) + // TWIM0, TWIS0, TWI0, SPIM1, SPIS1, SPI1 + #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 + // SPIM0, SPIS0, SPI0 + #define NRFX_PRS_BOX_1_ADDR NRF_SPIM0 + // UART0, UARTE0 + #define NRFX_PRS_BOX_2_ADDR NRF_UART0 #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0 #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0 diff --git a/hal/nrf_acl.h b/hal/nrf_acl.h index 99043d483..3c2972484 100644 --- a/hal/nrf_acl.h +++ b/hal/nrf_acl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_adc.h b/hal/nrf_adc.h index 97a8cdb38..eb3e1a868 100644 --- a/hal/nrf_adc.h +++ b/hal/nrf_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_bprot.h b/hal/nrf_bprot.h new file mode 100644 index 000000000..c8d94300b --- /dev/null +++ b/hal/nrf_bprot.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_BPROT_H__ +#define NRF_BPROT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_bprot_hal BPROT HAL + * @{ + * @ingroup nrf_bprot + * @brief Hardware access layer for managing the Block Protection (BPROT) mechanism. + */ + +/** + * @brief Function for enabling protection for specified non-volatile memory blocks. + * + * Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB. + * Any attempt to write or erase a protected block will result in hard fault. + * The memory block protection can be disabled only by resetting the device. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] group_idx Non-volatile memory group containing memory blocks to protect. + * @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents + * one memory block in the specified group. + */ +__STATIC_INLINE void nrf_bprot_nvm_blocks_protection_enable(NRF_BPROT_Type * p_reg, + uint8_t group_idx, + uint32_t block_mask); + +/** + * @brief Function for setting the non-volatile memory (NVM) protection during debug. + * + * NVM protection is disabled by default while debugging. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if NVM protection during debug is to be enabled. + * False if otherwise. + */ +__STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg, + bool enable); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_bprot_nvm_blocks_protection_enable(NRF_BPROT_Type * p_reg, + uint8_t group_idx, + uint32_t block_mask) +{ + switch (group_idx) + { + case 0: + p_reg->CONFIG0 = block_mask; + break; + + case 1: + p_reg->CONFIG1 = block_mask; + break; + +#if defined(BPROT_CONFIG2_REGION64_Pos) + case 2: + p_reg->CONFIG2 = block_mask; + break; +#endif + +#if defined(BPROT_CONFIG3_REGION96_Pos) + case 3: + p_reg->CONFIG3 = block_mask; + break; +#endif + + default: + NRFX_ASSERT(false); + break; + } +} + +__STATIC_INLINE void nrf_bprot_nvm_protection_in_debug_set(NRF_BPROT_Type * p_reg, + bool enable) +{ + p_reg->DISABLEINDEBUG = + (enable ? 0 : BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_BPROT_H__ diff --git a/hal/nrf_ccm.h b/hal/nrf_ccm.h index 7546cb50d..0583ac796 100644 --- a/hal/nrf_ccm.h +++ b/hal/nrf_ccm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_clock.h b/hal/nrf_clock.h index 4443a3e90..a6941561f 100644 --- a/hal/nrf_clock.h +++ b/hal/nrf_clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_comp.h b/hal/nrf_comp.h index 766349132..f0725cf85 100644 --- a/hal/nrf_comp.h +++ b/hal/nrf_comp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_dppi.h b/hal/nrf_dppi.h index 9eae63e05..b1ee7da7e 100644 --- a/hal/nrf_dppi.h +++ b/hal/nrf_dppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_ecb.c b/hal/nrf_ecb.c index b83935e72..1a196057e 100644 --- a/hal/nrf_ecb.c +++ b/hal/nrf_ecb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_ecb.h b/hal/nrf_ecb.h index 25e7200ec..40064a99d 100644 --- a/hal/nrf_ecb.h +++ b/hal/nrf_ecb.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_egu.h b/hal/nrf_egu.h index dc7bc305e..5fb9ce677 100644 --- a/hal/nrf_egu.h +++ b/hal/nrf_egu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index ba4fa4096..7af4c548c 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -325,6 +325,15 @@ __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) */ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number); +/** + * @brief Function for reading the status of GPIO pin input buffer. + * + * @param pin_number Pin number to be read. + * + * @retval Input buffer configuration. + */ +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number); + /** * @brief Function for reading the pull configuration of a GPIO pin. * @@ -694,6 +703,13 @@ __STATIC_INLINE nrf_gpio_pin_dir_t nrf_gpio_pin_dir_get(uint32_t pin_number) GPIO_PIN_CNF_DIR_Msk) >> GPIO_PIN_CNF_DIR_Pos); } +__STATIC_INLINE nrf_gpio_pin_input_t nrf_gpio_pin_input_get(uint32_t pin_number) +{ + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); + + return (nrf_gpio_pin_input_t)((reg->PIN_CNF[pin_number] & + GPIO_PIN_CNF_INPUT_Msk) >> GPIO_PIN_CNF_INPUT_Pos); +} __STATIC_INLINE nrf_gpio_pin_pull_t nrf_gpio_pin_pull_get(uint32_t pin_number) { diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index e801d997e..346e9505a 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_i2s.h b/hal/nrf_i2s.h index 5d3ebf133..4e141ef74 100644 --- a/hal/nrf_i2s.h +++ b/hal/nrf_i2s.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_kmu.h b/hal/nrf_kmu.h index f54b9b1fa..3bfbcf415 100644 --- a/hal/nrf_kmu.h +++ b/hal/nrf_kmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_lpcomp.h b/hal/nrf_lpcomp.h index 50ee41fe3..d1d249cfe 100644 --- a/hal/nrf_lpcomp.h +++ b/hal/nrf_lpcomp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_mpu.h b/hal/nrf_mpu.h new file mode 100644 index 000000000..0c9b48e7e --- /dev/null +++ b/hal/nrf_mpu.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_MPU_H__ +#define NRF_MPU_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_mpu_hal MPU HAL + * @{ + * @ingroup nrf_mpu + * @brief Hardware access layer for managing the Memory Protection Unit (MPU) peripheral. + */ + +/** + * @brief Macro for getting MPU region configuration mask for the specified peripheral. + * + * @param[in] base_addr Peripheral base address. + * + * @return MPU configuration mask for the specified peripheral. + */ +#define NRF_MPU_PERIPHERAL_MASK_GET(base_addr) (1UL << NRFX_PERIPHERAL_ID_GET(base_addr)) + +/** + * @brief Function for setting the size of the RAM region 0. + * + * When memory protection is enabled, the Memory Protection Unit enforces + * runtime protection and readback protection of resources classified as region 0. + * See the product specification for more information. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] size Size of the RAM region 0, in bytes. Must be word-aligned. + */ +__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size); + +/** + * @brief Function for configuring specified peripherals in the memory region 0. + * + * When the memory protection is enabled, the Memory Protection Unit enforces + * runtime protection and readback protection of resources classified as region 0. + * See the product specification for more information. + * + * After reset, all peripherals are configured as *not* assigned to region 0. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] peripheral_mask Mask that specifies peripherals to be configured in the memory region 0. + * Compose this mask using @ref NRF_MPU_PERIPHERAL_MASK_GET macro. + */ +__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg, + uint32_t peripheral_mask); + +/** + * @brief Function for getting the bitmask that specifies peripherals configured in the memory region 0. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Bitmask representing peripherals configured in region 0. + */ +__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg); + +/** + * @brief Function for enabling protection for specified non-volatile memory blocks. + * + * Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB. + * Any attempt to write or erase a protected block will result in hard fault. + * The memory block protection can be disabled only by resetting the device. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] group_idx Non-volatile memory group containing memory blocks to protect. + * @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents + * one memory block in the specified group. + */ +__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg, + uint8_t group_idx, + uint32_t block_mask); + +/** + * @brief Function for setting the non-volatile memory (NVM) protection during debug. + * + * NVM protection during debug is disabled by default. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if NVM protection during debug is to be enabled. + * False if otherwise. + */ +__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg, + bool enable); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size) +{ + NRFX_ASSERT(nrfx_is_word_aligned((const void *)size)); + p_reg->RLENR0 = size; +} + +__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg, + uint32_t peripheral_mask) +{ + p_reg->PERR0 = peripheral_mask; +} + +__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg) +{ + return p_reg->PERR0; +} + +__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg, + uint8_t group_idx, + uint32_t block_mask) +{ + switch (group_idx) + { + case 0: + p_reg->PROTENSET0 = block_mask; + break; + + case 1: + p_reg->PROTENSET1 = block_mask; + break; + + default: + NRFX_ASSERT(false); + break; + } +} + +__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg, + bool enable) +{ + p_reg->DISABLEINDEBUG = + (enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_MPU_H__ diff --git a/hal/nrf_mwu.h b/hal/nrf_mwu.h new file mode 100644 index 000000000..6495468e4 --- /dev/null +++ b/hal/nrf_mwu.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_MWU_H__ +#define NRF_MWU_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_mwu_hal MWU HAL + * @{ + * @ingroup nrf_mwu + * @brief Hardware access layer for managing the Memory Watch Unit (MWU) peripheral. + */ + +/** @brief MWU events. */ +typedef enum +{ + NRF_MWU_EVENT_REGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[0].WA), ///< Write access to region 0 detected. + NRF_MWU_EVENT_REGION0_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[0].RA), ///< Read access to region 0 detected. + NRF_MWU_EVENT_REGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[1].WA), ///< Write access to region 1 detected. + NRF_MWU_EVENT_REGION1_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[1].RA), ///< Read access to region 1 detected. + NRF_MWU_EVENT_REGION2_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[2].WA), ///< Write access to region 2 detected. + NRF_MWU_EVENT_REGION2_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[2].RA), ///< Read access to region 2 detected. + NRF_MWU_EVENT_REGION3_WRITE = offsetof(NRF_MWU_Type, EVENTS_REGION[3].WA), ///< Write access to region 3 detected. + NRF_MWU_EVENT_REGION3_READ = offsetof(NRF_MWU_Type, EVENTS_REGION[3].RA), ///< Read access to region 3 detected. + NRF_MWU_EVENT_PREGION0_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].WA), ///< Write access to peripheral region 0 detected. + NRF_MWU_EVENT_PREGION0_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[0].RA), ///< Read access to peripheral region 0 detected. + NRF_MWU_EVENT_PREGION1_WRITE = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].WA), ///< Write access to peripheral region 1 detected. + NRF_MWU_EVENT_PREGION1_READ = offsetof(NRF_MWU_Type, EVENTS_PREGION[1].RA), ///< Read access to peripheral region 1 detected. +} nrf_mwu_event_t; + +/** @brief MWU interrupt masks. */ +typedef enum +{ + NRF_MWU_INT_REGION0_WRITE_MASK = MWU_INTEN_REGION0WA_Msk, ///< Interrupt on REGION[0].WA event. + NRF_MWU_INT_REGION0_READ_MASK = MWU_INTEN_REGION0RA_Msk, ///< Interrupt on REGION[0].RA event. + NRF_MWU_INT_REGION1_WRITE_MASK = MWU_INTEN_REGION1WA_Msk, ///< Interrupt on REGION[1].WA event. + NRF_MWU_INT_REGION1_READ_MASK = MWU_INTEN_REGION1RA_Msk, ///< Interrupt on REGION[1].RA event. + NRF_MWU_INT_REGION2_WRITE_MASK = MWU_INTEN_REGION2WA_Msk, ///< Interrupt on REGION[2].WA event. + NRF_MWU_INT_REGION2_READ_MASK = MWU_INTEN_REGION2RA_Msk, ///< Interrupt on REGION[2].RA event. + NRF_MWU_INT_REGION3_WRITE_MASK = MWU_INTEN_REGION3WA_Msk, ///< Interrupt on REGION[3].WA event. + NRF_MWU_INT_REGION3_READ_MASK = MWU_INTEN_REGION3RA_Msk, ///< Interrupt on REGION[3].RA event. + NRF_MWU_INT_PREGION0_WRITE_MASK = MWU_INTEN_PREGION0WA_Msk, ///< Interrupt on PREGION[0].WA event. + NRF_MWU_INT_PREGION0_READ_MASK = MWU_INTEN_PREGION0RA_Msk, ///< Interrupt on PREGION[0].RA event. + NRF_MWU_INT_PREGION1_WRITE_MASK = MWU_INTEN_PREGION1WA_Msk, ///< Interrupt on PREGION[1].WA event. + NRF_MWU_INT_PREGION1_READ_MASK = MWU_INTEN_PREGION1RA_Msk, ///< Interrupt on PREGION[1].RA event. +} nrf_mwu_int_mask_t; + +/** @brief MWU region watch masks. */ +typedef enum +{ + NRF_MWU_WATCH_REGION0_WRITE = MWU_REGIONEN_RGN0WA_Msk, ///< Region 0 write access watch mask + NRF_MWU_WATCH_REGION0_READ = MWU_REGIONEN_RGN0RA_Msk, ///< Region 0 read access watch mask + NRF_MWU_WATCH_REGION1_WRITE = MWU_REGIONEN_RGN1WA_Msk, ///< Region 1 write access watch mask + NRF_MWU_WATCH_REGION1_READ = MWU_REGIONEN_RGN1RA_Msk, ///< Region 1 read access watch mask + NRF_MWU_WATCH_REGION2_WRITE = MWU_REGIONEN_RGN2WA_Msk, ///< Region 2 write access watch mask + NRF_MWU_WATCH_REGION2_READ = MWU_REGIONEN_RGN2RA_Msk, ///< Region 2 read access watch mask + NRF_MWU_WATCH_REGION3_WRITE = MWU_REGIONEN_RGN3WA_Msk, ///< Region 3 write access watch mask + NRF_MWU_WATCH_REGION3_READ = MWU_REGIONEN_RGN3RA_Msk, ///< Region 3 read access watch mask + NRF_MWU_WATCH_PREGION0_WRITE = MWU_REGIONEN_PRGN0WA_Msk, ///< Peripheral region 0 write access watch mask + NRF_MWU_WATCH_PREGION0_READ = MWU_REGIONEN_PRGN0RA_Msk, ///< Peripheral region 0 read access watch mask + NRF_MWU_WATCH_PREGION1_WRITE = MWU_REGIONEN_PRGN1WA_Msk, ///< Peripheral region 1 write access watch mask + NRF_MWU_WATCH_PREGION1_READ = MWU_REGIONEN_PRGN1RA_Msk, ///< Peripheral region 1 read access watch mask +} nrf_mwu_region_watch_t; + +/** + * @brief Function for checking the state of a specific MWU event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mwu_event Event to check. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg, + nrf_mwu_event_t mwu_event); + +/** + * @brief Function for clearing a specific MWU event. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mwu_event Event to clear. + */ +__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg, + nrf_mwu_event_t mwu_event); + +/** + * @brief Function for getting the address of a specific MWU event register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mwu_event Requested event. + * + * @return Address of the specified event register. + */ +__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg, + nrf_mwu_event_t mwu_event); + +/** + * @brief Function for enabling specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a specific interrupt. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mwu_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg, + nrf_mwu_int_mask_t mwu_int); + +/** + * @brief Function for disabling specified interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for enabling specified non-maskable interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] int_mask Interrupts to enable. + */ +__STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a specific non-maskable interrupt. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mwu_int Interrupt to check. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg, + nrf_mwu_int_mask_t mwu_int); + +/** + * @brief Function for disabling specified non-maskable interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] int_mask Interrupts to disable. + */ +__STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask); + +/** + * @brief Function for setting address range of the specified user region. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] region_idx Region number to configure. + * @param[in] start_addr Memory address defining the beginning of the region. + * @param[in] end_addr Memory address defining the end of the region. + */ +__STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg, + uint8_t region_idx, + uint32_t start_addr, + uint32_t end_addr); + +/** + * @brief Function for enabling memory access watch mechanism. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] reg_watch_mask Mask that defines regions and access types to watch. + * Compose this mask from @ref nrf_mwu_region_watch_t values. + */ +__STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask); + +/** + * @brief Function for disabling memory access watch mechanism. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] reg_watch_mask Mask that defines regions and access types to stop watching. + * Compose this mask from @ref nrf_mwu_region_watch_t values. + */ +__STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask); + +/** + * @brief Function for getting memory access watch configuration mask. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Mask that defines regions and access types being watched. + */ +__STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg); + +/** + * @brief Function for configuring peripheral subregions for watching. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] per_reg_idx Peripheral region containing specified subregions. + * @param[in] subregion_mask Mask that defines subregions to include into the specified peripheral region. + */ +__STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask); + +/** + * @brief Function for getting the mask of the write access flags of peripheral subregions + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] per_reg_idx Peripheral region containing subregions to check. + * + * @return Mask specifying subregions that were write accessed. + */ +__STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg, + uint8_t per_reg_idx); + +/** + * @brief Function for clearing write access flags of peripheral subregions. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] per_reg_idx Peripheral region containing subregion accesses to clear. + * @param[in] subregion_mask Mask that defines subregion write accesses to clear. + */ +__STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask); + +/** + * @brief Function for getting the mask of the read access flags of peripheral subregions + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] per_reg_idx Peripheral region containing subregions to check. + * + * @return Mask specifying subregions that were read accessed. + */ +__STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg, + uint8_t per_reg_idx); + +/** + * @brief Function for clearing read access flags of peripheral subregions. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] per_reg_idx Peripheral region containing subregion accesses to clear. + * @param[in] subregion_mask Mask that defines subregion read accesses to clear. + */ +__STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrf_mwu_event_check(NRF_MWU_Type const * p_reg, + nrf_mwu_event_t mwu_event) +{ + return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event); +} + +__STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg, + nrf_mwu_event_t mwu_event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event)) = 0; +#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)mwu_event)); + (void)dummy; +#endif +} + +__STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg, + nrf_mwu_event_t mwu_event) +{ + return (uint32_t)((uint8_t *)p_reg + (uint32_t)mwu_event); +} + +__STATIC_INLINE void nrf_mwu_int_enable(NRF_MWU_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENSET = int_mask; +} + +__STATIC_INLINE bool nrf_mwu_int_enable_check(NRF_MWU_Type const * p_reg, + nrf_mwu_int_mask_t mwu_int) +{ + return (bool)(p_reg->INTENSET & mwu_int); +} + +__STATIC_INLINE void nrf_mwu_int_disable(NRF_MWU_Type * p_reg, uint32_t int_mask) +{ + p_reg->INTENCLR = int_mask; +} + +__STATIC_INLINE void nrf_mwu_nmi_enable(NRF_MWU_Type * p_reg, uint32_t int_mask) +{ + p_reg->NMIENSET = int_mask; +} + +__STATIC_INLINE bool nrf_mwu_nmi_enable_check(NRF_MWU_Type const * p_reg, + nrf_mwu_int_mask_t mwu_int) +{ + return (bool)(p_reg->NMIENSET & mwu_int); +} + +__STATIC_INLINE void nrf_mwu_nmi_disable(NRF_MWU_Type * p_reg, uint32_t int_mask) +{ + p_reg->NMIENCLR = int_mask; +} + +__STATIC_INLINE void nrf_mwu_user_region_range_set(NRF_MWU_Type * p_reg, + uint8_t region_idx, + uint32_t start_addr, + uint32_t end_addr) +{ + NRFX_ASSERT(region_idx < NRFX_ARRAY_SIZE(NRF_MWU->REGION)); + NRFX_ASSERT(end_addr >= start_addr); + + p_reg->REGION[region_idx].START = start_addr; + p_reg->REGION[region_idx].END = end_addr; +} + +__STATIC_INLINE void nrf_mwu_region_watch_enable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask) +{ + p_reg->REGIONENSET = reg_watch_mask; +} + +__STATIC_INLINE void nrf_mwu_region_watch_disable(NRF_MWU_Type * p_reg, uint32_t reg_watch_mask) +{ + p_reg->REGIONENCLR = reg_watch_mask; +} + +__STATIC_INLINE uint32_t nrf_mwu_region_watch_get(NRF_MWU_Type const * p_reg) +{ + return p_reg->REGIONENSET; +} + +__STATIC_INLINE void nrf_mwu_subregions_configure(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask) +{ + NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION)); + + p_reg->PREGION[per_reg_idx].SUBS = subregion_mask; +} + +__STATIC_INLINE uint32_t nrf_mwu_subregions_write_accesses_get(NRF_MWU_Type const * p_reg, + uint8_t per_reg_idx) +{ + NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION)); + + return p_reg->PERREGION[per_reg_idx].SUBSTATWA; +} + +__STATIC_INLINE void nrf_mwu_subregions_write_accesses_clear(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask) +{ + NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION)); + + p_reg->PERREGION[per_reg_idx].SUBSTATWA = subregion_mask; +} + +__STATIC_INLINE uint32_t nrf_mwu_subregions_read_accesses_get(NRF_MWU_Type const * p_reg, + uint8_t per_reg_idx) +{ + NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION)); + + return p_reg->PERREGION[per_reg_idx].SUBSTATRA; +} + +__STATIC_INLINE void nrf_mwu_subregions_read_accesses_clear(NRF_MWU_Type * p_reg, + uint8_t per_reg_idx, + uint32_t subregion_mask) +{ + NRFX_ASSERT(per_reg_idx < NRFX_ARRAY_SIZE(NRF_MWU->PREGION)); + + p_reg->PERREGION[per_reg_idx].SUBSTATRA = subregion_mask; +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_MWU_H__ diff --git a/hal/nrf_nfct.h b/hal/nrf_nfct.h index e07bc3704..e6f44db91 100644 --- a/hal/nrf_nfct.h +++ b/hal/nrf_nfct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_nvmc.c b/hal/nrf_nvmc.c index be4bde459..93cdaaf4e 100644 --- a/hal/nrf_nvmc.c +++ b/hal/nrf_nvmc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_nvmc.h b/hal/nrf_nvmc.h index 556672a2d..506f35850 100644 --- a/hal/nrf_nvmc.h +++ b/hal/nrf_nvmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_pdm.h b/hal/nrf_pdm.h index 89b3d977c..3e726c06e 100644 --- a/hal/nrf_pdm.h +++ b/hal/nrf_pdm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_power.h b/hal/nrf_power.h index 268323c24..9e4d16253 100644 --- a/hal/nrf_power.h +++ b/hal/nrf_power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_ppi.h b/hal/nrf_ppi.h index 40f912436..c87c7edac 100644 --- a/hal/nrf_ppi.h +++ b/hal/nrf_ppi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index 19e7bf5e2..a85216404 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_qdec.h b/hal/nrf_qdec.h index d7adde57b..bd95f18db 100644 --- a/hal/nrf_qdec.h +++ b/hal/nrf_qdec.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -399,9 +399,23 @@ __STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void) __STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled) { +#if defined(QDEC_PSEL_A_CONNECT_Pos) + NRF_QDEC->PSEL.A = psela; +#else NRF_QDEC->PSELA = psela; +#endif + +#if defined(QDEC_PSEL_B_CONNECT_Pos) + NRF_QDEC->PSEL.B = pselb; +#else NRF_QDEC->PSELB = pselb; +#endif + +#if defined(QDEC_PSEL_LED_CONNECT_Pos) + NRF_QDEC->PSEL.LED = pselled; +#else NRF_QDEC->PSELLED = pselled; +#endif } __STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task) diff --git a/hal/nrf_qspi.h b/hal/nrf_qspi.h index a53c2142a..c7982bd8b 100644 --- a/hal/nrf_qspi.h +++ b/hal/nrf_qspi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_radio.h b/hal/nrf_radio.h index 4861d047b..d42a71f4c 100644 --- a/hal/nrf_radio.h +++ b/hal/nrf_radio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_regulators.h b/hal/nrf_regulators.h index f49a77be7..6af58bfc5 100644 --- a/hal/nrf_regulators.h +++ b/hal/nrf_regulators.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_rng.h b/hal/nrf_rng.h index 21cee2db6..07b285812 100644 --- a/hal/nrf_rng.h +++ b/hal/nrf_rng.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_rtc.h b/hal/nrf_rtc.h index 31a417f16..079898c67 100644 --- a/hal/nrf_rtc.h +++ b/hal/nrf_rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index c77e42891..c63bb211e 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -384,7 +384,7 @@ __STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf * @param[in] pselp Positive input. * @param[in] pseln Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode. */ -__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, +__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, nrf_saadc_input_t pselp, nrf_saadc_input_t pseln); @@ -394,7 +394,7 @@ __STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel, * @param[in] channel Channel number. * @param[in] pselp Positive input. */ -__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel, +__STATIC_INLINE void nrf_saadc_channel_pos_input_set(uint8_t channel, nrf_saadc_input_t pselp); /** @@ -522,6 +522,27 @@ __STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample) */ __STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void); +/** + * @brief Function for enabling the continuous sampling. + * + * This function configures the SAADC internal timer to automatically take new samples at a fixed + * sample rate. Trigger the START task to begin continuous sampling. To stop the sampling, trigger + * the STOP task. + * + * @note The internal timer can only be used when a single input channel is enabled. + * + * @param[in] cc Capture and compare value. Sample rate is 16 MHz/cc. Valid CC range is + * from 80 to 2047. + */ +__STATIC_INLINE void nrf_saadc_continuous_mode_enable(uint16_t cc); + +/** + * @brief Function for disabling the continuous sampling. + * + * New samples can still be acquired by manually triggering the SAMPLE task or by PPI. + */ +__STATIC_INLINE void nrf_saadc_continuous_mode_disable(void); + /** * @brief Function for initializing the SAADC channel. * @@ -729,6 +750,18 @@ __STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void) return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE; } +__STATIC_INLINE void nrf_saadc_continuous_mode_enable(uint16_t cc) +{ + NRFX_ASSERT((cc >= 80) && (cc <= 2047)); + NRF_SAADC->SAMPLERATE = (SAADC_SAMPLERATE_MODE_Timers << SAADC_SAMPLERATE_MODE_Pos) + | ((uint32_t)cc << SAADC_SAMPLERATE_CC_Pos); +} + +__STATIC_INLINE void nrf_saadc_continuous_mode_disable(void) +{ + NRF_SAADC->SAMPLERATE = SAADC_SAMPLERATE_MODE_Task << SAADC_SAMPLERATE_MODE_Pos; +} + __STATIC_INLINE void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config) { diff --git a/hal/nrf_spi.h b/hal/nrf_spi.h index d942d2dd7..8366deb85 100644 --- a/hal/nrf_spi.h +++ b/hal/nrf_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -296,9 +296,23 @@ __STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg, uint32_t mosi_pin, uint32_t miso_pin) { +#if defined(SPI_PSEL_SCK_CONNECT_Pos) + p_reg->PSEL.SCK = sck_pin; +#else p_reg->PSELSCK = sck_pin; +#endif + +#if defined(SPI_PSEL_MOSI_CONNECT_Pos) + p_reg->PSEL.MOSI = mosi_pin; +#else p_reg->PSELMOSI = mosi_pin; +#endif + +#if defined(SPI_PSEL_MISO_CONNECT_Pos) + p_reg->PSEL.MISO = miso_pin; +#else p_reg->PSELMISO = miso_pin; +#endif } __STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data) diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index 9f76eb5df..d49cb941b 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_spis.h b/hal/nrf_spis.h index ab8daa1ce..5896bb263 100644 --- a/hal/nrf_spis.h +++ b/hal/nrf_spis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_spu.h b/hal/nrf_spu.h index cd19be65c..e188e076d 100644 --- a/hal/nrf_spu.h +++ b/hal/nrf_spu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_systick.h b/hal/nrf_systick.h index 3058089ff..d99e6145e 100644 --- a/hal/nrf_systick.h +++ b/hal/nrf_systick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_temp.h b/hal/nrf_temp.h index b08b42333..c39c2e0b3 100644 --- a/hal/nrf_temp.h +++ b/hal/nrf_temp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index 805f86f08..7f2e7bc09 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_twi.h b/hal/nrf_twi.h index 2aa275e8c..d668e3f9c 100644 --- a/hal/nrf_twi.h +++ b/hal/nrf_twi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -186,7 +186,7 @@ __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, * @param[in] shorts_mask Shortcuts to enable. */ __STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); + uint32_t shorts_mask); /** * @brief Function for disabling specified shortcuts. @@ -195,7 +195,7 @@ __STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, * @param[in] shorts_mask Shortcuts to disable. */ __STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); + uint32_t shorts_mask); /** * @brief Function for enabling specified interrupts. @@ -204,7 +204,7 @@ __STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, * @param[in] int_mask Interrupts to enable. */ __STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, - uint32_t int_mask); + uint32_t int_mask); /** * @brief Function for disabling specified interrupts. @@ -213,7 +213,7 @@ __STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, * @param[in] int_mask Interrupts to disable. */ __STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, - uint32_t int_mask); + uint32_t int_mask); /** * @brief Function for retrieving the state of a given interrupt. @@ -224,7 +224,7 @@ __STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, * @retval true If the interrupt is enabled. * @retval false If the interrupt is not enabled. */ -__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, nrf_twi_int_mask_t int_mask); /** @@ -244,14 +244,31 @@ __STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg); /** * @brief Function for configuring TWI pins. * - * * @param[in] p_reg Pointer to the peripheral registers structure. * @param[in] scl_pin SCL pin number. * @param[in] sda_pin SDA pin number. */ __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin); + uint32_t scl_pin, + uint32_t sda_pin); + +/** + * @brief Function for retrieving the SCL pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure + * + * @retval pin SCL pin number. + */ +__STATIC_INLINE uint32_t nrf_twi_scl_pin_get(NRF_TWI_Type * p_reg); + +/** + * @brief Function for retrieving the SDA pin number. + * + * @param[in] p_reg Pointer to the peripheral registers structure + * + * @retval pin SDA pin number. + */ +__STATIC_INLINE uint32_t nrf_twi_sda_pin_get(NRF_TWI_Type * p_reg); /** * @brief Function for setting the TWI master clock frequency. @@ -259,7 +276,7 @@ __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, * @param[in] p_reg Pointer to the peripheral registers structure. * @param[in] frequency TWI frequency. */ -__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, nrf_twi_frequency_t frequency); /** @@ -299,7 +316,7 @@ __STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg); __STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data); __STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, - uint32_t shorts_mask); + uint32_t shorts_mask); #ifndef SUPPRESS_INLINE_IMPLEMENTATION @@ -338,30 +355,30 @@ __STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type * p_reg, } __STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) + uint32_t shorts_mask) { p_reg->SHORTS |= shorts_mask; } __STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) + uint32_t shorts_mask) { p_reg->SHORTS &= ~(shorts_mask); } __STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg, - uint32_t int_mask) + uint32_t int_mask) { p_reg->INTENSET = int_mask; } __STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg, - uint32_t int_mask) + uint32_t int_mask) { p_reg->INTENCLR = int_mask; } -__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, +__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg, nrf_twi_int_mask_t int_mask) { return (bool)(p_reg->INTENSET & int_mask); @@ -378,8 +395,8 @@ __STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg) } __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, - uint32_t scl_pin, - uint32_t sda_pin) + uint32_t scl_pin, + uint32_t sda_pin) { #if defined(TWI_PSEL_SCL_CONNECT_Pos) p_reg->PSEL.SCL = scl_pin; @@ -394,7 +411,25 @@ __STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg, #endif } -__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, +__STATIC_INLINE uint32_t nrf_twi_scl_pin_get(NRF_TWI_Type * p_reg) +{ +#if defined(TWI_PSEL_SCL_CONNECT_Pos) + return p_reg->PSEL.SCL; +#else + return p_reg->PSELSCL; +#endif +} + +__STATIC_INLINE uint32_t nrf_twi_sda_pin_get(NRF_TWI_Type * p_reg) +{ +#if defined(TWI_PSEL_SDA_CONNECT_Pos) + return p_reg->PSEL.SDA; +#else + return p_reg->PSELSDA; +#endif +} + +__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg, nrf_twi_frequency_t frequency) { p_reg->FREQUENCY = frequency; @@ -426,7 +461,7 @@ __STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data) } __STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg, - uint32_t shorts_mask) + uint32_t shorts_mask) { p_reg->SHORTS = shorts_mask; } diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index f06db8e0a..ffe18f0b2 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_twis.h b/hal/nrf_twis.h index 0ab947a11..1b4701446 100644 --- a/hal/nrf_twis.h +++ b/hal/nrf_twis.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_uart.h b/hal/nrf_uart.h index cc00c745a..cd894eaf7 100644 --- a/hal/nrf_uart.h +++ b/hal/nrf_uart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_uarte.h b/hal/nrf_uarte.h index 317a668c1..b1e2feb1d 100644 --- a/hal/nrf_uarte.h +++ b/hal/nrf_uarte.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_usbd.h b/hal/nrf_usbd.h index 681367f60..1f87cc78c 100644 --- a/hal/nrf_usbd.h +++ b/hal/nrf_usbd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_vmc.h b/hal/nrf_vmc.h index b1c6b8880..957baa44d 100644 --- a/hal/nrf_vmc.h +++ b/hal/nrf_vmc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/hal/nrf_wdt.h b/hal/nrf_wdt.h index 3f4747317..4f1dfcc57 100644 --- a/hal/nrf_wdt.h +++ b/hal/nrf_wdt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/mdk/arm_startup_nrf52810.s b/mdk/arm_startup_nrf52810.s index a41de458c..7f7545961 100644 --- a/mdk/arm_startup_nrf52810.s +++ b/mdk/arm_startup_nrf52810.s @@ -86,9 +86,9 @@ __Vectors DCD __initial_sp ; Top of Stack ; External Interrupts DCD POWER_CLOCK_IRQHandler DCD RADIO_IRQHandler - DCD UARTE0_IRQHandler - DCD TWIM0_TWIS0_IRQHandler - DCD SPIM0_SPIS0_IRQHandler + DCD UARTE0_UART0_IRQHandler + DCD TWIM0_TWIS0_TWI0_IRQHandler + DCD SPIM0_SPIS0_SPI0_IRQHandler DCD 0 ; Reserved DCD GPIOTE_IRQHandler DCD SAADC_IRQHandler @@ -266,9 +266,9 @@ Default_Handler PROC EXPORT POWER_CLOCK_IRQHandler [WEAK] EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_IRQHandler [WEAK] - EXPORT TWIM0_TWIS0_IRQHandler [WEAK] - EXPORT SPIM0_SPIS0_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler [WEAK] + EXPORT TWIM0_TWIS0_TWI0_IRQHandler [WEAK] + EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK] EXPORT GPIOTE_IRQHandler [WEAK] EXPORT SAADC_IRQHandler [WEAK] EXPORT TIMER0_IRQHandler [WEAK] @@ -293,9 +293,9 @@ Default_Handler PROC EXPORT PDM_IRQHandler [WEAK] POWER_CLOCK_IRQHandler RADIO_IRQHandler -UARTE0_IRQHandler -TWIM0_TWIS0_IRQHandler -SPIM0_SPIS0_IRQHandler +UARTE0_UART0_IRQHandler +TWIM0_TWIS0_TWI0_IRQHandler +SPIM0_SPIS0_SPI0_IRQHandler GPIOTE_IRQHandler SAADC_IRQHandler TIMER0_IRQHandler diff --git a/mdk/arm_startup_nrf52811.s b/mdk/arm_startup_nrf52811.s new file mode 100644 index 000000000..d2baa9cb0 --- /dev/null +++ b/mdk/arm_startup_nrf52811.s @@ -0,0 +1,351 @@ +; Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + + IF :DEF: __STARTUP_CONFIG +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE + ELIF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 2048 + ENDIF + + IF :DEF: __STARTUP_CONFIG +Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT + ELSE +Stack_Align EQU 3 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align +Stack_Mem SPACE Stack_Size +__initial_sp + + IF :DEF: __STARTUP_CONFIG +Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE + ELIF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 2048 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler + DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + DCD SPIM0_SPIS0_SPI0_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE_IRQHandler + DCD SAADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler + DCD RTC1_IRQHandler + DCD QDEC_IRQHandler + DCD COMP_IRQHandler + DCD SWI0_EGU0_IRQHandler + DCD SWI1_EGU1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PWM0_IRQHandler + DCD PDM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler [WEAK] + EXPORT TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler [WEAK] + EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK] + EXPORT GPIOTE_IRQHandler [WEAK] + EXPORT SAADC_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC1_IRQHandler [WEAK] + EXPORT QDEC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT SWI0_EGU0_IRQHandler [WEAK] + EXPORT SWI1_EGU1_IRQHandler [WEAK] + EXPORT SWI2_IRQHandler [WEAK] + EXPORT SWI3_IRQHandler [WEAK] + EXPORT SWI4_IRQHandler [WEAK] + EXPORT SWI5_IRQHandler [WEAK] + EXPORT PWM0_IRQHandler [WEAK] + EXPORT PDM_IRQHandler [WEAK] +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler +TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +SPIM0_SPIS0_SPI0_IRQHandler +GPIOTE_IRQHandler +SAADC_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +RTC0_IRQHandler +TEMP_IRQHandler +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler +RTC1_IRQHandler +QDEC_IRQHandler +COMP_IRQHandler +SWI0_EGU0_IRQHandler +SWI1_EGU1_IRQHandler +SWI2_IRQHandler +SWI3_IRQHandler +SWI4_IRQHandler +SWI5_IRQHandler +PWM0_IRQHandler +PDM_IRQHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/mdk/gcc_startup_nrf52810.S b/mdk/gcc_startup_nrf52810.S index 1c782f4c8..ab01718a8 100644 --- a/mdk/gcc_startup_nrf52810.S +++ b/mdk/gcc_startup_nrf52810.S @@ -92,9 +92,9 @@ __isr_vector: /* External Interrupts */ .long POWER_CLOCK_IRQHandler .long RADIO_IRQHandler - .long UARTE0_IRQHandler - .long TWIM0_TWIS0_IRQHandler - .long SPIM0_SPIS0_IRQHandler + .long UARTE0_UART0_IRQHandler + .long TWIM0_TWIS0_TWI0_IRQHandler + .long SPIM0_SPIS0_SPI0_IRQHandler .long 0 /*Reserved */ .long GPIOTE_IRQHandler .long SAADC_IRQHandler @@ -365,9 +365,9 @@ Default_Handler: IRQ POWER_CLOCK_IRQHandler IRQ RADIO_IRQHandler - IRQ UARTE0_IRQHandler - IRQ TWIM0_TWIS0_IRQHandler - IRQ SPIM0_SPIS0_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ TWIM0_TWIS0_TWI0_IRQHandler + IRQ SPIM0_SPIS0_SPI0_IRQHandler IRQ GPIOTE_IRQHandler IRQ SAADC_IRQHandler IRQ TIMER0_IRQHandler diff --git a/mdk/gcc_startup_nrf52811.S b/mdk/gcc_startup_nrf52811.S new file mode 100644 index 000000000..0a1a1e40a --- /dev/null +++ b/mdk/gcc_startup_nrf52811.S @@ -0,0 +1,394 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + + .syntax unified + .arch armv7e-m + +#ifdef __STARTUP_CONFIG +#include "startup_config.h" +#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT +#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 +#endif +#endif + + .section .stack +#if defined(__STARTUP_CONFIG) + .align __STARTUP_CONFIG_STACK_ALIGNEMENT + .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE +#elif defined(__STACK_SIZE) + .align 3 + .equ Stack_Size, __STACK_SIZE +#else + .align 3 + .equ Stack_Size, 2048 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#if defined(__STARTUP_CONFIG) + .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE +#elif defined(__HEAP_SIZE) + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 2048 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long MemoryManagement_Handler + .long BusFault_Handler + .long UsageFault_Handler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long SVC_Handler + .long DebugMon_Handler + .long 0 /*Reserved */ + .long PendSV_Handler + .long SysTick_Handler + + /* External Interrupts */ + .long POWER_CLOCK_IRQHandler + .long RADIO_IRQHandler + .long UARTE0_UART0_IRQHandler + .long TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + .long SPIM0_SPIS0_SPI0_IRQHandler + .long 0 /*Reserved */ + .long GPIOTE_IRQHandler + .long SAADC_IRQHandler + .long TIMER0_IRQHandler + .long TIMER1_IRQHandler + .long TIMER2_IRQHandler + .long RTC0_IRQHandler + .long TEMP_IRQHandler + .long RNG_IRQHandler + .long ECB_IRQHandler + .long CCM_AAR_IRQHandler + .long WDT_IRQHandler + .long RTC1_IRQHandler + .long QDEC_IRQHandler + .long COMP_IRQHandler + .long SWI0_EGU0_IRQHandler + .long SWI1_EGU1_IRQHandler + .long SWI2_IRQHandler + .long SWI3_IRQHandler + .long SWI4_IRQHandler + .long SWI5_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long PWM0_IRQHandler + .long PDM_IRQHandler + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + + .size __isr_vector, . - __isr_vector + +/* Reset Handler */ + + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + + +/* Loop to copy data from read only memory to RAM. + * The ranges of copy from/to are specified by following symbols: + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to. + * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__bss_start__ + + subs r3, r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: + +/* This part of work usually is done in C library startup code. Otherwise, + * define __STARTUP_CLEAR_BSS to enable it in this startup. This section + * clears the RAM where BSS data is located. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * All addresses must be aligned to 4 bytes boundary. + */ +#ifdef __STARTUP_CLEAR_BSS + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, r2, #4 + str r0, [r1, r2] + bgt .L_loop3 + +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS */ + +/* Execute SystemInit function. */ + bl SystemInit + +/* Call _start function provided by libraries. + * If those libraries are not accessible, define __START as your entry point. + */ +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler,.-Reset_Handler + + .section ".text" + + +/* Dummy Exception Handlers (infinite loops which can be modified) */ + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + + .weak MemoryManagement_Handler + .type MemoryManagement_Handler, %function +MemoryManagement_Handler: + b . + .size MemoryManagement_Handler, . - MemoryManagement_Handler + + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + +/* IRQ Handlers */ + + .globl Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm + + IRQ POWER_CLOCK_IRQHandler + IRQ RADIO_IRQHandler + IRQ UARTE0_UART0_IRQHandler + IRQ TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + IRQ SPIM0_SPIS0_SPI0_IRQHandler + IRQ GPIOTE_IRQHandler + IRQ SAADC_IRQHandler + IRQ TIMER0_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ RTC0_IRQHandler + IRQ TEMP_IRQHandler + IRQ RNG_IRQHandler + IRQ ECB_IRQHandler + IRQ CCM_AAR_IRQHandler + IRQ WDT_IRQHandler + IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler + IRQ COMP_IRQHandler + IRQ SWI0_EGU0_IRQHandler + IRQ SWI1_EGU1_IRQHandler + IRQ SWI2_IRQHandler + IRQ SWI3_IRQHandler + IRQ SWI4_IRQHandler + IRQ SWI5_IRQHandler + IRQ PWM0_IRQHandler + IRQ PDM_IRQHandler + + .end diff --git a/mdk/iar_startup_nrf52810.s b/mdk/iar_startup_nrf52810.s index e1342f9b5..e22585821 100644 --- a/mdk/iar_startup_nrf52810.s +++ b/mdk/iar_startup_nrf52810.s @@ -87,9 +87,9 @@ __vector_table ; External Interrupts DCD POWER_CLOCK_IRQHandler DCD RADIO_IRQHandler - DCD UARTE0_IRQHandler - DCD TWIM0_TWIS0_IRQHandler - DCD SPIM0_SPIS0_IRQHandler + DCD UARTE0_UART0_IRQHandler + DCD TWIM0_TWIS0_TWI0_IRQHandler + DCD SPIM0_SPIS0_SPI0_IRQHandler DCD 0 ; Reserved DCD GPIOTE_IRQHandler DCD SAADC_IRQHandler @@ -276,19 +276,19 @@ POWER_CLOCK_IRQHandler RADIO_IRQHandler B . - PUBWEAK UARTE0_IRQHandler + PUBWEAK UARTE0_UART0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -UARTE0_IRQHandler +UARTE0_UART0_IRQHandler B . - PUBWEAK TWIM0_TWIS0_IRQHandler + PUBWEAK TWIM0_TWIS0_TWI0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -TWIM0_TWIS0_IRQHandler +TWIM0_TWIS0_TWI0_IRQHandler B . - PUBWEAK SPIM0_SPIS0_IRQHandler + PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM0_SPIS0_IRQHandler +SPIM0_SPIS0_SPI0_IRQHandler B . PUBWEAK GPIOTE_IRQHandler diff --git a/mdk/iar_startup_nrf52811.s b/mdk/iar_startup_nrf52811.s new file mode 100644 index 000000000..c44794955 --- /dev/null +++ b/mdk/iar_startup_nrf52811.s @@ -0,0 +1,406 @@ +; Copyright (c) 2009-2018 ARM Limited. All rights reserved. +; +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the License); you may +; not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an AS IS BASIS, WITHOUT +; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; +; NOTICE: This file has been modified by Nordic Semiconductor ASA. + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + MODULE ?cstartup + +#if defined(__STARTUP_CONFIG) + + #include "startup_config.h" + + #ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT + #define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 + #endif + + SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT) + DS8 __STARTUP_CONFIG_STACK_SIZE + + SECTION HEAP:DATA:NOROOT(3) + DS8 __STARTUP_CONFIG_HEAP_SIZE + +#else + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + +#endif + + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler + DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + DCD SPIM0_SPIS0_SPI0_IRQHandler + DCD 0 ; Reserved + DCD GPIOTE_IRQHandler + DCD SAADC_IRQHandler + DCD TIMER0_IRQHandler + DCD TIMER1_IRQHandler + DCD TIMER2_IRQHandler + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler + DCD RTC1_IRQHandler + DCD QDEC_IRQHandler + DCD COMP_IRQHandler + DCD SWI0_EGU0_IRQHandler + DCD SWI1_EGU1_IRQHandler + DCD SWI2_IRQHandler + DCD SWI3_IRQHandler + DCD SWI4_IRQHandler + DCD SWI5_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PWM0_IRQHandler + DCD PDM_IRQHandler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RADIO_IRQHandler + B . + + PUBWEAK UARTE0_UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTE0_UART0_IRQHandler + B . + + PUBWEAK TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + B . + + PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPIM0_SPIS0_SPI0_IRQHandler + B . + + PUBWEAK GPIOTE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOTE_IRQHandler + B . + + PUBWEAK SAADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAADC_IRQHandler + B . + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B . + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B . + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TEMP_IRQHandler + B . + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B . + + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ECB_IRQHandler + B . + + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CCM_AAR_IRQHandler + B . + + PUBWEAK WDT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_IRQHandler + B . + + PUBWEAK RTC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC1_IRQHandler + B . + + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_IRQHandler + B . + + PUBWEAK SWI0_EGU0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI0_EGU0_IRQHandler + B . + + PUBWEAK SWI1_EGU1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI1_EGU1_IRQHandler + B . + + PUBWEAK SWI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI2_IRQHandler + B . + + PUBWEAK SWI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI3_IRQHandler + B . + + PUBWEAK SWI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI4_IRQHandler + B . + + PUBWEAK SWI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SWI5_IRQHandler + B . + + PUBWEAK PWM0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_IRQHandler + B . + + PUBWEAK PDM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PDM_IRQHandler + B . + + END + + diff --git a/mdk/nrf.h b/mdk/nrf.h index cfef670f4..8649d0bfe 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -35,7 +35,7 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 21 +#define MDK_MINOR_VERSION 23 #define MDK_MICRO_VERSION 1 /* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ @@ -46,7 +46,7 @@ POSSIBILITY OF SUCH DAMAGE. #endif /* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ -#if defined (NRF52810_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) +#if defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) #ifndef NRF52_SERIES #define NRF52_SERIES #endif @@ -78,6 +78,12 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf52810_bitfields.h" #include "nrf51_to_nrf52810.h" #include "nrf52_to_nrf52810.h" + #elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) #include "nrf52.h" #include "nrf52_bitfields.h" @@ -95,7 +101,7 @@ POSSIBILITY OF SUCH DAMAGE. #else #error "Device must be defined. See nrf.h." - #endif /* NRF51, NRF52810_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA, NRF9160_XXAA */ + #endif /* NRF51, NRF52810_XXAA, NRF52811_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52840_XXAA, NRF9160_XXAA */ #include "compiler_abstraction.h" diff --git a/mdk/nrf51.h b/mdk/nrf51.h index e77541d52..903423952 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -30,10 +30,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 03. December 2018 - * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 * from File 'nrf51.svd', - * last modified on Monday, 03.12.2018 10:18:20 + * last modified on Thursday, 17.01.2019 16:25:34 */ diff --git a/mdk/nrf51_to_nrf52.h b/mdk/nrf51_to_nrf52.h index 9cdae0c7c..1e13e6671 100644 --- a/mdk/nrf51_to_nrf52.h +++ b/mdk/nrf51_to_nrf52.h @@ -43,908 +43,2309 @@ POSSIBILITY OF SUCH DAMAGE. /* IRQ */ /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ -#define UART0_IRQHandler UARTE0_UART0_IRQHandler -#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define ADC_IRQHandler SAADC_IRQHandler -#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler -#define SWI0_IRQHandler SWI0_EGU0_IRQHandler -#define SWI1_IRQHandler SWI1_EGU1_IRQHandler -#define SWI2_IRQHandler SWI2_EGU2_IRQHandler -#define SWI3_IRQHandler SWI3_EGU3_IRQHandler -#define SWI4_IRQHandler SWI4_EGU4_IRQHandler -#define SWI5_IRQHandler SWI5_EGU5_IRQHandler - -#define UART0_IRQn UARTE0_UART0_IRQn -#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#define ADC_IRQn SAADC_IRQn -#define LPCOMP_IRQn COMP_LPCOMP_IRQn -#define SWI0_IRQn SWI0_EGU0_IRQn -#define SWI1_IRQn SWI1_EGU1_IRQn -#define SWI2_IRQn SWI2_EGU2_IRQn -#define SWI3_IRQn SWI3_EGU3_IRQn -#define SWI4_IRQn SWI4_EGU4_IRQn -#define SWI5_IRQn SWI5_EGU5_IRQn +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif /* UICR */ /* Register RBPCONF was renamed to APPROTECT. */ -#define RBPCONF APPROTECT - -#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos -#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk -#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled -#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled - +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif /* GPIO */ /* GPIO port was renamed to P0. */ -#define NRF_GPIO NRF_P0 -#define NRF_GPIO_BASE NRF_P0_BASE - +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif /* QDEC */ /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ -#define PSELLED PSEL.LED -#define PSELA PSEL.A -#define PSELB PSEL.B +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif /* SPIS */ /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ -#define PSELSCK PSEL.SCK -#define PSELMISO PSEL.MISO -#define PSELMOSI PSEL.MOSI -#define PSELCSN PSEL.CSN +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ -#define RXDPTR RXD.PTR -#define MAXRX RXD.MAXCNT -#define AMOUNTRX RXD.AMOUNT - -#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ -#define TXDPTR TXD.PTR -#define MAXTX TXD.MAXCNT -#define AMOUNTTX TXD.AMOUNT - -#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk - +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif /* MPU */ /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ -#define NRF_MPU NRF_BPROT +#ifndef NRF_MPU + #define NRF_MPU NRF_BPROT +#endif /* Register DISABLEINDEBUG macros were affected. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#endif +#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled + #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled +#endif /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ -#define PROTENSET0 CONFIG0 -#define PROTENSET1 CONFIG1 - -#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos -#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk -#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled -#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled -#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled - -#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos -#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk -#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled -#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled -#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled - -#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos -#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk -#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled -#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled -#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled - -#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos -#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk -#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled -#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled -#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled - -#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos -#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk -#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled -#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled -#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled - -#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos -#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk -#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled -#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled -#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled - -#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos -#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk -#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled -#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled -#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled - -#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos -#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk -#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled -#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled -#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled - -#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos -#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk -#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled -#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled -#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled - -#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos -#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk -#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled -#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled -#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled - -#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos -#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk -#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled -#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled -#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled - -#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos -#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk -#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled -#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled -#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled - -#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos -#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk -#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled -#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled -#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled - -#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos -#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk -#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled -#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled -#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled - -#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos -#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk -#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled -#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled -#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled - -#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos -#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk -#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled -#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled -#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled - -#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos -#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk -#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled -#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled -#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled - -#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos -#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk -#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled -#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled -#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled - -#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos -#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk -#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled -#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled -#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled - -#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos -#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk -#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled -#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled -#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled - -#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos -#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk -#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled -#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled -#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled - -#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos -#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk -#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled -#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled -#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled - -#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos -#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk -#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled -#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled -#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled - -#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos -#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk -#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled -#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled -#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled - -#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos -#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk -#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled -#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled -#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled - -#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos -#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk -#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled -#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled -#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled - -#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos -#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk -#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled -#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled -#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled - -#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos -#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk -#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled -#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled -#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled - -#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos -#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk -#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled -#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled -#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled - -#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos -#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk -#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled -#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled -#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled - -#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos -#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk -#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled -#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled -#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled - -#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos -#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk -#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled -#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled -#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled - -#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos -#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk -#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled -#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled -#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled - -#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos -#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk -#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled -#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled -#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled - -#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos -#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk -#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled -#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled -#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled - -#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos -#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk -#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled -#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled -#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled - -#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos -#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk -#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled -#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled -#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled - -#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos -#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk -#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled -#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled -#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled - -#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos -#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk -#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled -#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled -#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled - -#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos -#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk -#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled -#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled -#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled - -#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos -#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk -#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled -#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled -#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled - -#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos -#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk -#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled -#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled -#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled - -#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos -#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk -#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled -#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled -#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled - -#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos -#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk -#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled -#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled -#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled - -#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos -#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk -#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled -#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled -#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled - -#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos -#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk -#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled -#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled -#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled - -#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos -#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk -#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled -#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled -#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled - -#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos -#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk -#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled -#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled -#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled - -#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos -#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk -#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled -#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled -#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled - -#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos -#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk -#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled -#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled -#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled - -#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos -#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk -#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled -#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled -#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled - -#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos -#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk -#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled -#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled -#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled - -#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos -#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk -#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled -#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled -#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled - -#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos -#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk -#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled -#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled -#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled - -#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos -#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk -#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled -#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled -#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled - -#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos -#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk -#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled -#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled -#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled - -#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos -#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk -#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled -#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled -#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled - -#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos -#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk -#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled -#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled -#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled - -#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos -#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk -#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled -#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled -#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled - -#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos -#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk -#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled -#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled -#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled - -#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos -#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk -#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled -#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled -#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled - -#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos -#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk -#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled -#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled -#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled - -#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos -#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk -#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled -#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled -#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled - -#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos -#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk -#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled -#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled -#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled +#ifndef PROTENSET0 + #define PROTENSET0 CONFIG0 +#endif +#ifndef PROTENSET1 + #define PROTENSET1 CONFIG1 +#endif + +#ifndef MPU_PROTENSET1_PROTREG63_Pos + #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Msk + #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Disabled + #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Enabled + #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG63_Set + #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG62_Pos + #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Msk + #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Disabled + #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Enabled + #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG62_Set + #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG61_Pos + #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Msk + #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Disabled + #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Enabled + #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG61_Set + #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG60_Pos + #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Msk + #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Disabled + #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Enabled + #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG60_Set + #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG59_Pos + #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Msk + #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Disabled + #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Enabled + #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG59_Set + #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG58_Pos + #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Msk + #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Disabled + #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Enabled + #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG58_Set + #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG57_Pos + #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Msk + #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Disabled + #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Enabled + #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG57_Set + #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG56_Pos + #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Msk + #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Disabled + #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Enabled + #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG56_Set + #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG55_Pos + #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Msk + #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Disabled + #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Enabled + #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG55_Set + #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG54_Pos + #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Msk + #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Disabled + #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Enabled + #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG54_Set + #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG53_Pos + #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Msk + #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Disabled + #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Enabled + #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG53_Set + #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG52_Pos + #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Msk + #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Disabled + #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Enabled + #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG52_Set + #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG51_Pos + #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Msk + #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Disabled + #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Enabled + #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG51_Set + #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG50_Pos + #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Msk + #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Disabled + #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Enabled + #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG50_Set + #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG49_Pos + #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Msk + #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Disabled + #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Enabled + #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG49_Set + #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG48_Pos + #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Msk + #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Disabled + #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Enabled + #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG48_Set + #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG47_Pos + #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Msk + #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Disabled + #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Enabled + #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG47_Set + #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG46_Pos + #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Msk + #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Disabled + #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Enabled + #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG46_Set + #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG45_Pos + #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Msk + #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Disabled + #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Enabled + #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG45_Set + #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG44_Pos + #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Msk + #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Disabled + #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Enabled + #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG44_Set + #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG43_Pos + #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Msk + #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Disabled + #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Enabled + #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG43_Set + #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG42_Pos + #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Msk + #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Disabled + #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Enabled + #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG42_Set + #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG41_Pos + #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Msk + #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Disabled + #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Enabled + #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG41_Set + #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG40_Pos + #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Msk + #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Disabled + #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Enabled + #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG40_Set + #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG39_Pos + #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Msk + #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Disabled + #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Enabled + #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG39_Set + #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG38_Pos + #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Msk + #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Disabled + #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Enabled + #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG38_Set + #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG37_Pos + #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Msk + #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Disabled + #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Enabled + #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG37_Set + #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG36_Pos + #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Msk + #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Disabled + #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Enabled + #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG36_Set + #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG35_Pos + #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Msk + #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Disabled + #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Enabled + #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG35_Set + #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG34_Pos + #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Msk + #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Disabled + #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Enabled + #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG34_Set + #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG33_Pos + #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Msk + #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Disabled + #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Enabled + #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG33_Set + #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled +#endif + +#ifndef MPU_PROTENSET1_PROTREG32_Pos + #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Msk + #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Disabled + #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Enabled + #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#endif +#ifndef MPU_PROTENSET1_PROTREG32_Set + #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG31_Pos + #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Msk + #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Disabled + #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Enabled + #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG31_Set + #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG30_Pos + #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Msk + #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Disabled + #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Enabled + #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG30_Set + #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG29_Pos + #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Msk + #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Disabled + #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Enabled + #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG29_Set + #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG28_Pos + #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Msk + #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Disabled + #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Enabled + #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG28_Set + #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG27_Pos + #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Msk + #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Disabled + #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Enabled + #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG27_Set + #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG26_Pos + #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Msk + #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Disabled + #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Enabled + #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG26_Set + #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG25_Pos + #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Msk + #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Disabled + #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Enabled + #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG25_Set + #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG24_Pos + #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Msk + #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Disabled + #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Enabled + #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG24_Set + #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG23_Pos + #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Msk + #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Disabled + #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Enabled + #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG23_Set + #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG22_Pos + #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Msk + #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Disabled + #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Enabled + #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG22_Set + #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG21_Pos + #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Msk + #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Disabled + #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Enabled + #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG21_Set + #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG20_Pos + #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Msk + #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Disabled + #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Enabled + #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG20_Set + #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG19_Pos + #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Msk + #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Disabled + #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Enabled + #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG19_Set + #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG18_Pos + #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Msk + #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Disabled + #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Enabled + #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG18_Set + #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG17_Pos + #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Msk + #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Disabled + #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Enabled + #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG17_Set + #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Pos + #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Msk + #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Disabled + #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Enabled + #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG16_Set + #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Msk + #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Disabled + #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Enabled + #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG15_Set + #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG14_Pos + #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Msk + #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Disabled + #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Enabled + #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG14_Set + #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG13_Pos + #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Msk + #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Disabled + #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Enabled + #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG13_Set + #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG12_Pos + #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Msk + #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Disabled + #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Enabled + #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG12_Set + #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG11_Pos + #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Msk + #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Disabled + #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Enabled + #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG11_Set + #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG10_Pos + #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Msk + #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Disabled + #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Enabled + #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG10_Set + #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG9_Pos + #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Msk + #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Disabled + #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Enabled + #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG9_Set + #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG8_Pos + #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Msk + #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Disabled + #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Enabled + #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG8_Set + #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG7_Pos + #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Msk + #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Disabled + #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Enabled + #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG7_Set + #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG6_Pos + #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Msk + #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Disabled + #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Enabled + #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG6_Set + #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG5_Pos + #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Msk + #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Disabled + #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Enabled + #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG5_Set + #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG4_Pos + #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Msk + #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Disabled + #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Enabled + #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG4_Set + #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG3_Pos + #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Msk + #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Disabled + #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Enabled + #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG3_Set + #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG2_Pos + #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Msk + #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Disabled + #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Enabled + #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG2_Set + #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG1_Pos + #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Msk + #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Disabled + #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Enabled + #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG1_Set + #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled +#endif + +#ifndef MPU_PROTENSET0_PROTREG0_Pos + #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Msk + #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Disabled + #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Enabled + #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#endif +#ifndef MPU_PROTENSET0_PROTREG0_Set + #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled +#endif /* From nrf51_deprecated.h */ /* NVMC */ /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ -#define ERASEPROTECTEDPAGE ERASEPCR0 +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif /* IRQ */ /* COMP module was eliminated. Adapted to nrf52 headers. */ -#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler -#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif /* REFSEL register redefined enumerated values and added some more. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd - +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif /* RADIO */ /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif /* FICR */ /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#define DEVICEID0 DEVICEID[0] -#define DEVICEID1 DEVICEID[1] +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#define ER0 ER[0] -#define ER1 ER[1] -#define ER2 ER[2] -#define ER3 ER[3] +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#define IR0 IR[0] -#define IR1 IR[1] -#define IR2 IR[2] -#define IR3 IR[3] +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#define DEVICEADDR0 DEVICEADDR[0] -#define DEVICEADDR1 DEVICEADDR[1] +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif /* PPI */ /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#define TASKS_CHG0EN TASKS_CHG[0].EN -#define TASKS_CHG0DIS TASKS_CHG[0].DIS -#define TASKS_CHG1EN TASKS_CHG[1].EN -#define TASKS_CHG1DIS TASKS_CHG[1].DIS -#define TASKS_CHG2EN TASKS_CHG[2].EN -#define TASKS_CHG2DIS TASKS_CHG[2].DIS -#define TASKS_CHG3EN TASKS_CHG[3].EN -#define TASKS_CHG3DIS TASKS_CHG[3].DIS +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#define CH0_EEP CH[0].EEP -#define CH0_TEP CH[0].TEP -#define CH1_EEP CH[1].EEP -#define CH1_TEP CH[1].TEP -#define CH2_EEP CH[2].EEP -#define CH2_TEP CH[2].TEP -#define CH3_EEP CH[3].EEP -#define CH3_TEP CH[3].TEP -#define CH4_EEP CH[4].EEP -#define CH4_TEP CH[4].TEP -#define CH5_EEP CH[5].EEP -#define CH5_TEP CH[5].TEP -#define CH6_EEP CH[6].EEP -#define CH6_TEP CH[6].TEP -#define CH7_EEP CH[7].EEP -#define CH7_TEP CH[7].TEP -#define CH8_EEP CH[8].EEP -#define CH8_TEP CH[8].TEP -#define CH9_EEP CH[9].EEP -#define CH9_TEP CH[9].TEP -#define CH10_EEP CH[10].EEP -#define CH10_TEP CH[10].TEP -#define CH11_EEP CH[11].EEP -#define CH11_TEP CH[11].TEP -#define CH12_EEP CH[12].EEP -#define CH12_TEP CH[12].TEP -#define CH13_EEP CH[13].EEP -#define CH13_TEP CH[13].TEP -#define CH14_EEP CH[14].EEP -#define CH14_TEP CH[14].TEP -#define CH15_EEP CH[15].EEP -#define CH15_TEP CH[15].TEP +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#define CHG0 CHG[0] -#define CHG1 CHG[1] -#define CHG2 CHG[2] -#define CHG3 CHG[3] +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif /* All bitfield macros for the CHGx registers therefore changed name. */ -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included - +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif diff --git a/mdk/nrf51_to_nrf52810.h b/mdk/nrf51_to_nrf52810.h index ff521ab65..b56a89136 100644 --- a/mdk/nrf51_to_nrf52810.h +++ b/mdk/nrf51_to_nrf52810.h @@ -45,474 +45,1173 @@ POSSIBILITY OF SUCH DAMAGE. /* IRQ */ /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ -#define SWI0_IRQHandler SWI0_EGU0_IRQHandler -#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif -#define SWI0_IRQn SWI0_EGU0_IRQn -#define SWI1_IRQn SWI1_EGU1_IRQn +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif /* UICR */ /* Register RBPCONF was renamed to APPROTECT. */ -#define RBPCONF APPROTECT - -#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos -#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk -#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled -#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif /* GPIO */ /* GPIO port was renamed to P0. */ -#define NRF_GPIO NRF_P0 -#define NRF_GPIO_BASE NRF_P0_BASE +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif /* QDEC */ /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ -#define PSELLED PSEL.LED -#define PSELA PSEL.A -#define PSELB PSEL.B +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif /* SPIS */ /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ -#define PSELSCK PSEL.SCK -#define PSELMISO PSEL.MISO -#define PSELMOSI PSEL.MOSI -#define PSELCSN PSEL.CSN - -/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ -#define RXDPTR RXD.PTR -#define MAXRX RXD.MAXCNT -#define AMOUNTRX RXD.AMOUNT +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif -#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk -#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ -#define TXDPTR TXD.PTR -#define MAXTX TXD.MAXCNT -#define AMOUNTTX TXD.AMOUNT - -#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif /* From nrf51_deprecated.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ /* NVMC */ /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ -#define ERASEPROTECTEDPAGE ERASEPCR0 +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif /* RADIO */ /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif /* FICR */ /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#define DEVICEID0 DEVICEID[0] -#define DEVICEID1 DEVICEID[1] +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#define ER0 ER[0] -#define ER1 ER[1] -#define ER2 ER[2] -#define ER3 ER[3] +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#define IR0 IR[0] -#define IR1 IR[1] -#define IR2 IR[2] -#define IR3 IR[3] +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#define DEVICEADDR0 DEVICEADDR[0] -#define DEVICEADDR1 DEVICEADDR[1] +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif /* PPI */ /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#define TASKS_CHG0EN TASKS_CHG[0].EN -#define TASKS_CHG0DIS TASKS_CHG[0].DIS -#define TASKS_CHG1EN TASKS_CHG[1].EN -#define TASKS_CHG1DIS TASKS_CHG[1].DIS -#define TASKS_CHG2EN TASKS_CHG[2].EN -#define TASKS_CHG2DIS TASKS_CHG[2].DIS -#define TASKS_CHG3EN TASKS_CHG[3].EN -#define TASKS_CHG3DIS TASKS_CHG[3].DIS +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#define CH0_EEP CH[0].EEP -#define CH0_TEP CH[0].TEP -#define CH1_EEP CH[1].EEP -#define CH1_TEP CH[1].TEP -#define CH2_EEP CH[2].EEP -#define CH2_TEP CH[2].TEP -#define CH3_EEP CH[3].EEP -#define CH3_TEP CH[3].TEP -#define CH4_EEP CH[4].EEP -#define CH4_TEP CH[4].TEP -#define CH5_EEP CH[5].EEP -#define CH5_TEP CH[5].TEP -#define CH6_EEP CH[6].EEP -#define CH6_TEP CH[6].TEP -#define CH7_EEP CH[7].EEP -#define CH7_TEP CH[7].TEP -#define CH8_EEP CH[8].EEP -#define CH8_TEP CH[8].TEP -#define CH9_EEP CH[9].EEP -#define CH9_TEP CH[9].TEP -#define CH10_EEP CH[10].EEP -#define CH10_TEP CH[10].TEP -#define CH11_EEP CH[11].EEP -#define CH11_TEP CH[11].TEP -#define CH12_EEP CH[12].EEP -#define CH12_TEP CH[12].TEP -#define CH13_EEP CH[13].EEP -#define CH13_TEP CH[13].TEP -#define CH14_EEP CH[14].EEP -#define CH14_TEP CH[14].TEP -#define CH15_EEP CH[15].EEP -#define CH15_TEP CH[15].TEP +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#define CHG0 CHG[0] -#define CHG1 CHG[1] -#define CHG2 CHG[2] -#define CHG3 CHG[3] +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif /* All bitfield macros for the CHGx registers therefore changed name. */ -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif diff --git a/mdk/nrf51_to_nrf52840.h b/mdk/nrf51_to_nrf52840.h index d0a442162..eaf68dd9c 100644 --- a/mdk/nrf51_to_nrf52840.h +++ b/mdk/nrf51_to_nrf52840.h @@ -43,522 +43,1286 @@ POSSIBILITY OF SUCH DAMAGE. /* IRQ */ /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ -#define UART0_IRQHandler UARTE0_UART0_IRQHandler -#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#define ADC_IRQHandler SAADC_IRQHandler -#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler -#define SWI0_IRQHandler SWI0_EGU0_IRQHandler -#define SWI1_IRQHandler SWI1_EGU1_IRQHandler -#define SWI2_IRQHandler SWI2_EGU2_IRQHandler -#define SWI3_IRQHandler SWI3_EGU3_IRQHandler -#define SWI4_IRQHandler SWI4_EGU4_IRQHandler -#define SWI5_IRQHandler SWI5_EGU5_IRQHandler - -#define UART0_IRQn UARTE0_UART0_IRQn -#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#define ADC_IRQn SAADC_IRQn -#define LPCOMP_IRQn COMP_LPCOMP_IRQn -#define SWI0_IRQn SWI0_EGU0_IRQn -#define SWI1_IRQn SWI1_EGU1_IRQn -#define SWI2_IRQn SWI2_EGU2_IRQn -#define SWI3_IRQn SWI3_EGU3_IRQn -#define SWI4_IRQn SWI4_EGU4_IRQn -#define SWI5_IRQn SWI5_EGU5_IRQn +#ifndef UART0_IRQHandler + #define UART0_IRQHandler UARTE0_UART0_IRQHandler +#endif +#ifndef SPI0_TWI0_IRQHandler + #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#endif +#ifndef SPI1_TWI1_IRQHandler + #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#endif +#ifndef ADC_IRQHandler + #define ADC_IRQHandler SAADC_IRQHandler +#endif +#ifndef LPCOMP_IRQHandler + #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef SWI0_IRQHandler + #define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#endif +#ifndef SWI1_IRQHandler + #define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#endif +#ifndef SWI2_IRQHandler + #define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#endif +#ifndef SWI3_IRQHandler + #define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#endif +#ifndef SWI4_IRQHandler + #define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#endif +#ifndef SWI5_IRQHandler + #define SWI5_IRQHandler SWI5_EGU5_IRQHandler +#endif + +#ifndef UART0_IRQn + #define UART0_IRQn UARTE0_UART0_IRQn +#endif +#ifndef SPI0_TWI0_IRQn + #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#endif +#ifndef SPI1_TWI1_IRQn + #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#endif +#ifndef ADC_IRQn + #define ADC_IRQn SAADC_IRQn +#endif +#ifndef LPCOMP_IRQn + #define LPCOMP_IRQn COMP_LPCOMP_IRQn +#endif +#ifndef SWI0_IRQn + #define SWI0_IRQn SWI0_EGU0_IRQn +#endif +#ifndef SWI1_IRQn + #define SWI1_IRQn SWI1_EGU1_IRQn +#endif +#ifndef SWI2_IRQn + #define SWI2_IRQn SWI2_EGU2_IRQn +#endif +#ifndef SWI3_IRQn + #define SWI3_IRQn SWI3_EGU3_IRQn +#endif +#ifndef SWI4_IRQn + #define SWI4_IRQn SWI4_EGU4_IRQn +#endif +#ifndef SWI5_IRQn + #define SWI5_IRQn SWI5_EGU5_IRQn +#endif /* UICR */ /* Register RBPCONF was renamed to APPROTECT. */ -#define RBPCONF APPROTECT - -#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos -#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk -#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled -#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#ifndef RBPCONF + #define RBPCONF APPROTECT +#endif + +#ifndef UICR_RBPCONF_PALL_Pos + #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#endif +#ifndef UICR_RBPCONF_PALL_Msk + #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#endif +#ifndef UICR_RBPCONF_PALL_Enabled + #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#endif +#ifndef UICR_RBPCONF_PALL_Disabled + #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled +#endif /* GPIO */ /* GPIO port was renamed to P0. */ -#define NRF_GPIO NRF_P0 -#define NRF_GPIO_BASE NRF_P0_BASE +#ifndef NRF_GPIO + #define NRF_GPIO NRF_P0 +#endif +#ifndef NRF_GPIO_BASE + #define NRF_GPIO_BASE NRF_P0_BASE +#endif /* QDEC */ /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ -#define PSELLED PSEL.LED -#define PSELA PSEL.A -#define PSELB PSEL.B +#ifndef PSELLED + #define PSELLED PSEL.LED +#endif +#ifndef PSELA + #define PSELA PSEL.A +#endif +#ifndef PSELB + #define PSELB PSEL.B +#endif /* SPIS */ /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ -#define PSELSCK PSEL.SCK -#define PSELMISO PSEL.MISO -#define PSELMOSI PSEL.MOSI -#define PSELCSN PSEL.CSN +#ifndef PSELSCK + #define PSELSCK PSEL.SCK +#endif +#ifndef PSELMISO + #define PSELMISO PSEL.MISO +#endif +#ifndef PSELMOSI + #define PSELMOSI PSEL.MOSI +#endif +#ifndef PSELCSN + #define PSELCSN PSEL.CSN +#endif /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ -#define RXDPTR RXD.PTR -#define MAXRX RXD.MAXCNT -#define AMOUNTRX RXD.AMOUNT - -#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#ifndef RXDPTR + #define RXDPTR RXD.PTR +#endif +#ifndef MAXRX + #define MAXRX RXD.MAXCNT +#endif +#ifndef AMOUNTRX + #define AMOUNTRX RXD.AMOUNT +#endif + +#ifndef SPIS_MAXRX_MAXRX_Pos + #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXRX_MAXRX_Msk + #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos + #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk + #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk +#endif /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ -#define TXDPTR TXD.PTR -#define MAXTX TXD.MAXCNT -#define AMOUNTTX TXD.AMOUNT - -#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos -#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk - -#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos -#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#ifndef TXDPTR + #define TXDPTR TXD.PTR +#endif +#ifndef MAXTX + #define MAXTX TXD.MAXCNT +#endif +#ifndef AMOUNTTX + #define AMOUNTTX TXD.AMOUNT +#endif + +#ifndef SPIS_MAXTX_MAXTX_Pos + #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#endif +#ifndef SPIS_MAXTX_MAXTX_Msk + #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk +#endif + +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos + #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#endif +#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk + #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk +#endif /* UART */ /* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ -#define PSELRTS PSEL.RTS -#define PSELTXD PSEL.TXD -#define PSELCTS PSEL.CTS -#define PSELRXD PSEL.RXD +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif /* TWI */ /* The registers PSELSCL, PSELSDA were restructured into a struct. */ -#define PSELSCL PSEL.SCL -#define PSELSDA PSEL.SDA - +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif /* From nrf51_deprecated.h */ /* NVMC */ /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ -#define ERASEPROTECTEDPAGE ERASEPCR0 +#ifndef ERASEPROTECTEDPAGE + #define ERASEPROTECTEDPAGE ERASEPCR0 +#endif /* IRQ */ /* COMP module was eliminated. Adapted to nrf52840 headers. */ -#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler -#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#ifndef LPCOMP_COMP_IRQHandler + #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#endif +#ifndef LPCOMP_COMP_IRQn + #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +#endif /* REFSEL register redefined enumerated values and added some more. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#endif +#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling + #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd +#endif /* RADIO */ /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos + #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk + #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Include + #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#endif +#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip + #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip +#endif /* FICR */ /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#define DEVICEID0 DEVICEID[0] -#define DEVICEID1 DEVICEID[1] +#ifndef DEVICEID0 + #define DEVICEID0 DEVICEID[0] +#endif +#ifndef DEVICEID1 + #define DEVICEID1 DEVICEID[1] +#endif /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#define ER0 ER[0] -#define ER1 ER[1] -#define ER2 ER[2] -#define ER3 ER[3] +#ifndef ER0 + #define ER0 ER[0] +#endif +#ifndef ER1 + #define ER1 ER[1] +#endif +#ifndef ER2 + #define ER2 ER[2] +#endif +#ifndef ER3 + #define ER3 ER[3] +#endif /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#define IR0 IR[0] -#define IR1 IR[1] -#define IR2 IR[2] -#define IR3 IR[3] +#ifndef IR0 + #define IR0 IR[0] +#endif +#ifndef IR1 + #define IR1 IR[1] +#endif +#ifndef IR2 + #define IR2 IR[2] +#endif +#ifndef IR3 + #define IR3 IR[3] +#endif /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#define DEVICEADDR0 DEVICEADDR[0] -#define DEVICEADDR1 DEVICEADDR[1] +#ifndef DEVICEADDR0 + #define DEVICEADDR0 DEVICEADDR[0] +#endif +#ifndef DEVICEADDR1 + #define DEVICEADDR1 DEVICEADDR[1] +#endif /* PPI */ /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#define TASKS_CHG0EN TASKS_CHG[0].EN -#define TASKS_CHG0DIS TASKS_CHG[0].DIS -#define TASKS_CHG1EN TASKS_CHG[1].EN -#define TASKS_CHG1DIS TASKS_CHG[1].DIS -#define TASKS_CHG2EN TASKS_CHG[2].EN -#define TASKS_CHG2DIS TASKS_CHG[2].DIS -#define TASKS_CHG3EN TASKS_CHG[3].EN -#define TASKS_CHG3DIS TASKS_CHG[3].DIS +#ifndef TASKS_CHG0EN + #define TASKS_CHG0EN TASKS_CHG[0].EN +#endif +#ifndef TASKS_CHG0DIS + #define TASKS_CHG0DIS TASKS_CHG[0].DIS +#endif +#ifndef TASKS_CHG1EN + #define TASKS_CHG1EN TASKS_CHG[1].EN +#endif +#ifndef TASKS_CHG1DIS + #define TASKS_CHG1DIS TASKS_CHG[1].DIS +#endif +#ifndef TASKS_CHG2EN + #define TASKS_CHG2EN TASKS_CHG[2].EN +#endif +#ifndef TASKS_CHG2DIS + #define TASKS_CHG2DIS TASKS_CHG[2].DIS +#endif +#ifndef TASKS_CHG3EN + #define TASKS_CHG3EN TASKS_CHG[3].EN +#endif +#ifndef TASKS_CHG3DIS + #define TASKS_CHG3DIS TASKS_CHG[3].DIS +#endif /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#define CH0_EEP CH[0].EEP -#define CH0_TEP CH[0].TEP -#define CH1_EEP CH[1].EEP -#define CH1_TEP CH[1].TEP -#define CH2_EEP CH[2].EEP -#define CH2_TEP CH[2].TEP -#define CH3_EEP CH[3].EEP -#define CH3_TEP CH[3].TEP -#define CH4_EEP CH[4].EEP -#define CH4_TEP CH[4].TEP -#define CH5_EEP CH[5].EEP -#define CH5_TEP CH[5].TEP -#define CH6_EEP CH[6].EEP -#define CH6_TEP CH[6].TEP -#define CH7_EEP CH[7].EEP -#define CH7_TEP CH[7].TEP -#define CH8_EEP CH[8].EEP -#define CH8_TEP CH[8].TEP -#define CH9_EEP CH[9].EEP -#define CH9_TEP CH[9].TEP -#define CH10_EEP CH[10].EEP -#define CH10_TEP CH[10].TEP -#define CH11_EEP CH[11].EEP -#define CH11_TEP CH[11].TEP -#define CH12_EEP CH[12].EEP -#define CH12_TEP CH[12].TEP -#define CH13_EEP CH[13].EEP -#define CH13_TEP CH[13].TEP -#define CH14_EEP CH[14].EEP -#define CH14_TEP CH[14].TEP -#define CH15_EEP CH[15].EEP -#define CH15_TEP CH[15].TEP +#ifndef CH0_EEP + #define CH0_EEP CH[0].EEP +#endif +#ifndef CH0_TEP + #define CH0_TEP CH[0].TEP +#endif +#ifndef CH1_EEP + #define CH1_EEP CH[1].EEP +#endif +#ifndef CH1_TEP + #define CH1_TEP CH[1].TEP +#endif +#ifndef CH2_EEP + #define CH2_EEP CH[2].EEP +#endif +#ifndef CH2_TEP + #define CH2_TEP CH[2].TEP +#endif +#ifndef CH3_EEP + #define CH3_EEP CH[3].EEP +#endif +#ifndef CH3_TEP + #define CH3_TEP CH[3].TEP +#endif +#ifndef CH4_EEP + #define CH4_EEP CH[4].EEP +#endif +#ifndef CH4_TEP + #define CH4_TEP CH[4].TEP +#endif +#ifndef CH5_EEP + #define CH5_EEP CH[5].EEP +#endif +#ifndef CH5_TEP + #define CH5_TEP CH[5].TEP +#endif +#ifndef CH6_EEP + #define CH6_EEP CH[6].EEP +#endif +#ifndef CH6_TEP + #define CH6_TEP CH[6].TEP +#endif +#ifndef CH7_EEP + #define CH7_EEP CH[7].EEP +#endif +#ifndef CH7_TEP + #define CH7_TEP CH[7].TEP +#endif +#ifndef CH8_EEP + #define CH8_EEP CH[8].EEP +#endif +#ifndef CH8_TEP + #define CH8_TEP CH[8].TEP +#endif +#ifndef CH9_EEP + #define CH9_EEP CH[9].EEP +#endif +#ifndef CH9_TEP + #define CH9_TEP CH[9].TEP +#endif +#ifndef CH10_EEP + #define CH10_EEP CH[10].EEP +#endif +#ifndef CH10_TEP + #define CH10_TEP CH[10].TEP +#endif +#ifndef CH11_EEP + #define CH11_EEP CH[11].EEP +#endif +#ifndef CH11_TEP + #define CH11_TEP CH[11].TEP +#endif +#ifndef CH12_EEP + #define CH12_EEP CH[12].EEP +#endif +#ifndef CH12_TEP + #define CH12_TEP CH[12].TEP +#endif +#ifndef CH13_EEP + #define CH13_EEP CH[13].EEP +#endif +#ifndef CH13_TEP + #define CH13_TEP CH[13].TEP +#endif +#ifndef CH14_EEP + #define CH14_EEP CH[14].EEP +#endif +#ifndef CH14_TEP + #define CH14_TEP CH[14].TEP +#endif +#ifndef CH15_EEP + #define CH15_EEP CH[15].EEP +#endif +#ifndef CH15_TEP + #define CH15_TEP CH[15].TEP +#endif /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#define CHG0 CHG[0] -#define CHG1 CHG[1] -#define CHG2 CHG[2] -#define CHG3 CHG[3] +#ifndef CHG0 + #define CHG0 CHG[0] +#endif +#ifndef CHG1 + #define CHG1 CHG[1] +#endif +#ifndef CHG2 + #define CHG2 CHG[2] +#endif +#ifndef CHG3 + #define CHG3 CHG[3] +#endif /* All bitfield macros for the CHGx registers therefore changed name. */ -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included - -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included - -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included - -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included - -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included - -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included - -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included - -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included - -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included - -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included - -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included - -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included - -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included - -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included - -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included - -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included - -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#ifndef PPI_CHG0_CH15_Pos + #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG0_CH15_Msk + #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG0_CH15_Excluded + #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG0_CH15_Included + #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG0_CH14_Pos + #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG0_CH14_Msk + #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG0_CH14_Excluded + #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG0_CH14_Included + #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG0_CH13_Pos + #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG0_CH13_Msk + #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG0_CH13_Excluded + #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG0_CH13_Included + #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG0_CH12_Pos + #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG0_CH12_Msk + #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG0_CH12_Excluded + #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG0_CH12_Included + #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG0_CH11_Pos + #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG0_CH11_Msk + #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG0_CH11_Excluded + #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG0_CH11_Included + #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG0_CH10_Pos + #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG0_CH10_Msk + #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG0_CH10_Excluded + #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG0_CH10_Included + #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG0_CH9_Pos + #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG0_CH9_Msk + #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG0_CH9_Excluded + #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG0_CH9_Included + #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG0_CH8_Pos + #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG0_CH8_Msk + #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG0_CH8_Excluded + #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG0_CH8_Included + #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG0_CH7_Pos + #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG0_CH7_Msk + #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG0_CH7_Excluded + #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG0_CH7_Included + #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG0_CH6_Pos + #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG0_CH6_Msk + #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG0_CH6_Excluded + #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG0_CH6_Included + #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG0_CH5_Pos + #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG0_CH5_Msk + #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG0_CH5_Excluded + #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG0_CH5_Included + #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG0_CH4_Pos + #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG0_CH4_Msk + #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG0_CH4_Excluded + #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG0_CH4_Included + #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG0_CH3_Pos + #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG0_CH3_Msk + #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG0_CH3_Excluded + #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG0_CH3_Included + #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG0_CH2_Pos + #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG0_CH2_Msk + #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG0_CH2_Excluded + #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG0_CH2_Included + #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG0_CH1_Pos + #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG0_CH1_Msk + #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG0_CH1_Excluded + #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG0_CH1_Included + #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG0_CH0_Pos + #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG0_CH0_Msk + #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG0_CH0_Excluded + #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG0_CH0_Included + #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG1_CH15_Pos + #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG1_CH15_Msk + #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG1_CH15_Excluded + #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG1_CH15_Included + #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG1_CH14_Pos + #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG1_CH14_Msk + #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG1_CH14_Excluded + #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG1_CH14_Included + #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG1_CH13_Pos + #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG1_CH13_Msk + #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG1_CH13_Excluded + #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG1_CH13_Included + #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG1_CH12_Pos + #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG1_CH12_Msk + #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG1_CH12_Excluded + #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG1_CH12_Included + #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG1_CH11_Pos + #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG1_CH11_Msk + #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG1_CH11_Excluded + #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG1_CH11_Included + #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG1_CH10_Pos + #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG1_CH10_Msk + #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG1_CH10_Excluded + #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG1_CH10_Included + #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG1_CH9_Pos + #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG1_CH9_Msk + #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG1_CH9_Excluded + #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG1_CH9_Included + #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG1_CH8_Pos + #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG1_CH8_Msk + #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG1_CH8_Excluded + #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG1_CH8_Included + #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG1_CH7_Pos + #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG1_CH7_Msk + #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG1_CH7_Excluded + #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG1_CH7_Included + #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG1_CH6_Pos + #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG1_CH6_Msk + #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG1_CH6_Excluded + #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG1_CH6_Included + #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG1_CH5_Pos + #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG1_CH5_Msk + #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG1_CH5_Excluded + #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG1_CH5_Included + #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG1_CH4_Pos + #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG1_CH4_Msk + #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG1_CH4_Excluded + #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG1_CH4_Included + #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG1_CH3_Pos + #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG1_CH3_Msk + #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG1_CH3_Excluded + #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG1_CH3_Included + #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG1_CH2_Pos + #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG1_CH2_Msk + #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG1_CH2_Excluded + #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG1_CH2_Included + #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG1_CH1_Pos + #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG1_CH1_Msk + #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG1_CH1_Excluded + #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG1_CH1_Included + #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG1_CH0_Pos + #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG1_CH0_Msk + #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG1_CH0_Excluded + #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG1_CH0_Included + #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG2_CH15_Pos + #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG2_CH15_Msk + #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG2_CH15_Excluded + #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG2_CH15_Included + #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG2_CH14_Pos + #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG2_CH14_Msk + #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG2_CH14_Excluded + #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG2_CH14_Included + #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG2_CH13_Pos + #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG2_CH13_Msk + #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG2_CH13_Excluded + #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG2_CH13_Included + #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG2_CH12_Pos + #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG2_CH12_Msk + #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG2_CH12_Excluded + #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG2_CH12_Included + #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG2_CH11_Pos + #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG2_CH11_Msk + #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG2_CH11_Excluded + #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG2_CH11_Included + #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG2_CH10_Pos + #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG2_CH10_Msk + #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG2_CH10_Excluded + #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG2_CH10_Included + #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG2_CH9_Pos + #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG2_CH9_Msk + #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG2_CH9_Excluded + #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG2_CH9_Included + #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG2_CH8_Pos + #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG2_CH8_Msk + #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG2_CH8_Excluded + #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG2_CH8_Included + #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG2_CH7_Pos + #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG2_CH7_Msk + #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG2_CH7_Excluded + #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG2_CH7_Included + #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG2_CH6_Pos + #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG2_CH6_Msk + #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG2_CH6_Excluded + #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG2_CH6_Included + #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG2_CH5_Pos + #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG2_CH5_Msk + #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG2_CH5_Excluded + #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG2_CH5_Included + #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG2_CH4_Pos + #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG2_CH4_Msk + #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG2_CH4_Excluded + #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG2_CH4_Included + #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG2_CH3_Pos + #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG2_CH3_Msk + #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG2_CH3_Excluded + #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG2_CH3_Included + #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG2_CH2_Pos + #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG2_CH2_Msk + #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG2_CH2_Excluded + #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG2_CH2_Included + #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG2_CH1_Pos + #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG2_CH1_Msk + #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG2_CH1_Excluded + #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG2_CH1_Included + #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG2_CH0_Pos + #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG2_CH0_Msk + #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG2_CH0_Excluded + #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG2_CH0_Included + #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included +#endif + +#ifndef PPI_CHG3_CH15_Pos + #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#endif +#ifndef PPI_CHG3_CH15_Msk + #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#endif +#ifndef PPI_CHG3_CH15_Excluded + #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#endif +#ifndef PPI_CHG3_CH15_Included + #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included +#endif + +#ifndef PPI_CHG3_CH14_Pos + #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#endif +#ifndef PPI_CHG3_CH14_Msk + #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#endif +#ifndef PPI_CHG3_CH14_Excluded + #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#endif +#ifndef PPI_CHG3_CH14_Included + #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included +#endif + +#ifndef PPI_CHG3_CH13_Pos + #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#endif +#ifndef PPI_CHG3_CH13_Msk + #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#endif +#ifndef PPI_CHG3_CH13_Excluded + #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#endif +#ifndef PPI_CHG3_CH13_Included + #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included +#endif + +#ifndef PPI_CHG3_CH12_Pos + #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#endif +#ifndef PPI_CHG3_CH12_Msk + #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#endif +#ifndef PPI_CHG3_CH12_Excluded + #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#endif +#ifndef PPI_CHG3_CH12_Included + #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included +#endif + +#ifndef PPI_CHG3_CH11_Pos + #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#endif +#ifndef PPI_CHG3_CH11_Msk + #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#endif +#ifndef PPI_CHG3_CH11_Excluded + #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#endif +#ifndef PPI_CHG3_CH11_Included + #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included +#endif + +#ifndef PPI_CHG3_CH10_Pos + #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#endif +#ifndef PPI_CHG3_CH10_Msk + #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#endif +#ifndef PPI_CHG3_CH10_Excluded + #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#endif +#ifndef PPI_CHG3_CH10_Included + #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included +#endif + +#ifndef PPI_CHG3_CH9_Pos + #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#endif +#ifndef PPI_CHG3_CH9_Msk + #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#endif +#ifndef PPI_CHG3_CH9_Excluded + #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#endif +#ifndef PPI_CHG3_CH9_Included + #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included +#endif + +#ifndef PPI_CHG3_CH8_Pos + #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#endif +#ifndef PPI_CHG3_CH8_Msk + #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#endif +#ifndef PPI_CHG3_CH8_Excluded + #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#endif +#ifndef PPI_CHG3_CH8_Included + #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included +#endif + +#ifndef PPI_CHG3_CH7_Pos + #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#endif +#ifndef PPI_CHG3_CH7_Msk + #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#endif +#ifndef PPI_CHG3_CH7_Excluded + #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#endif +#ifndef PPI_CHG3_CH7_Included + #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included +#endif + +#ifndef PPI_CHG3_CH6_Pos + #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#endif +#ifndef PPI_CHG3_CH6_Msk + #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#endif +#ifndef PPI_CHG3_CH6_Excluded + #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#endif +#ifndef PPI_CHG3_CH6_Included + #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included +#endif + +#ifndef PPI_CHG3_CH5_Pos + #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#endif +#ifndef PPI_CHG3_CH5_Msk + #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#endif +#ifndef PPI_CHG3_CH5_Excluded + #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#endif +#ifndef PPI_CHG3_CH5_Included + #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included +#endif + +#ifndef PPI_CHG3_CH4_Pos + #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#endif +#ifndef PPI_CHG3_CH4_Msk + #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#endif +#ifndef PPI_CHG3_CH4_Excluded + #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#endif +#ifndef PPI_CHG3_CH4_Included + #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included +#endif + +#ifndef PPI_CHG3_CH3_Pos + #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#endif +#ifndef PPI_CHG3_CH3_Msk + #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#endif +#ifndef PPI_CHG3_CH3_Excluded + #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#endif +#ifndef PPI_CHG3_CH3_Included + #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included +#endif + +#ifndef PPI_CHG3_CH2_Pos + #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#endif +#ifndef PPI_CHG3_CH2_Msk + #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#endif +#ifndef PPI_CHG3_CH2_Excluded + #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#endif +#ifndef PPI_CHG3_CH2_Included + #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included +#endif + +#ifndef PPI_CHG3_CH1_Pos + #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#endif +#ifndef PPI_CHG3_CH1_Msk + #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#endif +#ifndef PPI_CHG3_CH1_Excluded + #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#endif +#ifndef PPI_CHG3_CH1_Included + #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included +#endif + +#ifndef PPI_CHG3_CH0_Pos + #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#endif +#ifndef PPI_CHG3_CH0_Msk + #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#endif +#ifndef PPI_CHG3_CH0_Excluded + #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#endif +#ifndef PPI_CHG3_CH0_Included + #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included +#endif + diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 96ad7a270..5e67f0b1d 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -30,10 +30,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 03. December 2018 - * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 * from File 'nrf52.svd', - * last modified on Monday, 03.12.2018 10:18:20 + * last modified on Thursday, 17.01.2019 16:25:35 */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index d7c0d2af8..5f91e3bc7 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -30,10 +30,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 03. December 2018 - * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 * from File 'nrf52810.svd', - * last modified on Monday, 03.12.2018 10:18:20 + * last modified on Thursday, 17.01.2019 16:25:35 */ @@ -83,9 +83,9 @@ typedef enum { /* ========================================== nrf52810 Specific Interrupt Numbers ========================================== */ POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_IRQn = 2, /*!< 2 UARTE0 */ - TWIM0_TWIS0_IRQn = 3, /*!< 3 TWIM0_TWIS0 */ - SPIM0_SPIS0_IRQn = 4, /*!< 4 SPIM0_SPIS0 */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + TWIM0_TWIS0_TWI0_IRQn = 3, /*!< 3 TWIM0_TWIS0_TWI0 */ + SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ SAADC_IRQn = 7, /*!< 7 SAADC */ TIMER0_IRQn = 8, /*!< 8 TIMER0 */ @@ -187,8 +187,7 @@ typedef struct { __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ - __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ -} FICR_INFO_Type; /*!< Size = 32 (0x20) */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ /** @@ -219,19 +218,29 @@ typedef struct { * @brief POWER_RAM [RAM] (Unspecified) */ typedef struct { - __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register. + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ - __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set - register */ - __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear register */ __IM uint32_t RESERVED; } POWER_RAM_Type; /*!< Size = 16 (0x10) */ +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + /** * @brief UARTE_PSEL [PSEL] (Unspecified) */ @@ -263,6 +272,15 @@ typedef struct { } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + /** * @brief TWIM_PSEL [PSEL] (Unspecified) */ @@ -310,7 +328,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -320,7 +339,18 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ /** @@ -373,7 +403,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -383,17 +414,18 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ /** - * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) */ typedef struct { - __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last results is equal - or above CH[n].LIMIT.HIGH */ - __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last results is equal - or below CH[n].LIMIT.LOW */ + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or + below CH[n].LIMIT.LOW */ } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ @@ -401,13 +433,13 @@ typedef struct { * @brief SAADC_CH [CH] (Unspecified) */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection for CH[n] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for CH[n] */ - __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event monitoring a channel */ } SAADC_CH_Type; /*!< Size = 16 (0x10) */ @@ -437,15 +469,14 @@ typedef struct { * @brief PWM_SEQ [SEQ] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in - RAM of this sequence */ - __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty - cycles) in this sequence */ - __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional - PWM periods between samples loaded into - compare register */ - __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the - sequence */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ __IM uint32_t RESERVED[4]; } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ @@ -454,8 +485,8 @@ typedef struct { * @brief PWM_PSEL [PSEL] (Unspecified) */ typedef struct { - __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select - for PWM channel n */ + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ @@ -483,10 +514,8 @@ typedef struct { * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group - n */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group - n */ + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ @@ -494,8 +523,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -503,7 +532,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -535,18 +564,17 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ __IM uint32_t RESERVED1[18]; - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ __IM uint32_t RESERVED2[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word - n */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity root, word + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ __IM uint32_t RESERVED3[21]; - __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ - __IM uint32_t RESERVED4[185]; - __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[188]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization coefficients */ } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ @@ -562,18 +590,14 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu */ typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ - __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ - __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ - __IM uint32_t RESERVED; - __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ - __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic - firmware design */ - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic - hardware design */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ __IM uint32_t RESERVED1[64]; - __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ @@ -594,8 +618,7 @@ typedef struct { /*!< (@ 0x40000000) BPROT Struct __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ - __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ -} NRF_BPROT_Type; /*!< Size = 1552 (0x610) */ +} NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ @@ -681,6 +704,36 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + /* =========================================================================================================================== */ /* ================ RADIO ================ */ /* =========================================================================================================================== */ @@ -718,7 +771,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ __IM uint32_t RESERVED3[50]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED4[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -744,28 +797,76 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED8; __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ - __IM uint32_t RESERVED8; + __IM uint32_t RESERVED9; __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ - __IM uint32_t RESERVED9[2]; + __IM uint32_t RESERVED10[2]; __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ - __IM uint32_t RESERVED10[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base - segment n */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix + __IM uint32_t RESERVED11[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ - __IM uint32_t RESERVED11[3]; + __IM uint32_t RESERVED12[3]; __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ - __IM uint32_t RESERVED12[618]; + __IM uint32_t RESERVED13[618]; __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + /* =========================================================================================================================== */ /* ================ UARTE0 ================ */ /* =========================================================================================================================== */ @@ -801,7 +902,7 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IM uint32_t RESERVED6; __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ __IM uint32_t RESERVED7[41]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -826,6 +927,59 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + /* =========================================================================================================================== */ /* ================ TWIM0 ================ */ /* =========================================================================================================================== */ @@ -860,7 +1014,7 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last byte */ __IM uint32_t RESERVED7[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -912,7 +1066,7 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ __IM uint32_t RESERVED7[37]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -927,21 +1081,50 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED12[9]; __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED13; __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[14]; - __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address - n */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match mechanism */ - __IM uint32_t RESERVED16[10]; + __IM uint32_t RESERVED15[10]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an over-read of the transmit buffer. */ } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface (SPI0) + */ + +typedef struct { /*!< (@ 0x40004000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + /* =========================================================================================================================== */ /* ================ SPIM0 ================ */ /* =========================================================================================================================== */ @@ -969,7 +1152,7 @@ typedef struct { /*!< (@ 0x40004000) SPIM0 Struct __IM uint32_t RESERVED6[10]; __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ __IM uint32_t RESERVED7[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1012,7 +1195,7 @@ typedef struct { /*!< (@ 0x40004000) SPIS0 Struct __IM uint32_t RESERVED3[5]; __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1026,14 +1209,12 @@ typedef struct { /*!< (@ 0x40004000) SPIS0 Struct __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED10[7]; __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ - __IM uint32_t RESERVED11; __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ - __IM uint32_t RESERVED12; __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED11; __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case of an ignored transaction. */ - __IM uint32_t RESERVED14[24]; + __IM uint32_t RESERVED12[24]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ @@ -1049,19 +1230,19 @@ typedef struct { /*!< (@ 0x40004000) SPIS0 Struct */ typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is configured in CONFIG[n].POLARITY. */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it high. */ + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ __IM uint32_t RESERVED1[4]; - __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it low. */ + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ __IM uint32_t RESERVED2[32]; - __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from pin specified in CONFIG[n].PSEL */ __IM uint32_t RESERVED3[23]; __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins @@ -1070,9 +1251,8 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED5[129]; - __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for - OUT[n], SET[n] and CLR[n] tasks and IN[n] - event */ + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n] and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1103,7 +1283,7 @@ typedef struct { /*!< (@ 0x40007000) SAADC Struct __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ - __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ __IM uint32_t RESERVED1[106]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1144,13 +1324,13 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value - to CC[n] register */ + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ __IM uint32_t RESERVED1[58]; - __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[42]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1160,7 +1340,7 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __IM uint32_t RESERVED5; __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register n */ } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ @@ -1184,7 +1364,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[109]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1198,7 +1378,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu t be written when RTC is stopped */ __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1262,7 +1442,7 @@ typedef struct { /*!< (@ 0x4000D000) RNG Structur __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number written to the VALUE register */ __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1355,7 +1535,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1400,7 +1580,7 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ @@ -1428,7 +1608,7 @@ typedef struct { /*!< (@ 0x40012000) QDEC Structu __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ __IM uint32_t RESERVED1[59]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1473,7 +1653,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1503,10 +1683,10 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ - __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ __IM uint32_t RESERVED[48]; - __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ __IM uint32_t RESERVED1[112]; @@ -1546,9 +1726,9 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ - __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM - value on all enabled channels from sequence - n, and starts playing that sequence at the + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on @@ -1558,16 +1738,16 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __IM uint32_t RESERVED1[60]; __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no longer generated */ - __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started on sequence n */ - __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of - every sequence n, when last value from RAM - has been applied to wave counter */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of times defined in LOOP.CNT */ __IM uint32_t RESERVED2[56]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1667,7 +1847,7 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu */ typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ __IM uint32_t RESERVED[308]; __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ @@ -1675,42 +1855,12 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur __IM uint32_t RESERVED1; __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ __IM uint32_t RESERVED2[148]; - __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ __IM uint32_t RESERVED3[62]; __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ - -/* =========================================================================================================================== */ -/* ================ P0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief GPIO Port (P0) - */ - -typedef struct { /*!< (@ 0x50000000) P0 Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ - __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that - have met the criteria set in the PIN_CNF[n].SENSE - registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour - and LDETECT mode */ - __IM uint32_t RESERVED1[118]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO - pins */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - /** @} */ /* End of group Device_Peripheral_peripherals */ @@ -1728,10 +1878,14 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_BPROT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL #define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL #define NRF_UARTE0_BASE 0x40002000UL +#define NRF_TWI0_BASE 0x40003000UL #define NRF_TWIM0_BASE 0x40003000UL #define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40004000UL #define NRF_SPIM0_BASE 0x40004000UL #define NRF_SPIS0_BASE 0x40004000UL #define NRF_GPIOTE_BASE 0x40006000UL @@ -1761,7 +1915,6 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_PDM_BASE 0x4001D000UL #define NRF_NVMC_BASE 0x4001E000UL #define NRF_PPI_BASE 0x4001F000UL -#define NRF_P0_BASE 0x50000000UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -1780,10 +1933,14 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) @@ -1813,7 +1970,6 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) -#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ diff --git a/mdk/nrf52810.svd b/mdk/nrf52810.svd index 62013cf7f..ad9d03896 100644 --- a/mdk/nrf52810.svd +++ b/mdk/nrf52810.svd @@ -104,7 +104,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 DEVICEID[%s] - Description collection[n]: Device identifier + Description collection: Device identifier 0x060 read-only 0xFFFFFFFF @@ -121,7 +121,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 ER[%s] - Description collection[n]: Encryption root, word n + Description collection: Encryption root, word n 0x080 read-only 0xFFFFFFFF @@ -138,7 +138,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 IR[%s] - Description collection[n]: Identity root, word n + Description collection: Identity root, word n 0x090 read-only 0xFFFFFFFF @@ -182,7 +182,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 DEVICEADDR[%s] - Description collection[n]: Device address n + Description collection: Device address n 0x0A4 read-only 0xFFFFFFFF @@ -199,6 +199,7 @@ POSSIBILITY OF SUCH DAMAGE.\n INFO Device info FICR_INFO + read-only 0x100 PART @@ -375,19 +376,12 @@ POSSIBILITY OF SUCH DAMAGE.\n - - 0x3 - 0x4 - UNUSED8[%s] - Unspecified - 0x014 - read-write - TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP + read-only 0x404 A0 @@ -659,35 +653,11 @@ POSSIBILITY OF SUCH DAMAGE.\n UICR 0x20 - - UNUSED0 - Unspecified - 0x000 - read-write - - - UNUSED1 - Unspecified - 0x004 - read-write - - - UNUSED2 - Unspecified - 0x008 - read-write - - - UNUSED3 - Unspecified - 0x010 - read-write - 0xF 0x4 NRFFW[%s] - Description collection[n]: Reserved for Nordic firmware design + Description collection: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF @@ -704,7 +674,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0xC 0x4 NRFHW[%s] - Description collection[n]: Reserved for Nordic hardware design + Description collection: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF @@ -721,7 +691,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 0x4 CUSTOMER[%s] - Description collection[n]: Reserved for customer + Description collection: Reserved for customer 0x080 read-write 0xFFFFFFFF @@ -738,16 +708,16 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 PSELRESET[%s] - Description collection[n]: Mapping of the nRESET function (see POWER chapter for details) + Description collection: Mapping of the nRESET function (see POWER chapter for details) 0x200 read-write 0xFFFFFFFF PIN - GPIO number P0.n onto which reset is exposed + GPIO pin number onto which nRESET is exposed 0 - 5 + 4 CONNECT @@ -1717,12 +1687,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - UNUSED0 - Unspecified - 0x60C - read-write - @@ -1750,8 +1714,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTART + Start HFCLK crystal oscillator 0 0 + + + Trigger + Trigger task + 1 + + @@ -1763,8 +1735,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator 0 0 + + + Trigger + Trigger task + 1 + + @@ -1776,8 +1756,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LFCLKSTART + Start LFCLK source 0 0 + + + Trigger + Trigger task + 1 + + @@ -1789,8 +1777,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LFCLKSTOP + Stop LFCLK source 0 0 + + + Trigger + Trigger task + 1 + + @@ -1802,8 +1798,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CAL + Start calibration of LFRC oscillator 0 0 + + + Trigger + Trigger task + 1 + + @@ -1815,8 +1819,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CTSTART + Start calibration timer 0 0 + + + Trigger + Trigger task + 1 + + @@ -1828,8 +1840,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CTSTOP + Stop calibration timer 0 0 + + + Trigger + Trigger task + 1 + + @@ -1841,8 +1861,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_HFCLKSTARTED + HFCLK oscillator started 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1854,8 +1887,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_LFCLKSTARTED + LFCLK started 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1867,8 +1913,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_DONE + Calibration of LFCLK RC oscillator complete event 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1880,8 +1939,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_CTTO + Calibration timer timeout 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1893,7 +1965,7 @@ POSSIBILITY OF SUCH DAMAGE.\n HFCLKSTARTED - Write '1' to enable interrupt for HFCLKSTARTED event + Write '1' to enable interrupt for event HFCLKSTARTED 0 0 @@ -1920,7 +1992,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LFCLKSTARTED - Write '1' to enable interrupt for LFCLKSTARTED event + Write '1' to enable interrupt for event LFCLKSTARTED 1 1 @@ -1947,7 +2019,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DONE - Write '1' to enable interrupt for DONE event + Write '1' to enable interrupt for event DONE 3 3 @@ -1974,7 +2046,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTTO - Write '1' to enable interrupt for CTTO event + Write '1' to enable interrupt for event CTTO 4 4 @@ -2009,7 +2081,7 @@ POSSIBILITY OF SUCH DAMAGE.\n HFCLKSTARTED - Write '1' to disable interrupt for HFCLKSTARTED event + Write '1' to disable interrupt for event HFCLKSTARTED 0 0 @@ -2036,7 +2108,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LFCLKSTARTED - Write '1' to disable interrupt for LFCLKSTARTED event + Write '1' to disable interrupt for event LFCLKSTARTED 1 1 @@ -2063,7 +2135,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DONE - Write '1' to disable interrupt for DONE event + Write '1' to disable interrupt for event DONE 3 3 @@ -2090,7 +2162,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTTO - Write '1' to disable interrupt for CTTO event + Write '1' to disable interrupt for event CTTO 4 4 @@ -2401,8 +2473,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CONSTLAT + Enable constant latency mode 0 0 + + + Trigger + Trigger task + 1 + + @@ -2414,8 +2494,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LOWPWR + Enable low power mode (variable latency) 0 0 + + + Trigger + Trigger task + 1 + + @@ -2427,8 +2515,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_POFWARN + Power failure warning 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2440,8 +2541,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2453,8 +2567,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2466,7 +2593,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POFWARN - Write '1' to enable interrupt for POFWARN event + Write '1' to enable interrupt for event POFWARN 2 2 @@ -2493,7 +2620,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPENTER - Write '1' to enable interrupt for SLEEPENTER event + Write '1' to enable interrupt for event SLEEPENTER 5 5 @@ -2520,7 +2647,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPEXIT - Write '1' to enable interrupt for SLEEPEXIT event + Write '1' to enable interrupt for event SLEEPEXIT 6 6 @@ -2555,7 +2682,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POFWARN - Write '1' to disable interrupt for POFWARN event + Write '1' to disable interrupt for event POFWARN 2 2 @@ -2582,7 +2709,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPENTER - Write '1' to disable interrupt for SLEEPENTER event + Write '1' to disable interrupt for event SLEEPENTER 5 5 @@ -2609,7 +2736,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPEXIT - Write '1' to disable interrupt for SLEEPEXIT event + Write '1' to disable interrupt for event SLEEPEXIT 6 6 @@ -2927,10 +3054,11 @@ POSSIBILITY OF SUCH DAMAGE.\n RAM[%s] Unspecified POWER_RAM + read-write 0x900 POWER - Description cluster[n]: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. + Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. 0x000 read-write 0x0000FFFF @@ -3011,7 +3139,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERSET - Description cluster[n]: RAMn power control set register + Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF @@ -3072,7 +3200,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERCLR - Description cluster[n]: RAMn power control clear register + Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF @@ -3135,732 +3263,596 @@ POSSIBILITY OF SUCH DAMAGE.\n - RADIO - 2.4 GHz Radio - 0x40001000 + P0 + GPIO Port + 0x50000000 + GPIO 0 0x1000 registers - - RADIO - 1 - - RADIO + GPIO 0x20 - TASKS_TXEN - Enable RADIO in TX mode - 0x000 - write-only - - - TASKS_TXEN - 0 - 0 - - - - - TASKS_RXEN - Enable RADIO in RX mode - 0x004 - write-only - - - TASKS_RXEN - 0 - 0 - - - - - TASKS_START - Start RADIO - 0x008 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop RADIO - 0x00C - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_DISABLE - Disable RADIO - 0x010 - write-only - - - TASKS_DISABLE - 0 - 0 - - - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength. - 0x014 - write-only - - - TASKS_RSSISTART - 0 - 0 - - - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0x018 - write-only - - - TASKS_RSSISTOP - 0 - 0 - - - - - TASKS_BCSTART - Start the bit counter - 0x01C - write-only - - - TASKS_BCSTART - 0 - 0 - - - - - TASKS_BCSTOP - Stop the bit counter - 0x020 - write-only - - - TASKS_BCSTOP - 0 - 0 - - - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0x100 - read-write - - - EVENTS_READY - 0 - 0 - - - - - EVENTS_ADDRESS - Address sent or received - 0x104 - read-write - - - EVENTS_ADDRESS - 0 - 0 - - - - - EVENTS_PAYLOAD - Packet payload sent or received - 0x108 - read-write - - - EVENTS_PAYLOAD - 0 - 0 - - - - - EVENTS_END - Packet sent or received - 0x10C - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_DISABLED - RADIO has been disabled - 0x110 - read-write - - - EVENTS_DISABLED - 0 - 0 - - - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0x114 - read-write - - - EVENTS_DEVMATCH - 0 - 0 - - - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0x118 - read-write - - - EVENTS_DEVMISS - 0 - 0 - - - - - EVENTS_RSSIEND - Sampling of receive signal strength complete. - 0x11C - read-write - - - EVENTS_RSSIEND - 0 - 0 - - - - - EVENTS_BCMATCH - Bit counter reached bit count value. - 0x128 - read-write - - - EVENTS_BCMATCH - 0 - 0 - - - - - EVENTS_CRCOK - Packet received with CRC ok - 0x130 - read-write - - - EVENTS_CRCOK - 0 - 0 - - - - - EVENTS_CRCERROR - Packet received with CRC error - 0x134 - read-write - - - EVENTS_CRCERROR - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 + OUT + Write GPIO port + 0x504 read-write - READY_START - Shortcut between READY event and START task + PIN0 + Pin 0 0 0 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - END_DISABLE - Shortcut between END event and DISABLE task + PIN1 + Pin 1 1 1 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_TXEN - Shortcut between DISABLED event and TXEN task + PIN2 + Pin 2 2 2 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_RXEN - Shortcut between DISABLED event and RXEN task + PIN3 + Pin 3 3 3 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - ADDRESS_RSSISTART - Shortcut between ADDRESS event and RSSISTART task + PIN4 + Pin 4 4 4 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - END_START - Shortcut between END event and START task + PIN5 + Pin 5 5 5 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - ADDRESS_BCSTART - Shortcut between ADDRESS event and BCSTART task + PIN6 + Pin 6 6 6 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_RSSISTOP - Shortcut between DISABLED event and RSSISTOP task - 8 - 8 + PIN7 + Pin 7 + 7 + 7 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + PIN8 + Pin 8 + 8 + 8 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN9 + Pin 9 + 9 + 9 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - ADDRESS - Write '1' to enable interrupt for ADDRESS event - 1 - 1 + PIN10 + Pin 10 + 10 + 10 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN11 + Pin 11 + 11 + 11 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - PAYLOAD - Write '1' to enable interrupt for PAYLOAD event - 2 - 2 + PIN12 + Pin 12 + 12 + 12 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN13 + Pin 13 + 13 + 13 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - END - Write '1' to enable interrupt for END event - 3 - 3 + PIN14 + Pin 14 + 14 + 14 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN15 + Pin 15 + 15 + 15 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - DISABLED - Write '1' to enable interrupt for DISABLED event - 4 - 4 + PIN16 + Pin 16 + 16 + 16 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN17 + Pin 17 + 17 + 17 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - DEVMATCH - Write '1' to enable interrupt for DEVMATCH event - 5 - 5 + PIN18 + Pin 18 + 18 + 18 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN19 + Pin 19 + 19 + 19 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - DEVMISS - Write '1' to enable interrupt for DEVMISS event - 6 - 6 + PIN20 + Pin 20 + 20 + 20 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN21 + Pin 21 + 21 + 21 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - RSSIEND - Write '1' to enable interrupt for RSSIEND event - 7 - 7 + PIN22 + Pin 22 + 22 + 22 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN23 + Pin 23 + 23 + 23 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - BCMATCH - Write '1' to enable interrupt for BCMATCH event - 10 - 10 + PIN24 + Pin 24 + 24 + 24 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN25 + Pin 25 + 25 + 25 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - CRCOK - Write '1' to enable interrupt for CRCOK event - 12 - 12 + PIN26 + Pin 26 + 26 + 26 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN27 + Pin 27 + 27 + 27 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 - CRCERROR - Write '1' to enable interrupt for CRCERROR event - 13 - 13 + PIN28 + Pin 28 + 28 + 28 - read - Disabled - Read: Disabled + Low + Pin driver is low 0 - Enabled - Read: Enabled + High + Pin driver is high 1 + + + PIN29 + Pin 29 + 29 + 29 - write - Set - Enable + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 @@ -3868,957 +3860,872 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + OUTSET + Set individual bits in GPIO port + 0x508 read-write + oneToSet - READY - Write '1' to disable interrupt for READY event + PIN0 + Pin 0 0 0 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDRESS - Write '1' to disable interrupt for ADDRESS event + PIN1 + Pin 1 1 1 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - PAYLOAD - Write '1' to disable interrupt for PAYLOAD event + PIN2 + Pin 2 2 2 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - END - Write '1' to disable interrupt for END event + PIN3 + Pin 3 3 3 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DISABLED - Write '1' to disable interrupt for DISABLED event + PIN4 + Pin 4 4 4 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMATCH - Write '1' to disable interrupt for DEVMATCH event + PIN5 + Pin 5 5 5 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMISS - Write '1' to disable interrupt for DEVMISS event + PIN6 + Pin 6 6 6 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - RSSIEND - Write '1' to disable interrupt for RSSIEND event + PIN7 + Pin 7 7 7 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - BCMATCH - Write '1' to disable interrupt for BCMATCH event - 10 - 10 + PIN8 + Pin 8 + 8 + 8 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CRCOK - Write '1' to disable interrupt for CRCOK event - 12 - 12 + PIN9 + Pin 9 + 9 + 9 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CRCERROR - Write '1' to disable interrupt for CRCERROR event - 13 - 13 + PIN10 + Pin 10 + 10 + 10 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - CRCSTATUS - CRC status - 0x400 - read-only - - CRCSTATUS - CRC status of packet received - 0 - 0 + PIN11 + Pin 11 + 11 + 11 + read - CRCError - Packet received with CRC error + Low + Read: pin driver is low 0 - CRCOk - Packet received with CRC ok + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - - RXMATCH - Received address - 0x408 - read-only - - - RXMATCH - Received address - 0 - 2 - - - - - RXCRC - CRC field of previously received packet - 0x40C - read-only - - - RXCRC - CRC field of previously received packet - 0 - 23 - - - - - DAI - Device address match index - 0x410 - read-only - - - DAI - Device address match index - 0 - 2 - - - - - PACKETPTR - Packet pointer - 0x504 - read-write - - - PACKETPTR - Packet pointer - 0 - 31 - - - - - FREQUENCY - Frequency - 0x508 - read-write - 0x00000002 - - - FREQUENCY - Radio channel frequency - 0 - 6 - MAP - Channel map selection. - 8 - 8 + PIN12 + Pin 12 + 12 + 12 + read - Default - Channel map between 2400 MHZ .. 2500 MHz + Low + Read: pin driver is low 0 - Low - Channel map between 2360 MHZ .. 2460 MHz + High + Read: pin driver is high 1 - - - - - TXPOWER - Output power - 0x50C - read-write - - - TXPOWER - RADIO output power. - 0 - 7 + write - Pos4dBm - +4 dBm - 0x04 + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + PIN13 + Pin 13 + 13 + 13 + + read - Pos3dBm - +3 dBm - 0x03 + Low + Read: pin driver is low + 0 - 0dBm - 0 dBm - 0x00 + High + Read: pin driver is high + 1 + + + write - Neg4dBm - -4 dBm - 0xFC + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + PIN14 + Pin 14 + 14 + 14 + + read - Neg8dBm - -8 dBm - 0xF8 + Low + Read: pin driver is low + 0 - Neg12dBm - -12 dBm - 0xF4 + High + Read: pin driver is high + 1 + + + write - Neg16dBm - -16 dBm - 0xF0 + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + PIN15 + Pin 15 + 15 + 15 + + read - Neg20dBm - -20 dBm - 0xEC + Low + Read: pin driver is low + 0 - Neg30dBm - Deprecated enumerator - -40 dBm - 0xFF + High + Read: pin driver is high + 1 + + + write - Neg40dBm - -40 dBm - 0xD8 + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 - - - - MODE - Data rate and modulation - 0x510 - read-write - - MODE - Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. - 0 - 3 + PIN16 + Pin 16 + 16 + 16 + read - Nrf_1Mbit - 1 Mbit/s Nordic proprietary radio mode + Low + Read: pin driver is low 0 - Nrf_2Mbit - 2 Mbit/s Nordic proprietary radio mode + High + Read: pin driver is high 1 + + + write - Ble_1Mbit - 1 Mbit/s Bluetooth Low Energy - 3 - - - Ble_2Mbit - 2 Mbit/s Bluetooth Low Energy - 4 + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 - - - - PCNF0 - Packet configuration register 0 - 0x514 - read-write - - - LFLEN - Length on air of LENGTH field in number of bits. - 0 - 3 - - - S0LEN - Length on air of S0 field in number of bytes. - 8 - 8 - - S1LEN - Length on air of S1 field in number of bits. - 16 - 19 - - - S1INCL - Include or exclude S1 field in RAM - 20 - 20 + PIN17 + Pin 17 + 17 + 17 + read - Automatic - Include S1 field in RAM only if S1LEN &gt; 0 + Low + Read: pin driver is low 0 - Include - Always include S1 field in RAM independent of S1LEN + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - PLEN - Length of preamble on air. Decision point: TASKS_START task - 24 - 24 + PIN18 + Pin 18 + 18 + 18 + read - 8bit - 8-bit preamble + Low + Read: pin driver is low 0 - 16bit - 16-bit preamble + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - - PCNF1 - Packet configuration register 1 - 0x518 - read-write - - - MAXLEN - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - 0 - 7 - - - STATLEN - Static length in number of bytes - 8 - 15 - BALEN - Base address length in number of bytes - 16 - 18 + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + - ENDIAN - On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. - 24 - 24 + PIN20 + Pin 20 + 20 + 20 + read - Little - Least Significant bit on air first + Low + Read: pin driver is low 0 - Big - Most significant bit on air first + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - WHITEEN - Enable or disable packet whitening - 25 - 25 + PIN21 + Pin 21 + 21 + 21 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - BASE0 - Base address 0 - 0x51C - read-write - - - BASE0 - Base address 0 - 0 - 31 - - - - - BASE1 - Base address 1 - 0x520 - read-write - - - BASE1 - Base address 1 - 0 - 31 - - - - - PREFIX0 - Prefixes bytes for logical addresses 0-3 - 0x524 - read-write - - - AP0 - Address prefix 0. - 0 - 7 - - - AP1 - Address prefix 1. - 8 - 15 - - - AP2 - Address prefix 2. - 16 - 23 - - - AP3 - Address prefix 3. - 24 - 31 - - - - - PREFIX1 - Prefixes bytes for logical addresses 4-7 - 0x528 - read-write - - - AP4 - Address prefix 4. - 0 - 7 - - - AP5 - Address prefix 5. - 8 - 15 - - - AP6 - Address prefix 6. - 16 - 23 - - - AP7 - Address prefix 7. - 24 - 31 - - - - - TXADDRESS - Transmit address select - 0x52C - read-write - - - TXADDRESS - Transmit address select - 0 - 2 - - - - - RXADDRESSES - Receive address select - 0x530 - read-write - - ADDR0 - Enable or disable reception on logical address 0. - 0 - 0 + PIN22 + Pin 22 + 22 + 22 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR1 - Enable or disable reception on logical address 1. - 1 - 1 + PIN23 + Pin 23 + 23 + 23 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR2 - Enable or disable reception on logical address 2. - 2 - 2 + PIN24 + Pin 24 + 24 + 24 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR3 - Enable or disable reception on logical address 3. - 3 - 3 + PIN25 + Pin 25 + 25 + 25 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR4 - Enable or disable reception on logical address 4. - 4 - 4 + PIN26 + Pin 26 + 26 + 26 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR5 - Enable or disable reception on logical address 5. - 5 - 5 + PIN27 + Pin 27 + 27 + 27 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR6 - Enable or disable reception on logical address 6. - 6 - 6 + PIN28 + Pin 28 + 28 + 28 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDR7 - Enable or disable reception on logical address 7. - 7 - 7 + PIN29 + Pin 29 + 29 + 29 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - CRCCNF - CRC configuration - 0x534 - read-write - - LEN - CRC length in number of bytes. - 0 - 1 + PIN30 + Pin 30 + 30 + 30 + read - Disabled - CRC length is zero and CRC calculation is disabled + Low + Read: pin driver is low 0 - One - CRC length is one byte and CRC calculation is enabled + High + Read: pin driver is high 1 + + + write - Two - CRC length is two bytes and CRC calculation is enabled - 2 - - - Three - CRC length is three bytes and CRC calculation is enabled - 3 + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 - SKIPADDR - Include or exclude packet address field out of CRC calculation. - 8 - 8 + PIN31 + Pin 31 + 31 + 31 + read - Include - CRC calculation includes address field + Low + Read: pin driver is low 0 - Skip - CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 @@ -4826,2684 +4733,2040 @@ POSSIBILITY OF SUCH DAMAGE.\n - CRCPOLY - CRC polynomial - 0x538 - read-write - 0x00000000 - - - CRCPOLY - CRC polynomial - 0 - 23 - - - - - CRCINIT - CRC initial value - 0x53C - read-write - - - CRCINIT - CRC initial value - 0 - 23 - - - - - UNUSED0 - Unspecified - 0x540 - read-write - - - TIFS - Inter Frame Spacing in us - 0x544 + OUTCLR + Clear individual bits in GPIO port + 0x50C read-write + oneToClear - TIFS - Inter Frame Spacing in us - 0 - 7 - - - - - RSSISAMPLE - RSSI sample - 0x548 - read-only - - - RSSISAMPLE - RSSI sample - 0 - 6 - - - - - STATE - Current radio state - 0x550 - read-only - - - STATE - Current radio state + PIN0 + Pin 0 0 - 3 + 0 + read - Disabled - RADIO is in the Disabled state + Low + Read: pin driver is low 0 - RxRu - RADIO is in the RXRU state + High + Read: pin driver is high 1 + + + write - RxIdle - RADIO is in the RXIDLE state - 2 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN1 + Pin 1 + 1 + 1 + + read - Rx - RADIO is in the RX state - 3 + Low + Read: pin driver is low + 0 - RxDisable - RADIO is in the RXDISABLED state - 4 + High + Read: pin driver is high + 1 + + + write - TxRu - RADIO is in the TXRU state - 9 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN2 + Pin 2 + 2 + 2 + + read - TxIdle - RADIO is in the TXIDLE state - 10 + Low + Read: pin driver is low + 0 - Tx - RADIO is in the TX state - 11 - - - TxDisable - RADIO is in the TXDISABLED state - 12 + High + Read: pin driver is high + 1 - - - - - DATAWHITEIV - Data whitening initial value - 0x554 - read-write - 0x00000040 - - - DATAWHITEIV - Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - 0 - 6 - - - - - BCC - Bit counter compare - 0x560 - read-write - - - BCC - Bit counter compare - 0 - 31 - - - - - 0x8 - 0x4 - DAB[%s] - Description collection[n]: Device address base segment n - 0x600 - read-write - - - DAB - Device address base segment n - 0 - 31 - - - - - 0x8 - 0x4 - DAP[%s] - Description collection[n]: Device address prefix n - 0x620 - read-write - - - DAP - Device address prefix n - 0 - 15 - - - - - DACNF - Device address match configuration - 0x640 - read-write - - - ENA0 - Enable or disable device address matching using device address 0 - 0 - 0 + write - Disabled - Disabled - 0 - - - Enabled - Enabled + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENA1 - Enable or disable device address matching using device address 1 - 1 - 1 + PIN3 + Pin 3 + 3 + 3 + read - Disabled - Disabled + Low + Read: pin driver is low 0 - Enabled - Enabled + High + Read: pin driver is high 1 - - - ENA2 - Enable or disable device address matching using device address 2 - 2 - 2 + write - Disabled - Disabled - 0 - - - Enabled - Enabled + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENA3 - Enable or disable device address matching using device address 3 - 3 - 3 + PIN4 + Pin 4 + 4 + 4 + read - Disabled - Disabled + Low + Read: pin driver is low 0 - Enabled - Enabled + High + Read: pin driver is high 1 - - - ENA4 - Enable or disable device address matching using device address 4 - 4 - 4 + write - Disabled - Disabled - 0 - - - Enabled - Enabled + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENA5 - Enable or disable device address matching using device address 5 + PIN5 + Pin 5 5 5 + read - Disabled - Disabled + Low + Read: pin driver is low 0 - Enabled - Enabled + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENA6 - Enable or disable device address matching using device address 6 + PIN6 + Pin 6 6 6 + read - Disabled - Disabled + Low + Read: pin driver is low 0 - Enabled - Enabled + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENA7 - Enable or disable device address matching using device address 7 + PIN7 + Pin 7 7 7 + read - Disabled - Disabled + Low + Read: pin driver is low 0 - Enabled - Enabled + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - TXADD0 - TxAdd for device address 0 + PIN8 + Pin 8 8 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD1 - TxAdd for device address 1 + PIN9 + Pin 9 9 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD2 - TxAdd for device address 2 + PIN10 + Pin 10 10 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD3 - TxAdd for device address 3 + PIN11 + Pin 11 11 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD4 - TxAdd for device address 4 + PIN12 + Pin 12 12 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD5 - TxAdd for device address 5 + PIN13 + Pin 13 13 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD6 - TxAdd for device address 6 + PIN14 + Pin 14 14 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - TXADD7 - TxAdd for device address 7 + PIN15 + Pin 15 15 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - - - - MODECNF0 - Radio mode configuration register 0 - 0x650 - read-write - 0x00000200 - - RU - Radio ramp-up time - 0 - 0 + PIN16 + Pin 16 + 16 + 16 + read - Default - Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + Low + Read: pin driver is low 0 - Fast - Fast ramp-up (tRXEN,FAST), see electrical specification for more information + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - DTX - Default TX value - 8 - 9 + PIN17 + Pin 17 + 17 + 17 + read - B1 - Transmit '1' + Low + Read: pin driver is low 0 - B0 - Transmit '0' + High + Read: pin driver is high 1 + + + write - Center - Transmit center frequency - 2 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 - - - - POWER - Peripheral power control - 0xFFC - read-write - 0x00000001 - - POWER - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - 0 - 0 + PIN18 + Pin 18 + 18 + 18 + read - Disabled - Peripheral is powered off + Low + Read: pin driver is low 0 - Enabled - Peripheral is powered on + High + Read: pin driver is high 1 - - - - - - - UARTE0 - UART with EasyDMA - 0x40002000 - UARTE - - 0 - 0x1000 - registers - - - UARTE0 - 2 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - 0 - 0 - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - 0 - 0 - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - 0 - 0 - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - 0 - 0 - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - 0 - 0 - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - 0 - 0 - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - 0 - 0 - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - ENDRX_STARTRX - Shortcut between ENDRX event and STARTRX task - 5 - 5 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENDRX_STOPRX - Shortcut between ENDRX event and STOPRX task - 6 - 6 + PIN19 + Pin 19 + 19 + 19 + read - Disabled - Disable shortcut + Low + Read: pin driver is low 0 - Enabled - Enable shortcut + High + Read: pin driver is high 1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - CTS - Enable or disable interrupt for CTS event - 0 - 0 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - NCTS - Enable or disable interrupt for NCTS event - 1 - 1 + PIN20 + Pin 20 + 20 + 20 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high 1 - - - RXDRDY - Enable or disable interrupt for RXDRDY event - 2 - 2 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENDRX - Enable or disable interrupt for ENDRX event - 4 - 4 + PIN21 + Pin 21 + 21 + 21 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high 1 - - - TXDRDY - Enable or disable interrupt for TXDRDY event - 7 - 7 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENDTX - Enable or disable interrupt for ENDTX event - 8 - 8 + PIN22 + Pin 22 + 22 + 22 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high 1 - - - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - RXTO - Enable or disable interrupt for RXTO event - 17 - 17 + PIN23 + Pin 23 + 23 + 23 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high 1 - - - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + PIN24 + Pin 24 + 24 + 24 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high 1 - - - TXSTOPPED - Enable or disable interrupt for TXSTOPPED event - 22 - 22 + write - Disabled - Disable - 0 - - - Enabled - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - CTS - Write '1' to enable interrupt for CTS event - 0 - 0 + PIN25 + Pin 25 + 25 + 25 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - NCTS - Write '1' to enable interrupt for NCTS event - 1 - 1 + PIN26 + Pin 26 + 26 + 26 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - RXDRDY - Write '1' to enable interrupt for RXDRDY event - 2 - 2 + PIN27 + Pin 27 + 27 + 27 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN28 + Pin 28 + 28 + 28 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - TXDRDY - Write '1' to enable interrupt for TXDRDY event - 7 - 7 + PIN29 + Pin 29 + 29 + 29 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN30 + Pin 30 + 30 + 30 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN31 + Pin 31 + 31 + 31 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Set - Enable + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 + + + + IN + Read GPIO port + 0x510 + read-only + - RXTO - Write '1' to enable interrupt for RXTO event - 17 - 17 + PIN0 + Pin 0 + 0 + 0 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + High + Pin input is high 1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + PIN1 + Pin 1 + 1 + 1 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + High + Pin input is high 1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + PIN2 + Pin 2 + 2 + 2 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + High + Pin input is high 1 - TXSTOPPED - Write '1' to enable interrupt for TXSTOPPED event - 22 - 22 + PIN3 + Pin 3 + 3 + 3 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + High + Pin input is high 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - CTS - Write '1' to disable interrupt for CTS event - 0 - 0 + PIN4 + Pin 4 + 4 + 4 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + High + Pin input is high 1 - NCTS - Write '1' to disable interrupt for NCTS event - 1 - 1 + PIN5 + Pin 5 + 5 + 5 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN6 + Pin 6 + 6 + 6 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - RXDRDY - Write '1' to disable interrupt for RXDRDY event - 2 - 2 + PIN7 + Pin 7 + 7 + 7 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN8 + Pin 8 + 8 + 8 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN9 + Pin 9 + 9 + 9 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN10 + Pin 10 + 10 + 10 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - TXDRDY - Write '1' to disable interrupt for TXDRDY event - 7 - 7 + PIN11 + Pin 11 + 11 + 11 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN12 + Pin 12 + 12 + 12 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - ENDTX - Write '1' to disable interrupt for ENDTX event - 8 - 8 + PIN13 + Pin 13 + 13 + 13 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN14 + Pin 14 + 14 + 14 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN15 + Pin 15 + 15 + 15 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN16 + Pin 16 + 16 + 16 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - RXTO - Write '1' to disable interrupt for RXTO event + PIN17 + Pin 17 17 17 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN18 + Pin 18 + 18 + 18 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event + PIN19 + Pin 19 19 19 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + High + Pin input is high 1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event + PIN20 + Pin 20 20 20 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN21 + Pin 21 + 21 + 21 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - TXSTOPPED - Write '1' to disable interrupt for TXSTOPPED event + PIN22 + Pin 22 22 22 - read - Disabled - Read: Disabled + Low + Pin input is low 0 - Enabled - Read: Enabled + High + Pin input is high 1 + + + PIN23 + Pin 23 + 23 + 23 - write - Clear - Disable + Low + Pin input is low + 0 + + + High + Pin input is high 1 - - - - ERRORSRC - Error source Note : this register is read / write one to clear. - 0x480 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + PIN24 + Pin 24 + 24 + 24 - read - NotPresent - Read: error not present + Low + Pin input is low 0 - Present - Read: error present + High + Pin input is high 1 - PARITY - Parity error - 1 - 1 + PIN25 + Pin 25 + 25 + 25 - read - NotPresent - Read: error not present + Low + Pin input is low 0 - Present - Read: error present + High + Pin input is high 1 - FRAMING - Framing error occurred - 2 - 2 + PIN26 + Pin 26 + 26 + 26 - read - NotPresent - Read: error not present + Low + Pin input is low 0 - Present - Read: error present + High + Pin input is high 1 - BREAK - Break condition - 3 - 3 + PIN27 + Pin 27 + 27 + 27 - read - NotPresent - Read: error not present + Low + Pin input is low 0 - Present - Read: error present + High + Pin input is high 1 - - - - ENABLE - Enable UART - 0x500 - read-write - - ENABLE - Enable or disable UARTE - 0 - 3 + PIN28 + Pin 28 + 28 + 28 - Disabled - Disable UARTE + Low + Pin input is low 0 - Enabled - Enable UARTE - 8 + High + Pin input is high + 1 - - - - PSEL - Unspecified - UARTE_PSEL - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - BAUDRATE - Baud rate - 0 - 31 + PIN29 + Pin 29 + 29 + 29 - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 - - - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 - - - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 - - - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 - - - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 - - - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 - - - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 - - - Baud31250 - 31250 baud - 0x00800000 - - - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 - - - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 + Low + Pin input is low + 0 - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 + High + Pin input is high + 1 + + + + PIN30 + Pin 30 + 30 + 30 + - Baud250000 - 250000 baud - 0x04000000 + Low + Pin input is low + 0 - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 + High + Pin input is high + 1 + + + + PIN31 + Pin 31 + 31 + 31 + - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 + Low + Pin input is low + 0 - Baud1M - 1Mega baud - 0x10000000 + High + Pin input is high + 1 - - RXD - RXD EasyDMA channel - UARTE_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C + DIR + Direction of GPIO pins + 0x514 read-write - HWFC - Hardware flow control + PIN0 + Pin 0 0 0 - Disabled - Disabled + Input + Pin set as input 0 - Enabled - Enabled + Output + Pin set as output 1 - PARITY - Parity + PIN1 + Pin 1 1 - 3 + 1 - Excluded - Exclude parity bit - 0x0 + Input + Pin set as input + 0 - Included - Include even parity bit - 0x7 + Output + Pin set as output + 1 - STOP - Stop bits - 4 - 4 + PIN2 + Pin 2 + 2 + 2 - One - One stop bit + Input + Pin set as input 0 - Two - Two stop bits + Output + Pin set as output 1 - - - - - - TWIM0 - I2C compatible Two-Wire Master Interface with EasyDMA - 0x40003000 - TWIM - - 0 - 0x1000 - registers - - - TWIM0_TWIS0 - 3 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - 0 - 0 - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - 0 - 0 - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - LASTTX_STARTRX - Shortcut between LASTTX event and STARTRX task - 7 - 7 + PIN3 + Pin 3 + 3 + 3 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - LASTTX_SUSPEND - Shortcut between LASTTX event and SUSPEND task - 8 - 8 + PIN4 + Pin 4 + 4 + 4 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - LASTTX_STOP - Shortcut between LASTTX event and STOP task - 9 - 9 + PIN5 + Pin 5 + 5 + 5 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - LASTRX_STARTTX - Shortcut between LASTRX event and STARTTX task - 10 - 10 + PIN6 + Pin 6 + 6 + 6 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - LASTRX_SUSPEND - Shortcut between LASTRX event and SUSPEND task - 11 - 11 + PIN7 + Pin 7 + 7 + 7 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - LASTRX_STOP - Shortcut between LASTRX event and STOP task - 12 - 12 + PIN8 + Pin 8 + 8 + 8 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + PIN9 + Pin 9 + 9 + 9 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + PIN10 + Pin 10 + 10 + 10 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - SUSPENDED - Enable or disable interrupt for SUSPENDED event - 18 - 18 + PIN11 + Pin 11 + 11 + 11 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + PIN12 + Pin 12 + 12 + 12 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + PIN13 + Pin 13 + 13 + 13 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - LASTRX - Enable or disable interrupt for LASTRX event - 23 - 23 + PIN14 + Pin 14 + 14 + 14 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - LASTTX - Enable or disable interrupt for LASTTX event - 24 - 24 + PIN15 + Pin 15 + 15 + 15 - Disabled - Disable + Input + Pin set as input 0 - Enabled - Enable + Output + Pin set as output 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + PIN16 + Pin 16 + 16 + 16 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN17 + Pin 17 + 17 + 17 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - SUSPENDED - Write '1' to enable interrupt for SUSPENDED event + PIN18 + Pin 18 18 18 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event + PIN19 + Pin 19 19 19 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event + PIN20 + Pin 20 20 20 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - LASTRX - Write '1' to enable interrupt for LASTRX event - 23 - 23 + PIN21 + Pin 21 + 21 + 21 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 - - write - - Set - Enable + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - LASTTX - Write '1' to enable interrupt for LASTTX event + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 24 24 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN25 + Pin 25 + 25 + 25 - write - Set - Enable + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output 1 @@ -7511,901 +6774,513 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + DIRSET + DIR set register + 0x518 read-write + oneToSet - STOPPED - Write '1' to disable interrupt for STOPPED event + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 1 1 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN2 + Set as output pin 2 + 2 + 2 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - SUSPENDED - Write '1' to disable interrupt for SUSPENDED event - 18 - 18 + PIN3 + Set as output pin 3 + 3 + 3 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event - 19 - 19 + PIN4 + Set as output pin 4 + 4 + 4 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event - 20 - 20 + PIN5 + Set as output pin 5 + 5 + 5 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - LASTRX - Write '1' to disable interrupt for LASTRX event - 23 - 23 + PIN6 + Set as output pin 6 + 6 + 6 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - LASTTX - Write '1' to disable interrupt for LASTTX event - 24 - 24 + PIN7 + Set as output pin 7 + 7 + 7 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - ERRORSRC - Error source - 0x4C4 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + PIN8 + Set as output pin 8 + 8 + 8 + read - NotReceived - Error did not occur + Input + Read: pin set as input 0 - Received - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ANACK - NACK received after sending the address (write '1' to clear) - 1 - 1 + PIN9 + Set as output pin 9 + 9 + 9 + read - NotReceived - Error did not occur + Input + Read: pin set as input 0 - Received - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - DNACK - NACK received after sending a data byte (write '1' to clear) - 2 - 2 + PIN10 + Set as output pin 10 + 10 + 10 + read - NotReceived - Error did not occur + Input + Read: pin set as input 0 - Received - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - ENABLE - Enable TWIM - 0x500 - read-write - - ENABLE - Enable or disable TWIM - 0 - 3 + PIN11 + Set as output pin 11 + 11 + 11 + read - Disabled - Disable TWIM + Input + Read: pin set as input 0 - Enabled - Enable TWIM - 6 + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 - - - - PSEL - Unspecified - TWIM_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - TWI master clock frequency - 0 - 31 + PIN12 + Set as output pin 12 + 12 + 12 + read - K100 - 100 kbps - 0x01980000 + Input + Read: pin set as input + 0 - K250 - 250 kbps - 0x04000000 + Output + Read: pin set as output + 1 + + + write - K400 - 400 kbps - 0x06400000 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 - - - - RXD - RXD EasyDMA channel - TWIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 9 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 9 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIS0 - I2C compatible Two-Wire Slave Interface with EasyDMA - 0x40003000 - TWIM0 - TWIS - - 0 - 0x1000 - registers - - - TWIM0_TWIS0 - 3 - - TWIS - 0x20 - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - - TASKS_PREPARERX - 0 - 0 - - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - - TASKS_PREPARETX - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_WRITE - Write command received - 0x164 - read-write - - - EVENTS_WRITE - 0 - 0 - - - - - EVENTS_READ - Read command received - 0x168 - read-write - - - EVENTS_READ - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - WRITE_SUSPEND - Shortcut between WRITE event and SUSPEND task + PIN13 + Set as output pin 13 13 13 + read - Disabled - Disable shortcut + Input + Read: pin set as input 0 - Enabled - Enable shortcut + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - READ_SUSPEND - Shortcut between READ event and SUSPEND task + PIN14 + Set as output pin 14 14 14 + read - Disabled - Disable shortcut + Input + Read: pin set as input 0 - Enabled - Enable shortcut + Output + Read: pin set as output 1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + PIN15 + Set as output pin 15 + 15 + 15 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + PIN16 + Set as output pin 16 + 16 + 16 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - WRITE - Enable or disable interrupt for WRITE event - 25 - 25 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - READ - Enable or disable interrupt for READ event - 26 - 26 + PIN17 + Set as output pin 17 + 17 + 17 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + PIN18 + Set as output pin 18 + 18 + 18 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8413,26 +7288,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN19 + Set as output pin 19 + 19 + 19 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8440,26 +7315,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + PIN20 + Set as output pin 20 + 20 + 20 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8467,26 +7342,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + PIN21 + Set as output pin 21 + 21 + 21 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8494,26 +7369,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - WRITE - Write '1' to enable interrupt for WRITE event - 25 - 25 + PIN22 + Set as output pin 22 + 22 + 22 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8521,26 +7396,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - READ - Write '1' to enable interrupt for READ event - 26 - 26 + PIN23 + Set as output pin 23 + 23 + 23 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -8548,177 +7423,223 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + PIN24 + Set as output pin 24 + 24 + 24 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN25 + Set as output pin 25 + 25 + 25 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event - 19 - 19 + PIN26 + Set as output pin 26 + 26 + 26 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event - 20 - 20 + PIN27 + Set as output pin 27 + 27 + 27 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - WRITE - Write '1' to disable interrupt for WRITE event - 25 - 25 + PIN28 + Set as output pin 28 + 28 + 28 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - READ - Write '1' to disable interrupt for READ event - 26 - 26 + PIN29 + Set as output pin 29 + 29 + 29 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 @@ -8726,677 +7647,351 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERRORSRC - Error source - 0x4D0 + DIRCLR + DIR clear register + 0x51C read-write oneToClear - OVERFLOW - RX buffer overflow detected, and prevented + PIN0 + Set as input pin 0 0 0 + read - NotDetected - Error did not occur + Input + Read: pin set as input 0 - Detected - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - DNACK - NACK sent after receiving a data byte + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 2 2 + read - NotReceived - Error did not occur + Input + Read: pin set as input 0 - Received - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - OVERREAD - TX buffer over-read detected, and prevented + PIN3 + Set as input pin 3 3 3 + read - NotDetected - Error did not occur + Input + Read: pin set as input 0 - Detected - Error occurred + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - MATCH - Status register indicating which address had a match - 0x4D4 - read-only - - MATCH - Which of the addresses in {ADDRESS} matched the incoming address - 0 - 0 + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + - - - - ENABLE - Enable TWIS - 0x500 - read-write - - ENABLE - Enable or disable TWIS - 0 - 3 + PIN5 + Set as input pin 5 + 5 + 5 + read - Disabled - Disable TWIS + Input + Read: pin set as input 0 - Enabled - Enable TWIS - 9 + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - PSEL - Unspecified - TWIS_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 9 - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 9 - - - - - - 0x2 - 0x4 - ADDRESS[%s] - Description collection[n]: TWI slave address n - 0x588 - read-write - - ADDRESS - TWI slave address - 0 + PIN6 + Set as input pin 6 + 6 6 - - - - - CONFIG - Configuration register for the address match mechanism - 0x594 - read-write - 0x00000001 - - - ADDRESS0 - Enable or disable address matching on ADDRESS[0] - 0 - 0 + read - Disabled - Disabled + Input + Read: pin set as input 0 - Enabled - Enabled + Output + Read: pin set as output 1 - - - ADDRESS1 - Enable or disable address matching on ADDRESS[1] - 1 - 1 + write - Disabled - Disabled - 0 - - - Enabled - Enabled + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 - read-write - - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 + PIN7 + Set as input pin 7 + 7 7 - - - - - - - SPIM0 - Serial Peripheral Interface Master with EasyDMA - 0x40004000 - SPIM - - 0 - 0x1000 - registers - - - SPIM0_SPIS0 - 4 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - END_START - Shortcut between END event and START task - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN8 + Set as input pin 8 + 8 + 8 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - END - Write '1' to enable interrupt for END event - 6 - 6 + PIN9 + Set as input pin 9 + 9 + 9 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN10 + Set as input pin 10 + 10 + 10 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - STARTED - Write '1' to enable interrupt for STARTED event - 19 - 19 + PIN11 + Set as input pin 11 + 11 + 11 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + PIN12 + Set as input pin 12 + 12 + 12 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9404,26 +7999,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN13 + Set as input pin 13 + 13 + 13 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9431,26 +8026,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - END - Write '1' to disable interrupt for END event - 6 - 6 + PIN14 + Set as input pin 14 + 14 + 14 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9458,26 +8053,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDTX - Write '1' to disable interrupt for ENDTX event - 8 - 8 + PIN15 + Set as input pin 15 + 15 + 15 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9485,26 +8080,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - STARTED - Write '1' to disable interrupt for STARTED event - 19 - 19 + PIN16 + Set as input pin 16 + 16 + 16 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9512,641 +8107,350 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - ENABLE - Enable SPIM - 0x500 - read-write - - ENABLE - Enable or disable SPIM - 0 - 3 + PIN17 + Set as input pin 17 + 17 + 17 + read - Disabled - Disable SPIM + Input + Read: pin set as input 0 - Enabled - Enable SPIM - 7 + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - PSEL - Unspecified - SPIM_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - SPI master data rate - 0 - 31 + PIN18 + Set as input pin 18 + 18 + 18 + read - K125 - 125 kbps - 0x02000000 + Input + Read: pin set as input + 0 - K250 - 250 kbps - 0x04000000 + Output + Read: pin set as output + 1 + + + write - K500 - 500 kbps - 0x08000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read - M1 - 1 Mbps - 0x10000000 + Input + Read: pin set as input + 0 - M2 - 2 Mbps - 0x20000000 + Output + Read: pin set as output + 1 + + + write - M4 - 4 Mbps - 0x40000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read - M8 - 8 Mbps - 0x80000000 + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - RXD - RXD EasyDMA channel - SPIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - ORDER - Bit order - 0 - 0 + PIN21 + Set as input pin 21 + 21 + 21 + read - MsbFirst - Most significant bit shifted out first + Input + Read: pin set as input 0 - LsbFirst - Least significant bit shifted out first + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - CPHA - Serial clock (SCK) phase - 1 - 1 + PIN22 + Set as input pin 22 + 22 + 22 + read - Leading - Sample on leading edge of clock, shift serial data on trailing edge + Input + Read: pin set as input 0 - Trailing - Sample on trailing edge of clock, shift serial data on leading edge + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - CPOL - Serial clock (SCK) polarity - 2 - 2 + PIN23 + Set as input pin 23 + 23 + 23 + read - ActiveHigh - Active high + Input + Read: pin set as input 0 - ActiveLow - Active low + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - ORC - Over-read character. Character clocked out in case and over-read of the TXD buffer. - 0x5C0 - read-write - - ORC - Over-read character. Character clocked out in case and over-read of the TXD buffer. - 0 - 7 - - - - - - - SPIS0 - SPI Slave - 0x40004000 - SPIM0 - SPIS - - 0 - 0x1000 - registers - - - SPIM0_SPIS0 - 4 - - SPIS - 0x20 - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0x024 - write-only - - - TASKS_ACQUIRE - 0 - 0 - - - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0x028 - write-only - - - TASKS_RELEASE - 0 - 0 - - - - - EVENTS_END - Granted transaction completed - 0x104 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_ACQUIRED - Semaphore acquired - 0x128 - read-write - - - EVENTS_ACQUIRED - 0 - 0 + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + - - - - SHORTS - Shortcut register - 0x200 - read-write - - END_ACQUIRE - Shortcut between END event and ACQUIRE task - 2 - 2 + PIN25 + Set as input pin 25 + 25 + 25 + read - Disabled - Disable shortcut + Input + Read: pin set as input 0 - Enabled - Enable shortcut + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - END - Write '1' to enable interrupt for END event - 1 - 1 + PIN26 + Set as input pin 26 + 26 + 26 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN27 + Set as input pin 27 + 27 + 27 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ACQUIRED - Write '1' to enable interrupt for ACQUIRED event - 10 - 10 + PIN28 + Set as input pin 28 + 28 + 28 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - END - Write '1' to disable interrupt for END event - 1 - 1 + PIN29 + Set as input pin 29 + 29 + 29 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10154,26 +8458,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN30 + Set as input pin 30 + 30 + 30 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10181,26 +8485,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ACQUIRED - Write '1' to disable interrupt for ACQUIRED event - 10 - 10 + PIN31 + Set as input pin 31 + 31 + 31 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10208,7 +8512,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 @@ -10216,1127 +8520,751 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write - SEMSTAT - Semaphore status + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 1 - Free - Semaphore is free + NotLatched + Criteria has not been met 0 - CPU - Semaphore is assigned to CPU + Latched + Criteria has been met 1 + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + - SPIS - Semaphore is assigned to SPI slave - 2 + NotLatched + Criteria has not been met + 0 - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 + Latched + Criteria has been met + 1 - - - - STATUS - Status from last transaction - 0x440 - read-write - - OVERREAD - TX buffer over-read detected, and prevented - 0 - 0 + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 - read - NotPresent - Read: error not present + NotLatched + Criteria has not been met 0 - Present - Read: error present + Latched + Criteria has been met 1 + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 - write - Clear - Write: clear error on writing '1' + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 - read - NotPresent - Read: error not present + NotLatched + Criteria has not been met 0 - Present - Read: error present + Latched + Criteria has been met 1 + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 - write - Clear - Write: clear error on writing '1' + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - - - - ENABLE - Enable SPI slave - 0x500 - read-write - - ENABLE - Enable or disable SPI slave - 0 - 3 + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 - Disabled - Disable SPI slave + NotLatched + Criteria has not been met 0 - Enabled - Enable SPI slave - 2 + Latched + Criteria has been met + 1 - - - - PSEL - Unspecified - SPIS_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 9 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 9 - - - - - - TXD - Unspecified - SPIS_TXD - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 9 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 9 - - - - - - CONFIG - Configuration register - 0x554 - read-write - - ORDER - Bit order - 0 - 0 + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 - MsbFirst - Most significant bit shifted out first + NotLatched + Criteria has not been met 0 - LsbFirst - Least significant bit shifted out first + Latched + Criteria has been met 1 - CPHA - Serial clock (SCK) phase - 1 - 1 + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 - Leading - Sample on leading edge of clock, shift serial data on trailing edge + NotLatched + Criteria has not been met 0 - Trailing - Sample on trailing edge of clock, shift serial data on leading edge + Latched + Criteria has been met 1 - CPOL - Serial clock (SCK) polarity - 2 - 2 + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 - ActiveHigh - Active high + NotLatched + Criteria has not been met 0 - ActiveLow - Active low + Latched + Criteria has been met 1 - - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write - - - DEF - Default character. Character clocked out in case of an ignored transaction. - 0 - 7 - - - - - ORC - Over-read character - 0x5C0 - read-write - - - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. - 0 - 7 - - - - - - - GPIOTE - GPIO Tasks and Events - 0x40006000 - - 0 - 0x1000 - registers - - - GPIOTE - 6 - - GPIOTE - 0x20 - - - 0x8 - 0x4 - TASKS_OUT[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. - 0x000 - write-only - - - TASKS_OUT - 0 - 0 - - - - - 0x8 - 0x4 - TASKS_SET[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 - write-only - - - TASKS_SET - 0 - 0 - - - - - 0x8 - 0x4 - TASKS_CLR[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 - write-only - - - TASKS_CLR - 0 - 0 - - - - - 0x8 - 0x4 - EVENTS_IN[%s] - Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write - - - EVENTS_IN - 0 - 0 - - - - - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write - - - EVENTS_PORT - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - IN0 - Write '1' to enable interrupt for IN[0] event - 0 - 0 + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - IN1 - Write '1' to enable interrupt for IN[1] event - 1 - 1 + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - IN2 - Write '1' to enable interrupt for IN[2] event - 2 - 2 + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - IN3 - Write '1' to enable interrupt for IN[3] event - 3 - 3 + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - IN4 - Write '1' to enable interrupt for IN[4] event - 4 - 4 + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - IN5 - Write '1' to enable interrupt for IN[5] event - 5 - 5 + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 - write - Set - Enable - 1 + NotLatched + Criteria has not been met + 0 - + + Latched + Criteria has been met + 1 + + - IN6 - Write '1' to enable interrupt for IN[6] event - 6 - 6 + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - IN7 - Write '1' to enable interrupt for IN[7] event - 7 - 7 + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - PORT - Write '1' to enable interrupt for PORT event - 31 - 31 + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - IN0 - Write '1' to disable interrupt for IN[0] event - 0 - 0 + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - IN1 - Write '1' to disable interrupt for IN[1] event - 1 - 1 + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - IN2 - Write '1' to disable interrupt for IN[2] event - 2 - 2 + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - IN3 - Write '1' to disable interrupt for IN[3] event - 3 - 3 + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - IN4 - Write '1' to disable interrupt for IN[4] event - 4 - 4 + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - IN5 - Write '1' to disable interrupt for IN[5] event - 5 - 5 + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 + + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write + - IN6 - Write '1' to disable interrupt for IN[6] event - 6 - 6 + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0 + 0 - read - Disabled - Read: Disabled + Default + DETECT directly connected to PIN DETECT signals 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + LDETECT + Use the latched LDETECT behaviour 1 + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + - IN7 - Write '1' to disable interrupt for IN[7] event - 7 - 7 + DIR + Pin direction. Same physical register as DIR register + 0 + 0 - read - Disabled - Read: Disabled + Input + Configure pin as an input pin 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Output + Configure pin as an output pin 1 - PORT - Write '1' to disable interrupt for PORT event - 31 - 31 + INPUT + Connect or disconnect input buffer + 1 + 1 - read - Disabled - Read: Disabled + Connect + Connect input buffer 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Disconnect + Disconnect input buffer 1 - - - - 0x8 - 0x4 - CONFIG[%s] - Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - 0x510 - read-write - - MODE - Mode - 0 - 1 + PULL + Pull configuration + 2 + 3 Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + No pull 0 - Event - Event mode + Pulldown + Pull down on pin 1 - Task - Task mode + Pullup + Pull up on pin 3 - PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + DRIVE + Drive configuration 8 - 12 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 - 17 + 10 - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + S0S1 + Standard '0', standard '1' 0 - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + H0S1 + High drive '0', standard '1' 1 - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + S0H1 + Standard '0', high drive '1' 2 - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + H0H1 + High drive '0', high 'drive '1'' 3 + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 + SENSE + Pin sensing mechanism + 16 + 17 - Low - Task mode: Initial value of pin before task triggering is low + Disabled + Disabled 0 High - Task mode: Initial value of pin before task triggering is high - 1 + Sense for high level + 2 + + + Low + Sense for low level + 3 @@ -11345,583 +9273,642 @@ POSSIBILITY OF SUCH DAMAGE.\n - SAADC - Analog to Digital Converter - 0x40007000 + RADIO + 2.4 GHz Radio + 0x40001000 0 0x1000 registers - SAADC - 7 + RADIO + 1 - SAADC + RADIO 0x20 - TASKS_START - Start the ADC and prepare the result buffer in RAM + TASKS_TXEN + Enable RADIO in TX mode 0x000 write-only - TASKS_START + TASKS_TXEN + Enable RADIO in TX mode 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_SAMPLE - Take one ADC sample, if scan is enabled all channels are sampled + TASKS_RXEN + Enable RADIO in RX mode 0x004 write-only - TASKS_SAMPLE + TASKS_RXEN + Enable RADIO in RX mode 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Stop the ADC and terminate any on-going conversion + TASKS_START + Start RADIO 0x008 write-only - TASKS_STOP + TASKS_START + Start RADIO 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration + TASKS_STOP + Stop RADIO 0x00C write-only - TASKS_CALIBRATEOFFSET + TASKS_STOP + Stop RADIO 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_STARTED - The ADC has started - 0x100 - read-write + TASKS_DISABLE + Disable RADIO + 0x010 + write-only - EVENTS_STARTED + TASKS_DISABLE + Disable RADIO 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_END - The ADC has filled up the Result buffer - 0x104 - read-write + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength. + 0x014 + write-only - EVENTS_END + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength. 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_DONE - A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. - 0x108 - read-write + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only - EVENTS_DONE - 0 - 0 - - - - - EVENTS_RESULTDONE - A result is ready to get transferred to RAM. - 0x10C - read-write - - - EVENTS_RESULTDONE + TASKS_RSSISTOP + Stop the RSSI measurement 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_CALIBRATEDONE - Calibration is complete - 0x110 - read-write + TASKS_BCSTART + Start the bit counter + 0x01C + write-only - EVENTS_CALIBRATEDONE + TASKS_BCSTART + Start the bit counter 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_STOPPED - The ADC has stopped - 0x114 - read-write + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only - EVENTS_STOPPED + TASKS_BCSTOP + Stop the bit counter 0 0 + + + Trigger + Trigger task + 1 + + - - 8 - 0x008 - EVENTS_CH[%s] - Unspecified - SAADC_EVENTS_CH - 0x118 - - LIMITH - Description cluster[n]: Last results is equal or above CH[n].LIMIT.HIGH - 0x000 - read-write - - - LIMITH - 0 - 0 - - - - - LIMITL - Description cluster[n]: Last results is equal or below CH[n].LIMIT.LOW - 0x004 - read-write - - - LIMITL - 0 - 0 - - - - - INTEN - Enable or disable interrupt - 0x300 + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 read-write - STARTED - Enable or disable interrupt for STARTED event + EVENTS_READY + RADIO has ramped up and is ready to be started 0 0 - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - END - Enable or disable interrupt for END event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - DONE - Enable or disable interrupt for DONE event - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RESULTDONE - Enable or disable interrupt for RESULTDONE event - 3 - 3 - - - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + - CALIBRATEDONE - Enable or disable interrupt for CALIBRATEDONE event - 4 - 4 + EVENTS_ADDRESS + Address sent or received + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + - STOPPED - Enable or disable interrupt for STOPPED event - 5 - 5 + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + - CH0LIMITH - Enable or disable interrupt for CH[0].LIMITH event - 6 - 6 + EVENTS_END + Packet sent or received + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + - CH0LIMITL - Enable or disable interrupt for CH[0].LIMITL event - 7 - 7 + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + - CH1LIMITH - Enable or disable interrupt for CH[1].LIMITH event - 8 - 8 + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + - CH1LIMITL - Enable or disable interrupt for CH[1].LIMITL event - 9 - 9 + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete. + 0x11C + read-write + - CH2LIMITH - Enable or disable interrupt for CH[2].LIMITH event - 10 - 10 + EVENTS_RSSIEND + Sampling of receive signal strength complete. + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_BCMATCH + Bit counter reached bit count value. + 0x128 + read-write + - CH2LIMITL - Enable or disable interrupt for CH[2].LIMITL event - 11 - 11 + EVENTS_BCMATCH + Bit counter reached bit count value. + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + - CH3LIMITH - Enable or disable interrupt for CH[3].LIMITH event - 12 - 12 + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + - CH3LIMITL - Enable or disable interrupt for CH[3].LIMITL event - 13 - 13 + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH4LIMITH - Enable or disable interrupt for CH[4].LIMITH event - 14 - 14 + READY_START + Shortcut between event READY and task START + 0 + 0 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH4LIMITL - Enable or disable interrupt for CH[4].LIMITL event - 15 - 15 + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH5LIMITH - Enable or disable interrupt for CH[5].LIMITH event - 16 - 16 + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH5LIMITL - Enable or disable interrupt for CH[5].LIMITL event - 17 - 17 + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH6LIMITH - Enable or disable interrupt for CH[6].LIMITH event - 18 - 18 + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH6LIMITL - Enable or disable interrupt for CH[6].LIMITL event - 19 - 19 + END_START + Shortcut between event END and task START + 5 + 5 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH7LIMITH - Enable or disable interrupt for CH[7].LIMITH event - 20 - 20 + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - CH7LIMITL - Enable or disable interrupt for CH[7].LIMITL event - 21 - 21 + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 @@ -11935,8 +9922,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - STARTED - Write '1' to enable interrupt for STARTED event + READY + Write '1' to enable interrupt for event READY 0 0 @@ -11962,8 +9949,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - END - Write '1' to enable interrupt for END event + ADDRESS + Write '1' to enable interrupt for event ADDRESS 1 1 @@ -11989,8 +9976,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - DONE - Write '1' to enable interrupt for DONE event + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD 2 2 @@ -12016,8 +10003,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - RESULTDONE - Write '1' to enable interrupt for RESULTDONE event + END + Write '1' to enable interrupt for event END 3 3 @@ -12043,8 +10030,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - CALIBRATEDONE - Write '1' to enable interrupt for CALIBRATEDONE event + DISABLED + Write '1' to enable interrupt for event DISABLED 4 4 @@ -12070,8 +10057,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to enable interrupt for STOPPED event + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH 5 5 @@ -12097,8 +10084,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH0LIMITH - Write '1' to enable interrupt for CH[0].LIMITH event + DEVMISS + Write '1' to enable interrupt for event DEVMISS 6 6 @@ -12124,8 +10111,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH0LIMITL - Write '1' to enable interrupt for CH[0].LIMITL event + RSSIEND + Write '1' to enable interrupt for event RSSIEND 7 7 @@ -12151,10 +10138,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH1LIMITH - Write '1' to enable interrupt for CH[1].LIMITH event - 8 - 8 + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 read @@ -12178,10 +10165,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH1LIMITL - Write '1' to enable interrupt for CH[1].LIMITL event - 9 - 9 + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 read @@ -12205,10 +10192,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH2LIMITH - Write '1' to enable interrupt for CH[2].LIMITH event - 10 - 10 + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 read @@ -12231,11 +10218,19 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH2LIMITL - Write '1' to enable interrupt for CH[2].LIMITL event - 11 - 11 + READY + Write '1' to disable interrupt for event READY + 0 + 0 read @@ -12252,17 +10247,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH3LIMITH - Write '1' to enable interrupt for CH[3].LIMITH event - 12 - 12 + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 read @@ -12279,17 +10274,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH3LIMITL - Write '1' to enable interrupt for CH[3].LIMITL event - 13 - 13 + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 read @@ -12306,17 +10301,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH4LIMITH - Write '1' to enable interrupt for CH[4].LIMITH event - 14 - 14 + END + Write '1' to disable interrupt for event END + 3 + 3 read @@ -12333,17 +10328,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH4LIMITL - Write '1' to enable interrupt for CH[4].LIMITL event - 15 - 15 + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 read @@ -12360,17 +10355,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH5LIMITH - Write '1' to enable interrupt for CH[5].LIMITH event - 16 - 16 + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 read @@ -12387,17 +10382,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH5LIMITL - Write '1' to enable interrupt for CH[5].LIMITL event - 17 - 17 + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 read @@ -12414,17 +10409,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH6LIMITH - Write '1' to enable interrupt for CH[6].LIMITH event - 18 - 18 + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 read @@ -12441,17 +10436,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH6LIMITL - Write '1' to enable interrupt for CH[6].LIMITL event - 19 - 19 + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 read @@ -12468,17 +10463,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH7LIMITH - Write '1' to enable interrupt for CH[7].LIMITH event - 20 - 20 + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 read @@ -12495,17 +10490,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CH7LIMITL - Write '1' to enable interrupt for CH[7].LIMITL event - 21 - 21 + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 read @@ -12522,8 +10517,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 @@ -12531,601 +10526,652 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 - read-write + CRCSTATUS + CRC status + 0x400 + read-only - STARTED - Write '1' to disable interrupt for STARTED event + CRCSTATUS + CRC status of packet received 0 0 - read - Disabled - Read: Disabled + CRCError + Packet received with CRC error 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + CRCOk + Packet received with CRC ok 1 + + + + RXMATCH + Received address + 0x408 + read-only + - END - Write '1' to disable interrupt for END event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + RXMATCH + Received address + 0 + 2 + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + - DONE - Write '1' to disable interrupt for DONE event - 2 + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + + + + PACKETPTR + Packet pointer + 0x504 + read-write + - RESULTDONE - Write '1' to disable interrupt for RESULTDONE event - 3 - 3 + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 - read - Disabled - Read: Disabled + Default + Channel map between 2400 MHZ .. 2500 MHz 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Low + Channel map between 2360 MHZ .. 2460 MHz 1 + + + + TXPOWER + Output power + 0x50C + read-write + - CALIBRATEDONE - Write '1' to disable interrupt for CALIBRATEDONE event - 4 - 4 + TXPOWER + RADIO output power. + 0 + 7 - read - Disabled - Read: Disabled - 0 + Pos4dBm + +4 dBm + 0x04 - Enabled - Read: Enabled - 1 + Pos3dBm + +3 dBm + 0x03 - - - write - Clear - Disable - 1 + 0dBm + 0 dBm + 0x00 - - - - STOPPED - Write '1' to disable interrupt for STOPPED event - 5 - 5 - - read - Disabled - Read: Disabled - 0 + Neg4dBm + -4 dBm + 0xFC - Enabled - Read: Enabled - 1 + Neg8dBm + -8 dBm + 0xF8 - - - write - Clear - Disable - 1 + Neg12dBm + -12 dBm + 0xF4 - - - - CH0LIMITH - Write '1' to disable interrupt for CH[0].LIMITH event - 6 - 6 - - read - Disabled - Read: Disabled - 0 + Neg16dBm + -16 dBm + 0xF0 - Enabled - Read: Enabled - 1 + Neg20dBm + -20 dBm + 0xEC - - - write - Clear - Disable - 1 + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + MODE + Data rate and modulation + 0x510 + read-write + - CH0LIMITL - Write '1' to disable interrupt for CH[0].LIMITL event - 7 - 7 + MODE + Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. + 0 + 3 - read - Disabled - Read: Disabled + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode 0 - Enabled - Read: Enabled + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode 1 - - - write - Clear - Disable - 1 + Ble_1Mbit + 1 Mbit/s Bluetooth Low Energy + 3 + + + Ble_2Mbit + 2 Mbit/s Bluetooth Low Energy + 4 + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + - CH1LIMITH - Write '1' to disable interrupt for CH[1].LIMITH event + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. 8 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - CH1LIMITL - Write '1' to disable interrupt for CH[1].LIMITL event - 9 - 9 + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 - read - Disabled - Read: Disabled + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Include + Always include S1 field in RAM independent of S1LEN 1 - CH2LIMITH - Write '1' to disable interrupt for CH[2].LIMITH event - 10 - 10 + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 24 - read - Disabled - Read: Disabled + 8bit + 8-bit preamble 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + 16bit + 16-bit preamble 1 + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + - CH2LIMITL - Write '1' to disable interrupt for CH[2].LIMITL event - 11 - 11 + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 - read - Disabled - Read: Disabled + Little + Least Significant bit on air first 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Big + Most significant bit on air first 1 - CH3LIMITH - Write '1' to disable interrupt for CH[3].LIMITH event - 12 - 12 + WHITEEN + Enable or disable packet whitening + 25 + 25 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 + + + + BASE0 + Base address 0 + 0x51C + read-write + - CH3LIMITL - Write '1' to disable interrupt for CH[3].LIMITL event - 13 - 13 + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH4LIMITH - Write '1' to disable interrupt for CH[4].LIMITH event - 14 - 14 + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH4LIMITL - Write '1' to disable interrupt for CH[4].LIMITL event - 15 - 15 + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH5LIMITH - Write '1' to disable interrupt for CH[5].LIMITH event - 16 - 16 + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH5LIMITL - Write '1' to disable interrupt for CH[5].LIMITL event - 17 - 17 + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH6LIMITH - Write '1' to disable interrupt for CH[6].LIMITH event - 18 - 18 + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 - CH6LIMITL - Write '1' to disable interrupt for CH[6].LIMITL event - 19 - 19 + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 + + + + CRCCNF + CRC configuration + 0x534 + read-write + - CH7LIMITH - Write '1' to disable interrupt for CH[7].LIMITH event - 20 - 20 + LEN + CRC length in number of bytes. + 0 + 1 - read Disabled - Read: Disabled + CRC length is zero and CRC calculation is disabled 0 - Enabled - Read: Enabled + One + CRC length is one byte and CRC calculation is enabled 1 - - - write - Clear - Disable - 1 + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 - CH7LIMITL - Write '1' to disable interrupt for CH[7].LIMITL event - 21 - 21 + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 8 - read - Disabled - Read: Disabled + Include + CRC calculation includes address field 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. 1 @@ -13133,560 +11179,5491 @@ POSSIBILITY OF SUCH DAMAGE.\n - STATUS - Status - 0x400 + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Inter Frame Spacing in us + 0x544 + read-write + + + TIFS + Inter Frame Spacing in us + 0 + 7 + + + + + RSSISAMPLE + RSSI sample + 0x548 read-only - STATUS - Status + RSSISAMPLE + RSSI sample 0 - 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 - Ready - ADC is ready. No on-going conversion. + Disabled + RADIO is in the Disabled state 0 - Busy - ADC is busy. Conversion in progress. + RxRu + RADIO is in the RXRU state 1 + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + - ENABLE - Enable or disable ADC - 0x500 + DATAWHITEIV + Data whitening initial value + 0x554 read-write + 0x00000040 - ENABLE - Enable or disable ADC + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 0 0 Disabled - Disable ADC + Disabled 0 Enabled - Enable ADC + Enabled 1 - - - - 8 - 0x010 - CH[%s] + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + UARTE0 + UART with EasyDMA + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source Note : this register is read / write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL Unspecified - SAADC_CH - 0x510 + UARTE_PSEL + read-write + 0x508 - PSELP - Description cluster[n]: Input positive pin selection for CH[n] + RTS + Pin select for RTS signal 0x000 read-write - 0x00000000 + 0xFFFFFFFF - PSELP - Analog positive input channel + PIN + Pin number 0 4 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 + Disconnected + Disconnect 1 - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 + Connected + Connect + 0 + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + - AnalogInput3 - AIN3 - 4 + Disconnected + Disconnect + 1 - AnalogInput4 - AIN4 - 5 + Connected + Connect + 0 + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + - AnalogInput5 - AIN5 - 6 + Disconnected + Disconnect + 1 - AnalogInput6 - AIN6 - 7 + Connected + Connect + 0 + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + - AnalogInput7 - AIN7 - 8 + Disconnected + Disconnect + 1 - VDD - VDD - 9 + Connected + Connect + 0 + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + TWI0 + I2C compatible Two-Wire Interface + 0x40003000 + TWI + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 - PSELN - Description cluster[n]: Input negative pin selection for CH[n] - 0x004 + SCL + Pin select for SCL + 0x000 read-write - 0x00000000 + 0xFFFFFFFF - PSELN - Analog negative input, enables differential channel + PIN + Pin number 0 4 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 + Disconnected + Disconnect 1 - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 + Connected + Connect + 0 - CONFIG - Description cluster[n]: Input configuration for CH[n] - 0x008 + SDA + Pin select for SDA + 0x004 read-write - 0x00020000 + 0xFFFFFFFF - RESP - Positive channel resistor control + PIN + Pin number 0 - 1 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - RESN - Negative channel resistor control - 4 - 5 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - - - GAIN - Gain control - 8 - 10 - - - Gain1_6 - 1/6 - 0 - - - Gain1_5 - 1/5 - 1 - - - Gain1_4 - 1/4 - 2 - - - Gain1_3 - 1/3 - 3 - - - Gain1_2 - 1/2 - 4 - - - Gain1 - 1 - 5 - - - Gain2 - 2 - 6 - - - Gain4 - 4 - 7 - - - - - REFSEL - Reference control - 12 - 12 - - - Internal - Internal reference (0.6 V) - 0 - - - VDD1_4 - VDD/4 as reference - 1 - - - - - TACQ - Acquisition time, the time the ADC uses to sample the input voltage - 16 - 18 - - - 3us - 3 us - 0 - - - 5us - 5 us - 1 - - - 10us - 10 us - 2 - - - 15us - 15 us - 3 - - - 20us - 20 us - 4 - - - 40us - 40 us - 5 - - + 4 - MODE - Enable differential mode - 20 - 20 + CONNECT + Connection + 31 + 31 - SE - Single ended, PSELN will be ignored, negative input to ADC shorted to GND - 0 - - - Diff - Differential + Disconnected + Disconnect 1 - - - - BURST - Enable burst mode - 24 - 24 - - Disabled - Burst mode is disabled (normal operation) + Connected + Connect 0 - - Enabled - Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 - - - LIMIT - Description cluster[n]: High/low limits for event monitoring a channel - 0x00C - read-write - 0x7FFF8000 - - - LOW - Low level limit - 0 - 15 - - - HIGH - High level limit - 16 - 31 - - - - RESOLUTION - Resolution configuration - 0x5F0 + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA + 0x40003000 + TWI0 + TWIM + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 read-write - 0x00000001 - VAL - Set the resolution - 0 - 2 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + read - 8bit - 8 bit + Disabled + Read: Disabled 0 - 10bit - 10 bit + Enabled + Read: Enabled 1 + + + write - 12bit - 12 bit - 2 + Set + Enable + 1 + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read - 14bit - 14 bit - 3 + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 - OVERSAMPLE - Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - 0x5F4 + INTENCLR + Disable interrupt + 0x308 read-write - OVERSAMPLE - Oversample control - 0 - 3 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + read - Bypass - Bypass oversampling + Disabled + Read: Disabled 0 - Over2x - Oversample 2x + Enabled + Read: Enabled 1 + + + write - Over4x - Oversample 4x - 2 + Clear + Disable + 1 + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read - Over8x - Oversample 8x - 3 + Disabled + Read: Disabled + 0 - Over16x - Oversample 16x - 4 + Enabled + Read: Enabled + 1 + + + write - Over32x - Oversample 32x - 5 + Clear + Disable + 1 + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read - Over64x - Oversample 64x - 6 + Disabled + Read: Disabled + 0 - Over128x - Oversample 128x - 7 + Enabled + Read: Enabled + 1 + + + write - Over256x - Oversample 256x - 8 + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 - SAMPLERATE - Controls normal or continuous sample rate - 0x5F8 + ERRORSRC + Error source + 0x4C4 read-write + oneToClear - CC - Capture and compare value. Sample rate is 16 MHz/CC + OVERRUN + Overrun error 0 - 10 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + - MODE - Select mode for sample rate control - 12 - 12 + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 - Task - Rate is controlled from SAMPLE task + NotReceived + Error did not occur 0 - Timers - Rate is controlled from local timer (use CC to control the rate) + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred 1 + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + - RESULT - RESULT EasyDMA channel - SAADC_RESULT - 0x62C + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 PTR Data pointer @@ -13703,365 +16680,1294 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXCNT - Maximum number of buffer words to transfer + Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT - Maximum number of buffer words to transfer + Maximum number of bytes in transmit buffer 0 - 14 + 9 AMOUNT - Number of buffer words transferred since last START + Number of bytes transferred in the last transaction 0x008 read-only AMOUNT - Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 - 14 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + - TIMER0 - Timer/Counter 0 - 0x40008000 - TIMER + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA + 0x40003000 + TWI0 + TWIS 0 0x1000 registers - TIMER0 - 8 + TWIM0_TWIS0_TWI0 + 3 - TIMER + TWIS 0x20 - TASKS_START - Start Timer - 0x000 + TASKS_STOP + Stop TWI transaction + 0x014 write-only - TASKS_START + TASKS_STOP + Stop TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Stop Timer - 0x004 + TASKS_SUSPEND + Suspend TWI transaction + 0x01C write-only - TASKS_STOP + TASKS_SUSPEND + Suspend TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 + TASKS_RESUME + Resume TWI transaction + 0x020 write-only - TASKS_COUNT + TASKS_RESUME + Resume TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_CLEAR - Clear time - 0x00C + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 write-only - TASKS_CLEAR + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 write-only - TASKS_SHUTDOWN + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - 0x6 - 0x4 - TASKS_CAPTURE[%s] - Description collection[n]: Capture Timer value to CC[n] register - 0x040 - write-only - - TASKS_CAPTURE - 0 - 0 + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - 0x6 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 - read-write - - EVENTS_COMPARE - 0 - 0 + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - SHORTS - Shortcut register - 0x200 + INTENCLR + Disable interrupt + 0x308 read-write - COMPARE0_CLEAR - Shortcut between COMPARE[0] event and CLEAR task - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE1_CLEAR - Shortcut between COMPARE[1] event and CLEAR task - 1 - 1 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE2_CLEAR - Shortcut between COMPARE[2] event and CLEAR task - 2 - 2 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE3_CLEAR - Shortcut between COMPARE[3] event and CLEAR task - 3 - 3 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE4_CLEAR - Shortcut between COMPARE[4] event and CLEAR task - 4 - 4 + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE5_CLEAR - Shortcut between COMPARE[5] event and CLEAR task - 5 - 5 + READ + Write '1' to disable interrupt for event READ + 26 + 26 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + - COMPARE0_STOP - Shortcut between COMPARE[0] event and STOP task - 8 - 8 + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Which of the addresses in {ADDRESS} matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 Disabled - Disable shortcut + Disable TWIS 0 Enabled - Enable shortcut - 1 + Enable TWIS + 9 + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + - COMPARE1_STOP - Shortcut between COMPARE[1] event and STOP task - 9 - 9 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - + ADDRESS + TWI slave address + 0 + 6 + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + - COMPARE2_STOP - Shortcut between COMPARE[2] event and STOP task - 10 - 10 + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 Disabled - Disable shortcut + Disabled 0 Enabled - Enable shortcut + Enabled 1 - COMPARE3_STOP - Shortcut between COMPARE[3] event and STOP task - 11 - 11 + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 Disabled - Disable shortcut + Disabled 0 Enabled - Enable shortcut + Enabled 1 + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + - COMPARE4_STOP - Shortcut between COMPARE[4] event and STOP task - 12 - 12 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + SPI0 + Serial Peripheral Interface + 0x40004000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_SPI0 + 4 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + - COMPARE5_STOP - Shortcut between COMPARE[5] event and STOP task - 13 - 13 + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 - Disabled - Disable shortcut + NotGenerated + Event not generated 0 - Enabled - Enable shortcut + Generated + Event generated 1 @@ -14075,145 +17981,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE4 - Write '1' to enable interrupt for COMPARE[4] event - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - COMPARE5 - Write '1' to enable interrupt for COMPARE[5] event - 21 - 21 + READY + Write '1' to enable interrupt for event READY + 2 + 2 read @@ -14245,10 +18016,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 + READY + Write '1' to disable interrupt for event READY + 2 + 2 read @@ -14271,407 +18042,552 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + ENABLE + Enable SPI + 0x500 + read-write + - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 + ENABLE + Enable or disable SPI + 0 + 3 - read Disabled - Read: Disabled + Disable SPI 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable SPI 1 + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + TXD + TX data to send. Double buffered + 0 + 7 + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + FREQUENCY + SPI master data rate + 0 + 31 - write - Clear - Disable - 1 + K125 + 125 kbps + 0x02000000 - - - - COMPARE4 - Write '1' to disable interrupt for COMPARE[4] event - 20 - 20 - - read - Disabled - Read: Disabled - 0 + K250 + 250 kbps + 0x04000000 - Enabled - Read: Enabled - 1 + K500 + 500 kbps + 0x08000000 - - - write - Clear - Disable - 1 + M1 + 1 Mbps + 0x10000000 - - - - COMPARE5 - Write '1' to disable interrupt for COMPARE[5] event - 21 - 21 - - read - Disabled - Read: Disabled - 0 + M2 + 2 Mbps + 0x20000000 - Enabled - Read: Enabled - 1 + M4 + 4 Mbps + 0x40000000 - - - write - Clear - Disable - 1 + M8 + 8 Mbps + 0x80000000 - MODE - Timer mode selection - 0x504 + CONFIG + Configuration register + 0x554 read-write - MODE - Timer mode + ORDER + Bit order 0 - 1 + 0 - Timer - Select Timer mode + MsbFirst + Most significant bit shifted out first 0 - Counter - Deprecated enumerator - Select Counter mode + LsbFirst + Least significant bit shifted out first 1 - - LowPowerCounter - Select Low Power Counter mode - 2 - - - - - BITMODE - Configure the number of bits used by the TIMER - 0x508 - read-write - - BITMODE - Timer bit width - 0 + CPHA + Serial clock (SCK) phase + 1 1 - 16Bit - 16 bit timer bit width + Leading + Sample on leading edge of clock, shift serial data on trailing edge 0 - 08Bit - 8 bit timer bit width + Trailing + Sample on trailing edge of clock, shift serial data on leading edge 1 + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + - 24Bit - 24 bit timer bit width - 2 + ActiveHigh + Active high + 0 - 32Bit - 32 bit timer bit width - 3 + ActiveLow + Active low + 1 - - PRESCALER - Timer prescaler register - 0x510 - read-write - 0x00000004 - - - PRESCALER - Prescaler value - 0 - 3 - - - - - 0x6 - 0x4 - CC[%s] - Description collection[n]: Capture/Compare register n - 0x540 - read-write - - - CC - Capture/Compare value - 0 - 31 - - - - - TIMER1 - Timer/Counter 1 - 0x40009000 - - TIMER1 - 9 - - - - TIMER2 - Timer/Counter 2 - 0x4000A000 - - TIMER2 - 10 - - - RTC0 - Real time counter 0 - 0x4000B000 - RTC + SPIM0 + Serial Peripheral Interface Master with EasyDMA + 0x40004000 + SPI0 + SPIM 0 0x1000 registers - RTC0 - 11 + SPIM0_SPIS0_SPI0 + 4 - RTC + SPIM 0x20 TASKS_START - Start RTC COUNTER - 0x000 + Start SPI transaction + 0x010 write-only TASKS_START + Start SPI transaction 0 0 + + + Trigger + Trigger task + 1 + + TASKS_STOP - Stop RTC COUNTER - 0x004 + Stop SPI transaction + 0x014 write-only TASKS_STOP + Stop SPI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_CLEAR - Clear RTC COUNTER - 0x008 + TASKS_SUSPEND + Suspend SPI transaction + 0x01C write-only - TASKS_CLEAR + TASKS_SUSPEND + Suspend SPI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_TRIGOVRFLW - Set COUNTER to 0xFFFFF0 - 0x00C + TASKS_RESUME + Resume SPI transaction + 0x020 write-only - TASKS_TRIGOVRFLW + TASKS_RESUME + Resume SPI transaction 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_TICK - Event on COUNTER increment - 0x100 + EVENTS_STOPPED + SPI transaction has stopped + 0x104 read-write - EVENTS_TICK + EVENTS_STOPPED + SPI transaction has stopped 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_OVRFLW - Event on COUNTER overflow - 0x104 + EVENTS_ENDRX + End of RXD buffer reached + 0x110 read-write - EVENTS_OVRFLW + EVENTS_ENDRX + End of RXD buffer reached 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - 0x4 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 read-write - EVENTS_COMPARE + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_STARTED + Transaction started + 0x14C read-write - TICK - Write '1' to enable interrupt for TICK event + EVENTS_STARTED + Transaction started 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 - write - Set - Enable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - OVRFLW - Write '1' to enable interrupt for OVRFLW event + STOPPED + Write '1' to enable interrupt for event STOPPED 1 1 @@ -14697,10 +18613,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read @@ -14724,10 +18640,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 + END + Write '1' to enable interrupt for event END + 6 + 6 read @@ -14751,10 +18667,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 read @@ -14778,8 +18694,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event + STARTED + Write '1' to enable interrupt for event STARTED 19 19 @@ -14813,10 +18729,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - TICK - Write '1' to disable interrupt for TICK event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read @@ -14840,10 +18756,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - OVRFLW - Write '1' to disable interrupt for OVRFLW event - 1 - 1 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read @@ -14867,10 +18783,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 + END + Write '1' to disable interrupt for event END + 6 + 6 read @@ -14894,10 +18810,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 read @@ -14921,10 +18837,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 read @@ -14947,315 +18863,526 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + ENABLE + Enable SPIM + 0x500 + read-write + - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 + ENABLE + Enable or disable SPIM + 0 + 3 - read Disabled - Read: Disabled + Disable SPIM 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable SPIM + 7 + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + - EVTEN - Enable or disable event routing - 0x340 + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 read-write + 0x04000000 - TICK - Enable or disable event routing for TICK event + FREQUENCY + SPI master data rate 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - OVRFLW - Enable or disable event routing for OVRFLW event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - COMPARE0 - Enable or disable event routing for COMPARE[0] event - 16 - 16 + 31 - Disabled - Disable - 0 - - - Enabled - Enable - 1 + K125 + 125 kbps + 0x02000000 - - - - COMPARE1 - Enable or disable event routing for COMPARE[1] event - 17 - 17 - - Disabled - Disable - 0 + K250 + 250 kbps + 0x04000000 - Enabled - Enable - 1 + K500 + 500 kbps + 0x08000000 - - - - COMPARE2 - Enable or disable event routing for COMPARE[2] event - 18 - 18 - - Disabled - Disable - 0 + M1 + 1 Mbps + 0x10000000 - Enabled - Enable - 1 + M2 + 2 Mbps + 0x20000000 - - - - COMPARE3 - Enable or disable event routing for COMPARE[3] event - 19 - 19 - - Disabled - Disable - 0 + M4 + 4 Mbps + 0x40000000 - Enabled - Enable - 1 + M8 + 8 Mbps + 0x80000000 + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + - EVTENSET - Enable event routing - 0x344 + CONFIG + Configuration register + 0x554 read-write - TICK - Write '1' to enable event routing for TICK event + ORDER + Bit order 0 0 - read - Disabled - Read: Disabled + MsbFirst + Most significant bit shifted out first 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + LsbFirst + Least significant bit shifted out first 1 - OVRFLW - Write '1' to enable event routing for OVRFLW event + CPHA + Serial clock (SCK) phase 1 1 - read - Disabled - Read: Disabled + Leading + Sample on leading edge of clock, shift serial data on trailing edge 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Trailing + Sample on trailing edge of clock, shift serial data on leading edge 1 - COMPARE0 - Write '1' to enable event routing for COMPARE[0] event - 16 - 16 + CPOL + Serial clock (SCK) polarity + 2 + 2 - read - Disabled - Read: Disabled + ActiveHigh + Active high 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + ActiveLow + Active low 1 + + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0x5C0 + read-write + - COMPARE1 - Write '1' to enable event routing for COMPARE[1] event - 17 - 17 + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS0 + SPI Slave + 0x40004000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_SPI0 + 4 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + - COMPARE2 - Write '1' to enable event routing for COMPARE[2] event - 18 - 18 + EVENTS_END + Granted transaction completed + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + - COMPARE3 - Write '1' to enable event routing for COMPARE[3] event - 19 - 19 + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 @@ -15263,70 +19390,68 @@ POSSIBILITY OF SUCH DAMAGE.\n - EVTENCLR - Disable event routing - 0x348 + EVENTS_ACQUIRED + Semaphore acquired + 0x128 read-write - TICK - Write '1' to disable event routing for TICK event + EVENTS_ACQUIRED + Semaphore acquired 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - OVRFLW - Write '1' to disable event routing for OVRFLW event - 1 - 1 + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - COMPARE0 - Write '1' to disable event routing for COMPARE[0] event - 16 - 16 + END + Write '1' to enable interrupt for event END + 1 + 1 read @@ -15343,17 +19468,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - COMPARE1 - Write '1' to disable event routing for COMPARE[1] event - 17 - 17 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read @@ -15370,17 +19495,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - COMPARE2 - Write '1' to disable event routing for COMPARE[2] event - 18 - 18 + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 read @@ -15397,17 +19522,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - COMPARE3 - Write '1' to disable event routing for COMPARE[3] event - 19 - 19 + END + Write '1' to disable interrupt for event END + 1 + 1 read @@ -15430,120 +19563,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - COUNTER - Current COUNTER value - 0x504 - read-only - - - COUNTER - Counter value - 0 - 23 - - - - - PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped - 0x508 - read-write - - - PRESCALER - Prescaler value - 0 - 11 - - - - - 0x4 - 0x4 - CC[%s] - Description collection[n]: Compare register n - 0x540 - read-write - - - COMPARE - Compare value - 0 - 23 - - - - - - - TEMP - Temperature Sensor - 0x4000C000 - - 0 - 0x1000 - registers - - - TEMP - 12 - - TEMP - 0x20 - - - TASKS_START - Start temperature measurement - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop temperature measurement - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0x100 - read-write - - - EVENTS_DATARDY - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - DATARDY - Write '1' to enable interrupt for DATARDY event - 0 - 0 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read @@ -15560,25 +19584,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - DATARDY - Write '1' to disable interrupt for DATARDY event - 0 - 0 + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 read @@ -15604,387 +19620,98 @@ POSSIBILITY OF SUCH DAMAGE.\n - TEMP - Temperature in degC (0.25deg steps) - 0x508 + SEMSTAT + Semaphore status register + 0x400 read-only - int32_t - - - TEMP - Temperature in degC (0.25deg steps) - 0 - 31 - - - - - A0 - Slope of 1st piece wise linear function - 0x520 - read-write - 0x00000326 - - - A0 - Slope of 1st piece wise linear function - 0 - 11 - - - - - A1 - Slope of 2nd piece wise linear function - 0x524 - read-write - 0x00000348 - - - A1 - Slope of 2nd piece wise linear function - 0 - 11 - - - - - A2 - Slope of 3rd piece wise linear function - 0x528 - read-write - 0x000003AA - - - A2 - Slope of 3rd piece wise linear function - 0 - 11 - - - - - A3 - Slope of 4th piece wise linear function - 0x52C - read-write - 0x0000040E - - - A3 - Slope of 4th piece wise linear function - 0 - 11 - - - - - A4 - Slope of 5th piece wise linear function - 0x530 - read-write - 0x000004BD - - - A4 - Slope of 5th piece wise linear function - 0 - 11 - - - - - A5 - Slope of 6th piece wise linear function - 0x534 - read-write - 0x000005A3 - - - A5 - Slope of 6th piece wise linear function - 0 - 11 - - - - - B0 - y-intercept of 1st piece wise linear function - 0x540 - read-write - 0x00003FEF - - - B0 - y-intercept of 1st piece wise linear function - 0 - 13 - - - - - B1 - y-intercept of 2nd piece wise linear function - 0x544 - read-write - 0x00003FBE - - - B1 - y-intercept of 2nd piece wise linear function - 0 - 13 - - - - - B2 - y-intercept of 3rd piece wise linear function - 0x548 - read-write - 0x00003FBE - - - B2 - y-intercept of 3rd piece wise linear function - 0 - 13 - - - - - B3 - y-intercept of 4th piece wise linear function - 0x54C - read-write - 0x00000012 - - - B3 - y-intercept of 4th piece wise linear function - 0 - 13 - - - - - B4 - y-intercept of 5th piece wise linear function - 0x550 - read-write - 0x00000124 - - - B4 - y-intercept of 5th piece wise linear function - 0 - 13 - - - - - B5 - y-intercept of 6th piece wise linear function - 0x554 - read-write - 0x0000027C - - - B5 - y-intercept of 6th piece wise linear function - 0 - 13 - - - - - T0 - End point of 1st piece wise linear function - 0x560 - read-write - 0x000000E2 - - - T0 - End point of 1st piece wise linear function - 0 - 7 - - - - - T1 - End point of 2nd piece wise linear function - 0x564 - read-write - 0x00000000 - - - T1 - End point of 2nd piece wise linear function - 0 - 7 - - - - - T2 - End point of 3rd piece wise linear function - 0x568 - read-write - 0x00000019 - - - T2 - End point of 3rd piece wise linear function - 0 - 7 - - - - - T3 - End point of 4th piece wise linear function - 0x56C - read-write - 0x0000003C - - - T3 - End point of 4th piece wise linear function - 0 - 7 - - - - - T4 - End point of 5th piece wise linear function - 0x570 - read-write - 0x00000050 - - - T4 - End point of 5th piece wise linear function - 0 - 7 - - - - - - - RNG - Random Number Generator - 0x4000D000 - - 0 - 0x1000 - registers - - - RNG - 13 - - RNG - 0x20 - - - TASKS_START - Task starting the random number generator - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Task stopping the random number generator - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0x100 - read-write + 0x00000001 - EVENTS_VALRDY + SEMSTAT + Semaphore status 0 - 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + - SHORTS - Shortcut register - 0x200 + STATUS + Status from last transaction + 0x440 read-write - VALRDY_STOP - Shortcut between VALRDY event and STOP task + OVERREAD + TX buffer over-read detected, and prevented 0 0 + read - Disabled - Disable shortcut + NotPresent + Read: error not present 0 - Enabled - Enable shortcut + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - VALRDY - Write '1' to enable interrupt for VALRDY event - 0 - 0 + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled + Present + Read: error present 1 write - Set - Enable + Clear + Write: clear error on writing '1' 1 @@ -15992,60 +19719,376 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + ENABLE + Enable SPI slave + 0x500 read-write - VALRDY - Write '1' to disable interrupt for VALRDY event + ENABLE + Enable or disable SPI slave 0 - 0 + 3 - read Disabled - Read: Disabled + Disable SPI slave 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 + Enable SPI slave + 2 + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 9 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + CONFIG Configuration register - 0x504 + 0x554 read-write - DERCEN - Bias correction + ORDER + Bit order 0 0 - Disabled - Disabled + MsbFirst + Most significant bit shifted out first 0 - Enabled - Enabled + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low 1 @@ -16053,14 +20096,28 @@ POSSIBILITY OF SUCH DAMAGE.\n - VALUE - Output random number - 0x508 - read-only + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write - VALUE - Generated random number + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 @@ -16069,70 +20126,141 @@ POSSIBILITY OF SUCH DAMAGE.\n - ECB - AES ECB Mode Encryption - 0x4000E000 + GPIOTE + GPIO Tasks and Events + 0x40006000 0 0x1000 registers - ECB - 14 + GPIOTE + 6 - ECB + GPIOTE 0x20 - TASKS_STARTECB - Start ECB block encrypt + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only - TASKS_STARTECB + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOPECB - Abort a possible executing ECB operation - 0x004 + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 write-only - TASKS_STOPECB + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_ENDECB - ECB block encrypt complete + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write - EVENTS_ENDECB + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0x104 + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C read-write - EVENTS_ERRORECB + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -16143,8 +20271,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - ENDECB - Write '1' to enable interrupt for ENDECB event + IN0 + Write '1' to enable interrupt for event IN[0] 0 0 @@ -16170,8 +20298,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERRORECB - Write '1' to enable interrupt for ERRORECB event + IN1 + Write '1' to enable interrupt for event IN[1] 1 1 @@ -16196,19 +20324,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - ENDECB - Write '1' to disable interrupt for ENDECB event - 0 - 0 + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 read @@ -16225,17 +20345,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ERRORECB - Write '1' to disable interrupt for ERRORECB event - 1 - 1 + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 read @@ -16252,122 +20372,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - ECBDATAPTR - ECB block encrypt memory pointers - 0x504 - read-write - - - ECBDATAPTR - Pointer to the ECB data structure (see Table 1 ECB data structure overview) - 0 - 31 - - - - - - - AAR - Accelerated Address Resolver - 0x4000F000 - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - AAR - 0x20 - - - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop resolving addresses - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_END - Address resolution procedure complete - 0x100 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_RESOLVED - Address resolved - 0x104 - read-write - - - EVENTS_RESOLVED - 0 - 0 - - - - - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write - - - EVENTS_NOTRESOLVED - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - END - Write '1' to enable interrupt for END event - 0 - 0 + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 read @@ -16391,10 +20406,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - RESOLVED - Write '1' to enable interrupt for RESOLVED event - 1 - 1 + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 read @@ -16418,10 +20433,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - NOTRESOLVED - Write '1' to enable interrupt for NOTRESOLVED event - 2 - 2 + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 read @@ -16444,19 +20459,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - END - Write '1' to disable interrupt for END event - 0 - 0 + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 read @@ -16473,17 +20480,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - RESOLVED - Write '1' to disable interrupt for RESOLVED event - 1 - 1 + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 read @@ -16500,17 +20507,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - NOTRESOLVED - Write '1' to disable interrupt for NOTRESOLVED event - 2 - 2 + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 read @@ -16533,252 +20548,38 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 - read-write - - ENABLE - Enable or disable AAR - 0 + IN1 + Write '1' to disable interrupt for event IN[1] + 1 1 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable - 3 + Read: Enabled + 1 - - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity root keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - - - CCM - AES CCM Mode Encryption - 0x4000F000 - AAR - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - CCM - 0x20 - - - TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. - 0x000 - write-only - - - TASKS_KSGEN - 0 - 0 - - - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0x004 - write-only - - - TASKS_CRYPT - 0 - 0 - - - - - TASKS_STOP - Stop encryption/decryption - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0x00C - write-only - - - TASKS_RATEOVERRIDE - 0 - 0 - - - - - EVENTS_ENDKSGEN - Key-stream generation complete - 0x100 - read-write - - - EVENTS_ENDKSGEN - 0 - 0 - - - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0x104 - read-write - - - EVENTS_ENDCRYPT - 0 - 0 - - - - - EVENTS_ERROR - Deprecated register - CCM error event - 0x108 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - ENDKSGEN_CRYPT - Shortcut between ENDKSGEN event and CRYPT task - 0 - 0 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - ENDKSGEN - Write '1' to enable interrupt for ENDKSGEN event - 0 - 0 + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 read @@ -16795,17 +20596,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - ENDCRYPT - Write '1' to enable interrupt for ENDCRYPT event - 1 - 1 + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 read @@ -16822,17 +20623,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - ERROR - Write '1' to enable interrupt for ERROR event - 2 - 2 + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 read @@ -16849,25 +20650,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - ENDKSGEN - Write '1' to disable interrupt for ENDKSGEN event - 0 - 0 + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 read @@ -16891,10 +20684,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ENDCRYPT - Write '1' to disable interrupt for ENDCRYPT event - 1 - 1 + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 read @@ -16918,10 +20711,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERROR - Write '1' to disable interrupt for ERROR event - 2 - 2 + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 read @@ -16944,1073 +20737,989 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - MICSTATUS - MIC check result - 0x400 - read-only - - MICSTATUS - The result of the MIC check performed during the previous decryption operation - 0 - 0 + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + read - CheckFailed - MIC check failed + Disabled + Read: Disabled 0 - CheckPassed - MIC check passed + Enabled + Read: Enabled 1 - - - - - ENABLE - Enable - 0x500 - read-write - - - ENABLE - Enable or disable CCM - 0 - 1 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable - 2 + 1 - MODE - Operation mode - 0x504 + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 read-write - 0x00000001 MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + Mode 0 - 0 + 1 - Encryption - AES CCM packet encryption mode + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0 - Decryption - AES CCM packet decryption mode + Event + Event mode 1 + + Task + Task mode + 3 + - DATARATE - Radio data rate that the CCM shall run synchronous with + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 - 1Mbit - 1 Mbps + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0 - 2Mbit - 2 Mbps + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 1 - 125Kbps - 125 Kbps + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 2 - 500Kbps - 500 Kbps + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 3 - LENGTH - Packet length configuration - 24 - 24 + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 - Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Low + Task mode: Initial value of pin before task triggering is low 0 - Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + High + Task mode: Initial value of pin before task triggering is high 1 + + + + SAADC + Analog to Digital Converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + - CNFPTR - Pointer to data structure holding AES key and NONCE vector - 0x508 - read-write + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only - CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + TASKS_START + Start the ADC and prepare the result buffer in RAM 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - INPTR - Input pointer - 0x50C - read-write + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only - INPTR - Input pointer + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - OUTPTR - Output pointer - 0x510 - read-write + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only - OUTPTR - Output pointer + TASKS_STOP + Stop the ADC and terminate any on-going conversion 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, - MIC generation and encryption/decryption. + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. - 0x518 + EVENTS_STARTED + The ADC has started + 0x100 read-write - 0x000000FB - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + EVENTS_STARTED + The ADC has started 0 - 7 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - RATEOVERRIDE - Data rate override setting. - 0x51C + EVENTS_END + The ADC has filled up the Result buffer + 0x104 read-write - 0x00000000 - RATEOVERRIDE - Data rate override setting. + EVENTS_END + The ADC has filled up the Result buffer 0 - 1 + 0 - 1Mbit - 1 Mbps + NotGenerated + Event not generated 0 - 2Mbit - 2 Mbps + Generated + Event generated 1 - - 125Kbps - 125 Kbps - 2 - - - 500Kbps - 500 Kbps - 3 - - - - - WDT - Watchdog Timer - 0x40010000 - - 0 - 0x1000 - registers - - - WDT - 16 - - WDT - 0x20 - - TASKS_START - Start the watchdog - 0x000 - write-only + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write - TASKS_START + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_TIMEOUT - Watchdog timeout - 0x100 + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C read-write - EVENTS_TIMEOUT + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 read-write - TIMEOUT - Write '1' to enable interrupt for TIMEOUT event + EVENTS_CALIBRATEDONE + Calibration is complete 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + - INTENCLR - Disable interrupt - 0x308 + INTEN + Enable or disable interrupt + 0x300 read-write - TIMEOUT - Write '1' to disable interrupt for TIMEOUT event + STARTED + Enable or disable interrupt for event STARTED 0 0 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + END + Enable or disable interrupt for event END + 1 + 1 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - - - - RUNSTATUS - Run status - 0x400 - read-only - - RUNSTATUS - Indicates whether or not the watchdog is running - 0 - 0 + DONE + Enable or disable interrupt for event DONE + 2 + 2 - NotRunning - Watchdog not running + Disabled + Disable 0 - Running - Watchdog is running + Enabled + Enable 1 - - - - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 - - RR0 - Request status for RR[0] register - 0 - 0 + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR1 - Request status for RR[1] register - 1 - 1 + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR2 - Request status for RR[2] register - 2 - 2 + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR3 - Request status for RR[3] register - 3 - 3 + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR4 - Request status for RR[4] register - 4 - 4 + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR5 - Request status for RR[5] register - 5 - 5 + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR6 - Request status for RR[6] register - 6 - 6 + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - RR7 - Request status for RR[7] register - 7 - 7 + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload + Disabled + Disable 0 - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload + Enabled + Enable 1 - - - - CRV - Counter reload value - 0x504 - read-write - 0xFFFFFFFF - - - CRV - Counter reload value in number of cycles of the 32.768 kHz clock - 0 - 31 - - - - - RREN - Enable register for reload request registers - 0x508 - read-write - 0x00000001 - - RR0 - Enable or disable RR[0] register - 0 - 0 + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 Disabled - Disable RR[0] register + Disable 0 Enabled - Enable RR[0] register + Enable 1 - RR1 - Enable or disable RR[1] register - 1 - 1 + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 Disabled - Disable RR[1] register + Disable 0 Enabled - Enable RR[1] register + Enable 1 - RR2 - Enable or disable RR[2] register - 2 - 2 + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 Disabled - Disable RR[2] register + Disable 0 Enabled - Enable RR[2] register + Enable 1 - RR3 - Enable or disable RR[3] register - 3 - 3 + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 Disabled - Disable RR[3] register + Disable 0 Enabled - Enable RR[3] register + Enable 1 - RR4 - Enable or disable RR[4] register - 4 - 4 + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 Disabled - Disable RR[4] register + Disable 0 Enabled - Enable RR[4] register + Enable 1 - RR5 - Enable or disable RR[5] register - 5 - 5 + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 Disabled - Disable RR[5] register + Disable 0 Enabled - Enable RR[5] register + Enable 1 - RR6 - Enable or disable RR[6] register - 6 - 6 + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 Disabled - Disable RR[6] register + Disable 0 Enabled - Enable RR[6] register + Enable 1 - RR7 - Enable or disable RR[7] register - 7 - 7 + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 Disabled - Disable RR[7] register + Disable 0 Enabled - Enable RR[7] register + Enable 1 - - - - CONFIG - Configuration register - 0x50C - read-write - 0x00000001 - - SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - 0 - 0 + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 - Pause - Pause watchdog while the CPU is sleeping + Disabled + Disable 0 - Run - Keep the watchdog running while the CPU is sleeping + Enabled + Enable 1 - HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 - Pause - Pause watchdog while the CPU is halted by the debugger + Disabled + Disable 0 - Run - Keep the watchdog running while the CPU is halted by the debugger + Enabled + Enable 1 - - - - 0x8 - 0x4 - RR[%s] - Description collection[n]: Reload request n - 0x600 - write-only - - RR - Reload request register - 0 - 31 + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 - Reload - Value to request a reload of the watchdog timer - 0x6E524635 + Disabled + Disable + 0 + + + Enabled + Enable + 1 - - - - RTC1 - Real time counter 1 - 0x40011000 - - RTC1 - 17 - - - - QDEC - Quadrature Decoder - 0x40012000 - - 0 - 0x1000 - registers - - - QDEC - 18 - - QDEC - 0x20 - - - TASKS_START - Task starting the quadrature decoder - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Task stopping the quadrature decoder - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_READCLRACC - Read and clear ACC and ACCDBL - 0x008 - write-only - - - TASKS_READCLRACC - 0 - 0 - - - - - TASKS_RDCLRACC - Read and clear ACC - 0x00C - write-only - - - TASKS_RDCLRACC - 0 - 0 - - - - - TASKS_RDCLRDBL - Read and clear ACCDBL - 0x010 - write-only - - - TASKS_RDCLRDBL - 0 - 0 - - - - - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0x100 - read-write - - - EVENTS_SAMPLERDY - 0 - 0 - - - - - EVENTS_REPORTRDY - Non-null report ready - 0x104 - read-write - - - EVENTS_REPORTRDY - 0 - 0 - - - - - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0x108 - read-write - - - EVENTS_ACCOF - 0 - 0 - - - - - EVENTS_DBLRDY - Double displacement(s) detected - 0x10C - read-write - - - EVENTS_DBLRDY - 0 - 0 - - - - - EVENTS_STOPPED - QDEC has been stopped - 0x110 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - SHORTS - Shortcut register - 0x200 + INTENSET + Enable interrupt + 0x304 read-write - REPORTRDY_READCLRACC - Shortcut between REPORTRDY event and READCLRACC task + STARTED + Write '1' to enable interrupt for event STARTED 0 0 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - SAMPLERDY_STOP - Shortcut between SAMPLERDY event and STOP task + END + Write '1' to enable interrupt for event END 1 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - REPORTRDY_RDCLRACC - Shortcut between REPORTRDY event and RDCLRACC task + DONE + Write '1' to enable interrupt for event DONE 2 2 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - REPORTRDY_STOP - Shortcut between REPORTRDY event and STOP task + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE 3 3 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - DBLRDY_RDCLRDBL - Shortcut between DBLRDY event and RDCLRDBL task - 4 - 4 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Set + Enable 1 - DBLRDY_STOP - Shortcut between DBLRDY event and STOP task - 5 - 5 + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - SAMPLERDY_READCLRACC - Shortcut between SAMPLERDY event and READCLRACC task - 6 - 6 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Set + Enable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - SAMPLERDY - Write '1' to enable interrupt for SAMPLERDY event - 0 - 0 + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 read @@ -18034,10 +21743,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - REPORTRDY - Write '1' to enable interrupt for REPORTRDY event - 1 - 1 + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 read @@ -18061,10 +21770,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ACCOF - Write '1' to enable interrupt for ACCOF event - 2 - 2 + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 read @@ -18088,10 +21797,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - DBLRDY - Write '1' to enable interrupt for DBLRDY event - 3 - 3 + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 read @@ -18115,10 +21824,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to enable interrupt for STOPPED event - 4 - 4 + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 read @@ -18141,19 +21850,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - SAMPLERDY - Write '1' to disable interrupt for SAMPLERDY event - 0 - 0 + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 read @@ -18170,17 +21871,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - REPORTRDY - Write '1' to disable interrupt for REPORTRDY event - 1 - 1 + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 read @@ -18197,17 +21898,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ACCOF - Write '1' to disable interrupt for ACCOF event - 2 - 2 + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 read @@ -18224,17 +21925,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - DBLRDY - Write '1' to disable interrupt for DBLRDY event - 3 - 3 + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 read @@ -18251,17 +21952,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - STOPPED - Write '1' to disable interrupt for STOPPED event - 4 - 4 + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 read @@ -18278,715 +21979,457 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - ENABLE - Enable the quadrature decoder - 0x500 - read-write - - ENABLE - Enable or disable the quadrature decoder - 0 - 0 + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - - - LEDPOL - LED output pin polarity - 0x504 - read-write - - - LEDPOL - LED output pin polarity - 0 - 0 + write - ActiveLow - Led active on output pin low - 0 - - - ActiveHigh - Led active on output pin high + Set + Enable 1 - - - - SAMPLEPER - Sample period - 0x508 - read-write - - SAMPLEPER - Sample period. The SAMPLE register will be updated for every new sample - 0 - 3 + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + read - 128us - 128 us + Disabled + Read: Disabled 0 - 256us - 256 us + Enabled + Read: Enabled 1 - - 512us - 512 us - 2 - - - 1024us - 1024 us - 3 - - - 2048us - 2048 us - 4 - - - 4096us - 4096 us - 5 - - - 8192us - 8192 us - 6 - - - 16384us - 16384 us - 7 - - - 32ms - 32768 us - 8 - - - 65ms - 65536 us - 9 - - - 131ms - 131072 us - 10 - - - - - - SAMPLE - Motion sample value - 0x50C - read-only - int32_t - - - SAMPLE - Last motion sample - 0 - 31 - - - - - REPORTPER - Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - 0x510 - read-write - - - REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - 0 - 3 + write - 10Smpl - 10 samples / report - 0 - - - 40Smpl - 40 samples / report + Set + Enable 1 - - 80Smpl - 80 samples / report - 2 - - - 120Smpl - 120 samples / report - 3 - - - 160Smpl - 160 samples / report - 4 - - - 200Smpl - 200 samples / report - 5 - - - 240Smpl - 240 samples / report - 6 - - - 280Smpl - 280 samples / report - 7 - - - 1Smpl - 1 sample / report - 8 - - - - - ACC - Register accumulating the valid transitions - 0x514 - read-only - int32_t - - - ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register - 0 - 31 - - - - - ACCREAD - Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - 0x518 - read-only - int32_t - - - ACCREAD - Snapshot of the ACC register. - 0 - 31 - - - - - PSEL - Unspecified - QDEC_PSEL - 0x51C - - LED - Pin select for LED signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - A - Pin select for A signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - B - Pin select for B signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - DBFEN - Enable input debounce filters - 0x528 - read-write - - DBFEN - Enable input debounce filters - 0 - 0 + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + read Disabled - Debounce input filters disabled + Read: Disabled 0 Enabled - Debounce input filters enabled - 1 - - - - - - - LEDPRE - Time period the LED is switched ON prior to sampling - 0x540 - read-write - 0x00000010 - - - LEDPRE - Period in us the LED is switched on prior to sampling - 0 - 8 - - - - - ACCDBL - Register accumulating the number of detected double transitions - 0x544 - read-only - - - ACCDBL - Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - 0 - 3 - - - - - ACCDBLREAD - Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - 0x548 - read-only - - - ACCDBLREAD - Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - 0 - 3 - - - - - - - COMP - Comparator - 0x40013000 - - 0 - 0x1000 - registers - - - COMP - 19 - - COMP - 0x20 - - - TASKS_START - Start comparator - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop comparator - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only - - - TASKS_SAMPLE - 0 - 0 + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - EVENTS_READY - COMP is ready and output is valid - 0x100 - read-write - - EVENTS_READY - 0 - 0 + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - EVENTS_DOWN - Downward crossing - 0x104 - read-write - - EVENTS_DOWN - 0 - 0 + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - EVENTS_UP - Upward crossing - 0x108 - read-write - - EVENTS_UP - 0 - 0 + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - EVENTS_CROSS - Downward or upward crossing - 0x10C - read-write - - EVENTS_CROSS - 0 - 0 + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - SHORTS - Shortcut register - 0x200 + INTENCLR + Disable interrupt + 0x308 read-write - READY_SAMPLE - Shortcut between READY event and SAMPLE task + STARTED + Write '1' to disable interrupt for event STARTED 0 0 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - READY_STOP - Shortcut between READY event and STOP task + END + Write '1' to disable interrupt for event END 1 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - DOWN_STOP - Shortcut between DOWN event and STOP task + DONE + Write '1' to disable interrupt for event DONE 2 2 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - UP_STOP - Shortcut between UP event and STOP task + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE 3 3 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CROSS_STOP - Shortcut between CROSS event and STOP task + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE 4 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - READY - Enable or disable interrupt for READY event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - DOWN - Enable or disable interrupt for DOWN event - 1 - 1 + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - UP - Enable or disable interrupt for UP event - 2 - 2 + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CROSS - Enable or disable interrupt for CROSS event - 3 - 3 + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 read @@ -19003,17 +22446,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - DOWN - Write '1' to enable interrupt for DOWN event - 1 - 1 + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 read @@ -19030,17 +22473,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - UP - Write '1' to enable interrupt for UP event - 2 - 2 + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 read @@ -19057,17 +22500,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CROSS - Write '1' to enable interrupt for CROSS event - 3 - 3 + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 read @@ -19084,25 +22527,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 read @@ -19126,10 +22561,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - DOWN - Write '1' to disable interrupt for DOWN event - 1 - 1 + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 read @@ -19153,10 +22588,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - UP - Write '1' to disable interrupt for UP event - 2 - 2 + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 read @@ -19180,10 +22615,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CROSS - Write '1' to disable interrupt for CROSS event - 3 - 3 + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 read @@ -19206,1214 +22641,1153 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - RESULT - Compare result - 0x400 - read-only - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + read - Below - Input voltage is below the threshold (VIN+ &lt; VIN-) + Disabled + Read: Disabled 0 - Above - Input voltage is above the threshold (VIN+ &gt; VIN-) + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ENABLE - COMP enable - 0x500 - read-write - - ENABLE - Enable or disable COMP - 0 - 1 + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable - 2 + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 - - - - PSEL - Pin select - 0x504 - read-write - - PSEL - Analog pin select - 0 - 2 + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + read - AnalogInput0 - AIN0 selected as analog input + Disabled + Read: Disabled 0 - AnalogInput1 - AIN1 selected as analog input + Enabled + Read: Enabled 1 + + + write - AnalogInput2 - AIN2 selected as analog input - 2 - - - AnalogInput3 - AIN3 selected as analog input - 3 - - - AnalogInput4 - AIN4 selected as analog input - 4 + Clear + Disable + 1 + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read - AnalogInput5 - AIN5 selected as analog input - 5 + Disabled + Read: Disabled + 0 - AnalogInput6 - AIN6 selected as analog input - 6 + Enabled + Read: Enabled + 1 + + + write - VddDiv2 - VDD/2 selected as analog input - 7 + Clear + Disable + 1 - - - - REFSEL - Reference source select for single-ended mode - 0x508 - read-write - 0x00000004 - - REFSEL - Reference select - 0 - 2 + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + read - Int1V2 - VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + Disabled + Read: Disabled 0 - Int1V8 - VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + Enabled + Read: Enabled 1 + + + write - Int2V4 - VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) - 2 - - - VDD - VREF = VDD - 4 - - - ARef - VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) - 5 + Clear + Disable + 1 - EXTREFSEL - External reference select - 0x50C - read-write + STATUS + Status + 0x400 + read-only - EXTREFSEL - External analog reference select + STATUS + Status 0 - 2 + 0 - AnalogReference0 - Use AIN0 as external analog reference + Ready + ADC is ready. No on-going conversion. 0 - AnalogReference1 - Use AIN1 as external analog reference + Busy + ADC is busy. Conversion in progress. 1 - - AnalogReference2 - Use AIN2 as external analog reference - 2 - - - AnalogReference3 - Use AIN3 as external analog reference - 3 - - - AnalogReference4 - Use AIN4 as external analog reference - 4 - - - AnalogReference5 - Use AIN5 as external analog reference - 5 - - - AnalogReference6 - Use AIN6 as external analog reference - 6 - - - AnalogReference7 - Use AIN7 as external analog reference - 7 - - TH - Threshold configuration for hysteresis unit - 0x530 + ENABLE + Enable or disable ADC + 0x500 read-write - 0x00000000 - THDOWN - VDOWN = (THDOWN+1)/64*VREF + ENABLE + Enable or disable ADC 0 - 5 - - - THUP - VUP = (THUP+1)/64*VREF - 8 - 13 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + - MODE - Mode configuration - 0x534 + RESOLUTION + Resolution configuration + 0x5F0 read-write + 0x00000001 - SP - Speed and power modes + VAL + Set the resolution 0 - 1 + 2 - Low - Low-power mode + 8bit + 8 bit 0 - Normal - Normal mode + 10bit + 10 bit 1 - High - High-speed mode + 12bit + 12 bit 2 - - - - MAIN - Main operation modes - 8 - 8 - - - SE - Single-ended mode - 0 - - - Diff - Differential mode - 1 - - - - - - - HYST - Comparator hysteresis enable - 0x538 - read-write - - - HYST - Comparator hysteresis - 0 - 0 - - - NoHyst - Comparator hysteresis disabled - 0 - - Hyst50mV - Comparator hysteresis enabled - 1 + 14bit + 14 bit + 3 - - - - EGU0 - Event Generator Unit 0 - 0x40014000 - EGU - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - EGU - 0x20 - - - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only - - - TASKS_TRIGGER - 0 - 0 - - - - - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write - - - EVENTS_TRIGGERED - 0 - 0 - - - - INTEN - Enable or disable interrupt - 0x300 + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 read-write - TRIGGERED0 - Enable or disable interrupt for TRIGGERED[0] event + OVERSAMPLE + Oversample control 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED1 - Enable or disable interrupt for TRIGGERED[1] event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED2 - Enable or disable interrupt for TRIGGERED[2] event - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED3 - Enable or disable interrupt for TRIGGERED[3] event - 3 3 - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED4 - Enable or disable interrupt for TRIGGERED[4] event - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED5 - Enable or disable interrupt for TRIGGERED[5] event - 5 - 5 - - - Disabled - Disable + Bypass + Bypass oversampling 0 - Enabled - Enable + Over2x + Oversample 2x 1 - - - - TRIGGERED6 - Enable or disable interrupt for TRIGGERED[6] event - 6 - 6 - - - Disabled - Disable - 0 - - Enabled - Enable - 1 + Over4x + Oversample 4x + 2 - - - - TRIGGERED7 - Enable or disable interrupt for TRIGGERED[7] event - 7 - 7 - - Disabled - Disable - 0 + Over8x + Oversample 8x + 3 - Enabled - Enable - 1 + Over16x + Oversample 16x + 4 - - - - TRIGGERED8 - Enable or disable interrupt for TRIGGERED[8] event - 8 - 8 - - Disabled - Disable - 0 + Over32x + Oversample 32x + 5 - Enabled - Enable - 1 + Over64x + Oversample 64x + 6 - - - - TRIGGERED9 - Enable or disable interrupt for TRIGGERED[9] event - 9 - 9 - - Disabled - Disable - 0 + Over128x + Oversample 128x + 7 - Enabled - Enable - 1 + Over256x + Oversample 256x + 8 + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + - TRIGGERED10 - Enable or disable interrupt for TRIGGERED[10] event - 10 + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 10 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED11 - Enable or disable interrupt for TRIGGERED[11] event - 11 - 11 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - TRIGGERED12 - Enable or disable interrupt for TRIGGERED[12] event + MODE + Select mode for sample rate control 12 12 - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED13 - Enable or disable interrupt for TRIGGERED[13] event - 13 - 13 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED14 - Enable or disable interrupt for TRIGGERED[14] event - 14 - 14 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED15 - Enable or disable interrupt for TRIGGERED[15] event - 15 - 15 - - - Disabled - Disable + Task + Rate is controlled from SAMPLE task 0 - Enabled - Enable + Timers + Rate is controlled from local timer (use CC to control the rate) 1 - - INTENSET - Enable interrupt - 0x304 + + RESULT + RESULT EasyDMA channel + SAADC_RESULT read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only - TRIGGERED0 - Write '1' to enable interrupt for TRIGGERED[0] event + TASKS_START + Start Timer 0 0 - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - TRIGGERED1 - Write '1' to enable interrupt for TRIGGERED[1] event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + - TRIGGERED2 - Write '1' to enable interrupt for TRIGGERED[2] event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_STOP + Stop Timer + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + - TRIGGERED3 - Write '1' to enable interrupt for TRIGGERED[3] event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + - TRIGGERED4 - Write '1' to enable interrupt for TRIGGERED[4] event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_CLEAR + Clear time + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + - TRIGGERED5 - Write '1' to enable interrupt for TRIGGERED[5] event - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + - TRIGGERED6 - Write '1' to enable interrupt for TRIGGERED[6] event - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + - TRIGGERED7 - Write '1' to enable interrupt for TRIGGERED[7] event - 7 - 7 + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - TRIGGERED8 - Write '1' to enable interrupt for TRIGGERED[8] event - 8 - 8 + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED9 - Write '1' to enable interrupt for TRIGGERED[9] event - 9 - 9 + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED10 - Write '1' to enable interrupt for TRIGGERED[10] event - 10 - 10 + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED11 - Write '1' to enable interrupt for TRIGGERED[11] event - 11 - 11 + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED12 - Write '1' to enable interrupt for TRIGGERED[12] event - 12 - 12 + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED13 - Write '1' to enable interrupt for TRIGGERED[13] event - 13 - 13 + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED14 - Write '1' to enable interrupt for TRIGGERED[14] event - 14 - 14 + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - TRIGGERED15 - Write '1' to enable interrupt for TRIGGERED[15] event - 15 - 15 + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - TRIGGERED0 - Write '1' to disable interrupt for TRIGGERED[0] event - 0 - 0 + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - TRIGGERED1 - Write '1' to disable interrupt for TRIGGERED[1] event - 1 - 1 + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - TRIGGERED2 - Write '1' to disable interrupt for TRIGGERED[2] event - 2 - 2 + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - TRIGGERED3 - Write '1' to disable interrupt for TRIGGERED[3] event - 3 - 3 + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - TRIGGERED4 - Write '1' to disable interrupt for TRIGGERED[4] event - 4 - 4 + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 read @@ -20430,17 +23804,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED5 - Write '1' to disable interrupt for TRIGGERED[5] event - 5 - 5 + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 read @@ -20457,17 +23831,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED6 - Write '1' to disable interrupt for TRIGGERED[6] event - 6 - 6 + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 read @@ -20484,17 +23858,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED7 - Write '1' to disable interrupt for TRIGGERED[7] event - 7 - 7 + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 read @@ -20511,17 +23885,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED8 - Write '1' to disable interrupt for TRIGGERED[8] event - 8 - 8 + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 read @@ -20538,17 +23912,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED9 - Write '1' to disable interrupt for TRIGGERED[9] event - 9 - 9 + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 read @@ -20565,17 +23939,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - TRIGGERED10 - Write '1' to disable interrupt for TRIGGERED[10] event - 10 - 10 + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 read @@ -20597,12 +23979,12 @@ POSSIBILITY OF SUCH DAMAGE.\n 1 - - - TRIGGERED11 - Write '1' to disable interrupt for TRIGGERED[11] event - 11 - 11 + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 read @@ -20626,10 +24008,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED12 - Write '1' to disable interrupt for TRIGGERED[12] event - 12 - 12 + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 read @@ -20653,10 +24035,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED13 - Write '1' to disable interrupt for TRIGGERED[13] event - 13 - 13 + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 read @@ -20680,10 +24062,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED14 - Write '1' to disable interrupt for TRIGGERED[14] event - 14 - 14 + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 read @@ -20707,10 +24089,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED15 - Write '1' to disable interrupt for TRIGGERED[15] event - 15 - 15 + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 read @@ -20735,309 +24117,219 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - SWI0 - Software interrupt 0 - 0x40014000 - EGU0 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - SWI - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - EGU1 - Event Generator Unit 1 - 0x40015000 - - SWI1_EGU1 - 21 - - - - SWI1 - Software interrupt 1 - 0x40015000 - EGU1 - - SWI1_EGU1 - 21 - - - - SWI2 - Software interrupt 2 - 0x40016000 - - SWI2 - 22 - - - - SWI3 - Software interrupt 3 - 0x40017000 - - SWI3 - 23 - - - - SWI4 - Software interrupt 4 - 0x40018000 - - SWI4 - 24 - - - - SWI5 - Software interrupt 5 - 0x40019000 - - SWI5 - 25 - - - - PWM0 - Pulse width modulation unit - 0x4001C000 - PWM - - 0 - 0x1000 - registers - - - PWM0 - 28 - - PWM - 0x20 - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - 0x2 - 0x4 - TASKS_SEQSTART[%s] - Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0x008 - write-only - - - TASKS_SEQSTART - 0 - 0 - - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0x010 - write-only + MODE + Timer mode selection + 0x504 + read-write - TASKS_NEXTSTEP + MODE + Timer mode 0 - 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0x104 + BITMODE + Configure the number of bits used by the TIMER + 0x508 read-write - EVENTS_STOPPED + BITMODE + Timer bit width 0 - 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + - 0x2 - 0x4 - EVENTS_SEQSTARTED[%s] - Description collection[n]: First PWM period started on sequence n - 0x108 + PRESCALER + Timer prescaler register + 0x510 read-write + 0x00000004 - EVENTS_SEQSTARTED + PRESCALER + Prescaler value 0 - 0 + 3 - 0x2 + 0x6 0x4 - EVENTS_SEQEND[%s] - Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0x110 + CC[%s] + Description collection: Capture/Compare register n + 0x540 read-write - EVENTS_SEQEND + CC + Capture/Compare value 0 - 0 + 31 + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0x118 - read-write + TASKS_START + Start RTC COUNTER + 0x000 + write-only - EVENTS_PWMPERIODEND + TASKS_START + Start RTC COUNTER 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0x11C - read-write + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only - EVENTS_LOOPSDONE + TASKS_STOP + Stop RTC COUNTER 0 0 + + + Trigger + Trigger task + 1 + + - SHORTS - Shortcut register - 0x200 - read-write + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only - SEQEND0_STOP - Shortcut between SEQEND[0] event and STOP task + TASKS_CLEAR + Clear RTC COUNTER 0 0 - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - SEQEND1_STOP - Shortcut between SEQEND[1] event and STOP task - 1 - 1 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART0 - Shortcut between LOOPSDONE event and SEQSTART[0] task - 2 - 2 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - LOOPSDONE_SEQSTART1 - Shortcut between LOOPSDONE event and SEQSTART[1] task - 3 - 3 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Trigger + Trigger task 1 + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + - LOOPSDONE_STOP - Shortcut between LOOPSDONE event and STOP task - 4 - 4 + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Trigger + Trigger task 1 @@ -21045,133 +24337,51 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTEN - Enable or disable interrupt - 0x300 + EVENTS_TICK + Event on COUNTER increment + 0x100 read-write - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED0 - Enable or disable interrupt for SEQSTARTED[0] event - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQSTARTED1 - Enable or disable interrupt for SEQSTARTED[1] event - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND0 - Enable or disable interrupt for SEQEND[0] event - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - SEQEND1 - Enable or disable interrupt for SEQEND[1] event - 5 - 5 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - PWMPERIODEND - Enable or disable interrupt for PWMPERIODEND event - 6 - 6 + EVENTS_TICK + Event on COUNTER increment + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 - - LOOPSDONE - Enable or disable interrupt for LOOPSDONE event - 7 - 7 + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 @@ -21179,43 +24389,44 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 read-write - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - SEQSTARTED0 - Write '1' to enable interrupt for SEQSTARTED[0] event - 2 - 2 + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 read @@ -21239,10 +24450,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEQSTARTED1 - Write '1' to enable interrupt for SEQSTARTED[1] event - 3 - 3 + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 read @@ -21266,10 +24477,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEQEND0 - Write '1' to enable interrupt for SEQEND[0] event - 4 - 4 + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 read @@ -21293,10 +24504,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEQEND1 - Write '1' to enable interrupt for SEQEND[1] event - 5 - 5 + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 read @@ -21320,10 +24531,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PWMPERIODEND - Write '1' to enable interrupt for PWMPERIODEND event - 6 - 6 + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 read @@ -21347,10 +24558,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LOOPSDONE - Write '1' to enable interrupt for LOOPSDONE event - 7 - 7 + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 read @@ -21382,64 +24593,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED0 - Write '1' to disable interrupt for SEQSTARTED[0] event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED1 - Write '1' to disable interrupt for SEQSTARTED[1] event - 3 - 3 + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 read @@ -21463,10 +24620,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEQEND0 - Write '1' to disable interrupt for SEQEND[0] event - 4 - 4 + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 read @@ -21490,10 +24647,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEQEND1 - Write '1' to disable interrupt for SEQEND[1] event - 5 - 5 + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 read @@ -21517,10 +24674,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PWMPERIODEND - Write '1' to disable interrupt for PWMPERIODEND event - 6 - 6 + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 read @@ -21544,10 +24701,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LOOPSDONE - Write '1' to disable interrupt for LOOPSDONE event - 7 - 7 + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 read @@ -21570,428 +24727,100 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - ENABLE - PWM module enable register - 0x500 - read-write - 0x00000000 - - - ENABLE - Enable or disable PWM module - 0 - 0 - - - Disabled - Disabled - 0 - - - Enabled - Enable - 1 - - - - - - - MODE - Selects operating mode of the wave counter - 0x504 - read-write - 0x00000000 - - - UPDOWN - Selects up mode or up-and-down mode for the counter - 0 - 0 - - - Up - Up counter, edge-aligned PWM duty cycle - 0 - - - UpAndDown - Up and down counter, center-aligned PWM duty cycle - 1 - - - - - - - COUNTERTOP - Value up to which the pulse generator counter counts - 0x508 - read-write - 0x000003FF - - - COUNTERTOP - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. - 0 - 14 - - - - - PRESCALER - Configuration for PWM_CLK - 0x50C - read-write - 0x00000000 - - - PRESCALER - Prescaler of PWM_CLK - 0 - 2 - - - DIV_1 - Divide by 1 (16 MHz) - 0 - - - DIV_2 - Divide by 2 (8 MHz) - 1 - - - DIV_4 - Divide by 4 (4 MHz) - 2 - - - DIV_8 - Divide by 8 (2 MHz) - 3 - - - DIV_16 - Divide by 16 (1 MHz) - 4 - - - DIV_32 - Divide by 32 (500 kHz) - 5 - - - DIV_64 - Divide by 64 (250 kHz) - 6 - - - DIV_128 - Divide by 128 (125 kHz) - 7 - - - - - - - DECODER - Configuration of the decoder - 0x510 - read-write - 0x00000000 - - - LOAD - How a sequence is read from RAM and spread to the compare register - 0 - 1 - - - Common - 1st half word (16-bit) used in all PWM channels 0..3 - 0 - - - Grouped - 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 - - - Individual - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 - - - WaveForm - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 - - - - - MODE - Selects source for advancing the active sequence - 8 - 8 - - - RefreshCount - SEQ[n].REFRESH is used to determine loading internal compare registers - 0 - - - NextStep - NEXTSTEP task causes a new value to be loaded to internal compare registers - 1 - - - - - - - LOOP - Number of playbacks of a loop - 0x514 - read-write - 0x00000000 - - - CNT - Number of playbacks of pattern cycles - 0 - 15 - - - Disabled - Looping disabled (stop at the end of the sequence) - 0 - - - - - - - 2 - 0x020 - SEQ[%s] - Unspecified - PWM_SEQ - 0x520 - - PTR - Description cluster[n]: Beginning address in RAM of this sequence - 0x000 - read-write - 0x00000000 - - - PTR - Beginning address in RAM of this sequence - 0 - 31 - - - - - CNT - Description cluster[n]: Number of values (duty cycles) in this sequence - 0x004 - read-write - 0x00000000 - - - CNT - Number of values (duty cycles) in this sequence - 0 - 14 - - - Disabled - Sequence is disabled, and shall not be started as it is empty - 0 - - - - - - - REFRESH - Description cluster[n]: Number of additional PWM periods between samples loaded into compare register - 0x008 - read-write - 0x00000001 - - - CNT - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) - 0 - 23 - - - Continuous - Update every PWM period - 0 - - - - - - - ENDDELAY - Description cluster[n]: Time added after the sequence - 0x00C - read-write - 0x00000000 - - - CNT - Time added after the sequence in PWM periods - 0 - 23 - - - - - - PSEL - Unspecified - PWM_PSEL - 0x560 - - 0x4 - 0x4 - OUT[%s] - Description collection[n]: Output pin select for PWM channel n - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - - - PDM - Pulse Density Modulation (Digital Microphone) Interface - 0x4001D000 - - 0 - 0x1000 - registers - - - PDM - 29 - - PDM - 0x20 - - - TASKS_START - Starts continuous PDM transfer - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stops PDM transfer - 0x004 - write-only - - TASKS_STOP - 0 - 0 + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - EVENTS_STARTED - PDM transfer has started - 0x100 + EVTEN + Enable or disable event routing + 0x340 read-write - EVENTS_STARTED + TICK + Enable or disable event routing for event TICK 0 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + - - - - EVENTS_STOPPED - PDM transfer has finished - 0x104 - read-write - - EVENTS_STOPPED - 0 - 0 + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + - - - - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0x108 - read-write - - EVENTS_END - 0 - 0 + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - STARTED - Enable or disable interrupt for STARTED event - 0 - 0 + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 Disabled @@ -22000,16 +24829,16 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Enable + Disable 1 - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 Disabled @@ -22018,16 +24847,16 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Enable + Disable 1 - END - Enable or disable interrupt for END event - 2 - 2 + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 Disabled @@ -22036,7 +24865,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - Enable + Disable 1 @@ -22044,14 +24873,14 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + EVTENSET + Enable event routing + 0x344 read-write - STARTED - Write '1' to enable interrupt for STARTED event + TICK + Write '1' to enable event routing for event TICK 0 0 @@ -22077,8 +24906,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to enable interrupt for STOPPED event + OVRFLW + Write '1' to enable event routing for event OVRFLW 1 1 @@ -22104,10 +24933,91 @@ POSSIBILITY OF SUCH DAMAGE.\n - END - Write '1' to enable interrupt for END event - 2 - 2 + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 read @@ -22133,14 +25043,14 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + EVTENCLR + Disable event routing + 0x348 read-write - STARTED - Write '1' to disable interrupt for STARTED event + TICK + Write '1' to disable event routing for event TICK 0 0 @@ -22166,8 +25076,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to disable interrupt for STOPPED event + OVRFLW + Write '1' to disable event routing for event OVRFLW 1 1 @@ -22193,10 +25103,291 @@ POSSIBILITY OF SUCH DAMAGE.\n - END - Write '1' to disable interrupt for END event - 2 - 2 + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 read @@ -22222,400 +25413,381 @@ POSSIBILITY OF SUCH DAMAGE.\n - ENABLE - PDM module enable register - 0x500 + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 read-write - 0x00000000 + 0x00000326 - ENABLE - Enable or disable PDM module + A0 + Slope of 1st piece wise linear function 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - + 11 - PDMCLKCTRL - PDM clock generator control - 0x504 + A1 + Slope of 2nd piece wise linear function + 0x524 read-write - 0x08400000 + 0x00000348 - FREQ - PDM_CLK frequency + A1 + Slope of 2nd piece wise linear function 0 - 31 - - - 1000K - PDM_CLK = 32 MHz / 32 = 1.000 MHz - 0x08000000 - - - Default - PDM_CLK = 32 MHz / 31 = 1.032 MHz - 0x08400000 - - - 1067K - PDM_CLK = 32 MHz / 30 = 1.067 MHz - 0x08800000 - - + 11 - MODE - Defines the routing of the connected PDM microphones' signals - 0x508 + A2 + Slope of 3rd piece wise linear function + 0x528 read-write - 0x00000000 + 0x000003AA - OPERATION - Mono or stereo operation + A2 + Slope of 3rd piece wise linear function 0 - 0 - - - Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] - 0 - - - Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] - 1 - - + 11 + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x0000040E + - EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled - 1 - 1 - - - LeftFalling - Left (or mono) is sampled on falling edge of PDM_CLK - 0 - - - LeftRising - Left (or mono) is sampled on rising edge of PDM_CLK - 1 - - + A3 + Slope of 4th piece wise linear function + 0 + 11 - GAINL - Left output gain adjustment - 0x518 + A4 + Slope of 5th piece wise linear function + 0x530 read-write - 0x00000028 + 0x000004BD - GAINL - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + A4 + Slope of 5th piece wise linear function 0 - 6 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment ('2500 RMS' requirement) - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - + 11 - GAINR - Right output gain adjustment - 0x51C + A5 + Slope of 6th piece wise linear function + 0x534 read-write - 0x00000028 + 0x000005A3 - GAINR - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + A5 + Slope of 6th piece wise linear function 0 - 7 - - - MinGain - -20dB gain adjustment (minimum) - 0x00 - - - DefaultGain - 0dB gain adjustment ('2500 RMS' requirement) - 0x28 - - - MaxGain - +20dB gain adjustment (maximum) - 0x50 - - + 11 - - PSEL - Unspecified - PDM_PSEL + + B0 + y-intercept of 1st piece wise linear function 0x540 - - CLK - Pin number configuration for PDM CLK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DIN - Pin number configuration for PDM DIN signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - SAMPLE - Unspecified - PDM_SAMPLE + read-write + 0x00003FEF + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function 0x560 - - PTR - RAM address pointer to write samples to with EasyDMA - 0x000 - read-write - - - SAMPLEPTR - Address to write PDM samples to over DMA - 0 - 31 - - - - - MAXCNT - Number of samples to allocate memory for in EasyDMA mode - 0x004 - read-write - - - BUFFSIZE - Length of DMA RAM allocation in number of samples - 0 - 14 - - - - + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + - NVMC - Non-volatile memory controller - 0x4001E000 + RNG + Random Number Generator + 0x4000D000 0 0x1000 registers - NVMC + + RNG + 13 + + RNG 0x20 - READY - Ready flag - 0x400 - read-only - 0x00000001 + TASKS_START + Task starting the random number generator + 0x000 + write-only - READY - NVMC is ready or busy + TASKS_START + Task starting the random number generator 0 0 - Busy - NVMC is busy (ongoing write or erase operation) - 0 - - - Ready - NVMC is ready - 1 - - - - - - - CONFIG - Configuration register - 0x504 - read-write - - - WEN - Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. - 0 - 1 - - - Ren - Read only access - 0 - - - Wen - Write enabled + Trigger + Trigger task 1 - - Een - Erase enabled - 2 - - ERASEPAGE - Register for erasing a page in code area - 0x508 - read-write + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only - ERASEPAGE - Register for starting erase of a page in code area. + TASKS_STOP + Task stopping the random number generator 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x508 + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 read-write - ERASEPAGE - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register 0 - 31 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - ERASEALL - Register for erasing all non-volatile user memory - 0x50C + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + VALRDY_STOP + Shortcut between event VALRDY and task STOP 0 0 - NoOperation - No operation + Disabled + Disable shortcut 0 - Erase - Start erase of chip + Enabled + Enable shortcut 1 @@ -22623,39 +25795,69 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x510 + INTENSET + Enable interrupt + 0x304 read-write - ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + VALRDY + Write '1' to enable interrupt for event VALRDY 0 - 31 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - ERASEUICR - Register for erasing user information configuration registers - 0x514 + INTENCLR + Disable interrupt + 0x308 read-write - ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + VALRDY + Write '1' to disable interrupt for event VALRDY 0 0 + read - NoOperation - No operation + Disabled + Read: Disabled 0 - Erase - Start erase of UICR + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 @@ -22663,823 +25865,936 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERASEPAGEPARTIAL - Register for partial erase of a page in code area - 0x518 + CONFIG + Configuration register + 0x504 read-write - ERASEPAGEPARTIAL - Register for starting partial erase of a page in code area + DERCEN + Bias correction 0 - 31 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C - read-write - 0x0000000A + VALUE + Output random number + 0x508 + read-only - DURATION - Duration of the partial erase in milliseconds + VALUE + Generated random number 0 - 6 + 7 - PPI - Programmable Peripheral Interconnect - 0x4001F000 + ECB + AES ECB Mode Encryption + 0x4000E000 0 0x1000 registers - PPI + + ECB + 14 + + ECB 0x20 - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - PPI_TASKS_CHG - 0x000 - - EN - Description cluster[n]: Enable channel group n - 0x000 - write-only - - - EN - 0 - 0 - - - - - DIS - Description cluster[n]: Disable channel group n - 0x004 - write-only - - - DIS - 0 - 0 - - - - - CHEN - Channel enable register - 0x500 - read-write + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only - CH0 - Enable or disable channel 0 + TASKS_STARTECB + Start ECB block encrypt 0 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH1 - Enable or disable channel 1 - 1 - 1 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Trigger + Trigger task 1 + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + - CH2 - Enable or disable channel 2 - 2 - 2 + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Trigger + Trigger task 1 + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + - CH3 - Enable or disable channel 3 - 3 - 3 + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 - Disabled - Disable channel + NotGenerated + Event not generated 0 - Enabled - Enable channel + Generated + Event generated 1 + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + - CH4 - Enable or disable channel 4 - 4 - 4 + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 - Disabled - Disable channel + NotGenerated + Event not generated 0 - Enabled - Enable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH5 - Enable or disable channel 5 - 5 - 5 + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH6 - Enable or disable channel 6 - 6 - 6 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH7 - Enable or disable channel 7 - 7 - 7 + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH8 - Enable or disable channel 8 - 8 - 8 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH9 - Enable or disable channel 9 - 9 - 9 + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH10 - Enable or disable channel 10 - 10 - 10 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH11 - Enable or disable channel 11 - 11 - 11 + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH12 - Enable or disable channel 12 - 12 - 12 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + - CH13 - Enable or disable channel 13 - 13 - 13 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + - CH14 - Enable or disable channel 14 - 14 - 14 + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + - CH15 - Enable or disable channel 15 - 15 - 15 - - - Disabled - Disable channel - 0 - + TASKS_STOP + Stop resolving addresses + 0 + 0 + - Enabled - Enable channel + Trigger + Trigger task 1 + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + - CH16 - Enable or disable channel 16 - 16 - 16 + EVENTS_END + Address resolution procedure complete + 0 + 0 - Disabled - Disable channel + NotGenerated + Event not generated 0 - Enabled - Enable channel + Generated + Event generated 1 + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + - CH17 - Enable or disable channel 17 - 17 - 17 + EVENTS_RESOLVED + Address resolved + 0 + 0 - Disabled - Disable channel + NotGenerated + Event not generated 0 - Enabled - Enable channel + Generated + Event generated 1 + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + - CH18 - Enable or disable channel 18 - 18 - 18 + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 - Disabled - Disable channel + NotGenerated + Event not generated 0 - Enabled - Enable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH19 - Enable or disable channel 19 - 19 - 19 + END + Write '1' to enable interrupt for event END + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH20 - Enable or disable channel 20 - 20 - 20 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH21 - Enable or disable channel 21 - 21 - 21 + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH22 - Enable or disable channel 22 - 22 - 22 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH23 - Enable or disable channel 23 - 23 - 23 + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH24 - Enable or disable channel 24 - 24 - 24 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH25 - Enable or disable channel 25 - 25 - 25 + END + Write '1' to disable interrupt for event END + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH26 - Enable or disable channel 26 - 26 - 26 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH27 - Enable or disable channel 27 - 27 - 27 + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH28 - Enable or disable channel 28 - 28 - 28 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH29 - Enable or disable channel 29 - 29 - 29 + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH30 - Enable or disable channel 30 - 30 - 30 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 + + + + STATUS + Resolution status + 0x400 + read-only + - CH31 - Enable or disable channel 31 - 31 - 31 + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 Disabled - Disable channel + Disable 0 Enabled - Enable channel - 1 + Enable + 3 - CHENSET - Channel enable set register + NIRK + Number of IRKs 0x504 read-write - oneToSet + 0x00000001 - CH0 - Channel 0 enable set register. Writing '0' has no effect + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. 0 0 - read - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + - CH1 - Channel 1 enable set register. Writing '0' has no effect - 1 - 1 + TASKS_STOP + Stop encryption/decryption + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0x100 + read-write + - CH2 - Channel 2 enable set register. Writing '0' has no effect - 2 - 2 + EVENTS_ENDKSGEN + Key-stream generation complete + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Generated + Event generated 1 + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + - CH3 - Channel 3 enable set register. Writing '0' has no effect - 3 - 3 + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled + Generated + Event generated 1 + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 - write - Set - Write: Enable channel + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH4 - Channel 4 enable set register. Writing '0' has no effect - 4 - 4 + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH5 - Channel 5 enable set register. Writing '0' has no effect - 5 - 5 + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -23487,26 +26802,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 - CH6 - Channel 6 enable set register. Writing '0' has no effect - 6 - 6 + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -23514,26 +26829,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 - CH7 - Channel 7 enable set register. Writing '0' has no effect - 7 - 7 + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -23541,269 +26856,422 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH8 - Channel 8 enable set register. Writing '0' has no effect - 8 - 8 + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH9 - Channel 9 enable set register. Writing '0' has no effect - 9 - 9 + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH10 - Channel 10 enable set register. Writing '0' has no effect - 10 - 10 + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + MICSTATUS + MIC check result + 0x400 + read-only + - CH11 - Channel 11 enable set register. Writing '0' has no effect - 11 - 11 + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 - read - Disabled - Read: channel disabled + CheckFailed + MIC check failed 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + CheckPassed + MIC check passed 1 + + + + ENABLE + Enable + 0x500 + read-write + - CH12 - Channel 12 enable set register. Writing '0' has no effect - 12 - 12 + ENABLE + Enable or disable CCM + 0 + 1 - read Disabled - Read: channel disabled + Disable 0 Enabled - Read: channel enabled - 1 + Enable + 2 + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 - write - Set - Write: Enable channel + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode 1 - CH13 - Channel 13 enable set register. Writing '0' has no effect - 13 - 13 + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 - read - Disabled - Read: channel disabled + 1Mbit + 1 Mbps 0 - Enabled - Read: channel enabled + 2Mbit + 2 Mbps 1 - - - write - Set - Write: Enable channel - 1 + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 - CH14 - Channel 14 enable set register. Writing '0' has no effect - 14 - 14 + LENGTH + Packet length configuration + 24 + 24 - read - Disabled - Read: channel disabled + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + - CH15 - Channel 15 enable set register. Writing '0' has no effect - 15 - 15 + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 - read - Disabled - Read: channel disabled + 1Mbit + 1 Mbps 0 - Enabled - Read: channel enabled + 2Mbit + 2 Mbps 1 + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + - CH16 - Channel 16 enable set register. Writing '0' has no effect - 16 - 16 + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH17 - Channel 17 enable set register. Writing '0' has no effect - 17 - 17 + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -23811,385 +27279,389 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH18 - Channel 18 enable set register. Writing '0' has no effect - 18 - 18 + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + RUNSTATUS + Run status + 0x400 + read-only + - CH19 - Channel 19 enable set register. Writing '0' has no effect - 19 - 19 + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 - read - Disabled - Read: channel disabled + NotRunning + Watchdog not running 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Running + Watchdog is running 1 + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + - CH20 - Channel 20 enable set register. Writing '0' has no effect - 20 - 20 + RR0 + Request status for RR[0] register + 0 + 0 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload 1 + + + RR1 + Request status for RR[1] register + 1 + 1 - write - Set - Write: Enable channel + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload 1 - CH21 - Channel 21 enable set register. Writing '0' has no effect - 21 - 21 + RR2 + Request status for RR[2] register + 2 + 2 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload 1 + + + RR3 + Request status for RR[3] register + 3 + 3 - write - Set - Write: Enable channel + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload 1 - CH22 - Channel 22 enable set register. Writing '0' has no effect - 22 - 22 + RR4 + Request status for RR[4] register + 4 + 4 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload 1 + + + RR5 + Request status for RR[5] register + 5 + 5 - write - Set - Write: Enable channel + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload 1 - CH23 - Channel 23 enable set register. Writing '0' has no effect - 23 - 23 + RR6 + Request status for RR[6] register + 6 + 6 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload 1 + + + RR7 + Request status for RR[7] register + 7 + 7 - write - Set - Write: Enable channel + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload 1 + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + - CH24 - Channel 24 enable set register. Writing '0' has no effect - 24 - 24 + RR0 + Enable or disable RR[0] register + 0 + 0 - read Disabled - Read: channel disabled + Disable RR[0] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[0] register 1 - CH25 - Channel 25 enable set register. Writing '0' has no effect - 25 - 25 + RR1 + Enable or disable RR[1] register + 1 + 1 - read Disabled - Read: channel disabled + Disable RR[1] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[1] register 1 - CH26 - Channel 26 enable set register. Writing '0' has no effect - 26 - 26 + RR2 + Enable or disable RR[2] register + 2 + 2 - read Disabled - Read: channel disabled + Disable RR[2] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[2] register 1 - CH27 - Channel 27 enable set register. Writing '0' has no effect - 27 - 27 + RR3 + Enable or disable RR[3] register + 3 + 3 - read Disabled - Read: channel disabled + Disable RR[3] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[3] register 1 - CH28 - Channel 28 enable set register. Writing '0' has no effect - 28 - 28 + RR4 + Enable or disable RR[4] register + 4 + 4 - read Disabled - Read: channel disabled + Disable RR[4] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[4] register 1 - CH29 - Channel 29 enable set register. Writing '0' has no effect - 29 - 29 + RR5 + Enable or disable RR[5] register + 5 + 5 - read Disabled - Read: channel disabled + Disable RR[5] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[5] register 1 - CH30 - Channel 30 enable set register. Writing '0' has no effect - 30 - 30 + RR6 + Enable or disable RR[6] register + 6 + 6 - read Disabled - Read: channel disabled + Disable RR[6] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[6] register 1 - CH31 - Channel 31 enable set register. Writing '0' has no effect - 31 - 31 + RR7 + Enable or disable RR[7] register + 7 + 7 - read Disabled - Read: channel disabled + Disable RR[7] register 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable RR[7] register 1 @@ -24197,567 +27669,633 @@ POSSIBILITY OF SUCH DAMAGE.\n - CHENCLR - Channel enable clear register - 0x508 + CONFIG + Configuration register + 0x50C read-write - oneToClear + 0x00000001 - CH0 - Channel 0 enable clear register. Writing '0' has no effect + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping 0 0 - read - Disabled - Read: channel disabled + Pause + Pause watchdog while the CPU is sleeping 0 - Enabled - Read: channel enabled + Run + Keep the watchdog running while the CPU is sleeping 1 + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 - write - Clear - Write: disable channel + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger 1 + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + - CH1 - Channel 1 enable clear register. Writing '0' has no effect - 1 - 1 + RR + Reload request register + 0 + 31 - read - Disabled - Read: channel disabled - 0 + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 - write - Clear - Write: disable channel + Trigger + Trigger task 1 + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + - CH2 - Channel 2 enable clear register. Writing '0' has no effect - 2 - 2 + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 - write - Clear - Write: disable channel + Trigger + Trigger task 1 + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + - CH3 - Channel 3 enable clear register. Writing '0' has no effect - 3 - 3 + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 - read - Disabled - Read: channel disabled - 0 + Trigger + Trigger task + 1 + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + - Enabled - Read: channel enabled - 1 + NotGenerated + Event not generated + 0 - - - write - Clear - Write: disable channel + Generated + Event generated 1 + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + - CH4 - Channel 4 enable clear register. Writing '0' has no effect - 4 - 4 + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + - CH5 - Channel 5 enable clear register. Writing '0' has no effect - 5 - 5 + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + - CH6 - Channel 6 enable clear register. Writing '0' has no effect - 6 - 6 + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + - CH7 - Channel 7 enable clear register. Writing '0' has no effect - 7 - 7 + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH8 - Channel 8 enable clear register. Writing '0' has no effect - 8 - 8 + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH9 - Channel 9 enable clear register. Writing '0' has no effect - 9 - 9 + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH10 - Channel 10 enable clear register. Writing '0' has no effect - 10 - 10 + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH11 - Channel 11 enable clear register. Writing '0' has no effect - 11 - 11 + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH12 - Channel 12 enable clear register. Writing '0' has no effect - 12 - 12 + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH13 - Channel 13 enable clear register. Writing '0' has no effect - 13 - 13 + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 - CH14 - Channel 14 enable clear register. Writing '0' has no effect - 14 - 14 + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH15 - Channel 15 enable clear register. Writing '0' has no effect - 15 - 15 + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH16 - Channel 16 enable clear register. Writing '0' has no effect - 16 - 16 + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH17 - Channel 17 enable clear register. Writing '0' has no effect - 17 - 17 + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH18 - Channel 18 enable clear register. Writing '0' has no effect - 18 - 18 + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH19 - Channel 19 enable clear register. Writing '0' has no effect - 19 - 19 + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH20 - Channel 20 enable clear register. Writing '0' has no effect - 20 - 20 + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -24765,26 +28303,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH21 - Channel 21 enable clear register. Writing '0' has no effect - 21 - 21 + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -24792,26 +28330,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH22 - Channel 22 enable clear register. Writing '0' has no effect - 22 - 22 + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -24819,26 +28357,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH23 - Channel 23 enable clear register. Writing '0' has no effect - 23 - 23 + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -24846,26 +28384,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH24 - Channel 24 enable clear register. Writing '0' has no effect - 24 - 24 + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -24873,1439 +28411,1674 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + - CH25 - Channel 25 enable clear register. Writing '0' has no effect - 25 - 25 + ENABLE + Enable or disable the quadrature decoder + 0 + 0 - read Disabled - Read: channel disabled + Disable 0 Enabled - Read: channel enabled + Enable 1 + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 - write - Clear - Write: disable channel + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high 1 + + + + SAMPLEPER + Sample period + 0x508 + read-write + - CH26 - Channel 26 enable clear register. Writing '0' has no effect - 26 - 26 + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 - read - Disabled - Read: channel disabled + 128us + 128 us 0 - Enabled - Read: channel enabled + 256us + 256 us 1 - - - write - Clear - Write: disable channel - 1 + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 - - - - CH27 - Channel 27 enable clear register. Writing '0' has no effect - 27 - 27 - - read - Disabled - Read: channel disabled - 0 + 4096us + 4096 us + 5 - Enabled - Read: channel enabled - 1 + 8192us + 8192 us + 6 - - - write - Clear - Write: disable channel - 1 + 16384us + 16384 us + 7 - - - - CH28 - Channel 28 enable clear register. Writing '0' has no effect - 28 - 28 - - read - Disabled - Read: channel disabled - 0 + 32ms + 32768 us + 8 - Enabled - Read: channel enabled - 1 + 65ms + 65536 us + 9 - - - write - Clear - Write: disable channel - 1 + 131ms + 131072 us + 10 + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + - CH29 - Channel 29 enable clear register. Writing '0' has no effect - 29 - 29 + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 - read - Disabled - Read: channel disabled + 10Smpl + 10 samples / report 0 - Enabled - Read: channel enabled + 40Smpl + 40 samples / report 1 - - - write - Clear - Write: disable channel - 1 + 80Smpl + 80 samples / report + 2 - - - - CH30 - Channel 30 enable clear register. Writing '0' has no effect - 30 - 30 - - read - Disabled - Read: channel disabled - 0 + 120Smpl + 120 samples / report + 3 - Enabled - Read: channel enabled - 1 + 160Smpl + 160 samples / report + 4 - - - write - Clear - Write: disable channel - 1 + 200Smpl + 200 samples / report + 5 - - - - CH31 - Channel 31 enable clear register. Writing '0' has no effect - 31 - 31 - - read - Disabled - Read: channel disabled - 0 + 240Smpl + 240 samples / report + 6 - Enabled - Read: channel enabled - 1 + 280Smpl + 280 samples / report + 7 - - - write - Clear - Write: disable channel - 1 + 1Smpl + 1 sample / report + 8 + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + - 20 - 0x008 - CH[%s] - PPI Channel - PPI_CH - 0x510 + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C - EEP - Description cluster[n]: Channel n event end-point + LED + Pin select for LED signal 0x000 read-write + 0xFFFFFFFF - EEP - Pointer to event register. Accepts only addresses to registers from the Event group. + PIN + Pin number 0 + 4 + + + CONNECT + Connection + 31 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + - TEP - Description cluster[n]: Channel n task end-point + A + Pin select for A signal 0x004 read-write + 0xFFFFFFFF - TEP - Pointer to task register. Accepts only addresses to registers from the Task group. + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number 0 + 4 + + + CONNECT + Connection + 31 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + - 0x6 - 0x4 - CHG[%s] - Description collection[n]: Channel group n - 0x800 + DBFEN + Enable input debounce filters + 0x528 read-write - CH0 - Include or exclude channel 0 + DBFEN + Enable input debounce filters 0 0 - Excluded - Exclude + Disabled + Debounce input filters disabled 0 - Included - Include + Enabled + Debounce input filters enabled 1 + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + - CH1 - Include or exclude channel 1 - 1 - 1 + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + - CH2 - Include or exclude channel 2 - 2 - 2 + TASKS_STOP + Stop comparator + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include + Trigger + Trigger task 1 + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + - CH3 - Include or exclude channel 3 - 3 - 3 + TASKS_SAMPLE + Sample comparator value + 0 + 0 - Excluded - Exclude - 0 - - - Included - Include + Trigger + Trigger task 1 + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + - CH4 - Include or exclude channel 4 - 4 - 4 + EVENTS_READY + COMP is ready and output is valid + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + - CH5 - Include or exclude channel 5 - 5 - 5 + EVENTS_DOWN + Downward crossing + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + - CH6 - Include or exclude channel 6 - 6 - 6 + EVENTS_UP + Upward crossing + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + - CH7 - Include or exclude channel 7 - 7 - 7 + EVENTS_CROSS + Downward or upward crossing + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH8 - Include or exclude channel 8 - 8 - 8 + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH9 - Include or exclude channel 9 - 9 - 9 + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH10 - Include or exclude channel 10 - 10 - 10 + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH11 - Include or exclude channel 11 - 11 - 11 + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH12 - Include or exclude channel 12 - 12 - 12 + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - CH13 - Include or exclude channel 13 - 13 - 13 + READY + Enable or disable interrupt for event READY + 0 + 0 - Excluded - Exclude + Disabled + Disable 0 - Included - Include + Enabled + Enable 1 - CH14 - Include or exclude channel 14 - 14 - 14 + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 - Excluded - Exclude + Disabled + Disable 0 - Included - Include + Enabled + Enable 1 - CH15 - Include or exclude channel 15 - 15 - 15 + UP + Enable or disable interrupt for event UP + 2 + 2 - Excluded - Exclude + Disabled + Disable 0 - Included - Include + Enabled + Enable 1 - CH16 - Include or exclude channel 16 - 16 - 16 + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 - Excluded - Exclude + Disabled + Disable 0 - Included - Include + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH17 - Include or exclude channel 17 - 17 - 17 + READY + Write '1' to enable interrupt for event READY + 0 + 0 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH18 - Include or exclude channel 18 - 18 - 18 + write - Excluded - Exclude - 0 - - - Included - Include + Set + Enable 1 - CH19 - Include or exclude channel 19 - 19 - 19 + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH20 - Include or exclude channel 20 - 20 - 20 + write - Excluded - Exclude - 0 - - - Included - Include + Set + Enable 1 - CH21 - Include or exclude channel 21 - 21 - 21 + UP + Write '1' to enable interrupt for event UP + 2 + 2 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH22 - Include or exclude channel 22 - 22 - 22 + write - Excluded - Exclude - 0 - - - Included - Include + Set + Enable 1 - CH23 - Include or exclude channel 23 - 23 - 23 + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH24 - Include or exclude channel 24 - 24 - 24 + write - Excluded - Exclude - 0 - - - Included - Include + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH25 - Include or exclude channel 25 - 25 - 25 + READY + Write '1' to disable interrupt for event READY + 0 + 0 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH26 - Include or exclude channel 26 - 26 - 26 + write - Excluded - Exclude - 0 - - - Included - Include + Clear + Disable 1 - CH27 - Include or exclude channel 27 - 27 - 27 + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH28 - Include or exclude channel 28 - 28 - 28 + write - Excluded - Exclude - 0 - - - Included - Include + Clear + Disable 1 - CH29 - Include or exclude channel 29 - 29 - 29 + UP + Write '1' to disable interrupt for event UP + 2 + 2 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled 1 - - - CH30 - Include or exclude channel 30 - 30 - 30 + write - Excluded - Exclude - 0 - - - Included - Include + Clear + Disable 1 - CH31 - Include or exclude channel 31 - 31 - 31 + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - 32 - 0x004 - FORK[%s] - Fork - PPI_FORK - 0x910 - - TEP - Description cluster[n]: Channel n task end-point - 0x000 - read-write - - - TEP - Pointer to task register - 0 - 31 - - - - - - - - P0 - GPIO Port - 0x50000000 - GPIO - - 0 - 0x1000 - registers - - GPIO - 0x20 - - OUT - Write GPIO port - 0x504 - read-write + RESULT + Compare result + 0x400 + read-only - PIN0 - Pin 0 + RESULT + Result of last compare. Decision point SAMPLE task. 0 0 - Low - Pin driver is low + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) 0 - High - Pin driver is high + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) 1 + + + + ENABLE + COMP enable + 0x500 + read-write + - PIN1 - Pin 1 - 1 + ENABLE + Enable or disable COMP + 0 1 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high - 1 + Enabled + Enable + 2 + + + + PSEL + Pin select + 0x504 + read-write + - PIN2 - Pin 2 - 2 + PSEL + Analog pin select + 0 2 - Low - Pin driver is low + AnalogInput0 + AIN0 selected as analog input 0 - High - Pin driver is high + AnalogInput1 + AIN1 selected as analog input 1 - - - - PIN3 - Pin 3 - 3 - 3 - - Low - Pin driver is low - 0 + AnalogInput2 + AIN2 selected as analog input + 2 - High - Pin driver is high - 1 + AnalogInput3 + AIN3 selected as analog input + 3 - - - - PIN4 - Pin 4 - 4 - 4 - - Low - Pin driver is low - 0 + AnalogInput4 + AIN4 selected as analog input + 4 - High - Pin driver is high - 1 + AnalogInput5 + AIN5 selected as analog input + 5 - - - - PIN5 - Pin 5 - 5 - 5 - - Low - Pin driver is low - 0 + AnalogInput6 + AIN6 selected as analog input + 6 - High - Pin driver is high - 1 + VddDiv2 + VDD/2 selected as analog input + 7 + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + - PIN6 - Pin 6 - 6 - 6 + REFSEL + Reference select + 0 + 2 - Low - Pin driver is low + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) 0 - High - Pin driver is high + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) 1 - - - - PIN7 - Pin 7 - 7 - 7 - - Low - Pin driver is low - 0 + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 - High - Pin driver is high - 1 + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 5 + + + + EXTREFSEL + External reference select + 0x50C + read-write + - PIN8 - Pin 8 - 8 - 8 + EXTREFSEL + External analog reference select + 0 + 2 - Low - Pin driver is low + AnalogReference0 + Use AIN0 as external analog reference 0 - High - Pin driver is high + AnalogReference1 + Use AIN1 as external analog reference 1 - - - - PIN9 - Pin 9 - 9 - 9 - - Low - Pin driver is low - 0 + AnalogReference2 + Use AIN2 as external analog reference + 2 - High - Pin driver is high - 1 + AnalogReference3 + Use AIN3 as external analog reference + 3 - - - - PIN10 - Pin 10 - 10 - 10 - - Low - Pin driver is low - 0 + AnalogReference4 + Use AIN4 as external analog reference + 4 - High - Pin driver is high - 1 + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + - PIN11 - Pin 11 - 11 - 11 + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 Low - Pin driver is low + Low-power mode 0 - High - Pin driver is high + Normal + Normal mode 1 + + High + High-speed mode + 2 + - PIN12 - Pin 12 - 12 - 12 + MAIN + Main operation modes + 8 + 8 - Low - Pin driver is low + SE + Single-ended mode 0 - High - Pin driver is high + Diff + Differential mode 1 + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + - PIN13 - Pin 13 - 13 - 13 + HYST + Comparator hysteresis + 0 + 0 - Low - Pin driver is low + NoHyst + Comparator hysteresis disabled 0 - High - Pin driver is high + Hyst50mV + Comparator hysteresis enabled 1 + + + + + + EGU0 + Event Generator Unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + - PIN14 - Pin 14 - 14 - 14 + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 - Low - Pin driver is low - 0 - - - High - Pin driver is high + Trigger + Trigger task 1 + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + - PIN15 - Pin 15 - 15 - 15 + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 - Low - Pin driver is low + NotGenerated + Event not generated 0 - High - Pin driver is high + Generated + Event generated 1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - PIN16 - Pin 16 - 16 - 16 + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN17 - Pin 17 - 17 - 17 + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN18 - Pin 18 - 18 - 18 + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN19 - Pin 19 - 19 - 19 + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN20 - Pin 20 - 20 - 20 + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN21 - Pin 21 - 21 - 21 + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN22 - Pin 22 - 22 - 22 + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN23 - Pin 23 - 23 - 23 + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN24 - Pin 24 - 24 - 24 + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN25 - Pin 25 - 25 - 25 + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN26 - Pin 26 - 26 - 26 + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN27 - Pin 27 - 27 - 27 + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN28 - Pin 28 - 28 - 28 + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN29 - Pin 29 - 29 - 29 + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN30 - Pin 30 - 30 - 30 + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN31 - Pin 31 - 31 - 31 + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 @@ -26313,27 +30086,26 @@ POSSIBILITY OF SUCH DAMAGE.\n - OUTSET - Set individual bits in GPIO port - 0x508 + INTENSET + Enable interrupt + 0x304 read-write - oneToSet - PIN0 - Pin 0 + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] 0 0 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26341,26 +30113,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN1 - Pin 1 + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] 1 1 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26368,26 +30140,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN2 - Pin 2 + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] 2 2 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26395,26 +30167,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN3 - Pin 3 + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] 3 3 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26422,26 +30194,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN4 - Pin 4 + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] 4 4 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26449,26 +30221,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN5 - Pin 5 + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] 5 5 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26476,26 +30248,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN6 - Pin 6 + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] 6 6 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26503,26 +30275,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN7 - Pin 7 + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] 7 7 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26530,26 +30302,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN8 - Pin 8 + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] 8 8 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26557,26 +30329,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN9 - Pin 9 + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] 9 9 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26584,26 +30356,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN10 - Pin 10 + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] 10 10 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26611,26 +30383,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN11 - Pin 11 + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] 11 11 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26638,26 +30410,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN12 - Pin 12 + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] 12 12 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26665,26 +30437,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN13 - Pin 13 + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] 13 13 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26692,26 +30464,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN14 - Pin 14 + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] 14 14 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26719,134 +30491,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 - PIN15 - Pin 15 + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] 15 15 read - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -26854,359 +30518,358 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PIN20 - Pin 20 - 20 - 20 + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN21 - Pin 21 - 21 - 21 + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN22 - Pin 22 - 22 - 22 + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN23 - Pin 23 - 23 - 23 + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN24 - Pin 24 - 24 - 24 + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - - - PIN25 - Pin 25 - 25 - 25 + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN26 - Pin 26 - 26 - 26 + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN27 - Pin 27 - 27 - 27 + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN28 - Pin 28 - 28 - 28 + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN29 - Pin 29 - 29 - 29 + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN30 - Pin 30 - 30 - 30 + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - PIN31 - Pin 31 - 31 - 31 + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Clear + Disable 1 - - - - OUTCLR - Clear individual bits in GPIO port - 0x50C - read-write - oneToClear - - PIN0 - Pin 0 - 0 - 0 + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27214,26 +30877,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN1 - Pin 1 - 1 - 1 + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27241,26 +30904,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN2 - Pin 2 - 2 - 2 + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27268,26 +30931,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN3 - Pin 3 - 3 - 3 + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27295,485 +30958,763 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event Generator Unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + SWI2 + Software interrupt 2 + 0x40016000 + + SWI2 + 22 + + + + SWI3 + Software interrupt 3 + 0x40017000 + + SWI3 + 23 + + + + SWI4 + Software interrupt 4 + 0x40018000 + + SWI4 + 24 + + + + SWI5 + Software interrupt 5 + 0x40019000 + + SWI5 + 25 + + + + PWM0 + Pulse width modulation unit + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + - PIN4 - Pin 4 - 4 - 4 + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 - read - Low - Read: pin driver is low - 0 + Trigger + Trigger task + 1 + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + - High - Read: pin driver is high + Trigger + Trigger task 1 + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Trigger + Trigger task 1 + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + - PIN5 - Pin 5 - 5 - 5 + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high + Generated + Event generated 1 + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + - PIN6 - Pin 6 - 6 - 6 + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high + Generated + Event generated 1 + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + - PIN7 - Pin 7 - 7 - 7 + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high + Generated + Event generated 1 + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 - PIN8 - Pin 8 - 8 - 8 + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 - read - Low - Read: pin driver is low + Disabled + Disable shortcut 0 - High - Read: pin driver is high + Enabled + Enable shortcut 1 + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 - PIN9 - Pin 9 - 9 - 9 + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 - read - Low - Read: pin driver is low + Disabled + Disable shortcut 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable shortcut 1 - PIN10 - Pin 10 - 10 - 10 + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 - read - Low - Read: pin driver is low + Disabled + Disable shortcut 0 - High - Read: pin driver is high + Enabled + Enable shortcut 1 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable + 0 + + + Enabled + Enable 1 - PIN11 - Pin 11 - 11 - 11 + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high + Enabled + Enable 1 + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable + 0 + + + Enabled + Enable 1 - PIN12 - Pin 12 - 12 - 12 + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high + Enabled + Enable 1 + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable + 0 + + + Enabled + Enable 1 - PIN13 - Pin 13 - 13 - 13 + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high + Enabled + Enable 1 + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disabled + Disable + 0 + + + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PIN14 - Pin 14 - 14 - 14 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN15 - Pin 15 - 15 - 15 + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN16 - Pin 16 - 16 - 16 + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN17 - Pin 17 - 17 - 17 + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN18 - Pin 18 - 18 - 18 + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN19 - Pin 19 - 19 - 19 + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN20 - Pin 20 - 20 - 20 + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PIN21 - Pin 21 - 21 - 21 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27781,26 +31722,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN22 - Pin 22 - 22 - 22 + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27808,26 +31749,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN23 - Pin 23 - 23 - 23 + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27835,26 +31776,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN24 - Pin 24 - 24 - 24 + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27862,26 +31803,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN25 - Pin 25 - 25 - 25 + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27889,26 +31830,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN26 - Pin 26 - 26 - 26 + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27916,26 +31857,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 - PIN27 - Pin 27 - 27 - 27 + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 @@ -27943,699 +31884,1156 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Disable 1 + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + - PIN28 - Pin 28 - 28 - 28 + ENABLE + Enable or disable PWM module + 0 + 0 - read - Low - Read: pin driver is low + Disabled + Disabled 0 - High - Read: pin driver is high + Enabled + Enable 1 + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle 1 + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + - PIN29 - Pin 29 - 29 - 29 + PRESCALER + Prescaler of PWM_CLK + 0 + 2 - read - Low - Read: pin driver is low + DIV_1 + Divide by 1 (16 MHz) 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + DIV_2 + Divide by 2 (8 MHz) 1 - - - - PIN30 - Pin 30 - 30 - 30 - - read - Low - Read: pin driver is low - 0 + DIV_4 + Divide by 4 (4 MHz) + 2 - High - Read: pin driver is high - 1 + DIV_8 + Divide by 8 (2 MHz) + 3 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DIV_16 + Divide by 16 (1 MHz) + 4 - - - - PIN31 - Pin 31 - 31 - 31 - - read - Low - Read: pin driver is low - 0 + DIV_32 + Divide by 32 (500 kHz) + 5 - High - Read: pin driver is high - 1 + DIV_64 + Divide by 64 (250 kHz) + 6 - - - write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + DIV_128 + Divide by 128 (125 kHz) + 7 - IN - Read GPIO port + DECODER + Configuration of the decoder 0x510 - read-only + read-write + 0x00000000 - PIN0 - Pin 0 + LOAD + How a sequence is read from RAM and spread to the compare register 0 - 0 + 1 - Low - Pin input is low + Common + 1st half word (16-bit) used in all PWM channels 0..3 0 - High - Pin input is high + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 1 - - - - PIN1 - Pin 1 - 1 - 1 - - Low - Pin input is low - 0 + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 - High - Pin input is high - 1 + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 - PIN2 - Pin 2 - 2 - 2 + MODE + Selects source for advancing the active sequence + 8 + 8 - Low - Pin input is low + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers 0 - High - Pin input is high + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers 1 + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + - PIN3 - Pin 3 - 3 - 3 + CNT + Number of playbacks of pattern cycles + 0 + 15 - Low - Pin input is low + Disabled + Looping disabled (stop at the end of the sequence) 0 - - High - Pin input is high - 1 - + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + - PIN4 - Pin 4 - 4 - 4 + TASKS_START + Starts continuous PDM transfer + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high + Trigger + Trigger task 1 + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + - PIN5 - Pin 5 - 5 - 5 + TASKS_STOP + Stops PDM transfer + 0 + 0 - Low - Pin input is low - 0 - - - High - Pin input is high + Trigger + Trigger task 1 + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + - PIN6 - Pin 6 - 6 - 6 + EVENTS_STARTED + PDM transfer has started + 0 + 0 - Low - Pin input is low + NotGenerated + Event not generated 0 - High - Pin input is high + Generated + Event generated 1 + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + - PIN7 - Pin 7 - 7 - 7 + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 - Low - Pin input is low + NotGenerated + Event not generated 0 - High - Pin input is high + Generated + Event generated 1 + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + - PIN8 - Pin 8 - 8 - 8 + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 - Low - Pin input is low + NotGenerated + Event not generated 0 - High - Pin input is high + Generated + Event generated 1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - PIN9 - Pin 9 - 9 - 9 + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 - Low - Pin input is low + Disabled + Disable 0 - High - Pin input is high + Enabled + Enable 1 - PIN10 - Pin 10 - 10 - 10 + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 - Low - Pin input is low + Disabled + Disable 0 - High - Pin input is high + Enabled + Enable 1 - PIN11 - Pin 11 - 11 - 11 + END + Enable or disable interrupt for event END + 2 + 2 - Low - Pin input is low + Disabled + Disable 0 - High - Pin input is high + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PIN12 - Pin 12 - 12 - 12 + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN13 - Pin 13 - 13 - 13 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN14 - Pin 14 - 14 - 14 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - PIN15 - Pin 15 - 15 - 15 + END + Write '1' to enable interrupt for event END + 2 + 2 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN16 - Pin 16 - 16 - 16 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PIN17 - Pin 17 - 17 - 17 + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN18 - Pin 18 - 18 - 18 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Clear + Disable 1 - PIN19 - Pin 19 - 19 - 19 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN20 - Pin 20 - 20 - 20 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Clear + Disable 1 - PIN21 - Pin 21 - 21 - 21 + END + Write '1' to disable interrupt for event END + 2 + 2 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + - PIN22 - Pin 22 - 22 - 22 + ENABLE + Enable or disable PDM module + 0 + 0 - Low - Pin input is low + Disabled + Disable 0 - High - Pin input is high + Enabled + Enable 1 + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + - PIN23 - Pin 23 - 23 - 23 + FREQ + PDM_CLK frequency + 0 + 31 - Low - Pin input is low - 0 + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 - High - Pin input is high - 1 + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + - PIN24 - Pin 24 - 24 - 24 + OPERATION + Mono or stereo operation + 0 + 0 - Low - Pin input is low + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] 0 - High - Pin input is high + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] 1 - PIN25 - Pin 25 - 25 - 25 + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 - Low - Pin input is low + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK 0 - High - Pin input is high + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK 1 + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + - PIN26 - Pin 26 - 26 - 26 + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 - Low - Pin input is low - 0 + MinGain + -20dB gain adjustment (minimum) + 0x00 - High - Pin input is high - 1 + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + - PIN27 - Pin 27 - 27 - 27 + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 7 - Low - Pin input is low - 0 + MinGain + -20dB gain adjustment (minimum) + 0x00 - High - Pin input is high - 1 + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + NVMC + Non-volatile memory controller + 0x4001E000 + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + - PIN28 - Pin 28 - 28 - 28 + READY + NVMC is ready or busy + 0 + 0 - Low - Pin input is low + Busy + NVMC is busy (ongoing write or erase operation) 0 - High - Pin input is high + Ready + NVMC is ready 1 + + + + CONFIG + Configuration register + 0x504 + read-write + - PIN29 - Pin 29 - 29 - 29 + WEN + Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. + 0 + 1 - Low - Pin input is low + Ren + Read only access 0 - High - Pin input is high + Wen + Write enabled 1 + + Een + Erase enabled + 2 + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in code area. + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + - PIN30 - Pin 30 - 30 - 30 + ERASEALL + Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 - Low - Pin input is low + NoOperation + No operation 0 - High - Pin input is high + Erase + Start erase of chip 1 + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x510 + read-write + - PIN31 - Pin 31 - 31 + ERASEPCR0 + Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + 0 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 - Low - Pin input is low + NoOperation + No operation 0 - High - Pin input is high + Erase + Start erase of UICR 1 @@ -28643,583 +33041,677 @@ POSSIBILITY OF SUCH DAMAGE.\n - DIR - Direction of GPIO pins - 0x514 + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 read-write - PIN0 - Pin 0 + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 0 0 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN1 - Pin 1 + CH1 + Enable or disable channel 1 1 1 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN2 - Pin 2 + CH2 + Enable or disable channel 2 2 2 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN3 - Pin 3 + CH3 + Enable or disable channel 3 3 3 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN4 - Pin 4 + CH4 + Enable or disable channel 4 4 4 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN5 - Pin 5 + CH5 + Enable or disable channel 5 5 5 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN6 - Pin 6 + CH6 + Enable or disable channel 6 6 6 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN7 - Pin 7 + CH7 + Enable or disable channel 7 7 7 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN8 - Pin 8 + CH8 + Enable or disable channel 8 8 8 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN9 - Pin 9 + CH9 + Enable or disable channel 9 9 9 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN10 - Pin 10 + CH10 + Enable or disable channel 10 10 10 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN11 - Pin 11 + CH11 + Enable or disable channel 11 11 11 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN12 - Pin 12 + CH12 + Enable or disable channel 12 12 12 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN13 - Pin 13 + CH13 + Enable or disable channel 13 13 13 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN14 - Pin 14 + CH14 + Enable or disable channel 14 14 14 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN15 - Pin 15 + CH15 + Enable or disable channel 15 15 15 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN16 - Pin 16 + CH16 + Enable or disable channel 16 16 16 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN17 - Pin 17 + CH17 + Enable or disable channel 17 17 17 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN18 - Pin 18 + CH18 + Enable or disable channel 18 18 18 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN19 - Pin 19 + CH19 + Enable or disable channel 19 19 19 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN20 - Pin 20 + CH20 + Enable or disable channel 20 20 20 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN21 - Pin 21 + CH21 + Enable or disable channel 21 21 21 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN22 - Pin 22 + CH22 + Enable or disable channel 22 22 22 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN23 - Pin 23 + CH23 + Enable or disable channel 23 23 23 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN24 - Pin 24 + CH24 + Enable or disable channel 24 24 24 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN25 - Pin 25 + CH25 + Enable or disable channel 25 25 25 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN26 - Pin 26 + CH26 + Enable or disable channel 26 26 26 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN27 - Pin 27 + CH27 + Enable or disable channel 27 27 27 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN28 - Pin 28 + CH28 + Enable or disable channel 28 28 28 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN29 - Pin 29 + CH29 + Enable or disable channel 29 29 29 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN30 - Pin 30 + CH30 + Enable or disable channel 30 30 30 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 - PIN31 - Pin 31 + CH31 + Enable or disable channel 31 31 31 - Input - Pin set as input + Disabled + Disable channel 0 - Output - Pin set as output + Enabled + Enable channel 1 @@ -29227,27 +33719,27 @@ POSSIBILITY OF SUCH DAMAGE.\n - DIRSET - DIR set register - 0x518 + CHENSET + Channel enable set register + 0x504 read-write oneToSet - PIN0 - Set as output pin 0 + CH0 + Channel 0 enable set register. Writing '0' has no effect 0 0 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29255,26 +33747,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN1 - Set as output pin 1 + CH1 + Channel 1 enable set register. Writing '0' has no effect 1 1 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29282,26 +33774,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN2 - Set as output pin 2 + CH2 + Channel 2 enable set register. Writing '0' has no effect 2 2 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29309,26 +33801,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN3 - Set as output pin 3 + CH3 + Channel 3 enable set register. Writing '0' has no effect 3 3 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29336,26 +33828,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN4 - Set as output pin 4 + CH4 + Channel 4 enable set register. Writing '0' has no effect 4 4 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29363,26 +33855,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN5 - Set as output pin 5 + CH5 + Channel 5 enable set register. Writing '0' has no effect 5 5 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29390,26 +33882,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN6 - Set as output pin 6 + CH6 + Channel 6 enable set register. Writing '0' has no effect 6 6 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29417,26 +33909,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN7 - Set as output pin 7 + CH7 + Channel 7 enable set register. Writing '0' has no effect 7 7 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29444,26 +33936,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN8 - Set as output pin 8 + CH8 + Channel 8 enable set register. Writing '0' has no effect 8 8 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29471,26 +33963,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN9 - Set as output pin 9 + CH9 + Channel 9 enable set register. Writing '0' has no effect 9 9 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29498,26 +33990,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN10 - Set as output pin 10 + CH10 + Channel 10 enable set register. Writing '0' has no effect 10 10 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29525,26 +34017,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN11 - Set as output pin 11 + CH11 + Channel 11 enable set register. Writing '0' has no effect 11 11 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29552,26 +34044,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN12 - Set as output pin 12 + CH12 + Channel 12 enable set register. Writing '0' has no effect 12 12 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29579,26 +34071,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN13 - Set as output pin 13 + CH13 + Channel 13 enable set register. Writing '0' has no effect 13 13 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29606,26 +34098,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN14 - Set as output pin 14 + CH14 + Channel 14 enable set register. Writing '0' has no effect 14 14 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29633,26 +34125,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN15 - Set as output pin 15 + CH15 + Channel 15 enable set register. Writing '0' has no effect 15 15 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29660,26 +34152,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN16 - Set as output pin 16 + CH16 + Channel 16 enable set register. Writing '0' has no effect 16 16 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29687,26 +34179,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN17 - Set as output pin 17 + CH17 + Channel 17 enable set register. Writing '0' has no effect 17 17 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29714,26 +34206,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN18 - Set as output pin 18 + CH18 + Channel 18 enable set register. Writing '0' has no effect 18 18 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29741,26 +34233,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN19 - Set as output pin 19 + CH19 + Channel 19 enable set register. Writing '0' has no effect 19 19 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29768,26 +34260,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN20 - Set as output pin 20 + CH20 + Channel 20 enable set register. Writing '0' has no effect 20 20 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29795,26 +34287,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN21 - Set as output pin 21 + CH21 + Channel 21 enable set register. Writing '0' has no effect 21 21 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29822,26 +34314,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN22 - Set as output pin 22 + CH22 + Channel 22 enable set register. Writing '0' has no effect 22 22 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29849,26 +34341,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN23 - Set as output pin 23 + CH23 + Channel 23 enable set register. Writing '0' has no effect 23 23 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29876,26 +34368,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN24 - Set as output pin 24 + CH24 + Channel 24 enable set register. Writing '0' has no effect 24 24 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29903,26 +34395,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN25 - Set as output pin 25 + CH25 + Channel 25 enable set register. Writing '0' has no effect 25 25 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29930,26 +34422,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN26 - Set as output pin 26 + CH26 + Channel 26 enable set register. Writing '0' has no effect 26 26 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29957,26 +34449,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN27 - Set as output pin 27 + CH27 + Channel 27 enable set register. Writing '0' has no effect 27 27 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -29984,26 +34476,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN28 - Set as output pin 28 + CH28 + Channel 28 enable set register. Writing '0' has no effect 28 28 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30011,26 +34503,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN29 - Set as output pin 29 + CH29 + Channel 29 enable set register. Writing '0' has no effect 29 29 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30038,26 +34530,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN30 - Set as output pin 30 + CH30 + Channel 30 enable set register. Writing '0' has no effect 30 30 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30065,26 +34557,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 - PIN31 - Set as output pin 31 + CH31 + Channel 31 enable set register. Writing '0' has no effect 31 31 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30092,7 +34584,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: Enable channel 1 @@ -30100,27 +34592,27 @@ POSSIBILITY OF SUCH DAMAGE.\n - DIRCLR - DIR clear register - 0x51C + CHENCLR + Channel enable clear register + 0x508 read-write oneToClear - PIN0 - Set as input pin 0 + CH0 + Channel 0 enable clear register. Writing '0' has no effect 0 0 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30128,26 +34620,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN1 - Set as input pin 1 + CH1 + Channel 1 enable clear register. Writing '0' has no effect 1 1 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30155,26 +34647,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN2 - Set as input pin 2 + CH2 + Channel 2 enable clear register. Writing '0' has no effect 2 2 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30182,26 +34674,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN3 - Set as input pin 3 + CH3 + Channel 3 enable clear register. Writing '0' has no effect 3 3 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30209,26 +34701,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN4 - Set as input pin 4 + CH4 + Channel 4 enable clear register. Writing '0' has no effect 4 4 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30236,26 +34728,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN5 - Set as input pin 5 + CH5 + Channel 5 enable clear register. Writing '0' has no effect 5 5 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30263,26 +34755,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN6 - Set as input pin 6 + CH6 + Channel 6 enable clear register. Writing '0' has no effect 6 6 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30290,26 +34782,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN7 - Set as input pin 7 + CH7 + Channel 7 enable clear register. Writing '0' has no effect 7 7 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30317,26 +34809,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN8 - Set as input pin 8 + CH8 + Channel 8 enable clear register. Writing '0' has no effect 8 8 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30344,26 +34836,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN9 - Set as input pin 9 + CH9 + Channel 9 enable clear register. Writing '0' has no effect 9 9 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30371,26 +34863,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN10 - Set as input pin 10 + CH10 + Channel 10 enable clear register. Writing '0' has no effect 10 10 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30398,26 +34890,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN11 - Set as input pin 11 + CH11 + Channel 11 enable clear register. Writing '0' has no effect 11 11 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30425,26 +34917,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN12 - Set as input pin 12 + CH12 + Channel 12 enable clear register. Writing '0' has no effect 12 12 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30452,26 +34944,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN13 - Set as input pin 13 + CH13 + Channel 13 enable clear register. Writing '0' has no effect 13 13 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30479,26 +34971,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN14 - Set as input pin 14 + CH14 + Channel 14 enable clear register. Writing '0' has no effect 14 14 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30506,26 +34998,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN15 - Set as input pin 15 + CH15 + Channel 15 enable clear register. Writing '0' has no effect 15 15 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30533,26 +35025,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN16 - Set as input pin 16 + CH16 + Channel 16 enable clear register. Writing '0' has no effect 16 16 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30560,26 +35052,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN17 - Set as input pin 17 + CH17 + Channel 17 enable clear register. Writing '0' has no effect 17 17 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30587,26 +35079,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN18 - Set as input pin 18 + CH18 + Channel 18 enable clear register. Writing '0' has no effect 18 18 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30614,26 +35106,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN19 - Set as input pin 19 + CH19 + Channel 19 enable clear register. Writing '0' has no effect 19 19 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30641,26 +35133,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN20 - Set as input pin 20 + CH20 + Channel 20 enable clear register. Writing '0' has no effect 20 20 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30668,26 +35160,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN21 - Set as input pin 21 + CH21 + Channel 21 enable clear register. Writing '0' has no effect 21 21 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30695,26 +35187,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN22 - Set as input pin 22 + CH22 + Channel 22 enable clear register. Writing '0' has no effect 22 22 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30722,26 +35214,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN23 - Set as input pin 23 + CH23 + Channel 23 enable clear register. Writing '0' has no effect 23 23 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30749,26 +35241,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN24 - Set as input pin 24 + CH24 + Channel 24 enable clear register. Writing '0' has no effect 24 24 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30776,26 +35268,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN25 - Set as input pin 25 + CH25 + Channel 25 enable clear register. Writing '0' has no effect 25 25 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30803,26 +35295,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN26 - Set as input pin 26 + CH26 + Channel 26 enable clear register. Writing '0' has no effect 26 26 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30830,26 +35322,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN27 - Set as input pin 27 + CH27 + Channel 27 enable clear register. Writing '0' has no effect 27 27 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30857,26 +35349,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN28 - Set as input pin 28 + CH28 + Channel 28 enable clear register. Writing '0' has no effect 28 28 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30884,26 +35376,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN29 - Set as input pin 29 + CH29 + Channel 29 enable clear register. Writing '0' has no effect 29 29 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30911,26 +35403,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN30 - Set as input pin 30 + CH30 + Channel 30 enable clear register. Writing '0' has no effect 30 30 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30938,26 +35430,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 - PIN31 - Set as input pin 31 + CH31 + Channel 31 enable clear register. Writing '0' has no effect 31 31 read - Input - Read: pin set as input + Disabled + Read: channel disabled 0 - Output - Read: pin set as output + Enabled + Read: channel enabled 1 @@ -30965,764 +35457,659 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: disable channel 1 + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x520 + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 read-write - PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + CH0 + Include or exclude channel 0 0 0 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + CH1 + Include or exclude channel 1 1 1 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + CH2 + Include or exclude channel 2 2 2 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + CH3 + Include or exclude channel 3 3 3 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + CH4 + Include or exclude channel 4 4 4 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + CH5 + Include or exclude channel 5 5 5 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + CH6 + Include or exclude channel 6 6 6 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + CH7 + Include or exclude channel 7 7 7 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + CH8 + Include or exclude channel 8 8 8 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + CH9 + Include or exclude channel 9 9 9 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + CH10 + Include or exclude channel 10 10 10 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + CH11 + Include or exclude channel 11 11 11 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + CH12 + Include or exclude channel 12 12 12 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + CH13 + Include or exclude channel 13 13 13 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + CH14 + Include or exclude channel 14 14 14 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + CH15 + Include or exclude channel 15 15 15 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + CH16 + Include or exclude channel 16 16 16 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + CH17 + Include or exclude channel 17 17 17 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + CH18 + Include or exclude channel 18 18 18 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + CH19 + Include or exclude channel 19 19 19 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + CH20 + Include or exclude channel 20 20 20 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + CH21 + Include or exclude channel 21 21 21 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + CH22 + Include or exclude channel 22 22 22 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + CH23 + Include or exclude channel 23 23 23 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + CH24 + Include or exclude channel 24 24 24 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + CH25 + Include or exclude channel 25 25 25 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + CH26 + Include or exclude channel 26 26 26 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + CH27 + Include or exclude channel 27 27 27 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + CH28 + Include or exclude channel 28 28 28 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + CH29 + Include or exclude channel 29 29 29 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + CH30 + Include or exclude channel 30 30 30 - NotLatched - Criteria has not been met + Excluded + Exclude 0 - Latched - Criteria has been met + Included + Include 1 - PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + CH31 + Include or exclude channel 31 31 31 - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - - - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0x524 - read-write - - - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals + Excluded + Exclude 0 - LDETECT - Use the latched LDETECT behaviour + Included + Include 1 - - 0x20 - 0x4 - PIN_CNF[%s] - Description collection[n]: Configuration of GPIO pins - 0x700 + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK read-write - 0x00000002 - - - DIR - Pin direction. Same physical register as DIR register - 0 - 0 - - - Input - Configure pin as an input pin - 0 - - - Output - Configure pin as an output pin - 1 - - - - - INPUT - Connect or disconnect input buffer - 1 - 1 - - - Connect - Connect input buffer - 0 - - - Disconnect - Disconnect input buffer - 1 - - - - - PULL - Pull configuration - 2 - 3 - - - Disabled - No pull - 0 - - - Pulldown - Pull down on pin - 1 - - - Pullup - Pull up on pin - 3 - - - - - DRIVE - Drive configuration - 8 - 10 - - - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' - 1 - - - S0H1 - Standard '0', high drive '1' - 2 - - - H0H1 - High drive '0', high 'drive '1'' - 3 - - - D0S1 - Disconnect '0' standard '1' (normally used for wired-or connections) - 4 - - - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 - - - S0D1 - Standard '0'. disconnect '1' (normally used for wired-and connections) - 6 - - - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) - 7 - - - - - SENSE - Pin sensing mechanism - 16 - 17 - - - Disabled - Disabled - 0 - - - High - Sense for high level - 2 - - - Low - Sense for low level - 3 - - - - - + 0x910 + + TEP + Description cluster: Channel n task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + diff --git a/mdk/nrf52810_bitfields.h b/mdk/nrf52810_bitfields.h index fa1980b11..fcd2fc346 100644 --- a/mdk/nrf52810_bitfields.h +++ b/mdk/nrf52810_bitfields.h @@ -41,56 +41,64 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_TASKS_START */ /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ -/* Bit 0 : */ +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_TASKS_STOP */ /* Description: Stop resolving addresses */ -/* Bit 0 : */ +/* Bit 0 : Stop resolving addresses */ #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_EVENTS_END */ /* Description: Address resolution procedure complete */ -/* Bit 0 : */ +/* Bit 0 : Address resolution procedure complete */ #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_RESOLVED */ /* Description: Address resolved */ -/* Bit 0 : */ +/* Bit 0 : Address resolved */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_NOTRESOLVED */ /* Description: Address not resolved */ -/* Bit 0 : */ +/* Bit 0 : Address not resolved */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for END event */ +/* Bit 0 : Write '1' to enable interrupt for event END */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -100,21 +108,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for END event */ +/* Bit 0 : Write '1' to disable interrupt for event END */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -479,56 +487,66 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of key-stream. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_CRYPT */ /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_STOP */ /* Description: Stop encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Stop encryption/decryption */ #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_RATEOVERRIDE */ /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ /* Description: Key-stream generation complete */ -/* Bit 0 : */ +/* Bit 0 : Key-stream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ENDCRYPT */ /* Description: Encrypt/decrypt complete */ -/* Bit 0 : */ +/* Bit 0 : Encrypt/decrypt complete */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ERROR */ /* Description: Deprecated register - CCM error event */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - CCM error event */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: CCM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ @@ -537,21 +555,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -561,21 +579,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -677,105 +695,120 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_TASKS_HFCLKSTART */ /* Description: Start HFCLK crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Start HFCLK crystal oscillator */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ /* Description: Stop HFCLK crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Stop HFCLK crystal oscillator */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTART */ /* Description: Start LFCLK source */ -/* Bit 0 : */ +/* Bit 0 : Start LFCLK source */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTOP */ /* Description: Stop LFCLK source */ -/* Bit 0 : */ +/* Bit 0 : Stop LFCLK source */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CAL */ /* Description: Start calibration of LFRC oscillator */ -/* Bit 0 : */ +/* Bit 0 : Start calibration of LFRC oscillator */ #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTART */ /* Description: Start calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Start calibration timer */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTOP */ /* Description: Stop calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Stop calibration timer */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFCLK oscillator started */ -/* Bit 0 : */ +/* Bit 0 : HFCLK oscillator started */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_LFCLKSTARTED */ /* Description: LFCLK started */ -/* Bit 0 : */ +/* Bit 0 : LFCLK started */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_DONE */ /* Description: Calibration of LFCLK RC oscillator complete event */ -/* Bit 0 : */ +/* Bit 0 : Calibration of LFCLK RC oscillator complete event */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTTO */ /* Description: Calibration timer timeout */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer timeout */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DONE event */ +/* Bit 3 : Write '1' to enable interrupt for event DONE */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -785,28 +818,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DONE event */ +/* Bit 3 : Write '1' to disable interrupt for event DONE */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -908,80 +941,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_EVENTS_READY */ /* Description: COMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : COMP is ready and output is valid */ #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: COMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -990,25 +1034,25 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 3 : Enable or disable interrupt for CROSS event */ +/* Bit 3 : Enable or disable interrupt for event CROSS */ #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for UP event */ +/* Bit 2 : Enable or disable interrupt for event UP */ #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for DOWN event */ +/* Bit 1 : Enable or disable interrupt for event DOWN */ #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -1017,28 +1061,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1048,28 +1092,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1179,42 +1223,48 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_TASKS_STARTECB */ /* Description: Start ECB block encrypt */ -/* Bit 0 : */ +/* Bit 0 : Start ECB block encrypt */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_TASKS_STOPECB */ /* Description: Abort a possible executing ECB operation */ -/* Bit 0 : */ +/* Bit 0 : Abort a possible executing ECB operation */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_EVENTS_ENDECB */ /* Description: ECB block encrypt complete */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt complete */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_EVENTS_ERRORECB */ /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1224,14 +1274,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1250,113 +1300,116 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Event Generator Unit 0 */ /* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ -/* Bit 0 : */ +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ /* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ -/* Bit 0 : */ +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ @@ -1365,112 +1418,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1480,112 +1533,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1611,21 +1664,21 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection[n]: Device identifier */ +/* Description: Description collection: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection[n]: Encryption root, word n */ +/* Description: Description collection: Encryption root, word n */ /* Bits 31..0 : Encryption root, word n */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection[n]: Identity root, word n */ +/* Description: Description collection: Identity root, word n */ /* Bits 31..0 : Identity root, word n */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ @@ -1641,7 +1694,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection[n]: Device address n */ +/* Description: Description collection: Device address n */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1824,100 +1877,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: GPIO Tasks and Events */ /* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ -/* Bit 0 : */ +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_EVENTS_PORT */ /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ -/* Bit 0 : */ +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to enable interrupt for PORT event */ +/* Bit 31 : Write '1' to enable interrupt for event PORT */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1927,63 +1987,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to disable interrupt for PORT event */ +/* Bit 31 : Write '1' to disable interrupt for event PORT */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1991,7 +2051,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -3796,7 +3856,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection[n]: Configuration of GPIO pins */ +/* Description: Description collection: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -3843,54 +3903,62 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_TASKS_START */ /* Description: Starts continuous PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous PDM transfer */ #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_TASKS_STOP */ /* Description: Stops PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Stops PDM transfer */ #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_EVENTS_STARTED */ /* Description: PDM transfer has started */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has started */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_STOPPED */ /* Description: PDM transfer has finished */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has finished */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_END */ /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ -/* Bit 0 : */ +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 2 : Enable or disable interrupt for END event */ +/* Bit 2 : Enable or disable interrupt for event END */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -3899,21 +3967,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for END event */ +/* Bit 2 : Write '1' to enable interrupt for event END */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -3923,21 +3991,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for END event */ +/* Bit 2 : Write '1' to disable interrupt for event END */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -4045,56 +4113,64 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_TASKS_CONSTLAT */ /* Description: Enable constant latency mode */ -/* Bit 0 : */ +/* Bit 0 : Enable constant latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ /* Description: Enable low power mode (variable latency) */ -/* Bit 0 : */ +/* Bit 0 : Enable low power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_EVENTS_POFWARN */ /* Description: Power failure warning */ -/* Bit 0 : */ +/* Bit 0 : Power failure warning */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPENTER */ /* Description: CPU entered WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU entered WFI/WFE sleep */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPEXIT */ /* Description: CPU exited WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU exited WFI/WFE sleep */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -4104,21 +4180,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -4221,7 +4297,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster[n]: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ +/* Description: Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ @@ -4248,7 +4324,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[n]: RAMn power control set register */ +/* Description: Description cluster: RAMn power control set register */ /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ @@ -4271,7 +4347,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[n]: RAMn power control clear register */ +/* Description: Description cluster: RAMn power control clear register */ /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ @@ -4298,18 +4374,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Programmable Peripheral Interconnect */ /* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster[n]: Enable channel group n */ +/* Description: Description cluster: Enable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Enable channel group n */ #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster[n]: Disable channel group n */ +/* Description: Description cluster: Disable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Disable channel group n */ #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_CHEN */ /* Description: Channel enable register */ @@ -4961,21 +5039,21 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster[n]: Channel n event end-point */ +/* Description: Description cluster: Channel n event end-point */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection[n]: Channel group n */ +/* Description: Description collection: Channel group n */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -5170,7 +5248,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -5183,87 +5261,100 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_TASKS_STOP */ /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ -/* Bit 0 : */ +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_NEXTSTEP */ /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_EVENTS_STOPPED */ /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ -/* Bit 0 : */ +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection[n]: First PWM period started on sequence n */ +/* Description: Description collection: First PWM period started on sequence n */ -/* Bit 0 : */ +/* Bit 0 : First PWM period started on sequence n */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ -/* Bit 0 : */ +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_PWMPERIODEND */ /* Description: Emitted at the end of each PWM period */ -/* Bit 0 : */ +/* Bit 0 : Emitted at the end of each PWM period */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_LOOPSDONE */ /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ -/* Bit 0 : */ +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ /* Register: PWM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -5272,43 +5363,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -5317,49 +5408,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -5369,49 +5460,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -5484,14 +5575,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ /* Bits 31..0 : Beginning address in RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -5499,7 +5590,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -5507,14 +5598,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[n]: Time added after the sequence */ +/* Description: Description cluster: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection[n]: Output pin select for PWM channel n */ +/* Description: Description collection: Output pin select for PWM channel n */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -5533,113 +5624,128 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_TASKS_START */ /* Description: Task starting the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task starting the quadrature decoder */ #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_STOP */ /* Description: Task stopping the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the quadrature decoder */ #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_READCLRACC */ /* Description: Read and clear ACC and ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC and ACCDBL */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRACC */ /* Description: Read and clear ACC */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRDBL */ /* Description: Read and clear ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACCDBL */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_EVENTS_SAMPLERDY */ /* Description: Event being generated for every new sample value written to the SAMPLE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_REPORTRDY */ /* Description: Non-null report ready */ -/* Bit 0 : */ +/* Bit 0 : Non-null report ready */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_ACCOF */ /* Description: ACC or ACCDBL register overflow */ -/* Bit 0 : */ +/* Bit 0 : ACC or ACCDBL register overflow */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_DBLRDY */ /* Description: Double displacement(s) detected */ -/* Bit 0 : */ +/* Bit 0 : Double displacement(s) detected */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_STOPPED */ /* Description: QDEC has been stopped */ -/* Bit 0 : */ +/* Bit 0 : QDEC has been stopped */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ @@ -5648,35 +5754,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -5686,35 +5792,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -5870,189 +5976,220 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TASKS_TXEN */ /* Description: Enable RADIO in TX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in TX mode */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RXEN */ /* Description: Enable RADIO in RX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in RX mode */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_START */ /* Description: Start RADIO */ -/* Bit 0 : */ +/* Bit 0 : Start RADIO */ #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_STOP */ /* Description: Stop RADIO */ -/* Bit 0 : */ +/* Bit 0 : Stop RADIO */ #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_DISABLE */ /* Description: Disable RADIO */ -/* Bit 0 : */ +/* Bit 0 : Disable RADIO */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTART */ /* Description: Start the RSSI and take one single sample of the receive signal strength. */ -/* Bit 0 : */ +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength. */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTOP */ /* Description: Stop the RSSI measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the RSSI measurement */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTART */ /* Description: Start the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Start the bit counter */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTOP */ /* Description: Stop the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Stop the bit counter */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_EVENTS_READY */ /* Description: RADIO has ramped up and is ready to be started */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started */ #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_ADDRESS */ /* Description: Address sent or received */ -/* Bit 0 : */ +/* Bit 0 : Address sent or received */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PAYLOAD */ /* Description: Packet payload sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet payload sent or received */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_END */ /* Description: Packet sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet sent or received */ #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DISABLED */ /* Description: RADIO has been disabled */ -/* Bit 0 : */ +/* Bit 0 : RADIO has been disabled */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMATCH */ /* Description: A device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : A device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMISS */ /* Description: No device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : No device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RSSIEND */ /* Description: Sampling of receive signal strength complete. */ -/* Bit 0 : */ +/* Bit 0 : Sampling of receive signal strength complete. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_BCMATCH */ /* Description: Bit counter reached bit count value. */ -/* Bit 0 : */ +/* Bit 0 : Bit counter reached bit count value. */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCOK */ /* Description: Packet received with CRC ok */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC ok */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCERROR */ /* Description: Packet received with CRC error */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC error */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between END event and START task */ +/* Bit 5 : Shortcut between event END and task START */ #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between END event and DISABLE task */ +/* Bit 1 : Shortcut between event END and task DISABLE */ #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and START task */ +/* Bit 0 : Shortcut between event READY and task START */ #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ @@ -6061,77 +6198,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for END event */ +/* Bit 3 : Write '1' to enable interrupt for event END */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -6141,77 +6278,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for END event */ +/* Bit 3 : Write '1' to disable interrupt for event END */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -6278,12 +6415,12 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -6536,14 +6673,14 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection[n]: Device address base segment n */ +/* Description: Description collection: Device address base segment n */ /* Bits 31..0 : Device address base segment n */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection[n]: Device address prefix n */ +/* Description: Description collection: Device address prefix n */ /* Bits 15..0 : Device address prefix n */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ @@ -6664,28 +6801,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_TASKS_START */ /* Description: Task starting the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task starting the random number generator */ #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_TASKS_STOP */ /* Description: Task stopping the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the random number generator */ #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_EVENTS_VALRDY */ /* Description: Event being generated for every new random number written to the VALUE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ /* Register: RNG_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between VALRDY event and STOP task */ +/* Bit 0 : Shortcut between event VALRDY and task STOP */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -6694,7 +6835,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -6704,7 +6845,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -6734,91 +6875,101 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_TASKS_START */ /* Description: Start RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Start RTC COUNTER */ #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_STOP */ /* Description: Stop RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Stop RTC COUNTER */ #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_CLEAR */ /* Description: Clear RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Clear RTC COUNTER */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_TRIGOVRFLW */ /* Description: Set COUNTER to 0xFFFFF0 */ -/* Bit 0 : */ +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_EVENTS_TICK */ /* Description: Event on COUNTER increment */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER increment */ #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_OVRFLW */ /* Description: Event on COUNTER overflow */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER overflow */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TICK event */ +/* Bit 0 : Write '1' to enable interrupt for event TICK */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -6828,42 +6979,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TICK event */ +/* Bit 0 : Write '1' to disable interrupt for event TICK */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -6873,81 +7024,81 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ -/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ -/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ -/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ -/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ -/* Bit 1 : Enable or disable event routing for OVRFLW event */ +/* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ -/* Bit 0 : Enable or disable event routing for TICK event */ +/* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable event routing for TICK event */ +/* Bit 0 : Write '1' to enable event routing for event TICK */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -6957,42 +7108,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable event routing for TICK event */ +/* Bit 0 : Write '1' to disable event routing for event TICK */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -7014,7 +7165,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection[n]: Compare register n */ +/* Description: Description collection: Compare register n */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -7027,217 +7178,237 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_TASKS_START */ /* Description: Start the ADC and prepare the result buffer in RAM */ -/* Bit 0 : */ +/* Bit 0 : Start the ADC and prepare the result buffer in RAM */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_SAMPLE */ /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ -/* Bit 0 : */ +/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ /* Description: Stop the ADC and terminate any on-going conversion */ -/* Bit 0 : */ +/* Bit 0 : Stop the ADC and terminate any on-going conversion */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_CALIBRATEOFFSET */ /* Description: Starts offset auto-calibration */ -/* Bit 0 : */ +/* Bit 0 : Starts offset auto-calibration */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_EVENTS_STARTED */ /* Description: The ADC has started */ -/* Bit 0 : */ +/* Bit 0 : The ADC has started */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_END */ /* Description: The ADC has filled up the Result buffer */ -/* Bit 0 : */ +/* Bit 0 : The ADC has filled up the Result buffer */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_DONE */ /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ -/* Bit 0 : */ +/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ /* Description: A result is ready to get transferred to RAM. */ -/* Bit 0 : */ +/* Bit 0 : A result is ready to get transferred to RAM. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CALIBRATEDONE */ /* Description: Calibration is complete */ -/* Bit 0 : */ +/* Bit 0 : Calibration is complete */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_STOPPED */ /* Description: The ADC has stopped */ -/* Bit 0 : */ +/* Bit 0 : The ADC has stopped */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster[n]: Last results is equal or above CH[n].LIMIT.HIGH */ +/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ -/* Bit 0 : */ +/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster[n]: Last results is equal or below CH[n].LIMIT.LOW */ +/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ -/* Bit 0 : */ +/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for STOPPED event */ +/* Bit 5 : Enable or disable interrupt for event STOPPED */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for DONE event */ +/* Bit 2 : Enable or disable interrupt for event DONE */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for END event */ +/* Bit 1 : Enable or disable interrupt for event END */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -7246,154 +7417,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for DONE event */ +/* Bit 2 : Write '1' to enable interrupt for event DONE */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -7403,154 +7574,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for DONE event */ +/* Bit 2 : Write '1' to disable interrupt for event DONE */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -7576,7 +7747,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -7593,7 +7764,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -7610,7 +7781,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[n]: Input configuration for CH[n] */ +/* Description: Description cluster: Input configuration for CH[n] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -7669,7 +7840,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[n]: High/low limits for event monitoring a channel */ +/* Description: Description cluster: High/low limits for event monitoring a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -7741,76 +7912,220 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface */ + +/* Register: SPI_EVENTS_READY */ +/* Description: TXD byte sent and RXD byte received */ + +/* Bit 0 : TXD byte sent and RXD byte received */ +#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event READY */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event READY */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + /* Peripheral: SPIM */ /* Description: Serial Peripheral Interface Master with EasyDMA */ /* Register: SPIM_TASKS_START */ /* Description: Start SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Start SPI transaction */ #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_STOP */ /* Description: Stop SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop SPI transaction */ #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_SUSPEND */ /* Description: Suspend SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend SPI transaction */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_RESUME */ /* Description: Resume SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume SPI transaction */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_EVENTS_STOPPED */ /* Description: SPI transaction has stopped */ -/* Bit 0 : */ +/* Bit 0 : SPI transaction has stopped */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_END */ /* Description: End of RXD buffer and TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer and TXD buffer reached */ #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDTX */ /* Description: End of TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of TXD buffer reached */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_STARTED */ /* Description: Transaction started */ -/* Bit 0 : */ +/* Bit 0 : Transaction started */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 17 : Shortcut between END event and START task */ +/* Bit 17 : Shortcut between event END and task START */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ @@ -7819,35 +8134,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for END event */ +/* Bit 6 : Write '1' to enable interrupt for event END */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -7857,35 +8172,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for END event */ +/* Bit 6 : Write '1' to disable interrupt for event END */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -7978,9 +8293,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_RXD_LIST */ /* Description: EasyDMA list type */ -/* Bits 2..0 : List type */ +/* Bits 1..0 : List type */ #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ @@ -8008,9 +8323,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_TXD_LIST */ /* Description: EasyDMA list type */ -/* Bits 2..0 : List type */ +/* Bits 1..0 : List type */ #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ @@ -8049,42 +8364,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_TASKS_ACQUIRE */ /* Description: Acquire SPI semaphore */ -/* Bit 0 : */ +/* Bit 0 : Acquire SPI semaphore */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_TASKS_RELEASE */ /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ -/* Bit 0 : */ +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_EVENTS_END */ /* Description: Granted transaction completed */ -/* Bit 0 : */ +/* Bit 0 : Granted transaction completed */ #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ACQUIRED */ /* Description: Semaphore acquired */ -/* Bit 0 : */ +/* Bit 0 : Semaphore acquired */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ /* Register: SPIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 2 : Shortcut between END event and ACQUIRE task */ +/* Bit 2 : Shortcut between event END and task ACQUIRE */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ @@ -8093,21 +8416,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -8117,21 +8440,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -8248,6 +8571,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -8269,6 +8601,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -8311,28 +8652,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_TASKS_START */ /* Description: Start temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Start temperature measurement */ #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_TASKS_STOP */ /* Description: Stop temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop temperature measurement */ #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_EVENTS_DATARDY */ /* Description: Temperature measurement complete, data ready */ -/* Bit 0 : */ +/* Bit 0 : Temperature measurement complete, data ready */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -8342,7 +8687,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -8482,122 +8827,130 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_TASKS_START */ /* Description: Start Timer */ -/* Bit 0 : */ +/* Bit 0 : Start Timer */ #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_STOP */ /* Description: Stop Timer */ -/* Bit 0 : */ +/* Bit 0 : Stop Timer */ #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_COUNT */ /* Description: Increment Timer (Counter mode only) */ -/* Bit 0 : */ +/* Bit 0 : Increment Timer (Counter mode only) */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CLEAR */ /* Description: Clear time */ -/* Bit 0 : */ +/* Bit 0 : Clear time */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_SHUTDOWN */ /* Description: Deprecated register - Shut down timer */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - Shut down timer */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection[n]: Capture Timer value to CC[n] register */ +/* Description: Description collection: Capture Timer value to CC[n] register */ -/* Bit 0 : */ +/* Bit 0 : Capture Timer value to CC[n] register */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: TIMER_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ @@ -8606,42 +8959,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -8651,42 +9004,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -8722,134 +9075,443 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection[n]: Capture/Compare register n */ +/* Description: Description collection: Capture/Compare register n */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface */ + +/* Register: TWI_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_RXDREADY */ +/* Description: TWI RXD byte received */ + +/* Bit 0 : TWI RXD byte received */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_TXDSENT */ +/* Description: TWI TXD byte sent */ + +/* Bit 0 : TWI TXD byte sent */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_BB */ +/* Description: TWI byte boundary, generated before each byte that is sent or received */ + +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ +#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_SUSPENDED */ +/* Description: TWI entered the suspended state */ + +/* Bit 0 : TWI entered the suspended state */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 1 : Shortcut between event BB and task STOP */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event BB and task SUSPEND */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event BB */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event BB */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + /* Peripheral: TWIM */ /* Description: I2C compatible Two-Wire Master Interface with EasyDMA */ /* Register: TWIM_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STOP */ /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : */ +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTRX */ /* Description: Byte boundary, starting to receive the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to receive the last byte */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTTX */ /* Description: Byte boundary, starting to transmit the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to transmit the last byte */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 12 : Shortcut between LASTRX event and STOP task */ +/* Bit 12 : Shortcut between event LASTRX and task STOP */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between LASTTX event and STOP task */ +/* Bit 9 : Shortcut between event LASTTX and task STOP */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -8858,43 +9520,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for LASTTX event */ +/* Bit 24 : Enable or disable interrupt for event LASTTX */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for LASTRX event */ +/* Bit 23 : Enable or disable interrupt for event LASTRX */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -8903,49 +9565,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8955,49 +9617,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -9144,90 +9806,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARERX */ /* Description: Prepare the TWI slave to respond to a write command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a write command */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARETX */ /* Description: Prepare the TWI slave to respond to a read command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a read command */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_WRITE */ /* Description: Write command received */ -/* Bit 0 : */ +/* Bit 0 : Write command received */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_READ */ /* Description: Read command received */ -/* Bit 0 : */ +/* Bit 0 : Read command received */ #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ /* Register: TWIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 14 : Shortcut between READ event and SUSPEND task */ +/* Bit 14 : Shortcut between event READ and task SUSPEND */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -9236,37 +9915,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 26 : Enable or disable interrupt for READ event */ +/* Bit 26 : Enable or disable interrupt for event READ */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for WRITE event */ +/* Bit 25 : Enable or disable interrupt for event WRITE */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -9275,42 +9954,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to enable interrupt for READ event */ +/* Bit 26 : Write '1' to enable interrupt for event READ */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -9320,42 +9999,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to disable interrupt for READ event */ +/* Bit 26 : Write '1' to disable interrupt for event READ */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -9446,6 +10125,15 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -9467,8 +10155,17 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_ADDRESS */ -/* Description: Description collection[n]: TWI slave address n */ +/* Description: Description collection: TWI slave address n */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -9497,131 +10194,509 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_SUSPEND */ +/* Description: Suspend UART */ + +/* Bit 0 : Suspend UART */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXDRDY */ +/* Description: Data received in RXD */ + +/* Bit 0 : Data received in RXD */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event CTS and task STARTRX */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + /* Peripheral: UARTE */ /* Description: UART with EasyDMA */ /* Register: UARTE_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_FLUSHRX */ /* Description: Flush RX FIFO into RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Flush RX FIFO into RX buffer */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXDRDY */ /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDRX */ /* Description: Receive buffer is filled up */ -/* Bit 0 : */ +/* Bit 0 : Receive buffer is filled up */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDTX */ /* Description: Last TX byte transmitted */ -/* Bit 0 : */ +/* Bit 0 : Last TX byte transmitted */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXSTARTED */ /* Description: UART receiver has started */ -/* Bit 0 : */ +/* Bit 0 : UART receiver has started */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTARTED */ /* Description: UART transmitter has started */ -/* Bit 0 : */ +/* Bit 0 : UART transmitter has started */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTOPPED */ /* Description: Transmitter stopped */ -/* Bit 0 : */ +/* Bit 0 : Transmitter stopped */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -9630,67 +10705,67 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for RXTO event */ +/* Bit 17 : Enable or disable interrupt for event RXTO */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDTX event */ +/* Bit 8 : Enable or disable interrupt for event ENDTX */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDRX event */ +/* Bit 4 : Enable or disable interrupt for event ENDRX */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for NCTS event */ +/* Bit 1 : Enable or disable interrupt for event NCTS */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for CTS event */ +/* Bit 0 : Enable or disable interrupt for event CTS */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ @@ -9699,77 +10774,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -9779,77 +10854,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -10037,28 +11112,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: User information configuration registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection[n]: Reserved for Nordic firmware design */ +/* Description: Description collection: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection[n]: Reserved for Nordic hardware design */ +/* Description: Description collection: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection[n]: Reserved for customer */ +/* Description: Description collection: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection[n]: Mapping of the nRESET function (see POWER chapter for details) */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -10066,9 +11141,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bits 5..0 : GPIO number P0.n onto which reset is exposed */ +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ /* Description: Access port protection */ @@ -10086,21 +11161,24 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_TASKS_START */ /* Description: Start the watchdog */ -/* Bit 0 : */ +/* Bit 0 : Start the watchdog */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_EVENTS_TIMEOUT */ /* Description: Watchdog timeout */ -/* Bit 0 : */ +/* Bit 0 : Watchdog timeout */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -10110,7 +11188,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -10251,7 +11329,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection[n]: Reload request n */ +/* Description: Description collection: Reload request n */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/mdk/nrf52810_name_change.h b/mdk/nrf52810_name_change.h new file mode 100644 index 000000000..6f7f6360d --- /dev/null +++ b/mdk/nrf52810_name_change.h @@ -0,0 +1,55 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52810_NAME_CHANGE_H +#define NRF52810_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf52810.h and + * nrf52810_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf52810.h and nrf52810_bitfields.h instead. + */ + + /* IRQ */ + /* Changes of interrupt names */ + #define SPIM0_SPIS0_IRQn SPIM0_SPIS0_SPI0_IRQn + #define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_IRQn + #define UARTE0_IRQn UARTE0_UART0_IRQn + + #define SPIM0_SPIS0_IRQHandler SPIM0_SPIS0_SPI0_IRQHandler + #define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_IRQHandler + #define UARTE0_IRQHandler UARTE0_UART0_IRQHandler + + /*lint --flb "Leave library region" */ + +#endif /* NRF52810_NAME_CHANGE_H */ \ No newline at end of file diff --git a/mdk/nrf52810_peripherals.h b/mdk/nrf52810_peripherals.h index 2adfa6731..7d9c46344 100644 --- a/mdk/nrf52810_peripherals.h +++ b/mdk/nrf52810_peripherals.h @@ -132,6 +132,10 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_PRESENT #define TEMP_COUNT 1 +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 1 + /* Serial Peripheral Interface Master with DMA */ #define SPIM_PRESENT #define SPIM_COUNT 1 @@ -152,6 +156,10 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS0_EASYDMA_MAXCNT_SIZE 10 +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 1 + /* Two Wire Interface Master with DMA */ #define TWIM_PRESENT #define TWIM_COUNT 1 @@ -164,6 +172,10 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS0_EASYDMA_MAXCNT_SIZE 10 +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + /* Universal Asynchronous Receiver-Transmitter with DMA */ #define UARTE_PRESENT #define UARTE_COUNT 1 diff --git a/mdk/nrf52810_to_nrf52811.h b/mdk/nrf52810_to_nrf52811.h new file mode 100644 index 000000000..c31ddf3d5 --- /dev/null +++ b/mdk/nrf52810_to_nrf52811.h @@ -0,0 +1,59 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF52810_TO_NRF52811_H +#define NRF52810_TO_NRF52811_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the name changes between nRF52810 and nRF52811 devices. + * It redefines the old nRF52810 names into the new ones as long as the functionality is still supported. If the + * functionality is gone, there old names are not defined, so compilation will fail. */ + +/* Differences between latest nRF52810 headers and nRF52811 headers. */ + +/* Interrupt service routines handlers. */ +#ifndef TWIM0_TWIS0_IRQHandler + #define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_SPIM1_SPIS1_IRQHandler +#endif + + +/* Interrupt service routines index. */ +#ifndef TWIM0_TWIS0_IRQn + #define TWIM0_TWIS0_IRQn TWIM0_TWIS0_SPIM1_SPIS1_IRQn +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF52810_TO_NRF52811_H */ + diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h new file mode 100644 index 000000000..641c447d4 --- /dev/null +++ b/mdk/nrf52811.h @@ -0,0 +1,2043 @@ +/* + * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52811.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:39 + * from File 'nrf52811.svd', + * last modified on Thursday, 17.01.2019 16:25:35 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52811 + * @{ + */ + + +#ifndef NRF52811_H +#define NRF52811_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52811 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn= 3, /*!< 3 TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 */ + SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_IRQn = 19, /*!< 19 COMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_IRQn = 22, /*!< 22 SWI2 */ + SWI3_IRQn = 23, /*!< 23 SWI3 */ + SWI4_IRQn = 24, /*!< 24 SWI4 */ + SWI5_IRQn = 25, /*!< 25 SWI5 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29 /*!< 29 PDM */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 0 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 0 /*!< FPU present or not */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ +#include "system_nrf52811.h" /*!< nrf52811 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production + configuration */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. + The RAM size will vary depending on product + variant, and the RAMn register will only + be present if the corresponding RAM AHB + slave is present on the device. */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or + below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event + monitoring a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last + START */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ + __IM uint32_t RESERVED3[21]; + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[188]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ +} NRF_FICR_Type; /*!< Size = 1096 (0x448) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ +} NRF_UICR_Type; /*!< Size = 524 (0x20c) */ + + + +/* =========================================================================================================================== */ +/* ================ BPROT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Block Protect (BPROT) + */ + +typedef struct { /*!< (@ 0x40000000) BPROT Structure */ + __IM uint32_t RESERVED[384]; + __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ + __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ + __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ +} NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[124]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED4; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED5[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED6[7]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ +} NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IM uint32_t RESERVED3[122]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[63]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ + __IM uint32_t RESERVED7[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED8[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ + __IM uint32_t RESERVED9[225]; + __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register. */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and + Ieee802154_250Kbit modes when last bit is + sent on air. */ + __IM uint32_t RESERVED4[36]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[59]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED9; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED10; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED12[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED13; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED15[611]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write + one to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI1) + */ + +typedef struct { /*!< (@ 0x40003000) SPI1 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM1) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM1 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED10; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED11[4]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED12[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in + case and over-read of the TXD buffer. */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS1) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS1 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED12[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND + task has been issued, TWI traffic is now + suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED15[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n] and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in + RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels + are sampled */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the mode, multiple conversions might + be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should + not be combined with SCAN. The RESOLUTION + is applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu + t be written when RTC is stopped */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event Generator Unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IM uint32_t RESERVED4[8]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non-volatile memory controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1[64]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + }; + __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area. Equivalent to ERASEPAGE. */ + __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ +} NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI1_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40003000UL +#define NRF_SPIS1_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40004000UL +#define NRF_SPIM0_BASE 0x40004000UL +#define NRF_SPIS0_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52811_H */ + + +/** @} */ /* End of group nrf52811 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd new file mode 100644 index 000000000..f9810a20a --- /dev/null +++ b/mdk/nrf52811.svd @@ -0,0 +1,37551 @@ + + + + Nordic Semiconductor + Nordic + nrf52811 + nrf52 + 1 + nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n +\n +Redistribution and use in source and binary forms, with or without\n +modification, are permitted provided that the following conditions are met:\n +\n +1. Redistributions of source code must retain the above copyright notice, this\n + list of conditions and the following disclaimer.\n +\n +2. Redistributions in binary form must reproduce the above copyright\n + notice, this list of conditions and the following disclaimer in the\n + documentation and/or other materials provided with the distribution.\n +\n +3. Neither the name of Nordic Semiconductor ASA nor the names of its\n + contributors may be used to endorse or promote products derived from this\n + software without specific prior written permission.\n +\n +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n +POSSIBILITY OF SUCH DAMAGE.\n + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + CM4 + r0p1 + little + 1 + 0 + 3 + 0 + + system_nrf52811 + NRF_ + + 2048 + 2048 + 112 + + + + FICR + Factory information configuration registers + 0x10000000 + + 0 + 0x1000 + registers + + FICR + 0x20 + + + CODEPAGESIZE + Code memory page size + 0x010 + read-only + 0x00001000 + + + CODEPAGESIZE + Code memory page size + 0 + 31 + + + + + CODESIZE + Code memory size + 0x014 + read-only + 0x00000030 + + + CODESIZE + Code memory size in number of pages + 0 + 31 + + + + + 0x2 + 0x4 + DEVICEID[%s] + Description collection: Device identifier + 0x060 + read-only + 0xFFFFFFFF + + + DEVICEID + 64 bit unique device identifier + 0 + 31 + + + + + 0x4 + 0x4 + ER[%s] + Description collection: Encryption root, word n + 0x080 + read-only + 0xFFFFFFFF + + + ER + Encryption root, word n + 0 + 31 + + + + + 0x4 + 0x4 + IR[%s] + Description collection: Identity root, word n + 0x090 + read-only + 0xFFFFFFFF + + + IR + Identity root, word n + 0 + 31 + + + + + DEVICEADDRTYPE + Device address type + 0x0A0 + read-only + 0xFFFFFFFF + + + DEVICEADDRTYPE + Device address type + 0 + 0 + + + Public + Public address + 0 + + + Random + Random address + 1 + + + + + + + 0x2 + 0x4 + DEVICEADDR[%s] + Description collection: Device address n + 0x0A4 + read-only + 0xFFFFFFFF + + + DEVICEADDR + 48 bit device address + 0 + 31 + + + + + INFO + Device info + FICR_INFO + read-only + 0x100 + + PART + Part code + 0x000 + read-only + 0x00052811 + + + PART + Part code + 0 + 31 + + + N52810 + nRF52810 + 0x52810 + + + N52811 + nRF52811 + 0x52811 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + VARIANT + Part variant, hardware version and production configuration + 0x004 + read-only + 0xFFFFFFFF + + + VARIANT + Part variant, hardware version and production configuration, encoded as ASCII + 0 + 31 + + + AAAA + AAAA + 0x41414141 + + + AAA0 + AAA0 + 0x41414130 + + + AABA + AABA + 0x41414241 + + + AABB + AABB + 0x41414242 + + + AAB0 + AAB0 + 0x41414230 + + + AACA + AACA + 0x41414341 + + + AACB + AACB + 0x41414342 + + + AAC0 + AAC0 + 0x41414330 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + PACKAGE + Package option + 0x008 + read-only + 0xFFFFFFFF + + + PACKAGE + Package option + 0 + 31 + + + QF + QFxx - 48-pin QFN + 0x2000 + + + QC + QCxx - 32-pin QFN + 0x2003 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + RAM + RAM variant + 0x00C + read-only + 0x00000018 + + + RAM + RAM variant + 0 + 31 + + + K24 + 24 kByte RAM + 0x18 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + FLASH + Flash variant + 0x010 + read-only + 0x000000C0 + + + FLASH + Flash variant + 0 + 31 + + + K192 + 192 kByte flash + 0xC0 + + + Unspecified + Unspecified + 0xFFFFFFFF + + + + + + + + TEMP + Registers storing factory TEMP module linearization coefficients + FICR_TEMP + read-only + 0x404 + + A0 + Slope definition A0 + 0x000 + read-only + 0x00000320 + + + A + A (slope definition) register + 0 + 11 + + + + + A1 + Slope definition A1 + 0x004 + read-only + 0x00000343 + + + A + A (slope definition) register + 0 + 11 + + + + + A2 + Slope definition A2 + 0x008 + read-only + 0x0000035D + + + A + A (slope definition) register + 0 + 11 + + + + + A3 + Slope definition A3 + 0x00C + read-only + 0x00000400 + + + A + A (slope definition) register + 0 + 11 + + + + + A4 + Slope definition A4 + 0x010 + read-only + 0x00000452 + + + A + A (slope definition) register + 0 + 11 + + + + + A5 + Slope definition A5 + 0x014 + read-only + 0x0000037B + + + A + A (slope definition) register + 0 + 11 + + + + + B0 + Y-intercept B0 + 0x018 + read-only + 0x00003FCC + + + B + B (y-intercept) + 0 + 13 + + + + + B1 + Y-intercept B1 + 0x01C + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B2 + Y-intercept B2 + 0x020 + read-only + 0x00003F98 + + + B + B (y-intercept) + 0 + 13 + + + + + B3 + Y-intercept B3 + 0x024 + read-only + 0x00000012 + + + B + B (y-intercept) + 0 + 13 + + + + + B4 + Y-intercept B4 + 0x028 + read-only + 0x0000004D + + + B + B (y-intercept) + 0 + 13 + + + + + B5 + Y-intercept B5 + 0x02C + read-only + 0x00003E10 + + + B + B (y-intercept) + 0 + 13 + + + + + T0 + Segment end T0 + 0x030 + read-only + 0x000000E2 + + + T + T (segment end) register + 0 + 7 + + + + + T1 + Segment end T1 + 0x034 + read-only + 0x00000000 + + + T + T (segment end) register + 0 + 7 + + + + + T2 + Segment end T2 + 0x038 + read-only + 0x00000014 + + + T + T (segment end) register + 0 + 7 + + + + + T3 + Segment end T3 + 0x03C + read-only + 0x00000019 + + + T + T (segment end) register + 0 + 7 + + + + + T4 + Segment end T4 + 0x040 + read-only + 0x00000050 + + + T + T (segment end) register + 0 + 7 + + + + + + + + UICR + User information configuration registers + 0x10001000 + + 0 + 0x1000 + registers + + UICR + 0x20 + + + 0xF + 0x4 + NRFFW[%s] + Description collection: Reserved for Nordic firmware design + 0x014 + read-write + 0xFFFFFFFF + + + NRFFW + Reserved for Nordic firmware design + 0 + 31 + + + + + 0xC + 0x4 + NRFHW[%s] + Description collection: Reserved for Nordic hardware design + 0x050 + read-write + 0xFFFFFFFF + + + NRFHW + Reserved for Nordic hardware design + 0 + 31 + + + + + 0x20 + 0x4 + CUSTOMER[%s] + Description collection: Reserved for customer + 0x080 + read-write + 0xFFFFFFFF + + + CUSTOMER + Reserved for customer + 0 + 31 + + + + + 0x2 + 0x4 + PSELRESET[%s] + Description collection: Mapping of the nRESET function (see POWER chapter for details) + 0x200 + read-write + 0xFFFFFFFF + + + PIN + GPIO pin number onto which nRESET is exposed + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + APPROTECT + Access port protection + 0x208 + read-write + 0xFFFFFFFF + + + PALL + Enable or disable access port protection. + 0 + 7 + + + Disabled + Disable + 0xFF + + + Enabled + Enable + 0x00 + + + + + + + + + BPROT + Block Protect + 0x40000000 + + 0 + 0x1000 + registers + + BPROT + 0x20 + + + CONFIG0 + Block protect configuration register 0 + 0x600 + read-write + + + REGION0 + Enable protection for region 0. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION1 + Enable protection for region 1. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION2 + Enable protection for region 2. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION3 + Enable protection for region 3. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION4 + Enable protection for region 4. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION5 + Enable protection for region 5. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION6 + Enable protection for region 6. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION7 + Enable protection for region 7. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION8 + Enable protection for region 8. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION9 + Enable protection for region 9. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION10 + Enable protection for region 10. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION11 + Enable protection for region 11. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION12 + Enable protection for region 12. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION13 + Enable protection for region 13. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION14 + Enable protection for region 14. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION15 + Enable protection for region 15. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION16 + Enable protection for region 16. Write '0' has no effect. + 16 + 16 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION17 + Enable protection for region 17. Write '0' has no effect. + 17 + 17 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION18 + Enable protection for region 18. Write '0' has no effect. + 18 + 18 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION19 + Enable protection for region 19. Write '0' has no effect. + 19 + 19 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION20 + Enable protection for region 20. Write '0' has no effect. + 20 + 20 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION21 + Enable protection for region 21. Write '0' has no effect. + 21 + 21 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION22 + Enable protection for region 22. Write '0' has no effect. + 22 + 22 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION23 + Enable protection for region 23. Write '0' has no effect. + 23 + 23 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION24 + Enable protection for region 24. Write '0' has no effect. + 24 + 24 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION25 + Enable protection for region 25. Write '0' has no effect. + 25 + 25 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION26 + Enable protection for region 26. Write '0' has no effect. + 26 + 26 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION27 + Enable protection for region 27. Write '0' has no effect. + 27 + 27 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION28 + Enable protection for region 28. Write '0' has no effect. + 28 + 28 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION29 + Enable protection for region 29. Write '0' has no effect. + 29 + 29 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION30 + Enable protection for region 30. Write '0' has no effect. + 30 + 30 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION31 + Enable protection for region 31. Write '0' has no effect. + 31 + 31 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + CONFIG1 + Block protect configuration register 1 + 0x604 + read-write + + + REGION32 + Enable protection for region 32. Write '0' has no effect. + 0 + 0 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION33 + Enable protection for region 33. Write '0' has no effect. + 1 + 1 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION34 + Enable protection for region 34. Write '0' has no effect. + 2 + 2 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION35 + Enable protection for region 35. Write '0' has no effect. + 3 + 3 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION36 + Enable protection for region 36. Write '0' has no effect. + 4 + 4 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION37 + Enable protection for region 37. Write '0' has no effect. + 5 + 5 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION38 + Enable protection for region 38. Write '0' has no effect. + 6 + 6 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION39 + Enable protection for region 39. Write '0' has no effect. + 7 + 7 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION40 + Enable protection for region 40. Write '0' has no effect. + 8 + 8 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION41 + Enable protection for region 41. Write '0' has no effect. + 9 + 9 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION42 + Enable protection for region 42. Write '0' has no effect. + 10 + 10 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION43 + Enable protection for region 43. Write '0' has no effect. + 11 + 11 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION44 + Enable protection for region 44. Write '0' has no effect. + 12 + 12 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION45 + Enable protection for region 45. Write '0' has no effect. + 13 + 13 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION46 + Enable protection for region 46. Write '0' has no effect. + 14 + 14 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + REGION47 + Enable protection for region 47. Write '0' has no effect. + 15 + 15 + + + Disabled + Protection disabled + 0 + + + Enabled + Protection enabled + 1 + + + + + + + DISABLEINDEBUG + Disable protection mechanism in debug mode + 0x608 + read-write + 0x00000001 + + + DISABLEINDEBUG + Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. + 0 + 0 + + + Disabled + Disabled in debug + 1 + + + Enabled + Enabled in debug + 0 + + + + + + + + + CLOCK + Clock control + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + CLOCK + 0x20 + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0x000 + write-only + + + TASKS_HFCLKSTART + Start HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0x004 + write-only + + + TASKS_HFCLKSTOP + Stop HFCLK crystal oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTART + Start LFCLK source + 0x008 + write-only + + + TASKS_LFCLKSTART + Start LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0x00C + write-only + + + TASKS_LFCLKSTOP + Stop LFCLK source + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CAL + Start calibration of LFRC oscillator + 0x010 + write-only + + + TASKS_CAL + Start calibration of LFRC oscillator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTART + Start calibration timer + 0x014 + write-only + + + TASKS_CTSTART + Start calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CTSTOP + Stop calibration timer + 0x018 + write-only + + + TASKS_CTSTOP + Stop calibration timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0x100 + read-write + + + EVENTS_HFCLKSTARTED + HFCLK oscillator started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LFCLKSTARTED + LFCLK started + 0x104 + read-write + + + EVENTS_LFCLKSTARTED + LFCLK started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0x10C + read-write + + + EVENTS_DONE + Calibration of LFCLK RC oscillator complete event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CTTO + Calibration timer timeout + 0x110 + read-write + + + EVENTS_CTTO + Calibration timer timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + HFCLKSTARTED + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LFCLKSTARTED + Write '1' to disable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CTTO + Write '1' to disable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + HFCLKRUN + Status indicating that HFCLKSTART task has been triggered + 0x408 + read-only + + + STATUS + HFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + HFCLKSTAT + HFCLK status + 0x40C + read-only + + + SRC + Source of HFCLK + 0 + 0 + + + RC + 64 MHz internal oscillator (HFINT) + 0 + + + Xtal + 64 MHz crystal oscillator (HFXO) + 1 + + + + + STATE + HFCLK state + 16 + 16 + + + NotRunning + HFCLK not running + 0 + + + Running + HFCLK running + 1 + + + + + + + LFCLKRUN + Status indicating that LFCLKSTART task has been triggered + 0x414 + read-only + + + STATUS + LFCLKSTART task triggered or not + 0 + 0 + + + NotTriggered + Task not triggered + 0 + + + Triggered + Task triggered + 1 + + + + + + + LFCLKSTAT + LFCLK status + 0x418 + read-only + + + SRC + Source of LFCLK + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + STATE + LFCLK state + 16 + 16 + + + NotRunning + LFCLK not running + 0 + + + Running + LFCLK running + 1 + + + + + + + LFCLKSRCCOPY + Copy of LFCLKSRC register, set when LFCLKSTART task was triggered + 0x41C + read-only + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + + + LFCLKSRC + Clock source for the LFCLK + 0x518 + read-write + + + SRC + Clock source + 0 + 1 + + + RC + 32.768 kHz RC oscillator + 0 + + + Xtal + 32.768 kHz crystal oscillator + 1 + + + Synth + 32.768 kHz synthesized from HFCLK + 2 + + + + + BYPASS + Enable or disable bypass of LFCLK crystal oscillator with external clock source + 16 + 16 + + + Disabled + Disable (use with Xtal or low-swing external source) + 0 + + + Enabled + Enable (use with rail-to-rail external source) + 1 + + + + + EXTERNAL + Enable or disable external source for LFCLK + 17 + 17 + + + Disabled + Disable external source (use with Xtal) + 0 + + + Enabled + Enable use of external source instead of Xtal (SRC needs to be set to Xtal) + 1 + + + + + + + CTIV + Calibration timer interval + 0x538 + read-write + + + CTIV + Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. + 0 + 6 + + + + + + + POWER + Power control + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + + POWER_CLOCK + 0 + + POWER + 0x20 + + + TASKS_CONSTLAT + Enable constant latency mode + 0x078 + write-only + + + TASKS_CONSTLAT + Enable constant latency mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0x07C + write-only + + + TASKS_LOWPWR + Enable low power mode (variable latency) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_POFWARN + Power failure warning + 0x108 + read-write + + + EVENTS_POFWARN + Power failure warning + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0x114 + read-write + + + EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0x118 + read-write + + + EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + POFWARN + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPENTER + Write '1' to disable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SLEEPEXIT + Write '1' to disable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESETREAS + Reset reason + 0x400 + read-write + + + RESETPIN + Reset from pin-reset detected + 0 + 0 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DOG + Reset from watchdog detected + 1 + 1 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + SREQ + Reset from soft reset detected + 2 + 2 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + LOCKUP + Reset from CPU lock-up detected + 3 + 3 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + OFF + Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO + 16 + 16 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + DIF + Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode + 18 + 18 + + + NotDetected + Not detected + 0 + + + Detected + Detected + 1 + + + + + + + SYSTEMOFF + System OFF register + 0x500 + write-only + + + SYSTEMOFF + Enable System OFF mode + 0 + 0 + + + Enter + Enable System OFF mode + 1 + + + + + + + POFCON + Power failure comparator configuration + 0x510 + read-write + + + POF + Enable or disable power failure comparator + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + THRESHOLD + Power failure comparator threshold setting + 1 + 4 + + + V17 + Set threshold to 1.7 V + 4 + + + V18 + Set threshold to 1.8 V + 5 + + + V19 + Set threshold to 1.9 V + 6 + + + V20 + Set threshold to 2.0 V + 7 + + + V21 + Set threshold to 2.1 V + 8 + + + V22 + Set threshold to 2.2 V + 9 + + + V23 + Set threshold to 2.3 V + 10 + + + V24 + Set threshold to 2.4 V + 11 + + + V25 + Set threshold to 2.5 V + 12 + + + V26 + Set threshold to 2.6 V + 13 + + + V27 + Set threshold to 2.7 V + 14 + + + V28 + Set threshold to 2.8 V + 15 + + + + + + + GPREGRET + General purpose retention register + 0x51C + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + GPREGRET2 + General purpose retention register + 0x520 + read-write + + + GPREGRET + General purpose retention register + 0 + 7 + + + + + DCDCEN + DC/DC enable register + 0x578 + read-write + + + DCDCEN + Enable or disable DC/DC converter + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + 8 + 0x010 + RAM[%s] + Unspecified + POWER_RAM + read-write + 0x900 + + POWER + Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. + 0x000 + read-write + 0x0000FFFF + + + S0POWER + Keep RAM section S0 ON or OFF in System ON mode. + 0 + 0 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 ON or OFF in System ON mode. + 1 + 1 + + + Off + Off + 0 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is in OFF + 16 + 16 + + + Off + Off + 0 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is in OFF + 17 + 17 + + + Off + Off + 0 + + + On + On + 1 + + + + + + + POWERSET + Description cluster: RAMn power control set register + 0x004 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + On + On + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + On + On + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + On + On + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + On + On + 1 + + + + + + + POWERCLR + Description cluster: RAMn power control clear register + 0x008 + write-only + 0x0000FFFF + + + S0POWER + Keep RAM section S0 of RAMn on or off in System ON mode + 0 + 0 + + + Off + Off + 1 + + + + + S1POWER + Keep RAM section S1 of RAMn on or off in System ON mode + 1 + 1 + + + Off + Off + 1 + + + + + S0RETENTION + Keep retention on RAM section S0 when RAM section is switched off + 16 + 16 + + + Off + Off + 1 + + + + + S1RETENTION + Keep retention on RAM section S1 when RAM section is switched off + 17 + 17 + + + Off + Off + 1 + + + + + + + + + + P0 + GPIO Port + 0x50000000 + GPIO + + 0 + 0x1000 + registers + + GPIO + 0x20 + + + OUT + Write GPIO port + 0x504 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + + + + + + OUTSET + Set individual bits in GPIO port + 0x508 + read-write + oneToSet + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect + 1 + + + + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + + + PIN0 + Pin 0 + 0 + 0 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + + + IN + Read GPIO port + 0x510 + read-only + + + PIN0 + Pin 0 + 0 + 0 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + + + + + + DIR + Direction of GPIO pins + 0x514 + read-write + + + PIN0 + Pin 0 + 0 + 0 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN1 + Pin 1 + 1 + 1 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN2 + Pin 2 + 2 + 2 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN6 + Pin 6 + 6 + 6 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN7 + Pin 7 + 7 + 7 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN8 + Pin 8 + 8 + 8 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN9 + Pin 9 + 9 + 9 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN10 + Pin 10 + 10 + 10 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN11 + Pin 11 + 11 + 11 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN12 + Pin 12 + 12 + 12 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN13 + Pin 13 + 13 + 13 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN14 + Pin 14 + 14 + 14 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN15 + Pin 15 + 15 + 15 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN16 + Pin 16 + 16 + 16 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN17 + Pin 17 + 17 + 17 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN18 + Pin 18 + 18 + 18 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN19 + Pin 19 + 19 + 19 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN20 + Pin 20 + 20 + 20 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN21 + Pin 21 + 21 + 21 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN22 + Pin 22 + 22 + 22 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN23 + Pin 23 + 23 + 23 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN24 + Pin 24 + 24 + 24 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN26 + Pin 26 + 26 + 26 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN27 + Pin 27 + 27 + 27 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN28 + Pin 28 + 28 + 28 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN29 + Pin 29 + 29 + 29 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN30 + Pin 30 + 30 + 30 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + + + DIRSET + DIR set register + 0x518 + read-write + oneToSet + + + PIN0 + Set as output pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN1 + Set as output pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN2 + Set as output pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN3 + Set as output pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN4 + Set as output pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN5 + Set as output pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN9 + Set as output pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN10 + Set as output pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN11 + Set as output pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN12 + Set as output pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN13 + Set as output pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN14 + Set as output pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN15 + Set as output pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN16 + Set as output pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN17 + Set as output pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN18 + Set as output pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN19 + Set as output pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN20 + Set as output pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN21 + Set as output pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN22 + Set as output pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN23 + Set as output pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN24 + Set as output pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN25 + Set as output pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN26 + Set as output pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN27 + Set as output pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN28 + Set as output pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN29 + Set as output pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN30 + Set as output pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + PIN31 + Set as output pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + + + PIN0 + Set as input pin 0 + 0 + 0 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN1 + Set as input pin 1 + 1 + 1 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN2 + Set as input pin 2 + 2 + 2 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN3 + Set as input pin 3 + 3 + 3 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN4 + Set as input pin 4 + 4 + 4 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN5 + Set as input pin 5 + 5 + 5 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN6 + Set as input pin 6 + 6 + 6 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN7 + Set as input pin 7 + 7 + 7 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN8 + Set as input pin 8 + 8 + 8 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN9 + Set as input pin 9 + 9 + 9 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN10 + Set as input pin 10 + 10 + 10 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN16 + Set as input pin 16 + 16 + 16 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN17 + Set as input pin 17 + 17 + 17 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN18 + Set as input pin 18 + 18 + 18 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN19 + Set as input pin 19 + 19 + 19 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN20 + Set as input pin 20 + 20 + 20 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN21 + Set as input pin 21 + 21 + 21 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN22 + Set as input pin 22 + 22 + 22 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN25 + Set as input pin 25 + 25 + 25 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN26 + Set as input pin 26 + 26 + 26 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN27 + Set as input pin 27 + 27 + 27 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN28 + Set as input pin 28 + 28 + 28 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN29 + Set as input pin 29 + 29 + 29 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN30 + Set as input pin 30 + 30 + 30 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + PIN31 + Set as input pin 31 + 31 + 31 + + read + + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + + + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + 4 + 4 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + 6 + 6 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + 8 + 8 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 + + + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met + 1 + + + + + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write + + + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0 + 0 + + + Default + DETECT directly connected to PIN DETECT signals + 0 + + + LDETECT + Use the latched LDETECT behaviour + 1 + + + + + + + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 + read-write + 0x00000002 + + + DIR + Pin direction. Same physical register as DIR register + 0 + 0 + + + Input + Configure pin as an input pin + 0 + + + Output + Configure pin as an output pin + 1 + + + + + INPUT + Connect or disconnect input buffer + 1 + 1 + + + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer + 1 + + + + + PULL + Pull configuration + 2 + 3 + + + Disabled + No pull + 0 + + + Pulldown + Pull down on pin + 1 + + + Pullup + Pull up on pin + 3 + + + + + DRIVE + Drive configuration + 8 + 10 + + + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' + 1 + + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + + + + + SENSE + Pin sensing mechanism + 16 + 17 + + + Disabled + Disabled + 0 + + + High + Sense for high level + 2 + + + Low + Sense for low level + 3 + + + + + + + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + + + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only + + + TASKS_TXEN + Enable RADIO in TX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + + + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_START + Start RADIO + 0x008 + write-only + + + TASKS_START + Start RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RADIO + 0x00C + write-only + + + TASKS_STOP + Stop RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_DISABLE + Disable RADIO + 0x010 + write-only + + + TASKS_DISABLE + Disable RADIO + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 + write-only + + + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 + write-only + + + TASKS_RSSISTOP + Stop the RSSI measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTART + Start the bit counter + 0x01C + write-only + + + TASKS_BCSTART + Start the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_BCSTOP + Stop the bit counter + 0x020 + write-only + + + TASKS_BCSTOP + Stop the bit counter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 + write-only + + + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only + + + TASKS_EDSTOP + Stop the energy detect measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only + + + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only + + + TASKS_CCASTOP + Stop the clear channel assessment + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 + read-write + + + EVENTS_READY + RADIO has ramped up and is ready to be started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ADDRESS + Address sent or received + 0x104 + read-write + + + EVENTS_ADDRESS + Address sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 + read-write + + + EVENTS_PAYLOAD + Packet payload sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + Packet sent or received + 0x10C + read-write + + + EVENTS_END + Packet sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + + + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 + read-write + + + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + + + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + + + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 + read-write + + + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + + + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + + + EVENTS_MHRMATCH + MAC header match found + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0x16C + read-write + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_START + Shortcut between event READY and task START + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_DISABLE + Shortcut between event END and task DISABLE + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ADDRESS + Write '1' to disable interrupt for event ADDRESS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CRCSTATUS + CRC status + 0x400 + read-only + + + CRCSTATUS + CRC status of packet received + 0 + 0 + + + CRCError + Packet received with CRC error + 0 + + + CRCOk + Packet received with CRC ok + 1 + + + + + + + RXMATCH + Received address + 0x408 + read-only + + + RXMATCH + Received address + 0 + 2 + + + + + RXCRC + CRC field of previously received packet + 0x40C + read-only + + + RXCRC + CRC field of previously received packet + 0 + 23 + + + + + DAI + Device address match index + 0x410 + read-only + + + DAI + Device address match index + 0 + 2 + + + + + PDUSTAT + Payload status + 0x414 + read-only + + + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN + 0 + 0 + + + LessThan + Payload less than PCNF1.MAXLEN + 0 + + + GreaterThan + Payload greater than PCNF1.MAXLEN + 1 + + + + + CISTAT + Status on what rate packet is received with in Long Range + 1 + 2 + + + LR125kbit + Frame is received at 125kbps + 0 + + + LR500kbit + Frame is received at 500kbps + 1 + + + + + + + PACKETPTR + Packet pointer + 0x504 + read-write + 0x00000000 + + + PACKETPTR + Packet pointer + 0 + 31 + + + + + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 + + + FREQUENCY + Radio channel frequency + 0 + 6 + + + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + + + + + + TXPOWER + Output power + 0x50C + read-write + + + TXPOWER + RADIO output power + 0 + 7 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + + + + + + MODE + Data rate and modulation + 0x510 + read-write + + + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. + 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbit/s BLE + 3 + + + Ble_2Mbit + 2 Mbit/s BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 5 + + + Ble_LR500Kbit + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbit/s + 15 + + + + + + + PCNF0 + Packet configuration register 0 + 0x514 + read-write + + + LFLEN + Length on air of LENGTH field in number of bits. + 0 + 3 + + + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 + + + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 + + + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + + + + CILEN + Length of code indicator - long range + 22 + 23 + + + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + + + + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + + + + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 + + + + + PCNF1 + Packet configuration register 1 + 0x518 + read-write + + + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. + 0 + 7 + + + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + BASE0 + Base address 0 + 0x51C + read-write + + + BASE0 + Base address 0 + 0 + 31 + + + + + BASE1 + Base address 1 + 0x520 + read-write + + + BASE1 + Base address 1 + 0 + 31 + + + + + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 + read-write + + + AP0 + Address prefix 0. + 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 + + + + + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 + read-write + + + AP4 + Address prefix 4. + 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 + + + + + TXADDRESS + Transmit address select + 0x52C + read-write + + + TXADDRESS + Transmit address select + 0 + 2 + + + + + RXADDRESSES + Receive address select + 0x530 + read-write + + + ADDR0 + Enable or disable reception on logical address 0. + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR1 + Enable or disable reception on logical address 1. + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR5 + Enable or disable reception on logical address 5. + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR6 + Enable or disable reception on logical address 6. + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ADDR7 + Enable or disable reception on logical address 7. + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + CRCCNF + CRC configuration + 0x534 + read-write + + + LEN + CRC length in number of bytes. + 0 + 1 + + + Disabled + CRC length is zero and CRC calculation is disabled + 0 + + + One + CRC length is one byte and CRC calculation is enabled + 1 + + + Two + CRC length is two bytes and CRC calculation is enabled + 2 + + + Three + CRC length is three bytes and CRC calculation is enabled + 3 + + + + + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 + + + Include + CRC calculation includes address field + 0 + + + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + 1 + + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + + + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 + + + Disabled + RADIO is in the Disabled state + 0 + + + RxRu + RADIO is in the RXRU state + 1 + + + RxIdle + RADIO is in the RXIDLE state + 2 + + + Rx + RADIO is in the RX state + 3 + + + RxDisable + RADIO is in the RXDISABLED state + 4 + + + TxRu + RADIO is in the TXRU state + 9 + + + TxIdle + RADIO is in the TXIDLE state + 10 + + + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 + + + + + + + DATAWHITEIV + Data whitening initial value + 0x554 + read-write + 0x00000040 + + + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA1 + Enable or disable device address matching using device address 1 + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA2 + Enable or disable device address matching using device address 2 + 2 + 2 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA3 + Enable or disable device address matching using device address 3 + 3 + 3 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA4 + Enable or disable device address matching using device address 4 + 4 + 4 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA5 + Enable or disable device address matching using device address 5 + 5 + 5 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA6 + Enable or disable device address matching using device address 6 + 6 + 6 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ENA7 + Enable or disable device address matching using device address 7 + 7 + 7 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 + 10 + 10 + + + TXADD3 + TxAdd for device address 3 + 11 + 11 + + + TXADD4 + TxAdd for device address 4 + 12 + 12 + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + + + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 + 0 + + + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + 1 + + + + + DTX + Default TX value + 8 + 9 + + + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' + 1 + + + Center + Transmit center frequency + 2 + + + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + + + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-write + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 + + + EdMode + Energy above threshold + 0 + + + CarrierMode + Carrier seen + 1 + + + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 + + + + + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 + + + Disabled + Peripheral is powered off + 0 + + + Enabled + Peripheral is powered on + 1 + + + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + CTS_STARTRX + Shortcut between event CTS and task STARTRX + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UART + 0 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + + + + + + PSEL + Unspecified + UART_PSEL + read-write + 0x508 + + RTS + Pin select for RTS + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received in previous transfers, double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + write-only + + + TXD + TX data to be transferred + 0 + 7 + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + UARTE0 + UART with EasyDMA + 0x40002000 + UART0 + UARTE + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UARTE + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + + + TASKS_STOPRX + Stop UART receiver + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + + + TASKS_STOPTX + Stop UART transmitter + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only + + + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 + read-write + + + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + + + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + + + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source Note : this register is read / write one to clear. + 0x480 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + PARITY + Parity error + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + FRAMING + Framing error occurred + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + BREAK + Break condition + 3 + 3 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable UART + 0x500 + read-write + + + ENABLE + Enable or disable UARTE + 0 + 3 + + + Disabled + Disable UARTE + 0 + + + Enabled + Enable UARTE + 8 + + + + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + BAUDRATE + Baud rate + 0 + 31 + + + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 + + + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 + + + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 + + + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 + + + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 + + + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 + + + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 + + + Baud31250 + 31250 baud + 0x00800000 + + + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 + + + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 + + + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 + + + Baud1M + 1Mega baud + 0x10000000 + + + + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 + + + + + STOP + Stop bits + 4 + 4 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + + + + + + + + SPI1 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + + + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPI + 0x500 + read-write + + + ENABLE + Enable or disable SPI + 0 + 3 + + + Disabled + Disable SPI + 0 + + + Enabled + Enable SPI + 1 + + + + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TX data to send. Double buffered + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI1 + SPIM + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + + + TASKS_START + Start SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + + + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + + + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + + + EVENTS_STARTED + Transaction started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_START + Shortcut between event END and task START + 17 + 17 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable SPIM + 0x500 + read-write + + + ENABLE + Enable or disable SPIM + 0 + 3 + + + Disabled + Disable SPIM + 0 + + + Enabled + Enable SPIM + 7 + + + + + + + PSEL + Unspecified + SPIM_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 + + + K125 + 125 kbps + 0x02000000 + + + K250 + 250 kbps + 0x04000000 + + + K500 + 500 kbps + 0x08000000 + + + M1 + 1 Mbps + 0x10000000 + + + M2 + 2 Mbps + 0x20000000 + + + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 + + + + + + + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out in case and over-read of the TXD buffer. + 0 + 7 + + + + + + + SPIS1 + SPI Slave 0 + 0x40003000 + SPI1 + SPIS + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 + write-only + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 + write-only + + + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Granted transaction completed + 0x104 + read-write + + + EVENTS_END + Granted transaction completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + + + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + + + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + END_ACQUIRE + Shortcut between event END and task ACQUIRE + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + + + SEMSTAT + Semaphore status + 0 + 1 + + + Free + Semaphore is free + 0 + + + CPU + Semaphore is assigned to CPU + 1 + + + SPIS + Semaphore is assigned to SPI slave + 2 + + + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 + + + + + + + STATUS + Status from last transaction + 0x440 + read-write + + + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + write + + Clear + Write: clear error on writing '1' + 1 + + + + + + + ENABLE + Enable SPI slave + 0x500 + read-write + + + ENABLE + Enable or disable SPI slave + 0 + 3 + + + Disabled + Disable SPI slave + 0 + + + Enabled + Enable SPI slave + 2 + + + + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + + + ORDER + Bit order + 0 + 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 + + + + + ORC + Over-read character + 0x5C0 + read-write + + + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + + TWI0 + I2C compatible Two-Wire Interface + 0x40003000 + SPI1 + TWI + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXDREADY + TWI RXD byte received + 0x108 + read-write + + + EVENTS_RXDREADY + TWI RXD byte received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C + read-write + + + EVENTS_TXDSENT + TWI TXD byte sent + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write + + + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 + read-write + + + EVENTS_SUSPENDED + TWI entered the suspended state + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + BB_SUSPEND + Shortcut between event BB and task SUSPEND + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + BB + Write '1' to enable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + BB + Write '1' to disable interrupt for event BB + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + read + + NotPresent + Read: no overrun occured + 0 + + + Present + Read: overrun occured + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + read + + NotPresent + Read: error not present + 0 + + + Present + Read: error present + 1 + + + + + + + ENABLE + Enable TWI + 0x500 + read-write + + + ENABLE + Enable or disable TWI + 0 + 3 + + + Disabled + Disable TWI + 0 + + + Enabled + Enable TWI + 5 + + + + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + + + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA + 0x40003000 + SPI1 + TWIM + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + + + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + + + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C + read-write + + + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4C4 + read-write + oneToClear + + + OVERRUN + Overrun error + 0 + 0 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + ANACK + NACK received after sending the address (write '1' to clear) + 1 + 1 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + + + ENABLE + Enable TWIM + 0x500 + read-write + + + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA + 0x40003000 + SPI1 + TWIS + + 0 + 0x1000 + registers + + + TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1 + 3 + + TWIS + 0x20 + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + + + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only + + + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only + + + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + + + EVENTS_STOPPED + TWI stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + + + EVENTS_ERROR + TWI error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + + + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_WRITE + Write command received + 0x164 + read-write + + + EVENTS_WRITE + Write command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_READ + Read command received + 0x168 + read-write + + + EVENTS_READ + Read command received + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + READ + Enable or disable interrupt for event READ + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + READ + Write '1' to enable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + READ + Write '1' to disable interrupt for event READ + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear + + + OVERFLOW + RX buffer overflow detected, and prevented + 0 + 0 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + DNACK + NACK sent after receiving a data byte + 2 + 2 + + + NotReceived + Error did not occur + 0 + + + Received + Error occurred + 1 + + + + + OVERREAD + TX buffer over-read detected, and prevented + 3 + 3 + + + NotDetected + Error did not occur + 0 + + + Detected + Error occurred + 1 + + + + + + + MATCH + Status register indicating which address had a match + 0x4D4 + read-only + + + MATCH + Which of the addresses in {ADDRESS} matched the incoming address + 0 + 0 + + + + + ENABLE + Enable TWIS + 0x500 + read-write + + + ENABLE + Enable or disable TWIS + 0 + 3 + + + Disabled + Disable TWIS + 0 + + + Enabled + Enable TWIS + 9 + + + + + + + PSEL + Unspecified + TWIS_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 13 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 13 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write + + + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0 + 7 + + + + + + + SPI0 + Serial Peripheral Interface 1 + 0x40004000 + + SPIM0_SPIS0_SPI0 + 4 + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI0 + + SPIM0_SPIS0_SPI0 + 4 + + + + SPIS0 + SPI Slave 1 + 0x40004000 + SPI0 + + SPIM0_SPIS0_SPI0 + 4 + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 + read-write + + + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + IN0 + Write '1' to enable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN1 + Write '1' to enable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN2 + Write '1' to enable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN3 + Write '1' to enable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN4 + Write '1' to enable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + IN0 + Write '1' to disable interrupt for event IN[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN1 + Write '1' to disable interrupt for event IN[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN2 + Write '1' to disable interrupt for event IN[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN3 + Write '1' to disable interrupt for event IN[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 + read-write + + + MODE + Mode + 0 + 1 + + + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + 0 + + + Event + Event mode + 1 + + + Task + Task mode + 3 + + + + + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + + + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 + + + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 + + + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 + + + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + + + Low + Task mode: Initial value of pin before task triggering is low + 0 + + + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + + SAADC + Analog to Digital Converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Start the ADC and prepare the result buffer in RAM + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0x004 + write-only + + + TASKS_SAMPLE + Take one ADC sample, if scan is enabled all channels are sampled + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0x008 + write-only + + + TASKS_STOP + Stop the ADC and terminate any on-going conversion + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + The ADC has started + 0x100 + read-write + + + EVENTS_STARTED + The ADC has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The ADC has filled up the Result buffer + 0x104 + read-write + + + EVENTS_END + The ADC has filled up the Result buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 + read-write + + + EVENTS_DONE + A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0x10C + read-write + + + EVENTS_RESULTDONE + A result is ready to get transferred to RAM. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write + + + EVENTS_CALIBRATEDONE + Calibration is complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + The ADC has stopped + 0x114 + read-write + + + EVENTS_STOPPED + The ADC has stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last results is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last results is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last results is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last results is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DONE + Enable or disable interrupt for event DONE + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RESULTDONE + Enable or disable interrupt for event RESULTDONE + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Status + 0x400 + read-only + + + STATUS + Status + 0 + 0 + + + Ready + ADC is ready. No on-going conversion. + 0 + + + Busy + ADC is busy. Conversion in progress. + 1 + + + + + + + ENABLE + Enable or disable ADC + 0x500 + read-write + + + ENABLE + Enable or disable ADC + 0 + 0 + + + Disabled + Disable ADC + 0 + + + Enabled + Enable ADC + 1 + + + + + + + 8 + 0x010 + CH[%s] + Unspecified + SAADC_CH + read-write + 0x510 + + PSELP + Description cluster: Input positive pin selection for CH[n] + 0x000 + read-write + 0x00000000 + + + PSELP + Analog positive input channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 + read-write + 0x00000000 + + + PSELN + Analog negative input, enables differential channel + 0 + 4 + + + NC + Not connected + 0 + + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + + + + + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the ADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single ended, PSELN will be ignored, negative input to ADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring a channel + 0x00C + read-write + 0x7FFF8000 + + + LOW + Low level limit + 0 + 15 + + + HIGH + High level limit + 16 + 31 + + + + + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bit + 0 + + + 10bit + 10 bit + 1 + + + 12bit + 12 bit + 2 + + + 14bit + 14 bit + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + + + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of buffer words to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of buffer words to transfer + 0 + 14 + + + + + AMOUNT + Number of buffer words transferred since last START + 0x008 + read-only + + + AMOUNT + Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. + 0 + 14 + + + + + + + + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER + + 0 + 0x1000 + registers + + + TIMER0 + 8 + + TIMER + 0x20 + + + TASKS_START + Start Timer + 0x000 + write-only + + + TASKS_START + Start Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop Timer + 0x004 + write-only + + + TASKS_STOP + Stop Timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only + + + TASKS_COUNT + Increment Timer (Counter mode only) + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear time + 0x00C + write-only + + + TASKS_CLEAR + Clear time + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MODE + Timer mode selection + 0x504 + read-write + + + MODE + Timer mode + 0 + 1 + + + Timer + Select Timer mode + 0 + + + Counter + Deprecated enumerator - Select Counter mode + 1 + + + LowPowerCounter + Select Low Power Counter mode + 2 + + + + + + + BITMODE + Configure the number of bits used by the TIMER + 0x508 + read-write + + + BITMODE + Timer bit width + 0 + 1 + + + 16Bit + 16 bit timer bit width + 0 + + + 08Bit + 8 bit timer bit width + 1 + + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + + + + + + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n + 0x540 + read-write + + + CC + Capture/Compare value + 0 + 31 + + + + + + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + + + + RTC0 + Real time counter 0 + 0x4000B000 + RTC + + 0 + 0x1000 + registers + + + RTC0 + 11 + + RTC + 0x20 + + + TASKS_START + Start RTC COUNTER + 0x000 + write-only + + + TASKS_START + Start RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only + + + TASKS_STOP + Stop RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only + + + TASKS_CLEAR + Clear RTC COUNTER + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only + + + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TICK + Event on COUNTER increment + 0x100 + read-write + + + EVENTS_TICK + Event on COUNTER increment + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 + read-write + + + EVENTS_OVRFLW + Event on COUNTER overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 + read-write + + + EVENTS_COMPARE + Compare event on CC[n] match + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TICK + Write '1' to enable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + + + TICK + Enable or disable event routing for event TICK + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE0 + Enable or disable event routing for event COMPARE[0] + 16 + 16 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE1 + Enable or disable event routing for event COMPARE[1] + 17 + 17 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE2 + Enable or disable event routing for event COMPARE[2] + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + COMPARE3 + Enable or disable event routing for event COMPARE[3] + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Disable + 1 + + + + + + + EVTENSET + Enable event routing + 0x344 + read-write + + + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + EVTENCLR + Disable event routing + 0x348 + read-write + + + TICK + Write '1' to disable event routing for event TICK + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + OVRFLW + Write '1' to disable event routing for event OVRFLW + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + COUNTER + Current COUNTER value + 0x504 + read-only + + + COUNTER + Counter value + 0 + 23 + + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + + + PRESCALER + Prescaler value + 0 + 11 + + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + + + COMPARE + Compare value + 0 + 23 + + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + + + TASKS_START + Start temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + + + TASKS_STOP + Stop temperature measurement + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + + + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000326 + + + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + DERCEN + Bias correction + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + + + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + + + EVENTS_RESOLVED + Address resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + END + Write '1' to enable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + END + Write '1' to disable interrupt for event END + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + RESOLVED + Write '1' to disable interrupt for event RESOLVED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + STATUS + Resolution status + 0x400 + read-only + + + STATUS + The IRK that was used last time an address was resolved + 0 + 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 3 + + + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0x100 + read-write + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + MICSTATUS + MIC check result + 0x400 + read-only + + + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 + + + CheckFailed + MIC check failed + 0 + + + CheckPassed + MIC check passed + 1 + + + + + + + ENABLE + Enable + 0x500 + read-write + + + ENABLE + Enable or disable CCM + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 + + + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode + 1 + + + + + DATARATE + Radio data rate that the CCM shall run synchronous with + 16 + 17 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + LENGTH + Packet length configuration + 24 + 24 + + + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + 1 + + + + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + + + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 + + + 1Mbit + 1 Mbps + 0 + + + 2Mbit + 2 Mbps + 1 + + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + + + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RUNSTATUS + Run status + 0x400 + read-only + + + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 + + + NotRunning + Watchdog not running + 0 + + + Running + Watchdog is running + 1 + + + + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + + + RR0 + Request status for RR[0] register + 0 + 0 + + + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload + 1 + + + + + RR1 + Request status for RR[1] register + 1 + 1 + + + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload + 1 + + + + + RR2 + Request status for RR[2] register + 2 + 2 + + + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload + 1 + + + + + RR3 + Request status for RR[3] register + 3 + 3 + + + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload + 1 + + + + + RR4 + Request status for RR[4] register + 4 + 4 + + + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload + 1 + + + + + RR5 + Request status for RR[5] register + 5 + 5 + + + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload + 1 + + + + + RR6 + Request status for RR[6] register + 6 + 6 + + + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload + 1 + + + + + RR7 + Request status for RR[7] register + 7 + 7 + + + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload + 0 + + + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload + 1 + + + + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + + + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 + 31 + + + + + RREN + Enable register for reload request registers + 0x508 + read-write + 0x00000001 + + + RR0 + Enable or disable RR[0] register + 0 + 0 + + + Disabled + Disable RR[0] register + 0 + + + Enabled + Enable RR[0] register + 1 + + + + + RR1 + Enable or disable RR[1] register + 1 + 1 + + + Disabled + Disable RR[1] register + 0 + + + Enabled + Enable RR[1] register + 1 + + + + + RR2 + Enable or disable RR[2] register + 2 + 2 + + + Disabled + Disable RR[2] register + 0 + + + Enabled + Enable RR[2] register + 1 + + + + + RR3 + Enable or disable RR[3] register + 3 + 3 + + + Disabled + Disable RR[3] register + 0 + + + Enabled + Enable RR[3] register + 1 + + + + + RR4 + Enable or disable RR[4] register + 4 + 4 + + + Disabled + Disable RR[4] register + 0 + + + Enabled + Enable RR[4] register + 1 + + + + + RR5 + Enable or disable RR[5] register + 5 + 5 + + + Disabled + Disable RR[5] register + 0 + + + Enabled + Enable RR[5] register + 1 + + + + + RR6 + Enable or disable RR[6] register + 6 + 6 + + + Disabled + Disable RR[6] register + 0 + + + Enabled + Enable RR[6] register + 1 + + + + + RR7 + Enable or disable RR[7] register + 7 + 7 + + + Disabled + Disable RR[7] register + 0 + + + Enabled + Enable RR[7] register + 1 + + + + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + + + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 + + + Pause + Pause watchdog while the CPU is sleeping + 0 + + + Run + Keep the watchdog running while the CPU is sleeping + 1 + + + + + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 + + + Pause + Pause watchdog while the CPU is halted by the debugger + 0 + + + Run + Keep the watchdog running while the CPU is halted by the debugger + 1 + + + + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + + + RR + Reload request register + 0 + 31 + + + Reload + Value to request a reload of the watchdog timer + 0x6E524635 + + + + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + + + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + + + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + + + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + + + ENABLE + Enable or disable the quadrature decoder + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + + + LEDPOL + LED output pin polarity + 0 + 0 + + + ActiveLow + Led active on output pin low + 0 + + + ActiveHigh + Led active on output pin high + 1 + + + + + + + SAMPLEPER + Sample period + 0x508 + read-write + + + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 + + + 128us + 128 us + 0 + + + 256us + 256 us + 1 + + + 512us + 512 us + 2 + + + 1024us + 1024 us + 3 + + + 2048us + 2048 us + 4 + + + 4096us + 4096 us + 5 + + + 8192us + 8192 us + 6 + + + 16384us + 16384 us + 7 + + + 32ms + 32768 us + 8 + + + 65ms + 65536 us + 9 + + + 131ms + 131072 us + 10 + + + + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + + + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 + + + 10Smpl + 10 samples / report + 0 + + + 40Smpl + 40 samples / report + 1 + + + 80Smpl + 80 samples / report + 2 + + + 120Smpl + 120 samples / report + 3 + + + 160Smpl + 160 samples / report + 4 + + + 200Smpl + 200 samples / report + 5 + + + 240Smpl + 240 samples / report + 6 + + + 280Smpl + 280 samples / report + 7 + + + 1Smpl + 1 sample / report + 8 + + + + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + + + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled + 0 + + + Enabled + Debounce input filters enabled + 1 + + + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + + + TASKS_STOP + Stop comparator + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + + + EVENTS_READY + COMP is ready and output is valid + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + + + EVENTS_UP + Upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + UP + Enable or disable interrupt for event UP + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + READY + Write '1' to enable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + UP + Write '1' to enable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + READY + Write '1' to disable interrupt for event READY + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + UP + Write '1' to disable interrupt for event UP + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + RESULT + Compare result + 0x400 + read-only + + + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 + + + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) + 0 + + + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) + 1 + + + + + + + ENABLE + COMP enable + 0x500 + read-write + + + ENABLE + Enable or disable COMP + 0 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 2 + + + + + + + PSEL + Pin select + 0x504 + read-write + + + PSEL + Analog pin select + 0 + 2 + + + AnalogInput0 + AIN0 selected as analog input + 0 + + + AnalogInput1 + AIN1 selected as analog input + 1 + + + AnalogInput2 + AIN2 selected as analog input + 2 + + + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + VddDiv2 + VDD/2 selected as analog input + 7 + + + + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + + + REFSEL + Reference select + 0 + 2 + + + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + 0 + + + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + 1 + + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 5 + + + + + + + EXTREFSEL + External reference select + 0x50C + read-write + + + EXTREFSEL + External analog reference select + 0 + 2 + + + AnalogReference0 + Use AIN0 as external analog reference + 0 + + + AnalogReference1 + Use AIN1 as external analog reference + 1 + + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + + + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 + + + Low + Low-power mode + 0 + + + Normal + Normal mode + 1 + + + High + High-speed mode + 2 + + + + + MAIN + Main operation modes + 8 + 8 + + + SE + Single-ended mode + 0 + + + Diff + Differential mode + 1 + + + + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + + + HYST + Comparator hysteresis + 0 + 0 + + + NoHyst + Comparator hysteresis disabled + 0 + + + Hyst50mV + Comparator hysteresis enabled + 1 + + + + + + + + + EGU0 + Event Generator Unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event Generator Unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + SWI2 + Software interrupt 2 + 0x40016000 + + SWI2 + 22 + + + + SWI3 + Software interrupt 3 + 0x40017000 + + SWI3 + 23 + + + + SWI4 + Software interrupt 4 + 0x40018000 + + SWI4 + 24 + + + + SWI5 + Software interrupt 5 + 0x40019000 + + SWI5 + 25 + + + + PWM0 + Pulse width modulation unit + 0x4001C000 + PWM + + 0 + 0x1000 + registers + + + PWM0 + 28 + + PWM + 0x20 + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 + write-only + + + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 + write-only + + + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0x104 + read-write + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n + 0x108 + read-write + + + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP + 0 + 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PWM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PWM module + 0 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enable + 1 + + + + + + + MODE + Selects operating mode of the wave counter + 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 + + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 + read-write + 0x00000000 + + + PTR + Beginning address in RAM of this sequence + 0 + 31 + + + + + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 + read-write + 0x00000000 + + + CNT + Number of values (duty cycles) in this sequence + 0 + 14 + + + Disabled + Sequence is disabled, and shall not be started as it is empty + 0 + + + + + + + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 + read-write + 0x00000001 + + + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + 0 + 23 + + + Continuous + Update every PWM period + 0 + + + + + + + ENDDELAY + Description cluster: Time added after the sequence + 0x00C + read-write + 0x00000000 + + + CNT + Time added after the sequence in PWM periods + 0 + 23 + + + + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 + + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 7 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment ('2500 RMS' requirement) + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + PSEL + Unspecified + PDM_PSEL + read-write + 0x540 + + CLK + Pin number configuration for PDM CLK signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + DIN + Pin number configuration for PDM DIN signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 + + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 + read-write + + + SAMPLEPTR + Address to write PDM samples to over DMA + 0 + 31 + + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + + + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + + NVMC + Non-volatile memory controller + 0x4001E000 + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (ongoing write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in code area. + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of chip + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x510 + read-write + + + ERASEPCR0 + Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + read-write + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write + + + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + + + CH0 + Channel 0 enable set register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH1 + Channel 1 enable set register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH2 + Channel 2 enable set register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH3 + Channel 3 enable set register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH4 + Channel 4 enable set register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH5 + Channel 5 enable set register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH6 + Channel 6 enable set register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH7 + Channel 7 enable set register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH8 + Channel 8 enable set register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH9 + Channel 9 enable set register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH10 + Channel 10 enable set register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH11 + Channel 11 enable set register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH12 + Channel 12 enable set register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH13 + Channel 13 enable set register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH14 + Channel 14 enable set register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH15 + Channel 15 enable set register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH16 + Channel 16 enable set register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH17 + Channel 17 enable set register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH18 + Channel 18 enable set register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH19 + Channel 19 enable set register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH20 + Channel 20 enable set register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH21 + Channel 21 enable set register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH22 + Channel 22 enable set register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH23 + Channel 23 enable set register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH24 + Channel 24 enable set register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH25 + Channel 25 enable set register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH26 + Channel 26 enable set register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH27 + Channel 27 enable set register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH28 + Channel 28 enable set register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH29 + Channel 29 enable set register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH30 + Channel 30 enable set register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + CH31 + Channel 31 enable set register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + + + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + + + CH0 + Channel 0 enable clear register. Writing '0' has no effect + 0 + 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH1 + Channel 1 enable clear register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH2 + Channel 2 enable clear register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH3 + Channel 3 enable clear register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH4 + Channel 4 enable clear register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH5 + Channel 5 enable clear register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH6 + Channel 6 enable clear register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH7 + Channel 7 enable clear register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH8 + Channel 8 enable clear register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH9 + Channel 9 enable clear register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH10 + Channel 10 enable clear register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH11 + Channel 11 enable clear register. Writing '0' has no effect + 11 + 11 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH12 + Channel 12 enable clear register. Writing '0' has no effect + 12 + 12 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH13 + Channel 13 enable clear register. Writing '0' has no effect + 13 + 13 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH14 + Channel 14 enable clear register. Writing '0' has no effect + 14 + 14 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH15 + Channel 15 enable clear register. Writing '0' has no effect + 15 + 15 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH16 + Channel 16 enable clear register. Writing '0' has no effect + 16 + 16 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH17 + Channel 17 enable clear register. Writing '0' has no effect + 17 + 17 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH18 + Channel 18 enable clear register. Writing '0' has no effect + 18 + 18 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH19 + Channel 19 enable clear register. Writing '0' has no effect + 19 + 19 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH20 + Channel 20 enable clear register. Writing '0' has no effect + 20 + 20 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH21 + Channel 21 enable clear register. Writing '0' has no effect + 21 + 21 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH22 + Channel 22 enable clear register. Writing '0' has no effect + 22 + 22 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH23 + Channel 23 enable clear register. Writing '0' has no effect + 23 + 23 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH24 + Channel 24 enable clear register. Writing '0' has no effect + 24 + 24 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH25 + Channel 25 enable clear register. Writing '0' has no effect + 25 + 25 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH26 + Channel 26 enable clear register. Writing '0' has no effect + 26 + 26 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH27 + Channel 27 enable clear register. Writing '0' has no effect + 27 + 27 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH28 + Channel 28 enable clear register. Writing '0' has no effect + 28 + 28 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH29 + Channel 29 enable clear register. Writing '0' has no effect + 29 + 29 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH30 + Channel 30 enable clear register. Writing '0' has no effect + 30 + 30 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + CH31 + Channel 31 enable clear register. Writing '0' has no effect + 31 + 31 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Clear + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH1 + Include or exclude channel 1 + 1 + 1 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH7 + Include or exclude channel 7 + 7 + 7 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH8 + Include or exclude channel 8 + 8 + 8 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH9 + Include or exclude channel 9 + 9 + 9 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH10 + Include or exclude channel 10 + 10 + 10 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH11 + Include or exclude channel 11 + 11 + 11 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH12 + Include or exclude channel 12 + 12 + 12 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH13 + Include or exclude channel 13 + 13 + 13 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH14 + Include or exclude channel 14 + 14 + 14 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH15 + Include or exclude channel 15 + 15 + 15 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH16 + Include or exclude channel 16 + 16 + 16 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH17 + Include or exclude channel 17 + 17 + 17 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH18 + Include or exclude channel 18 + 18 + 18 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH19 + Include or exclude channel 19 + 19 + 19 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH20 + Include or exclude channel 20 + 20 + 20 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH21 + Include or exclude channel 21 + 21 + 21 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH22 + Include or exclude channel 22 + 22 + 22 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH23 + Include or exclude channel 23 + 23 + 23 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH24 + Include or exclude channel 24 + 24 + 24 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH25 + Include or exclude channel 25 + 25 + 25 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH26 + Include or exclude channel 26 + 26 + 26 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH27 + Include or exclude channel 27 + 27 + 27 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH28 + Include or exclude channel 28 + 28 + 28 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH29 + Include or exclude channel 29 + 29 + 29 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH30 + Include or exclude channel 30 + 30 + 30 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH31 + Include or exclude channel 31 + 31 + 31 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + + + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + \ No newline at end of file diff --git a/mdk/nrf52811_bitfields.h b/mdk/nrf52811_bitfields.h new file mode 100644 index 000000000..4d0e08388 --- /dev/null +++ b/mdk/nrf52811_bitfields.h @@ -0,0 +1,11787 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef __NRF52811_BITS_H +#define __NRF52811_BITS_H + +/*lint ++flb "Enter library region" */ + +/* Peripheral: AAR */ +/* Description: Accelerated Address Resolver */ + +/* Register: AAR_TASKS_START */ +/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ + +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ +#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_TASKS_STOP */ +/* Description: Stop resolving addresses */ + +/* Bit 0 : Stop resolving addresses */ +#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: AAR_EVENTS_END */ +/* Description: Address resolution procedure complete */ + +/* Bit 0 : Address resolution procedure complete */ +#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_RESOLVED */ +/* Description: Address resolved */ + +/* Bit 0 : Address resolved */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_EVENTS_NOTRESOLVED */ +/* Description: Address not resolved */ + +/* Bit 0 : Address not resolved */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ + +/* Register: AAR_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ +#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ +#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event END */ +#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: AAR_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ +#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ +#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ +#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ +#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event END */ +#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ +#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: AAR_STATUS */ +/* Description: Resolution status */ + +/* Bits 3..0 : The IRK that was used last time an address was resolved */ +#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ + +/* Register: AAR_ENABLE */ +/* Description: Enable AAR */ + +/* Bits 1..0 : Enable or disable AAR */ +#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ + +/* Register: AAR_NIRK */ +/* Description: Number of IRKs */ + +/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ +#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ + +/* Register: AAR_IRKPTR */ +/* Description: Pointer to IRK data structure */ + +/* Bits 31..0 : Pointer to the IRK data structure */ +#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ +#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ + +/* Register: AAR_ADDRPTR */ +/* Description: Pointer to the resolvable address */ + +/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ +#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ +#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ + +/* Register: AAR_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + + +/* Peripheral: BPROT */ +/* Description: Block Protect */ + +/* Register: BPROT_CONFIG0 */ +/* Description: Block protect configuration register 0 */ + +/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ +#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ +#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ +#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ +#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ +#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ +#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ +#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ +#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ +#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ +#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ +#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ +#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ +#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ +#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ +#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ +#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ +#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ +#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ +#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ +#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ +#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ +#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ +#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ +#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ +#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ +#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ +#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ +#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ +#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ +#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ +#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ +#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ +#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_CONFIG1 */ +/* Description: Block protect configuration register 1 */ + +/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ +#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ +#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ +#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ +#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ +#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ +#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ +#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ +#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ +#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ +#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ +#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ +#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ +#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ +#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ +#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ + +/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ +#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ +#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ +#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ + +/* Register: BPROT_DISABLEINDEBUG */ +/* Description: Disable protection mechanism in debug mode */ + +/* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enabled in debug */ +#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */ + + +/* Peripheral: CCM */ +/* Description: AES CCM Mode Encryption */ + +/* Register: CCM_TASKS_KSGEN */ +/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ + +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_CRYPT */ +/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ + +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_STOP */ +/* Description: Stop encryption/decryption */ + +/* Bit 0 : Stop encryption/decryption */ +#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_TASKS_RATEOVERRIDE */ +/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ + +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ + +/* Register: CCM_EVENTS_ENDKSGEN */ +/* Description: Key-stream generation complete */ + +/* Bit 0 : Key-stream generation complete */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ENDCRYPT */ +/* Description: Encrypt/decrypt complete */ + +/* Bit 0 : Encrypt/decrypt complete */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_EVENTS_ERROR */ +/* Description: Deprecated register - CCM error event */ + +/* Bit 0 : Deprecated field - CCM error event */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: CCM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ +#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: CCM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ +#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ +#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ +#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ + +/* Register: CCM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ +#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ +#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ +#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ +#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ +#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ +#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ +#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ +#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ + +/* Register: CCM_MICSTATUS */ +/* Description: MIC check result */ + +/* Bit 0 : The result of the MIC check performed during the previous decryption operation */ +#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ +#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ +#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ + +/* Register: CCM_ENABLE */ +/* Description: Enable */ + +/* Bits 1..0 : Enable or disable CCM */ +#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: CCM_MODE */ +/* Description: Operation mode */ + +/* Bit 24 : Packet length configuration */ +#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ +#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ + +/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ +#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ +#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ +#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ + +/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */ +#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ +#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ + +/* Register: CCM_CNFPTR */ +/* Description: Pointer to data structure holding AES key and NONCE vector */ + +/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ +#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ +#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ + +/* Register: CCM_INPTR */ +/* Description: Input pointer */ + +/* Bits 31..0 : Input pointer */ +#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ +#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ + +/* Register: CCM_OUTPTR */ +/* Description: Output pointer */ + +/* Bits 31..0 : Output pointer */ +#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ +#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ + +/* Register: CCM_SCRATCHPTR */ +/* Description: Pointer to data area used for temporary storage */ + +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ +#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ + +/* Register: CCM_MAXPACKETSIZE */ +/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ + +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ +#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ + +/* Register: CCM_RATEOVERRIDE */ +/* Description: Data rate override setting. */ + +/* Bits 1..0 : Data rate override setting. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ + + +/* Peripheral: CLOCK */ +/* Description: Clock control */ + +/* Register: CLOCK_TASKS_HFCLKSTART */ +/* Description: Start HFCLK crystal oscillator */ + +/* Bit 0 : Start HFCLK crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_HFCLKSTOP */ +/* Description: Stop HFCLK crystal oscillator */ + +/* Bit 0 : Stop HFCLK crystal oscillator */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTART */ +/* Description: Start LFCLK source */ + +/* Bit 0 : Start LFCLK source */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_LFCLKSTOP */ +/* Description: Stop LFCLK source */ + +/* Bit 0 : Stop LFCLK source */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CAL */ +/* Description: Start calibration of LFRC oscillator */ + +/* Bit 0 : Start calibration of LFRC oscillator */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTART */ +/* Description: Start calibration timer */ + +/* Bit 0 : Start calibration timer */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_TASKS_CTSTOP */ +/* Description: Stop calibration timer */ + +/* Bit 0 : Stop calibration timer */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: CLOCK_EVENTS_HFCLKSTARTED */ +/* Description: HFCLK oscillator started */ + +/* Bit 0 : HFCLK oscillator started */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_LFCLKSTARTED */ +/* Description: LFCLK started */ + +/* Bit 0 : LFCLK started */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_DONE */ +/* Description: Calibration of LFCLK RC oscillator complete event */ + +/* Bit 0 : Calibration of LFCLK RC oscillator complete event */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_EVENTS_CTTO */ +/* Description: Calibration timer timeout */ + +/* Bit 0 : Calibration timer timeout */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ + +/* Register: CLOCK_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ +#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DONE */ +#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ + +/* Register: CLOCK_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ +#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ +#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DONE */ +#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ +#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ + +/* Register: CLOCK_HFCLKRUN */ +/* Description: Status indicating that HFCLKSTART task has been triggered */ + +/* Bit 0 : HFCLKSTART task triggered or not */ +#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_HFCLKSTAT */ +/* Description: HFCLK status */ + +/* Bit 16 : HFCLK state */ +#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ +#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ + +/* Bit 0 : Source of HFCLK */ +#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ +#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ + +/* Register: CLOCK_LFCLKRUN */ +/* Description: Status indicating that LFCLKSTART task has been triggered */ + +/* Bit 0 : LFCLKSTART task triggered or not */ +#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ + +/* Register: CLOCK_LFCLKSTAT */ +/* Description: LFCLK status */ + +/* Bit 16 : LFCLK state */ +#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ +#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ + +/* Bits 1..0 : Source of LFCLK */ +#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRCCOPY */ +/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_LFCLKSRC */ +/* Description: Clock source for the LFCLK */ + +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + +/* Bits 1..0 : Clock source */ +#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ + +/* Register: CLOCK_CTIV */ +/* Description: Calibration timer interval */ + +/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ +#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ +#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ + + +/* Peripheral: COMP */ +/* Description: Comparator */ + +/* Register: COMP_TASKS_START */ +/* Description: Start comparator */ + +/* Bit 0 : Start comparator */ +#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_STOP */ +/* Description: Stop comparator */ + +/* Bit 0 : Stop comparator */ +#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_TASKS_SAMPLE */ +/* Description: Sample comparator value */ + +/* Bit 0 : Sample comparator value */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: COMP_EVENTS_READY */ +/* Description: COMP is ready and output is valid */ + +/* Bit 0 : COMP is ready and output is valid */ +#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_DOWN */ +/* Description: Downward crossing */ + +/* Bit 0 : Downward crossing */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_UP */ +/* Description: Upward crossing */ + +/* Bit 0 : Upward crossing */ +#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_EVENTS_CROSS */ +/* Description: Downward or upward crossing */ + +/* Bit 0 : Downward or upward crossing */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ + +/* Register: COMP_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event CROSS and task STOP */ +#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ +#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event UP and task STOP */ +#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ +#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DOWN and task STOP */ +#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ +#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event READY and task STOP */ +#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ +#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task SAMPLE */ +#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ +#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ +#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: COMP_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 3 : Enable or disable interrupt for event CROSS */ +#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event UP */ +#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event DOWN */ +#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event READY */ +#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ +#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ + +/* Register: COMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event UP */ +#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: COMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ +#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ +#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event UP */ +#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ +#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ +#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ +#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ +#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: COMP_RESULT */ +/* Description: Compare result */ + +/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ +#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ +#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ +#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ +#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ + +/* Register: COMP_ENABLE */ +/* Description: COMP enable */ + +/* Bits 1..0 : Enable or disable COMP */ +#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ + +/* Register: COMP_PSEL */ +/* Description: Pin select */ + +/* Bits 2..0 : Analog pin select */ +#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ +#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ +#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ +#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ +#define COMP_PSEL_PSEL_VddDiv2 (7UL) /*!< VDD/2 selected as analog input */ + +/* Register: COMP_REFSEL */ +/* Description: Reference source select for single-ended mode */ + +/* Bits 2..0 : Reference select */ +#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ +#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ +#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ + +/* Register: COMP_EXTREFSEL */ +/* Description: External reference select */ + +/* Bits 2..0 : External analog reference select */ +#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ +#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ + +/* Register: COMP_TH */ +/* Description: Threshold configuration for hysteresis unit */ + +/* Bits 13..8 : VUP = (THUP+1)/64*VREF */ +#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ +#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ + +/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ +#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ +#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ + +/* Register: COMP_MODE */ +/* Description: Mode configuration */ + +/* Bit 8 : Main operation modes */ +#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ +#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ + +/* Bits 1..0 : Speed and power modes */ +#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ +#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ +#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ +#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ + +/* Register: COMP_HYST */ +/* Description: Comparator hysteresis enable */ + +/* Bit 0 : Comparator hysteresis */ +#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ +#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ +#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ + + +/* Peripheral: ECB */ +/* Description: AES ECB Mode Encryption */ + +/* Register: ECB_TASKS_STARTECB */ +/* Description: Start ECB block encrypt */ + +/* Bit 0 : Start ECB block encrypt */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_TASKS_STOPECB */ +/* Description: Abort a possible executing ECB operation */ + +/* Bit 0 : Abort a possible executing ECB operation */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ + +/* Register: ECB_EVENTS_ENDECB */ +/* Description: ECB block encrypt complete */ + +/* Bit 0 : ECB block encrypt complete */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_EVENTS_ERRORECB */ +/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ + +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ + +/* Register: ECB_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ +#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ +#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ + +/* Register: ECB_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ +#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ +#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ +#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ +#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ +#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ +#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ + +/* Register: ECB_ECBDATAPTR */ +/* Description: ECB block encrypt memory pointers */ + +/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ +#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ + + +/* Peripheral: EGU */ +/* Description: Event Generator Unit 0 */ + +/* Register: EGU_TASKS_TRIGGER */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ + +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ + +/* Register: EGU_EVENTS_TRIGGERED */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ + +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ + +/* Register: EGU_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ +#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ +#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ +#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ +#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ +#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ +#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ +#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ +#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ +#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ +#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ +#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ +#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ +#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ +#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ +#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ +#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ + +/* Register: EGU_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ +#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ +#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ +#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ +#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ +#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ +#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ +#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ +#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ +#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ +#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ +#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ +#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ +#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ +#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ +#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ +#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ + +/* Register: EGU_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ +#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ +#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ +#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ +#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ +#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ +#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ +#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ +#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ +#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ +#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ +#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ +#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ +#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ +#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ +#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ +#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ + + +/* Peripheral: FICR */ +/* Description: Factory information configuration registers */ + +/* Register: FICR_CODEPAGESIZE */ +/* Description: Code memory page size */ + +/* Bits 31..0 : Code memory page size */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ +#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ + +/* Register: FICR_CODESIZE */ +/* Description: Code memory size */ + +/* Bits 31..0 : Code memory size in number of pages */ +#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ +#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ + +/* Register: FICR_DEVICEID */ +/* Description: Description collection: Device identifier */ + +/* Bits 31..0 : 64 bit unique device identifier */ +#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ +#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ + +/* Register: FICR_ER */ +/* Description: Description collection: Encryption root, word n */ + +/* Bits 31..0 : Encryption root, word n */ +#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ +#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ + +/* Register: FICR_IR */ +/* Description: Description collection: Identity root, word n */ + +/* Bits 31..0 : Identity root, word n */ +#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ +#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ + +/* Register: FICR_DEVICEADDRTYPE */ +/* Description: Device address type */ + +/* Bit 0 : Device address type */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ +#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ + +/* Register: FICR_DEVICEADDR */ +/* Description: Description collection: Device address n */ + +/* Bits 31..0 : 48 bit device address */ +#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ +#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ + +/* Register: FICR_INFO_PART */ +/* Description: Part code */ + +/* Bits 31..0 : Part code */ +#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ +#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52810 (0x52810UL) /*!< nRF52810 */ +#define FICR_INFO_PART_PART_N52811 (0x52811UL) /*!< nRF52811 */ +#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_VARIANT */ +/* Description: Part variant, hardware version and production configuration */ + +/* Bits 31..0 : Part variant, hardware version and production configuration, encoded as ASCII */ +#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ +#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ +#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ +#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ +#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_AACB (0x41414342UL) /*!< AACB */ +#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_PACKAGE */ +/* Description: Package option */ + +/* Bits 31..0 : Package option */ +#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ +#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QC (0x2003UL) /*!< QCxx - 32-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_RAM */ +/* Description: RAM variant */ + +/* Bits 31..0 : RAM variant */ +#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ +#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ +#define FICR_INFO_RAM_RAM_K24 (0x18UL) /*!< 24 kByte RAM */ +#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_INFO_FLASH */ +/* Description: Flash variant */ + +/* Bits 31..0 : Flash variant */ +#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ +#define FICR_INFO_FLASH_FLASH_K192 (0xC0UL) /*!< 192 kByte flash */ +#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ + +/* Register: FICR_TEMP_A0 */ +/* Description: Slope definition A0 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A1 */ +/* Description: Slope definition A1 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A2 */ +/* Description: Slope definition A2 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A3 */ +/* Description: Slope definition A3 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A4 */ +/* Description: Slope definition A4 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_A5 */ +/* Description: Slope definition A5 */ + +/* Bits 11..0 : A (slope definition) register */ +#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ +#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ + +/* Register: FICR_TEMP_B0 */ +/* Description: Y-intercept B0 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B1 */ +/* Description: Y-intercept B1 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B2 */ +/* Description: Y-intercept B2 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B3 */ +/* Description: Y-intercept B3 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B4 */ +/* Description: Y-intercept B4 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_B5 */ +/* Description: Y-intercept B5 */ + +/* Bits 13..0 : B (y-intercept) */ +#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ +#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ + +/* Register: FICR_TEMP_T0 */ +/* Description: Segment end T0 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T1 */ +/* Description: Segment end T1 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T2 */ +/* Description: Segment end T2 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T3 */ +/* Description: Segment end T3 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ + +/* Register: FICR_TEMP_T4 */ +/* Description: Segment end T4 */ + +/* Bits 7..0 : T (segment end) register */ +#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ +#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ + + +/* Peripheral: GPIOTE */ +/* Description: GPIO Tasks and Events */ + +/* Register: GPIOTE_TASKS_OUT */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_SET */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_TASKS_CLR */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ + +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ + +/* Register: GPIOTE_EVENTS_IN */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ + +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_EVENTS_PORT */ +/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ + +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ + +/* Register: GPIOTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 31 : Write '1' to enable interrupt for event PORT */ +#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ +#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ +#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ +#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ +#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ +#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ +#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ +#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ +#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ + +/* Register: GPIOTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 31 : Write '1' to disable interrupt for event PORT */ +#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ +#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ +#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ +#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ +#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ +#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ +#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ +#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ +#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ +#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ +#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ +#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ +#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ +#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ +#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ +#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ +#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ + +/* Register: GPIOTE_CONFIG */ +/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ + +/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ +#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ +#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ + +/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ +#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ +#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ + +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ +#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ + +/* Bits 1..0 : Mode */ +#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ + + +/* Peripheral: NVMC */ +/* Description: Non-volatile memory controller */ + +/* Register: NVMC_READY */ +/* Description: Ready flag */ + +/* Bit 0 : NVMC is ready or busy */ +#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ +#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ +#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ + +/* Register: NVMC_CONFIG */ +/* Description: Configuration register */ + +/* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */ +#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ +#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ +#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ + +/* Register: NVMC_ERASEPAGE */ +/* Description: Register for erasing a page in code area */ + +/* Bits 31..0 : Register for starting erase of a page in code area. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ +#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ + +/* Register: NVMC_ERASEPCR1 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ +#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ + +/* Register: NVMC_ERASEALL */ +/* Description: Register for erasing all non-volatile user memory */ + +/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */ + +/* Register: NVMC_ERASEPCR0 */ +/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ + +/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ +#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ + +/* Register: NVMC_ERASEUICR */ +/* Description: Register for erasing user information configuration registers */ + +/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ +#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ +#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ + +/* Register: NVMC_ERASEPAGEPARTIAL */ +/* Description: Register for partial erase of a page in code area */ + +/* Bits 31..0 : Register for starting partial erase of a page in code area */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ +#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ + +/* Register: NVMC_ERASEPAGEPARTIALCFG */ +/* Description: Register for partial erase configuration */ + +/* Bits 6..0 : Duration of the partial erase in milliseconds */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ +#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ + + +/* Peripheral: GPIO */ +/* Description: GPIO Port */ + +/* Register: GPIO_OUT */ +/* Description: Write GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ + +/* Register: GPIO_OUTSET */ +/* Description: Set individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ + +/* Register: GPIO_OUTCLR */ +/* Description: Clear individual bits in GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 30 : Pin 30 */ +#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 29 : Pin 29 */ +#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 28 : Pin 28 */ +#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 27 : Pin 27 */ +#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 26 : Pin 26 */ +#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 25 : Pin 25 */ +#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 24 : Pin 24 */ +#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 23 : Pin 23 */ +#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 22 : Pin 22 */ +#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 21 : Pin 21 */ +#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 20 : Pin 20 */ +#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 19 : Pin 19 */ +#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 18 : Pin 18 */ +#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 17 : Pin 17 */ +#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 16 : Pin 16 */ +#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 15 : Pin 15 */ +#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 14 : Pin 14 */ +#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 13 : Pin 13 */ +#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 12 : Pin 12 */ +#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 11 : Pin 11 */ +#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 10 : Pin 10 */ +#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 9 : Pin 9 */ +#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 8 : Pin 8 */ +#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 7 : Pin 7 */ +#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 6 : Pin 6 */ +#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 5 : Pin 5 */ +#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 4 : Pin 4 */ +#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 3 : Pin 3 */ +#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 2 : Pin 2 */ +#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 1 : Pin 1 */ +#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Bit 0 : Pin 0 */ +#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ + +/* Register: GPIO_IN */ +/* Description: Read GPIO port */ + +/* Bit 31 : Pin 31 */ +#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ + +/* Bit 30 : Pin 30 */ +#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ + +/* Bit 29 : Pin 29 */ +#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ + +/* Bit 28 : Pin 28 */ +#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ + +/* Bit 27 : Pin 27 */ +#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ + +/* Bit 26 : Pin 26 */ +#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ + +/* Bit 25 : Pin 25 */ +#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ + +/* Bit 24 : Pin 24 */ +#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ + +/* Bit 23 : Pin 23 */ +#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ + +/* Bit 22 : Pin 22 */ +#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ + +/* Bit 21 : Pin 21 */ +#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ + +/* Bit 20 : Pin 20 */ +#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ + +/* Bit 19 : Pin 19 */ +#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ + +/* Bit 18 : Pin 18 */ +#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ + +/* Bit 17 : Pin 17 */ +#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ + +/* Bit 16 : Pin 16 */ +#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ + +/* Bit 15 : Pin 15 */ +#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ + +/* Bit 14 : Pin 14 */ +#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ + +/* Bit 13 : Pin 13 */ +#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ + +/* Bit 12 : Pin 12 */ +#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ + +/* Bit 11 : Pin 11 */ +#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ + +/* Bit 10 : Pin 10 */ +#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ + +/* Bit 9 : Pin 9 */ +#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ + +/* Bit 8 : Pin 8 */ +#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ + +/* Bit 7 : Pin 7 */ +#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ + +/* Bit 6 : Pin 6 */ +#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ + +/* Bit 5 : Pin 5 */ +#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ + +/* Bit 4 : Pin 4 */ +#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ + +/* Bit 3 : Pin 3 */ +#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ + +/* Bit 2 : Pin 2 */ +#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ + +/* Bit 1 : Pin 1 */ +#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ + +/* Bit 0 : Pin 0 */ +#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ + +/* Register: GPIO_DIR */ +/* Description: Direction of GPIO pins */ + +/* Bit 31 : Pin 31 */ +#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ + +/* Bit 30 : Pin 30 */ +#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ + +/* Bit 29 : Pin 29 */ +#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ + +/* Bit 28 : Pin 28 */ +#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ + +/* Bit 27 : Pin 27 */ +#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ + +/* Bit 26 : Pin 26 */ +#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ + +/* Bit 25 : Pin 25 */ +#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ + +/* Bit 24 : Pin 24 */ +#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ + +/* Bit 23 : Pin 23 */ +#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ + +/* Bit 22 : Pin 22 */ +#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ + +/* Bit 21 : Pin 21 */ +#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ + +/* Bit 20 : Pin 20 */ +#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ + +/* Bit 19 : Pin 19 */ +#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ + +/* Bit 18 : Pin 18 */ +#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ + +/* Bit 17 : Pin 17 */ +#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ + +/* Bit 16 : Pin 16 */ +#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ + +/* Bit 15 : Pin 15 */ +#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ + +/* Bit 14 : Pin 14 */ +#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ + +/* Bit 13 : Pin 13 */ +#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ + +/* Bit 12 : Pin 12 */ +#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ + +/* Bit 11 : Pin 11 */ +#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ + +/* Bit 10 : Pin 10 */ +#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ + +/* Bit 9 : Pin 9 */ +#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ + +/* Bit 8 : Pin 8 */ +#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ + +/* Bit 7 : Pin 7 */ +#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ + +/* Bit 6 : Pin 6 */ +#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ + +/* Bit 5 : Pin 5 */ +#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ + +/* Bit 4 : Pin 4 */ +#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ + +/* Bit 3 : Pin 3 */ +#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ + +/* Bit 2 : Pin 2 */ +#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ + +/* Bit 1 : Pin 1 */ +#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ + +/* Bit 0 : Pin 0 */ +#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ + +/* Register: GPIO_DIRSET */ +/* Description: DIR set register */ + +/* Bit 31 : Set as output pin 31 */ +#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 30 : Set as output pin 30 */ +#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 29 : Set as output pin 29 */ +#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 28 : Set as output pin 28 */ +#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 27 : Set as output pin 27 */ +#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 26 : Set as output pin 26 */ +#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 25 : Set as output pin 25 */ +#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 24 : Set as output pin 24 */ +#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 23 : Set as output pin 23 */ +#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 22 : Set as output pin 22 */ +#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 21 : Set as output pin 21 */ +#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 20 : Set as output pin 20 */ +#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 19 : Set as output pin 19 */ +#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 18 : Set as output pin 18 */ +#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 17 : Set as output pin 17 */ +#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 16 : Set as output pin 16 */ +#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 15 : Set as output pin 15 */ +#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 14 : Set as output pin 14 */ +#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 13 : Set as output pin 13 */ +#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 12 : Set as output pin 12 */ +#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 11 : Set as output pin 11 */ +#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 10 : Set as output pin 10 */ +#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 9 : Set as output pin 9 */ +#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 8 : Set as output pin 8 */ +#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 7 : Set as output pin 7 */ +#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 6 : Set as output pin 6 */ +#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 5 : Set as output pin 5 */ +#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 4 : Set as output pin 4 */ +#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 3 : Set as output pin 3 */ +#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 2 : Set as output pin 2 */ +#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 1 : Set as output pin 1 */ +#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Bit 0 : Set as output pin 0 */ +#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ + +/* Register: GPIO_DIRCLR */ +/* Description: DIR clear register */ + +/* Bit 31 : Set as input pin 31 */ +#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 30 : Set as input pin 30 */ +#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 29 : Set as input pin 29 */ +#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 28 : Set as input pin 28 */ +#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 27 : Set as input pin 27 */ +#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 26 : Set as input pin 26 */ +#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 25 : Set as input pin 25 */ +#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 24 : Set as input pin 24 */ +#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 23 : Set as input pin 23 */ +#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 22 : Set as input pin 22 */ +#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 21 : Set as input pin 21 */ +#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 20 : Set as input pin 20 */ +#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 19 : Set as input pin 19 */ +#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 18 : Set as input pin 18 */ +#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 17 : Set as input pin 17 */ +#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 16 : Set as input pin 16 */ +#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 15 : Set as input pin 15 */ +#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 14 : Set as input pin 14 */ +#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 13 : Set as input pin 13 */ +#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 12 : Set as input pin 12 */ +#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 11 : Set as input pin 11 */ +#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 10 : Set as input pin 10 */ +#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 9 : Set as input pin 9 */ +#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 8 : Set as input pin 8 */ +#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 7 : Set as input pin 7 */ +#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 6 : Set as input pin 6 */ +#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 5 : Set as input pin 5 */ +#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 4 : Set as input pin 4 */ +#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 3 : Set as input pin 3 */ +#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 2 : Set as input pin 2 */ +#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 1 : Set as input pin 1 */ +#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Bit 0 : Set as input pin 0 */ +#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ + +/* Register: GPIO_LATCH */ +/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ + +/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ +#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ +#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ +#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ +#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ +#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ +#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ +#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ +#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ +#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ +#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ +#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ +#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ +#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ +#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ +#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ +#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ +#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ +#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ +#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ +#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ +#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ +#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ +#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ +#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ +#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ +#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ +#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ +#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ +#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ +#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ +#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ +#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ +#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ +#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ +#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ +#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ +#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ +#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ +#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ +#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ +#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ +#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ +#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ +#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ +#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ +#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ +#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ +#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ +#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ +#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ +#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ +#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ +#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ +#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ +#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ +#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ +#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ +#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ +#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ +#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ +#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ +#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ + +/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ +#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ +#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ + +/* Register: GPIO_DETECTMODE */ +/* Description: Select between default DETECT signal behaviour and LDETECT mode */ + +/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ + +/* Register: GPIO_PIN_CNF */ +/* Description: Description collection: Configuration of GPIO pins */ + +/* Bits 17..16 : Pin sensing mechanism */ +#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ +#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ + +/* Bits 10..8 : Drive configuration */ +#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ + +/* Bits 3..2 : Pull configuration */ +#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ +#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ +#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ + +/* Bit 1 : Connect or disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ +#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ + +/* Bit 0 : Pin direction. Same physical register as DIR register */ +#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ +#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ +#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ + + +/* Peripheral: PDM */ +/* Description: Pulse Density Modulation (Digital Microphone) Interface */ + +/* Register: PDM_TASKS_START */ +/* Description: Starts continuous PDM transfer */ + +/* Bit 0 : Starts continuous PDM transfer */ +#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_TASKS_STOP */ +/* Description: Stops PDM transfer */ + +/* Bit 0 : Stops PDM transfer */ +#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PDM_EVENTS_STARTED */ +/* Description: PDM transfer has started */ + +/* Bit 0 : PDM transfer has started */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_STOPPED */ +/* Description: PDM transfer has finished */ + +/* Bit 0 : PDM transfer has finished */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_EVENTS_END */ +/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ + +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ +#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: PDM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 2 : Enable or disable interrupt for event END */ +#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event END */ +#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: PDM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event END */ +#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ +#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: PDM_ENABLE */ +/* Description: PDM module enable register */ + +/* Bit 0 : Enable or disable PDM module */ +#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PDM_PDMCLKCTRL */ +/* Description: PDM clock generator control */ + +/* Bits 31..0 : PDM_CLK frequency */ +#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ +#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ +#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ +#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ + +/* Register: PDM_MODE */ +/* Description: Defines the routing of the connected PDM microphones' signals */ + +/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ +#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ +#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ + +/* Bit 0 : Mono or stereo operation */ +#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ +#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ + +/* Register: PDM_GAINL */ +/* Description: Left output gain adjustment */ + +/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ +#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ +#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_GAINR */ +/* Description: Right output gain adjustment */ + +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ + +/* Register: PDM_PSEL_CLK */ +/* Description: Pin number configuration for PDM CLK signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_PSEL_DIN */ +/* Description: Pin number configuration for PDM DIN signal */ + +/* Bit 31 : Connection */ +#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: PDM_SAMPLE_PTR */ +/* Description: RAM address pointer to write samples to with EasyDMA */ + +/* Bits 31..0 : Address to write PDM samples to over DMA */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ +#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ + +/* Register: PDM_SAMPLE_MAXCNT */ +/* Description: Number of samples to allocate memory for in EasyDMA mode */ + +/* Bits 14..0 : Length of DMA RAM allocation in number of samples */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ +#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ + + +/* Peripheral: POWER */ +/* Description: Power control */ + +/* Register: POWER_TASKS_CONSTLAT */ +/* Description: Enable constant latency mode */ + +/* Bit 0 : Enable constant latency mode */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_TASKS_LOWPWR */ +/* Description: Enable low power mode (variable latency) */ + +/* Bit 0 : Enable low power mode (variable latency) */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ + +/* Register: POWER_EVENTS_POFWARN */ +/* Description: Power failure warning */ + +/* Bit 0 : Power failure warning */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPENTER */ +/* Description: CPU entered WFI/WFE sleep */ + +/* Bit 0 : CPU entered WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_EVENTS_SLEEPEXIT */ +/* Description: CPU exited WFI/WFE sleep */ + +/* Bit 0 : CPU exited WFI/WFE sleep */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ + +/* Register: POWER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ +#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ +#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ +#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ + +/* Register: POWER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ +#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ +#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ +#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ +#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ + +/* Register: POWER_RESETREAS */ +/* Description: Reset reason */ + +/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ +#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ +#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ +#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ + +/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ +#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ +#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ +#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ + +/* Bit 3 : Reset from CPU lock-up detected */ +#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ + +/* Bit 2 : Reset from soft reset detected */ +#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ +#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ +#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ + +/* Bit 1 : Reset from watchdog detected */ +#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ +#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ +#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ + +/* Bit 0 : Reset from pin-reset detected */ +#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ + +/* Register: POWER_SYSTEMOFF */ +/* Description: System OFF register */ + +/* Bit 0 : Enable System OFF mode */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ +#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ + +/* Register: POWER_POFCON */ +/* Description: Power failure comparator configuration */ + +/* Bits 4..1 : Power failure comparator threshold setting */ +#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ +#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ +#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ +#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ +#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ +#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ +#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ +#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ +#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ +#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ +#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ +#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ +#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ + +/* Bit 0 : Enable or disable power failure comparator */ +#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ +#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ +#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ +#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_GPREGRET */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_GPREGRET2 */ +/* Description: General purpose retention register */ + +/* Bits 7..0 : General purpose retention register */ +#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ +#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ + +/* Register: POWER_DCDCEN */ +/* Description: DC/DC enable register */ + +/* Bit 0 : Enable or disable DC/DC converter */ +#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ +#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ +#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ + +/* Register: POWER_RAM_POWER */ +/* Description: Description cluster: RAMn power control register. The RAM size will vary depending on product variant, and the RAMn register will only be present if the corresponding RAM AHB slave is present on the device. */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ +#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ +#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ +#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ +#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERSET */ +/* Description: Description cluster: RAMn power control set register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ + +/* Register: POWER_RAM_POWERCLR */ +/* Description: Description cluster: RAMn power control clear register */ + +/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ +#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ + +/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ +#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ +#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ + +/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ +#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ + +/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ +#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ + + +/* Peripheral: PPI */ +/* Description: Programmable Peripheral Interconnect */ + +/* Register: PPI_TASKS_CHG_EN */ +/* Description: Description cluster: Enable channel group n */ + +/* Bit 0 : Enable channel group n */ +#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_TASKS_CHG_DIS */ +/* Description: Description cluster: Disable channel group n */ + +/* Bit 0 : Disable channel group n */ +#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ + +/* Register: PPI_CHEN */ +/* Description: Channel enable register */ + +/* Bit 31 : Enable or disable channel 31 */ +#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ + +/* Bit 30 : Enable or disable channel 30 */ +#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ + +/* Bit 29 : Enable or disable channel 29 */ +#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ + +/* Bit 28 : Enable or disable channel 28 */ +#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ + +/* Bit 27 : Enable or disable channel 27 */ +#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ + +/* Bit 26 : Enable or disable channel 26 */ +#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ + +/* Bit 25 : Enable or disable channel 25 */ +#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ + +/* Bit 24 : Enable or disable channel 24 */ +#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ + +/* Bit 23 : Enable or disable channel 23 */ +#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ + +/* Bit 22 : Enable or disable channel 22 */ +#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ + +/* Bit 21 : Enable or disable channel 21 */ +#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ + +/* Bit 20 : Enable or disable channel 20 */ +#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ + +/* Bit 19 : Enable or disable channel 19 */ +#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ + +/* Bit 18 : Enable or disable channel 18 */ +#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ + +/* Bit 17 : Enable or disable channel 17 */ +#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ + +/* Bit 16 : Enable or disable channel 16 */ +#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ + +/* Bit 15 : Enable or disable channel 15 */ +#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ + +/* Bit 14 : Enable or disable channel 14 */ +#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ + +/* Bit 13 : Enable or disable channel 13 */ +#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ + +/* Bit 12 : Enable or disable channel 12 */ +#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ + +/* Bit 11 : Enable or disable channel 11 */ +#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ + +/* Bit 10 : Enable or disable channel 10 */ +#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ + +/* Bit 9 : Enable or disable channel 9 */ +#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ + +/* Bit 8 : Enable or disable channel 8 */ +#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ + +/* Bit 7 : Enable or disable channel 7 */ +#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ + +/* Bit 6 : Enable or disable channel 6 */ +#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ + +/* Bit 5 : Enable or disable channel 5 */ +#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ + +/* Bit 4 : Enable or disable channel 4 */ +#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ + +/* Bit 3 : Enable or disable channel 3 */ +#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ + +/* Bit 2 : Enable or disable channel 2 */ +#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ + +/* Bit 1 : Enable or disable channel 1 */ +#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ + +/* Bit 0 : Enable or disable channel 0 */ +#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ +#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ + +/* Register: PPI_CHENSET */ +/* Description: Channel enable set register */ + +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ + +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ + +/* Register: PPI_CHENCLR */ +/* Description: Channel enable clear register */ + +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ + +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ +#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ +#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ + +/* Register: PPI_CH_EEP */ +/* Description: Description cluster: Channel n event end-point */ + +/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ +#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ +#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ + +/* Register: PPI_CH_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ +#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + +/* Register: PPI_CHG */ +/* Description: Description collection: Channel group n */ + +/* Bit 31 : Include or exclude channel 31 */ +#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ +#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ +#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH31_Included (1UL) /*!< Include */ + +/* Bit 30 : Include or exclude channel 30 */ +#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ +#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ +#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH30_Included (1UL) /*!< Include */ + +/* Bit 29 : Include or exclude channel 29 */ +#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ +#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ +#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH29_Included (1UL) /*!< Include */ + +/* Bit 28 : Include or exclude channel 28 */ +#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ +#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ +#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH28_Included (1UL) /*!< Include */ + +/* Bit 27 : Include or exclude channel 27 */ +#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ +#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ +#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH27_Included (1UL) /*!< Include */ + +/* Bit 26 : Include or exclude channel 26 */ +#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ +#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ +#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH26_Included (1UL) /*!< Include */ + +/* Bit 25 : Include or exclude channel 25 */ +#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ +#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ +#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH25_Included (1UL) /*!< Include */ + +/* Bit 24 : Include or exclude channel 24 */ +#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ +#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ +#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH24_Included (1UL) /*!< Include */ + +/* Bit 23 : Include or exclude channel 23 */ +#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ +#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ +#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH23_Included (1UL) /*!< Include */ + +/* Bit 22 : Include or exclude channel 22 */ +#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ +#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ +#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH22_Included (1UL) /*!< Include */ + +/* Bit 21 : Include or exclude channel 21 */ +#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ +#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ +#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH21_Included (1UL) /*!< Include */ + +/* Bit 20 : Include or exclude channel 20 */ +#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ +#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ +#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH20_Included (1UL) /*!< Include */ + +/* Bit 19 : Include or exclude channel 19 */ +#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ +#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ +#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH19_Included (1UL) /*!< Include */ + +/* Bit 18 : Include or exclude channel 18 */ +#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ +#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ +#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH18_Included (1UL) /*!< Include */ + +/* Bit 17 : Include or exclude channel 17 */ +#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ +#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ +#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH17_Included (1UL) /*!< Include */ + +/* Bit 16 : Include or exclude channel 16 */ +#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ +#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ +#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH16_Included (1UL) /*!< Include */ + +/* Bit 15 : Include or exclude channel 15 */ +#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ +#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ +#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH15_Included (1UL) /*!< Include */ + +/* Bit 14 : Include or exclude channel 14 */ +#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ +#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ +#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH14_Included (1UL) /*!< Include */ + +/* Bit 13 : Include or exclude channel 13 */ +#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ +#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ +#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH13_Included (1UL) /*!< Include */ + +/* Bit 12 : Include or exclude channel 12 */ +#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ +#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ +#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH12_Included (1UL) /*!< Include */ + +/* Bit 11 : Include or exclude channel 11 */ +#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ +#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ +#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH11_Included (1UL) /*!< Include */ + +/* Bit 10 : Include or exclude channel 10 */ +#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ +#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ +#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH10_Included (1UL) /*!< Include */ + +/* Bit 9 : Include or exclude channel 9 */ +#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ +#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ +#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH9_Included (1UL) /*!< Include */ + +/* Bit 8 : Include or exclude channel 8 */ +#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ +#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ +#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH8_Included (1UL) /*!< Include */ + +/* Bit 7 : Include or exclude channel 7 */ +#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ +#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ +#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH7_Included (1UL) /*!< Include */ + +/* Bit 6 : Include or exclude channel 6 */ +#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ +#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ +#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH6_Included (1UL) /*!< Include */ + +/* Bit 5 : Include or exclude channel 5 */ +#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ +#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ +#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH5_Included (1UL) /*!< Include */ + +/* Bit 4 : Include or exclude channel 4 */ +#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ +#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ +#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH4_Included (1UL) /*!< Include */ + +/* Bit 3 : Include or exclude channel 3 */ +#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ +#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ +#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH3_Included (1UL) /*!< Include */ + +/* Bit 2 : Include or exclude channel 2 */ +#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ +#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ +#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH2_Included (1UL) /*!< Include */ + +/* Bit 1 : Include or exclude channel 1 */ +#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ +#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ +#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH1_Included (1UL) /*!< Include */ + +/* Bit 0 : Include or exclude channel 0 */ +#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ +#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ +#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ +#define PPI_CHG_CH0_Included (1UL) /*!< Include */ + +/* Register: PPI_FORK_TEP */ +/* Description: Description cluster: Channel n task end-point */ + +/* Bits 31..0 : Pointer to task register */ +#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ +#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ + + +/* Peripheral: PWM */ +/* Description: Pulse width modulation unit */ + +/* Register: PWM_TASKS_STOP */ +/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ + +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ +#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_SEQSTART */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ + +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_TASKS_NEXTSTEP */ +/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ + +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ + +/* Register: PWM_EVENTS_STOPPED */ +/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ + +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQSTARTED */ +/* Description: Description collection: First PWM period started on sequence n */ + +/* Bit 0 : First PWM period started on sequence n */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_SEQEND */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ + +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_PWMPERIODEND */ +/* Description: Emitted at the end of each PWM period */ + +/* Bit 0 : Emitted at the end of each PWM period */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_EVENTS_LOOPSDONE */ +/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ + +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ + +/* Register: PWM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ +#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ +#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ +#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: PWM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ +#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ +#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ +#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ +#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ +#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ +#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ +#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ +#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: PWM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ +#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ +#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ +#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ +#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ +#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ +#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ +#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ +#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: PWM_ENABLE */ +/* Description: PWM module enable register */ + +/* Bit 0 : Enable or disable PWM module */ +#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: PWM_MODE */ +/* Description: Selects operating mode of the wave counter */ + +/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ + +/* Register: PWM_COUNTERTOP */ +/* Description: Value up to which the pulse generator counter counts */ + +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ +#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ + +/* Register: PWM_PRESCALER */ +/* Description: Configuration for PWM_CLK */ + +/* Bits 2..0 : Prescaler of PWM_CLK */ +#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ + +/* Register: PWM_DECODER */ +/* Description: Configuration of the decoder */ + +/* Bit 8 : Selects source for advancing the active sequence */ +#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ +#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ +#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ + +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ + +/* Register: PWM_LOOP */ +/* Description: Number of playbacks of a loop */ + +/* Bits 15..0 : Number of playbacks of pattern cycles */ +#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ + +/* Register: PWM_SEQ_PTR */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ + +/* Bits 31..0 : Beginning address in RAM of this sequence */ +#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: PWM_SEQ_CNT */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ + +/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ + +/* Register: PWM_SEQ_REFRESH */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ + +/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ + +/* Register: PWM_SEQ_ENDDELAY */ +/* Description: Description cluster: Time added after the sequence */ + +/* Bits 23..0 : Time added after the sequence in PWM periods */ +#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ +#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ + +/* Register: PWM_PSEL_OUT */ +/* Description: Description collection: Output pin select for PWM channel n */ + +/* Bit 31 : Connection */ +#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ + + +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : Task starting the quadrature decoder */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : Task stopping the quadrature decoder */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : Read and clear ACC and ACCDBL */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : Read and clear ACC */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : Read and clear ACCDBL */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : Non-null report ready */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : ACC or ACCDBL register overflow */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : Double displacement(s) detected */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : QDEC has been stopped */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + +/* Peripheral: RADIO */ +/* Description: 2.4 GHz radio */ + +/* Register: RADIO_TASKS_TXEN */ +/* Description: Enable RADIO in TX mode */ + +/* Bit 0 : Enable RADIO in TX mode */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RXEN */ +/* Description: Enable RADIO in RX mode */ + +/* Bit 0 : Enable RADIO in RX mode */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_START */ +/* Description: Start RADIO */ + +/* Bit 0 : Start RADIO */ +#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_STOP */ +/* Description: Stop RADIO */ + +/* Bit 0 : Stop RADIO */ +#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_DISABLE */ +/* Description: Disable RADIO */ + +/* Bit 0 : Disable RADIO */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTART */ +/* Description: Start the RSSI and take one single sample of the receive signal strength */ + +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_RSSISTOP */ +/* Description: Stop the RSSI measurement */ + +/* Bit 0 : Stop the RSSI measurement */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTART */ +/* Description: Start the bit counter */ + +/* Bit 0 : Start the bit counter */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_BCSTOP */ +/* Description: Stop the bit counter */ + +/* Bit 0 : Stop the bit counter */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTART */ +/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_EDSTOP */ +/* Description: Stop the energy detect measurement */ + +/* Bit 0 : Stop the energy detect measurement */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTART */ +/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ + +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_TASKS_CCASTOP */ +/* Description: Stop the clear channel assessment */ + +/* Bit 0 : Stop the clear channel assessment */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RADIO_EVENTS_READY */ +/* Description: RADIO has ramped up and is ready to be started */ + +/* Bit 0 : RADIO has ramped up and is ready to be started */ +#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_ADDRESS */ +/* Description: Address sent or received */ + +/* Bit 0 : Address sent or received */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PAYLOAD */ +/* Description: Packet payload sent or received */ + +/* Bit 0 : Packet payload sent or received */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_END */ +/* Description: Packet sent or received */ + +/* Bit 0 : Packet sent or received */ +#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DISABLED */ +/* Description: RADIO has been disabled */ + +/* Bit 0 : RADIO has been disabled */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMATCH */ +/* Description: A device address match occurred on the last received packet */ + +/* Bit 0 : A device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_DEVMISS */ +/* Description: No device address match occurred on the last received packet */ + +/* Bit 0 : No device address match occurred on the last received packet */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RSSIEND */ +/* Description: Sampling of receive signal strength complete */ + +/* Bit 0 : Sampling of receive signal strength complete */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_BCMATCH */ +/* Description: Bit counter reached bit count value */ + +/* Bit 0 : Bit counter reached bit count value */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCOK */ +/* Description: Packet received with CRC ok */ + +/* Bit 0 : Packet received with CRC ok */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CRCERROR */ +/* Description: Packet received with CRC error */ + +/* Bit 0 : Packet received with CRC error */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_FRAMESTART */ +/* Description: IEEE 802.15.4 length field received */ + +/* Bit 0 : IEEE 802.15.4 length field received */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDEND */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ + +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_EDSTOPPED */ +/* Description: The sampling of energy detection has stopped */ + +/* Bit 0 : The sampling of energy detection has stopped */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCAIDLE */ +/* Description: Wireless medium in idle - clear to send */ + +/* Bit 0 : Wireless medium in idle - clear to send */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCABUSY */ +/* Description: Wireless medium busy - do not send */ + +/* Bit 0 : Wireless medium busy - do not send */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_CCASTOPPED */ +/* Description: The CCA has stopped */ + +/* Bit 0 : The CCA has stopped */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RATEBOOST */ +/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ + +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_TXREADY */ +/* Description: RADIO has ramped up and is ready to be started TX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_RXREADY */ +/* Description: RADIO has ramped up and is ready to be started RX path */ + +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_MHRMATCH */ +/* Description: MAC header match found */ + +/* Bit 0 : MAC header match found */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_EVENTS_PHYEND */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ + +/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ + +/* Register: RADIO_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 21 : Shortcut between event PHYEND and task START */ +#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ +#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ +#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ +#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 19 : Shortcut between event RXREADY and task START */ +#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ +#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 18 : Shortcut between event TXREADY and task START */ +#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ +#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ +#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ +#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ +#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ +#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 15 : Shortcut between event READY and task EDSTART */ +#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ +#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ +#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ +#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event END and task START */ +#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ +#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ +#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ +#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ +#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ +#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event END and task DISABLE */ +#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ +#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event READY and task START */ +#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ +#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ +#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ +#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RADIO_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ +#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ +#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ + +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ +#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ + +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ +#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ +#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ +#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ +#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ +#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ +#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ +#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ +#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ +#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ +#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ +#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ +#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ +#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ +#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ +#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event END */ +#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ +#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ +#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event READY */ +#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: RADIO_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ +#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ +#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ +#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ +#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ +#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ +#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ +#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ +#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ +#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ +#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ +#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ +#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ +#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ +#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ +#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ +#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ +#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ +#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ +#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ +#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ +#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ +#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ +#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ +#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ +#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ +#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ +#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ +#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ +#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ +#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ +#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ +#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ +#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ +#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ +#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ +#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event END */ +#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ +#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ +#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ +#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ +#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ +#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event READY */ +#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ +#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: RADIO_CRCSTATUS */ +/* Description: CRC status */ + +/* Bit 0 : CRC status of packet received */ +#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ +#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ + +/* Register: RADIO_RXMATCH */ +/* Description: Received address */ + +/* Bits 2..0 : Received address */ +#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ +#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ + +/* Register: RADIO_RXCRC */ +/* Description: CRC field of previously received packet */ + +/* Bits 23..0 : CRC field of previously received packet */ +#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ +#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ + +/* Register: RADIO_DAI */ +/* Description: Device address match index */ + +/* Bits 2..0 : Device address match index */ +#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ +#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ + +/* Register: RADIO_PDUSTAT */ +/* Description: Payload status */ + +/* Bits 2..1 : Status on what rate packet is received with in Long Range */ +#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ +#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */ +#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */ + +/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ +#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ +#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ + +/* Register: RADIO_PACKETPTR */ +/* Description: Packet pointer */ + +/* Bits 31..0 : Packet pointer */ +#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ +#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ + +/* Register: RADIO_FREQUENCY */ +/* Description: Frequency */ + +/* Bit 8 : Channel map selection. */ +#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ +#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ + +/* Bits 6..0 : Radio channel frequency */ +#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ + +/* Register: RADIO_TXPOWER */ +/* Description: Output power */ + +/* Bits 7..0 : RADIO output power */ +#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ +#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ + +/* Register: RADIO_MODE */ +/* Description: Data rate and modulation */ + +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ +#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ + +/* Register: RADIO_PCNF0 */ +/* Description: Packet configuration register 0 */ + +/* Bits 30..29 : Length of TERM field in Long Range operation */ +#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */ +#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */ + +/* Bit 26 : Indicates if LENGTH field contains CRC or not */ +#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */ +#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */ +#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */ + +/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */ +#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ +#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ +#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ +#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ +#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ + +/* Bits 23..22 : Length of code indicator - long range */ +#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ +#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ + +/* Bit 20 : Include or exclude S1 field in RAM */ +#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ +#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ +#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ + +/* Bits 19..16 : Length on air of S1 field in number of bits. */ +#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ +#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ + +/* Bit 8 : Length on air of S0 field in number of bytes. */ +#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ +#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ + +/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ +#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ + +/* Register: RADIO_PCNF1 */ +/* Description: Packet configuration register 1 */ + +/* Bit 25 : Enable or disable packet whitening */ +#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ +#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ +#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ +#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ + +/* Bits 18..16 : Base address length in number of bytes */ +#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ +#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ + +/* Bits 15..8 : Static length in number of bytes */ +#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ +#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ + +/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ +#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ +#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ + +/* Register: RADIO_BASE0 */ +/* Description: Base address 0 */ + +/* Bits 31..0 : Base address 0 */ +#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ +#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ + +/* Register: RADIO_BASE1 */ +/* Description: Base address 1 */ + +/* Bits 31..0 : Base address 1 */ +#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ +#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ + +/* Register: RADIO_PREFIX0 */ +/* Description: Prefixes bytes for logical addresses 0-3 */ + +/* Bits 31..24 : Address prefix 3. */ +#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ +#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ + +/* Bits 23..16 : Address prefix 2. */ +#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ +#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ + +/* Bits 15..8 : Address prefix 1. */ +#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ +#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ + +/* Bits 7..0 : Address prefix 0. */ +#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ +#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ + +/* Register: RADIO_PREFIX1 */ +/* Description: Prefixes bytes for logical addresses 4-7 */ + +/* Bits 31..24 : Address prefix 7. */ +#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ +#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ + +/* Bits 23..16 : Address prefix 6. */ +#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ +#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ + +/* Bits 15..8 : Address prefix 5. */ +#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ +#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ + +/* Bits 7..0 : Address prefix 4. */ +#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ +#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ + +/* Register: RADIO_TXADDRESS */ +/* Description: Transmit address select */ + +/* Bits 2..0 : Transmit address select */ +#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ +#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ + +/* Register: RADIO_RXADDRESSES */ +/* Description: Receive address select */ + +/* Bit 7 : Enable or disable reception on logical address 7. */ +#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ +#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable reception on logical address 6. */ +#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ +#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable reception on logical address 5. */ +#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ +#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable reception on logical address 4. */ +#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ +#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable reception on logical address 3. */ +#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ +#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable reception on logical address 2. */ +#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ +#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable reception on logical address 1. */ +#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ +#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable reception on logical address 0. */ +#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ +#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ +#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ + +/* Register: RADIO_CRCCNF */ +/* Description: CRC configuration */ + +/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */ +#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ +#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ +#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ +#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ + +/* Bits 1..0 : CRC length in number of bytes. */ +#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ +#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ +#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ +#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ +#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ + +/* Register: RADIO_CRCPOLY */ +/* Description: CRC polynomial */ + +/* Bits 23..0 : CRC polynomial */ +#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ +#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ + +/* Register: RADIO_CRCINIT */ +/* Description: CRC initial value */ + +/* Bits 23..0 : CRC initial value */ +#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ +#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ + +/* Register: RADIO_TIFS */ +/* Description: Interframe spacing in us */ + +/* Bits 9..0 : Interframe spacing in us */ +#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ +#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ + +/* Register: RADIO_RSSISAMPLE */ +/* Description: RSSI sample */ + +/* Bits 6..0 : RSSI sample */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ +#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ + +/* Register: RADIO_STATE */ +/* Description: Current radio state */ + +/* Bits 3..0 : Current radio state */ +#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ +#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ +#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ +#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ +#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ +#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ +#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ +#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ +#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ +#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ +#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ + +/* Register: RADIO_DATAWHITEIV */ +/* Description: Data whitening initial value */ + +/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ +#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ + +/* Register: RADIO_BCC */ +/* Description: Bit counter compare */ + +/* Bits 31..0 : Bit counter compare */ +#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ +#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ + +/* Register: RADIO_DAB */ +/* Description: Description collection: Device address base segment n */ + +/* Bits 31..0 : Device address base segment n */ +#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ +#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ + +/* Register: RADIO_DAP */ +/* Description: Description collection: Device address prefix n */ + +/* Bits 15..0 : Device address prefix n */ +#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ +#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ + +/* Register: RADIO_DACNF */ +/* Description: Device address match configuration */ + +/* Bit 15 : TxAdd for device address 7 */ +#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ +#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ + +/* Bit 14 : TxAdd for device address 6 */ +#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ +#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ + +/* Bit 13 : TxAdd for device address 5 */ +#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ +#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ + +/* Bit 12 : TxAdd for device address 4 */ +#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ +#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ + +/* Bit 11 : TxAdd for device address 3 */ +#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ +#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ + +/* Bit 10 : TxAdd for device address 2 */ +#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ +#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ + +/* Bit 9 : TxAdd for device address 1 */ +#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ +#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ + +/* Bit 8 : TxAdd for device address 0 */ +#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ +#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ + +/* Bit 7 : Enable or disable device address matching using device address 7 */ +#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ +#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ +#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ + +/* Bit 6 : Enable or disable device address matching using device address 6 */ +#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ +#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ +#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ + +/* Bit 5 : Enable or disable device address matching using device address 5 */ +#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ +#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ +#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ + +/* Bit 4 : Enable or disable device address matching using device address 4 */ +#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ +#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ +#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ + +/* Bit 3 : Enable or disable device address matching using device address 3 */ +#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ +#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ +#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ + +/* Bit 2 : Enable or disable device address matching using device address 2 */ +#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ +#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ +#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ + +/* Bit 1 : Enable or disable device address matching using device address 1 */ +#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ +#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ +#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable device address matching using device address 0 */ +#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ +#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ +#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ +#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ + +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + +/* Register: RADIO_MODECNF0 */ +/* Description: Radio mode configuration register 0 */ + +/* Bits 9..8 : Default TX value */ +#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ +#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ +#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ +#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ +#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ + +/* Bit 0 : Radio ramp-up time */ +#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ +#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ + +/* Register: RADIO_SFD */ +/* Description: IEEE 802.15.4 start of frame delimiter */ + +/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ +#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ +#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ + +/* Register: RADIO_EDCNT */ +/* Description: IEEE 802.15.4 energy detect loop count */ + +/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ +#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ +#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ + +/* Register: RADIO_EDSAMPLE */ +/* Description: IEEE 802.15.4 energy detect level */ + +/* Bits 7..0 : IEEE 802.15.4 energy detect level */ +#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ +#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ + +/* Register: RADIO_CCACTRL */ +/* Description: IEEE 802.15.4 clear channel assessment control */ + +/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ +#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ +#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ + +/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ +#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ + +/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ +#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ +#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ + +/* Bits 2..0 : CCA mode of operation */ +#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ + +/* Register: RADIO_POWER */ +/* Description: Peripheral power control */ + +/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ +#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ +#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ + + +/* Peripheral: RNG */ +/* Description: Random Number Generator */ + +/* Register: RNG_TASKS_START */ +/* Description: Task starting the random number generator */ + +/* Bit 0 : Task starting the random number generator */ +#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_TASKS_STOP */ +/* Description: Task stopping the random number generator */ + +/* Bit 0 : Task stopping the random number generator */ +#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RNG_EVENTS_VALRDY */ +/* Description: Event being generated for every new random number written to the VALUE register */ + +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ + +/* Register: RNG_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 0 : Shortcut between event VALRDY and task STOP */ +#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ +#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: RNG_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ +#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ + +/* Register: RNG_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ +#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ +#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ +#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ +#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ + +/* Register: RNG_CONFIG */ +/* Description: Configuration register */ + +/* Bit 0 : Bias correction */ +#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ +#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ +#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ + +/* Register: RNG_VALUE */ +/* Description: Output random number */ + +/* Bits 7..0 : Generated random number */ +#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ +#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ + + +/* Peripheral: RTC */ +/* Description: Real time counter 0 */ + +/* Register: RTC_TASKS_START */ +/* Description: Start RTC COUNTER */ + +/* Bit 0 : Start RTC COUNTER */ +#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_STOP */ +/* Description: Stop RTC COUNTER */ + +/* Bit 0 : Stop RTC COUNTER */ +#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_CLEAR */ +/* Description: Clear RTC COUNTER */ + +/* Bit 0 : Clear RTC COUNTER */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_TASKS_TRIGOVRFLW */ +/* Description: Set COUNTER to 0xFFFFF0 */ + +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ + +/* Register: RTC_EVENTS_TICK */ +/* Description: Event on COUNTER increment */ + +/* Bit 0 : Event on COUNTER increment */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_OVRFLW */ +/* Description: Event on COUNTER overflow */ + +/* Bit 0 : Event on COUNTER overflow */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: RTC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ +#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event TICK */ +#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ +#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event TICK */ +#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_EVTEN */ +/* Description: Enable or disable event routing */ + +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ +#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ + +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ +#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ + +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ +#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ + +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ +#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ + +/* Bit 1 : Enable or disable event routing for event OVRFLW */ +#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ + +/* Bit 0 : Enable or disable event routing for event TICK */ +#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ + +/* Register: RTC_EVTENSET */ +/* Description: Enable event routing */ + +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ +#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ +#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ +#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ +#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ +#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable event routing for event TICK */ +#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ + +/* Register: RTC_EVTENCLR */ +/* Description: Disable event routing */ + +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ +#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ +#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ +#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ +#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ +#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable event routing for event TICK */ +#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ +#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ +#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ + +/* Register: RTC_COUNTER */ +/* Description: Current COUNTER value */ + +/* Bits 23..0 : Counter value */ +#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ +#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ + +/* Register: RTC_PRESCALER */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ + +/* Bits 11..0 : Prescaler value */ +#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: RTC_CC */ +/* Description: Description collection: Compare register n */ + +/* Bits 23..0 : Compare value */ +#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ +#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ + + +/* Peripheral: SAADC */ +/* Description: Analog to Digital Converter */ + +/* Register: SAADC_TASKS_START */ +/* Description: Start the ADC and prepare the result buffer in RAM */ + +/* Bit 0 : Start the ADC and prepare the result buffer in RAM */ +#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_SAMPLE */ +/* Description: Take one ADC sample, if scan is enabled all channels are sampled */ + +/* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_STOP */ +/* Description: Stop the ADC and terminate any on-going conversion */ + +/* Bit 0 : Stop the ADC and terminate any on-going conversion */ +#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_TASKS_CALIBRATEOFFSET */ +/* Description: Starts offset auto-calibration */ + +/* Bit 0 : Starts offset auto-calibration */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ + +/* Register: SAADC_EVENTS_STARTED */ +/* Description: The ADC has started */ + +/* Bit 0 : The ADC has started */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_END */ +/* Description: The ADC has filled up the Result buffer */ + +/* Bit 0 : The ADC has filled up the Result buffer */ +#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_DONE */ +/* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ + +/* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_RESULTDONE */ +/* Description: A result is ready to get transferred to RAM. */ + +/* Bit 0 : A result is ready to get transferred to RAM. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CALIBRATEDONE */ +/* Description: Calibration is complete */ + +/* Bit 0 : Calibration is complete */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_STOPPED */ +/* Description: The ADC has stopped */ + +/* Bit 0 : The ADC has stopped */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITH */ +/* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ + +/* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_EVENTS_CH_LIMITL */ +/* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ + +/* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ + +/* Register: SAADC_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ +#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ +#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ +#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ +#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ +#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ +#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ +#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ +#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ +#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ +#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ +#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ +#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ +#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ +#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ +#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ + +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ +#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ + +/* Bit 5 : Enable or disable interrupt for event STOPPED */ +#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ +#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event DONE */ +#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event END */ +#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event STARTED */ +#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ + +/* Register: SAADC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ +#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ +#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ +#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ +#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ +#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ +#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ +#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ +#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ +#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ +#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ +#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ +#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ +#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ +#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ +#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ +#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ + +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ +#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ +#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event DONE */ +#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Register: SAADC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ +#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ +#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ +#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ +#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ +#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ +#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ +#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ +#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ +#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ +#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ +#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ +#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ +#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ +#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ +#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ +#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ + +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ +#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ +#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ +#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event DONE */ +#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ +#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ +#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Register: SAADC_STATUS */ +/* Description: Status */ + +/* Bit 0 : Status */ +#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ + +/* Register: SAADC_ENABLE */ +/* Description: Enable or disable ADC */ + +/* Bit 0 : Enable or disable ADC */ +#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ + +/* Register: SAADC_CH_PSELP */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ + +/* Bits 4..0 : Analog positive input channel */ +#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ +#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_PSELN */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ + +/* Bits 4..0 : Analog negative input, enables differential channel */ +#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ +#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ + +/* Register: SAADC_CH_CONFIG */ +/* Description: Description cluster: Input configuration for CH[n] */ + +/* Bit 24 : Enable burst mode */ +#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ + +/* Bit 20 : Enable differential mode */ +#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ +#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ + +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ +#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ +#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ + +/* Bit 12 : Reference control */ +#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ + +/* Bits 10..8 : Gain control */ +#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ + +/* Bits 5..4 : Negative channel resistor control */ +#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ +#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Bits 1..0 : Positive channel resistor control */ +#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ +#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ + +/* Register: SAADC_CH_LIMIT */ +/* Description: Description cluster: High/low limits for event monitoring a channel */ + +/* Bits 31..16 : High level limit */ +#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ +#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ + +/* Bits 15..0 : Low level limit */ +#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ +#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ + +/* Register: SAADC_RESOLUTION */ +/* Description: Resolution configuration */ + +/* Bits 2..0 : Set the resolution */ +#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ +#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ + +/* Register: SAADC_OVERSAMPLE */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ + +/* Bits 3..0 : Oversample control */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ + +/* Register: SAADC_SAMPLERATE */ +/* Description: Controls normal or continuous sample rate */ + +/* Bit 12 : Select mode for sample rate control */ +#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ + +/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ +#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ + +/* Register: SAADC_RESULT_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SAADC_RESULT_MAXCNT */ +/* Description: Maximum number of buffer words to transfer */ + +/* Bits 14..0 : Maximum number of buffer words to transfer */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SAADC_RESULT_AMOUNT */ +/* Description: Number of buffer words transferred since last START */ + +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + + +/* Peripheral: SPI */ +/* Description: Serial Peripheral Interface 0 */ + +/* Register: SPI_EVENTS_READY */ +/* Description: TXD byte sent and RXD byte received */ + +/* Bit 0 : TXD byte sent and RXD byte received */ +#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ + +/* Register: SPI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 2 : Write '1' to enable interrupt for event READY */ +#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ + +/* Register: SPI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 2 : Write '1' to disable interrupt for event READY */ +#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ +#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ +#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ +#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ +#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ + +/* Register: SPI_ENABLE */ +/* Description: Enable SPI */ + +/* Bits 3..0 : Enable or disable SPI */ +#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ +#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ + +/* Register: SPI_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received. Double buffered */ +#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: SPI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to send. Double buffered */ +#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: SPI_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPI_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + + +/* Peripheral: SPIM */ +/* Description: Serial Peripheral Interface Master with EasyDMA 0 */ + +/* Register: SPIM_TASKS_START */ +/* Description: Start SPI transaction */ + +/* Bit 0 : Start SPI transaction */ +#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_STOP */ +/* Description: Stop SPI transaction */ + +/* Bit 0 : Stop SPI transaction */ +#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_SUSPEND */ +/* Description: Suspend SPI transaction */ + +/* Bit 0 : Suspend SPI transaction */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_TASKS_RESUME */ +/* Description: Resume SPI transaction */ + +/* Bit 0 : Resume SPI transaction */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIM_EVENTS_STOPPED */ +/* Description: SPI transaction has stopped */ + +/* Bit 0 : SPI transaction has stopped */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_END */ +/* Description: End of RXD buffer and TXD buffer reached */ + +/* Bit 0 : End of RXD buffer and TXD buffer reached */ +#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_ENDTX */ +/* Description: End of TXD buffer reached */ + +/* Bit 0 : End of TXD buffer reached */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_EVENTS_STARTED */ +/* Description: Transaction started */ + +/* Bit 0 : Transaction started */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 17 : Shortcut between event END and task START */ +#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ +#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ +#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 6 : Write '1' to enable interrupt for event END */ +#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: SPIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 6 : Write '1' to disable interrupt for event END */ +#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ +#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM */ + +/* Bits 3..0 : Enable or disable SPIM */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ + +/* Register: SPIM_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : SPI master data rate */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 13..0 : Maximum number of bytes in receive buffer */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last transaction */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 13..0 : Maximum number of bytes in transmit buffer */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last transaction */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ + +/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: SPIS */ +/* Description: SPI Slave 0 */ + +/* Register: SPIS_TASKS_ACQUIRE */ +/* Description: Acquire SPI semaphore */ + +/* Bit 0 : Acquire SPI semaphore */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_TASKS_RELEASE */ +/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ + +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ + +/* Register: SPIS_EVENTS_END */ +/* Description: Granted transaction completed */ + +/* Bit 0 : Granted transaction completed */ +#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ENDRX */ +/* Description: End of RXD buffer reached */ + +/* Bit 0 : End of RXD buffer reached */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_EVENTS_ACQUIRED */ +/* Description: Semaphore acquired */ + +/* Bit 0 : Semaphore acquired */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ + +/* Register: SPIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 2 : Shortcut between event END and task ACQUIRE */ +#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: SPIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ +#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event END */ +#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ + +/* Register: SPIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ +#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event END */ +#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ +#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ +#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ + +/* Register: SPIS_SEMSTAT */ +/* Description: Semaphore status register */ + +/* Bits 1..0 : Semaphore status */ +#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ + +/* Register: SPIS_STATUS */ +/* Description: Status from last transaction */ + +/* Bit 1 : RX buffer overflow detected, and prevented */ +#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Bit 0 : TX buffer over-read detected, and prevented */ +#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ + +/* Register: SPIS_ENABLE */ +/* Description: Enable SPI slave */ + +/* Bits 3..0 : Enable or disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ + +/* Register: SPIS_PSEL_SCK */ +/* Description: Pin select for SCK */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MISO */ +/* Description: Pin select for MISO signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_MOSI */ +/* Description: Pin select for MOSI signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_PSEL_CSN */ +/* Description: Pin select for CSN signal */ + +/* Bit 31 : Connection */ +#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: SPIS_RXD_PTR */ +/* Description: RXD data pointer */ + +/* Bits 31..0 : RXD data pointer */ +#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 13..0 : Maximum number of bytes in receive buffer */ +#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_RXD_AMOUNT */ +/* Description: Number of bytes received in last granted transaction */ + +/* Bits 13..0 : Number of bytes received in the last granted transaction */ +#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_TXD_PTR */ +/* Description: TXD data pointer */ + +/* Bits 31..0 : TXD data pointer */ +#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 13..0 : Maximum number of bytes in transmit buffer */ +#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIS_TXD_AMOUNT */ +/* Description: Number of bytes transmitted in last granted transaction */ + +/* Bits 13..0 : Number of bytes transmitted in last granted transaction */ +#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: SPIS_CONFIG */ +/* Description: Configuration register */ + +/* Bit 2 : Serial clock (SCK) polarity */ +#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ + +/* Bit 1 : Serial clock (SCK) phase */ +#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ + +/* Bit 0 : Bit order */ +#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ + +/* Register: SPIS_DEF */ +/* Description: Default character. Character clocked out in case of an ignored transaction. */ + +/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ +#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ +#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ + +/* Register: SPIS_ORC */ +/* Description: Over-read character */ + +/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ +#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: TEMP */ +/* Description: Temperature Sensor */ + +/* Register: TEMP_TASKS_START */ +/* Description: Start temperature measurement */ + +/* Bit 0 : Start temperature measurement */ +#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_TASKS_STOP */ +/* Description: Stop temperature measurement */ + +/* Bit 0 : Stop temperature measurement */ +#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TEMP_EVENTS_DATARDY */ +/* Description: Temperature measurement complete, data ready */ + +/* Bit 0 : Temperature measurement complete, data ready */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ + +/* Register: TEMP_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ +#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ + +/* Register: TEMP_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ +#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ +#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ +#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ +#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ + +/* Register: TEMP_TEMP */ +/* Description: Temperature in degC (0.25deg steps) */ + +/* Bits 31..0 : Temperature in degC (0.25deg steps) */ +#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ +#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ + +/* Register: TEMP_A0 */ +/* Description: Slope of 1st piece wise linear function */ + +/* Bits 11..0 : Slope of 1st piece wise linear function */ +#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ +#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ + +/* Register: TEMP_A1 */ +/* Description: Slope of 2nd piece wise linear function */ + +/* Bits 11..0 : Slope of 2nd piece wise linear function */ +#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ +#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ + +/* Register: TEMP_A2 */ +/* Description: Slope of 3rd piece wise linear function */ + +/* Bits 11..0 : Slope of 3rd piece wise linear function */ +#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ +#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ + +/* Register: TEMP_A3 */ +/* Description: Slope of 4th piece wise linear function */ + +/* Bits 11..0 : Slope of 4th piece wise linear function */ +#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ +#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ + +/* Register: TEMP_A4 */ +/* Description: Slope of 5th piece wise linear function */ + +/* Bits 11..0 : Slope of 5th piece wise linear function */ +#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ +#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ + +/* Register: TEMP_A5 */ +/* Description: Slope of 6th piece wise linear function */ + +/* Bits 11..0 : Slope of 6th piece wise linear function */ +#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ +#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ + +/* Register: TEMP_B0 */ +/* Description: y-intercept of 1st piece wise linear function */ + +/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ +#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ + +/* Register: TEMP_B1 */ +/* Description: y-intercept of 2nd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ +#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ + +/* Register: TEMP_B2 */ +/* Description: y-intercept of 3rd piece wise linear function */ + +/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ +#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ + +/* Register: TEMP_B3 */ +/* Description: y-intercept of 4th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ +#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ + +/* Register: TEMP_B4 */ +/* Description: y-intercept of 5th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ +#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ + +/* Register: TEMP_B5 */ +/* Description: y-intercept of 6th piece wise linear function */ + +/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ +#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ + +/* Register: TEMP_T0 */ +/* Description: End point of 1st piece wise linear function */ + +/* Bits 7..0 : End point of 1st piece wise linear function */ +#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ +#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ + +/* Register: TEMP_T1 */ +/* Description: End point of 2nd piece wise linear function */ + +/* Bits 7..0 : End point of 2nd piece wise linear function */ +#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ +#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ + +/* Register: TEMP_T2 */ +/* Description: End point of 3rd piece wise linear function */ + +/* Bits 7..0 : End point of 3rd piece wise linear function */ +#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ +#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ + +/* Register: TEMP_T3 */ +/* Description: End point of 4th piece wise linear function */ + +/* Bits 7..0 : End point of 4th piece wise linear function */ +#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ +#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ + +/* Register: TEMP_T4 */ +/* Description: End point of 5th piece wise linear function */ + +/* Bits 7..0 : End point of 5th piece wise linear function */ +#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ +#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ + + +/* Peripheral: TIMER */ +/* Description: Timer/Counter 0 */ + +/* Register: TIMER_TASKS_START */ +/* Description: Start Timer */ + +/* Bit 0 : Start Timer */ +#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_STOP */ +/* Description: Stop Timer */ + +/* Bit 0 : Stop Timer */ +#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_COUNT */ +/* Description: Increment Timer (Counter mode only) */ + +/* Bit 0 : Increment Timer (Counter mode only) */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CLEAR */ +/* Description: Clear time */ + +/* Bit 0 : Clear time */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_SHUTDOWN */ +/* Description: Deprecated register - Shut down timer */ + +/* Bit 0 : Deprecated field - Shut down timer */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_TASKS_CAPTURE */ +/* Description: Description collection: Capture Timer value to CC[n] register */ + +/* Bit 0 : Capture Timer value to CC[n] register */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ + +/* Register: TIMER_EVENTS_COMPARE */ +/* Description: Description collection: Compare event on CC[n] match */ + +/* Bit 0 : Compare event on CC[n] match */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ + +/* Register: TIMER_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ +#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ +#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ +#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ +#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ +#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ +#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TIMER_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ +#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ +#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ + +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ + +/* Register: TIMER_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ +#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ +#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ + +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ + +/* Register: TIMER_MODE */ +/* Description: Timer mode selection */ + +/* Bits 1..0 : Timer mode */ +#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ +#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ +#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ + +/* Register: TIMER_BITMODE */ +/* Description: Configure the number of bits used by the TIMER */ + +/* Bits 1..0 : Timer bit width */ +#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ +#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ + +/* Register: TIMER_PRESCALER */ +/* Description: Timer prescaler register */ + +/* Bits 3..0 : Prescaler value */ +#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ +#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* Register: TIMER_CC */ +/* Description: Description collection: Capture/Compare register n */ + +/* Bits 31..0 : Capture/Compare value */ +#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ +#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ + + +/* Peripheral: TWI */ +/* Description: I2C compatible Two-Wire Interface */ + +/* Register: TWI_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWI_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_RXDREADY */ +/* Description: TWI RXD byte received */ + +/* Bit 0 : TWI RXD byte received */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_TXDSENT */ +/* Description: TWI TXD byte sent */ + +/* Bit 0 : TWI TXD byte sent */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_BB */ +/* Description: TWI byte boundary, generated before each byte that is sent or received */ + +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ +#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_EVENTS_SUSPENDED */ +/* Description: TWI entered the suspended state */ + +/* Bit 0 : TWI entered the suspended state */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWI_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 1 : Shortcut between event BB and task STOP */ +#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ +#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event BB and task SUSPEND */ +#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ +#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWI_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 14 : Write '1' to enable interrupt for event BB */ +#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ +#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ +#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWI_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 14 : Write '1' to disable interrupt for event BB */ +#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ +#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ +#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ +#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ +#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ +#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ +#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWI_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ +#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ + +/* Register: TWI_ENABLE */ +/* Description: Enable TWI */ + +/* Bits 3..0 : Enable or disable TWI */ +#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ +#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ + +/* Register: TWI_PSEL_SCL */ +/* Description: Pin select for SCL */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_PSEL_SDA */ +/* Description: Pin select for SDA */ + +/* Bit 31 : Connection */ +#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWI_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RXD register */ +#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: TWI_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TXD register */ +#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: TWI_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ + +/* Register: TWI_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIM */ +/* Description: I2C compatible Two-Wire Master Interface with EasyDMA */ + +/* Register: TWIM_TASKS_STARTRX */ +/* Description: Start TWI receive sequence */ + +/* Bit 0 : Start TWI receive sequence */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STARTTX */ +/* Description: Start TWI transmit sequence */ + +/* Bit 0 : Start TWI transmit sequence */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_STOP */ +/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ + +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIM_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_SUSPENDED */ +/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ + +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTRX */ +/* Description: Byte boundary, starting to receive the last byte */ + +/* Bit 0 : Byte boundary, starting to receive the last byte */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_EVENTS_LASTTX */ +/* Description: Byte boundary, starting to transmit the last byte */ + +/* Bit 0 : Byte boundary, starting to transmit the last byte */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ + +/* Register: TWIM_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 12 : Shortcut between event LASTRX and task STOP */ +#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ +#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 9 : Shortcut between event LASTTX and task STOP */ +#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ +#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIM_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 24 : Enable or disable interrupt for event LASTTX */ +#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ + +/* Bit 23 : Enable or disable interrupt for event LASTRX */ +#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ +#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIM_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ +#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ + +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ +#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIM_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ +#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ +#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ + +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ +#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ +#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIM_ERRORSRC */ +/* Description: Error source */ + +/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ +#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 1 : NACK received after sending the address (write '1' to clear) */ +#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + +/* Register: TWIM_ENABLE */ +/* Description: Enable TWIM */ + +/* Bits 3..0 : Enable or disable TWIM */ +#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ + +/* Register: TWIM_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIM_FREQUENCY */ +/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : TWI master clock frequency */ +#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ +#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ + +/* Register: TWIM_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 13..0 : Maximum number of bytes in receive buffer */ +#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIM_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 13..0 : Maximum number of bytes in transmit buffer */ +#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIM_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIM_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 2..0 : List type */ +#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIM_ADDRESS */ +/* Description: Address used in the TWI transfer */ + +/* Bits 6..0 : Address used in the TWI transfer */ +#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + + +/* Peripheral: TWIS */ +/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA */ + +/* Register: TWIS_TASKS_STOP */ +/* Description: Stop TWI transaction */ + +/* Bit 0 : Stop TWI transaction */ +#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_SUSPEND */ +/* Description: Suspend TWI transaction */ + +/* Bit 0 : Suspend TWI transaction */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_RESUME */ +/* Description: Resume TWI transaction */ + +/* Bit 0 : Resume TWI transaction */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARERX */ +/* Description: Prepare the TWI slave to respond to a write command */ + +/* Bit 0 : Prepare the TWI slave to respond to a write command */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_TASKS_PREPARETX */ +/* Description: Prepare the TWI slave to respond to a read command */ + +/* Bit 0 : Prepare the TWI slave to respond to a read command */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ + +/* Register: TWIS_EVENTS_STOPPED */ +/* Description: TWI stopped */ + +/* Bit 0 : TWI stopped */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_ERROR */ +/* Description: TWI error */ + +/* Bit 0 : TWI error */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_RXSTARTED */ +/* Description: Receive sequence started */ + +/* Bit 0 : Receive sequence started */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_TXSTARTED */ +/* Description: Transmit sequence started */ + +/* Bit 0 : Transmit sequence started */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_WRITE */ +/* Description: Write command received */ + +/* Bit 0 : Write command received */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_EVENTS_READ */ +/* Description: Read command received */ + +/* Bit 0 : Read command received */ +#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ + +/* Register: TWIS_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 14 : Shortcut between event READ and task SUSPEND */ +#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ +#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: TWIS_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 26 : Enable or disable interrupt for event READ */ +#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ + +/* Bit 25 : Enable or disable interrupt for event WRITE */ +#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event STOPPED */ +#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ + +/* Register: TWIS_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 26 : Write '1' to enable interrupt for event READ */ +#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ + +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ +#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Register: TWIS_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 26 : Write '1' to disable interrupt for event READ */ +#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ +#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ +#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ + +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ +#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ +#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Register: TWIS_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : TX buffer over-read detected, and prevented */ +#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ + +/* Bit 2 : NACK sent after receiving a data byte */ +#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ + +/* Bit 0 : RX buffer overflow detected, and prevented */ +#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ + +/* Register: TWIS_MATCH */ +/* Description: Status register indicating which address had a match */ + +/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ +#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ + +/* Register: TWIS_ENABLE */ +/* Description: Enable TWIS */ + +/* Bits 3..0 : Enable or disable TWIS */ +#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ + +/* Register: TWIS_PSEL_SCL */ +/* Description: Pin select for SCL signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_PSEL_SDA */ +/* Description: Pin select for SDA signal */ + +/* Bit 31 : Connection */ +#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: TWIS_RXD_PTR */ +/* Description: RXD Data pointer */ + +/* Bits 31..0 : RXD Data pointer */ +#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_RXD_MAXCNT */ +/* Description: Maximum number of bytes in RXD buffer */ + +/* Bits 13..0 : Maximum number of bytes in RXD buffer */ +#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last RXD transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last RXD transaction */ +#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_TXD_PTR */ +/* Description: TXD Data pointer */ + +/* Bits 31..0 : TXD Data pointer */ +#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: TWIS_TXD_MAXCNT */ +/* Description: Maximum number of bytes in TXD buffer */ + +/* Bits 13..0 : Maximum number of bytes in TXD buffer */ +#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: TWIS_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last TXD transaction */ + +/* Bits 13..0 : Number of bytes transferred in the last TXD transaction */ +#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0x3FFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + +/* Register: TWIS_ADDRESS */ +/* Description: Description collection: TWI slave address n */ + +/* Bits 6..0 : TWI slave address */ +#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ +#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ + +/* Register: TWIS_CONFIG */ +/* Description: Configuration register for the address match mechanism */ + +/* Bit 1 : Enable or disable address matching on ADDRESS[1] */ +#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ + +/* Bit 0 : Enable or disable address matching on ADDRESS[0] */ +#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ + +/* Register: TWIS_ORC */ +/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ + +/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ +#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + + +/* Peripheral: UART */ +/* Description: Universal Asynchronous Receiver/Transmitter */ + +/* Register: UART_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_TASKS_SUSPEND */ +/* Description: Suspend UART */ + +/* Bit 0 : Suspend UART */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ + +/* Register: UART_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXDRDY */ +/* Description: Data received in RXD */ + +/* Bit 0 : Data received in RXD */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UART_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UART_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ +#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ +#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event CTS and task STARTRX */ +#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ +#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UART_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UART_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UART_ERRORSRC */ +/* Description: Error source */ + +/* Bit 3 : Break condition */ +#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UART_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UART */ +#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ +#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ + +/* Register: UART_PSEL_RTS */ +/* Description: Pin select for RTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_TXD */ +/* Description: Pin select for TXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_CTS */ +/* Description: Pin select for CTS */ + +/* Bit 31 : Connection */ +#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_PSEL_RXD */ +/* Description: Pin select for RXD */ + +/* Bit 31 : Connection */ +#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UART_RXD */ +/* Description: RXD register */ + +/* Bits 7..0 : RX data received in previous transfers, double buffered */ +#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ +#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ + +/* Register: UART_TXD */ +/* Description: TXD register */ + +/* Bits 7..0 : TX data to be transferred */ +#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ +#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ + +/* Register: UART_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ +#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ +#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ +#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ +#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UART_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UARTE */ +/* Description: UART with EasyDMA */ + +/* Register: UARTE_TASKS_STARTRX */ +/* Description: Start UART receiver */ + +/* Bit 0 : Start UART receiver */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPRX */ +/* Description: Stop UART receiver */ + +/* Bit 0 : Stop UART receiver */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STARTTX */ +/* Description: Start UART transmitter */ + +/* Bit 0 : Start UART transmitter */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_STOPTX */ +/* Description: Stop UART transmitter */ + +/* Bit 0 : Stop UART transmitter */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_TASKS_FLUSHRX */ +/* Description: Flush RX FIFO into RX buffer */ + +/* Bit 0 : Flush RX FIFO into RX buffer */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ + +/* Register: UARTE_EVENTS_CTS */ +/* Description: CTS is activated (set low). Clear To Send. */ + +/* Bit 0 : CTS is activated (set low). Clear To Send. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_NCTS */ +/* Description: CTS is deactivated (set high). Not Clear To Send. */ + +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXDRDY */ +/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ + +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDRX */ +/* Description: Receive buffer is filled up */ + +/* Bit 0 : Receive buffer is filled up */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXDRDY */ +/* Description: Data sent from TXD */ + +/* Bit 0 : Data sent from TXD */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ENDTX */ +/* Description: Last TX byte transmitted */ + +/* Bit 0 : Last TX byte transmitted */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_ERROR */ +/* Description: Error detected */ + +/* Bit 0 : Error detected */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXTO */ +/* Description: Receiver timeout */ + +/* Bit 0 : Receiver timeout */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_RXSTARTED */ +/* Description: UART receiver has started */ + +/* Bit 0 : UART receiver has started */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTARTED */ +/* Description: UART transmitter has started */ + +/* Bit 0 : UART transmitter has started */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_EVENTS_TXSTOPPED */ +/* Description: Transmitter stopped */ + +/* Bit 0 : Transmitter stopped */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: UARTE_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ +#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ +#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: UARTE_INTEN */ +/* Description: Enable or disable interrupt */ + +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ +#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ + +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ + +/* Bit 17 : Enable or disable interrupt for event RXTO */ +#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ + +/* Bit 9 : Enable or disable interrupt for event ERROR */ +#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ + +/* Bit 8 : Enable or disable interrupt for event ENDTX */ +#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ + +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 4 : Enable or disable interrupt for event ENDRX */ +#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ + +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + +/* Bit 1 : Enable or disable interrupt for event NCTS */ +#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ + +/* Bit 0 : Enable or disable interrupt for event CTS */ +#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ + +/* Register: UARTE_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ +#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ + +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ + +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ + +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ + +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ + +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event CTS */ +#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ + +/* Register: UARTE_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ +#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ + +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ +#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ + +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ +#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ + +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ + +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ +#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event CTS */ +#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ +#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ +#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ + +/* Register: UARTE_ERRORSRC */ +/* Description: Error source Note : this register is read / write one to clear. */ + +/* Bit 3 : Break condition */ +#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ + +/* Bit 2 : Framing error occurred */ +#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ + +/* Bit 1 : Parity error */ +#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ + +/* Bit 0 : Overrun error */ +#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ + +/* Register: UARTE_ENABLE */ +/* Description: Enable UART */ + +/* Bits 3..0 : Enable or disable UARTE */ +#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ + +/* Register: UARTE_PSEL_RTS */ +/* Description: Pin select for RTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_TXD */ +/* Description: Pin select for TXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_CTS */ +/* Description: Pin select for CTS signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_PSEL_RXD */ +/* Description: Pin select for RXD signal */ + +/* Bit 31 : Connection */ +#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UARTE_BAUDRATE */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ + +/* Bits 31..0 : Baud rate */ +#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ + +/* Register: UARTE_RXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_RXD_MAXCNT */ +/* Description: Maximum number of bytes in receive buffer */ + +/* Bits 9..0 : Maximum number of bytes in receive buffer */ +#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_RXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_TXD_PTR */ +/* Description: Data pointer */ + +/* Bits 31..0 : Data pointer */ +#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: UARTE_TXD_MAXCNT */ +/* Description: Maximum number of bytes in transmit buffer */ + +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ +#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: UARTE_TXD_AMOUNT */ +/* Description: Number of bytes transferred in the last transaction */ + +/* Bits 9..0 : Number of bytes transferred in the last transaction */ +#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: UARTE_CONFIG */ +/* Description: Configuration of parity and hardware flow control */ + +/* Bit 4 : Stop bits */ +#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + +/* Bits 3..1 : Parity */ +#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ +#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ +#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ +#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */ + +/* Bit 0 : Hardware flow control */ +#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ +#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ +#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ + + +/* Peripheral: UICR */ +/* Description: User information configuration registers */ + +/* Register: UICR_NRFFW */ +/* Description: Description collection: Reserved for Nordic firmware design */ + +/* Bits 31..0 : Reserved for Nordic firmware design */ +#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ +#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ + +/* Register: UICR_NRFHW */ +/* Description: Description collection: Reserved for Nordic hardware design */ + +/* Bits 31..0 : Reserved for Nordic hardware design */ +#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ +#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ + +/* Register: UICR_CUSTOMER */ +/* Description: Description collection: Reserved for customer */ + +/* Bits 31..0 : Reserved for customer */ +#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ +#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ + +/* Register: UICR_PSELRESET */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ + +/* Bit 31 : Connection */ +#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ +#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ +#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: UICR_APPROTECT */ +/* Description: Access port protection */ + +/* Bits 7..0 : Enable or disable access port protection. */ +#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ +#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ +#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ + + +/* Peripheral: WDT */ +/* Description: Watchdog Timer */ + +/* Register: WDT_TASKS_START */ +/* Description: Start the watchdog */ + +/* Bit 0 : Start the watchdog */ +#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: WDT_EVENTS_TIMEOUT */ +/* Description: Watchdog timeout */ + +/* Bit 0 : Watchdog timeout */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ + +/* Register: WDT_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ +#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ + +/* Register: WDT_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ +#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ + +/* Register: WDT_RUNSTATUS */ +/* Description: Run status */ + +/* Bit 0 : Indicates whether or not the watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ +#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ + +/* Register: WDT_REQSTATUS */ +/* Description: Request status */ + +/* Bit 7 : Request status for RR[7] register */ +#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ + +/* Bit 6 : Request status for RR[6] register */ +#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ + +/* Bit 5 : Request status for RR[5] register */ +#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ + +/* Bit 4 : Request status for RR[4] register */ +#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ + +/* Bit 3 : Request status for RR[3] register */ +#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ + +/* Bit 2 : Request status for RR[2] register */ +#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ + +/* Bit 1 : Request status for RR[1] register */ +#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ + +/* Bit 0 : Request status for RR[0] register */ +#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ + +/* Register: WDT_CRV */ +/* Description: Counter reload value */ + +/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ +#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ +#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ + +/* Register: WDT_RREN */ +/* Description: Enable register for reload request registers */ + +/* Bit 7 : Enable or disable RR[7] register */ +#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ +#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ +#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ + +/* Bit 6 : Enable or disable RR[6] register */ +#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ +#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ +#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ + +/* Bit 5 : Enable or disable RR[5] register */ +#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ +#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ +#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ + +/* Bit 4 : Enable or disable RR[4] register */ +#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ +#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ +#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ + +/* Bit 3 : Enable or disable RR[3] register */ +#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ +#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ +#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ + +/* Bit 2 : Enable or disable RR[2] register */ +#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ +#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ +#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ + +/* Bit 1 : Enable or disable RR[1] register */ +#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ +#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ +#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ + +/* Bit 0 : Enable or disable RR[0] register */ +#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ +#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ +#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ + +/* Register: WDT_CONFIG */ +/* Description: Configuration register */ + +/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ +#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ + +/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ + +/* Register: WDT_RR */ +/* Description: Description collection: Reload request n */ + +/* Bits 31..0 : Reload request register */ +#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ +#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ +#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ + + +/*lint --flb "Leave library region" */ +#endif diff --git a/mdk/nrf52811_peripherals.h b/mdk/nrf52811_peripherals.h new file mode 100644 index 000000000..b14e6486d --- /dev/null +++ b/mdk/nrf52811_peripherals.h @@ -0,0 +1,231 @@ +/* + +Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef _NRF52811_PERIPHERALS_H +#define _NRF52811_PERIPHERALS_H + + +/* Clock Peripheral */ +#define CLOCK_PRESENT +#define CLOCK_COUNT 1 + +/* Power Peripheral */ +#define POWER_PRESENT +#define POWER_COUNT 1 + +#define POWER_FEATURE_RAM_REGISTERS_PRESENT +#define POWER_FEATURE_RAM_REGISTERS_COUNT 3 + +/* Systick timer */ +#define SYSTICK_PRESENT +#define SYSTICK_COUNT 1 + +/* Software Interrupts */ +#define SWI_PRESENT +#define SWI_COUNT 6 + +/* GPIO */ +#define GPIO_PRESENT +#define GPIO_COUNT 1 + +#define P0_PIN_NUM 32 + +/* MPU and BPROT */ +#define BPROT_PRESENT + +#define BPROT_REGIONS_SIZE 4096 +#define BPROT_REGIONS_NUM 48 + +/* Radio */ +#define RADIO_PRESENT +#define RADIO_COUNT 1 + +#define RADIO_EASYDMA_MAXCNT_SIZE 8 + +/* Accelerated Address Resolver */ +#define AAR_PRESENT +#define AAR_COUNT 1 + +#define AAR_MAX_IRK_NUM 16 + +/* AES Electronic CodeBook mode encryption */ +#define ECB_PRESENT +#define ECB_COUNT 1 + +/* AES CCM mode encryption */ +#define CCM_PRESENT +#define CCM_COUNT 1 + +/* Peripheral to Peripheral Interconnect */ +#define PPI_PRESENT +#define PPI_COUNT 1 + +#define PPI_CH_NUM 20 +#define PPI_FIXED_CH_NUM 12 +#define PPI_GROUP_NUM 6 +#define PPI_FEATURE_FORKS_PRESENT + +/* Event Generator Unit */ +#define EGU_PRESENT +#define EGU_COUNT 2 + +#define EGU0_CH_NUM 16 +#define EGU1_CH_NUM 16 + +/* Timer/Counter */ +#define TIMER_PRESENT +#define TIMER_COUNT 3 + +#define TIMER0_MAX_SIZE 32 +#define TIMER1_MAX_SIZE 32 +#define TIMER2_MAX_SIZE 32 + +#define TIMER0_CC_NUM 4 +#define TIMER1_CC_NUM 4 +#define TIMER2_CC_NUM 4 + +/* Real Time Counter */ +#define RTC_PRESENT +#define RTC_COUNT 2 + +#define RTC0_CC_NUM 3 +#define RTC1_CC_NUM 4 + +/* RNG */ +#define RNG_PRESENT +#define RNG_COUNT 1 + +/* Watchdog Timer */ +#define WDT_PRESENT +#define WDT_COUNT 1 + +/* Temperature Sensor */ +#define TEMP_PRESENT +#define TEMP_COUNT 1 + +/* Serial Peripheral Interface Master */ +#define SPI_PRESENT +#define SPI_COUNT 2 + +/* Serial Peripheral Interface Master with DMA */ +#define SPIM_PRESENT +#define SPIM_COUNT 2 + +#define SPIM0_MAX_DATARATE 8 +#define SPIM1_MAX_DATARATE 8 + +#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 +#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 + +#define SPIM0_FEATURE_DCX_PRESENT 0 +#define SPIM1_FEATURE_DCX_PRESENT 0 + +#define SPIM0_FEATURE_RXDELAY_PRESENT 0 +#define SPIM1_FEATURE_RXDELAY_PRESENT 0 + +#define SPIM0_EASYDMA_MAXCNT_SIZE 14 +#define SPIM1_EASYDMA_MAXCNT_SIZE 14 + +/* Serial Peripheral Interface Slave with DMA*/ +#define SPIS_PRESENT +#define SPIS_COUNT 2 + +#define SPIS0_EASYDMA_MAXCNT_SIZE 14 +#define SPIS1_EASYDMA_MAXCNT_SIZE 14 + +/* Two Wire Interface Master */ +#define TWI_PRESENT +#define TWI_COUNT 1 + +/* Two Wire Interface Master with DMA */ +#define TWIM_PRESENT +#define TWIM_COUNT 1 + +#define TWIM0_EASYDMA_MAXCNT_SIZE 14 + +/* Two Wire Interface Slave with DMA */ +#define TWIS_PRESENT +#define TWIS_COUNT 1 + +#define TWIS0_EASYDMA_MAXCNT_SIZE 14 + +/* Universal Asynchronous Receiver-Transmitter */ +#define UART_PRESENT +#define UART_COUNT 1 + +/* Universal Asynchronous Receiver-Transmitter with DMA */ +#define UARTE_PRESENT +#define UARTE_COUNT 1 + +#define UARTE0_EASYDMA_MAXCNT_SIZE 14 + +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + +/* Successive Approximation Analog to Digital Converter */ +#define SAADC_PRESENT +#define SAADC_COUNT 1 + +#define SAADC_EASYDMA_MAXCNT_SIZE 15 + +#define SAADC_CH_NUM 8 + +/* GPIO Tasks and Events */ +#define GPIOTE_PRESENT +#define GPIOTE_COUNT 1 + +#define GPIOTE_CH_NUM 8 + +#define GPIOTE_FEATURE_SET_PRESENT +#define GPIOTE_FEATURE_CLR_PRESENT + +/* Comparator */ +#define COMP_PRESENT +#define COMP_COUNT 1 + +/* Pulse Width Modulator */ +#define PWM_PRESENT +#define PWM_COUNT 1 + +#define PWM0_CH_NUM 4 + +#define PWM0_EASYDMA_MAXCNT_SIZE 15 + +/* Pulse Density Modulator */ +#define PDM_PRESENT +#define PDM_COUNT 1 + +#define PDM_EASYDMA_MAXCNT_SIZE 15 + + +#endif // _NRF52811_PERIPHERALS_H diff --git a/mdk/nrf52811_xxaa.ld b/mdk/nrf52811_xxaa.ld new file mode 100644 index 000000000..b8ef436ee --- /dev/null +++ b/mdk/nrf52811_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index e7172566d..0fefdd405 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -30,10 +30,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 03. December 2018 - * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:25 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40 * from File 'nrf52840.svd', - * last modified on Monday, 03.12.2018 10:18:21 + * last modified on Thursday, 17.01.2019 16:25:35 */ @@ -202,8 +202,7 @@ typedef struct { __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ - __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ -} FICR_INFO_Type; /*!< Size = 32 (0x20) */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ /** @@ -268,10 +267,9 @@ typedef struct { * @brief POWER_RAM [RAM] (Unspecified) */ typedef struct { - __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ - __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set - register */ - __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear register */ __IM uint32_t RESERVED; } POWER_RAM_Type; /*!< Size = 16 (0x10) */ @@ -391,7 +389,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -401,7 +400,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ /** @@ -460,7 +460,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ /** @@ -470,7 +471,8 @@ typedef struct { __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ /** @@ -500,13 +502,13 @@ typedef struct { /** - * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) */ typedef struct { - __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal - or above CH[n].LIMIT.HIGH */ - __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal - or below CH[n].LIMIT.LOW */ + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or + below CH[n].LIMIT.LOW */ } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ @@ -514,13 +516,13 @@ typedef struct { * @brief SAADC_CH [CH] (Unspecified) */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection for CH[n] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for CH[n] */ - __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event monitoring of a channel */ } SAADC_CH_Type; /*!< Size = 16 (0x10) */ @@ -551,15 +553,14 @@ typedef struct { * @brief PWM_SEQ [SEQ] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in - RAM of this sequence */ - __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty - cycles) in this sequence */ - __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional - PWM periods between samples loaded into - compare register */ - __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the - sequence */ + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ __IM uint32_t RESERVED[4]; } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ @@ -568,8 +569,8 @@ typedef struct { * @brief PWM_PSEL [PSEL] (Unspecified) */ typedef struct { - __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select - for PWM channel n */ + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ @@ -597,15 +598,15 @@ typedef struct { * @brief ACL_ACL [ACL] (Unspecified) */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned start address of region n to protect */ - __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ - __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for - region n as defined by start address ACL[n].ADDR + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ - __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ + __IM uint32_t RESERVED; } ACL_ACL_Type; /*!< Size = 16 (0x10) */ @@ -613,10 +614,8 @@ typedef struct { * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group - n */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group - n */ + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ @@ -624,8 +623,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -633,28 +632,28 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ /** - * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region - n detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region - n detected */ + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n + detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n + detected */ } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ /** - * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral region n detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral region n detected */ } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ @@ -663,11 +662,11 @@ typedef struct { * @brief MWU_PERREGION [PERREGION] (Unspecified) */ typedef struct { - __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ - __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ @@ -678,10 +677,9 @@ typedef struct { * @brief MWU_REGION [REGION] (Unspecified) */ typedef struct { - __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region - n */ - __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ __IM uint32_t RESERVED[2]; } MWU_REGION_Type; /*!< Size = 16 (0x10) */ @@ -690,10 +688,9 @@ typedef struct { * @brief MWU_PREGION [PREGION] (Unspecified) */ typedef struct { - __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ - __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ - __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region - n */ + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ __IM uint32_t RESERVED; } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ @@ -755,13 +752,13 @@ typedef struct { * @brief USBD_HALTED [HALTED] (Unspecified) */ typedef struct { - __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted - status. Can be used as is as response to - a GetStatus() request to endpoint. */ + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ __IM uint32_t RESERVED; - __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted - status. Can be used as is as response to - a GetStatus() request to endpoint. */ + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ @@ -769,7 +766,7 @@ typedef struct { * @brief USBD_SIZE [SIZE] (Unspecified) */ typedef struct { - __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received last in the data stage of this OUT endpoint */ __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT data endpoint */ @@ -780,10 +777,10 @@ typedef struct { * @brief USBD_EPIN [EPIN] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred in the last transaction */ __IM uint32_t RESERVED[2]; } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ @@ -803,10 +800,10 @@ typedef struct { * @brief USBD_EPOUT [EPOUT] (Unspecified) */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred in the last transaction */ __IM uint32_t RESERVED[2]; } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ @@ -893,21 +890,20 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ __IM uint32_t RESERVED1[18]; - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ __IM uint32_t RESERVED2[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word - n */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ __IM uint32_t RESERVED3[21]; - __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ - __IM uint32_t RESERVED4[140]; - __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature n */ __IM uint32_t RESERVED5[42]; - __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization coefficients */ __IM uint32_t RESERVED6[2]; __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ @@ -927,19 +923,15 @@ typedef struct { /*!< (@ 0x10000000) FICR Structu */ typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ - __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ - __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ - __IM uint32_t RESERVED; - __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ - __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic - firmware design */ - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic - hardware design */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ __IM uint32_t RESERVED1[64]; - __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET - function */ + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -1056,6 +1048,36 @@ typedef struct { /*!< (@ 0x40000000) POWER Struct +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + /* =========================================================================================================================== */ /* ================ RADIO ================ */ /* =========================================================================================================================== */ @@ -1115,10 +1137,10 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ __IM uint32_t RESERVED3[3]; __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and - BleIeee802154_250Kbit modes when last bit - is sent on air. */ + Ieee802154_250Kbit modes when last bit is + sent on air. */ __IM uint32_t RESERVED4[36]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1154,9 +1176,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IM uint32_t RESERVED11[2]; __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ __IM uint32_t RESERVED12[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base - segment n */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix n */ __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ @@ -1201,7 +1223,7 @@ typedef struct { /*!< (@ 0x40002000) UART0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ __IM uint32_t RESERVED5[46]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED6[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1257,7 +1279,7 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IM uint32_t RESERVED6; __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ __IM uint32_t RESERVED7[41]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1340,7 +1362,7 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct __IM uint32_t RESERVED6[10]; __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ __IM uint32_t RESERVED7[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1394,7 +1416,7 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct __IM uint32_t RESERVED3[5]; __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED5[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1408,14 +1430,12 @@ typedef struct { /*!< (@ 0x40003000) SPIS0 Struct __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED10[7]; __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ - __IM uint32_t RESERVED11; __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ - __IM uint32_t RESERVED12; __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED13; + __IM uint32_t RESERVED11; __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case of an ignored transaction. */ - __IM uint32_t RESERVED14[24]; + __IM uint32_t RESERVED12[24]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ @@ -1452,7 +1472,7 @@ typedef struct { /*!< (@ 0x40003000) TWI0 Structu __IM uint32_t RESERVED7[3]; __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ __IM uint32_t RESERVED8[45]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED9[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1508,7 +1528,7 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last byte */ __IM uint32_t RESERVED7[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1560,7 +1580,7 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ __IM uint32_t RESERVED7[37]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED8[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1575,15 +1595,13 @@ typedef struct { /*!< (@ 0x40003000) TWIS0 Struct __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ __IM uint32_t RESERVED12[9]; __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED13; __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[14]; - __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address - n */ - __IM uint32_t RESERVED15; + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match mechanism */ - __IM uint32_t RESERVED16[10]; + __IM uint32_t RESERVED15[10]; __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case of an over-read of the transmit buffer. */ } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ @@ -1643,7 +1661,7 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ __IM uint32_t RESERVED6[43]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED7[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1690,19 +1708,19 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu */ typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is configured in CONFIG[n].POLARITY. */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it high. */ + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ __IM uint32_t RESERVED1[4]; - __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to - pin specified in CONFIG[n].PSEL. Action - on pin is to set it low. */ + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ __IM uint32_t RESERVED2[32]; - __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from pin specified in CONFIG[n].PSEL */ __IM uint32_t RESERVED3[23]; __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins @@ -1711,9 +1729,8 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED5[129]; - __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for - OUT[n], SET[n] and CLR[n] tasks and IN[n] - event */ + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n] and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1743,7 +1760,7 @@ typedef struct { /*!< (@ 0x40007000) SAADC Struct __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ - __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ __IM uint32_t RESERVED1[106]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1783,13 +1800,13 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value - to CC[n] register */ + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ __IM uint32_t RESERVED1[58]; - __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[42]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1799,7 +1816,7 @@ typedef struct { /*!< (@ 0x40008000) TIMER0 Struc __IM uint32_t RESERVED5; __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register n */ } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ @@ -1823,7 +1840,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] match */ __IM uint32_t RESERVED2[109]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -1837,7 +1854,7 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu t be written when RTC is stopped */ __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1901,7 +1918,7 @@ typedef struct { /*!< (@ 0x4000D000) RNG Structur __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number written to the VALUE register */ __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -1994,7 +2011,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2039,7 +2056,7 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ @@ -2067,7 +2084,7 @@ typedef struct { /*!< (@ 0x40012000) QDEC Structu __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ __IM uint32_t RESERVED1[59]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2112,7 +2129,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2151,7 +2168,7 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED2[64]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ @@ -2180,10 +2197,10 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ - __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ __IM uint32_t RESERVED[48]; - __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ __IM uint32_t RESERVED1[112]; @@ -2223,9 +2240,9 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ - __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM - value on all enabled channels from sequence - n, and starts playing that sequence at the + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on @@ -2235,16 +2252,16 @@ typedef struct { /*!< (@ 0x4001C000) PWM0 Structu __IM uint32_t RESERVED1[60]; __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses are no longer generated */ - __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started on sequence n */ - __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of - every sequence n, when last value from RAM - has been applied to wave counter */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount of times defined in LOOP.CNT */ __IM uint32_t RESERVED2[56]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2369,7 +2386,7 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu */ typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ __IM uint32_t RESERVED[308]; __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ @@ -2377,7 +2394,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur __IM uint32_t RESERVED1; __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ __IM uint32_t RESERVED2[148]; - __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ __IM uint32_t RESERVED3[62]; __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ @@ -2395,17 +2412,17 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur typedef struct { /*!< (@ 0x40020000) MWU Structure */ __IM uint32_t RESERVED[64]; - __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ __IM uint32_t RESERVED1[16]; - __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ __IM uint32_t RESERVED2[100]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ - __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ - __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ __IM uint32_t RESERVED4[53]; __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ __IM uint32_t RESERVED5[64]; @@ -2433,7 +2450,7 @@ typedef struct { /*!< (@ 0x40025000) I2S Structur __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. - Triggering this task will cause the {event:STOPPED} + Triggering this task will cause the STOPPED event to be generated. */ __IM uint32_t RESERVED[63]; __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal @@ -2493,14 +2510,14 @@ typedef struct { /*!< (@ 0x40026000) FPU Structur typedef struct { /*!< (@ 0x40027000) USBD Structure */ __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ - __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ @@ -2522,16 +2539,16 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ - __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] - buffer has been consumed. The RAM buffer - can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The RAM buffer can be + accessed safely by software. */ __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place on the control endpoint */ __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ - __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] - buffer has been consumed. The RAM buffer - can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The RAM buffer can be + accessed safely by software. */ __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition @@ -2544,7 +2561,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ __IM uint32_t RESERVED2[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED3[63]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ @@ -2651,36 +2668,6 @@ typedef struct { /*!< (@ 0x40029000) QSPI Structu -/* =========================================================================================================================== */ -/* ================ P0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief GPIO Port 1 (P0) - */ - -typedef struct { /*!< (@ 0x50000000) P0 Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ - __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that - have met the criteria set in the PIN_CNF[n].SENSE - registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour - and LDETECT mode */ - __IM uint32_t RESERVED1[118]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO - pins */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - - /* =========================================================================================================================== */ /* ================ CC_HOST_RGF ================ */ /* =========================================================================================================================== */ @@ -2750,6 +2737,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_UICR_BASE 0x10001000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL #define NRF_RADIO_BASE 0x40001000UL #define NRF_UART0_BASE 0x40002000UL #define NRF_UARTE0_BASE 0x40002000UL @@ -2813,12 +2802,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_USBD_BASE 0x40027000UL #define NRF_UARTE1_BASE 0x40028000UL #define NRF_QSPI_BASE 0x40029000UL -#define NRF_PWM3_BASE 0x4002D000UL -#define NRF_SPIM3_BASE 0x4002F000UL -#define NRF_P0_BASE 0x50000000UL -#define NRF_P1_BASE 0x50000300UL #define NRF_CC_HOST_RGF_BASE 0x5002A000UL #define NRF_CRYPTOCELL_BASE 0x5002A000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL /** @} */ /* End of group Device_Peripheral_peripheralAddr */ @@ -2836,6 +2823,8 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) @@ -2899,12 +2888,10 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) -#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) -#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) -#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) -#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) /** @} */ /* End of group Device_Peripheral_declaration */ diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index 1ff982163..74bc36206 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -104,7 +104,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 DEVICEID[%s] - Description collection[n]: Device identifier + Description collection: Device identifier 0x060 read-only 0xFFFFFFFF @@ -121,7 +121,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 ER[%s] - Description collection[n]: Encryption root, word n + Description collection: Encryption root, word n 0x080 read-only 0xFFFFFFFF @@ -138,7 +138,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x4 0x4 IR[%s] - Description collection[n]: Identity Root, word n + Description collection: Identity Root, word n 0x090 read-only 0xFFFFFFFF @@ -182,7 +182,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 DEVICEADDR[%s] - Description collection[n]: Device address n + Description collection: Device address n 0x0A4 read-only 0xFFFFFFFF @@ -199,6 +199,7 @@ POSSIBILITY OF SUCH DAMAGE.\n INFO Device info FICR_INFO + read-only 0x100 PART @@ -405,20 +406,12 @@ POSSIBILITY OF SUCH DAMAGE.\n - - 0x3 - 0x4 - UNUSED8[%s] - Unspecified - 0x014 - read-write - 0x3 0x4 PRODTEST[%s] - Description collection[n]: Production test signature n + Description collection: Production test signature n 0x350 read-only 0xFFFFFFFF @@ -447,6 +440,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP + read-only 0x404 A0 @@ -708,6 +702,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NFC Unspecified FICR_NFC + read-write 0x450 TAGHEADER0 @@ -846,6 +841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TRNG90B NIST800-90B RNG calibration data FICR_TRNG90B + read-write 0xC00 BYTES @@ -982,35 +978,11 @@ POSSIBILITY OF SUCH DAMAGE.\n UICR 0x20 - - UNUSED0 - Unspecified - 0x000 - read-write - - - UNUSED1 - Unspecified - 0x004 - read-write - - - UNUSED2 - Unspecified - 0x008 - read-write - - - UNUSED3 - Unspecified - 0x010 - read-write - 0xF 0x4 NRFFW[%s] - Description collection[n]: Reserved for Nordic firmware design + Description collection: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF @@ -1027,7 +999,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0xC 0x4 NRFHW[%s] - Description collection[n]: Reserved for Nordic hardware design + Description collection: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF @@ -1044,7 +1016,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x20 0x4 CUSTOMER[%s] - Description collection[n]: Reserved for customer + Description collection: Reserved for customer 0x080 read-write 0xFFFFFFFF @@ -1061,14 +1033,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x2 0x4 PSELRESET[%s] - Description collection[n]: Mapping of the nRESET function + Description collection: Mapping of the nRESET function (see POWER chapter for details) 0x200 read-write 0xFFFFFFFF PIN - Pin number of PORT onto which nRESET is exposed + GPIO pin number onto which nRESET is exposed 0 4 @@ -1275,8 +1247,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTART + Start HFXO crystal oscillator 0 0 + + + Trigger + Trigger task + 1 + + @@ -1288,8 +1268,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTOP + Stop HFXO crystal oscillator 0 0 + + + Trigger + Trigger task + 1 + + @@ -1301,8 +1289,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LFCLKSTART + Start LFCLK 0 0 + + + Trigger + Trigger task + 1 + + @@ -1314,8 +1310,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LFCLKSTOP + Stop LFCLK 0 0 + + + Trigger + Trigger task + 1 + + @@ -1327,8 +1331,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CAL + Start calibration of LFRC 0 0 + + + Trigger + Trigger task + 1 + + @@ -1340,8 +1352,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CTSTART + Start calibration timer 0 0 + + + Trigger + Trigger task + 1 + + @@ -1353,8 +1373,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CTSTOP + Stop calibration timer 0 0 + + + Trigger + Trigger task + 1 + + @@ -1366,8 +1394,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_HFCLKSTARTED + HFXO crystal oscillator started 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1379,8 +1420,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_LFCLKSTARTED + LFCLK started 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1392,8 +1446,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_DONE + Calibration of LFRC completed 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1405,8 +1472,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_CTTO + Calibration timer timeout 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1418,8 +1498,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_CTSTARTED + Calibration timer has been started and is ready to process new tasks 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -1431,175 +1524,18 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_CTSTOPPED + Calibration timer has been stopped and is ready to process new tasks 0 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - HFCLKSTARTED - Write '1' to enable interrupt for HFCLKSTARTED event - 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LFCLKSTARTED - Write '1' to enable interrupt for LFCLKSTARTED event - 1 - 1 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - DONE - Write '1' to enable interrupt for DONE event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTTO - Write '1' to enable interrupt for CTTO event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTSTARTED - Write '1' to enable interrupt for CTSTARTED event - 10 - 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CTSTOPPED - Write '1' to enable interrupt for CTSTOPPED event - 11 - 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 @@ -1607,14 +1543,184 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + INTENSET + Enable interrupt + 0x304 read-write HFCLKSTARTED - Write '1' to disable interrupt for HFCLKSTARTED event + Write '1' to enable interrupt for event HFCLKSTARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LFCLKSTARTED + Write '1' to enable interrupt for event LFCLKSTARTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + DONE + Write '1' to enable interrupt for event DONE + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTTO + Write '1' to enable interrupt for event CTTO + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTARTED + Write '1' to enable interrupt for event CTSTARTED + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CTSTOPPED + Write '1' to enable interrupt for event CTSTOPPED + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + HFCLKSTARTED + Write '1' to disable interrupt for event HFCLKSTARTED 0 0 @@ -1641,7 +1747,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LFCLKSTARTED - Write '1' to disable interrupt for LFCLKSTARTED event + Write '1' to disable interrupt for event LFCLKSTARTED 1 1 @@ -1668,7 +1774,7 @@ POSSIBILITY OF SUCH DAMAGE.\n DONE - Write '1' to disable interrupt for DONE event + Write '1' to disable interrupt for event DONE 3 3 @@ -1695,7 +1801,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTTO - Write '1' to disable interrupt for CTTO event + Write '1' to disable interrupt for event CTTO 4 4 @@ -1722,7 +1828,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTSTARTED - Write '1' to disable interrupt for CTSTARTED event + Write '1' to disable interrupt for event CTSTARTED 10 10 @@ -1749,7 +1855,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CTSTOPPED - Write '1' to disable interrupt for CTSTOPPED event + Write '1' to disable interrupt for event CTSTOPPED 11 11 @@ -2192,8 +2298,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_CONSTLAT + Enable constant latency mode 0 0 + + + Trigger + Trigger task + 1 + + @@ -2205,8 +2319,16 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_LOWPWR + Enable low power mode (variable latency) 0 0 + + + Trigger + Trigger task + 1 + + @@ -2218,8 +2340,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_POFWARN + Power failure warning 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2231,8 +2366,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SLEEPENTER + CPU entered WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2244,8 +2392,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SLEEPEXIT + CPU exited WFI/WFE sleep 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2257,8 +2418,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_USBDETECTED + Voltage supply detected on VBUS 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2270,8 +2444,21 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_USBREMOVED + Voltage supply removed from VBUS 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + @@ -2283,175 +2470,18 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_USBPWRRDY + USB 3.3 V supply ready 0 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - POFWARN - Write '1' to enable interrupt for POFWARN event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPENTER - Write '1' to enable interrupt for SLEEPENTER event - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - SLEEPEXIT - Write '1' to enable interrupt for SLEEPEXIT event - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBDETECTED - Write '1' to enable interrupt for USBDETECTED event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBREMOVED - Write '1' to enable interrupt for USBREMOVED event - 8 - 8 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - USBPWRRDY - Write '1' to enable interrupt for USBPWRRDY event - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 @@ -2459,14 +2489,184 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + INTENSET + Enable interrupt + 0x304 read-write POFWARN - Write '1' to disable interrupt for POFWARN event + Write '1' to enable interrupt for event POFWARN + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPENTER + Write '1' to enable interrupt for event SLEEPENTER + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SLEEPEXIT + Write '1' to enable interrupt for event SLEEPEXIT + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBDETECTED + Write '1' to enable interrupt for event USBDETECTED + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBREMOVED + Write '1' to enable interrupt for event USBREMOVED + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + USBPWRRDY + Write '1' to enable interrupt for event USBPWRRDY + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + POFWARN + Write '1' to disable interrupt for event POFWARN 2 2 @@ -2493,7 +2693,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPENTER - Write '1' to disable interrupt for SLEEPENTER event + Write '1' to disable interrupt for event SLEEPENTER 5 5 @@ -2520,7 +2720,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SLEEPEXIT - Write '1' to disable interrupt for SLEEPEXIT event + Write '1' to disable interrupt for event SLEEPEXIT 6 6 @@ -2547,7 +2747,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBDETECTED - Write '1' to disable interrupt for USBDETECTED event + Write '1' to disable interrupt for event USBDETECTED 7 7 @@ -2574,7 +2774,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBREMOVED - Write '1' to disable interrupt for USBREMOVED event + Write '1' to disable interrupt for event USBREMOVED 8 8 @@ -2601,7 +2801,7 @@ POSSIBILITY OF SUCH DAMAGE.\n USBPWRRDY - Write '1' to disable interrupt for USBPWRRDY event + Write '1' to disable interrupt for event USBPWRRDY 9 9 @@ -3240,10 +3440,11 @@ POSSIBILITY OF SUCH DAMAGE.\n RAM[%s] Unspecified POWER_RAM + read-write 0x900 POWER - Description cluster[n]: RAMn power control register + Description cluster: RAMn power control register 0x000 read-write 0x0000FFFF @@ -3828,7 +4029,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERSET - Description cluster[n]: RAMn power control set register + Description cluster: RAMn power control set register 0x004 write-only 0x0000FFFF @@ -4253,7 +4454,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWERCLR - Description cluster[n]: RAMn power control clear register + Description cluster: RAMn power control clear register 0x008 write-only 0x0000FFFF @@ -4680,820 +4881,596 @@ POSSIBILITY OF SUCH DAMAGE.\n - RADIO - 2.4 GHz radio - 0x40001000 + P0 + GPIO Port 1 + 0x50000000 + GPIO 0 0x1000 registers - - RADIO - 1 - - RADIO + GPIO 0x20 - TASKS_TXEN - Enable RADIO in TX mode - 0x000 - write-only + OUT + Write GPIO port + 0x504 + read-write - TASKS_TXEN + PIN0 + Pin 0 0 0 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_RXEN - Enable RADIO in RX mode - 0x004 - write-only - - TASKS_RXEN - 0 - 0 + PIN1 + Pin 1 + 1 + 1 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_START - Start RADIO - 0x008 - write-only - - TASKS_START - 0 - 0 + PIN2 + Pin 2 + 2 + 2 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_STOP - Stop RADIO - 0x00C - write-only - - TASKS_STOP - 0 - 0 + PIN3 + Pin 3 + 3 + 3 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_DISABLE - Disable RADIO - 0x010 - write-only - - TASKS_DISABLE - 0 - 0 + PIN4 + Pin 4 + 4 + 4 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_RSSISTART - Start the RSSI and take one single sample of the receive signal strength - 0x014 - write-only - - TASKS_RSSISTART - 0 - 0 + PIN5 + Pin 5 + 5 + 5 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_RSSISTOP - Stop the RSSI measurement - 0x018 - write-only - - TASKS_RSSISTOP - 0 - 0 + PIN6 + Pin 6 + 6 + 6 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_BCSTART - Start the bit counter - 0x01C - write-only - - TASKS_BCSTART - 0 - 0 + PIN7 + Pin 7 + 7 + 7 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_BCSTOP - Stop the bit counter - 0x020 - write-only - - TASKS_BCSTOP - 0 - 0 + PIN8 + Pin 8 + 8 + 8 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_EDSTART - Start the energy detect measurement used in IEEE 802.15.4 mode - 0x024 - write-only - - TASKS_EDSTART - 0 - 0 + PIN9 + Pin 9 + 9 + 9 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_EDSTOP - Stop the energy detect measurement - 0x028 - write-only - - TASKS_EDSTOP - 0 - 0 + PIN10 + Pin 10 + 10 + 10 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_CCASTART - Start the clear channel assessment used in IEEE 802.15.4 mode - 0x02C - write-only - - TASKS_CCASTART - 0 - 0 + PIN11 + Pin 11 + 11 + 11 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high + 1 + + - - - - TASKS_CCASTOP - Stop the clear channel assessment - 0x030 - write-only - - TASKS_CCASTOP - 0 - 0 - - - - - EVENTS_READY - RADIO has ramped up and is ready to be started - 0x100 - read-write - - - EVENTS_READY - 0 - 0 - - - - - EVENTS_ADDRESS - Address sent or received - 0x104 - read-write - - - EVENTS_ADDRESS - 0 - 0 - - - - - EVENTS_PAYLOAD - Packet payload sent or received - 0x108 - read-write - - - EVENTS_PAYLOAD - 0 - 0 - - - - - EVENTS_END - Packet sent or received - 0x10C - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_DISABLED - RADIO has been disabled - 0x110 - read-write - - - EVENTS_DISABLED - 0 - 0 - - - - - EVENTS_DEVMATCH - A device address match occurred on the last received packet - 0x114 - read-write - - - EVENTS_DEVMATCH - 0 - 0 - - - - - EVENTS_DEVMISS - No device address match occurred on the last received packet - 0x118 - read-write - - - EVENTS_DEVMISS - 0 - 0 - - - - - EVENTS_RSSIEND - Sampling of receive signal strength complete - 0x11C - read-write - - - EVENTS_RSSIEND - 0 - 0 - - - - - EVENTS_BCMATCH - Bit counter reached bit count value - 0x128 - read-write - - - EVENTS_BCMATCH - 0 - 0 - - - - - EVENTS_CRCOK - Packet received with CRC ok - 0x130 - read-write - - - EVENTS_CRCOK - 0 - 0 - - - - - EVENTS_CRCERROR - Packet received with CRC error - 0x134 - read-write - - - EVENTS_CRCERROR - 0 - 0 - - - - - EVENTS_FRAMESTART - IEEE 802.15.4 length field received - 0x138 - read-write - - - EVENTS_FRAMESTART - 0 - 0 - - - - - EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. - 0x13C - read-write - - - EVENTS_EDEND - 0 - 0 - - - - - EVENTS_EDSTOPPED - The sampling of energy detection has stopped - 0x140 - read-write - - - EVENTS_EDSTOPPED - 0 - 0 - - - - - EVENTS_CCAIDLE - Wireless medium in idle - clear to send - 0x144 - read-write - - - EVENTS_CCAIDLE - 0 - 0 - - - - - EVENTS_CCABUSY - Wireless medium busy - do not send - 0x148 - read-write - - - EVENTS_CCABUSY - 0 - 0 - - - - - EVENTS_CCASTOPPED - The CCA has stopped - 0x14C - read-write - - - EVENTS_CCASTOPPED - 0 - 0 - - - - - EVENTS_RATEBOOST - Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. - 0x150 - read-write - - - EVENTS_RATEBOOST - 0 - 0 - - - - - EVENTS_TXREADY - RADIO has ramped up and is ready to be started TX path - 0x154 - read-write - - - EVENTS_TXREADY - 0 - 0 - - - - - EVENTS_RXREADY - RADIO has ramped up and is ready to be started RX path - 0x158 - read-write - - - EVENTS_RXREADY - 0 - 0 - - - - - EVENTS_MHRMATCH - MAC header match found - 0x15C - read-write - - - EVENTS_MHRMATCH - 0 - 0 - - - - - EVENTS_PHYEND - Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. - 0x16C - read-write - - - EVENTS_PHYEND - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - READY_START - Shortcut between READY event and START task - 0 - 0 + PIN12 + Pin 12 + 12 + 12 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - END_DISABLE - Shortcut between END event and DISABLE task - 1 - 1 + PIN13 + Pin 13 + 13 + 13 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_TXEN - Shortcut between DISABLED event and TXEN task - 2 - 2 + PIN14 + Pin 14 + 14 + 14 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_RXEN - Shortcut between DISABLED event and RXEN task - 3 - 3 + PIN15 + Pin 15 + 15 + 15 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - ADDRESS_RSSISTART - Shortcut between ADDRESS event and RSSISTART task - 4 - 4 + PIN16 + Pin 16 + 16 + 16 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - END_START - Shortcut between END event and START task - 5 - 5 + PIN17 + Pin 17 + 17 + 17 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - ADDRESS_BCSTART - Shortcut between ADDRESS event and BCSTART task - 6 - 6 + PIN18 + Pin 18 + 18 + 18 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - DISABLED_RSSISTOP - Shortcut between DISABLED event and RSSISTOP task - 8 - 8 + PIN19 + Pin 19 + 19 + 19 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - RXREADY_CCASTART - Shortcut between RXREADY event and CCASTART task - 11 - 11 + PIN20 + Pin 20 + 20 + 20 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - CCAIDLE_TXEN - Shortcut between CCAIDLE event and TXEN task - 12 - 12 + PIN21 + Pin 21 + 21 + 21 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - CCABUSY_DISABLE - Shortcut between CCABUSY event and DISABLE task - 13 - 13 + PIN22 + Pin 22 + 22 + 22 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - FRAMESTART_BCSTART - Shortcut between FRAMESTART event and BCSTART task - 14 - 14 + PIN23 + Pin 23 + 23 + 23 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - READY_EDSTART - Shortcut between READY event and EDSTART task - 15 - 15 + PIN24 + Pin 24 + 24 + 24 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - EDEND_DISABLE - Shortcut between EDEND event and DISABLE task - 16 - 16 + PIN25 + Pin 25 + 25 + 25 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - CCAIDLE_STOP - Shortcut between CCAIDLE event and STOP task - 17 - 17 + PIN26 + Pin 26 + 26 + 26 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - TXREADY_START - Shortcut between TXREADY event and START task - 18 - 18 + PIN27 + Pin 27 + 27 + 27 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - RXREADY_START - Shortcut between RXREADY event and START task - 19 - 19 + PIN28 + Pin 28 + 28 + 28 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - PHYEND_DISABLE - Shortcut between PHYEND event and DISABLE task - 20 - 20 + PIN29 + Pin 29 + 29 + 29 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high 1 - PHYEND_START - Shortcut between PHYEND event and START task - 21 - 21 + PIN30 + Pin 30 + 30 + 30 - Disabled - Disable shortcut + Low + Pin driver is low 0 - Enabled - Enable shortcut + High + Pin driver is high + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin driver is low + 0 + + + High + Pin driver is high 1 @@ -5501,26 +5478,27 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + OUTSET + Set individual bits in GPIO port + 0x508 read-write + oneToSet - READY - Write '1' to enable interrupt for READY event + PIN0 + Pin 0 0 0 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5528,26 +5506,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDRESS - Write '1' to enable interrupt for ADDRESS event + PIN1 + Pin 1 1 1 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5555,26 +5533,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - PAYLOAD - Write '1' to enable interrupt for PAYLOAD event + PIN2 + Pin 2 2 2 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5582,26 +5560,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - END - Write '1' to enable interrupt for END event + PIN3 + Pin 3 3 3 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5609,26 +5587,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DISABLED - Write '1' to enable interrupt for DISABLED event + PIN4 + Pin 4 4 4 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5636,26 +5614,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMATCH - Write '1' to enable interrupt for DEVMATCH event + PIN5 + Pin 5 5 5 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5663,26 +5641,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMISS - Write '1' to enable interrupt for DEVMISS event + PIN6 + Pin 6 6 6 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5690,26 +5668,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - RSSIEND - Write '1' to enable interrupt for RSSIEND event + PIN7 + Pin 7 7 7 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5717,26 +5695,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - BCMATCH - Write '1' to enable interrupt for BCMATCH event - 10 - 10 + PIN8 + Pin 8 + 8 + 8 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5744,26 +5722,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CRCOK - Write '1' to enable interrupt for CRCOK event - 12 - 12 + PIN9 + Pin 9 + 9 + 9 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5771,26 +5749,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CRCERROR - Write '1' to enable interrupt for CRCERROR event - 13 - 13 + PIN10 + Pin 10 + 10 + 10 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5798,26 +5776,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - FRAMESTART - Write '1' to enable interrupt for FRAMESTART event - 14 - 14 + PIN11 + Pin 11 + 11 + 11 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5825,26 +5803,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - EDEND - Write '1' to enable interrupt for EDEND event - 15 - 15 + PIN12 + Pin 12 + 12 + 12 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5852,26 +5830,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - EDSTOPPED - Write '1' to enable interrupt for EDSTOPPED event - 16 - 16 + PIN13 + Pin 13 + 13 + 13 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5879,26 +5857,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CCAIDLE - Write '1' to enable interrupt for CCAIDLE event - 17 - 17 + PIN14 + Pin 14 + 14 + 14 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5906,26 +5884,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CCABUSY - Write '1' to enable interrupt for CCABUSY event - 18 - 18 + PIN15 + Pin 15 + 15 + 15 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5933,26 +5911,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CCASTOPPED - Write '1' to enable interrupt for CCASTOPPED event - 19 - 19 + PIN16 + Pin 16 + 16 + 16 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5960,26 +5938,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - RATEBOOST - Write '1' to enable interrupt for RATEBOOST event - 20 - 20 + PIN17 + Pin 17 + 17 + 17 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -5987,26 +5965,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - TXREADY - Write '1' to enable interrupt for TXREADY event - 21 - 21 + PIN18 + Pin 18 + 18 + 18 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6014,26 +5992,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - RXREADY - Write '1' to enable interrupt for RXREADY event - 22 - 22 + PIN19 + Pin 19 + 19 + 19 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6041,26 +6019,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - MHRMATCH - Write '1' to enable interrupt for MHRMATCH event - 23 - 23 + PIN20 + Pin 20 + 20 + 20 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6068,26 +6046,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - PHYEND - Write '1' to enable interrupt for PHYEND event - 27 - 27 + PIN21 + Pin 21 + 21 + 21 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6095,304 +6073,305 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + PIN22 + Pin 22 + 22 + 22 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - ADDRESS - Write '1' to disable interrupt for ADDRESS event - 1 - 1 + PIN23 + Pin 23 + 23 + 23 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - PAYLOAD - Write '1' to disable interrupt for PAYLOAD event - 2 - 2 + PIN24 + Pin 24 + 24 + 24 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - END - Write '1' to disable interrupt for END event - 3 - 3 + PIN25 + Pin 25 + 25 + 25 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DISABLED - Write '1' to disable interrupt for DISABLED event - 4 - 4 + PIN26 + Pin 26 + 26 + 26 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMATCH - Write '1' to disable interrupt for DEVMATCH event - 5 - 5 + PIN27 + Pin 27 + 27 + 27 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - DEVMISS - Write '1' to disable interrupt for DEVMISS event - 6 - 6 + PIN28 + Pin 28 + 28 + 28 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - RSSIEND - Write '1' to disable interrupt for RSSIEND event - 7 - 7 + PIN29 + Pin 29 + 29 + 29 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - BCMATCH - Write '1' to disable interrupt for BCMATCH event - 10 - 10 + PIN30 + Pin 30 + 30 + 30 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 - CRCOK - Write '1' to disable interrupt for CRCOK event - 12 - 12 + PIN31 + Pin 31 + 31 + 31 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 write - Clear - Disable + Set + Write: writing a '1' sets the pin high; writing a '0' has no effect 1 + + + + OUTCLR + Clear individual bits in GPIO port + 0x50C + read-write + oneToClear + - CRCERROR - Write '1' to disable interrupt for CRCERROR event - 13 - 13 + PIN0 + Pin 0 + 0 + 0 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6400,26 +6379,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - FRAMESTART - Write '1' to disable interrupt for FRAMESTART event - 14 - 14 + PIN1 + Pin 1 + 1 + 1 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6427,26 +6406,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - EDEND - Write '1' to disable interrupt for EDEND event - 15 - 15 + PIN2 + Pin 2 + 2 + 2 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6454,26 +6433,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - EDSTOPPED - Write '1' to disable interrupt for EDSTOPPED event - 16 - 16 + PIN3 + Pin 3 + 3 + 3 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6481,26 +6460,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - CCAIDLE - Write '1' to disable interrupt for CCAIDLE event - 17 - 17 + PIN4 + Pin 4 + 4 + 4 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6508,26 +6487,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - CCABUSY - Write '1' to disable interrupt for CCABUSY event - 18 - 18 + PIN5 + Pin 5 + 5 + 5 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6535,26 +6514,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - CCASTOPPED - Write '1' to disable interrupt for CCASTOPPED event - 19 - 19 + PIN6 + Pin 6 + 6 + 6 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6562,26 +6541,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - RATEBOOST - Write '1' to disable interrupt for RATEBOOST event - 20 - 20 + PIN7 + Pin 7 + 7 + 7 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6589,26 +6568,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - TXREADY - Write '1' to disable interrupt for TXREADY event - 21 - 21 + PIN8 + Pin 8 + 8 + 8 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6616,26 +6595,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - RXREADY - Write '1' to disable interrupt for RXREADY event - 22 - 22 + PIN9 + Pin 9 + 9 + 9 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6643,26 +6622,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - MHRMATCH - Write '1' to disable interrupt for MHRMATCH event - 23 - 23 + PIN10 + Pin 10 + 10 + 10 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6670,26 +6649,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - PHYEND - Write '1' to disable interrupt for PHYEND event - 27 - 27 + PIN11 + Pin 11 + 11 + 11 read - Disabled - Read: Disabled + Low + Read: pin driver is low 0 - Enabled - Read: Enabled + High + Read: pin driver is high 1 @@ -6697,1908 +6676,1715 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - - - - CRCSTATUS - CRC status - 0x400 - read-only - - CRCSTATUS - CRC status of packet received - 0 - 0 + PIN12 + Pin 12 + 12 + 12 + read - CRCError - Packet received with CRC error + Low + Read: pin driver is low 0 - CRCOk - Packet received with CRC ok + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - - - - RXMATCH - Received address - 0x408 - read-only - - - RXMATCH - Received address - 0 - 2 - - - - - RXCRC - CRC field of previously received packet - 0x40C - read-only - - - RXCRC - CRC field of previously received packet - 0 - 23 - - - - - DAI - Device address match index - 0x410 - read-only - - - DAI - Device address match index - 0 - 2 - - - - - PDUSTAT - Payload status - 0x414 - read-only - - PDUSTAT - Status on payload length vs. PCNF1.MAXLEN - 0 - 0 + PIN13 + Pin 13 + 13 + 13 + read - LessThan - Payload less than PCNF1.MAXLEN + Low + Read: pin driver is low 0 - GreaterThan - Payload greater than PCNF1.MAXLEN + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - CISTAT - Status on what rate packet is received with in Long Range - 1 - 2 + PIN14 + Pin 14 + 14 + 14 + read - LR125kbit - Frame is received at 125kbps + Low + Read: pin driver is low 0 - LR500kbit - Frame is received at 500kbps + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - - - - - PACKETPTR - Packet pointer - 0x504 - read-write - - - PACKETPTR - Packet pointer - 0 - 31 - - - - - FREQUENCY - Frequency - 0x508 - read-write - 0x00000002 - - - FREQUENCY - Radio channel frequency - 0 - 6 - MAP - Channel map selection. - 8 - 8 + PIN15 + Pin 15 + 15 + 15 + read - Default - Channel map between 2400 MHZ .. 2500 MHz + Low + Read: pin driver is low 0 - Low - Channel map between 2360 MHZ .. 2460 MHz + High + Read: pin driver is high 1 - - - - - TXPOWER - Output power - 0x50C - read-write - + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + - TXPOWER - RADIO output power - 0 - 7 + PIN16 + Pin 16 + 16 + 16 + read - Pos8dBm - +8 dBm - 0x8 + Low + Read: pin driver is low + 0 - Pos7dBm - +7 dBm - 0x7 + High + Read: pin driver is high + 1 + + + write - Pos6dBm - +6 dBm - 0x6 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN17 + Pin 17 + 17 + 17 + + read - Pos5dBm - +5 dBm - 0x5 + Low + Read: pin driver is low + 0 - Pos4dBm - +4 dBm - 0x4 + High + Read: pin driver is high + 1 + + + write - Pos3dBm - +3 dBm - 0x3 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN18 + Pin 18 + 18 + 18 + + read - Pos2dBm - +2 dBm - 0x2 + Low + Read: pin driver is low + 0 - 0dBm - 0 dBm - 0x0 + High + Read: pin driver is high + 1 + + + write - Neg4dBm - -4 dBm - 0xFC + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN19 + Pin 19 + 19 + 19 + + read - Neg8dBm - -8 dBm - 0xF8 + Low + Read: pin driver is low + 0 - Neg12dBm - -12 dBm - 0xF4 + High + Read: pin driver is high + 1 + + + write - Neg16dBm - -16 dBm - 0xF0 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN20 + Pin 20 + 20 + 20 + + read - Neg20dBm - -20 dBm - 0xEC + Low + Read: pin driver is low + 0 - Neg30dBm - Deprecated enumerator - -40 dBm - 0xFF + High + Read: pin driver is high + 1 + + + write - Neg40dBm - -40 dBm - 0xD8 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 - - - - MODE - Data rate and modulation - 0x510 - read-write - - MODE - Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. - 0 - 3 + PIN21 + Pin 21 + 21 + 21 + read - Nrf_1Mbit - 1 Mbit/s Nordic proprietary radio mode + Low + Read: pin driver is low 0 - Nrf_2Mbit - 2 Mbit/s Nordic proprietary radio mode + High + Read: pin driver is high 1 + + + write - Ble_1Mbit - 1 Mbit/s BLE - 3 - - - Ble_2Mbit - 2 Mbit/s BLE - 4 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + PIN22 + Pin 22 + 22 + 22 + + read - Ble_LR125Kbit - Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX - 5 + Low + Read: pin driver is low + 0 - Ble_LR500Kbit - Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX - 6 + High + Read: pin driver is high + 1 + + + write - Ieee802154_250Kbit - IEEE 802.15.4-2006 250 kbit/s - 15 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 - - - - PCNF0 - Packet configuration register 0 - 0x514 - read-write - - - LFLEN - Length on air of LENGTH field in number of bits. - 0 - 3 - - - S0LEN - Length on air of S0 field in number of bytes. - 8 - 8 - - - S1LEN - Length on air of S1 field in number of bits. - 16 - 19 - - S1INCL - Include or exclude S1 field in RAM - 20 - 20 + PIN23 + Pin 23 + 23 + 23 + read - Automatic - Include S1 field in RAM only if S1LEN &gt; 0 + Low + Read: pin driver is low 0 - Include - Always include S1 field in RAM independent of S1LEN + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - CILEN - Length of code indicator - long range - 22 - 23 - - - PLEN - Length of preamble on air. Decision point: TASKS_START task + PIN24 + Pin 24 24 - 25 + 24 + read - 8bit - 8-bit preamble + Low + Read: pin driver is low 0 - 16bit - 16-bit preamble + High + Read: pin driver is high 1 + + + write - 32bitZero - 32-bit zero preamble - used for IEEE 802.15.4 - 2 + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + + + + PIN25 + Pin 25 + 25 + 25 + + read + + Low + Read: pin driver is low + 0 - LongRange - Preamble - used for BLE long range - 3 + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 - CRCINC - Indicates if LENGTH field contains CRC or not + PIN26 + Pin 26 26 26 + read - Exclude - LENGTH does not contain CRC + Low + Read: pin driver is low 0 - Include - LENGTH includes CRC + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - TERMLEN - Length of TERM field in Long Range operation - 29 - 30 - - - - - PCNF1 - Packet configuration register 1 - 0x518 - read-write - - - MAXLEN - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. - 0 - 7 - - - STATLEN - Static length in number of bytes - 8 - 15 + PIN27 + Pin 27 + 27 + 27 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - BALEN - Base address length in number of bytes - 16 - 18 + PIN28 + Pin 28 + 28 + 28 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - ENDIAN - On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. - 24 - 24 + PIN29 + Pin 29 + 29 + 29 + read - Little - Least significant bit on air first + Low + Read: pin driver is low 0 - Big - Most significant bit on air first + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - WHITEEN - Enable or disable packet whitening - 25 - 25 + PIN30 + Pin 30 + 30 + 30 + read - Disabled - Disable + Low + Read: pin driver is low 0 - Enabled - Enable + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect 1 - - - - BASE0 - Base address 0 - 0x51C - read-write - - BASE0 - Base address 0 - 0 + PIN31 + Pin 31 + 31 31 + + read + + Low + Read: pin driver is low + 0 + + + High + Read: pin driver is high + 1 + + + + write + + Clear + Write: writing a '1' sets the pin low; writing a '0' has no effect + 1 + + - BASE1 - Base address 1 - 0x520 - read-write - - - BASE1 - Base address 1 - 0 - 31 - - - - - PREFIX0 - Prefixes bytes for logical addresses 0-3 - 0x524 - read-write - - - AP0 - Address prefix 0. - 0 - 7 - - - AP1 - Address prefix 1. - 8 - 15 - - - AP2 - Address prefix 2. - 16 - 23 - - - AP3 - Address prefix 3. - 24 - 31 - - - - - PREFIX1 - Prefixes bytes for logical addresses 4-7 - 0x528 - read-write - - - AP4 - Address prefix 4. - 0 - 7 - - - AP5 - Address prefix 5. - 8 - 15 - - - AP6 - Address prefix 6. - 16 - 23 - - - AP7 - Address prefix 7. - 24 - 31 - - - - - TXADDRESS - Transmit address select - 0x52C - read-write - - - TXADDRESS - Transmit address select - 0 - 2 - - - - - RXADDRESSES - Receive address select - 0x530 - read-write + IN + Read GPIO port + 0x510 + read-only - ADDR0 - Enable or disable reception on logical address 0. + PIN0 + Pin 0 0 0 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR1 - Enable or disable reception on logical address 1. + PIN1 + Pin 1 1 1 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR2 - Enable or disable reception on logical address 2. + PIN2 + Pin 2 2 2 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR3 - Enable or disable reception on logical address 3. + PIN3 + Pin 3 3 3 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR4 - Enable or disable reception on logical address 4. + PIN4 + Pin 4 4 4 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR5 - Enable or disable reception on logical address 5. + PIN5 + Pin 5 5 5 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR6 - Enable or disable reception on logical address 6. + PIN6 + Pin 6 6 6 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - ADDR7 - Enable or disable reception on logical address 7. + PIN7 + Pin 7 7 7 - Disabled - Disable + Low + Pin input is low 0 - Enabled - Enable + High + Pin input is high 1 - - - - CRCCNF - CRC configuration - 0x534 - read-write - - LEN - CRC length in number of bytes. - 0 - 1 + PIN8 + Pin 8 + 8 + 8 - Disabled - CRC length is zero and CRC calculation is disabled + Low + Pin input is low 0 - One - CRC length is one byte and CRC calculation is enabled + High + Pin input is high 1 - - Two - CRC length is two bytes and CRC calculation is enabled - 2 - - - Three - CRC length is three bytes and CRC calculation is enabled - 3 - - SKIPADDR - Include or exclude packet address field out of CRC calculation. - 8 + PIN9 + Pin 9 + 9 9 - Include - CRC calculation includes address field + Low + Pin input is low 0 - Skip - CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. + High + Pin input is high 1 - - Ieee802154 - CRC calculation as per 802.15.4 standard. Starting at first byte after length field. - 2 - - - - - CRCPOLY - CRC polynomial - 0x538 - read-write - 0x00000000 - - - CRCPOLY - CRC polynomial - 0 - 23 - - - - - CRCINIT - CRC initial value - 0x53C - read-write - - - CRCINIT - CRC initial value - 0 - 23 - - - - - TIFS - Interframe spacing in us - 0x544 - read-write - - - TIFS - Interframe spacing in us - 0 - 9 - - - - - RSSISAMPLE - RSSI sample - 0x548 - read-only - - - RSSISAMPLE - RSSI sample - 0 - 6 - - - - - STATE - Current radio state - 0x550 - read-only - - STATE - Current radio state - 0 - 3 + PIN10 + Pin 10 + 10 + 10 - Disabled - RADIO is in the Disabled state + Low + Pin input is low 0 - RxRu - RADIO is in the RXRU state + High + Pin input is high 1 - - RxIdle - RADIO is in the RXIDLE state - 2 - - - Rx - RADIO is in the RX state - 3 - - - RxDisable - RADIO is in the RXDISABLED state - 4 - - - TxRu - RADIO is in the TXRU state - 9 - - - TxIdle - RADIO is in the TXIDLE state - 10 - - - Tx - RADIO is in the TX state - 11 - - - TxDisable - RADIO is in the TXDISABLED state - 12 - - - - - DATAWHITEIV - Data whitening initial value - 0x554 - read-write - 0x00000040 - - - DATAWHITEIV - Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. - 0 - 6 - - - - - BCC - Bit counter compare - 0x560 - read-write - - - BCC - Bit counter compare - 0 - 31 - - - - - 0x8 - 0x4 - DAB[%s] - Description collection[n]: Device address base segment n - 0x600 - read-write - - - DAB - Device address base segment n - 0 - 31 - - - - - 0x8 - 0x4 - DAP[%s] - Description collection[n]: Device address prefix n - 0x620 - read-write - - - DAP - Device address prefix n - 0 - 15 - - - - - DACNF - Device address match configuration - 0x640 - read-write - - ENA0 - Enable or disable device address matching using device address 0 - 0 - 0 + PIN11 + Pin 11 + 11 + 11 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA1 - Enable or disable device address matching using device address 1 - 1 - 1 + PIN12 + Pin 12 + 12 + 12 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA2 - Enable or disable device address matching using device address 2 - 2 - 2 + PIN13 + Pin 13 + 13 + 13 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA3 - Enable or disable device address matching using device address 3 - 3 - 3 + PIN14 + Pin 14 + 14 + 14 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA4 - Enable or disable device address matching using device address 4 - 4 - 4 + PIN15 + Pin 15 + 15 + 15 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA5 - Enable or disable device address matching using device address 5 - 5 - 5 + PIN16 + Pin 16 + 16 + 16 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA6 - Enable or disable device address matching using device address 6 - 6 - 6 + PIN17 + Pin 17 + 17 + 17 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - ENA7 - Enable or disable device address matching using device address 7 - 7 - 7 + PIN18 + Pin 18 + 18 + 18 - Disabled - Disabled + Low + Pin input is low 0 - Enabled - Enabled + High + Pin input is high 1 - TXADD0 - TxAdd for device address 0 - 8 - 8 - - - TXADD1 - TxAdd for device address 1 - 9 - 9 + PIN19 + Pin 19 + 19 + 19 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD2 - TxAdd for device address 2 - 10 - 10 + PIN20 + Pin 20 + 20 + 20 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD3 - TxAdd for device address 3 - 11 - 11 + PIN21 + Pin 21 + 21 + 21 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD4 - TxAdd for device address 4 - 12 - 12 + PIN22 + Pin 22 + 22 + 22 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD5 - TxAdd for device address 5 - 13 - 13 + PIN23 + Pin 23 + 23 + 23 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD6 - TxAdd for device address 6 - 14 - 14 + PIN24 + Pin 24 + 24 + 24 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - TXADD7 - TxAdd for device address 7 - 15 - 15 + PIN25 + Pin 25 + 25 + 25 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - - - - MHRMATCHCONF - Search pattern configuration - 0x644 - read-write - - - MHRMATCHMAS - Pattern mask - 0x648 - read-write - - - MODECNF0 - Radio mode configuration register 0 - 0x650 - read-write - 0x00000200 - - RU - Radio ramp-up time - 0 - 0 + PIN26 + Pin 26 + 26 + 26 - Default - Default ramp-up time (tRXEN), compatible with firmware written for nRF51 + Low + Pin input is low 0 - Fast - Fast ramp-up (tRXEN,FAST), see electrical specification for more information + High + Pin input is high 1 - DTX - Default TX value - 8 - 9 + PIN27 + Pin 27 + 27 + 27 - B1 - Transmit '1' + Low + Pin input is low 0 - B0 - Transmit '0' + High + Pin input is high 1 + + + + PIN28 + Pin 28 + 28 + 28 + - Center - Transmit center frequency - 2 + Low + Pin input is low + 0 + + + High + Pin input is high + 1 - - - - SFD - IEEE 802.15.4 start of frame delimiter - 0x660 - read-write - 0x000000A7 - - SFD - IEEE 802.15.4 start of frame delimiter - 0 - 7 + PIN29 + Pin 29 + 29 + 29 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - - - - EDCNT - IEEE 802.15.4 energy detect loop count - 0x664 - read-write - 0x00000000 - - EDCNT - IEEE 802.15.4 energy detect loop count - 0 - 20 + PIN30 + Pin 30 + 30 + 30 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - - - - EDSAMPLE - IEEE 802.15.4 energy detect level - 0x668 - read-write - 0x00000000 - - EDLVL - IEEE 802.15.4 energy detect level - 0 - 7 + PIN31 + Pin 31 + 31 + 31 + + + Low + Pin input is low + 0 + + + High + Pin input is high + 1 + + - CCACTRL - IEEE 802.15.4 clear channel assessment control - 0x66C + DIR + Direction of GPIO pins + 0x514 read-write - 0x00000000 - CCAMODE - CCA mode of operation + PIN0 + Pin 0 0 - 2 + 0 - EdMode - Energy above threshold + Input + Pin set as input 0 - CarrierMode - Carrier seen + Output + Pin set as output 1 + + + + PIN1 + Pin 1 + 1 + 1 + - CarrierAndEdMode - Energy above threshold AND carrier seen - 2 + Input + Pin set as input + 0 - CarrierOrEdMode - Energy above threshold OR carrier seen - 3 + Output + Pin set as output + 1 + + + + PIN2 + Pin 2 + 2 + 2 + - EdModeTest1 - Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. - 4 + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 - CCAEDTHRES - CCA energy busy threshold. Used in all the CCA modes except CarrierMode. - 8 - 15 + PIN3 + Pin 3 + 3 + 3 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + - CCACORRTHRES - CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. - 16 - 23 + PIN4 + Pin 4 + 4 + 4 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + - CCACORRCNT - Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. - 24 - 31 + PIN5 + Pin 5 + 5 + 5 + + + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + - - - - POWER - Peripheral power control - 0xFFC - read-write - 0x00000001 - - POWER - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. - 0 - 0 + PIN6 + Pin 6 + 6 + 6 - Disabled - Peripheral is powered off + Input + Pin set as input 0 - Enabled - Peripheral is powered on + Output + Pin set as output 1 - - - - - - UART0 - Universal Asynchronous Receiver/Transmitter - 0x40002000 - UART - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UART - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - 0 - 0 - - - - - TASKS_SUSPEND - Suspend UART - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - 0 - 0 - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - 0 - 0 - - - - - EVENTS_RXDRDY - Data received in RXD - 0x108 - read-write - - - EVENTS_RXDRDY - 0 - 0 - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - 0 - 0 - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - CTS_STARTRX - Shortcut between CTS event and STARTRX task - 3 - 3 + PIN7 + Pin 7 + 7 + 7 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - NCTS_STOPRX - Shortcut between NCTS event and STOPRX task - 4 - 4 + PIN8 + Pin 8 + 8 + 8 - Disabled - Disable shortcut + Input + Pin set as input 0 - Enabled - Enable shortcut + Output + Pin set as output 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - CTS - Write '1' to enable interrupt for CTS event - 0 - 0 + PIN9 + Pin 9 + 9 + 9 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - NCTS - Write '1' to enable interrupt for NCTS event - 1 - 1 + PIN10 + Pin 10 + 10 + 10 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Output + Pin set as output 1 - RXDRDY - Write '1' to enable interrupt for RXDRDY event - 2 - 2 + PIN11 + Pin 11 + 11 + 11 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN12 + Pin 12 + 12 + 12 - write - Set - Enable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - TXDRDY - Write '1' to enable interrupt for TXDRDY event - 7 - 7 + PIN13 + Pin 13 + 13 + 13 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN14 + Pin 14 + 14 + 14 - write - Set - Enable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN15 + Pin 15 + 15 + 15 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN16 + Pin 16 + 16 + 16 - write - Set - Enable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - RXTO - Write '1' to enable interrupt for RXTO event + PIN17 + Pin 17 17 17 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN18 + Pin 18 + 18 + 18 - write - Set - Enable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - CTS - Write '1' to disable interrupt for CTS event - 0 - 0 + PIN19 + Pin 19 + 19 + 19 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN20 + Pin 20 + 20 + 20 - write - Clear - Disable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - NCTS - Write '1' to disable interrupt for NCTS event - 1 - 1 + PIN21 + Pin 21 + 21 + 21 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN22 + Pin 22 + 22 + 22 - write - Clear - Disable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - RXDRDY - Write '1' to disable interrupt for RXDRDY event - 2 - 2 + PIN23 + Pin 23 + 23 + 23 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN24 + Pin 24 + 24 + 24 - write - Clear - Disable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - TXDRDY - Write '1' to disable interrupt for TXDRDY event - 7 - 7 + PIN25 + Pin 25 + 25 + 25 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN26 + Pin 26 + 26 + 26 - write - Clear - Disable - 1 + Input + Pin set as input + 0 - + + Output + Pin set as output + 1 + + - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN27 + Pin 27 + 27 + 27 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN28 + Pin 28 + 28 + 28 - write - Clear - Disable + Input + Pin set as input + 0 + + + Output + Pin set as output 1 - RXTO - Write '1' to disable interrupt for RXTO event - 17 - 17 + PIN29 + Pin 29 + 29 + 29 - read - Disabled - Read: Disabled + Input + Pin set as input 0 - Enabled - Read: Enabled + Output + Pin set as output 1 + + + PIN30 + Pin 30 + 30 + 30 - write - Clear - Disable + Input + Pin set as input + 0 + + + Output + Pin set as output + 1 + + + + + PIN31 + Pin 31 + 31 + 31 + + + Input + Pin set as input + 0 + + + Output + Pin set as output 1 @@ -8606,957 +8392,486 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERRORSRC - Error source - 0x480 + DIRSET + DIR set register + 0x518 read-write - oneToClear + oneToSet - OVERRUN - Overrun error + PIN0 + Set as output pin 0 0 0 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - PARITY - Parity error + PIN1 + Set as output pin 1 1 1 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - FRAMING - Framing error occurred + PIN2 + Set as output pin 2 2 2 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - BREAK - Break condition + PIN3 + Set as output pin 3 3 3 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - ENABLE - Enable UART - 0x500 - read-write - - ENABLE - Enable or disable UART - 0 - 3 + PIN4 + Set as output pin 4 + 4 + 4 + read - Disabled - Disable UART + Input + Read: pin set as input 0 - Enabled - Enable UART - 4 + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 - - - - PSEL - Unspecified - UART_PSEL - 0x508 - - RTS - Pin select for RTS - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received in previous transfers, double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - write-only - - - TXD - TX data to be transferred - 0 - 7 - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - BAUDRATE - Baud rate - 0 - 31 + PIN5 + Set as output pin 5 + 5 + 5 + read - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 + Input + Read: pin set as input + 0 - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 + Output + Read: pin set as output + 1 + + + write - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + PIN6 + Set as output pin 6 + 6 + 6 + + read - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 + Input + Read: pin set as input + 0 - Baud14400 - 14400 baud (actual rate: 14414) - 0x003B0000 + Output + Read: pin set as output + 1 + + + write - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + PIN7 + Set as output pin 7 + 7 + 7 + + read - Baud28800 - 28800 baud (actual rate: 28829) - 0x0075F000 + Input + Read: pin set as input + 0 - Baud31250 - 31250 baud - 0x00800000 + Output + Read: pin set as output + 1 + + + write - Baud38400 - 38400 baud (actual rate: 38462) - 0x009D5000 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 + + + + PIN8 + Set as output pin 8 + 8 + 8 + + read - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 - - - Baud57600 - 57600 baud (actual rate: 57762) - 0x00EBF000 - - - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 - - - Baud115200 - 115200 baud (actual rate: 115942) - 0x01D7E000 - - - Baud230400 - 230400 baud (actual rate: 231884) - 0x03AFB000 - - - Baud250000 - 250000 baud - 0x04000000 - - - Baud460800 - 460800 baud (actual rate: 470588) - 0x075F7000 + Input + Read: pin set as input + 0 - Baud921600 - 921600 baud (actual rate: 941176) - 0x0EBED000 + Output + Read: pin set as output + 1 + + + write - Baud1M - 1Mega baud - 0x10000000 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - HWFC - Hardware flow control - 0 - 0 + PIN9 + Set as output pin 9 + 9 + 9 + read - Disabled - Disabled + Input + Read: pin set as input 0 - Enabled - Enabled + Output + Read: pin set as output 1 - - - PARITY - Parity - 1 - 3 + write - Excluded - Exclude parity bit - 0x0 - - - Included - Include parity bit - 0x7 + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect + 1 - - - - - - UARTE0 - UART with EasyDMA 0 - 0x40002000 - UART0 - UARTE - - 0 - 0x1000 - registers - - - UARTE0_UART0 - 2 - - UARTE - 0x20 - - - TASKS_STARTRX - Start UART receiver - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STOPRX - Stop UART receiver - 0x004 - write-only - - - TASKS_STOPRX - 0 - 0 - - - - - TASKS_STARTTX - Start UART transmitter - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOPTX - Stop UART transmitter - 0x00C - write-only - - - TASKS_STOPTX - 0 - 0 - - - - - TASKS_FLUSHRX - Flush RX FIFO into RX buffer - 0x02C - write-only - - - TASKS_FLUSHRX - 0 - 0 - - - - - EVENTS_CTS - CTS is activated (set low). Clear To Send. - 0x100 - read-write - - - EVENTS_CTS - 0 - 0 - - - - - EVENTS_NCTS - CTS is deactivated (set high). Not Clear To Send. - 0x104 - read-write - - - EVENTS_NCTS - 0 - 0 - - - - - EVENTS_RXDRDY - Data received in RXD (but potentially not yet transferred to Data RAM) - 0x108 - read-write - - - EVENTS_RXDRDY - 0 - 0 - - - - - EVENTS_ENDRX - Receive buffer is filled up - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_TXDRDY - Data sent from TXD - 0x11C - read-write - - - EVENTS_TXDRDY - 0 - 0 - - - - - EVENTS_ENDTX - Last TX byte transmitted - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_ERROR - Error detected - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXTO - Receiver timeout - 0x144 - read-write - - - EVENTS_RXTO - 0 - 0 - - - - - EVENTS_RXSTARTED - UART receiver has started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - UART transmitter has started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_TXSTOPPED - Transmitter stopped - 0x158 - read-write - - - EVENTS_TXSTOPPED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - ENDRX_STARTRX - Shortcut between ENDRX event and STARTRX task - 5 - 5 + PIN10 + Set as output pin 10 + 10 + 10 + read - Disabled - Disable shortcut + Input + Read: pin set as input 0 - Enabled - Enable shortcut + Output + Read: pin set as output 1 - - - ENDRX_STOPRX - Shortcut between ENDRX event and STOPRX task - 6 - 6 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - CTS - Enable or disable interrupt for CTS event - 0 - 0 + PIN11 + Set as output pin 11 + 11 + 11 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - NCTS - Enable or disable interrupt for NCTS event - 1 - 1 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXDRDY - Enable or disable interrupt for RXDRDY event - 2 - 2 + PIN12 + Set as output pin 12 + 12 + 12 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - ENDRX - Enable or disable interrupt for ENDRX event - 4 - 4 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXDRDY - Enable or disable interrupt for TXDRDY event - 7 - 7 + PIN13 + Set as output pin 13 + 13 + 13 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - ENDTX - Enable or disable interrupt for ENDTX event - 8 - 8 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + PIN14 + Set as output pin 14 + 14 + 14 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - RXTO - Enable or disable interrupt for RXTO event - 17 - 17 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + PIN15 + Set as output pin 15 + 15 + 15 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output 1 - - - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTOPPED - Enable or disable interrupt for TXSTOPPED event - 22 - 22 + PIN16 + Set as output pin 16 + 16 + 16 + read - Disabled - Disable + Input + Read: pin set as input 0 - Enabled - Enable + Output + Read: pin set as output + 1 + + + + write + + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - CTS - Write '1' to enable interrupt for CTS event - 0 - 0 + PIN17 + Set as output pin 17 + 17 + 17 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9564,26 +8879,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - NCTS - Write '1' to enable interrupt for NCTS event - 1 - 1 + PIN18 + Set as output pin 18 + 18 + 18 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9591,26 +8906,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXDRDY - Write '1' to enable interrupt for RXDRDY event - 2 - 2 + PIN19 + Set as output pin 19 + 19 + 19 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9618,26 +8933,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN20 + Set as output pin 20 + 20 + 20 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9645,26 +8960,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXDRDY - Write '1' to enable interrupt for TXDRDY event - 7 - 7 + PIN21 + Set as output pin 21 + 21 + 21 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9672,26 +8987,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN22 + Set as output pin 22 + 22 + 22 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9699,26 +9014,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + PIN23 + Set as output pin 23 + 23 + 23 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9726,26 +9041,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXTO - Write '1' to enable interrupt for RXTO event - 17 - 17 + PIN24 + Set as output pin 24 + 24 + 24 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9753,26 +9068,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + PIN25 + Set as output pin 25 + 25 + 25 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9780,26 +9095,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + PIN26 + Set as output pin 26 + 26 + 26 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9807,26 +9122,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - TXSTOPPED - Write '1' to enable interrupt for TXSTOPPED event - 22 - 22 + PIN27 + Set as output pin 27 + 27 + 27 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9834,142 +9149,143 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Enable + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - CTS - Write '1' to disable interrupt for CTS event - 0 - 0 + PIN28 + Set as output pin 28 + 28 + 28 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - NCTS - Write '1' to disable interrupt for NCTS event - 1 - 1 + PIN29 + Set as output pin 29 + 29 + 29 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - RXDRDY - Write '1' to disable interrupt for RXDRDY event - 2 - 2 + PIN30 + Set as output pin 30 + 30 + 30 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN31 + Set as output pin 31 + 31 + 31 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Clear - Disable + Set + Write: writing a '1' sets pin to output; writing a '0' has no effect 1 + + + + DIRCLR + DIR clear register + 0x51C + read-write + oneToClear + - TXDRDY - Write '1' to disable interrupt for TXDRDY event - 7 - 7 + PIN0 + Set as input pin 0 + 0 + 0 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -9977,26 +9293,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDTX - Write '1' to disable interrupt for ENDTX event - 8 - 8 + PIN1 + Set as input pin 1 + 1 + 1 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10004,26 +9320,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + PIN2 + Set as input pin 2 + 2 + 2 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10031,26 +9347,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - RXTO - Write '1' to disable interrupt for RXTO event - 17 - 17 + PIN3 + Set as input pin 3 + 3 + 3 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10058,26 +9374,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event - 19 - 19 + PIN4 + Set as input pin 4 + 4 + 4 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10085,26 +9401,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event - 20 - 20 + PIN5 + Set as input pin 5 + 5 + 5 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10112,26 +9428,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - TXSTOPPED - Write '1' to disable interrupt for TXSTOPPED event - 22 - 22 + PIN6 + Set as input pin 6 + 6 + 6 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10139,639 +9455,377 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - ERRORSRC - Error source Note : this register is read / write one to clear. - 0x480 - read-write - oneToClear - - OVERRUN - Overrun error - 0 - 0 + PIN7 + Set as input pin 7 + 7 + 7 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output 1 - - - PARITY - Parity error - 1 - 1 - read - - NotPresent - Read: error not present - 0 - + write - Present - Read: error present + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - FRAMING - Framing error occurred - 2 - 2 + PIN8 + Set as input pin 8 + 8 + 8 read - NotPresent - Read: error not present + Input + Read: pin set as input 0 - Present - Read: error present + Output + Read: pin set as output 1 - - - BREAK - Break condition - 3 - 3 - read + write - NotPresent - Read: error not present - 0 - - - Present - Read: error present - 1 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - ENABLE - Enable UART - 0x500 - read-write - - ENABLE - Enable or disable UARTE - 0 - 3 + PIN9 + Set as input pin 9 + 9 + 9 + read - Disabled - Disable UARTE + Input + Read: pin set as input 0 - Enabled - Enable UARTE - 8 + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - PSEL - Unspecified - UARTE_PSEL - 0x508 - - RTS - Pin select for RTS signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - TXD - Pin select for TXD signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CTS - Pin select for CTS signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - RXD - Pin select for RXD signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - BAUDRATE - Baud rate. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - BAUDRATE - Baud rate - 0 - 31 + PIN10 + Set as input pin 10 + 10 + 10 + read - Baud1200 - 1200 baud (actual rate: 1205) - 0x0004F000 + Input + Read: pin set as input + 0 - Baud2400 - 2400 baud (actual rate: 2396) - 0x0009D000 + Output + Read: pin set as output + 1 + + + write - Baud4800 - 4800 baud (actual rate: 4808) - 0x0013B000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN11 + Set as input pin 11 + 11 + 11 + + read - Baud9600 - 9600 baud (actual rate: 9598) - 0x00275000 + Input + Read: pin set as input + 0 - Baud14400 - 14400 baud (actual rate: 14401) - 0x003AF000 + Output + Read: pin set as output + 1 + + + write - Baud19200 - 19200 baud (actual rate: 19208) - 0x004EA000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN12 + Set as input pin 12 + 12 + 12 + + read - Baud28800 - 28800 baud (actual rate: 28777) - 0x0075C000 + Input + Read: pin set as input + 0 - Baud31250 - 31250 baud - 0x00800000 + Output + Read: pin set as output + 1 + + + write - Baud38400 - 38400 baud (actual rate: 38369) - 0x009D0000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN13 + Set as input pin 13 + 13 + 13 + + read - Baud56000 - 56000 baud (actual rate: 55944) - 0x00E50000 + Input + Read: pin set as input + 0 - Baud57600 - 57600 baud (actual rate: 57554) - 0x00EB0000 + Output + Read: pin set as output + 1 + + + write - Baud76800 - 76800 baud (actual rate: 76923) - 0x013A9000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN14 + Set as input pin 14 + 14 + 14 + + read - Baud115200 - 115200 baud (actual rate: 115108) - 0x01D60000 + Input + Read: pin set as input + 0 - Baud230400 - 230400 baud (actual rate: 231884) - 0x03B00000 + Output + Read: pin set as output + 1 + + + write - Baud250000 - 250000 baud - 0x04000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN15 + Set as input pin 15 + 15 + 15 + + read - Baud460800 - 460800 baud (actual rate: 457143) - 0x07400000 + Input + Read: pin set as input + 0 - Baud921600 - 921600 baud (actual rate: 941176) - 0x0F000000 + Output + Read: pin set as output + 1 + + + write - Baud1M - 1Mega baud - 0x10000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - RXD - RXD EasyDMA channel - UARTE_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - UARTE_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - - CONFIG - Configuration of parity and hardware flow control - 0x56C - read-write - - HWFC - Hardware flow control - 0 - 0 + PIN16 + Set as input pin 16 + 16 + 16 + read - Disabled - Disabled + Input + Read: pin set as input 0 - Enabled - Enabled + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - PARITY - Parity - 1 - 3 + PIN17 + Set as input pin 17 + 17 + 17 + read - Excluded - Exclude parity bit - 0x0 + Input + Read: pin set as input + 0 - Included - Include even parity bit - 0x7 + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - STOP - Stop bits - 4 - 4 + PIN18 + Set as input pin 18 + 18 + 18 + read - One - One stop bit + Input + Read: pin set as input 0 - Two - Two stop bits + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - - - SPI0 - Serial Peripheral Interface 0 - 0x40003000 - SPI - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPI - 0x20 - - - EVENTS_READY - TXD byte sent and RXD byte received - 0x108 - read-write - - - EVENTS_READY - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 2 - 2 + PIN19 + Set as input pin 19 + 19 + 19 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 2 - 2 + PIN20 + Set as input pin 20 + 20 + 20 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 @@ -10779,1672 +9833,888 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - ENABLE - Enable SPI - 0x500 - read-write - - ENABLE - Enable or disable SPI - 0 - 3 + PIN21 + Set as input pin 21 + 21 + 21 + read - Disabled - Disable SPI + Input + Read: pin set as input 0 - Enabled - Enable SPI + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - PSEL - Unspecified - SPI_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RX data received. Double buffered - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TX data to send. Double buffered - 0 - 7 - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - SPI master data rate - 0 - 31 + PIN22 + Set as input pin 22 + 22 + 22 + read - K125 - 125 kbps - 0x02000000 + Input + Read: pin set as input + 0 - K250 - 250 kbps - 0x04000000 + Output + Read: pin set as output + 1 + + + write - K500 - 500 kbps - 0x08000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN23 + Set as input pin 23 + 23 + 23 + + read - M1 - 1 Mbps - 0x10000000 + Input + Read: pin set as input + 0 - M2 - 2 Mbps - 0x20000000 + Output + Read: pin set as output + 1 + + + write - M4 - 4 Mbps - 0x40000000 + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 + + + + PIN24 + Set as input pin 24 + 24 + 24 + + read - M8 - 8 Mbps - 0x80000000 + Input + Read: pin set as input + 0 + + + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect + 1 - - - - CONFIG - Configuration register - 0x554 - read-write - - ORDER - Bit order - 0 - 0 + PIN25 + Set as input pin 25 + 25 + 25 + read - MsbFirst - Most significant bit shifted out first + Input + Read: pin set as input 0 - LsbFirst - Least significant bit shifted out first + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - CPHA - Serial clock (SCK) phase - 1 - 1 + PIN26 + Set as input pin 26 + 26 + 26 + read - Leading - Sample on leading edge of clock, shift serial data on trailing edge + Input + Read: pin set as input 0 - Trailing - Sample on trailing edge of clock, shift serial data on leading edge + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - CPOL - Serial clock (SCK) polarity - 2 - 2 + PIN27 + Set as input pin 27 + 27 + 27 + read - ActiveHigh - Active high + Input + Read: pin set as input 0 - ActiveLow - Active low + Output + Read: pin set as output + 1 + + + + write + + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - - - - - - SPIM0 - Serial Peripheral Interface Master with EasyDMA 0 - 0x40003000 - SPI0 - SPIM - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPIM - 0x20 - - - TASKS_START - Start SPI transaction - 0x010 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop SPI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend SPI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume SPI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - SPI transaction has stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_END - End of RXD buffer and TXD buffer reached - 0x118 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_ENDTX - End of TXD buffer reached - 0x120 - read-write - - - EVENTS_ENDTX - 0 - 0 - - - - - EVENTS_STARTED - Transaction started - 0x14C - read-write - - - EVENTS_STARTED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - END_START - Shortcut between END event and START task - 17 - 17 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + PIN28 + Set as input pin 28 + 28 + 28 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN29 + Set as input pin 29 + 29 + 29 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - END - Write '1' to enable interrupt for END event - 6 - 6 + PIN30 + Set as input pin 30 + 30 + 30 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 - ENDTX - Write '1' to enable interrupt for ENDTX event - 8 - 8 + PIN31 + Set as input pin 31 + 31 + 31 read - Disabled - Read: Disabled + Input + Read: pin set as input 0 - Enabled - Read: Enabled + Output + Read: pin set as output 1 write - Set - Enable + Clear + Write: writing a '1' sets pin to input; writing a '0' has no effect 1 + + + + LATCH + Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers + 0x520 + read-write + - STARTED - Write '1' to enable interrupt for STARTED event - 19 - 19 + PIN0 + Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + 0 + 0 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN1 + Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + 1 + 1 - write - Set - Enable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + PIN2 + Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + 2 + 2 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN3 + Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + 3 + 3 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - ENDRX - Write '1' to disable interrupt for ENDRX event + PIN4 + Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN5 + Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + 5 + 5 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - END - Write '1' to disable interrupt for END event + PIN6 + Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. 6 6 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN7 + Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + 7 + 7 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - ENDTX - Write '1' to disable interrupt for ENDTX event + PIN8 + Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. 8 8 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN9 + Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + 9 + 9 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - STARTED - Write '1' to disable interrupt for STARTED event - 19 - 19 + PIN10 + Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + 10 + 10 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN11 + Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + 11 + 11 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - - - - STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. - 0x400 - read-write - 0x00000000 - - TX - Stall status for EasyDMA RAM reads - 0 - 0 + PIN12 + Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + 12 + 12 - NOSTALL - No stall + NotLatched + Criteria has not been met 0 - STALL - A stall has occurred + Latched + Criteria has been met 1 - RX - Stall status for EasyDMA RAM writes - 1 - 1 + PIN13 + Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + 13 + 13 - NOSTALL - No stall + NotLatched + Criteria has not been met 0 - STALL - A stall has occurred + Latched + Criteria has been met 1 - - - - ENABLE - Enable SPIM - 0x500 - read-write - - ENABLE - Enable or disable SPIM - 0 - 3 + PIN14 + Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + 14 + 14 - Disabled - Disable SPIM + NotLatched + Criteria has not been met 0 - Enabled - Enable SPIM - 7 + Latched + Criteria has been met + 1 - - - - PSEL - Unspecified - SPIM_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - SPI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - SPI master data rate - 0 - 31 + PIN15 + Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + 15 + 15 - K125 - 125 kbps - 0x02000000 - - - K250 - 250 kbps - 0x04000000 - - - K500 - 500 kbps - 0x08000000 - - - M1 - 1 Mbps - 0x10000000 + NotLatched + Criteria has not been met + 0 - M2 - 2 Mbps - 0x20000000 + Latched + Criteria has been met + 1 + + + + PIN16 + Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + 16 + 16 + - M4 - 4 Mbps - 0x40000000 + NotLatched + Criteria has not been met + 0 - M8 - 8 Mbps - 0x80000000 + Latched + Criteria has been met + 1 + + + + PIN17 + Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + 17 + 17 + - M16 - 16 Mbps - 0x0A000000 + NotLatched + Criteria has not been met + 0 - M32 - 32 Mbps - 0x14000000 + Latched + Criteria has been met + 1 - - - - RXD - RXD EasyDMA channel - SPIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - SPIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 1 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - CONFIG - Configuration register - 0x554 - read-write - - ORDER - Bit order - 0 - 0 + PIN18 + Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + 18 + 18 - MsbFirst - Most significant bit shifted out first + NotLatched + Criteria has not been met 0 - LsbFirst - Least significant bit shifted out first + Latched + Criteria has been met 1 - CPHA - Serial clock (SCK) phase - 1 - 1 + PIN19 + Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + 19 + 19 - Leading - Sample on leading edge of clock, shift serial data on trailing edge + NotLatched + Criteria has not been met 0 - Trailing - Sample on trailing edge of clock, shift serial data on leading edge + Latched + Criteria has been met 1 - CPOL - Serial clock (SCK) polarity - 2 - 2 + PIN20 + Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + 20 + 20 - ActiveHigh - Active high + NotLatched + Criteria has not been met 0 - ActiveLow - Active low + Latched + Criteria has been met 1 - - - - IFTIMING - Unspecified - SPIM_IFTIMING - 0x560 - - RXDELAY - Sample delay for input serial data on MISO - 0x000 - read-write - 0x00000002 - - - RXDELAY - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. - 0 - 2 - - - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions - 0x004 - read-write - 0x00000002 - - - CSNDUR - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). - 0 - 7 - - - - - - CSNPOL - Polarity of CSN output - 0x568 - read-write - 0x00000000 - - CSNPOL - Polarity of CSN output - 0 - 0 + PIN21 + Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + 21 + 21 - LOW - Active low (idle state high) + NotLatched + Criteria has not been met 0 - HIGH - Active high (idle state low) + Latched + Criteria has been met 1 - - - - PSELDCX - Pin select for DCX signal - 0x56C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - CONNECT - Connection - 31 - 31 + PIN22 + Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + 22 + 22 - Disconnected - Disconnect - 1 + NotLatched + Criteria has not been met + 0 - Connected - Connect - 0 + Latched + Criteria has been met + 1 - - - - DCXCNT - DCX configuration - 0x570 - read-write - - - DCXCNT - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. - 0 - 3 - - - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT - 0x5C0 - read-write - - - ORC - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. - 0 - 7 - - - - - - - SPIS0 - SPI Slave 0 - 0x40003000 - SPI0 - SPIS - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - SPIS - 0x20 - - - TASKS_ACQUIRE - Acquire SPI semaphore - 0x024 - write-only - - - TASKS_ACQUIRE - 0 - 0 - - - - - TASKS_RELEASE - Release SPI semaphore, enabling the SPI slave to acquire it - 0x028 - write-only - - - TASKS_RELEASE - 0 - 0 - - - - - EVENTS_END - Granted transaction completed - 0x104 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_ENDRX - End of RXD buffer reached - 0x110 - read-write - - - EVENTS_ENDRX - 0 - 0 - - - - - EVENTS_ACQUIRED - Semaphore acquired - 0x128 - read-write - - - EVENTS_ACQUIRED - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - END_ACQUIRE - Shortcut between END event and ACQUIRE task - 2 - 2 + PIN23 + Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + 23 + 23 - Disabled - Disable shortcut + NotLatched + Criteria has not been met 0 - Enabled - Enable shortcut + Latched + Criteria has been met 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - END - Write '1' to enable interrupt for END event - 1 - 1 + PIN24 + Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + 24 + 24 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - ENDRX - Write '1' to enable interrupt for ENDRX event - 4 - 4 + PIN25 + Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + 25 + 25 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - ACQUIRED - Write '1' to enable interrupt for ACQUIRED event - 10 - 10 + PIN26 + Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + 26 + 26 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Latched + Criteria has been met 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - END - Write '1' to disable interrupt for END event - 1 - 1 + PIN27 + Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + 27 + 27 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Latched + Criteria has been met 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 4 - 4 + PIN28 + Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + 28 + 28 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN29 + Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + 29 + 29 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 - ACQUIRED - Write '1' to disable interrupt for ACQUIRED event - 10 - 10 + PIN30 + Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + 30 + 30 - read - Disabled - Read: Disabled + NotLatched + Criteria has not been met 0 - Enabled - Read: Enabled + Latched + Criteria has been met 1 + + + PIN31 + Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + 31 + 31 - write - Clear - Disable + NotLatched + Criteria has not been met + 0 + + + Latched + Criteria has been met 1 @@ -12452,444 +10722,253 @@ POSSIBILITY OF SUCH DAMAGE.\n - SEMSTAT - Semaphore status register - 0x400 - read-only - 0x00000001 + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode + 0x524 + read-write - SEMSTAT - Semaphore status + DETECTMODE + Select between default DETECT signal behaviour and LDETECT mode 0 - 1 + 0 - Free - Semaphore is free + Default + DETECT directly connected to PIN DETECT signals 0 - CPU - Semaphore is assigned to CPU + LDETECT + Use the latched LDETECT behaviour 1 - - SPIS - Semaphore is assigned to SPI slave - 2 - - - CPUPending - Semaphore is assigned to SPI but a handover to the CPU is pending - 3 - - STATUS - Status from last transaction - 0x440 + 0x20 + 0x4 + PIN_CNF[%s] + Description collection: Configuration of GPIO pins + 0x700 read-write + 0x00000002 - OVERREAD - TX buffer over-read detected, and prevented + DIR + Pin direction. Same physical register as DIR register 0 0 - read - NotPresent - Read: error not present + Input + Configure pin as an input pin 0 - Present - Read: error present + Output + Configure pin as an output pin 1 + + + INPUT + Connect or disconnect input buffer + 1 + 1 - write - Clear - Write: clear error on writing '1' + Connect + Connect input buffer + 0 + + + Disconnect + Disconnect input buffer 1 - OVERFLOW - RX buffer overflow detected, and prevented - 1 - 1 + PULL + Pull configuration + 2 + 3 - read - NotPresent - Read: error not present + Disabled + No pull 0 - Present - Read: error present + Pulldown + Pull down on pin 1 + + Pullup + Pull up on pin + 3 + + + + DRIVE + Drive configuration + 8 + 10 - write - Clear - Write: clear error on writing '1' + S0S1 + Standard '0', standard '1' + 0 + + + H0S1 + High drive '0', standard '1' 1 + + S0H1 + Standard '0', high drive '1' + 2 + + + H0H1 + High drive '0', high 'drive '1'' + 3 + + + D0S1 + Disconnect '0' standard '1' (normally used for wired-or connections) + 4 + + + D0H1 + Disconnect '0', high drive '1' (normally used for wired-or connections) + 5 + + + S0D1 + Standard '0'. disconnect '1' (normally used for wired-and connections) + 6 + + + H0D1 + High drive '0', disconnect '1' (normally used for wired-and connections) + 7 + - - - - ENABLE - Enable SPI slave - 0x500 - read-write - - ENABLE - Enable or disable SPI slave - 0 - 3 + SENSE + Pin sensing mechanism + 16 + 17 Disabled - Disable SPI slave + Disabled 0 - Enabled - Enable SPI slave + High + Sense for high level 2 + + Low + Sense for low level + 3 + - - PSEL - Unspecified - SPIS_PSEL - 0x508 - - SCK - Pin select for SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MISO - Pin select for MISO signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - MOSI - Pin select for MOSI signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - CSN - Pin select for CSN signal - 0x00C - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - Unspecified - SPIS_RXD - 0x534 - - PTR - RXD data pointer - 0x000 - read-write - - - PTR - RXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes received in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes received in the last granted transaction - 0 - 15 - - - - - - TXD - Unspecified - SPIS_TXD - 0x544 - - PTR - TXD data pointer - 0x000 - read-write - - - PTR - TXD data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transmitted in last granted transaction - 0 - 15 - - - - + + + + P1 + GPIO Port 2 + 0x50000300 + P0 + + + RADIO + 2.4 GHz radio + 0x40001000 + + 0 + 0x1000 + registers + + + RADIO + 1 + + RADIO + 0x20 + - CONFIG - Configuration register - 0x554 - read-write + TASKS_TXEN + Enable RADIO in TX mode + 0x000 + write-only - ORDER - Bit order + TASKS_TXEN + Enable RADIO in TX mode 0 0 - MsbFirst - Most significant bit shifted out first - 0 - - - LsbFirst - Least significant bit shifted out first + Trigger + Trigger task 1 + + + + TASKS_RXEN + Enable RADIO in RX mode + 0x004 + write-only + - CPHA - Serial clock (SCK) phase - 1 - 1 + TASKS_RXEN + Enable RADIO in RX mode + 0 + 0 - Leading - Sample on leading edge of clock, shift serial data on trailing edge - 0 - - - Trailing - Sample on trailing edge of clock, shift serial data on leading edge + Trigger + Trigger task 1 + + + + TASKS_START + Start RADIO + 0x008 + write-only + - CPOL - Serial clock (SCK) polarity - 2 - 2 + TASKS_START + Start RADIO + 0 + 0 - ActiveHigh - Active high - 0 - - - ActiveLow - Active low + Trigger + Trigger task 1 @@ -12897,234 +10976,339 @@ POSSIBILITY OF SUCH DAMAGE.\n - DEF - Default character. Character clocked out in case of an ignored transaction. - 0x55C - read-write + TASKS_STOP + Stop RADIO + 0x00C + write-only - DEF - Default character. Character clocked out in case of an ignored transaction. + TASKS_STOP + Stop RADIO 0 - 7 + 0 + + + Trigger + Trigger task + 1 + + - ORC - Over-read character - 0x5C0 - read-write + TASKS_DISABLE + Disable RADIO + 0x010 + write-only - ORC - Over-read character. Character clocked out after an over-read of the transmit buffer. + TASKS_DISABLE + Disable RADIO 0 - 7 + 0 + + + Trigger + Trigger task + 1 + + - - - - TWI0 - I2C compatible Two-Wire Interface 0 - 0x40003000 - SPI0 - TWI - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWI - 0x20 - - TASKS_STARTRX - Start TWI receive sequence - 0x000 + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength + 0x014 write-only - TASKS_STARTRX + TASKS_RSSISTART + Start the RSSI and take one single sample of the receive signal strength 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STARTTX - Start TWI transmit sequence - 0x008 + TASKS_RSSISTOP + Stop the RSSI measurement + 0x018 write-only - TASKS_STARTTX + TASKS_RSSISTOP + Stop the RSSI measurement 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Stop TWI transaction - 0x014 + TASKS_BCSTART + Start the bit counter + 0x01C write-only - TASKS_STOP + TASKS_BCSTART + Start the bit counter 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_SUSPEND - Suspend TWI transaction - 0x01C + TASKS_BCSTOP + Stop the bit counter + 0x020 write-only - TASKS_SUSPEND + TASKS_BCSTOP + Stop the bit counter 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_RESUME - Resume TWI transaction - 0x020 + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode + 0x024 write-only - TASKS_RESUME + TASKS_EDSTART + Start the energy detect measurement used in IEEE 802.15.4 mode 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_STOPPED - TWI stopped - 0x104 - read-write + TASKS_EDSTOP + Stop the energy detect measurement + 0x028 + write-only - EVENTS_STOPPED + TASKS_EDSTOP + Stop the energy detect measurement 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_RXDREADY - TWI RXD byte received - 0x108 - read-write + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode + 0x02C + write-only - EVENTS_RXDREADY + TASKS_CCASTART + Start the clear channel assessment used in IEEE 802.15.4 mode 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_TXDSENT - TWI TXD byte sent - 0x11C - read-write + TASKS_CCASTOP + Stop the clear channel assessment + 0x030 + write-only - EVENTS_TXDSENT + TASKS_CCASTOP + Stop the clear channel assessment 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_ERROR - TWI error - 0x124 + EVENTS_READY + RADIO has ramped up and is ready to be started + 0x100 read-write - EVENTS_ERROR + EVENTS_READY + RADIO has ramped up and is ready to be started 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_BB - TWI byte boundary, generated before each byte that is sent or received - 0x138 + EVENTS_ADDRESS + Address sent or received + 0x104 read-write - EVENTS_BB + EVENTS_ADDRESS + Address sent or received 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_SUSPENDED - TWI entered the suspended state - 0x148 + EVENTS_PAYLOAD + Packet payload sent or received + 0x108 read-write - EVENTS_SUSPENDED + EVENTS_PAYLOAD + Packet payload sent or received 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_END + Packet sent or received + 0x10C read-write - BB_SUSPEND - Shortcut between BB event and SUSPEND task + EVENTS_END + Packet sent or received 0 0 - Disabled - Disable shortcut + NotGenerated + Event not generated 0 - Enabled - Enable shortcut + Generated + Event generated 1 + + + + EVENTS_DISABLED + RADIO has been disabled + 0x110 + read-write + - BB_STOP - Shortcut between BB event and STOP task - 1 - 1 + EVENTS_DISABLED + RADIO has been disabled + 0 + 0 - Disabled - Disable shortcut + NotGenerated + Event not generated 0 - Enabled - Enable shortcut + Generated + Event generated 1 @@ -13132,169 +11316,155 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0x114 read-write - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + EVENTS_DEVMATCH + A device address match occurred on the last received packet + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0x118 + read-write + - RXDREADY - Write '1' to enable interrupt for RXDREADY event - 2 - 2 + EVENTS_DEVMISS + No device address match occurred on the last received packet + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0x11C + read-write + - TXDSENT - Write '1' to enable interrupt for TXDSENT event - 7 - 7 + EVENTS_RSSIEND + Sampling of receive signal strength complete + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_BCMATCH + Bit counter reached bit count value + 0x128 + read-write + - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + EVENTS_BCMATCH + Bit counter reached bit count value + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_CRCOK + Packet received with CRC ok + 0x130 + read-write + - BB - Write '1' to enable interrupt for BB event - 14 - 14 + EVENTS_CRCOK + Packet received with CRC ok + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_CRCERROR + Packet received with CRC error + 0x134 + read-write + - SUSPENDED - Write '1' to enable interrupt for SUSPENDED event - 18 - 18 + EVENTS_CRCERROR + Packet received with CRC error + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 @@ -13302,169 +11472,285 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0x138 read-write - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + EVENTS_FRAMESTART + IEEE 802.15.4 length field received + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0x13C + read-write + - RXDREADY - Write '1' to disable interrupt for RXDREADY event - 2 - 2 + EVENTS_EDEND + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0x140 + read-write + + + EVENTS_EDSTOPPED + The sampling of energy detection has stopped + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0x144 + read-write + - TXDSENT - Write '1' to disable interrupt for TXDSENT event - 7 - 7 + EVENTS_CCAIDLE + Wireless medium in idle - clear to send + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0x148 + read-write + + + EVENTS_CCABUSY + Wireless medium busy - do not send + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_CCASTOPPED + The CCA has stopped + 0x14C + read-write + - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + EVENTS_CCASTOPPED + The CCA has stopped + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0x150 + read-write + + + EVENTS_RATEBOOST + Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0x154 + read-write + - BB - Write '1' to disable interrupt for BB event - 14 - 14 + EVENTS_TXREADY + RADIO has ramped up and is ready to be started TX path + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0x158 + read-write + + + EVENTS_RXREADY + RADIO has ramped up and is ready to be started RX path + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_MHRMATCH + MAC header match found + 0x15C + read-write + - SUSPENDED - Write '1' to disable interrupt for SUSPENDED event - 18 - 18 + EVENTS_MHRMATCH + MAC header match found + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0x16C + read-write + + + EVENTS_PHYEND + Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 @@ -13472,443 +11758,124 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERRORSRC - Error source - 0x4C4 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - oneToClear - OVERRUN - Overrun error + READY_START + Shortcut between event READY and task START 0 0 - read - NotPresent - Read: no overrun occured + Disabled + Disable shortcut 0 - Present - Read: overrun occured + Enabled + Enable shortcut 1 - ANACK - NACK received after sending the address (write '1' to clear) + END_DISABLE + Shortcut between event END and task DISABLE 1 1 - read - NotPresent - Read: error not present + Disabled + Disable shortcut 0 - Present - Read: error present + Enabled + Enable shortcut 1 - DNACK - NACK received after sending a data byte (write '1' to clear) + DISABLED_TXEN + Shortcut between event DISABLED and task TXEN 2 2 - read - NotPresent - Read: error not present + Disabled + Disable shortcut 0 - Present - Read: error present + Enabled + Enable shortcut 1 - - - - ENABLE - Enable TWI - 0x500 - read-write - - ENABLE - Enable or disable TWI - 0 + DISABLED_RXEN + Shortcut between event DISABLED and task RXEN + 3 3 Disabled - Disable TWI + Disable shortcut 0 Enabled - Enable TWI - 5 + Enable shortcut + 1 - - - - PSEL - Unspecified - TWI_PSEL - 0x508 - - SCL - Pin select for SCL - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD register - 0x518 - read-only - modifyExternal - - - RXD - RXD register - 0 - 7 - - - - - TXD - TXD register - 0x51C - read-write - - - TXD - TXD register - 0 - 7 - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - TWI master clock frequency - 0 - 31 + ADDRESS_RSSISTART + Shortcut between event ADDRESS and task RSSISTART + 4 + 4 - K100 - 100 kbps - 0x01980000 + Disabled + Disable shortcut + 0 - K250 - 250 kbps - 0x04000000 + Enabled + Enable shortcut + 1 + + + + + END_START + Shortcut between event END and task START + 5 + 5 + + + Disabled + Disable shortcut + 0 - K400 - 400 kbps (actual rate 410.256 kbps) - 0x06680000 + Enabled + Enable shortcut + 1 - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - ADDRESS - Address used in the TWI transfer - 0 + ADDRESS_BCSTART + Shortcut between event ADDRESS and task BCSTART + 6 6 - - - - - - - TWIM0 - I2C compatible Two-Wire Master Interface with EasyDMA 0 - 0x40003000 - SPI0 - TWIM - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWIM - 0x20 - - - TASKS_STARTRX - Start TWI receive sequence - 0x000 - write-only - - - TASKS_STARTRX - 0 - 0 - - - - - TASKS_STARTTX - Start TWI transmit sequence - 0x008 - write-only - - - TASKS_STARTTX - 0 - 0 - - - - - TASKS_STOP - Stop TWI transaction. Must be issued while the TWI master is not suspended. - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. - 0x148 - read-write - - - EVENTS_SUSPENDED - 0 - 0 - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_LASTRX - Byte boundary, starting to receive the last byte - 0x15C - read-write - - - EVENTS_LASTRX - 0 - 0 - - - - - EVENTS_LASTTX - Byte boundary, starting to transmit the last byte - 0x160 - read-write - - - EVENTS_LASTTX - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - LASTTX_STARTRX - Shortcut between LASTTX event and STARTRX task - 7 - 7 Disabled @@ -13923,8 +11890,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTTX_SUSPEND - Shortcut between LASTTX event and SUSPEND task + DISABLED_RSSISTOP + Shortcut between event DISABLED and task RSSISTOP 8 8 @@ -13941,10 +11908,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTTX_STOP - Shortcut between LASTTX event and STOP task - 9 - 9 + RXREADY_CCASTART + Shortcut between event RXREADY and task CCASTART + 11 + 11 Disabled @@ -13959,10 +11926,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTRX_STARTTX - Shortcut between LASTRX event and STARTTX task - 10 - 10 + CCAIDLE_TXEN + Shortcut between event CCAIDLE and task TXEN + 12 + 12 Disabled @@ -13977,10 +11944,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTRX_SUSPEND - Shortcut between LASTRX event and SUSPEND task - 11 - 11 + CCABUSY_DISABLE + Shortcut between event CCABUSY and task DISABLE + 13 + 13 Disabled @@ -13995,10 +11962,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTRX_STOP - Shortcut between LASTRX event and STOP task - 12 - 12 + FRAMESTART_BCSTART + Shortcut between event FRAMESTART and task BCSTART + 14 + 14 Disabled @@ -14012,136 +11979,128 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + READY_EDSTART + Shortcut between event READY and task EDSTART + 15 + 15 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + EDEND_DISABLE + Shortcut between event EDEND and task DISABLE + 16 + 16 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - SUSPENDED - Enable or disable interrupt for SUSPENDED event - 18 - 18 + CCAIDLE_STOP + Shortcut between event CCAIDLE and task STOP + 17 + 17 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + TXREADY_START + Shortcut between event TXREADY and task START + 18 + 18 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + RXREADY_START + Shortcut between event RXREADY and task START + 19 + 19 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - LASTRX - Enable or disable interrupt for LASTRX event - 23 - 23 + PHYEND_DISABLE + Shortcut between event PHYEND and task DISABLE + 20 + 20 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - LASTTX - Enable or disable interrupt for LASTTX event - 24 - 24 + PHYEND_START + Shortcut between event PHYEND and task START + 21 + 21 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 @@ -14155,10 +12114,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + READY + Write '1' to enable interrupt for event READY + 0 + 0 read @@ -14182,10 +12141,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + ADDRESS + Write '1' to enable interrupt for event ADDRESS + 1 + 1 read @@ -14209,10 +12168,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SUSPENDED - Write '1' to enable interrupt for SUSPENDED event - 18 - 18 + PAYLOAD + Write '1' to enable interrupt for event PAYLOAD + 2 + 2 read @@ -14236,10 +12195,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + END + Write '1' to enable interrupt for event END + 3 + 3 read @@ -14263,10 +12222,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + DISABLED + Write '1' to enable interrupt for event DISABLED + 4 + 4 read @@ -14290,10 +12249,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTRX - Write '1' to enable interrupt for LASTRX event - 23 - 23 + DEVMATCH + Write '1' to enable interrupt for event DEVMATCH + 5 + 5 read @@ -14317,10 +12276,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - LASTTX - Write '1' to enable interrupt for LASTTX event - 24 - 24 + DEVMISS + Write '1' to enable interrupt for event DEVMISS + 6 + 6 read @@ -14343,19 +12302,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + RSSIEND + Write '1' to enable interrupt for event RSSIEND + 7 + 7 read @@ -14372,17 +12323,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + BCMATCH + Write '1' to enable interrupt for event BCMATCH + 10 + 10 read @@ -14399,15 +12350,177 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - SUSPENDED - Write '1' to disable interrupt for SUSPENDED event + CRCOK + Write '1' to enable interrupt for event CRCOK + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CRCERROR + Write '1' to enable interrupt for event CRCERROR + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + FRAMESTART + Write '1' to enable interrupt for event FRAMESTART + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDEND + Write '1' to enable interrupt for event EDEND + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + EDSTOPPED + Write '1' to enable interrupt for event EDSTOPPED + 16 + 16 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCAIDLE + Write '1' to enable interrupt for event CCAIDLE + 17 + 17 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CCABUSY + Write '1' to enable interrupt for event CCABUSY 18 18 @@ -14426,15 +12539,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event + CCASTOPPED + Write '1' to enable interrupt for event CCASTOPPED 19 19 @@ -14453,15 +12566,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event + RATEBOOST + Write '1' to enable interrupt for event RATEBOOST 20 20 @@ -14480,15 +12593,69 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - LASTRX - Write '1' to disable interrupt for LASTRX event + TXREADY + Write '1' to enable interrupt for event TXREADY + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + RXREADY + Write '1' to enable interrupt for event RXREADY + 22 + 22 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + MHRMATCH + Write '1' to enable interrupt for event MHRMATCH 23 23 @@ -14507,17 +12674,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - LASTTX - Write '1' to disable interrupt for LASTTX event - 24 - 24 + PHYEND + Write '1' to enable interrupt for event PHYEND + 27 + 27 read @@ -14534,8 +12701,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 @@ -14543,706 +12710,259 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERRORSRC - Error source - 0x4C4 + INTENCLR + Disable interrupt + 0x308 read-write - oneToClear - OVERRUN - Overrun error + READY + Write '1' to disable interrupt for event READY 0 0 + read - NotReceived - Error did not occur + Disabled + Read: Disabled 0 - Received - Error occurred + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - ANACK - NACK received after sending the address (write '1' to clear) + ADDRESS + Write '1' to disable interrupt for event ADDRESS 1 1 + read - NotReceived - Error did not occur + Disabled + Read: Disabled 0 - Received - Error occurred + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - DNACK - NACK received after sending a data byte (write '1' to clear) + PAYLOAD + Write '1' to disable interrupt for event PAYLOAD 2 2 + read - NotReceived - Error did not occur + Disabled + Read: Disabled 0 - Received - Error occurred + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ENABLE - Enable TWIM - 0x500 - read-write - - ENABLE - Enable or disable TWIM - 0 + END + Write '1' to disable interrupt for event END + 3 3 + read Disabled - Disable TWIM + Read: Disabled 0 Enabled - Enable TWIM - 6 + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 - - - - PSEL - Unspecified - TWIM_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - FREQUENCY - TWI frequency. Accuracy depends on the HFCLK source selected. - 0x524 - read-write - 0x04000000 - - FREQUENCY - TWI master clock frequency - 0 - 31 + DISABLED + Write '1' to disable interrupt for event DISABLED + 4 + 4 + read - K100 - 100 kbps - 0x01980000 + Disabled + Read: Disabled + 0 - K250 - 250 kbps - 0x04000000 + Enabled + Read: Enabled + 1 + + + write - K400 - 400 kbps - 0x06400000 + Clear + Disable + 1 - - - - RXD - RXD EasyDMA channel - TWIM_RXD - 0x534 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in receive buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in receive buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - TXD - TXD EasyDMA channel - TWIM_TXD - 0x544 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in transmit buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in transmit buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. - 0 - 15 - - - - - LIST - EasyDMA list type - 0x00C - read-write - - - LIST - List type - 0 - 2 - - - Disabled - Disable EasyDMA list - 0 - - - ArrayList - Use array list - 1 - - - - - - - - ADDRESS - Address used in the TWI transfer - 0x588 - read-write - - - ADDRESS - Address used in the TWI transfer - 0 - 6 - - - - - - - TWIS0 - I2C compatible Two-Wire Slave Interface with EasyDMA 0 - 0x40003000 - SPI0 - TWIS - - 0 - 0x1000 - registers - - - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 - 3 - - TWIS - 0x20 - - - TASKS_STOP - Stop TWI transaction - 0x014 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SUSPEND - Suspend TWI transaction - 0x01C - write-only - - - TASKS_SUSPEND - 0 - 0 - - - - - TASKS_RESUME - Resume TWI transaction - 0x020 - write-only - - - TASKS_RESUME - 0 - 0 - - - - - TASKS_PREPARERX - Prepare the TWI slave to respond to a write command - 0x030 - write-only - - - TASKS_PREPARERX - 0 - 0 - - - - - TASKS_PREPARETX - Prepare the TWI slave to respond to a read command - 0x034 - write-only - - - TASKS_PREPARETX - 0 - 0 - - - - - EVENTS_STOPPED - TWI stopped - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - EVENTS_ERROR - TWI error - 0x124 - read-write - - - EVENTS_ERROR - 0 - 0 - - - - - EVENTS_RXSTARTED - Receive sequence started - 0x14C - read-write - - - EVENTS_RXSTARTED - 0 - 0 - - - - - EVENTS_TXSTARTED - Transmit sequence started - 0x150 - read-write - - - EVENTS_TXSTARTED - 0 - 0 - - - - - EVENTS_WRITE - Write command received - 0x164 - read-write - - - EVENTS_WRITE - 0 - 0 - - - - - EVENTS_READ - Read command received - 0x168 - read-write - - - EVENTS_READ - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - WRITE_SUSPEND - Shortcut between WRITE event and SUSPEND task - 13 - 13 + DEVMATCH + Write '1' to disable interrupt for event DEVMATCH + 5 + 5 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - READ_SUSPEND - Shortcut between READ event and SUSPEND task - 14 - 14 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + DEVMISS + Write '1' to disable interrupt for event DEVMISS + 6 + 6 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - ERROR - Enable or disable interrupt for ERROR event - 9 - 9 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - RXSTARTED - Enable or disable interrupt for RXSTARTED event - 19 - 19 + RSSIEND + Write '1' to disable interrupt for event RSSIEND + 7 + 7 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - TXSTARTED - Enable or disable interrupt for TXSTARTED event - 20 - 20 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - WRITE - Enable or disable interrupt for WRITE event - 25 - 25 + BCMATCH + Write '1' to disable interrupt for event BCMATCH + 10 + 10 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - READ - Enable or disable interrupt for READ event - 26 - 26 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + CRCOK + Write '1' to disable interrupt for event CRCOK + 12 + 12 read @@ -15259,17 +12979,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - ERROR - Write '1' to enable interrupt for ERROR event - 9 - 9 + CRCERROR + Write '1' to disable interrupt for event CRCERROR + 13 + 13 read @@ -15286,17 +13006,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - RXSTARTED - Write '1' to enable interrupt for RXSTARTED event - 19 - 19 + FRAMESTART + Write '1' to disable interrupt for event FRAMESTART + 14 + 14 read @@ -15313,17 +13033,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - TXSTARTED - Write '1' to enable interrupt for TXSTARTED event - 20 - 20 + EDEND + Write '1' to disable interrupt for event EDEND + 15 + 15 read @@ -15340,17 +13060,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - WRITE - Write '1' to enable interrupt for WRITE event - 25 - 25 + EDSTOPPED + Write '1' to disable interrupt for event EDSTOPPED + 16 + 16 read @@ -15367,17 +13087,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - READ - Write '1' to enable interrupt for READ event - 26 - 26 + CCAIDLE + Write '1' to disable interrupt for event CCAIDLE + 17 + 17 read @@ -15394,25 +13114,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + CCABUSY + Write '1' to disable interrupt for event CCABUSY + 18 + 18 read @@ -15436,10 +13148,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERROR - Write '1' to disable interrupt for ERROR event - 9 - 9 + CCASTOPPED + Write '1' to disable interrupt for event CCASTOPPED + 19 + 19 read @@ -15463,10 +13175,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - RXSTARTED - Write '1' to disable interrupt for RXSTARTED event - 19 - 19 + RATEBOOST + Write '1' to disable interrupt for event RATEBOOST + 20 + 20 read @@ -15490,10 +13202,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXSTARTED - Write '1' to disable interrupt for TXSTARTED event - 20 - 20 + TXREADY + Write '1' to disable interrupt for event TXREADY + 21 + 21 read @@ -15517,10 +13229,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - WRITE - Write '1' to disable interrupt for WRITE event - 25 - 25 + RXREADY + Write '1' to disable interrupt for event RXREADY + 22 + 22 read @@ -15544,10 +13256,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - READ - Write '1' to disable interrupt for READ event - 26 - 26 + MHRMATCH + Write '1' to disable interrupt for event MHRMATCH + 23 + 23 read @@ -15570,65 +13282,55 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - ERRORSRC - Error source - 0x4D0 - read-write - oneToClear - - OVERFLOW - RX buffer overflow detected, and prevented - 0 - 0 + PHYEND + Write '1' to disable interrupt for event PHYEND + 27 + 27 + read - NotDetected - Error did not occur + Disabled + Read: Disabled 0 - Detected - Error occurred + Enabled + Read: Enabled 1 - - - DNACK - NACK sent after receiving a data byte - 2 - 2 + write - NotReceived - Error did not occur - 0 - - - Received - Error occurred + Clear + Disable 1 + + + + CRCSTATUS + CRC status + 0x400 + read-only + - OVERREAD - TX buffer over-read detected, and prevented - 3 - 3 + CRCSTATUS + CRC status of packet received + 0 + 0 - NotDetected - Error did not occur + CRCError + Packet received with CRC error 0 - Detected - Error occurred + CRCOk + Packet received with CRC ok 1 @@ -15636,280 +13338,85 @@ POSSIBILITY OF SUCH DAMAGE.\n - MATCH - Status register indicating which address had a match - 0x4D4 + RXMATCH + Received address + 0x408 read-only - MATCH - Which of the addresses in {ADDRESS} matched the incoming address + RXMATCH + Received address 0 - 0 + 2 - ENABLE - Enable TWIS - 0x500 - read-write + RXCRC + CRC field of previously received packet + 0x40C + read-only - ENABLE - Enable or disable TWIS + RXCRC + CRC field of previously received packet 0 - 3 - - - Disabled - Disable TWIS - 0 - - - Enabled - Enable TWIS - 9 - - + 23 - - PSEL - Unspecified - TWIS_PSEL - 0x508 - - SCL - Pin select for SCL signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - SDA - Pin select for SDA signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - RXD - RXD EasyDMA channel - TWIS_RXD - 0x534 - - PTR - RXD Data pointer - 0x000 - read-write - - - PTR - RXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in RXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in RXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last RXD transaction - 0 - 15 - - - - - - TXD - TXD EasyDMA channel - TWIS_TXD - 0x544 - - PTR - TXD Data pointer - 0x000 - read-write - - - PTR - TXD Data pointer - 0 - 31 - - - - - MAXCNT - Maximum number of bytes in TXD buffer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes in TXD buffer - 0 - 15 - - - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last TXD transaction - 0 - 15 - - - - - 0x2 - 0x4 - ADDRESS[%s] - Description collection[n]: TWI slave address n - 0x588 - read-write + DAI + Device address match index + 0x410 + read-only - ADDRESS - TWI slave address + DAI + Device address match index 0 - 6 + 2 - CONFIG - Configuration register for the address match mechanism - 0x594 - read-write - 0x00000001 + PDUSTAT + Payload status + 0x414 + read-only - ADDRESS0 - Enable or disable address matching on ADDRESS[0] + PDUSTAT + Status on payload length vs. PCNF1.MAXLEN 0 0 - Disabled - Disabled + LessThan + Payload less than PCNF1.MAXLEN 0 - Enabled - Enabled + GreaterThan + Payload greater than PCNF1.MAXLEN 1 - ADDRESS1 - Enable or disable address matching on ADDRESS[1] + CISTAT + Status on what rate packet is received with in Long Range 1 - 1 + 2 - Disabled - Disabled + LR125kbit + Frame is received at 125kbps 0 - Enabled - Enabled + LR500kbit + Frame is received at 500kbps 1 @@ -15917,455 +13424,529 @@ POSSIBILITY OF SUCH DAMAGE.\n - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0x5C0 + PACKETPTR + Packet pointer + 0x504 read-write - ORC - Over-read character. Character sent out in case of an over-read of the transmit buffer. - 0 - 7 - - - - - - - SPI1 - Serial Peripheral Interface 1 - 0x40004000 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - SPIM1 - Serial Peripheral Interface Master with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - SPIS1 - SPI Slave 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWI1 - I2C compatible Two-Wire Interface 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIM1 - I2C compatible Two-Wire Master Interface with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - TWIS1 - I2C compatible Two-Wire Slave Interface with EasyDMA 1 - 0x40004000 - SPI1 - - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 - 4 - - - - NFCT - NFC-A compatible radio - 0x40005000 - - 0 - 0x1000 - registers - - - NFCT - 5 - - NFCT - 0x20 - - - TASKS_ACTIVATE - Activate NFCT peripheral for incoming and outgoing frames, change state to activated - 0x000 - write-only - - - TASKS_ACTIVATE - 0 - 0 - - - - - TASKS_DISABLE - Disable NFCT peripheral - 0x004 - write-only - - - TASKS_DISABLE + PACKETPTR + Packet pointer 0 - 0 + 31 - TASKS_SENSE - Enable NFC sense field mode, change state to sense mode - 0x008 - write-only + FREQUENCY + Frequency + 0x508 + read-write + 0x00000002 - TASKS_SENSE + FREQUENCY + Radio channel frequency 0 - 0 + 6 - - - - TASKS_STARTTX - Start transmission of an outgoing frame, change state to transmit - 0x00C - write-only - - TASKS_STARTTX - 0 - 0 + MAP + Channel map selection. + 8 + 8 + + + Default + Channel map between 2400 MHZ .. 2500 MHz + 0 + + + Low + Channel map between 2360 MHZ .. 2460 MHz + 1 + + - TASKS_ENABLERXDATA - Initializes the EasyDMA for receive. - 0x01C - write-only + TXPOWER + Output power + 0x50C + read-write - TASKS_ENABLERXDATA + TXPOWER + RADIO output power 0 - 0 - - - - - TASKS_GOIDLE - Force state machine to IDLE state - 0x024 - write-only - - - TASKS_GOIDLE - 0 - 0 + 7 + + + Pos8dBm + +8 dBm + 0x8 + + + Pos7dBm + +7 dBm + 0x7 + + + Pos6dBm + +6 dBm + 0x6 + + + Pos5dBm + +5 dBm + 0x5 + + + Pos4dBm + +4 dBm + 0x4 + + + Pos3dBm + +3 dBm + 0x3 + + + Pos2dBm + +2 dBm + 0x2 + + + 0dBm + 0 dBm + 0x0 + + + Neg4dBm + -4 dBm + 0xFC + + + Neg8dBm + -8 dBm + 0xF8 + + + Neg12dBm + -12 dBm + 0xF4 + + + Neg16dBm + -16 dBm + 0xF0 + + + Neg20dBm + -20 dBm + 0xEC + + + Neg30dBm + Deprecated enumerator - -40 dBm + 0xE2 + + + Neg40dBm + -40 dBm + 0xD8 + + - TASKS_GOSLEEP - Force state machine to SLEEP_A state - 0x028 - write-only + MODE + Data rate and modulation + 0x510 + read-write - TASKS_GOSLEEP + MODE + Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 - 0 + 3 + + + Nrf_1Mbit + 1 Mbit/s Nordic proprietary radio mode + 0 + + + Nrf_2Mbit + 2 Mbit/s Nordic proprietary radio mode + 1 + + + Ble_1Mbit + 1 Mbit/s BLE + 3 + + + Ble_2Mbit + 2 Mbit/s BLE + 4 + + + Ble_LR125Kbit + Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 5 + + + Ble_LR500Kbit + Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX + 6 + + + Ieee802154_250Kbit + IEEE 802.15.4-2006 250 kbit/s + 15 + + - EVENTS_READY - The NFCT peripheral is ready to receive and send frames - 0x100 + PCNF0 + Packet configuration register 0 + 0x514 read-write - EVENTS_READY + LFLEN + Length on air of LENGTH field in number of bits. 0 - 0 + 3 - - - - EVENTS_FIELDDETECTED - Remote NFC field detected - 0x104 - read-write - - EVENTS_FIELDDETECTED - 0 - 0 + S0LEN + Length on air of S0 field in number of bytes. + 8 + 8 - - - - EVENTS_FIELDLOST - Remote NFC field lost - 0x108 - read-write - - EVENTS_FIELDLOST - 0 - 0 + S1LEN + Length on air of S1 field in number of bits. + 16 + 19 - - - - EVENTS_TXFRAMESTART - Marks the start of the first symbol of a transmitted frame - 0x10C - read-write - - EVENTS_TXFRAMESTART - 0 - 0 + S1INCL + Include or exclude S1 field in RAM + 20 + 20 + + + Automatic + Include S1 field in RAM only if S1LEN &gt; 0 + 0 + + + Include + Always include S1 field in RAM independent of S1LEN + 1 + + - - - - EVENTS_TXFRAMEEND - Marks the end of the last transmitted on-air symbol of a frame - 0x110 - read-write - - EVENTS_TXFRAMEEND - 0 - 0 + CILEN + Length of code indicator - long range + 22 + 23 - - - - EVENTS_RXFRAMESTART - Marks the end of the first symbol of a received frame - 0x114 - read-write - - EVENTS_RXFRAMESTART - 0 - 0 + PLEN + Length of preamble on air. Decision point: TASKS_START task + 24 + 25 + + + 8bit + 8-bit preamble + 0 + + + 16bit + 16-bit preamble + 1 + + + 32bitZero + 32-bit zero preamble - used for IEEE 802.15.4 + 2 + + + LongRange + Preamble - used for BLE long range + 3 + + - - - - EVENTS_RXFRAMEEND - Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer - 0x118 - read-write - - EVENTS_RXFRAMEEND - 0 - 0 + CRCINC + Indicates if LENGTH field contains CRC or not + 26 + 26 + + + Exclude + LENGTH does not contain CRC + 0 + + + Include + LENGTH includes CRC + 1 + + - - - - EVENTS_ERROR - NFC error reported. The ERRORSTATUS register contains details on the source of the error. - 0x11C - read-write - - EVENTS_ERROR - 0 - 0 + TERMLEN + Length of TERM field in Long Range operation + 29 + 30 - EVENTS_RXERROR - NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. - 0x128 + PCNF1 + Packet configuration register 1 + 0x518 read-write - EVENTS_RXERROR + MAXLEN + Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. 0 - 0 + 7 - - - - EVENTS_ENDRX - RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. - 0x12C - read-write - - EVENTS_ENDRX - 0 - 0 + STATLEN + Static length in number of bytes + 8 + 15 + + + BALEN + Base address length in number of bytes + 16 + 18 + + + ENDIAN + On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. + 24 + 24 + + + Little + Least significant bit on air first + 0 + + + Big + Most significant bit on air first + 1 + + + + + WHITEEN + Enable or disable packet whitening + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - EVENTS_ENDTX - Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer - 0x130 + BASE0 + Base address 0 + 0x51C read-write - EVENTS_ENDTX + BASE0 + Base address 0 0 - 0 + 31 - EVENTS_AUTOCOLRESSTARTED - Auto collision resolution process has started - 0x138 + BASE1 + Base address 1 + 0x520 read-write - EVENTS_AUTOCOLRESSTARTED + BASE1 + Base address 1 0 - 0 + 31 - EVENTS_COLLISION - NFC auto collision resolution error reported. - 0x148 + PREFIX0 + Prefixes bytes for logical addresses 0-3 + 0x524 read-write - EVENTS_COLLISION + AP0 + Address prefix 0. 0 - 0 + 7 + + + AP1 + Address prefix 1. + 8 + 15 + + + AP2 + Address prefix 2. + 16 + 23 + + + AP3 + Address prefix 3. + 24 + 31 - EVENTS_SELECTED - NFC auto collision resolution successfully completed - 0x14C + PREFIX1 + Prefixes bytes for logical addresses 4-7 + 0x528 read-write - EVENTS_SELECTED + AP4 + Address prefix 4. 0 - 0 + 7 + + + AP5 + Address prefix 5. + 8 + 15 + + + AP6 + Address prefix 6. + 16 + 23 + + + AP7 + Address prefix 7. + 24 + 31 - EVENTS_STARTED - EasyDMA is ready to receive or send frames. - 0x150 + TXADDRESS + Transmit address select + 0x52C read-write - EVENTS_STARTED + TXADDRESS + Transmit address select 0 - 0 + 2 - SHORTS - Shortcut register - 0x200 + RXADDRESSES + Receive address select + 0x530 read-write - FIELDDETECTED_ACTIVATE - Shortcut between FIELDDETECTED event and ACTIVATE task + ADDR0 + Enable or disable reception on logical address 0. 0 0 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - FIELDLOST_SENSE - Shortcut between FIELDLOST event and SENSE task + ADDR1 + Enable or disable reception on logical address 1. 1 1 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - TXFRAMEEND_ENABLERXDATA - Shortcut between TXFRAMEEND event and ENABLERXDATA task - 5 - 5 + ADDR2 + Enable or disable reception on logical address 2. + 2 + 2 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - READY - Enable or disable interrupt for READY event - 0 - 0 + ADDR3 + Enable or disable reception on logical address 3. + 3 + 3 Disabled @@ -16380,10 +13961,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - FIELDDETECTED - Enable or disable interrupt for FIELDDETECTED event - 1 - 1 + ADDR4 + Enable or disable reception on logical address 4. + 4 + 4 Disabled @@ -16398,62 +13979,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - FIELDLOST - Enable or disable interrupt for FIELDLOST event - 2 - 2 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMESTART - Enable or disable interrupt for TXFRAMESTART event - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TXFRAMEEND - Enable or disable interrupt for TXFRAMEEND event - 4 - 4 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - RXFRAMESTART - Enable or disable interrupt for RXFRAMESTART event + ADDR5 + Enable or disable reception on logical address 5. 5 5 @@ -16470,8 +13997,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - RXFRAMEEND - Enable or disable interrupt for RXFRAMEEND event + ADDR6 + Enable or disable reception on logical address 6. 6 6 @@ -16488,8 +14015,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERROR - Enable or disable interrupt for ERROR event + ADDR7 + Enable or disable reception on logical address 7. 7 7 @@ -16505,541 +14032,774 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + CRCCNF + CRC configuration + 0x534 + read-write + - RXERROR - Enable or disable interrupt for RXERROR event - 10 - 10 + LEN + CRC length in number of bytes. + 0 + 1 Disabled - Disable + CRC length is zero and CRC calculation is disabled 0 - Enabled - Enable + One + CRC length is one byte and CRC calculation is enabled 1 - - - - ENDRX - Enable or disable interrupt for ENDRX event - 11 - 11 - - Disabled - Disable - 0 + Two + CRC length is two bytes and CRC calculation is enabled + 2 - Enabled - Enable - 1 + Three + CRC length is three bytes and CRC calculation is enabled + 3 - ENDTX - Enable or disable interrupt for ENDTX event - 12 - 12 + SKIPADDR + Include or exclude packet address field out of CRC calculation. + 8 + 9 - Disabled - Disable + Include + CRC calculation includes address field 0 - Enabled - Enable + Skip + CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. 1 + + Ieee802154 + CRC calculation as per 802.15.4 standard. Starting at first byte after length field. + 2 + + + + + CRCPOLY + CRC polynomial + 0x538 + read-write + 0x00000000 + - AUTOCOLRESSTARTED - Enable or disable interrupt for AUTOCOLRESSTARTED event - 14 - 14 + CRCPOLY + CRC polynomial + 0 + 23 + + + + + CRCINIT + CRC initial value + 0x53C + read-write + + + CRCINIT + CRC initial value + 0 + 23 + + + + + TIFS + Interframe spacing in us + 0x544 + read-write + + + TIFS + Interframe spacing in us + 0 + 9 + + + + + RSSISAMPLE + RSSI sample + 0x548 + read-only + + + RSSISAMPLE + RSSI sample + 0 + 6 + + + + + STATE + Current radio state + 0x550 + read-only + + + STATE + Current radio state + 0 + 3 Disabled - Disable + RADIO is in the Disabled state 0 - Enabled - Enable + RxRu + RADIO is in the RXRU state 1 - - - - COLLISION - Enable or disable interrupt for COLLISION event - 18 - 18 - - Disabled - Disable - 0 + RxIdle + RADIO is in the RXIDLE state + 2 - Enabled - Enable - 1 + Rx + RADIO is in the RX state + 3 - - - - SELECTED - Enable or disable interrupt for SELECTED event - 19 - 19 - - Disabled - Disable - 0 + RxDisable + RADIO is in the RXDISABLED state + 4 - Enabled - Enable - 1 + TxRu + RADIO is in the TXRU state + 9 - - - - STARTED - Enable or disable interrupt for STARTED event - 20 - 20 - - Disabled - Disable - 0 + TxIdle + RADIO is in the TXIDLE state + 10 - Enabled - Enable - 1 + Tx + RADIO is in the TX state + 11 + + + TxDisable + RADIO is in the TXDISABLED state + 12 - INTENSET - Enable interrupt - 0x304 + DATAWHITEIV + Data whitening initial value + 0x554 read-write + 0x00000040 - READY - Write '1' to enable interrupt for READY event + DATAWHITEIV + Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. + 0 + 6 + + + + + BCC + Bit counter compare + 0x560 + read-write + + + BCC + Bit counter compare + 0 + 31 + + + + + 0x8 + 0x4 + DAB[%s] + Description collection: Device address base segment n + 0x600 + read-write + + + DAB + Device address base segment n + 0 + 31 + + + + + 0x8 + 0x4 + DAP[%s] + Description collection: Device address prefix n + 0x620 + read-write + + + DAP + Device address prefix n + 0 + 15 + + + + + DACNF + Device address match configuration + 0x640 + read-write + + + ENA0 + Enable or disable device address matching using device address 0 0 0 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - FIELDDETECTED - Write '1' to enable interrupt for FIELDDETECTED event + ENA1 + Enable or disable device address matching using device address 1 1 1 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - FIELDLOST - Write '1' to enable interrupt for FIELDLOST event + ENA2 + Enable or disable device address matching using device address 2 2 2 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - TXFRAMESTART - Write '1' to enable interrupt for TXFRAMESTART event + ENA3 + Enable or disable device address matching using device address 3 3 3 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - TXFRAMEEND - Write '1' to enable interrupt for TXFRAMEEND event + ENA4 + Enable or disable device address matching using device address 4 4 4 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - RXFRAMESTART - Write '1' to enable interrupt for RXFRAMESTART event + ENA5 + Enable or disable device address matching using device address 5 5 5 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - RXFRAMEEND - Write '1' to enable interrupt for RXFRAMEEND event + ENA6 + Enable or disable device address matching using device address 6 6 6 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - ERROR - Write '1' to enable interrupt for ERROR event + ENA7 + Enable or disable device address matching using device address 7 7 7 - read Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enabled 1 - RXERROR - Write '1' to enable interrupt for RXERROR event + TXADD0 + TxAdd for device address 0 + 8 + 8 + + + TXADD1 + TxAdd for device address 1 + 9 + 9 + + + TXADD2 + TxAdd for device address 2 10 10 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - ENDRX - Write '1' to enable interrupt for ENDRX event + TXADD3 + TxAdd for device address 3 11 11 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - ENDTX - Write '1' to enable interrupt for ENDTX event + TXADD4 + TxAdd for device address 4 12 12 - - read + + + TXADD5 + TxAdd for device address 5 + 13 + 13 + + + TXADD6 + TxAdd for device address 6 + 14 + 14 + + + TXADD7 + TxAdd for device address 7 + 15 + 15 + + + + + MHRMATCHCONF + Search pattern configuration + 0x644 + read-write + + + MHRMATCHCONF + Search pattern configuration + 0 + 31 + + + + + MHRMATCHMAS + Pattern mask + 0x648 + read-write + + + MHRMATCHMAS + Pattern mask + 0 + 31 + + + + + MODECNF0 + Radio mode configuration register 0 + 0x650 + read-write + 0x00000200 + + + RU + Radio ramp-up time + 0 + 0 + - Disabled - Read: Disabled + Default + Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 0 - Enabled - Read: Enabled + Fast + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information 1 + + + DTX + Default TX value + 8 + 9 - write - Set - Enable + B1 + Transmit '1' + 0 + + + B0 + Transmit '0' 1 + + Center + Transmit center frequency + 2 + + + + + SFD + IEEE 802.15.4 start of frame delimiter + 0x660 + read-write + 0x000000A7 + - AUTOCOLRESSTARTED - Write '1' to enable interrupt for AUTOCOLRESSTARTED event - 14 - 14 + SFD + IEEE 802.15.4 start of frame delimiter + 0 + 7 + + + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0x664 + read-write + 0x00000000 + + + EDCNT + IEEE 802.15.4 energy detect loop count + 0 + 20 + + + + + EDSAMPLE + IEEE 802.15.4 energy detect level + 0x668 + read-write + 0x00000000 + + + EDLVL + IEEE 802.15.4 energy detect level + 0 + 7 + + + + + CCACTRL + IEEE 802.15.4 clear channel assessment control + 0x66C + read-write + 0x052D0000 + + + CCAMODE + CCA mode of operation + 0 + 2 - read - Disabled - Read: Disabled + EdMode + Energy above threshold 0 - Enabled - Read: Enabled + CarrierMode + Carrier seen 1 - - - write - Set - Enable - 1 + CarrierAndEdMode + Energy above threshold AND carrier seen + 2 + + + CarrierOrEdMode + Energy above threshold OR carrier seen + 3 + + + EdModeTest1 + Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. + 4 - COLLISION - Write '1' to enable interrupt for COLLISION event - 18 - 18 + CCAEDTHRES + CCA energy busy threshold. Used in all the CCA modes except CarrierMode. + 8 + 15 + + + CCACORRTHRES + CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. + 16 + 23 + + + CCACORRCNT + Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. + 24 + 31 + + + + + POWER + Peripheral power control + 0xFFC + read-write + 0x00000001 + + + POWER + Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. + 0 + 0 - read Disabled - Read: Disabled + Peripheral is powered off 0 Enabled - Read: Enabled + Peripheral is powered on 1 + + + + + + + UART0 + Universal Asynchronous Receiver/Transmitter + 0x40002000 + UART + + 0 + 0x1000 + registers + + + UARTE0_UART0 + 2 + + UART + 0x20 + + + TASKS_STARTRX + Start UART receiver + 0x000 + write-only + + + TASKS_STARTRX + Start UART receiver + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_STOPRX + Stop UART receiver + 0x004 + write-only + - SELECTED - Write '1' to enable interrupt for SELECTED event - 19 - 19 + TASKS_STOPRX + Stop UART receiver + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_STARTTX + Start UART transmitter + 0x008 + write-only + + + TASKS_STARTTX + Start UART transmitter + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only + - STARTED - Write '1' to enable interrupt for STARTED event - 20 - 20 + TASKS_STOPTX + Stop UART transmitter + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_SUSPEND + Suspend UART + 0x01C + write-only + + + TASKS_SUSPEND + Suspend UART + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 @@ -17047,124 +14807,216 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 read-write - READY - Write '1' to disable interrupt for READY event + EVENTS_CTS + CTS is activated (set low). Clear To Send. 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_RXDRDY + Data received in RXD + 0x108 + read-write + - FIELDDETECTED - Write '1' to disable interrupt for FIELDDETECTED event - 1 - 1 + EVENTS_RXDRDY + Data received in RXD + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + - FIELDLOST - Write '1' to disable interrupt for FIELDLOST event - 2 - 2 + EVENTS_ERROR + Error detected + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 - write - Clear - Disable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - TXFRAMESTART - Write '1' to disable interrupt for TXFRAMESTART event + CTS_STARTRX + Shortcut between event CTS and task STARTRX 3 3 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut 1 + + + NCTS_STOPRX + Shortcut between event NCTS and task STOPRX + 4 + 4 - write - Clear - Disable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - TXFRAMEEND - Write '1' to disable interrupt for TXFRAMEEND event - 4 - 4 + CTS + Write '1' to enable interrupt for event CTS + 0 + 0 read @@ -17181,17 +15033,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - RXFRAMESTART - Write '1' to disable interrupt for RXFRAMESTART event - 5 - 5 + NCTS + Write '1' to enable interrupt for event NCTS + 1 + 1 read @@ -17208,17 +15060,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - RXFRAMEEND - Write '1' to disable interrupt for RXFRAMEEND event - 6 - 6 + RXDRDY + Write '1' to enable interrupt for event RXDRDY + 2 + 2 read @@ -17235,15 +15087,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ERROR - Write '1' to disable interrupt for ERROR event + TXDRDY + Write '1' to enable interrupt for event TXDRDY 7 7 @@ -17262,17 +15114,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - RXERROR - Write '1' to disable interrupt for RXERROR event - 10 - 10 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read @@ -17289,17 +15141,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ENDRX - Write '1' to disable interrupt for ENDRX event - 11 - 11 + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 read @@ -17316,17 +15168,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - ENDTX - Write '1' to disable interrupt for ENDTX event - 12 - 12 + CTS + Write '1' to disable interrupt for event CTS + 0 + 0 read @@ -17350,10 +15210,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - AUTOCOLRESSTARTED - Write '1' to disable interrupt for AUTOCOLRESSTARTED event - 14 - 14 + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 read @@ -17377,10 +15237,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COLLISION - Write '1' to disable interrupt for COLLISION event - 18 - 18 + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 read @@ -17404,10 +15264,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - SELECTED - Write '1' to disable interrupt for SELECTED event - 19 - 19 + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 read @@ -17431,10 +15291,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - STARTED - Write '1' to disable interrupt for STARTED event - 20 - 20 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read @@ -17457,1076 +15317,1161 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - ERRORSTATUS - NFC Error Status register - 0x404 - read-write - oneToClear - - - FRAMEDELAYTIMEOUT - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX - 0 - 0 - - - - - FRAMESTATUS - Unspecified - NFCT_FRAMESTATUS - 0x40C - - RX - Result of last incoming frame - 0x000 - read-write - oneToClear - - - CRCERROR - No valid end of frame (EoF) detected - 0 - 0 - - - CRCCorrect - Valid CRC detected - 0 - - - CRCError - CRC received does not match local check - 1 - - - - - PARITYSTATUS - Parity status of received frame - 2 - 2 - - - ParityOK - Frame received with parity OK - 0 - - - ParityError - Frame received with parity error - 1 - - - - - OVERRUN - Overrun detected - 3 - 3 - - - NoOverrun - No overrun detected - 0 - - - Overrun - Overrun error - 1 - - - - - - - - NFCTAGSTATE - NfcTag state register - 0x410 - read-only - - NFCTAGSTATE - NfcTag state - 0 - 2 + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + read Disabled - Disabled or sense + Read: Disabled 0 - RampUp - RampUp - 2 - - - Idle - Idle - 3 - - - Receive - Receive - 4 - - - FrameDelay - FrameDelay - 5 + Enabled + Read: Enabled + 1 + + + write - Transmit - Transmit - 6 + Clear + Disable + 1 - SLEEPSTATE - Sleep state during automatic collision resolution - 0x420 - read-only - 0x00000000 + ERRORSRC + Error source + 0x480 + read-write + oneToClear - SLEEPSTATE - Reflects the sleep state during automatic collision resolution. Set to IDLE - by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a - GOSLEEP task. + OVERRUN + Overrun error 0 0 + read - Idle - State is IDLE. + NotPresent + Read: error not present 0 - SleepA - State is SLEEP_A. + Present + Read: error present 1 - - - - FIELDPRESENT - Indicates the presence or not of a valid field - 0x43C - read-only - - FIELDPRESENT - Indicates if a valid field is present. Available only in the activated state. - 0 - 0 + PARITY + Parity error + 1 + 1 + read - NoField - No valid field detected + NotPresent + Read: error not present 0 - FieldPresent - Valid field detected + Present + Read: error present 1 - LOCKDETECT - Indicates if the low level has locked to the field - 1 - 1 + FRAMING + Framing error occurred + 2 + 2 + read - NotLocked - Not locked to field + NotPresent + Read: error not present 0 - Locked - Locked to field + Present + Read: error present 1 - - - - FRAMEDELAYMIN - Minimum frame delay - 0x504 - read-write - 0x00000480 - - - FRAMEDELAYMIN - Minimum frame delay in number of 13.56 MHz clocks - 0 - 15 - - - - - FRAMEDELAYMAX - Maximum frame delay - 0x508 - read-write - 0x00001000 - - - FRAMEDELAYMAX - Maximum frame delay in number of 13.56 MHz clocks - 0 - 19 - - - - - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer - 0x50C - read-write - 0x00000001 - - FRAMEDELAYMODE - Configuration register for the Frame Delay Timer - 0 - 1 + BREAK + Break condition + 3 + 3 + read - FreeRun - Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. + NotPresent + Read: error not present 0 - Window - Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX + Present + Read: error present 1 - - ExactVal - Frame is transmitted exactly at FRAMEDELAYMAX - 2 - - - WindowGrid - Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX - 3 - - PACKETPTR - Packet pointer for TXD and RXD data storage in Data RAM - 0x510 - read-write - 0x00000000 - - - PTR - Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. - 0 - 31 - - - - - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each - 0x514 + ENABLE + Enable UART + 0x500 read-write - MAXLEN - Size of the RAM buffer allocated to TXD and RXD data storage each + ENABLE + Enable or disable UART 0 - 8 + 3 + + + Disabled + Disable UART + 0 + + + Enabled + Enable UART + 4 + + - TXD + PSEL Unspecified - NFCT_TXD - 0x518 + UART_PSEL + read-write + 0x508 - FRAMECONFIG - Configuration of outgoing frames + RTS + Pin select for RTS 0x000 read-write - 0x00000017 + 0xFFFFFFFF - PARITY - Indicates if parity is added to the frame + PIN + Pin number 0 - 0 - - - NoParity - Parity is not added to TX frames - 0 - - - Parity - Parity is added to TX frames - 1 - - + 4 - DISCARDMODE - Discarding unused bits at start or end of a frame - 1 - 1 + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - DiscardEnd - Unused bits are discarded at end of frame (EoF) - 0 + Disconnected + Disconnect + 1 - DiscardStart - Unused bits are discarded at start of frame (SoF) - 1 + Connected + Connect + 0 + + + + TXD + Pin select for TXD + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + - SOF - Adding SoF or not in TX frames - 2 - 2 + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NoSoF - SoF symbol not added - 0 + Disconnected + Disconnect + 1 - SoF - SoF symbol added - 1 + Connected + Connect + 0 + + + + CTS + Pin select for CTS + 0x008 + read-write + 0xFFFFFFFF + - CRCMODETX - CRC mode for outgoing frames - 4 + PIN + Pin number + 0 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NoCRCTX - CRC is not added to the frame - 0 + Disconnected + Disconnect + 1 - CRC16TX - 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame - 1 + Connected + Connect + 0 - AMOUNT - Size of outgoing frame - 0x004 + RXD + Pin select for RXD + 0x00C read-write + 0xFFFFFFFF - TXDATABITS - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + PIN + Pin number 0 - 2 + 4 - TXDATABYTES - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing - 3 - 11 - - - - - - RXD - Unspecified - NFCT_RXD - 0x520 - - FRAMECONFIG - Configuration of incoming frames - 0x000 - read-write - 0x00000015 - - - PARITY - Indicates if parity expected in RX frame - 0 - 0 - - - NoParity - Parity is not expected in RX frames - 0 - - - Parity - Parity is expected in RX frames - 1 - - + PORT + Port number + 5 + 5 - SOF - SoF expected or not in RX frames - 2 - 2 + CONNECT + Connection + 31 + 31 - NoSoF - SoF symbol is not expected in RX frames - 0 - - - SoF - SoF symbol is expected in RX frames + Disconnected + Disconnect 1 - - - - CRCMODERX - CRC mode for incoming frames - 4 - 4 - - NoCRCRX - CRC is not expected in RX frames + Connected + Connect 0 - - CRC16RX - Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated - 1 - - - AMOUNT - Size of last incoming frame - 0x004 - read-only - - - RXDATABITS - Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). - 0 - 2 - - - RXDATABYTES - Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) - 3 - 11 - - - - NFCID1_LAST - Last NFCID1 part (4, 7 or 10 bytes ID) - 0x590 - read-write - 0x00006363 - - - NFCID1_Z - NFCID1 byte Z (very last byte sent) - 0 - 7 - - - NFCID1_Y - NFCID1 byte Y - 8 - 15 - - - NFCID1_X - NFCID1 byte X - 16 - 23 - - - NFCID1_W - NFCID1 byte W - 24 - 31 - - - - - NFCID1_2ND_LAST - Second last NFCID1 part (7 or 10 bytes ID) - 0x594 - read-write + RXD + RXD register + 0x518 + read-only + modifyExternal - NFCID1_V - NFCID1 byte V + RXD + RX data received in previous transfers, double buffered 0 7 - - NFCID1_U - NFCID1 byte U - 8 - 15 - - - NFCID1_T - NFCID1 byte T - 16 - 23 - - NFCID1_3RD_LAST - Third last NFCID1 part (10 bytes ID) - 0x598 - read-write + TXD + TXD register + 0x51C + write-only - NFCID1_S - NFCID1 byte S + TXD + TX data to be transferred 0 7 - - NFCID1_R - NFCID1 byte R - 8 - 15 - - - NFCID1_Q - NFCID1 byte Q - 16 - 23 - - AUTOCOLRESCONFIG - Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. - 0x59C + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 read-write - 0x00000002 + 0x04000000 - MODE - Enables/disables auto collision resolution + BAUDRATE + Baud rate 0 - 0 + 31 - Enabled - Auto collision resolution enabled - 0 + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 - Disabled - Auto collision resolution disabled - 1 + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 - - - - - - SENSRES - NFC-A SENS_RES auto-response settings - 0x5A0 - read-write - 0x00000001 - - - BITFRAMESDD - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 0 - 4 - - SDD00000 - SDD pattern 00000 - 0 + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 - SDD00001 - SDD pattern 00001 - 1 + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 - SDD00010 - SDD pattern 00010 - 2 + Baud14400 + 14400 baud (actual rate: 14414) + 0x003B0000 - SDD00100 - SDD pattern 00100 - 4 + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 - SDD01000 - SDD pattern 01000 - 8 + Baud28800 + 28800 baud (actual rate: 28829) + 0x0075F000 - SDD10000 - SDD pattern 10000 - 16 + Baud31250 + 31250 baud + 0x00800000 - - - - RFU5 - Reserved for future use. Shall be 0. - 5 - 5 - - - NFCIDSIZE - NFCID1 size. This value is used by the auto collision resolution engine. - 6 - 7 - - NFCID1Single - NFCID1 size: single (4 bytes) - 0 + Baud38400 + 38400 baud (actual rate: 38462) + 0x009D5000 - NFCID1Double - NFCID1 size: double (7 bytes) - 1 + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 - NFCID1Triple - NFCID1 size: triple (10 bytes) - 2 + Baud57600 + 57600 baud (actual rate: 57762) + 0x00EBF000 + + + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 + + + Baud115200 + 115200 baud (actual rate: 115942) + 0x01D7E000 + + + Baud230400 + 230400 baud (actual rate: 231884) + 0x03AFB000 + + + Baud250000 + 250000 baud + 0x04000000 + + + Baud460800 + 460800 baud (actual rate: 470588) + 0x075F7000 + + + Baud921600 + 921600 baud (actual rate: 941176) + 0x0EBED000 + + + Baud1M + 1Mega baud + 0x10000000 - - PLATFCONFIG - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 8 - 11 - - - RFU74 - Reserved for future use. Shall be 0. - 12 - 15 - - SELRES - NFC-A SEL_RES auto-response settings - 0x5A4 + CONFIG + Configuration of parity and hardware flow control + 0x56C read-write - RFU10 - Reserved for future use. Shall be 0. + HWFC + Hardware flow control 0 - 1 + 0 + + + Disabled + Disabled + 0 + + + Enabled + Enabled + 1 + + - CASCADE - Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) - 2 - 2 + PARITY + Parity + 1 + 3 + + + Excluded + Exclude parity bit + 0x0 + + + Included + Include parity bit + 0x7 + + - RFU43 - Reserved for future use. Shall be 0. - 3 + STOP + Stop bits + 4 4 - - - PROTOCOL - Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification - 5 - 6 - - - RFU7 - Reserved for future use. Shall be 0. - 7 - 7 + + + One + One stop bit + 0 + + + Two + Two stop bits + 1 + + - GPIOTE - GPIO Tasks and Events - 0x40006000 + UARTE0 + UART with EasyDMA 0 + 0x40002000 + UART0 + UARTE 0 0x1000 registers - GPIOTE - 6 + UARTE0_UART0 + 2 - GPIOTE + UARTE 0x20 - 0x8 - 0x4 - TASKS_OUT[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + TASKS_STARTRX + Start UART receiver 0x000 write-only - TASKS_OUT + TASKS_STARTRX + Start UART receiver 0 0 + + + Trigger + Trigger task + 1 + + - 0x8 - 0x4 - TASKS_SET[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. - 0x030 + TASKS_STOPRX + Stop UART receiver + 0x004 write-only - TASKS_SET + TASKS_STOPRX + Stop UART receiver 0 0 + + + Trigger + Trigger task + 1 + + - 0x8 - 0x4 - TASKS_CLR[%s] - Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. - 0x060 + TASKS_STARTTX + Start UART transmitter + 0x008 write-only - TASKS_CLR + TASKS_STARTTX + Start UART transmitter 0 0 + + + Trigger + Trigger task + 1 + + - 0x8 - 0x4 - EVENTS_IN[%s] - Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL - 0x100 - read-write + TASKS_STOPTX + Stop UART transmitter + 0x00C + write-only - EVENTS_IN + TASKS_STOPTX + Stop UART transmitter 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_PORT - Event generated from multiple input GPIO pins with SENSE mechanism enabled - 0x17C - read-write + TASKS_FLUSHRX + Flush RX FIFO into RX buffer + 0x02C + write-only - EVENTS_PORT + TASKS_FLUSHRX + Flush RX FIFO into RX buffer 0 0 + + + Trigger + Trigger task + 1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_CTS + CTS is activated (set low). Clear To Send. + 0x100 read-write - IN0 - Write '1' to enable interrupt for IN[0] event + EVENTS_CTS + CTS is activated (set low). Clear To Send. 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 - - IN1 - Write '1' to enable interrupt for IN[1] event - 1 - 1 - - read + + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0x104 + read-write + + + EVENTS_NCTS + CTS is deactivated (set high). Not Clear To Send. + 0 + 0 + - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0x108 + read-write + + + EVENTS_RXDRDY + Data received in RXD (but potentially not yet transferred to Data RAM) + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_ENDRX + Receive buffer is filled up + 0x110 + read-write + - IN2 - Write '1' to enable interrupt for IN[2] event - 2 - 2 + EVENTS_ENDRX + Receive buffer is filled up + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated + 1 + + + + + + + EVENTS_TXDRDY + Data sent from TXD + 0x11C + read-write + + + EVENTS_TXDRDY + Data sent from TXD + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + + EVENTS_ENDTX + Last TX byte transmitted + 0x120 + read-write + + + EVENTS_ENDTX + Last TX byte transmitted + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_ERROR + Error detected + 0x124 + read-write + - IN3 - Write '1' to enable interrupt for IN[3] event - 3 - 3 + EVENTS_ERROR + Error detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXTO + Receiver timeout + 0x144 + read-write + + + EVENTS_RXTO + Receiver timeout + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXSTARTED + UART receiver has started + 0x14C + read-write + + + EVENTS_RXSTARTED + UART receiver has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTARTED + UART transmitter has started + 0x150 + read-write + + + EVENTS_TXSTARTED + UART transmitter has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXSTOPPED + Transmitter stopped + 0x158 + read-write + + + EVENTS_TXSTOPPED + Transmitter stopped + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + ENDRX_STARTRX + Shortcut between event ENDRX and task STARTRX + 5 + 5 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut + 1 + + + + + ENDRX_STOPRX + Shortcut between event ENDRX and task STOPRX + 6 + 6 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + CTS + Enable or disable interrupt for event CTS + 0 + 0 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - IN4 - Write '1' to enable interrupt for IN[4] event - 4 - 4 + NCTS + Enable or disable interrupt for event NCTS + 1 + 1 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + RXDRDY + Enable or disable interrupt for event RXDRDY + 2 + 2 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - IN5 - Write '1' to enable interrupt for IN[5] event - 5 - 5 + ENDRX + Enable or disable interrupt for event ENDRX + 4 + 4 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TXDRDY + Enable or disable interrupt for event TXDRDY + 7 + 7 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - IN6 - Write '1' to enable interrupt for IN[6] event - 6 - 6 + ENDTX + Enable or disable interrupt for event ENDTX + 8 + 8 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - IN7 - Write '1' to enable interrupt for IN[7] event - 7 - 7 + RXTO + Enable or disable interrupt for event RXTO + 17 + 17 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - PORT - Write '1' to enable interrupt for PORT event - 31 - 31 + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TXSTOPPED + Enable or disable interrupt for event TXSTOPPED + 22 + 22 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 @@ -18535,14 +16480,14 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + INTENSET + Enable interrupt + 0x304 read-write - IN0 - Write '1' to disable interrupt for IN[0] event + CTS + Write '1' to enable interrupt for event CTS 0 0 @@ -18561,15 +16506,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN1 - Write '1' to disable interrupt for IN[1] event + NCTS + Write '1' to enable interrupt for event NCTS 1 1 @@ -18588,15 +16533,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN2 - Write '1' to disable interrupt for IN[2] event + RXDRDY + Write '1' to enable interrupt for event RXDRDY 2 2 @@ -18615,17 +16560,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN3 - Write '1' to disable interrupt for IN[3] event - 3 - 3 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read @@ -18642,17 +16587,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN4 - Write '1' to disable interrupt for IN[4] event - 4 - 4 + TXDRDY + Write '1' to enable interrupt for event TXDRDY + 7 + 7 read @@ -18669,17 +16614,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN5 - Write '1' to disable interrupt for IN[5] event - 5 - 5 + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 read @@ -18696,17 +16641,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN6 - Write '1' to disable interrupt for IN[6] event - 6 - 6 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read @@ -18723,17 +16668,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - IN7 - Write '1' to disable interrupt for IN[7] event - 7 - 7 + RXTO + Write '1' to enable interrupt for event RXTO + 17 + 17 read @@ -18750,17 +16695,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - PORT - Write '1' to disable interrupt for PORT event - 31 - 31 + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 read @@ -18777,685 +16722,367 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - 0x8 - 0x4 - CONFIG[%s] - Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event - 0x510 - read-write - - MODE - Mode - 0 - 1 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + read Disabled - Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. + Read: Disabled 0 - Event - Event mode + Enabled + Read: Enabled 1 + + + write - Task - Task mode - 3 + Set + Enable + 1 - PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event - 8 - 12 - - - PORT - Port number - 13 - 13 - - - POLARITY - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. - 16 - 17 + TXSTOPPED + Write '1' to enable interrupt for event TXSTOPPED + 22 + 22 + read - None - Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + Disabled + Read: Disabled 0 - LoToHi - Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + Enabled + Read: Enabled 1 - - HiToLo - Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 - - - Toggle - Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 - - - - OUTINIT - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. - 20 - 20 + write - Low - Task mode: Initial value of pin before task triggering is low - 0 - - - High - Task mode: Initial value of pin before task triggering is high + Set + Enable 1 - - - - SAADC - Successive approximation register (SAR) analog-to-digital converter - 0x40007000 - - 0 - 0x1000 - registers - - - SAADC - 7 - - SAADC - 0x20 - - - TASKS_START - Starts the SAADC and prepares the result buffer in RAM - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_SAMPLE - Takes one SAADC sample - 0x004 - write-only - - - TASKS_SAMPLE - 0 - 0 - - - - - TASKS_STOP - Stops the SAADC and terminates all on-going conversions - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_CALIBRATEOFFSET - Starts offset auto-calibration - 0x00C - write-only - - - TASKS_CALIBRATEOFFSET - 0 - 0 - - - - - EVENTS_STARTED - The SAADC has started - 0x100 - read-write - - - EVENTS_STARTED - 0 - 0 - - - - - EVENTS_END - The SAADC has filled up the result buffer - 0x104 - read-write - - - EVENTS_END - 0 - 0 - - - - - EVENTS_DONE - A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. - 0x108 - read-write - - - EVENTS_DONE - 0 - 0 - - - - - EVENTS_RESULTDONE - Result ready for transfer to RAM - 0x10C - read-write - - - EVENTS_RESULTDONE - 0 - 0 - - - - - EVENTS_CALIBRATEDONE - Calibration is complete - 0x110 - read-write - - - EVENTS_CALIBRATEDONE - 0 - 0 - - - - - EVENTS_STOPPED - The SAADC has stopped - 0x114 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - 8 - 0x008 - EVENTS_CH[%s] - Unspecified - SAADC_EVENTS_CH - 0x118 - - LIMITH - Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH - 0x000 - read-write - - - LIMITH - 0 - 0 - - - - - LIMITL - Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW - 0x004 - read-write - - - LIMITL - 0 - 0 - - - - - INTEN - Enable or disable interrupt - 0x300 + INTENCLR + Disable interrupt + 0x308 read-write - STARTED - Enable or disable interrupt for STARTED event + CTS + Write '1' to disable interrupt for event CTS 0 0 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - END - Enable or disable interrupt for END event - 1 - 1 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - DONE - Enable or disable interrupt for DONE event - 2 - 2 + NCTS + Write '1' to disable interrupt for event NCTS + 1 + 1 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - RESULTDONE - Enable or disable interrupt for RESULTDONE event - 3 - 3 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CALIBRATEDONE - Enable or disable interrupt for CALIBRATEDONE event - 4 - 4 + RXDRDY + Write '1' to disable interrupt for event RXDRDY + 2 + 2 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - STOPPED - Enable or disable interrupt for STOPPED event - 5 - 5 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH0LIMITH - Enable or disable interrupt for CH[0].LIMITH event - 6 - 6 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH0LIMITL - Enable or disable interrupt for CH[0].LIMITL event - 7 - 7 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH1LIMITH - Enable or disable interrupt for CH[1].LIMITH event - 8 - 8 + TXDRDY + Write '1' to disable interrupt for event TXDRDY + 7 + 7 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH1LIMITL - Enable or disable interrupt for CH[1].LIMITL event - 9 - 9 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH2LIMITH - Enable or disable interrupt for CH[2].LIMITH event - 10 - 10 + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH2LIMITL - Enable or disable interrupt for CH[2].LIMITL event - 11 - 11 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH3LIMITH - Enable or disable interrupt for CH[3].LIMITH event - 12 - 12 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH3LIMITL - Enable or disable interrupt for CH[3].LIMITL event - 13 - 13 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH4LIMITH - Enable or disable interrupt for CH[4].LIMITH event - 14 - 14 + RXTO + Write '1' to disable interrupt for event RXTO + 17 + 17 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH4LIMITL - Enable or disable interrupt for CH[4].LIMITL event - 15 - 15 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH5LIMITH - Enable or disable interrupt for CH[5].LIMITH event - 16 - 16 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH5LIMITL - Enable or disable interrupt for CH[5].LIMITL event - 17 - 17 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH6LIMITH - Enable or disable interrupt for CH[6].LIMITH event - 18 - 18 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH6LIMITL - Enable or disable interrupt for CH[6].LIMITL event - 19 - 19 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CH7LIMITH - Enable or disable interrupt for CH[7].LIMITH event - 20 - 20 + TXSTOPPED + Write '1' to disable interrupt for event TXSTOPPED + 22 + 22 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - CH7LIMITL - Enable or disable interrupt for CH[7].LIMITL event - 21 - 21 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 @@ -19463,475 +17090,602 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + ERRORSRC + Error source Note : this register is read / write one to clear. + 0x480 read-write + oneToClear - STARTED - Write '1' to enable interrupt for STARTED event + OVERRUN + Overrun error 0 0 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Present + Read: error present 1 - END - Write '1' to enable interrupt for END event + PARITY + Parity error 1 1 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Present + Read: error present 1 - DONE - Write '1' to enable interrupt for DONE event + FRAMING + Framing error occurred 2 2 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Present + Read: error present 1 - RESULTDONE - Write '1' to enable interrupt for RESULTDONE event + BREAK + Break condition 3 3 read - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CALIBRATEDONE - Write '1' to enable interrupt for CALIBRATEDONE event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - STOPPED - Write '1' to enable interrupt for STOPPED event - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - CH0LIMITH - Write '1' to enable interrupt for CH[0].LIMITH event - 6 - 6 - - read - - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Present + Read: error present 1 + + + + ENABLE + Enable UART + 0x500 + read-write + - CH0LIMITL - Write '1' to enable interrupt for CH[0].LIMITL event - 7 - 7 + ENABLE + Enable or disable UARTE + 0 + 3 - read Disabled - Read: Disabled + Disable UARTE 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + Enable UARTE + 8 + + + + PSEL + Unspecified + UARTE_PSEL + read-write + 0x508 + + RTS + Pin select for RTS signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + TXD + Pin select for TXD signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CTS + Pin select for CTS signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + RXD + Pin select for RXD signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + BAUDRATE + Baud rate. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + - CH1LIMITH - Write '1' to enable interrupt for CH[1].LIMITH event - 8 - 8 + BAUDRATE + Baud rate + 0 + 31 - read - Disabled - Read: Disabled - 0 + Baud1200 + 1200 baud (actual rate: 1205) + 0x0004F000 - Enabled - Read: Enabled - 1 + Baud2400 + 2400 baud (actual rate: 2396) + 0x0009D000 - - - write - Set - Enable - 1 + Baud4800 + 4800 baud (actual rate: 4808) + 0x0013B000 - - - - CH1LIMITL - Write '1' to enable interrupt for CH[1].LIMITL event - 9 - 9 - - read - Disabled - Read: Disabled - 0 + Baud9600 + 9600 baud (actual rate: 9598) + 0x00275000 - Enabled - Read: Enabled - 1 + Baud14400 + 14400 baud (actual rate: 14401) + 0x003AF000 - - - write - Set - Enable - 1 + Baud19200 + 19200 baud (actual rate: 19208) + 0x004EA000 - - - - CH2LIMITH - Write '1' to enable interrupt for CH[2].LIMITH event - 10 - 10 - - read - Disabled - Read: Disabled - 0 + Baud28800 + 28800 baud (actual rate: 28777) + 0x0075C000 - Enabled - Read: Enabled - 1 + Baud31250 + 31250 baud + 0x00800000 - - - write - Set - Enable - 1 + Baud38400 + 38400 baud (actual rate: 38369) + 0x009D0000 - - - - CH2LIMITL - Write '1' to enable interrupt for CH[2].LIMITL event - 11 - 11 - - read - Disabled - Read: Disabled - 0 + Baud56000 + 56000 baud (actual rate: 55944) + 0x00E50000 - Enabled - Read: Enabled - 1 + Baud57600 + 57600 baud (actual rate: 57554) + 0x00EB0000 - - - write - Set - Enable - 1 + Baud76800 + 76800 baud (actual rate: 76923) + 0x013A9000 - - - - CH3LIMITH - Write '1' to enable interrupt for CH[3].LIMITH event - 12 - 12 - - read - Disabled - Read: Disabled - 0 + Baud115200 + 115200 baud (actual rate: 115108) + 0x01D60000 - Enabled - Read: Enabled - 1 + Baud230400 + 230400 baud (actual rate: 231884) + 0x03B00000 - - - write - Set - Enable - 1 + Baud250000 + 250000 baud + 0x04000000 - - - - CH3LIMITL - Write '1' to enable interrupt for CH[3].LIMITL event - 13 - 13 - - read - Disabled - Read: Disabled - 0 + Baud460800 + 460800 baud (actual rate: 457143) + 0x07400000 - Enabled - Read: Enabled - 1 + Baud921600 + 921600 baud (actual rate: 941176) + 0x0F000000 - - - write - Set - Enable - 1 + Baud1M + 1Mega baud + 0x10000000 - - CH4LIMITH - Write '1' to enable interrupt for CH[4].LIMITH event - 14 - 14 - - read + + + + RXD + RXD EasyDMA channel + UARTE_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + TXD + TXD EasyDMA channel + UARTE_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + + CONFIG + Configuration of parity and hardware flow control + 0x56C + read-write + + + HWFC + Hardware flow control + 0 + 0 + Disabled - Read: Disabled + Disabled 0 Enabled - Read: Enabled + Enabled 1 + + + PARITY + Parity + 1 + 3 - write - Set - Enable - 1 + Excluded + Exclude parity bit + 0x0 + + + Included + Include even parity bit + 0x7 - CH4LIMITL - Write '1' to enable interrupt for CH[4].LIMITL event - 15 - 15 + STOP + Stop bits + 4 + 4 - read - Disabled - Read: Disabled + One + One stop bit 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Two + Two stop bits 1 + + + + + + SPI0 + Serial Peripheral Interface 0 + 0x40003000 + SPI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPI + 0x20 + + + EVENTS_READY + TXD byte sent and RXD byte received + 0x108 + read-write + - CH5LIMITH - Write '1' to enable interrupt for CH[5].LIMITH event - 16 - 16 + EVENTS_READY + TXD byte sent and RXD byte received + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH5LIMITL - Write '1' to enable interrupt for CH[5].LIMITL event - 17 - 17 + READY + Write '1' to enable interrupt for event READY + 2 + 2 read @@ -19954,11 +17708,19 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH6LIMITH - Write '1' to enable interrupt for CH[6].LIMITH event - 18 - 18 + READY + Write '1' to disable interrupt for event READY + 2 + 2 read @@ -19975,403 +17737,578 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 + + + + ENABLE + Enable SPI + 0x500 + read-write + - CH6LIMITL - Write '1' to enable interrupt for CH[6].LIMITL event - 19 - 19 + ENABLE + Enable or disable SPI + 0 + 3 - read Disabled - Read: Disabled + Disable SPI 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable SPI 1 + + + + PSEL + Unspecified + SPI_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RX data received. Double buffered + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + - CH7LIMITH - Write '1' to enable interrupt for CH[7].LIMITH event - 20 - 20 + TXD + TX data to send. Double buffered + 0 + 7 + + + + + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + SPI master data rate + 0 + 31 - read - Disabled - Read: Disabled - 0 + K125 + 125 kbps + 0x02000000 - Enabled - Read: Enabled - 1 + K250 + 250 kbps + 0x04000000 - - - write - Set - Enable - 1 + K500 + 500 kbps + 0x08000000 - - - - CH7LIMITL - Write '1' to enable interrupt for CH[7].LIMITL event - 21 - 21 - - read - Disabled - Read: Disabled - 0 + M1 + 1 Mbps + 0x10000000 - Enabled - Read: Enabled - 1 + M2 + 2 Mbps + 0x20000000 - - - write - Set - Enable - 1 + M4 + 4 Mbps + 0x40000000 + + + M8 + 8 Mbps + 0x80000000 - INTENCLR - Disable interrupt - 0x308 + CONFIG + Configuration register + 0x554 read-write - STARTED - Write '1' to disable interrupt for STARTED event + ORDER + Bit order 0 0 - read - Disabled - Read: Disabled + MsbFirst + Most significant bit shifted out first 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + LsbFirst + Least significant bit shifted out first 1 - END - Write '1' to disable interrupt for END event + CPHA + Serial clock (SCK) phase 1 1 - read - Disabled - Read: Disabled + Leading + Sample on leading edge of clock, shift serial data on trailing edge 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Trailing + Sample on trailing edge of clock, shift serial data on leading edge 1 - DONE - Write '1' to disable interrupt for DONE event + CPOL + Serial clock (SCK) polarity 2 2 - read - Disabled - Read: Disabled + ActiveHigh + Active high 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + ActiveLow + Active low 1 + + + + + + SPIM0 + Serial Peripheral Interface Master with EasyDMA 0 + 0x40003000 + SPI0 + SPIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIM + 0x20 + + + TASKS_START + Start SPI transaction + 0x010 + write-only + - RESULTDONE - Write '1' to disable interrupt for RESULTDONE event - 3 - 3 + TASKS_START + Start SPI transaction + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_STOP + Stop SPI transaction + 0x014 + write-only + + + TASKS_STOP + Stop SPI transaction + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + TASKS_SUSPEND + Suspend SPI transaction + 0x01C + write-only + - CALIBRATEDONE - Write '1' to disable interrupt for CALIBRATEDONE event - 4 - 4 + TASKS_SUSPEND + Suspend SPI transaction + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_RESUME + Resume SPI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume SPI transaction + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + EVENTS_STOPPED + SPI transaction has stopped + 0x104 + read-write + - STOPPED - Write '1' to disable interrupt for STOPPED event - 5 - 5 + EVENTS_STOPPED + SPI transaction has stopped + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_ENDRX + End of RXD buffer reached + 0x110 + read-write + - CH0LIMITH - Write '1' to disable interrupt for CH[0].LIMITH event - 6 - 6 + EVENTS_ENDRX + End of RXD buffer reached + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_END + End of RXD buffer and TXD buffer reached + 0x118 + read-write + - CH0LIMITL - Write '1' to disable interrupt for CH[0].LIMITL event - 7 - 7 + EVENTS_END + End of RXD buffer and TXD buffer reached + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_ENDTX + End of TXD buffer reached + 0x120 + read-write + - CH1LIMITH - Write '1' to disable interrupt for CH[1].LIMITH event - 8 - 8 + EVENTS_ENDTX + End of TXD buffer reached + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_STARTED + Transaction started + 0x14C + read-write + - CH1LIMITL - Write '1' to disable interrupt for CH[1].LIMITL event - 9 - 9 + EVENTS_STARTED + Transaction started + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH2LIMITH - Write '1' to disable interrupt for CH[2].LIMITH event - 10 - 10 + END_START + Shortcut between event END and task START + 17 + 17 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH2LIMITL - Write '1' to disable interrupt for CH[2].LIMITL event - 11 - 11 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read @@ -20388,17 +18325,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - CH3LIMITH - Write '1' to disable interrupt for CH[3].LIMITH event - 12 - 12 + ENDRX + Write '1' to enable interrupt for event ENDRX + 4 + 4 read @@ -20415,17 +18352,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - CH3LIMITL - Write '1' to disable interrupt for CH[3].LIMITL event - 13 - 13 + END + Write '1' to enable interrupt for event END + 6 + 6 read @@ -20442,17 +18379,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - CH4LIMITH - Write '1' to disable interrupt for CH[4].LIMITH event - 14 - 14 + ENDTX + Write '1' to enable interrupt for event ENDTX + 8 + 8 read @@ -20469,17 +18406,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - CH4LIMITL - Write '1' to disable interrupt for CH[4].LIMITL event - 15 - 15 + STARTED + Write '1' to enable interrupt for event STARTED + 19 + 19 read @@ -20496,17 +18433,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH5LIMITH - Write '1' to disable interrupt for CH[5].LIMITH event - 16 - 16 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read @@ -20530,10 +18475,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH5LIMITL - Write '1' to disable interrupt for CH[5].LIMITL event - 17 - 17 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 read @@ -20557,10 +18502,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH6LIMITH - Write '1' to disable interrupt for CH[6].LIMITH event - 18 - 18 + END + Write '1' to disable interrupt for event END + 6 + 6 read @@ -20584,10 +18529,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH6LIMITL - Write '1' to disable interrupt for CH[6].LIMITL event - 19 - 19 + ENDTX + Write '1' to disable interrupt for event ENDTX + 8 + 8 read @@ -20611,10 +18556,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH7LIMITH - Write '1' to disable interrupt for CH[7].LIMITH event - 20 - 20 + STARTED + Write '1' to disable interrupt for event STARTED + 19 + 19 read @@ -20637,55 +18582,47 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + STALLSTAT + Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + 0x400 + read-write + 0x00000000 + - CH7LIMITL - Write '1' to disable interrupt for CH[7].LIMITL event - 21 - 21 + TX + Stall status for EasyDMA RAM reads + 0 + 0 - read - Disabled - Read: Disabled + NOSTALL + No stall 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + STALL + A stall has occurred 1 - - - - STATUS - Status - 0x400 - read-only - - STATUS - Status - 0 - 0 + RX + Stall status for EasyDMA RAM writes + 1 + 1 - Ready - SAADC is ready. No on-going conversions. + NOSTALL + No stall 0 - Busy - SAADC is busy. Conversion in progress. + STALL + A stall has occurred 1 @@ -20694,543 +18631,261 @@ POSSIBILITY OF SUCH DAMAGE.\n ENABLE - Enable or disable SAADC + Enable SPIM 0x500 read-write ENABLE - Enable or disable SAADC + Enable or disable SPIM 0 - 0 + 3 Disabled - Disable SAADC + Disable SPIM 0 Enabled - Enable SAADC - 1 + Enable SPIM + 7 - 8 - 0x010 - CH[%s] + PSEL Unspecified - SAADC_CH - 0x510 + SPIM_PSEL + read-write + 0x508 - PSELP - Description cluster[n]: Input positive pin selection for CH[n] + SCK + Pin select for SCK 0x000 read-write - 0x00000000 + 0xFFFFFFFF - PSELP - Analog positive input channel + PIN + Pin number 0 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 + Disconnected + Disconnect 1 - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - VDDHDIV5 - VDDH/5 - 0x0D + Connected + Connect + 0 - PSELN - Description cluster[n]: Input negative pin selection for CH[n] + MOSI + Pin select for MOSI signal 0x004 read-write - 0x00000000 + 0xFFFFFFFF - PSELN - Analog negative input, enables differential channel + PIN + Pin number 0 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - NC - Not connected - 0 - - - AnalogInput0 - AIN0 + Disconnected + Disconnect 1 - AnalogInput1 - AIN1 - 2 - - - AnalogInput2 - AIN2 - 3 - - - AnalogInput3 - AIN3 - 4 - - - AnalogInput4 - AIN4 - 5 - - - AnalogInput5 - AIN5 - 6 - - - AnalogInput6 - AIN6 - 7 - - - AnalogInput7 - AIN7 - 8 - - - VDD - VDD - 9 - - - VDDHDIV5 - VDDH/5 - 0x0D + Connected + Connect + 0 - CONFIG - Description cluster[n]: Input configuration for CH[n] + MISO + Pin select for MISO signal 0x008 read-write - 0x00020000 + 0xFFFFFFFF - RESP - Positive channel resistor control + PIN + Pin number 0 - 1 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - + 4 - RESN - Negative channel resistor control - 4 + PORT + Port number + 5 5 - - - Bypass - Bypass resistor ladder - 0 - - - Pulldown - Pull-down to GND - 1 - - - Pullup - Pull-up to VDD - 2 - - - VDD1_2 - Set input at VDD/2 - 3 - - - GAIN - Gain control - 8 - 10 + CONNECT + Connection + 31 + 31 - Gain1_6 - 1/6 - 0 - - - Gain1_5 - 1/5 + Disconnected + Disconnect 1 - Gain1_4 - 1/4 - 2 - - - Gain1_3 - 1/3 - 3 - - - Gain1_2 - 1/2 - 4 - - - Gain1 - 1 - 5 - - - Gain2 - 2 - 6 - - - Gain4 - 4 - 7 + Connected + Connect + 0 + + + + CSN + Pin select for CSN + 0x00C + read-write + 0xFFFFFFFF + - REFSEL - Reference control - 12 - 12 - - - Internal - Internal reference (0.6 V) - 0 - - - VDD1_4 - VDD/4 as reference - 1 - - + PIN + Pin number + 0 + 4 - TACQ - Acquisition time, the time the SAADC uses to sample the input voltage - 16 - 18 - - - 3us - 3 us - 0 - - - 5us - 5 us - 1 - - - 10us - 10 us - 2 - - - 15us - 15 us - 3 - - - 20us - 20 us - 4 - - - 40us - 40 us - 5 - - + PORT + Port number + 5 + 5 - MODE - Enable differential mode - 20 - 20 + CONNECT + Connection + 31 + 31 - SE - Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND - 0 - - - Diff - Differential + Disconnected + Disconnect 1 - - - - BURST - Enable burst mode - 24 - 24 - - Disabled - Burst mode is disabled (normal operation) + Connected + Connect 0 - - Enabled - Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 - - - LIMIT - Description cluster[n]: High/low limits for event monitoring of a channel - 0x00C - read-write - 0x7FFF8000 - - - LOW - Low level limit - 0 - 15 - - - HIGH - High level limit - 16 - 31 - - - - RESOLUTION - Resolution configuration - 0x5F0 - read-write - 0x00000001 - - - VAL - Set the resolution - 0 - 2 - - - 8bit - 8 bits - 0 - - - 10bit - 10 bits - 1 - - - 12bit - 12 bits - 2 - - - 14bit - 14 bits - 3 - - - - - - - OVERSAMPLE - Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. - 0x5F4 + FREQUENCY + SPI frequency. Accuracy depends on the HFCLK source selected. + 0x524 read-write + 0x04000000 - OVERSAMPLE - Oversample control + FREQUENCY + SPI master data rate 0 - 3 + 31 - Bypass - Bypass oversampling - 0 - - - Over2x - Oversample 2x - 1 - - - Over4x - Oversample 4x - 2 + K125 + 125 kbps + 0x02000000 - Over8x - Oversample 8x - 3 + K250 + 250 kbps + 0x04000000 - Over16x - Oversample 16x - 4 + K500 + 500 kbps + 0x08000000 - Over32x - Oversample 32x - 5 + M1 + 1 Mbps + 0x10000000 - Over64x - Oversample 64x - 6 + M2 + 2 Mbps + 0x20000000 - Over128x - Oversample 128x - 7 + M4 + 4 Mbps + 0x40000000 - Over256x - Oversample 256x - 8 + M8 + 8 Mbps + 0x80000000 - - - - - - SAMPLERATE - Controls normal or continuous sample rate - 0x5F8 - read-write - - - CC - Capture and compare value. Sample rate is 16 MHz/CC - 0 - 10 - - - MODE - Select mode for sample rate control - 12 - 12 - - Task - Rate is controlled from SAMPLE task - 0 + M16 + 16 Mbps + 0x0A000000 - Timers - Rate is controlled from local timer (use CC to control the rate) - 1 + M32 + 32 Mbps + 0x14000000 - RESULT - RESULT EasyDMA channel - SAADC_RESULT - 0x62C + RXD + RXD EasyDMA channel + SPIM_RXD + read-write + 0x534 PTR Data pointer @@ -21247,192 +18902,476 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXCNT - Maximum number of 16-bit samples to be written to output RAM buffer + Maximum number of bytes in receive buffer 0x004 read-write MAXCNT - Maximum number of 16-bit samples to be written to output RAM buffer + Maximum number of bytes in receive buffer 0 - 14 + 15 AMOUNT - Number of 16-bit samples written to output RAM buffer since the previous START task + Number of bytes transferred in the last transaction 0x008 read-only AMOUNT - Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + Number of bytes transferred in the last transaction 0 - 14 + 15 - - - - - TIMER0 - Timer/Counter 0 - 0x40008000 - TIMER - - 0 - 0x1000 - registers - - - TIMER0 - 8 - - TIMER - 0x20 - + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + SPIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + - TASKS_START - Start Timer - 0x000 - write-only + CONFIG + Configuration register + 0x554 + read-write - TASKS_START + ORDER + Bit order 0 0 + + + MsbFirst + Most significant bit shifted out first + 0 + + + LsbFirst + Least significant bit shifted out first + 1 + + + + + CPHA + Serial clock (SCK) phase + 1 + 1 + + + Leading + Sample on leading edge of clock, shift serial data on trailing edge + 0 + + + Trailing + Sample on trailing edge of clock, shift serial data on leading edge + 1 + + + + + CPOL + Serial clock (SCK) polarity + 2 + 2 + + + ActiveHigh + Active high + 0 + + + ActiveLow + Active low + 1 + + + + IFTIMING + Unspecified + SPIM_IFTIMING + read-write + 0x560 + + RXDELAY + Sample delay for input serial data on MISO + 0x000 + read-write + 0x00000002 + + + RXDELAY + Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. + 0 + 2 + + + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions + 0x004 + read-write + 0x00000002 + + + CSNDUR + Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). + 0 + 7 + + + + - TASKS_STOP - Stop Timer - 0x004 - write-only + CSNPOL + Polarity of CSN output + 0x568 + read-write + 0x00000000 - TASKS_STOP + CSNPOL + Polarity of CSN output 0 0 + + + LOW + Active low (idle state high) + 0 + + + HIGH + Active high (idle state low) + 1 + + - TASKS_COUNT - Increment Timer (Counter mode only) - 0x008 - write-only + PSELDCX + Pin select for DCX signal + 0x56C + read-write + 0xFFFFFFFF - TASKS_COUNT + PIN + Pin number 0 - 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + - TASKS_CLEAR - Clear time - 0x00C - write-only + DCXCNT + DCX configuration + 0x570 + read-write - TASKS_CLEAR + DCXCNT + This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. 0 - 0 + 3 - TASKS_SHUTDOWN - Deprecated register - Shut down timer - 0x010 + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT + 0x5C0 + read-write + + + ORC + Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. + 0 + 7 + + + + + + + SPIS0 + SPI Slave 0 + 0x40003000 + SPI0 + SPIS + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + SPIS + 0x20 + + + TASKS_ACQUIRE + Acquire SPI semaphore + 0x024 write-only - TASKS_SHUTDOWN + TASKS_ACQUIRE + Acquire SPI semaphore 0 0 + + + Trigger + Trigger task + 1 + + - 0x6 - 0x4 - TASKS_CAPTURE[%s] - Description collection[n]: Capture Timer value to CC[n] register - 0x040 + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it + 0x028 write-only - TASKS_CAPTURE + TASKS_RELEASE + Release SPI semaphore, enabling the SPI slave to acquire it 0 0 + + + Trigger + Trigger task + 1 + + - 0x6 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 + EVENTS_END + Granted transaction completed + 0x104 read-write - EVENTS_COMPARE + EVENTS_END + Granted transaction completed 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - SHORTS - Shortcut register - 0x200 + EVENTS_ENDRX + End of RXD buffer reached + 0x110 read-write - COMPARE0_CLEAR - Shortcut between COMPARE[0] event and CLEAR task + EVENTS_ENDRX + End of RXD buffer reached 0 0 - Disabled - Disable shortcut + NotGenerated + Event not generated 0 - Enabled - Enable shortcut + Generated + Event generated 1 + + + + EVENTS_ACQUIRED + Semaphore acquired + 0x128 + read-write + - COMPARE1_CLEAR - Shortcut between COMPARE[1] event and CLEAR task - 1 - 1 + EVENTS_ACQUIRED + Semaphore acquired + 0 + 0 - Disabled - Disable shortcut + NotGenerated + Event not generated 0 - Enabled - Enable shortcut + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - COMPARE2_CLEAR - Shortcut between COMPARE[2] event and CLEAR task + END_ACQUIRE + Shortcut between event END and task ACQUIRE 2 2 @@ -21448,504 +19387,833 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + INTENSET + Enable interrupt + 0x304 + read-write + - COMPARE3_CLEAR - Shortcut between COMPARE[3] event and CLEAR task - 3 - 3 + END + Write '1' to enable interrupt for event END + 1 + 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - COMPARE4_CLEAR - Shortcut between COMPARE[4] event and CLEAR task + ENDRX + Write '1' to enable interrupt for event ENDRX 4 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - COMPARE5_CLEAR - Shortcut between COMPARE[5] event and CLEAR task - 5 - 5 + ACQUIRED + Write '1' to enable interrupt for event ACQUIRED + 10 + 10 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - COMPARE0_STOP - Shortcut between COMPARE[0] event and STOP task - 8 - 8 + END + Write '1' to disable interrupt for event END + 1 + 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE1_STOP - Shortcut between COMPARE[1] event and STOP task - 9 - 9 + ENDRX + Write '1' to disable interrupt for event ENDRX + 4 + 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - COMPARE2_STOP - Shortcut between COMPARE[2] event and STOP task + ACQUIRED + Write '1' to disable interrupt for event ACQUIRED 10 10 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - COMPARE3_STOP - Shortcut between COMPARE[3] event and STOP task - 11 - 11 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 + + + + SEMSTAT + Semaphore status register + 0x400 + read-only + 0x00000001 + - COMPARE4_STOP - Shortcut between COMPARE[4] event and STOP task - 12 - 12 + SEMSTAT + Semaphore status + 0 + 1 - Disabled - Disable shortcut + Free + Semaphore is free 0 - Enabled - Enable shortcut + CPU + Semaphore is assigned to CPU 1 - - - - COMPARE5_STOP - Shortcut between COMPARE[5] event and STOP task - 13 - 13 - - Disabled - Disable shortcut - 0 + SPIS + Semaphore is assigned to SPI slave + 2 - Enabled - Enable shortcut - 1 + CPUPending + Semaphore is assigned to SPI but a handover to the CPU is pending + 3 - INTENSET - Enable interrupt - 0x304 + STATUS + Status from last transaction + 0x440 read-write - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 + OVERREAD + TX buffer over-read detected, and prevented + 0 + 0 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled + Present + Read: error present 1 write - Set - Enable + Clear + Write: clear error on writing '1' 1 - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 + OVERFLOW + RX buffer overflow detected, and prevented + 1 + 1 read - Disabled - Read: Disabled + NotPresent + Read: error not present 0 - Enabled - Read: Enabled + Present + Read: error present 1 write - Set - Enable + Clear + Write: clear error on writing '1' 1 + + + + ENABLE + Enable SPI slave + 0x500 + read-write + - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 + ENABLE + Enable or disable SPI slave + 0 + 3 - read Disabled - Read: Disabled + Disable SPI slave 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 + Enable SPI slave + 2 + + + + PSEL + Unspecified + SPIS_PSEL + read-write + 0x508 + + SCK + Pin select for SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MISO + Pin select for MISO signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + MOSI + Pin select for MOSI signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for CSN signal + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + Unspecified + SPIS_RXD + read-write + 0x534 + + PTR + RXD data pointer + 0x000 + read-write + + + PTR + RXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes received in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes received in the last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + Unspecified + SPIS_TXD + read-write + 0x544 + + PTR + TXD data pointer + 0x000 + read-write + + + PTR + TXD data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transmitted in last granted transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + CONFIG + Configuration register + 0x554 + read-write + - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event - 19 - 19 + ORDER + Bit order + 0 + 0 - read - Disabled - Read: Disabled + MsbFirst + Most significant bit shifted out first 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + LsbFirst + Least significant bit shifted out first 1 - COMPARE4 - Write '1' to enable interrupt for COMPARE[4] event - 20 - 20 + CPHA + Serial clock (SCK) phase + 1 + 1 - read - Disabled - Read: Disabled + Leading + Sample on leading edge of clock, shift serial data on trailing edge 0 - Enabled - Read: Enabled + Trailing + Sample on trailing edge of clock, shift serial data on leading edge 1 + + + CPOL + Serial clock (SCK) polarity + 2 + 2 - write - Set - Enable + ActiveHigh + Active high + 0 + + + ActiveLow + Active low 1 - - COMPARE5 - Write '1' to enable interrupt for COMPARE[5] event - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - + + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0x55C + read-write + + + DEF + Default character. Character clocked out in case of an ignored transaction. + 0 + 7 - INTENCLR - Disable interrupt - 0x308 + ORC + Over-read character + 0x5C0 read-write - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + ORC + Over-read character. Character clocked out after an over-read of the transmit buffer. + 0 + 7 + + + + + + TWI0 + I2C compatible Two-Wire Interface 0 + 0x40003000 + SPI0 + TWI + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWI + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only + - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_STARTTX + Start TWI transmit sequence + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop TWI transaction + 0x014 + write-only + - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_STOP + Stop TWI transaction + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + - COMPARE4 - Write '1' to disable interrupt for COMPARE[4] event - 20 - 20 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + - COMPARE5 - Write '1' to disable interrupt for COMPARE[5] event - 21 - 21 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - + TASKS_RESUME + Resume TWI transaction + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 @@ -21953,230 +20221,202 @@ POSSIBILITY OF SUCH DAMAGE.\n - MODE - Timer mode selection - 0x504 + EVENTS_STOPPED + TWI stopped + 0x104 read-write - MODE - Timer mode + EVENTS_STOPPED + TWI stopped 0 - 1 + 0 - Timer - Select Timer mode + NotGenerated + Event not generated 0 - Counter - Deprecated enumerator - Select Counter mode + Generated + Event generated 1 - - LowPowerCounter - Select Low Power Counter mode - 2 - - BITMODE - Configure the number of bits used by the TIMER - 0x508 + EVENTS_RXDREADY + TWI RXD byte received + 0x108 read-write - BITMODE - Timer bit width + EVENTS_RXDREADY + TWI RXD byte received 0 - 1 + 0 - 16Bit - 16 bit timer bit width + NotGenerated + Event not generated 0 - 08Bit - 8 bit timer bit width + Generated + Event generated 1 - - 24Bit - 24 bit timer bit width - 2 - - - 32Bit - 32 bit timer bit width - 3 - - PRESCALER - Timer prescaler register - 0x510 - read-write - 0x00000004 - - - PRESCALER - Prescaler value - 0 - 3 - - - - - 0x6 - 0x4 - CC[%s] - Description collection[n]: Capture/Compare register n - 0x540 + EVENTS_TXDSENT + TWI TXD byte sent + 0x11C read-write - CC - Capture/Compare value - 0 - 31 - - - - - - - TIMER1 - Timer/Counter 1 - 0x40009000 - - TIMER1 - 9 - - - - TIMER2 - Timer/Counter 2 - 0x4000A000 - - TIMER2 - 10 - - - - RTC0 - Real time counter 0 - 0x4000B000 - RTC - - 0 - 0x1000 - registers - - - RTC0 - 11 - - RTC - 0x20 - - - TASKS_START - Start RTC COUNTER - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop RTC COUNTER - 0x004 - write-only - - - TASKS_STOP + EVENTS_TXDSENT + TWI TXD byte sent 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - TASKS_CLEAR - Clear RTC COUNTER - 0x008 - write-only + EVENTS_ERROR + TWI error + 0x124 + read-write - TASKS_CLEAR + EVENTS_ERROR + TWI error 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - TASKS_TRIGOVRFLW - Set COUNTER to 0xFFFFF0 - 0x00C - write-only + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received + 0x138 + read-write - TASKS_TRIGOVRFLW + EVENTS_BB + TWI byte boundary, generated before each byte that is sent or received 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_TICK - Event on COUNTER increment - 0x100 + EVENTS_SUSPENDED + TWI entered the suspended state + 0x148 read-write - EVENTS_TICK + EVENTS_SUSPENDED + TWI entered the suspended state 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_OVRFLW - Event on COUNTER overflow - 0x104 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - EVENTS_OVRFLW + BB_SUSPEND + Shortcut between event BB and task SUSPEND 0 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + - - - - 0x4 - 0x4 - EVENTS_COMPARE[%s] - Description collection[n]: Compare event on CC[n] match - 0x140 - read-write - - EVENTS_COMPARE - 0 - 0 + BB_STOP + Shortcut between event BB and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + @@ -22187,10 +20427,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - TICK - Write '1' to enable interrupt for TICK event - 0 - 0 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read @@ -22214,10 +20454,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - OVRFLW - Write '1' to enable interrupt for OVRFLW event - 1 - 1 + RXDREADY + Write '1' to enable interrupt for event RXDREADY + 2 + 2 read @@ -22241,10 +20481,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE0 - Write '1' to enable interrupt for COMPARE[0] event - 16 - 16 + TXDSENT + Write '1' to enable interrupt for event TXDSENT + 7 + 7 read @@ -22268,10 +20508,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE1 - Write '1' to enable interrupt for COMPARE[1] event - 17 - 17 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read @@ -22295,10 +20535,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE2 - Write '1' to enable interrupt for COMPARE[2] event - 18 - 18 + BB + Write '1' to enable interrupt for event BB + 14 + 14 read @@ -22322,10 +20562,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE3 - Write '1' to enable interrupt for COMPARE[3] event - 19 - 19 + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED + 18 + 18 read @@ -22357,10 +20597,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - TICK - Write '1' to disable interrupt for TICK event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read @@ -22384,10 +20624,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - OVRFLW - Write '1' to disable interrupt for OVRFLW event - 1 - 1 + RXDREADY + Write '1' to disable interrupt for event RXDREADY + 2 + 2 read @@ -22411,10 +20651,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE0 - Write '1' to disable interrupt for COMPARE[0] event - 16 - 16 + TXDSENT + Write '1' to disable interrupt for event TXDSENT + 7 + 7 read @@ -22438,10 +20678,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE1 - Write '1' to disable interrupt for COMPARE[1] event - 17 - 17 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 read @@ -22465,10 +20705,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE2 - Write '1' to disable interrupt for COMPARE[2] event - 18 - 18 + BB + Write '1' to disable interrupt for event BB + 14 + 14 read @@ -22492,10 +20732,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - COMPARE3 - Write '1' to disable interrupt for COMPARE[3] event - 19 - 19 + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 read @@ -22521,115 +20761,292 @@ POSSIBILITY OF SUCH DAMAGE.\n - EVTEN - Enable or disable event routing - 0x340 + ERRORSRC + Error source + 0x4C4 read-write + oneToClear - TICK - Enable or disable event routing for TICK event + OVERRUN + Overrun error 0 0 + read - Disabled - Disable + NotPresent + Read: no overrun occured 0 - Enabled - Enable + Present + Read: overrun occured 1 - OVRFLW - Enable or disable event routing for OVRFLW event + ANACK + NACK received after sending the address (write '1' to clear) 1 1 + read - Disabled - Disable + NotPresent + Read: error not present 0 - Enabled - Enable + Present + Read: error present 1 - COMPARE0 - Enable or disable event routing for COMPARE[0] event - 16 - 16 + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 + read - Disabled - Disable + NotPresent + Read: error not present 0 - Enabled - Enable + Present + Read: error present 1 + + + + ENABLE + Enable TWI + 0x500 + read-write + - COMPARE1 - Enable or disable event routing for COMPARE[1] event - 17 - 17 + ENABLE + Enable or disable TWI + 0 + 3 Disabled - Disable + Disable TWI 0 Enabled - Enable - 1 + Enable TWI + 5 + + + + PSEL + Unspecified + TWI_PSEL + read-write + 0x508 + + SCL + Pin select for SCL + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD register + 0x518 + read-only + modifyExternal + + + RXD + RXD register + 0 + 7 + + + + + TXD + TXD register + 0x51C + read-write + - COMPARE2 - Enable or disable event routing for COMPARE[2] event - 18 - 18 + TXD + TXD register + 0 + 7 + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency + 0 + 31 - Disabled - Disable - 0 + K100 + 100 kbps + 0x01980000 - Enabled - Enable - 1 + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps (actual rate 410.256 kbps) + 0x06680000 + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 + + + + + + + TWIM0 + I2C compatible Two-Wire Master Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIM + + 0 + 0x1000 + registers + + + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 + + TWIM + 0x20 + + + TASKS_STARTRX + Start TWI receive sequence + 0x000 + write-only + - COMPARE3 - Enable or disable event routing for COMPARE[3] event - 19 - 19 + TASKS_STARTRX + Start TWI receive sequence + 0 + 0 - Disabled - Disable - 0 - - - Enabled - Enable + Trigger + Trigger task 1 @@ -22637,169 +21054,213 @@ POSSIBILITY OF SUCH DAMAGE.\n - EVTENSET - Enable event routing - 0x344 - read-write + TASKS_STARTTX + Start TWI transmit sequence + 0x008 + write-only - TICK - Write '1' to enable event routing for TICK event + TASKS_STARTTX + Start TWI transmit sequence 0 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0x014 + write-only + + + TASKS_STOP + Stop TWI transaction. Must be issued while the TWI master is not suspended. + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_SUSPEND + Suspend TWI transaction + 0x01C + write-only + - OVRFLW - Write '1' to enable event routing for OVRFLW event - 1 - 1 + TASKS_SUSPEND + Suspend TWI transaction + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only + + + TASKS_RESUME + Resume TWI transaction + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + EVENTS_STOPPED + TWI stopped + 0x104 + read-write + - COMPARE0 - Write '1' to enable event routing for COMPARE[0] event - 16 - 16 + EVENTS_STOPPED + TWI stopped + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + - COMPARE1 - Write '1' to enable event routing for COMPARE[1] event - 17 - 17 + EVENTS_ERROR + TWI error + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0x148 + read-write + - COMPARE2 - Write '1' to enable event routing for COMPARE[2] event - 18 - 18 + EVENTS_SUSPENDED + Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + - COMPARE3 - Write '1' to enable event routing for COMPARE[3] event - 19 - 19 + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 @@ -22807,70 +21268,318 @@ POSSIBILITY OF SUCH DAMAGE.\n - EVTENCLR - Disable event routing - 0x348 + EVENTS_LASTRX + Byte boundary, starting to receive the last byte + 0x15C read-write - TICK - Write '1' to disable event routing for TICK event + EVENTS_LASTRX + Byte boundary, starting to receive the last byte 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0x160 + read-write + + + EVENTS_LASTTX + Byte boundary, starting to transmit the last byte + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + LASTTX_STARTRX + Shortcut between event LASTTX and task STARTRX + 7 + 7 + + + Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut 1 + + + LASTTX_SUSPEND + Shortcut between event LASTTX and task SUSPEND + 8 + 8 - write - Clear - Disable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 - OVRFLW - Write '1' to disable event routing for OVRFLW event + LASTTX_STOP + Shortcut between event LASTTX and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STARTTX + Shortcut between event LASTRX and task STARTTX + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_SUSPEND + Shortcut between event LASTRX and task SUSPEND + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LASTRX_STOP + Shortcut between event LASTRX and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED 1 1 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - COMPARE0 - Write '1' to disable event routing for COMPARE[0] event - 16 - 16 + SUSPENDED + Enable or disable interrupt for event SUSPENDED + 18 + 18 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTRX + Enable or disable interrupt for event LASTRX + 23 + 23 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + LASTTX + Enable or disable interrupt for event LASTTX + 24 + 24 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read @@ -22887,17 +21596,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - COMPARE1 - Write '1' to disable event routing for COMPARE[1] event - 17 - 17 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read @@ -22914,15 +21623,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - COMPARE2 - Write '1' to disable event routing for COMPARE[2] event + SUSPENDED + Write '1' to enable interrupt for event SUSPENDED 18 18 @@ -22941,15 +21650,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - COMPARE3 - Write '1' to disable event routing for COMPARE[3] event + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED 19 19 @@ -22968,126 +21677,71 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - COUNTER - Current COUNTER value - 0x504 - read-only - - - COUNTER - Counter value - 0 - 23 - - - - - PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped - 0x508 - read-write - - PRESCALER - Prescaler value - 0 - 11 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - 0x4 - 0x4 - CC[%s] - Description collection[n]: Compare register n - 0x540 - read-write - - COMPARE - Compare value - 0 + LASTRX + Write '1' to enable interrupt for event LASTRX + 23 23 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - - - TEMP - Temperature Sensor - 0x4000C000 - - 0 - 0x1000 - registers - - - TEMP - 12 - - TEMP - 0x20 - - - TASKS_START - Start temperature measurement - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop temperature measurement - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_DATARDY - Temperature measurement complete, data ready - 0x100 - read-write - - - EVENTS_DATARDY - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - DATARDY - Write '1' to enable interrupt for DATARDY event - 0 - 0 + LASTTX + Write '1' to enable interrupt for event LASTTX + 24 + 24 read @@ -23119,10 +21773,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - DATARDY - Write '1' to disable interrupt for DATARDY event - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 read @@ -23145,372 +21799,38 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - TEMP - Temperature in degC (0.25deg steps) - 0x508 - read-only - int32_t - - - TEMP - Temperature in degC (0.25deg steps) - 0 - 31 - - - - - A0 - Slope of 1st piece wise linear function - 0x520 - read-write - 0x00000326 - - A0 - Slope of 1st piece wise linear function - 0 - 11 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - - - - A1 - Slope of 2nd piece wise linear function - 0x524 - read-write - 0x00000348 - - A1 - Slope of 2nd piece wise linear function - 0 - 11 - - - - - A2 - Slope of 3rd piece wise linear function - 0x528 - read-write - 0x000003AA - - - A2 - Slope of 3rd piece wise linear function - 0 - 11 - - - - - A3 - Slope of 4th piece wise linear function - 0x52C - read-write - 0x0000040E - - - A3 - Slope of 4th piece wise linear function - 0 - 11 - - - - - A4 - Slope of 5th piece wise linear function - 0x530 - read-write - 0x000004BD - - - A4 - Slope of 5th piece wise linear function - 0 - 11 - - - - - A5 - Slope of 6th piece wise linear function - 0x534 - read-write - 0x000005A3 - - - A5 - Slope of 6th piece wise linear function - 0 - 11 - - - - - B0 - y-intercept of 1st piece wise linear function - 0x540 - read-write - 0x00003FEF - - - B0 - y-intercept of 1st piece wise linear function - 0 - 13 - - - - - B1 - y-intercept of 2nd piece wise linear function - 0x544 - read-write - 0x00003FBE - - - B1 - y-intercept of 2nd piece wise linear function - 0 - 13 - - - - - B2 - y-intercept of 3rd piece wise linear function - 0x548 - read-write - 0x00003FBE - - - B2 - y-intercept of 3rd piece wise linear function - 0 - 13 - - - - - B3 - y-intercept of 4th piece wise linear function - 0x54C - read-write - 0x00000012 - - - B3 - y-intercept of 4th piece wise linear function - 0 - 13 - - - - - B4 - y-intercept of 5th piece wise linear function - 0x550 - read-write - 0x00000124 - - - B4 - y-intercept of 5th piece wise linear function - 0 - 13 - - - - - B5 - y-intercept of 6th piece wise linear function - 0x554 - read-write - 0x0000027C - - - B5 - y-intercept of 6th piece wise linear function - 0 - 13 - - - - - T0 - End point of 1st piece wise linear function - 0x560 - read-write - 0x000000E2 - - - T0 - End point of 1st piece wise linear function - 0 - 7 - - - - - T1 - End point of 2nd piece wise linear function - 0x564 - read-write - 0x00000000 - - - T1 - End point of 2nd piece wise linear function - 0 - 7 - - - - - T2 - End point of 3rd piece wise linear function - 0x568 - read-write - 0x00000019 - - - T2 - End point of 3rd piece wise linear function - 0 - 7 - - - - - T3 - End point of 4th piece wise linear function - 0x56C - read-write - 0x0000003C - - - T3 - End point of 4th piece wise linear function - 0 - 7 - - - - - T4 - End point of 5th piece wise linear function - 0x570 - read-write - 0x00000050 - - - T4 - End point of 5th piece wise linear function - 0 - 7 - - - - - - - RNG - Random Number Generator - 0x4000D000 - - 0 - 0x1000 - registers - - - RNG - 13 - - RNG - 0x20 - - - TASKS_START - Task starting the random number generator - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Task stopping the random number generator - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - EVENTS_VALRDY - Event being generated for every new random number written to the VALUE register - 0x100 - read-write - - - EVENTS_VALRDY - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - VALRDY_STOP - Shortcut between VALRDY event and STOP task - 0 - 0 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - - VALRDY - Write '1' to enable interrupt for VALRDY event - 0 - 0 + SUSPENDED + Write '1' to disable interrupt for event SUSPENDED + 18 + 18 read @@ -23527,25 +21847,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - VALRDY - Write '1' to disable interrupt for VALRDY event - 0 - 0 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 read @@ -23568,129 +21880,38 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - CONFIG - Configuration register - 0x504 - read-write - - DERCEN - Bias correction - 0 - 0 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + read Disabled - Disabled + Read: Disabled 0 Enabled - Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - VALUE - Output random number - 0x508 - read-only - - - VALUE - Generated random number - 0 - 7 - - - - - - - ECB - AES ECB Mode Encryption - 0x4000E000 - - 0 - 0x1000 - registers - - - ECB - 14 - - ECB - 0x20 - - - TASKS_STARTECB - Start ECB block encrypt - 0x000 - write-only - - - TASKS_STARTECB - 0 - 0 - - - - - TASKS_STOPECB - Abort a possible executing ECB operation - 0x004 - write-only - - - TASKS_STOPECB - 0 - 0 - - - - - EVENTS_ENDECB - ECB block encrypt complete - 0x100 - read-write - - - EVENTS_ENDECB - 0 - 0 - - - - - EVENTS_ERRORECB - ECB block encrypt aborted because of a STOPECB task or due to an error - 0x104 - read-write - - - EVENTS_ERRORECB - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - ENDECB - Write '1' to enable interrupt for ENDECB event - 0 - 0 + LASTRX + Write '1' to disable interrupt for event LASTRX + 23 + 23 read @@ -23707,17 +21928,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - ERRORECB - Write '1' to enable interrupt for ERRORECB event - 1 - 1 + LASTTX + Write '1' to disable interrupt for event LASTTX + 24 + 24 read @@ -23734,8 +21955,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 @@ -23743,61 +21964,62 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + ERRORSRC + Error source + 0x4C4 read-write + oneToClear - ENDECB - Write '1' to disable interrupt for ENDECB event + OVERRUN + Overrun error 0 0 - read - Disabled - Read: Disabled + NotReceived + Error did not occur 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Received + Error occurred 1 - ERRORECB - Write '1' to disable interrupt for ERRORECB event + ANACK + NACK received after sending the address (write '1' to clear) 1 1 - read - Disabled - Read: Disabled + NotReceived + Error did not occur 0 - Enabled - Read: Enabled + Received + Error occurred 1 + + + DNACK + NACK received after sending a data byte (write '1' to clear) + 2 + 2 - write - Clear - Disable + NotReceived + Error did not occur + 0 + + + Received + Error occurred 1 @@ -23805,185 +22027,535 @@ POSSIBILITY OF SUCH DAMAGE.\n - ECBDATAPTR - ECB block encrypt memory pointers - 0x504 + ENABLE + Enable TWIM + 0x500 read-write - ECBDATAPTR - Pointer to the ECB data structure (see Table 1 ECB data structure overview) + ENABLE + Enable or disable TWIM + 0 + 3 + + + Disabled + Disable TWIM + 0 + + + Enabled + Enable TWIM + 6 + + + + + + + PSEL + Unspecified + TWIM_PSEL + read-write + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + FREQUENCY + TWI frequency. Accuracy depends on the HFCLK source selected. + 0x524 + read-write + 0x04000000 + + + FREQUENCY + TWI master clock frequency 0 31 + + + K100 + 100 kbps + 0x01980000 + + + K250 + 250 kbps + 0x04000000 + + + K400 + 400 kbps + 0x06400000 + + + + + + + RXD + RXD EasyDMA channel + TWIM_RXD + read-write + 0x534 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in receive buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in receive buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIM_TXD + read-write + 0x544 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in transmit buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in transmit buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 2 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + ADDRESS + Address used in the TWI transfer + 0x588 + read-write + + + ADDRESS + Address used in the TWI transfer + 0 + 6 - AAR - Accelerated Address Resolver - 0x4000F000 + TWIS0 + I2C compatible Two-Wire Slave Interface with EasyDMA 0 + 0x40003000 + SPI0 + TWIS 0 0x1000 registers - CCM_AAR - 15 + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 + 3 - AAR + TWIS 0x20 - TASKS_START - Start resolving addresses based on IRKs specified in the IRK data structure - 0x000 + TASKS_STOP + Stop TWI transaction + 0x014 write-only - TASKS_START + TASKS_STOP + Stop TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Stop resolving addresses - 0x008 + TASKS_SUSPEND + Suspend TWI transaction + 0x01C write-only - TASKS_STOP + TASKS_SUSPEND + Suspend TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_END - Address resolution procedure complete - 0x100 - read-write + TASKS_RESUME + Resume TWI transaction + 0x020 + write-only - EVENTS_END + TASKS_RESUME + Resume TWI transaction 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_RESOLVED - Address resolved - 0x104 - read-write + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command + 0x030 + write-only - EVENTS_RESOLVED + TASKS_PREPARERX + Prepare the TWI slave to respond to a write command 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_NOTRESOLVED - Address not resolved - 0x108 - read-write + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command + 0x034 + write-only - EVENTS_NOTRESOLVED + TASKS_PREPARETX + Prepare the TWI slave to respond to a read command 0 0 + + + Trigger + Trigger task + 1 + + - INTENSET - Enable interrupt - 0x304 + EVENTS_STOPPED + TWI stopped + 0x104 read-write - END - Write '1' to enable interrupt for END event + EVENTS_STOPPED + TWI stopped 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_ERROR + TWI error + 0x124 + read-write + - RESOLVED - Write '1' to enable interrupt for RESOLVED event - 1 - 1 + EVENTS_ERROR + TWI error + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_RXSTARTED + Receive sequence started + 0x14C + read-write + - NOTRESOLVED - Write '1' to enable interrupt for NOTRESOLVED event - 2 - 2 + EVENTS_RXSTARTED + Receive sequence started + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_TXSTARTED + Transmit sequence started + 0x150 + read-write + + + EVENTS_TXSTARTED + Transmit sequence started + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 @@ -23991,88 +22563,95 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + EVENTS_WRITE + Write command received + 0x164 read-write - END - Write '1' to disable interrupt for END event + EVENTS_WRITE + Write command received 0 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + EVENTS_READ + Read command received + 0x168 + read-write + - RESOLVED - Write '1' to disable interrupt for RESOLVED event - 1 - 1 + EVENTS_READ + Read command received + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - NOTRESOLVED - Write '1' to disable interrupt for NOTRESOLVED event - 2 - 2 + WRITE_SUSPEND + Shortcut between event WRITE and task SUSPEND + 13 + 13 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut 1 + + + READ_SUSPEND + Shortcut between event READ and task SUSPEND + 14 + 14 - write - Clear - Disable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 @@ -24080,29 +22659,15 @@ POSSIBILITY OF SUCH DAMAGE.\n - STATUS - Resolution status - 0x400 - read-only - - - STATUS - The IRK that was used last time an address was resolved - 0 - 3 - - - - - ENABLE - Enable AAR - 0x500 + INTEN + Enable or disable interrupt + 0x300 read-write - ENABLE - Enable or disable AAR - 0 + STOPPED + Enable or disable interrupt for event STOPPED + 1 1 @@ -24113,199 +22678,96 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled Enable - 3 + 1 - - - - NIRK - Number of IRKs - 0x504 - read-write - 0x00000001 - - - NIRK - Number of Identity root keys available in the IRK data structure - 0 - 4 - - - - - IRKPTR - Pointer to IRK data structure - 0x508 - read-write - - - IRKPTR - Pointer to the IRK data structure - 0 - 31 - - - - - ADDRPTR - Pointer to the resolvable address - 0x510 - read-write - - - ADDRPTR - Pointer to the resolvable address (6-bytes) - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. - 0 - 31 - - - - - - - CCM - AES CCM Mode Encryption - 0x4000F000 - AAR - - 0 - 0x1000 - registers - - - CCM_AAR - 15 - - CCM - 0x20 - - - TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. - 0x000 - write-only - - - TASKS_KSGEN - 0 - 0 - - - - - TASKS_CRYPT - Start encryption/decryption. This operation will stop by itself when completed. - 0x004 - write-only - - - TASKS_CRYPT - 0 - 0 - - - - - TASKS_STOP - Stop encryption/decryption - 0x008 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_RATEOVERRIDE - Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption - 0x00C - write-only - - TASKS_RATEOVERRIDE - 0 - 0 + ERROR + Enable or disable interrupt for event ERROR + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - EVENTS_ENDKSGEN - Key-stream generation complete - 0x100 - read-write - - EVENTS_ENDKSGEN - 0 - 0 + RXSTARTED + Enable or disable interrupt for event RXSTARTED + 19 + 19 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - EVENTS_ENDCRYPT - Encrypt/decrypt complete - 0x104 - read-write - - EVENTS_ENDCRYPT - 0 - 0 + TXSTARTED + Enable or disable interrupt for event TXSTARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - EVENTS_ERROR - Deprecated register - CCM error event - 0x108 - read-write - - EVENTS_ERROR - 0 - 0 + WRITE + Enable or disable interrupt for event WRITE + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - SHORTS - Shortcut register - 0x200 - read-write - - ENDKSGEN_CRYPT - Shortcut between ENDKSGEN event and CRYPT task - 0 - 0 + READ + Enable or disable interrupt for event READ + 26 + 26 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 @@ -24319,10 +22781,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - ENDKSGEN - Write '1' to enable interrupt for ENDKSGEN event - 0 - 0 + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 read @@ -24346,10 +22808,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ENDCRYPT - Write '1' to enable interrupt for ENDCRYPT event - 1 - 1 + ERROR + Write '1' to enable interrupt for event ERROR + 9 + 9 read @@ -24373,10 +22835,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERROR - Write '1' to enable interrupt for ERROR event - 2 - 2 + RXSTARTED + Write '1' to enable interrupt for event RXSTARTED + 19 + 19 read @@ -24399,19 +22861,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - ENDKSGEN - Write '1' to disable interrupt for ENDKSGEN event - 0 - 0 + TXSTARTED + Write '1' to enable interrupt for event TXSTARTED + 20 + 20 read @@ -24428,17 +22882,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ENDCRYPT - Write '1' to disable interrupt for ENDCRYPT event - 1 - 1 + WRITE + Write '1' to enable interrupt for event WRITE + 25 + 25 read @@ -24455,17 +22909,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ERROR - Write '1' to disable interrupt for ERROR event - 2 - 2 + READ + Write '1' to enable interrupt for event READ + 26 + 26 read @@ -24482,8 +22936,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 @@ -24491,294 +22945,124 @@ POSSIBILITY OF SUCH DAMAGE.\n - MICSTATUS - MIC check result - 0x400 - read-only + INTENCLR + Disable interrupt + 0x308 + read-write - MICSTATUS - The result of the MIC check performed during the previous decryption operation - 0 - 0 + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + read - CheckFailed - MIC check failed + Disabled + Read: Disabled 0 - CheckPassed - MIC check passed + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ENABLE - Enable - 0x500 - read-write - - ENABLE - Enable or disable CCM - 0 - 1 + ERROR + Write '1' to disable interrupt for event ERROR + 9 + 9 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable - 2 + Read: Enabled + 1 - - - - - MODE - Operation mode - 0x504 - read-write - 0x00000001 - - - MODE - The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. - 0 - 0 + write - Encryption - AES CCM packet encryption mode - 0 - - - Decryption - AES CCM packet decryption mode + Clear + Disable 1 - DATARATE - Radio data rate that the CCM shall run synchronous with - 16 - 17 + RXSTARTED + Write '1' to disable interrupt for event RXSTARTED + 19 + 19 + read - 1Mbit - 1 Mbps + Disabled + Read: Disabled 0 - 2Mbit - 2 Mbps + Enabled + Read: Enabled 1 + + + write - 125Kbps - 125 Kbps - 2 - - - 500Kbps - 500 Kbps - 3 + Clear + Disable + 1 - LENGTH - Packet length configuration - 24 - 24 + TXSTARTED + Write '1' to disable interrupt for event TXSTARTED + 20 + 20 + read - Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Disabled + Read: Disabled 0 - Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Enabled + Read: Enabled 1 - - - - - CNFPTR - Pointer to data structure holding AES key and NONCE vector - 0x508 - read-write - - - CNFPTR - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) - 0 - 31 - - - - - INPTR - Input pointer - 0x50C - read-write - - - INPTR - Input pointer - 0 - 31 - - - - - OUTPTR - Output pointer - 0x510 - read-write - - - OUTPTR - Output pointer - 0 - 31 - - - - - SCRATCHPTR - Pointer to data area used for temporary storage - 0x514 - read-write - - - SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, - MIC generation and encryption/decryption. - 0 - 31 - - - - - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. - 0x518 - read-write - 0x000000FB - - - MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. - 0 - 7 - - - - - RATEOVERRIDE - Data rate override setting. - 0x51C - read-write - 0x00000000 - - - RATEOVERRIDE - Data rate override setting. - 0 - 1 + write - 1Mbit - 1 Mbps - 0 - - - 2Mbit - 2 Mbps + Clear + Disable 1 - - 125Kbps - 125 Kbps - 2 - - - 500Kbps - 500 Kbps - 3 - - - - - - - WDT - Watchdog Timer - 0x40010000 - - 0 - 0x1000 - registers - - - WDT - 16 - - WDT - 0x20 - - - TASKS_START - Start the watchdog - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - EVENTS_TIMEOUT - Watchdog timeout - 0x100 - read-write - - - EVENTS_TIMEOUT - 0 - 0 - - - - - INTENSET - Enable interrupt - 0x304 - read-write - - TIMEOUT - Write '1' to enable interrupt for TIMEOUT event - 0 - 0 + WRITE + Write '1' to disable interrupt for event WRITE + 25 + 25 read @@ -24795,25 +23079,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - TIMEOUT - Write '1' to disable interrupt for TIMEOUT event - 0 - 0 + READ + Write '1' to disable interrupt for event READ + 26 + 26 read @@ -24839,178 +23115,62 @@ POSSIBILITY OF SUCH DAMAGE.\n - RUNSTATUS - Run status - 0x400 - read-only - - - RUNSTATUS - Indicates whether or not the watchdog is running - 0 - 0 - - - NotRunning - Watchdog not running - 0 - - - Running - Watchdog is running - 1 - - - - - - - REQSTATUS - Request status - 0x404 - read-only - 0x00000001 + ERRORSRC + Error source + 0x4D0 + read-write + oneToClear - RR0 - Request status for RR[0] register + OVERFLOW + RX buffer overflow detected, and prevented 0 0 - DisabledOrRequested - RR[0] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[0] register is enabled, and are not yet requesting reload - 1 - - - - - RR1 - Request status for RR[1] register - 1 - 1 - - - DisabledOrRequested - RR[1] register is not enabled, or are already requesting reload + NotDetected + Error did not occur 0 - EnabledAndUnrequested - RR[1] register is enabled, and are not yet requesting reload + Detected + Error occurred 1 - RR2 - Request status for RR[2] register + DNACK + NACK sent after receiving a data byte 2 2 - DisabledOrRequested - RR[2] register is not enabled, or are already requesting reload + NotReceived + Error did not occur 0 - EnabledAndUnrequested - RR[2] register is enabled, and are not yet requesting reload + Received + Error occurred 1 - RR3 - Request status for RR[3] register + OVERREAD + TX buffer over-read detected, and prevented 3 3 - DisabledOrRequested - RR[3] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[3] register is enabled, and are not yet requesting reload - 1 - - - - - RR4 - Request status for RR[4] register - 4 - 4 - - - DisabledOrRequested - RR[4] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[4] register is enabled, and are not yet requesting reload - 1 - - - - - RR5 - Request status for RR[5] register - 5 - 5 - - - DisabledOrRequested - RR[5] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[5] register is enabled, and are not yet requesting reload - 1 - - - - - RR6 - Request status for RR[6] register - 6 - 6 - - - DisabledOrRequested - RR[6] register is not enabled, or are already requesting reload - 0 - - - EnabledAndUnrequested - RR[6] register is enabled, and are not yet requesting reload - 1 - - - - - RR7 - Request status for RR[7] register - 7 - 7 - - - DisabledOrRequested - RR[7] register is not enabled, or are already requesting reload + NotDetected + Error did not occur 0 - EnabledAndUnrequested - RR[7] register is enabled, and are not yet requesting reload + Detected + Error occurred 1 @@ -25018,212 +23178,335 @@ POSSIBILITY OF SUCH DAMAGE.\n - CRV - Counter reload value - 0x504 - read-write - 0xFFFFFFFF + MATCH + Status register indicating which address had a match + 0x4D4 + read-only - CRV - Counter reload value in number of cycles of the 32.768 kHz clock + MATCH + Which of the addresses in {ADDRESS} matched the incoming address 0 - 31 + 0 - RREN - Enable register for reload request registers - 0x508 + ENABLE + Enable TWIS + 0x500 read-write - 0x00000001 - RR0 - Enable or disable RR[0] register + ENABLE + Enable or disable TWIS 0 - 0 - - - Disabled - Disable RR[0] register - 0 - - - Enabled - Enable RR[0] register - 1 - - - - - RR1 - Enable or disable RR[1] register - 1 - 1 - - - Disabled - Disable RR[1] register - 0 - - - Enabled - Enable RR[1] register - 1 - - - - - RR2 - Enable or disable RR[2] register - 2 - 2 - - - Disabled - Disable RR[2] register - 0 - - - Enabled - Enable RR[2] register - 1 - - - - - RR3 - Enable or disable RR[3] register - 3 3 Disabled - Disable RR[3] register - 0 - - - Enabled - Enable RR[3] register - 1 - - - - - RR4 - Enable or disable RR[4] register - 4 - 4 - - - Disabled - Disable RR[4] register - 0 - - - Enabled - Enable RR[4] register - 1 - - - - - RR5 - Enable or disable RR[5] register - 5 - 5 - - - Disabled - Disable RR[5] register - 0 - - - Enabled - Enable RR[5] register - 1 - - - - - RR6 - Enable or disable RR[6] register - 6 - 6 - - - Disabled - Disable RR[6] register - 0 - - - Enabled - Enable RR[6] register - 1 - - - - - RR7 - Enable or disable RR[7] register - 7 - 7 - - - Disabled - Disable RR[7] register + Disable TWIS 0 Enabled - Enable RR[7] register - 1 + Enable TWIS + 9 - - CONFIG - Configuration register - 0x50C + + PSEL + Unspecified + TWIS_PSEL read-write - 0x00000001 - - - SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping - 0 - 0 + 0x508 + + SCL + Pin select for SCL signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDA + Pin select for SDA signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + RXD + RXD EasyDMA channel + TWIS_RXD + read-write + 0x534 + + PTR + RXD Data pointer + 0x000 + read-write + + + PTR + RXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in RXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in RXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last RXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + TXD + TXD EasyDMA channel + TWIS_TXD + read-write + 0x544 + + PTR + TXD Data pointer + 0x000 + read-write + + + PTR + TXD Data pointer + 0 + 31 + + + + + MAXCNT + Maximum number of bytes in TXD buffer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes in TXD buffer + 0 + 15 + + + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last TXD transaction + 0 + 15 + + + + + LIST + EasyDMA list type + 0x00C + read-write + + + LIST + List type + 0 + 1 + + + Disabled + Disable EasyDMA list + 0 + + + ArrayList + Use array list + 1 + + + + + + + + 0x2 + 0x4 + ADDRESS[%s] + Description collection: TWI slave address n + 0x588 + read-write + + + ADDRESS + TWI slave address + 0 + 6 + + + + + CONFIG + Configuration register for the address match mechanism + 0x594 + read-write + 0x00000001 + + + ADDRESS0 + Enable or disable address matching on ADDRESS[0] + 0 + 0 - Pause - Pause watchdog while the CPU is sleeping + Disabled + Disabled 0 - Run - Keep the watchdog running while the CPU is sleeping + Enabled + Enabled 1 - HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger - 3 - 3 + ADDRESS1 + Enable or disable address matching on ADDRESS[1] + 1 + 1 - Pause - Pause watchdog while the CPU is halted by the debugger + Disabled + Disabled 0 - Run - Keep the watchdog running while the CPU is halted by the debugger + Enabled + Enabled 1 @@ -25231,194 +23514,642 @@ POSSIBILITY OF SUCH DAMAGE.\n - 0x8 - 0x4 - RR[%s] - Description collection[n]: Reload request n - 0x600 - write-only + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. + 0x5C0 + read-write - RR - Reload request register + ORC + Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 - 31 - - - Reload - Value to request a reload of the watchdog timer - 0x6E524635 - - + 7 - - RTC1 - Real time counter 1 - 0x40011000 + + SPI1 + Serial Peripheral Interface 1 + 0x40004000 - RTC1 - 17 + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIM1 + Serial Peripheral Interface Master with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + SPIS1 + SPI Slave 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWI1 + I2C compatible Two-Wire Interface 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIM1 + I2C compatible Two-Wire Master Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 + + + + TWIS1 + I2C compatible Two-Wire Slave Interface with EasyDMA 1 + 0x40004000 + SPI1 + + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 + 4 - QDEC - Quadrature Decoder - 0x40012000 + NFCT + NFC-A compatible radio + 0x40005000 0 0x1000 registers - QDEC - 18 + NFCT + 5 - QDEC + NFCT 0x20 - TASKS_START - Task starting the quadrature decoder + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0x000 write-only - TASKS_START + TASKS_ACTIVATE + Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Task stopping the quadrature decoder + TASKS_DISABLE + Disable NFCT peripheral 0x004 write-only - TASKS_STOP + TASKS_DISABLE + Disable NFCT peripheral 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_READCLRACC - Read and clear ACC and ACCDBL + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode 0x008 write-only - TASKS_READCLRACC + TASKS_SENSE + Enable NFC sense field mode, change state to sense mode 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_RDCLRACC - Read and clear ACC + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit 0x00C write-only - TASKS_RDCLRACC + TASKS_STARTTX + Start transmission of an outgoing frame, change state to transmit 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_RDCLRDBL - Read and clear ACCDBL - 0x010 + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. + 0x01C write-only - TASKS_RDCLRDBL + TASKS_ENABLERXDATA + Initializes the EasyDMA for receive. 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_SAMPLERDY - Event being generated for every new sample value written to the SAMPLE register - 0x100 - read-write + TASKS_GOIDLE + Force state machine to IDLE state + 0x024 + write-only - EVENTS_SAMPLERDY + TASKS_GOIDLE + Force state machine to IDLE state 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_REPORTRDY - Non-null report ready - 0x104 - read-write + TASKS_GOSLEEP + Force state machine to SLEEP_A state + 0x028 + write-only - EVENTS_REPORTRDY + TASKS_GOSLEEP + Force state machine to SLEEP_A state 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_ACCOF - ACC or ACCDBL register overflow - 0x108 + EVENTS_READY + The NFCT peripheral is ready to receive and send frames + 0x100 read-write - EVENTS_ACCOF + EVENTS_READY + The NFCT peripheral is ready to receive and send frames 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_DBLRDY - Double displacement(s) detected - 0x10C + EVENTS_FIELDDETECTED + Remote NFC field detected + 0x104 read-write - EVENTS_DBLRDY + EVENTS_FIELDDETECTED + Remote NFC field detected 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_STOPPED - QDEC has been stopped - 0x110 + EVENTS_FIELDLOST + Remote NFC field lost + 0x108 read-write - EVENTS_STOPPED + EVENTS_FIELDLOST + Remote NFC field lost 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0x10C + read-write + + + EVENTS_TXFRAMESTART + Marks the start of the first symbol of a transmitted frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0x110 + read-write + + + EVENTS_TXFRAMEEND + Marks the end of the last transmitted on-air symbol of a frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0x114 + read-write + + + EVENTS_RXFRAMESTART + Marks the end of the first symbol of a received frame + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0x118 + read-write + + + EVENTS_RXFRAMEEND + Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0x11C + read-write + + + EVENTS_ERROR + NFC error reported. The ERRORSTATUS register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0x128 + read-write + + + EVENTS_RXERROR + NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0x12C + read-write + + + EVENTS_ENDRX + RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0x130 + read-write + + + EVENTS_ENDTX + Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0x138 + read-write + + + EVENTS_AUTOCOLRESSTARTED + Auto collision resolution process has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0x148 + read-write + + + EVENTS_COLLISION + NFC auto collision resolution error reported. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0x14C + read-write + + + EVENTS_SELECTED + NFC auto collision resolution successfully completed + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0x150 + read-write + + + EVENTS_STARTED + EasyDMA is ready to receive or send frames. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + SHORTS - Shortcut register + Shortcuts between local events and tasks 0x200 read-write - REPORTRDY_READCLRACC - Shortcut between REPORTRDY event and READCLRACC task + FIELDDETECTED_ACTIVATE + Shortcut between event FIELDDETECTED and task ACTIVATE 0 0 @@ -25435,8 +24166,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - SAMPLERDY_STOP - Shortcut between SAMPLERDY event and STOP task + FIELDLOST_SENSE + Shortcut between event FIELDLOST and task SENSE 1 1 @@ -25453,10 +24184,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - REPORTRDY_RDCLRACC - Shortcut between REPORTRDY event and RDCLRACC task - 2 - 2 + TXFRAMEEND_ENABLERXDATA + Shortcut between event TXFRAMEEND and task ENABLERXDATA + 5 + 5 Disabled @@ -25470,216 +24201,279 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - REPORTRDY_STOP - Shortcut between REPORTRDY event and STOP task - 3 - 3 + READY + Enable or disable interrupt for event READY + 0 + 0 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - DBLRDY_RDCLRDBL - Shortcut between DBLRDY event and RDCLRDBL task - 4 - 4 + FIELDDETECTED + Enable or disable interrupt for event FIELDDETECTED + 1 + 1 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - DBLRDY_STOP - Shortcut between DBLRDY event and STOP task - 5 - 5 + FIELDLOST + Enable or disable interrupt for event FIELDLOST + 2 + 2 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - SAMPLERDY_READCLRACC - Shortcut between SAMPLERDY event and READCLRACC task - 6 - 6 + TXFRAMESTART + Enable or disable interrupt for event TXFRAMESTART + 3 + 3 Disabled - Disable shortcut + Disable 0 Enabled - Enable shortcut + Enable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - SAMPLERDY - Write '1' to enable interrupt for SAMPLERDY event - 0 - 0 + TXFRAMEEND + Enable or disable interrupt for event TXFRAMEEND + 4 + 4 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + RXFRAMESTART + Enable or disable interrupt for event RXFRAMESTART + 5 + 5 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - REPORTRDY - Write '1' to enable interrupt for REPORTRDY event - 1 - 1 + RXFRAMEEND + Enable or disable interrupt for event RXFRAMEEND + 6 + 6 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + ERROR + Enable or disable interrupt for event ERROR + 7 + 7 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - ACCOF - Write '1' to enable interrupt for ACCOF event - 2 - 2 + RXERROR + Enable or disable interrupt for event RXERROR + 10 + 10 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + ENDRX + Enable or disable interrupt for event ENDRX + 11 + 11 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - DBLRDY - Write '1' to enable interrupt for DBLRDY event - 3 - 3 + ENDTX + Enable or disable interrupt for event ENDTX + 12 + 12 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + AUTOCOLRESSTARTED + Enable or disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - STOPPED - Write '1' to enable interrupt for STOPPED event - 4 - 4 + COLLISION + Enable or disable interrupt for event COLLISION + 18 + 18 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + SELECTED + Enable or disable interrupt for event SELECTED + 19 + 19 - write - Set + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STARTED + Enable or disable interrupt for event STARTED + 20 + 20 + + + Disabled + Disable + 0 + + + Enabled Enable 1 @@ -25688,14 +24482,14 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + INTENSET + Enable interrupt + 0x304 read-write - SAMPLERDY - Write '1' to disable interrupt for SAMPLERDY event + READY + Write '1' to enable interrupt for event READY 0 0 @@ -25714,15 +24508,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - REPORTRDY - Write '1' to disable interrupt for REPORTRDY event + FIELDDETECTED + Write '1' to enable interrupt for event FIELDDETECTED 1 1 @@ -25741,15 +24535,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - ACCOF - Write '1' to disable interrupt for ACCOF event + FIELDLOST + Write '1' to enable interrupt for event FIELDLOST 2 2 @@ -25768,15 +24562,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - DBLRDY - Write '1' to disable interrupt for DBLRDY event + TXFRAMESTART + Write '1' to enable interrupt for event TXFRAMESTART 3 3 @@ -25795,15 +24589,15 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - STOPPED - Write '1' to disable interrupt for STOPPED event + TXFRAMEEND + Write '1' to enable interrupt for event TXFRAMEEND 4 4 @@ -25822,733 +24616,484 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - ENABLE - Enable the quadrature decoder - 0x500 - read-write - - ENABLE - Enable or disable the quadrature decoder - 0 - 0 + RXFRAMESTART + Write '1' to enable interrupt for event RXFRAMESTART + 5 + 5 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - - - LEDPOL - LED output pin polarity - 0x504 - read-write - + + write + + Set + Enable + 1 + + + - LEDPOL - LED output pin polarity - 0 - 0 + RXFRAMEEND + Write '1' to enable interrupt for event RXFRAMEEND + 6 + 6 + read - ActiveLow - Led active on output pin low + Disabled + Read: Disabled 0 - ActiveHigh - Led active on output pin high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - SAMPLEPER - Sample period - 0x508 - read-write - - SAMPLEPER - Sample period. The SAMPLE register will be updated for every new sample - 0 - 3 + ERROR + Write '1' to enable interrupt for event ERROR + 7 + 7 + read - 128us - 128 us + Disabled + Read: Disabled 0 - 256us - 256 us + Enabled + Read: Enabled 1 + + + write - 512us - 512 us - 2 + Set + Enable + 1 + + + + RXERROR + Write '1' to enable interrupt for event RXERROR + 10 + 10 + + read - 1024us - 1024 us - 3 + Disabled + Read: Disabled + 0 - 2048us - 2048 us - 4 + Enabled + Read: Enabled + 1 + + + write - 4096us - 4096 us - 5 + Set + Enable + 1 + + + + ENDRX + Write '1' to enable interrupt for event ENDRX + 11 + 11 + + read - 8192us - 8192 us - 6 + Disabled + Read: Disabled + 0 - 16384us - 16384 us - 7 + Enabled + Read: Enabled + 1 + + + write - 32ms - 32768 us - 8 + Set + Enable + 1 + + + + ENDTX + Write '1' to enable interrupt for event ENDTX + 12 + 12 + + read - 65ms - 65536 us - 9 + Disabled + Read: Disabled + 0 - 131ms - 131072 us - 10 + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 - - - - SAMPLE - Motion sample value - 0x50C - read-only - int32_t - - - SAMPLE - Last motion sample - 0 - 31 - - - - - REPORTPER - Number of samples to be taken before REPORTRDY and DBLRDY events can be generated - 0x510 - read-write - - REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated - 0 - 3 + AUTOCOLRESSTARTED + Write '1' to enable interrupt for event AUTOCOLRESSTARTED + 14 + 14 + read - 10Smpl - 10 samples / report + Disabled + Read: Disabled 0 - 40Smpl - 40 samples / report + Enabled + Read: Enabled 1 + + + write - 80Smpl - 80 samples / report - 2 + Set + Enable + 1 + + + + COLLISION + Write '1' to enable interrupt for event COLLISION + 18 + 18 + + read - 120Smpl - 120 samples / report - 3 + Disabled + Read: Disabled + 0 - 160Smpl - 160 samples / report - 4 + Enabled + Read: Enabled + 1 + + + write - 200Smpl - 200 samples / report - 5 + Set + Enable + 1 + + + + SELECTED + Write '1' to enable interrupt for event SELECTED + 19 + 19 + + read - 240Smpl - 240 samples / report - 6 + Disabled + Read: Disabled + 0 - 280Smpl - 280 samples / report - 7 + Enabled + Read: Enabled + 1 + + + write - 1Smpl - 1 sample / report - 8 + Set + Enable + 1 - - - - ACC - Register accumulating the valid transitions - 0x514 - read-only - int32_t - - - ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register - 0 - 31 - - - - - ACCREAD - Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task - 0x518 - read-only - int32_t - - ACCREAD - Snapshot of the ACC register. - 0 - 31 + STARTED + Write '1' to enable interrupt for event STARTED + 20 + 20 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - PSEL - Unspecified - QDEC_PSEL - 0x51C - - LED - Pin select for LED signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - A - Pin select for A signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - B - Pin select for B signal - 0x008 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DBFEN - Enable input debounce filters - 0x528 + INTENCLR + Disable interrupt + 0x308 read-write - DBFEN - Enable input debounce filters + READY + Write '1' to disable interrupt for event READY 0 0 + read Disabled - Debounce input filters disabled + Read: Disabled 0 Enabled - Debounce input filters enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - LEDPRE - Time period the LED is switched ON prior to sampling - 0x540 - read-write - 0x00000010 - - LEDPRE - Period in us the LED is switched on prior to sampling - 0 - 8 + FIELDDETECTED + Write '1' to disable interrupt for event FIELDDETECTED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - - - - ACCDBL - Register accumulating the number of detected double transitions - 0x544 - read-only - - ACCDBL - Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). - 0 - 3 - - - - - ACCDBLREAD - Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task - 0x548 - read-only - - - ACCDBLREAD - Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. - 0 - 3 - - - - - - - COMP - Comparator - 0x40013000 - - 0 - 0x1000 - registers - - - COMP_LPCOMP - 19 - - COMP - 0x20 - - - TASKS_START - Start comparator - 0x000 - write-only - - - TASKS_START - 0 - 0 - - - - - TASKS_STOP - Stop comparator - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only - - - TASKS_SAMPLE - 0 - 0 - - - - - EVENTS_READY - COMP is ready and output is valid - 0x100 - read-write - - - EVENTS_READY - 0 - 0 - - - - - EVENTS_DOWN - Downward crossing - 0x104 - read-write - - - EVENTS_DOWN - 0 - 0 - - - - - EVENTS_UP - Upward crossing - 0x108 - read-write - - - EVENTS_UP - 0 - 0 - - - - - EVENTS_CROSS - Downward or upward crossing - 0x10C - read-write - - - EVENTS_CROSS - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - - READY_SAMPLE - Shortcut between READY event and SAMPLE task - 0 - 0 + FIELDLOST + Write '1' to disable interrupt for event FIELDLOST + 2 + 2 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - READY_STOP - Shortcut between READY event and STOP task - 1 - 1 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - DOWN_STOP - Shortcut between DOWN event and STOP task - 2 - 2 + TXFRAMESTART + Write '1' to disable interrupt for event TXFRAMESTART + 3 + 3 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - UP_STOP - Shortcut between UP event and STOP task - 3 - 3 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - CROSS_STOP - Shortcut between CROSS event and STOP task + TXFRAMEEND + Write '1' to disable interrupt for event TXFRAMEEND 4 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - READY - Enable or disable interrupt for READY event - 0 - 0 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - DOWN - Enable or disable interrupt for DOWN event - 1 - 1 + RXFRAMESTART + Write '1' to disable interrupt for event RXFRAMESTART + 5 + 5 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - UP - Enable or disable interrupt for UP event - 2 - 2 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - CROSS - Enable or disable interrupt for CROSS event - 3 - 3 + RXFRAMEEND + Write '1' to disable interrupt for event RXFRAMEEND + 6 + 6 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + ERROR + Write '1' to disable interrupt for event ERROR + 7 + 7 read @@ -26565,17 +25110,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - DOWN - Write '1' to enable interrupt for DOWN event - 1 - 1 + RXERROR + Write '1' to disable interrupt for event RXERROR + 10 + 10 read @@ -26592,17 +25137,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - UP - Write '1' to enable interrupt for UP event - 2 - 2 + ENDRX + Write '1' to disable interrupt for event ENDRX + 11 + 11 read @@ -26619,17 +25164,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - CROSS - Write '1' to enable interrupt for CROSS event - 3 - 3 + ENDTX + Write '1' to disable interrupt for event ENDTX + 12 + 12 read @@ -26646,25 +25191,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + AUTOCOLRESSTARTED + Write '1' to disable interrupt for event AUTOCOLRESSTARTED + 14 + 14 read @@ -26688,10 +25225,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - DOWN - Write '1' to disable interrupt for DOWN event - 1 - 1 + COLLISION + Write '1' to disable interrupt for event COLLISION + 18 + 18 read @@ -26715,10 +25252,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - UP - Write '1' to disable interrupt for UP event - 2 - 2 + SELECTED + Write '1' to disable interrupt for event SELECTED + 19 + 19 read @@ -26742,10 +25279,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CROSS - Write '1' to disable interrupt for CROSS event - 3 - 3 + STARTED + Write '1' to disable interrupt for event STARTED + 20 + 20 read @@ -26771,526 +25308,1028 @@ POSSIBILITY OF SUCH DAMAGE.\n - RESULT - Compare result - 0x400 - read-only + ERRORSTATUS + NFC Error Status register + 0x404 + read-write + oneToClear - RESULT - Result of last compare. Decision point SAMPLE task. + FRAMEDELAYTIMEOUT + No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 0 0 - - - Below - Input voltage is below the threshold (VIN+ &lt; VIN-) - 0 - - - Above - Input voltage is above the threshold (VIN+ &gt; VIN-) - 1 - - - - ENABLE - COMP enable - 0x500 + + FRAMESTATUS + Unspecified + NFCT_FRAMESTATUS read-write - - - ENABLE - Enable or disable COMP - 0 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable - 2 - - - - - + 0x40C + + RX + Result of last incoming frame + 0x000 + read-write + oneToClear + + + CRCERROR + No valid end of frame (EoF) detected + 0 + 0 + + + CRCCorrect + Valid CRC detected + 0 + + + CRCError + CRC received does not match local check + 1 + + + + + PARITYSTATUS + Parity status of received frame + 2 + 2 + + + ParityOK + Frame received with parity OK + 0 + + + ParityError + Frame received with parity error + 1 + + + + + OVERRUN + Overrun detected + 3 + 3 + + + NoOverrun + No overrun detected + 0 + + + Overrun + Overrun error + 1 + + + + + + - PSEL - Pin select - 0x504 - read-write + NFCTAGSTATE + NfcTag state register + 0x410 + read-only - PSEL - Analog pin select + NFCTAGSTATE + NfcTag state 0 2 - AnalogInput0 - AIN0 selected as analog input + Disabled + Disabled or sense 0 - AnalogInput1 - AIN1 selected as analog input - 1 - - - AnalogInput2 - AIN2 selected as analog input + RampUp + RampUp 2 - AnalogInput3 - AIN3 selected as analog input + Idle + Idle 3 - AnalogInput4 - AIN4 selected as analog input + Receive + Receive 4 - AnalogInput5 - AIN5 selected as analog input + FrameDelay + FrameDelay 5 - AnalogInput6 - AIN6 selected as analog input + Transmit + Transmit 6 - - AnalogInput7 - AIN7 selected as analog input - 7 - - REFSEL - Reference source select for single-ended mode - 0x508 - read-write - 0x00000004 + SLEEPSTATE + Sleep state during automatic collision resolution + 0x420 + read-only + 0x00000000 - REFSEL - Reference select + SLEEPSTATE + Reflects the sleep state during automatic collision resolution. Set to IDLE + by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a + GOSLEEP task. 0 - 2 + 0 - Int1V2 - VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) + Idle + State is IDLE. 0 - Int1V8 - VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) + SleepA + State is SLEEP_A. 1 - - Int2V4 - VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) - 2 - - - VDD - VREF = VDD - 4 - - - ARef - VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) - 5 - - EXTREFSEL - External reference select - 0x50C - read-write + FIELDPRESENT + Indicates the presence or not of a valid field + 0x43C + read-only - EXTREFSEL - External analog reference select + FIELDPRESENT + Indicates if a valid field is present. Available only in the activated state. 0 - 2 + 0 - AnalogReference0 - Use AIN0 as external analog reference + NoField + No valid field detected 0 - AnalogReference1 - Use AIN1 as external analog reference + FieldPresent + Valid field detected 1 + + + + LOCKDETECT + Indicates if the low level has locked to the field + 1 + 1 + - AnalogReference2 - Use AIN2 as external analog reference - 2 - - - AnalogReference3 - Use AIN3 as external analog reference - 3 - - - AnalogReference4 - Use AIN4 as external analog reference - 4 - - - AnalogReference5 - Use AIN5 as external analog reference - 5 - - - AnalogReference6 - Use AIN6 as external analog reference - 6 + NotLocked + Not locked to field + 0 - AnalogReference7 - Use AIN7 as external analog reference - 7 + Locked + Locked to field + 1 - TH - Threshold configuration for hysteresis unit - 0x530 + FRAMEDELAYMIN + Minimum frame delay + 0x504 read-write - 0x00000000 + 0x00000480 - THDOWN - VDOWN = (THDOWN+1)/64*VREF + FRAMEDELAYMIN + Minimum frame delay in number of 13.56 MHz clocks 0 - 5 + 15 + + + + FRAMEDELAYMAX + Maximum frame delay + 0x508 + read-write + 0x00001000 + - THUP - VUP = (THUP+1)/64*VREF - 8 - 13 + FRAMEDELAYMAX + Maximum frame delay in number of 13.56 MHz clocks + 0 + 19 - MODE - Mode configuration - 0x534 + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer + 0x50C read-write + 0x00000001 - SP - Speed and power modes + FRAMEDELAYMODE + Configuration register for the Frame Delay Timer 0 1 - Low - Low-power mode + FreeRun + Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. 0 - Normal - Normal mode + Window + Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX 1 - High - High-speed mode + ExactVal + Frame is transmitted exactly at FRAMEDELAYMAX 2 - - - - MAIN - Main operation modes - 8 - 8 - - - SE - Single-ended mode - 0 - - Diff - Differential mode - 1 + WindowGrid + Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX + 3 - HYST - Comparator hysteresis enable - 0x538 + PACKETPTR + Packet pointer for TXD and RXD data storage in Data RAM + 0x510 read-write + 0x00000000 - HYST - Comparator hysteresis + PTR + Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. 0 - 0 - - - NoHyst - Comparator hysteresis disabled - 0 - - - Hyst50mV - Comparator hysteresis enabled - 1 - - + 31 - - - - LPCOMP - Low Power Comparator - 0x40013000 - COMP - - 0 - 0x1000 - registers - - - COMP_LPCOMP - 19 - - LPCOMP - 0x20 - - TASKS_START - Start comparator - 0x000 - write-only + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each + 0x514 + read-write - TASKS_START + MAXLEN + Size of the RAM buffer allocated to TXD and RXD data storage each 0 - 0 + 8 + + TXD + Unspecified + NFCT_TXD + read-write + 0x518 + + FRAMECONFIG + Configuration of outgoing frames + 0x000 + read-write + 0x00000017 + + + PARITY + Indicates if parity is added to the frame + 0 + 0 + + + NoParity + Parity is not added to TX frames + 0 + + + Parity + Parity is added to TX frames + 1 + + + + + DISCARDMODE + Discarding unused bits at start or end of a frame + 1 + 1 + + + DiscardEnd + Unused bits are discarded at end of frame (EoF) + 0 + + + DiscardStart + Unused bits are discarded at start of frame (SoF) + 1 + + + + + SOF + Adding SoF or not in TX frames + 2 + 2 + + + NoSoF + SoF symbol not added + 0 + + + SoF + SoF symbol added + 1 + + + + + CRCMODETX + CRC mode for outgoing frames + 4 + 4 + + + NoCRCTX + CRC is not added to the frame + 0 + + + CRC16TX + 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame + 1 + + + + + + + AMOUNT + Size of outgoing frame + 0x004 + read-write + + + TXDATABITS + Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). + 0 + 2 + + + TXDATABYTES + Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + 3 + 11 + + + + + + RXD + Unspecified + NFCT_RXD + read-write + 0x520 + + FRAMECONFIG + Configuration of incoming frames + 0x000 + read-write + 0x00000015 + + + PARITY + Indicates if parity expected in RX frame + 0 + 0 + + + NoParity + Parity is not expected in RX frames + 0 + + + Parity + Parity is expected in RX frames + 1 + + + + + SOF + SoF expected or not in RX frames + 2 + 2 + + + NoSoF + SoF symbol is not expected in RX frames + 0 + + + SoF + SoF symbol is expected in RX frames + 1 + + + + + CRCMODERX + CRC mode for incoming frames + 4 + 4 + + + NoCRCRX + CRC is not expected in RX frames + 0 + + + CRC16RX + Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated + 1 + + + + + + + AMOUNT + Size of last incoming frame + 0x004 + read-only + + + RXDATABITS + Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). + 0 + 2 + + + RXDATABYTES + Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) + 3 + 11 + + + + - TASKS_STOP - Stop comparator - 0x004 - write-only + NFCID1_LAST + Last NFCID1 part (4, 7 or 10 bytes ID) + 0x590 + read-write + 0x00006363 - TASKS_STOP + NFCID1_Z + NFCID1 byte Z (very last byte sent) 0 - 0 + 7 + + + NFCID1_Y + NFCID1 byte Y + 8 + 15 + + + NFCID1_X + NFCID1 byte X + 16 + 23 + + + NFCID1_W + NFCID1 byte W + 24 + 31 - TASKS_SAMPLE - Sample comparator value - 0x008 - write-only + NFCID1_2ND_LAST + Second last NFCID1 part (7 or 10 bytes ID) + 0x594 + read-write - TASKS_SAMPLE + NFCID1_V + NFCID1 byte V 0 - 0 + 7 + + + NFCID1_U + NFCID1 byte U + 8 + 15 + + + NFCID1_T + NFCID1 byte T + 16 + 23 - EVENTS_READY - LPCOMP is ready and output is valid - 0x100 + NFCID1_3RD_LAST + Third last NFCID1 part (10 bytes ID) + 0x598 read-write - EVENTS_READY + NFCID1_S + NFCID1 byte S 0 - 0 + 7 + + + NFCID1_R + NFCID1 byte R + 8 + 15 + + + NFCID1_Q + NFCID1 byte Q + 16 + 23 - EVENTS_DOWN - Downward crossing - 0x104 + AUTOCOLRESCONFIG + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. + 0x59C read-write + 0x00000002 - EVENTS_DOWN + MODE + Enables/disables auto collision resolution 0 0 - - - + + + Enabled + Auto collision resolution enabled + 0 + + + Disabled + Auto collision resolution disabled + 1 + + + + + - EVENTS_UP - Upward crossing - 0x108 + SENSRES + NFC-A SENS_RES auto-response settings + 0x5A0 read-write + 0x00000001 - EVENTS_UP + BITFRAMESDD + Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 0 + 4 + + + SDD00000 + SDD pattern 00000 + 0 + + + SDD00001 + SDD pattern 00001 + 1 + + + SDD00010 + SDD pattern 00010 + 2 + + + SDD00100 + SDD pattern 00100 + 4 + + + SDD01000 + SDD pattern 01000 + 8 + + + SDD10000 + SDD pattern 10000 + 16 + + + + + RFU5 + Reserved for future use. Shall be 0. + 5 + 5 + + + NFCIDSIZE + NFCID1 size. This value is used by the auto collision resolution engine. + 6 + 7 + + + NFCID1Single + NFCID1 size: single (4 bytes) + 0 + + + NFCID1Double + NFCID1 size: double (7 bytes) + 1 + + + NFCID1Triple + NFCID1 size: triple (10 bytes) + 2 + + + + + PLATFCONFIG + Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 8 + 11 + + + RFU74 + Reserved for future use. Shall be 0. + 12 + 15 + + + + + SELRES + NFC-A SEL_RES auto-response settings + 0x5A4 + read-write + + + RFU10 + Reserved for future use. Shall be 0. + 0 + 1 + + + CASCADE + Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) + 2 + 2 + + + RFU43 + Reserved for future use. Shall be 0. + 3 + 4 + + + PROTOCOL + Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification + 5 + 6 + + + RFU7 + Reserved for future use. Shall be 0. + 7 + 7 + + + + + + + GPIOTE + GPIO Tasks and Events + 0x40006000 + + 0 + 0x1000 + registers + + + GPIOTE + 6 + + GPIOTE + 0x20 + + + 0x8 + 0x4 + TASKS_OUT[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. + 0x000 + write-only + + + TASKS_OUT + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_CROSS - Downward or upward crossing - 0x10C + 0x8 + 0x4 + TASKS_SET[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0x030 + write-only + + + TASKS_SET + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + TASKS_CLR[%s] + Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0x060 + write-only + + + TASKS_CLR + Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x8 + 0x4 + EVENTS_IN[%s] + Description collection: Event generated from pin specified in CONFIG[n].PSEL + 0x100 read-write - EVENTS_CROSS + EVENTS_IN + Event generated from pin specified in CONFIG[n].PSEL + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled + 0x17C + read-write + + + EVENTS_PORT + Event generated from multiple input GPIO pins with SENSE mechanism enabled 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - SHORTS - Shortcut register - 0x200 + INTENSET + Enable interrupt + 0x304 read-write - READY_SAMPLE - Shortcut between READY event and SAMPLE task + IN0 + Write '1' to enable interrupt for event IN[0] 0 0 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - READY_STOP - Shortcut between READY event and STOP task + IN1 + Write '1' to enable interrupt for event IN[1] 1 1 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - DOWN_STOP - Shortcut between DOWN event and STOP task + IN2 + Write '1' to enable interrupt for event IN[2] 2 2 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - UP_STOP - Shortcut between UP event and STOP task + IN3 + Write '1' to enable interrupt for event IN[3] 3 3 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CROSS_STOP - Shortcut between CROSS event and STOP task + IN4 + Write '1' to enable interrupt for event IN[4] 4 4 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + IN5 + Write '1' to enable interrupt for event IN[5] + 5 + 5 read @@ -27314,10 +26353,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - DOWN - Write '1' to enable interrupt for DOWN event - 1 - 1 + IN6 + Write '1' to enable interrupt for event IN[6] + 6 + 6 read @@ -27341,10 +26380,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - UP - Write '1' to enable interrupt for UP event - 2 - 2 + IN7 + Write '1' to enable interrupt for event IN[7] + 7 + 7 read @@ -27368,10 +26407,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CROSS - Write '1' to enable interrupt for CROSS event - 3 - 3 + PORT + Write '1' to enable interrupt for event PORT + 31 + 31 read @@ -27403,8 +26442,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - READY - Write '1' to disable interrupt for READY event + IN0 + Write '1' to disable interrupt for event IN[0] 0 0 @@ -27430,8 +26469,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - DOWN - Write '1' to disable interrupt for DOWN event + IN1 + Write '1' to disable interrupt for event IN[1] 1 1 @@ -27457,8 +26496,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - UP - Write '1' to disable interrupt for UP event + IN2 + Write '1' to disable interrupt for event IN[2] 2 2 @@ -27484,8 +26523,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - CROSS - Write '1' to disable interrupt for CROSS event + IN3 + Write '1' to disable interrupt for event IN[3] 3 3 @@ -27510,233 +26549,382 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - RESULT - Compare result - 0x400 - read-only - - RESULT - Result of last compare. Decision point SAMPLE task. - 0 - 0 + IN4 + Write '1' to disable interrupt for event IN[4] + 4 + 4 + read - Below - Input voltage is below the reference threshold (VIN+ &lt; VIN-). + Disabled + Read: Disabled 0 - Above - Input voltage is above the reference threshold (VIN+ &gt; VIN-). + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ENABLE - Enable LPCOMP - 0x500 - read-write - - ENABLE - Enable or disable LPCOMP - 0 - 1 + IN5 + Write '1' to disable interrupt for event IN[5] + 5 + 5 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - PSEL - Input pin select - 0x504 - read-write - - PSEL - Analog pin select - 0 - 2 + IN6 + Write '1' to disable interrupt for event IN[6] + 6 + 6 + read - AnalogInput0 - AIN0 selected as analog input + Disabled + Read: Disabled 0 - AnalogInput1 - AIN1 selected as analog input + Enabled + Read: Enabled 1 + + + write - AnalogInput2 - AIN2 selected as analog input - 2 + Clear + Disable + 1 + + + + IN7 + Write '1' to disable interrupt for event IN[7] + 7 + 7 + + read - AnalogInput3 - AIN3 selected as analog input - 3 + Disabled + Read: Disabled + 0 - AnalogInput4 - AIN4 selected as analog input - 4 + Enabled + Read: Enabled + 1 + + + write - AnalogInput5 - AIN5 selected as analog input - 5 + Clear + Disable + 1 + + + + PORT + Write '1' to disable interrupt for event PORT + 31 + 31 + + read - AnalogInput6 - AIN6 selected as analog input - 6 + Disabled + Read: Disabled + 0 - AnalogInput7 - AIN7 selected as analog input - 7 + Enabled + Read: Enabled + 1 - + + write + + Clear + Disable + 1 + + + - REFSEL - Reference select - 0x508 + 0x8 + 0x4 + CONFIG[%s] + Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + 0x510 read-write - 0x00000004 - REFSEL - Reference select + MODE + Mode 0 - 3 + 1 - Ref1_8Vdd - VDD * 1/8 selected as reference + Disabled + Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0 - Ref2_8Vdd - VDD * 2/8 selected as reference + Event + Event mode 1 - Ref3_8Vdd - VDD * 3/8 selected as reference - 2 - - - Ref4_8Vdd - VDD * 4/8 selected as reference + Task + Task mode 3 + + + + PSEL + GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + 8 + 12 + + + PORT + Port number + 13 + 13 + + + POLARITY + When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. + 16 + 17 + - Ref5_8Vdd - VDD * 5/8 selected as reference - 4 + None + Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. + 0 - Ref6_8Vdd - VDD * 6/8 selected as reference - 5 + LoToHi + Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. + 1 - Ref7_8Vdd - VDD * 7/8 selected as reference - 6 + HiToLo + Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. + 2 - ARef - External analog reference selected - 7 + Toggle + Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. + 3 + + + + OUTINIT + When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. + 20 + 20 + - Ref1_16Vdd - VDD * 1/16 selected as reference - 8 + Low + Task mode: Initial value of pin before task triggering is low + 0 - Ref3_16Vdd - VDD * 3/16 selected as reference - 9 + High + Task mode: Initial value of pin before task triggering is high + 1 + + + + + + + + SAADC + Successive approximation register (SAR) analog-to-digital converter + 0x40007000 + + 0 + 0x1000 + registers + + + SAADC + 7 + + SAADC + 0x20 + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0x000 + write-only + + + TASKS_START + Starts the SAADC and prepares the result buffer in RAM + 0 + 0 + - Ref5_16Vdd - VDD * 5/16 selected as reference - 10 + Trigger + Trigger task + 1 + + + + + + TASKS_SAMPLE + Takes one SAADC sample + 0x004 + write-only + + + TASKS_SAMPLE + Takes one SAADC sample + 0 + 0 + - Ref7_16Vdd - VDD * 7/16 selected as reference - 11 + Trigger + Trigger task + 1 + + + + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0x008 + write-only + + + TASKS_STOP + Stops the SAADC and terminates all on-going conversions + 0 + 0 + - Ref9_16Vdd - VDD * 9/16 selected as reference - 12 + Trigger + Trigger task + 1 + + + + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0x00C + write-only + + + TASKS_CALIBRATEOFFSET + Starts offset auto-calibration + 0 + 0 + - Ref11_16Vdd - VDD * 11/16 selected as reference - 13 + Trigger + Trigger task + 1 + + + + + + EVENTS_STARTED + The SAADC has started + 0x100 + read-write + + + EVENTS_STARTED + The SAADC has started + 0 + 0 + - Ref13_16Vdd - VDD * 13/16 selected as reference - 14 + NotGenerated + Event not generated + 0 - Ref15_16Vdd - VDD * 15/16 selected as reference - 15 + Generated + Event generated + 1 - EXTREFSEL - External reference select - 0x50C + EVENTS_END + The SAADC has filled up the result buffer + 0x104 read-write - EXTREFSEL - External analog reference select + EVENTS_END + The SAADC has filled up the result buffer 0 0 - AnalogReference0 - Use AIN0 as external analog reference + NotGenerated + Event not generated 0 - AnalogReference1 - Use AIN1 as external analog reference + Generated + Event generated 1 @@ -27744,111 +26932,170 @@ POSSIBILITY OF SUCH DAMAGE.\n - ANADETECT - Analog detect configuration - 0x520 + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. + 0x108 read-write - ANADETECT - Analog detect configuration + EVENTS_DONE + A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0 - 1 + 0 - Cross - Generate ANADETECT on crossing, both upward crossing and downward crossing + NotGenerated + Event not generated 0 - Up - Generate ANADETECT on upward crossing only + Generated + Event generated 1 - - Down - Generate ANADETECT on downward crossing only - 2 - - HYST - Comparator hysteresis enable - 0x538 + EVENTS_RESULTDONE + Result ready for transfer to RAM + 0x10C read-write - HYST - Comparator hysteresis enable + EVENTS_RESULTDONE + Result ready for transfer to RAM 0 0 - Disabled - Comparator hysteresis disabled + NotGenerated + Event not generated 0 - Enabled - Comparator hysteresis enabled + Generated + Event generated 1 - - - - EGU0 - Event Generator Unit 0 - 0x40014000 - EGU - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - EGU - 0x20 - - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event - 0x000 - write-only + EVENTS_CALIBRATEDONE + Calibration is complete + 0x110 + read-write - TASKS_TRIGGER + EVENTS_CALIBRATEDONE + Calibration is complete 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 + EVENTS_STOPPED + The SAADC has stopped + 0x114 read-write - EVENTS_TRIGGERED + EVENTS_STOPPED + The SAADC has stopped 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + 8 + 0x008 + EVENTS_CH[%s] + Peripheral events. + SAADC_EVENTS_CH + read-write + 0x118 + + LIMITH + Description cluster: Last result is equal or above CH[n].LIMIT.HIGH + 0x000 + read-write + + + LIMITH + Last result is equal or above CH[n].LIMIT.HIGH + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + LIMITL + Description cluster: Last result is equal or below CH[n].LIMIT.LOW + 0x004 + read-write + + + LIMITL + Last result is equal or below CH[n].LIMIT.LOW + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + INTEN Enable or disable interrupt @@ -27856,8 +27103,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - TRIGGERED0 - Enable or disable interrupt for TRIGGERED[0] event + STARTED + Enable or disable interrupt for event STARTED 0 0 @@ -27874,8 +27121,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED1 - Enable or disable interrupt for TRIGGERED[1] event + END + Enable or disable interrupt for event END 1 1 @@ -27892,8 +27139,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED2 - Enable or disable interrupt for TRIGGERED[2] event + DONE + Enable or disable interrupt for event DONE 2 2 @@ -27910,8 +27157,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED3 - Enable or disable interrupt for TRIGGERED[3] event + RESULTDONE + Enable or disable interrupt for event RESULTDONE 3 3 @@ -27928,8 +27175,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED4 - Enable or disable interrupt for TRIGGERED[4] event + CALIBRATEDONE + Enable or disable interrupt for event CALIBRATEDONE 4 4 @@ -27946,8 +27193,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED5 - Enable or disable interrupt for TRIGGERED[5] event + STOPPED + Enable or disable interrupt for event STOPPED 5 5 @@ -27964,8 +27211,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED6 - Enable or disable interrupt for TRIGGERED[6] event + CH0LIMITH + Enable or disable interrupt for event CH0LIMITH 6 6 @@ -27982,8 +27229,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED7 - Enable or disable interrupt for TRIGGERED[7] event + CH0LIMITL + Enable or disable interrupt for event CH0LIMITL 7 7 @@ -28000,8 +27247,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED8 - Enable or disable interrupt for TRIGGERED[8] event + CH1LIMITH + Enable or disable interrupt for event CH1LIMITH 8 8 @@ -28018,8 +27265,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED9 - Enable or disable interrupt for TRIGGERED[9] event + CH1LIMITL + Enable or disable interrupt for event CH1LIMITL 9 9 @@ -28036,8 +27283,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED10 - Enable or disable interrupt for TRIGGERED[10] event + CH2LIMITH + Enable or disable interrupt for event CH2LIMITH 10 10 @@ -28054,8 +27301,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED11 - Enable or disable interrupt for TRIGGERED[11] event + CH2LIMITL + Enable or disable interrupt for event CH2LIMITL 11 11 @@ -28072,8 +27319,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED12 - Enable or disable interrupt for TRIGGERED[12] event + CH3LIMITH + Enable or disable interrupt for event CH3LIMITH 12 12 @@ -28090,8 +27337,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED13 - Enable or disable interrupt for TRIGGERED[13] event + CH3LIMITL + Enable or disable interrupt for event CH3LIMITL 13 13 @@ -28108,8 +27355,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED14 - Enable or disable interrupt for TRIGGERED[14] event + CH4LIMITH + Enable or disable interrupt for event CH4LIMITH 14 14 @@ -28126,8 +27373,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED15 - Enable or disable interrupt for TRIGGERED[15] event + CH4LIMITL + Enable or disable interrupt for event CH4LIMITL 15 15 @@ -28143,100 +27390,127 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENSET - Enable interrupt - 0x304 - read-write - - TRIGGERED0 - Write '1' to enable interrupt for TRIGGERED[0] event - 0 - 0 + CH5LIMITH + Enable or disable interrupt for event CH5LIMITH + 16 + 16 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + CH5LIMITL + Enable or disable interrupt for event CH5LIMITL + 17 + 17 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - TRIGGERED1 - Write '1' to enable interrupt for TRIGGERED[1] event - 1 - 1 + CH6LIMITH + Enable or disable interrupt for event CH6LIMITH + 18 + 18 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + CH6LIMITL + Enable or disable interrupt for event CH6LIMITL + 19 + 19 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 - TRIGGERED2 - Write '1' to enable interrupt for TRIGGERED[2] event - 2 - 2 + CH7LIMITH + Enable or disable interrupt for event CH7LIMITH + 20 + 20 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + CH7LIMITL + Enable or disable interrupt for event CH7LIMITL + 21 + 21 - write - Set + Disabled + Disable + 0 + + + Enabled Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - TRIGGERED3 - Write '1' to enable interrupt for TRIGGERED[3] event - 3 - 3 + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 read @@ -28260,10 +27534,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED4 - Write '1' to enable interrupt for TRIGGERED[4] event - 4 - 4 + END + Write '1' to enable interrupt for event END + 1 + 1 read @@ -28287,10 +27561,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED5 - Write '1' to enable interrupt for TRIGGERED[5] event - 5 - 5 + DONE + Write '1' to enable interrupt for event DONE + 2 + 2 read @@ -28314,11 +27588,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED6 - Write '1' to enable interrupt for TRIGGERED[6] event - 6 - 6 - + RESULTDONE + Write '1' to enable interrupt for event RESULTDONE + 3 + 3 + read Disabled @@ -28341,8 +27615,89 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED7 - Write '1' to enable interrupt for TRIGGERED[7] event + CALIBRATEDONE + Write '1' to enable interrupt for event CALIBRATEDONE + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITH + Write '1' to enable interrupt for event CH0LIMITH + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + CH0LIMITL + Write '1' to enable interrupt for event CH0LIMITL 7 7 @@ -28368,8 +27723,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED8 - Write '1' to enable interrupt for TRIGGERED[8] event + CH1LIMITH + Write '1' to enable interrupt for event CH1LIMITH 8 8 @@ -28395,8 +27750,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED9 - Write '1' to enable interrupt for TRIGGERED[9] event + CH1LIMITL + Write '1' to enable interrupt for event CH1LIMITL 9 9 @@ -28422,8 +27777,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED10 - Write '1' to enable interrupt for TRIGGERED[10] event + CH2LIMITH + Write '1' to enable interrupt for event CH2LIMITH 10 10 @@ -28449,8 +27804,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED11 - Write '1' to enable interrupt for TRIGGERED[11] event + CH2LIMITL + Write '1' to enable interrupt for event CH2LIMITL 11 11 @@ -28476,8 +27831,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED12 - Write '1' to enable interrupt for TRIGGERED[12] event + CH3LIMITH + Write '1' to enable interrupt for event CH3LIMITH 12 12 @@ -28503,8 +27858,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED13 - Write '1' to enable interrupt for TRIGGERED[13] event + CH3LIMITL + Write '1' to enable interrupt for event CH3LIMITL 13 13 @@ -28530,8 +27885,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED14 - Write '1' to enable interrupt for TRIGGERED[14] event + CH4LIMITH + Write '1' to enable interrupt for event CH4LIMITH 14 14 @@ -28557,8 +27912,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED15 - Write '1' to enable interrupt for TRIGGERED[15] event + CH4LIMITL + Write '1' to enable interrupt for event CH4LIMITL 15 15 @@ -28583,19 +27938,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - TRIGGERED0 - Write '1' to disable interrupt for TRIGGERED[0] event - 0 - 0 + CH5LIMITH + Write '1' to enable interrupt for event CH5LIMITH + 16 + 16 read @@ -28612,17 +27959,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED1 - Write '1' to disable interrupt for TRIGGERED[1] event - 1 - 1 + CH5LIMITL + Write '1' to enable interrupt for event CH5LIMITL + 17 + 17 read @@ -28639,17 +27986,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED2 - Write '1' to disable interrupt for TRIGGERED[2] event - 2 - 2 + CH6LIMITH + Write '1' to enable interrupt for event CH6LIMITH + 18 + 18 read @@ -28666,17 +28013,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED3 - Write '1' to disable interrupt for TRIGGERED[3] event - 3 - 3 + CH6LIMITL + Write '1' to enable interrupt for event CH6LIMITL + 19 + 19 read @@ -28693,17 +28040,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED4 - Write '1' to disable interrupt for TRIGGERED[4] event - 4 - 4 + CH7LIMITH + Write '1' to enable interrupt for event CH7LIMITH + 20 + 20 read @@ -28720,17 +28067,52 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED5 - Write '1' to disable interrupt for TRIGGERED[5] event - 5 - 5 + CH7LIMITL + Write '1' to enable interrupt for event CH7LIMITL + 21 + 21 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 read @@ -28754,10 +28136,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED6 - Write '1' to disable interrupt for TRIGGERED[6] event - 6 - 6 + END + Write '1' to disable interrupt for event END + 1 + 1 read @@ -28781,10 +28163,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED7 - Write '1' to disable interrupt for TRIGGERED[7] event - 7 - 7 + DONE + Write '1' to disable interrupt for event DONE + 2 + 2 read @@ -28808,10 +28190,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED8 - Write '1' to disable interrupt for TRIGGERED[8] event - 8 - 8 + RESULTDONE + Write '1' to disable interrupt for event RESULTDONE + 3 + 3 read @@ -28835,10 +28217,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED9 - Write '1' to disable interrupt for TRIGGERED[9] event - 9 - 9 + CALIBRATEDONE + Write '1' to disable interrupt for event CALIBRATEDONE + 4 + 4 read @@ -28862,10 +28244,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED10 - Write '1' to disable interrupt for TRIGGERED[10] event - 10 - 10 + STOPPED + Write '1' to disable interrupt for event STOPPED + 5 + 5 read @@ -28889,10 +28271,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED11 - Write '1' to disable interrupt for TRIGGERED[11] event - 11 - 11 + CH0LIMITH + Write '1' to disable interrupt for event CH0LIMITH + 6 + 6 read @@ -28916,10 +28298,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED12 - Write '1' to disable interrupt for TRIGGERED[12] event - 12 - 12 + CH0LIMITL + Write '1' to disable interrupt for event CH0LIMITL + 7 + 7 read @@ -28943,10 +28325,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED13 - Write '1' to disable interrupt for TRIGGERED[13] event - 13 - 13 + CH1LIMITH + Write '1' to disable interrupt for event CH1LIMITH + 8 + 8 read @@ -28970,10 +28352,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED14 - Write '1' to disable interrupt for TRIGGERED[14] event - 14 - 14 + CH1LIMITL + Write '1' to disable interrupt for event CH1LIMITL + 9 + 9 read @@ -28997,10 +28379,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED15 - Write '1' to disable interrupt for TRIGGERED[15] event - 15 - 15 + CH2LIMITH + Write '1' to disable interrupt for event CH2LIMITH + 10 + 10 read @@ -29023,520 +28405,173 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - - - SWI0 - Software interrupt 0 - 0x40014000 - EGU0 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - SWI - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - EGU1 - Event Generator Unit 1 - 0x40015000 - - SWI1_EGU1 - 21 - - - - SWI1 - Software interrupt 1 - 0x40015000 - EGU1 - - SWI1_EGU1 - 21 - - - - EGU2 - Event Generator Unit 2 - 0x40016000 - - SWI2_EGU2 - 22 - - - - SWI2 - Software interrupt 2 - 0x40016000 - EGU2 - - SWI2_EGU2 - 22 - - - - EGU3 - Event Generator Unit 3 - 0x40017000 - - SWI3_EGU3 - 23 - - - - SWI3 - Software interrupt 3 - 0x40017000 - EGU3 - - SWI3_EGU3 - 23 - - - - EGU4 - Event Generator Unit 4 - 0x40018000 - - SWI4_EGU4 - 24 - - - - SWI4 - Software interrupt 4 - 0x40018000 - EGU4 - - SWI4_EGU4 - 24 - - - - EGU5 - Event Generator Unit 5 - 0x40019000 - - SWI5_EGU5 - 25 - - - - SWI5 - Software interrupt 5 - 0x40019000 - EGU5 - - SWI5_EGU5 - 25 - - - - TIMER3 - Timer/Counter 3 - 0x4001A000 - - TIMER3 - 26 - - - - TIMER4 - Timer/Counter 4 - 0x4001B000 - - TIMER4 - 27 - - - - PWM0 - Pulse width modulation unit 0 - 0x4001C000 - PWM - - 0 - 0x1000 - registers - - - PWM0 - 28 - - PWM - 0x20 - - - TASKS_STOP - Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback - 0x004 - write-only - - - TASKS_STOP - 0 - 0 - - - - - 0x2 - 0x4 - TASKS_SEQSTART[%s] - Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. - 0x008 - write-only - - - TASKS_SEQSTART - 0 - 0 - - - - - TASKS_NEXTSTEP - Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. - 0x010 - write-only - - - TASKS_NEXTSTEP - 0 - 0 - - - - - EVENTS_STOPPED - Response to STOP task, emitted when PWM pulses are no longer generated - 0x104 - read-write - - - EVENTS_STOPPED - 0 - 0 - - - - - 0x2 - 0x4 - EVENTS_SEQSTARTED[%s] - Description collection[n]: First PWM period started on sequence n - 0x108 - read-write - - - EVENTS_SEQSTARTED - 0 - 0 - - - - - 0x2 - 0x4 - EVENTS_SEQEND[%s] - Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter - 0x110 - read-write - - - EVENTS_SEQEND - 0 - 0 - - - - - EVENTS_PWMPERIODEND - Emitted at the end of each PWM period - 0x118 - read-write - - - EVENTS_PWMPERIODEND - 0 - 0 - - - - - EVENTS_LOOPSDONE - Concatenated sequences have been played the amount of times defined in LOOP.CNT - 0x11C - read-write - - - EVENTS_LOOPSDONE - 0 - 0 - - - - - SHORTS - Shortcut register - 0x200 - read-write - - SEQEND0_STOP - Shortcut between SEQEND[0] event and STOP task - 0 - 0 + CH2LIMITL + Write '1' to disable interrupt for event CH2LIMITL + 11 + 11 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - SEQEND1_STOP - Shortcut between SEQEND[1] event and STOP task - 1 - 1 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - LOOPSDONE_SEQSTART0 - Shortcut between LOOPSDONE event and SEQSTART[0] task - 2 - 2 + CH3LIMITH + Write '1' to disable interrupt for event CH3LIMITH + 12 + 12 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - LOOPSDONE_SEQSTART1 - Shortcut between LOOPSDONE event and SEQSTART[1] task - 3 - 3 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Clear + Disable 1 - LOOPSDONE_STOP - Shortcut between LOOPSDONE event and STOP task - 4 - 4 + CH3LIMITL + Write '1' to disable interrupt for event CH3LIMITL + 13 + 13 + read Disabled - Disable shortcut + Read: Disabled 0 Enabled - Enable shortcut + Read: Enabled 1 - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - STOPPED - Enable or disable interrupt for STOPPED event - 1 - 1 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - SEQSTARTED0 - Enable or disable interrupt for SEQSTARTED[0] event - 2 - 2 + CH4LIMITH + Write '1' to disable interrupt for event CH4LIMITH + 14 + 14 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - SEQSTARTED1 - Enable or disable interrupt for SEQSTARTED[1] event - 3 - 3 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - SEQEND0 - Enable or disable interrupt for SEQEND[0] event - 4 - 4 + CH4LIMITL + Write '1' to disable interrupt for event CH4LIMITL + 15 + 15 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - SEQEND1 - Enable or disable interrupt for SEQEND[1] event - 5 - 5 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - PWMPERIODEND - Enable or disable interrupt for PWMPERIODEND event - 6 - 6 + CH5LIMITH + Write '1' to disable interrupt for event CH5LIMITH + 16 + 16 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - LOOPSDONE - Enable or disable interrupt for LOOPSDONE event - 7 - 7 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + CH5LIMITL + Write '1' to disable interrupt for event CH5LIMITL + 17 + 17 read @@ -29553,17 +28588,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - SEQSTARTED0 - Write '1' to enable interrupt for SEQSTARTED[0] event - 2 - 2 + CH6LIMITH + Write '1' to disable interrupt for event CH6LIMITH + 18 + 18 read @@ -29580,17 +28615,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - SEQSTARTED1 - Write '1' to enable interrupt for SEQSTARTED[1] event - 3 - 3 + CH6LIMITL + Write '1' to disable interrupt for event CH6LIMITL + 19 + 19 read @@ -29607,17 +28642,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - SEQEND0 - Write '1' to enable interrupt for SEQEND[0] event - 4 - 4 + CH7LIMITH + Write '1' to disable interrupt for event CH7LIMITH + 20 + 20 read @@ -29634,17 +28669,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - SEQEND1 - Write '1' to enable interrupt for SEQEND[1] event - 5 - 5 + CH7LIMITL + Write '1' to disable interrupt for event CH7LIMITL + 21 + 21 read @@ -29661,259 +28696,34 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 + + + + STATUS + Status + 0x400 + read-only + - PWMPERIODEND - Write '1' to enable interrupt for PWMPERIODEND event - 6 - 6 + STATUS + Status + 0 + 0 - read - Disabled - Read: Disabled + Ready + SAADC is ready. No on-going conversions. 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - LOOPSDONE - Write '1' to enable interrupt for LOOPSDONE event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED0 - Write '1' to disable interrupt for SEQSTARTED[0] event - 2 - 2 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQSTARTED1 - Write '1' to disable interrupt for SEQSTARTED[1] event - 3 - 3 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND0 - Write '1' to disable interrupt for SEQEND[0] event - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - SEQEND1 - Write '1' to disable interrupt for SEQEND[1] event - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - PWMPERIODEND - Write '1' to disable interrupt for PWMPERIODEND event - 6 - 6 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - LOOPSDONE - Write '1' to disable interrupt for LOOPSDONE event - 7 - 7 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Busy + SAADC is busy. Conversion in progress. 1 @@ -29922,332 +28732,584 @@ POSSIBILITY OF SUCH DAMAGE.\n ENABLE - PWM module enable register + Enable or disable SAADC 0x500 read-write - 0x00000000 ENABLE - Enable or disable PWM module + Enable or disable SAADC 0 0 Disabled - Disabled + Disable SAADC 0 Enabled - Enable - 1 - - - - - - - MODE - Selects operating mode of the wave counter - 0x504 - read-write - 0x00000000 - - - UPDOWN - Selects up mode or up-and-down mode for the counter - 0 - 0 - - - Up - Up counter, edge-aligned PWM duty cycle - 0 - - - UpAndDown - Up and down counter, center-aligned PWM duty cycle - 1 - - - - - - - COUNTERTOP - Value up to which the pulse generator counter counts - 0x508 - read-write - 0x000003FF - - - COUNTERTOP - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. - 0 - 14 - - - - - PRESCALER - Configuration for PWM_CLK - 0x50C - read-write - 0x00000000 - - - PRESCALER - Prescaler of PWM_CLK - 0 - 2 - - - DIV_1 - Divide by 1 (16 MHz) - 0 - - - DIV_2 - Divide by 2 (8 MHz) - 1 - - - DIV_4 - Divide by 4 (4 MHz) - 2 - - - DIV_8 - Divide by 8 (2 MHz) - 3 - - - DIV_16 - Divide by 16 (1 MHz) - 4 - - - DIV_32 - Divide by 32 (500 kHz) - 5 - - - DIV_64 - Divide by 64 (250 kHz) - 6 - - - DIV_128 - Divide by 128 (125 kHz) - 7 - - - - - - - DECODER - Configuration of the decoder - 0x510 - read-write - 0x00000000 - - - LOAD - How a sequence is read from RAM and spread to the compare register - 0 - 1 - - - Common - 1st half word (16-bit) used in all PWM channels 0..3 - 0 - - - Grouped - 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 - - - Individual - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 - - - WaveForm - 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 - - - - - MODE - Selects source for advancing the active sequence - 8 - 8 - - - RefreshCount - SEQ[n].REFRESH is used to determine loading internal compare registers - 0 - - - NextStep - NEXTSTEP task causes a new value to be loaded to internal compare registers + Enable SAADC 1 - - LOOP - Number of playbacks of a loop - 0x514 - read-write - 0x00000000 - - - CNT - Number of playbacks of pattern cycles - 0 - 15 - - - Disabled - Looping disabled (stop at the end of the sequence) - 0 - - - - - - 2 - 0x020 - SEQ[%s] + 8 + 0x010 + CH[%s] Unspecified - PWM_SEQ - 0x520 + SAADC_CH + read-write + 0x510 - PTR - Description cluster[n]: Beginning address in RAM of this sequence + PSELP + Description cluster: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 - PTR - Beginning address in RAM of this sequence - 0 - 31 - - - - - CNT - Description cluster[n]: Number of values (duty cycles) in this sequence - 0x004 - read-write - 0x00000000 - - - CNT - Number of values (duty cycles) in this sequence + PSELP + Analog positive input channel 0 - 14 + 4 - Disabled - Sequence is disabled, and shall not be started as it is empty + NC + Not connected 0 + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + - REFRESH - Description cluster[n]: Number of additional PWM periods between samples loaded into compare register - 0x008 + PSELN + Description cluster: Input negative pin selection for CH[n] + 0x004 read-write - 0x00000001 + 0x00000000 - CNT - Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) + PSELN + Analog negative input, enables differential channel 0 - 23 + 4 - Continuous - Update every PWM period + NC + Not connected 0 - + + AnalogInput0 + AIN0 + 1 + + + AnalogInput1 + AIN1 + 2 + + + AnalogInput2 + AIN2 + 3 + + + AnalogInput3 + AIN3 + 4 + + + AnalogInput4 + AIN4 + 5 + + + AnalogInput5 + AIN5 + 6 + + + AnalogInput6 + AIN6 + 7 + + + AnalogInput7 + AIN7 + 8 + + + VDD + VDD + 9 + + + VDDHDIV5 + VDDH/5 + 0x0D + + - ENDDELAY - Description cluster[n]: Time added after the sequence + CONFIG + Description cluster: Input configuration for CH[n] + 0x008 + read-write + 0x00020000 + + + RESP + Positive channel resistor control + 0 + 1 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + RESN + Negative channel resistor control + 4 + 5 + + + Bypass + Bypass resistor ladder + 0 + + + Pulldown + Pull-down to GND + 1 + + + Pullup + Pull-up to VDD + 2 + + + VDD1_2 + Set input at VDD/2 + 3 + + + + + GAIN + Gain control + 8 + 10 + + + Gain1_6 + 1/6 + 0 + + + Gain1_5 + 1/5 + 1 + + + Gain1_4 + 1/4 + 2 + + + Gain1_3 + 1/3 + 3 + + + Gain1_2 + 1/2 + 4 + + + Gain1 + 1 + 5 + + + Gain2 + 2 + 6 + + + Gain4 + 4 + 7 + + + + + REFSEL + Reference control + 12 + 12 + + + Internal + Internal reference (0.6 V) + 0 + + + VDD1_4 + VDD/4 as reference + 1 + + + + + TACQ + Acquisition time, the time the SAADC uses to sample the input voltage + 16 + 18 + + + 3us + 3 us + 0 + + + 5us + 5 us + 1 + + + 10us + 10 us + 2 + + + 15us + 15 us + 3 + + + 20us + 20 us + 4 + + + 40us + 40 us + 5 + + + + + MODE + Enable differential mode + 20 + 20 + + + SE + Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND + 0 + + + Diff + Differential + 1 + + + + + BURST + Enable burst mode + 24 + 24 + + + Disabled + Burst mode is disabled (normal operation) + 0 + + + Enabled + Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. + 1 + + + + + + + LIMIT + Description cluster: High/low limits for event monitoring of a channel 0x00C read-write - 0x00000000 + 0x7FFF8000 - CNT - Time added after the sequence in PWM periods + LOW + Low level limit 0 - 23 + 15 + + + HIGH + High level limit + 16 + 31 + + RESOLUTION + Resolution configuration + 0x5F0 + read-write + 0x00000001 + + + VAL + Set the resolution + 0 + 2 + + + 8bit + 8 bits + 0 + + + 10bit + 10 bits + 1 + + + 12bit + 12 bits + 2 + + + 14bit + 14 bits + 3 + + + + + + + OVERSAMPLE + Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. + 0x5F4 + read-write + + + OVERSAMPLE + Oversample control + 0 + 3 + + + Bypass + Bypass oversampling + 0 + + + Over2x + Oversample 2x + 1 + + + Over4x + Oversample 4x + 2 + + + Over8x + Oversample 8x + 3 + + + Over16x + Oversample 16x + 4 + + + Over32x + Oversample 32x + 5 + + + Over64x + Oversample 64x + 6 + + + Over128x + Oversample 128x + 7 + + + Over256x + Oversample 256x + 8 + + + + + + + SAMPLERATE + Controls normal or continuous sample rate + 0x5F8 + read-write + + + CC + Capture and compare value. Sample rate is 16 MHz/CC + 0 + 10 + + + MODE + Select mode for sample rate control + 12 + 12 + + + Task + Rate is controlled from SAMPLE task + 0 + + + Timers + Rate is controlled from local timer (use CC to control the rate) + 1 + + + + + - PSEL - Unspecified - PWM_PSEL - 0x560 + RESULT + RESULT EasyDMA channel + SAADC_RESULT + read-write + 0x62C - 0x4 - 0x4 - OUT[%s] - Description collection[n]: Output pin select for PWM channel n + PTR + Data pointer 0x000 read-write - 0xFFFFFFFF - PIN - Pin number + PTR + Data pointer 0 - 4 + 31 + + + + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0x004 + read-write + - PORT - Port number - 5 - 5 + MAXCNT + Maximum number of 16-bit samples to be written to output RAM buffer + 0 + 14 + + + + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task + 0x008 + read-only + - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - + AMOUNT + Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. + 0 + 14 @@ -30255,142 +29317,396 @@ POSSIBILITY OF SUCH DAMAGE.\n - PDM - Pulse Density Modulation (Digital Microphone) Interface - 0x4001D000 + TIMER0 + Timer/Counter 0 + 0x40008000 + TIMER 0 0x1000 registers - PDM - 29 + TIMER0 + 8 - PDM + TIMER 0x20 TASKS_START - Starts continuous PDM transfer + Start Timer 0x000 write-only TASKS_START + Start Timer 0 0 + + + Trigger + Trigger task + 1 + + TASKS_STOP - Stops PDM transfer + Stop Timer 0x004 write-only TASKS_STOP + Stop Timer 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_STARTED - PDM transfer has started - 0x100 - read-write + TASKS_COUNT + Increment Timer (Counter mode only) + 0x008 + write-only - EVENTS_STARTED + TASKS_COUNT + Increment Timer (Counter mode only) 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_STOPPED - PDM transfer has finished - 0x104 - read-write + TASKS_CLEAR + Clear time + 0x00C + write-only - EVENTS_STOPPED + TASKS_CLEAR + Clear time 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_END - The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM - 0x108 + TASKS_SHUTDOWN + Deprecated register - Shut down timer + 0x010 + write-only + + + TASKS_SHUTDOWN + Deprecated field - Shut down timer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + TASKS_CAPTURE[%s] + Description collection: Capture Timer value to CC[n] register + 0x040 + write-only + + + TASKS_CAPTURE + Capture Timer value to CC[n] register + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + 0x6 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 read-write - EVENTS_END + EVENTS_COMPARE + Compare event on CC[n] match 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - INTEN - Enable or disable interrupt - 0x300 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - STARTED - Enable or disable interrupt for STARTED event + COMPARE0_CLEAR + Shortcut between event COMPARE[0] and task CLEAR 0 0 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - STOPPED - Enable or disable interrupt for STOPPED event + COMPARE1_CLEAR + Shortcut between event COMPARE[1] and task CLEAR 1 1 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - END - Enable or disable interrupt for END event + COMPARE2_CLEAR + Shortcut between event COMPARE[2] and task CLEAR 2 2 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut + 1 + + + + + COMPARE3_CLEAR + Shortcut between event COMPARE[3] and task CLEAR + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_CLEAR + Shortcut between event COMPARE[4] and task CLEAR + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_CLEAR + Shortcut between event COMPARE[5] and task CLEAR + 5 + 5 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE0_STOP + Shortcut between event COMPARE[0] and task STOP + 8 + 8 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE1_STOP + Shortcut between event COMPARE[1] and task STOP + 9 + 9 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE2_STOP + Shortcut between event COMPARE[2] and task STOP + 10 + 10 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE3_STOP + Shortcut between event COMPARE[3] and task STOP + 11 + 11 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE4_STOP + Shortcut between event COMPARE[4] and task STOP + 12 + 12 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + COMPARE5_STOP + Shortcut between event COMPARE[5] and task STOP + 13 + 13 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 @@ -30404,10 +29720,10 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - STARTED - Write '1' to enable interrupt for STARTED event - 0 - 0 + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 read @@ -30431,10 +29747,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to enable interrupt for STOPPED event - 1 - 1 + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 read @@ -30458,10 +29774,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - END - Write '1' to enable interrupt for END event - 2 - 2 + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 read @@ -30484,19 +29800,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - STARTED - Write '1' to disable interrupt for STARTED event - 0 - 0 + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 read @@ -30513,17 +29821,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - STOPPED - Write '1' to disable interrupt for STOPPED event - 1 - 1 + COMPARE4 + Write '1' to enable interrupt for event COMPARE[4] + 20 + 20 read @@ -30540,17 +29848,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - END - Write '1' to disable interrupt for END event - 2 - 2 + COMPARE5 + Write '1' to enable interrupt for event COMPARE[5] + 21 + 21 read @@ -30567,8 +29875,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 @@ -30576,472 +29884,325 @@ POSSIBILITY OF SUCH DAMAGE.\n - ENABLE - PDM module enable register - 0x500 + INTENCLR + Disable interrupt + 0x308 read-write - 0x00000000 - ENABLE - Enable or disable PDM module - 0 - 0 + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - PDMCLKCTRL - PDM clock generator control - 0x504 - read-write - 0x08400000 - - FREQ - PDM_CLK frequency - 0 - 31 + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + read - 1000K - PDM_CLK = 32 MHz / 32 = 1.000 MHz - 0x08000000 + Disabled + Read: Disabled + 0 - Default - PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. - 0x08400000 + Enabled + Read: Enabled + 1 + + + write - 1067K - PDM_CLK = 32 MHz / 30 = 1.067 MHz - 0x08800000 + Clear + Disable + 1 + + + + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + + read - 1231K - PDM_CLK = 32 MHz / 26 = 1.231 MHz - 0x09800000 + Disabled + Read: Disabled + 0 - 1280K - PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. - 0x0A000000 + Enabled + Read: Enabled + 1 + + + write - 1333K - PDM_CLK = 32 MHz / 24 = 1.333 MHz - 0x0A800000 + Clear + Disable + 1 - - - - MODE - Defines the routing of the connected PDM microphones' signals - 0x508 - read-write - 0x00000000 - - OPERATION - Mono or stereo operation - 0 - 0 + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + read - Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Disabled + Read: Disabled 0 - Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled - 1 - 1 + COMPARE4 + Write '1' to disable interrupt for event COMPARE[4] + 20 + 20 + read - LeftFalling - Left (or mono) is sampled on falling edge of PDM_CLK + Disabled + Read: Disabled 0 - LeftRising - Left (or mono) is sampled on rising edge of PDM_CLK + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - GAINL - Left output gain adjustment - 0x518 - read-write - 0x00000028 - - GAINL - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust - 0 - 6 + COMPARE5 + Write '1' to disable interrupt for event COMPARE[5] + 21 + 21 + read - MinGain - -20dB gain adjustment (minimum) - 0x00 + Disabled + Read: Disabled + 0 - DefaultGain - 0dB gain adjustment - 0x28 + Enabled + Read: Enabled + 1 + + + write - MaxGain - +20dB gain adjustment (maximum) - 0x50 + Clear + Disable + 1 - GAINR - Right output gain adjustment - 0x51C + MODE + Timer mode selection + 0x504 read-write - 0x00000028 - GAINR - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + MODE + Timer mode 0 - 6 + 1 - MinGain - -20dB gain adjustment (minimum) - 0x00 + Timer + Select Timer mode + 0 - DefaultGain - 0dB gain adjustment - 0x28 + Counter + Deprecated enumerator - Select Counter mode + 1 - MaxGain - +20dB gain adjustment (maximum) - 0x50 + LowPowerCounter + Select Low Power Counter mode + 2 - RATIO - Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. - 0x520 + BITMODE + Configure the number of bits used by the TIMER + 0x508 read-write - 0x00000000 - RATIO - Selects the ratio between PDM_CLK and output sample rate + BITMODE + Timer bit width 0 - 0 + 1 - Ratio64 - Ratio of 64 + 16Bit + 16 bit timer bit width 0 - Ratio80 - Ratio of 80 + 08Bit + 8 bit timer bit width 1 + + 24Bit + 24 bit timer bit width + 2 + + + 32Bit + 32 bit timer bit width + 3 + - - PSEL - Unspecified - PDM_PSEL + + PRESCALER + Timer prescaler register + 0x510 + read-write + 0x00000004 + + + PRESCALER + Prescaler value + 0 + 3 + + + + + 0x6 + 0x4 + CC[%s] + Description collection: Capture/Compare register n 0x540 - - CLK - Pin number configuration for PDM CLK signal - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - DIN - Pin number configuration for PDM DIN signal - 0x004 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - - CONNECT - Connection - 31 - 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - - - - - - SAMPLE - Unspecified - PDM_SAMPLE - 0x560 - - PTR - RAM address pointer to write samples to with EasyDMA - 0x000 - read-write - - - SAMPLEPTR - Address to write PDM samples to over DMA - 0 - 31 - - - - - MAXCNT - Number of samples to allocate memory for in EasyDMA mode - 0x004 - read-write - - - BUFFSIZE - Length of DMA RAM allocation in number of samples - 0 - 14 - - - - + read-write + + + CC + Capture/Compare value + 0 + 31 + + + - - ACL - Access control lists - 0x4001E000 - - 0 - 0x1000 - registers - - ACL - 0x20 - - - 8 - 0x010 - ACL[%s] - Unspecified - ACL_ACL - 0x800 - - ADDR - Description cluster[n]: Configure the word-aligned start address of region n to protect - 0x000 - read-write - 0x00000000 - - - ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. - 0 - 31 - - - - - SIZE - Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. - 0x004 - read-write - 0x00000000 - - - SIZE - Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. - 0 - 31 - - - - - PERM - Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE - 0x008 - read-write - 0x00000000 - - - WRITE - Configure write and erase permissions for region n. Write '0' has no effect. - 1 - 1 - - - Enable - Allow write and erase instructions to region n - 0 - - - Disable - Block write and erase instructions to region n - 1 - - - - - READ - Configure read permissions for region n. Write '0' has no effect. - 2 - 2 - - - Enable - Allow read instructions to region n - 0 - - - Disable - Block read instructions to region n - 1 - - - - - - - UNUSED0 - Unspecified - 0x00C - read-write - - - + + TIMER1 + Timer/Counter 1 + 0x40009000 + + TIMER1 + 9 + + + + TIMER2 + Timer/Counter 2 + 0x4000A000 + + TIMER2 + 10 + - NVMC - Non Volatile Memory Controller - 0x4001E000 - ACL + RTC0 + Real time counter 0 + 0x4000B000 + RTC 0 0x1000 registers - NVMC + + RTC0 + 11 + + RTC 0x20 - READY - Ready flag - 0x400 - read-only - 0x00000001 + TASKS_START + Start RTC COUNTER + 0x000 + write-only - READY - NVMC is ready or busy + TASKS_START + Start RTC COUNTER 0 0 - Busy - NVMC is busy (on-going write or erase operation) - 0 - - - Ready - NVMC is ready + Trigger + Trigger task 1 @@ -31049,25 +30210,20 @@ POSSIBILITY OF SUCH DAMAGE.\n - READYNEXT - Ready flag - 0x408 - read-only + TASKS_STOP + Stop RTC COUNTER + 0x004 + write-only - READYNEXT - NVMC can accept a new write operation + TASKS_STOP + Stop RTC COUNTER 0 0 - Busy - NVMC cannot accept any write operation - 0 - - - Ready - NVMC is ready + Trigger + Trigger task 1 @@ -31075,85 +30231,67 @@ POSSIBILITY OF SUCH DAMAGE.\n - CONFIG - Configuration register - 0x504 - read-write + TASKS_CLEAR + Clear RTC COUNTER + 0x008 + write-only - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + TASKS_CLEAR + Clear RTC COUNTER 0 - 1 + 0 - Ren - Read only access - 0 - - - Wen - Write enabled + Trigger + Trigger task 1 - - Een - Erase enabled - 2 - - ERASEPAGE - Register for erasing a page in code area - 0x508 - read-write - - - ERASEPAGE - Register for starting erase of a page in code area - 0 - 31 - - - - - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x508 - read-write - ERASEPAGE + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 + 0x00C + write-only - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. + TASKS_TRIGOVRFLW + Set COUNTER to 0xFFFFF0 0 - 31 + 0 + + + Trigger + Trigger task + 1 + + - ERASEALL - Register for erasing all non-volatile user memory - 0x50C + EVENTS_TICK + Event on COUNTER increment + 0x100 read-write - ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + EVENTS_TICK + Event on COUNTER increment 0 0 - NoOperation - No operation + NotGenerated + Event not generated 0 - Erase - Start chip erase + Generated + Event generated 1 @@ -31161,39 +30299,25 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x510 - read-write - - - ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. - 0 - 31 - - - - - ERASEUICR - Register for erasing user information configuration registers - 0x514 + EVENTS_OVRFLW + Event on COUNTER overflow + 0x104 read-write - ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + EVENTS_OVRFLW + Event on COUNTER overflow 0 0 - NoOperation - No operation + NotGenerated + Event not generated 0 - Erase - Start erase of UICR + Generated + Event generated 1 @@ -31201,733 +30325,653 @@ POSSIBILITY OF SUCH DAMAGE.\n - ERASEPAGEPARTIAL - Register for partial erase of a page in code area - 0x518 - read-write - - - ERASEPAGEPARTIAL - Register for starting partial erase of a page in code area - 0 - 31 - - - - - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C + 0x4 + 0x4 + EVENTS_COMPARE[%s] + Description collection: Compare event on CC[n] match + 0x140 read-write - 0x0000000A - DURATION - Duration of the partial erase in milliseconds + EVENTS_COMPARE + Compare event on CC[n] match 0 - 6 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - ICACHECNF - I-code cache configuration register. - 0x540 + INTENSET + Enable interrupt + 0x304 read-write - 0x00000000 - CACHEEN - Cache enable + TICK + Write '1' to enable interrupt for event TICK 0 0 + read Disabled - Disable cache. Invalidates all cache entries. + Read: Disabled 0 Enabled - Enable cache + Read: Enabled 1 - - - CACHEPROFEN - Cache profiling enable - 8 - 8 + write - Disabled - Disable cache profiling - 0 - - - Enabled - Enable cache profiling + Set + Enable 1 - - - - IHIT - I-code cache hit counter. - 0x548 - read-write - - - HITS - Number of cache hits - 0 - 31 - - - - - IMISS - I-code cache miss counter. - 0x54C - read-write - - - MISSES - Number of cache misses - 0 - 31 - - - - - - - PPI - Programmable Peripheral Interconnect - 0x4001F000 - - 0 - 0x1000 - registers - - PPI - 0x20 - - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - PPI_TASKS_CHG - 0x000 - - EN - Description cluster[n]: Enable channel group n - 0x000 - write-only - - - EN - 0 - 0 - - - - - DIS - Description cluster[n]: Disable channel group n - 0x004 - write-only - - - DIS - 0 - 0 - - - - - - CHEN - Channel enable register - 0x500 - read-write - - CH0 - Enable or disable channel 0 - 0 - 0 + OVRFLW + Write '1' to enable interrupt for event OVRFLW + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH1 - Enable or disable channel 1 - 1 - 1 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH2 - Enable or disable channel 2 - 2 - 2 + COMPARE0 + Write '1' to enable interrupt for event COMPARE[0] + 16 + 16 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH3 - Enable or disable channel 3 - 3 - 3 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH4 - Enable or disable channel 4 - 4 - 4 + COMPARE1 + Write '1' to enable interrupt for event COMPARE[1] + 17 + 17 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH5 - Enable or disable channel 5 - 5 - 5 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 - CH6 - Enable or disable channel 6 - 6 - 6 + COMPARE2 + Write '1' to enable interrupt for event COMPARE[2] + 18 + 18 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH7 - Enable or disable channel 7 - 7 - 7 + COMPARE3 + Write '1' to enable interrupt for event COMPARE[3] + 19 + 19 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH8 - Enable or disable channel 8 - 8 - 8 + TICK + Write '1' to disable interrupt for event TICK + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH9 - Enable or disable channel 9 - 9 - 9 + OVRFLW + Write '1' to disable interrupt for event OVRFLW + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH10 - Enable or disable channel 10 - 10 - 10 + COMPARE0 + Write '1' to disable interrupt for event COMPARE[0] + 16 + 16 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH11 - Enable or disable channel 11 - 11 - 11 + COMPARE1 + Write '1' to disable interrupt for event COMPARE[1] + 17 + 17 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH12 - Enable or disable channel 12 - 12 - 12 + COMPARE2 + Write '1' to disable interrupt for event COMPARE[2] + 18 + 18 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH13 - Enable or disable channel 13 - 13 - 13 + COMPARE3 + Write '1' to disable interrupt for event COMPARE[3] + 19 + 19 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 + + + + EVTEN + Enable or disable event routing + 0x340 + read-write + - CH14 - Enable or disable channel 14 - 14 - 14 + TICK + Enable or disable event routing for event TICK + 0 + 0 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 - CH15 - Enable or disable channel 15 - 15 - 15 + OVRFLW + Enable or disable event routing for event OVRFLW + 1 + 1 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 - CH16 - Enable or disable channel 16 + COMPARE0 + Enable or disable event routing for event COMPARE[0] 16 16 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 - CH17 - Enable or disable channel 17 + COMPARE1 + Enable or disable event routing for event COMPARE[1] 17 17 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 - CH18 - Enable or disable channel 18 + COMPARE2 + Enable or disable event routing for event COMPARE[2] 18 18 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 - CH19 - Enable or disable channel 19 + COMPARE3 + Enable or disable event routing for event COMPARE[3] 19 19 Disabled - Disable channel + Disable 0 Enabled - Enable channel + Disable 1 + + + + EVTENSET + Enable event routing + 0x344 + read-write + - CH20 - Enable or disable channel 20 - 20 - 20 + TICK + Write '1' to enable event routing for event TICK + 0 + 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH21 - Enable or disable channel 21 - 21 - 21 + OVRFLW + Write '1' to enable event routing for event OVRFLW + 1 + 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH22 - Enable or disable channel 22 - 22 - 22 + COMPARE0 + Write '1' to enable event routing for event COMPARE[0] + 16 + 16 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH23 - Enable or disable channel 23 - 23 - 23 + COMPARE1 + Write '1' to enable event routing for event COMPARE[1] + 17 + 17 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH24 - Enable or disable channel 24 - 24 - 24 + COMPARE2 + Write '1' to enable event routing for event COMPARE[2] + 18 + 18 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH25 - Enable or disable channel 25 - 25 - 25 + COMPARE3 + Write '1' to enable event routing for event COMPARE[3] + 19 + 19 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH26 - Enable or disable channel 26 - 26 - 26 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH27 - Enable or disable channel 27 - 27 - 27 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH28 - Enable or disable channel 28 - 28 - 28 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH29 - Enable or disable channel 29 - 29 - 29 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH30 - Enable or disable channel 30 - 30 - 30 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - - - - CH31 - Enable or disable channel 31 - 31 - 31 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Set + Enable 1 @@ -31935,351 +30979,326 @@ POSSIBILITY OF SUCH DAMAGE.\n - CHENSET - Channel enable set register - 0x504 + EVTENCLR + Disable event routing + 0x348 read-write - oneToSet - CH0 - Channel 0 enable set register. Writing '0' has no effect + TICK + Write '1' to disable event routing for event TICK 0 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH1 - Channel 1 enable set register. Writing '0' has no effect + OVRFLW + Write '1' to disable event routing for event OVRFLW 1 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH2 - Channel 2 enable set register. Writing '0' has no effect - 2 - 2 + COMPARE0 + Write '1' to disable event routing for event COMPARE[0] + 16 + 16 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH3 - Channel 3 enable set register. Writing '0' has no effect - 3 - 3 + COMPARE1 + Write '1' to disable event routing for event COMPARE[1] + 17 + 17 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH4 - Channel 4 enable set register. Writing '0' has no effect - 4 - 4 + COMPARE2 + Write '1' to disable event routing for event COMPARE[2] + 18 + 18 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH5 - Channel 5 enable set register. Writing '0' has no effect - 5 - 5 + COMPARE3 + Write '1' to disable event routing for event COMPARE[3] + 19 + 19 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + COUNTER + Current COUNTER value + 0x504 + read-only + - CH6 - Channel 6 enable set register. Writing '0' has no effect - 6 - 6 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - + COUNTER + Counter value + 0 + 23 + + + + PRESCALER + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 0x508 + read-write + - CH7 - Channel 7 enable set register. Writing '0' has no effect - 7 - 7 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - + PRESCALER + Prescaler value + 0 + 11 + + + + 0x4 + 0x4 + CC[%s] + Description collection: Compare register n + 0x540 + read-write + - CH8 - Channel 8 enable set register. Writing '0' has no effect - 8 - 8 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - + COMPARE + Compare value + 0 + 23 + + + + + + TEMP + Temperature Sensor + 0x4000C000 + + 0 + 0x1000 + registers + + + TEMP + 12 + + TEMP + 0x20 + + + TASKS_START + Start temperature measurement + 0x000 + write-only + - CH9 - Channel 9 enable set register. Writing '0' has no effect - 9 - 9 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - + TASKS_START + Start temperature measurement + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop temperature measurement + 0x004 + write-only + - CH10 - Channel 10 enable set register. Writing '0' has no effect - 10 - 10 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - + TASKS_STOP + Stop temperature measurement + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + EVENTS_DATARDY + Temperature measurement complete, data ready + 0x100 + read-write + - CH11 - Channel 11 enable set register. Writing '0' has no effect - 11 - 11 + EVENTS_DATARDY + Temperature measurement complete, data ready + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH12 - Channel 12 enable set register. Writing '0' has no effect - 12 - 12 + DATARDY + Write '1' to enable interrupt for event DATARDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32287,161 +31306,451 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH13 - Channel 13 enable set register. Writing '0' has no effect - 13 - 13 + DATARDY + Write '1' to disable interrupt for event DATARDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + TEMP + Temperature in degC (0.25deg steps) + 0x508 + read-only + int32_t + - CH14 - Channel 14 enable set register. Writing '0' has no effect - 14 - 14 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel - 1 - - + TEMP + Temperature in degC (0.25deg steps) + 0 + 31 + + + + A0 + Slope of 1st piece wise linear function + 0x520 + read-write + 0x00000326 + - CH15 - Channel 15 enable set register. Writing '0' has no effect - 15 - 15 - - read - - Disabled - Read: channel disabled - 0 - + A0 + Slope of 1st piece wise linear function + 0 + 11 + + + + + A1 + Slope of 2nd piece wise linear function + 0x524 + read-write + 0x00000348 + + + A1 + Slope of 2nd piece wise linear function + 0 + 11 + + + + + A2 + Slope of 3rd piece wise linear function + 0x528 + read-write + 0x000003AA + + + A2 + Slope of 3rd piece wise linear function + 0 + 11 + + + + + A3 + Slope of 4th piece wise linear function + 0x52C + read-write + 0x0000040E + + + A3 + Slope of 4th piece wise linear function + 0 + 11 + + + + + A4 + Slope of 5th piece wise linear function + 0x530 + read-write + 0x000004BD + + + A4 + Slope of 5th piece wise linear function + 0 + 11 + + + + + A5 + Slope of 6th piece wise linear function + 0x534 + read-write + 0x000005A3 + + + A5 + Slope of 6th piece wise linear function + 0 + 11 + + + + + B0 + y-intercept of 1st piece wise linear function + 0x540 + read-write + 0x00003FEF + + + B0 + y-intercept of 1st piece wise linear function + 0 + 13 + + + + + B1 + y-intercept of 2nd piece wise linear function + 0x544 + read-write + 0x00003FBE + + + B1 + y-intercept of 2nd piece wise linear function + 0 + 13 + + + + + B2 + y-intercept of 3rd piece wise linear function + 0x548 + read-write + 0x00003FBE + + + B2 + y-intercept of 3rd piece wise linear function + 0 + 13 + + + + + B3 + y-intercept of 4th piece wise linear function + 0x54C + read-write + 0x00000012 + + + B3 + y-intercept of 4th piece wise linear function + 0 + 13 + + + + + B4 + y-intercept of 5th piece wise linear function + 0x550 + read-write + 0x00000124 + + + B4 + y-intercept of 5th piece wise linear function + 0 + 13 + + + + + B5 + y-intercept of 6th piece wise linear function + 0x554 + read-write + 0x0000027C + + + B5 + y-intercept of 6th piece wise linear function + 0 + 13 + + + + + T0 + End point of 1st piece wise linear function + 0x560 + read-write + 0x000000E2 + + + T0 + End point of 1st piece wise linear function + 0 + 7 + + + + + T1 + End point of 2nd piece wise linear function + 0x564 + read-write + 0x00000000 + + + T1 + End point of 2nd piece wise linear function + 0 + 7 + + + + + T2 + End point of 3rd piece wise linear function + 0x568 + read-write + 0x00000019 + + + T2 + End point of 3rd piece wise linear function + 0 + 7 + + + + + T3 + End point of 4th piece wise linear function + 0x56C + read-write + 0x0000003C + + + T3 + End point of 4th piece wise linear function + 0 + 7 + + + + + T4 + End point of 5th piece wise linear function + 0x570 + read-write + 0x00000050 + + + T4 + End point of 5th piece wise linear function + 0 + 7 + + + + + + + RNG + Random Number Generator + 0x4000D000 + + 0 + 0x1000 + registers + + + RNG + 13 + + RNG + 0x20 + + + TASKS_START + Task starting the random number generator + 0x000 + write-only + + + TASKS_START + Task starting the random number generator + 0 + 0 + - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_STOP + Task stopping the random number generator + 0x004 + write-only + + + TASKS_STOP + Task stopping the random number generator + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0x100 + read-write + - CH16 - Channel 16 enable set register. Writing '0' has no effect - 16 - 16 + EVENTS_VALRDY + Event being generated for every new random number written to the VALUE register + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH17 - Channel 17 enable set register. Writing '0' has no effect - 17 - 17 + VALRDY_STOP + Shortcut between event VALRDY and task STOP + 0 + 0 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH18 - Channel 18 enable set register. Writing '0' has no effect - 18 - 18 + VALRDY + Write '1' to enable interrupt for event VALRDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32449,134 +31758,221 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH19 - Channel 19 enable set register. Writing '0' has no effect - 19 - 19 + VALRDY + Write '1' to disable interrupt for event VALRDY + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + CONFIG + Configuration register + 0x504 + read-write + - CH20 - Channel 20 enable set register. Writing '0' has no effect - 20 - 20 + DERCEN + Bias correction + 0 + 0 - read Disabled - Read: channel disabled + Disabled 0 Enabled - Read: channel enabled + Enabled 1 + + + + + VALUE + Output random number + 0x508 + read-only + + + VALUE + Generated random number + 0 + 7 + + + + + + + ECB + AES ECB Mode Encryption + 0x4000E000 + + 0 + 0x1000 + registers + + + ECB + 14 + + ECB + 0x20 + + + TASKS_STARTECB + Start ECB block encrypt + 0x000 + write-only + + + TASKS_STARTECB + Start ECB block encrypt + 0 + 0 - write - Set - Write: Enable channel + Trigger + Trigger task 1 + + + + TASKS_STOPECB + Abort a possible executing ECB operation + 0x004 + write-only + - CH21 - Channel 21 enable set register. Writing '0' has no effect - 21 - 21 + TASKS_STOPECB + Abort a possible executing ECB operation + 0 + 0 - read - - Disabled - Read: channel disabled - 0 - - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + EVENTS_ENDECB + ECB block encrypt complete + 0x100 + read-write + + + EVENTS_ENDECB + ECB block encrypt complete + 0 + 0 - write - Set - Write: Enable channel + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 - - CH22 - Channel 22 enable set register. Writing '0' has no effect - 22 - 22 + + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0x104 + read-write + + + EVENTS_ERRORECB + ECB block encrypt aborted because of a STOPECB task or due to an error + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH23 - Channel 23 enable set register. Writing '0' has no effect - 23 - 23 + ENDECB + Write '1' to enable interrupt for event ENDECB + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32584,26 +31980,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 - CH24 - Channel 24 enable set register. Writing '0' has no effect - 24 - 24 + ERRORECB + Write '1' to enable interrupt for event ERRORECB + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32611,134 +32007,248 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH25 - Channel 25 enable set register. Writing '0' has no effect - 25 - 25 + ENDECB + Write '1' to disable interrupt for event ENDECB + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 - CH26 - Channel 26 enable set register. Writing '0' has no effect - 26 - 26 + ERRORECB + Write '1' to disable interrupt for event ERRORECB + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Set - Write: Enable channel + Clear + Disable 1 + + + + ECBDATAPTR + ECB block encrypt memory pointers + 0x504 + read-write + - CH27 - Channel 27 enable set register. Writing '0' has no effect - 27 - 27 + ECBDATAPTR + Pointer to the ECB data structure (see Table 1 ECB data structure overview) + 0 + 31 + + + + + + + AAR + Accelerated Address Resolver + 0x4000F000 + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + AAR + 0x20 + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0x000 + write-only + + + TASKS_START + Start resolving addresses based on IRKs specified in the IRK data structure + 0 + 0 - read - Disabled - Read: channel disabled - 0 + Trigger + Trigger task + 1 + + + + + + TASKS_STOP + Stop resolving addresses + 0x008 + write-only + + + TASKS_STOP + Stop resolving addresses + 0 + 0 + - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + EVENTS_END + Address resolution procedure complete + 0x100 + read-write + + + EVENTS_END + Address resolution procedure complete + 0 + 0 - write - Set - Write: Enable channel + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_RESOLVED + Address resolved + 0x104 + read-write + - CH28 - Channel 28 enable set register. Writing '0' has no effect - 28 - 28 + EVENTS_RESOLVED + Address resolved + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled + Generated + Event generated 1 + + + + + EVENTS_NOTRESOLVED + Address not resolved + 0x108 + read-write + + + EVENTS_NOTRESOLVED + Address not resolved + 0 + 0 - write - Set - Write: Enable channel + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH29 - Channel 29 enable set register. Writing '0' has no effect - 29 - 29 + END + Write '1' to enable interrupt for event END + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32746,26 +32256,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 - CH30 - Channel 30 enable set register. Writing '0' has no effect - 30 - 30 + RESOLVED + Write '1' to enable interrupt for event RESOLVED + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32773,26 +32283,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 - CH31 - Channel 31 enable set register. Writing '0' has no effect - 31 - 31 + NOTRESOLVED + Write '1' to enable interrupt for event NOTRESOLVED + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32800,7 +32310,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: Enable channel + Enable 1 @@ -32808,27 +32318,26 @@ POSSIBILITY OF SUCH DAMAGE.\n - CHENCLR - Channel enable clear register - 0x508 + INTENCLR + Disable interrupt + 0x308 read-write - oneToClear - CH0 - Channel 0 enable clear register. Writing '0' has no effect + END + Write '1' to disable interrupt for event END 0 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32836,26 +32345,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH1 - Channel 1 enable clear register. Writing '0' has no effect + RESOLVED + Write '1' to disable interrupt for event RESOLVED 1 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32863,26 +32372,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH2 - Channel 2 enable clear register. Writing '0' has no effect + NOTRESOLVED + Write '1' to disable interrupt for event NOTRESOLVED 2 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -32890,242 +32399,427 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 + + + + STATUS + Resolution status + 0x400 + read-only + - CH3 - Channel 3 enable clear register. Writing '0' has no effect - 3 + STATUS + The IRK that was used last time an address was resolved + 0 3 + + + + + ENABLE + Enable AAR + 0x500 + read-write + + + ENABLE + Enable or disable AAR + 0 + 1 - read Disabled - Read: channel disabled + Disable 0 Enabled - Read: channel enabled - 1 + Enable + 3 + + + + + NIRK + Number of IRKs + 0x504 + read-write + 0x00000001 + + + NIRK + Number of Identity root keys available in the IRK data structure + 0 + 4 + + + + + IRKPTR + Pointer to IRK data structure + 0x508 + read-write + + + IRKPTR + Pointer to the IRK data structure + 0 + 31 + + + + + ADDRPTR + Pointer to the resolvable address + 0x510 + read-write + + + ADDRPTR + Pointer to the resolvable address (6-bytes) + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + 0 + 31 + + + + + + + CCM + AES CCM Mode Encryption + 0x4000F000 + AAR + + 0 + 0x1000 + registers + + + CCM_AAR + 15 + + CCM + 0x20 + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0x000 + write-only + + + TASKS_KSGEN + Start generation of key-stream. This operation will stop by itself when completed. + 0 + 0 - write - Clear - Write: disable channel + Trigger + Trigger task 1 + + + + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0x004 + write-only + - CH4 - Channel 4 enable clear register. Writing '0' has no effect - 4 - 4 + TASKS_CRYPT + Start encryption/decryption. This operation will stop by itself when completed. + 0 + 0 - read - Disabled - Read: channel disabled - 0 + Trigger + Trigger task + 1 + + + + + + TASKS_STOP + Stop encryption/decryption + 0x008 + write-only + + + TASKS_STOP + Stop encryption/decryption + 0 + 0 + - Enabled - Read: channel enabled + Trigger + Trigger task 1 + + + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0x00C + write-only + + + TASKS_RATEOVERRIDE + Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption + 0 + 0 - write - Clear - Write: disable channel + Trigger + Trigger task 1 + + + + EVENTS_ENDKSGEN + Key-stream generation complete + 0x100 + read-write + - CH5 - Channel 5 enable clear register. Writing '0' has no effect - 5 - 5 + EVENTS_ENDKSGEN + Key-stream generation complete + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0x104 + read-write + - CH6 - Channel 6 enable clear register. Writing '0' has no effect - 6 - 6 + EVENTS_ENDCRYPT + Encrypt/decrypt complete + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled + Generated + Event generated 1 + + + + + EVENTS_ERROR + Deprecated register - CCM error event + 0x108 + read-write + + + EVENTS_ERROR + Deprecated field - CCM error event + 0 + 0 - write - Clear - Write: disable channel + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH7 - Channel 7 enable clear register. Writing '0' has no effect - 7 - 7 + ENDKSGEN_CRYPT + Shortcut between event ENDKSGEN and task CRYPT + 0 + 0 - read Disabled - Read: channel disabled + Disable shortcut 0 Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH8 - Channel 8 enable clear register. Writing '0' has no effect - 8 - 8 + ENDKSGEN + Write '1' to enable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH9 - Channel 9 enable clear register. Writing '0' has no effect - 9 - 9 + ENDCRYPT + Write '1' to enable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 - CH10 - Channel 10 enable clear register. Writing '0' has no effect - 10 - 10 + ERROR + Deprecated intsetfield - Write '1' to enable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH11 - Channel 11 enable clear register. Writing '0' has no effect - 11 - 11 + ENDKSGEN + Write '1' to disable interrupt for event ENDKSGEN + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -33133,26 +32827,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH12 - Channel 12 enable clear register. Writing '0' has no effect - 12 - 12 + ENDCRYPT + Write '1' to disable interrupt for event ENDCRYPT + 1 + 1 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -33160,26 +32854,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 - CH13 - Channel 13 enable clear register. Writing '0' has no effect - 13 - 13 + ERROR + Deprecated intclrfield - Write '1' to disable interrupt for event ERROR + 2 + 2 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -33187,188 +32881,368 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 + + + + MICSTATUS + MIC check result + 0x400 + read-only + - CH14 - Channel 14 enable clear register. Writing '0' has no effect - 14 - 14 + MICSTATUS + The result of the MIC check performed during the previous decryption operation + 0 + 0 - read - Disabled - Read: channel disabled + CheckFailed + MIC check failed 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + CheckPassed + MIC check passed 1 + + + + ENABLE + Enable + 0x500 + read-write + - CH15 - Channel 15 enable clear register. Writing '0' has no effect - 15 - 15 + ENABLE + Enable or disable CCM + 0 + 1 - read Disabled - Read: channel disabled + Disable 0 Enabled - Read: channel enabled - 1 + Enable + 2 + + + + + MODE + Operation mode + 0x504 + read-write + 0x00000001 + + + MODE + The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. + 0 + 0 - write - Clear - Write: disable channel + Encryption + AES CCM packet encryption mode + 0 + + + Decryption + AES CCM packet decryption mode 1 - CH16 - Channel 16 enable clear register. Writing '0' has no effect + DATARATE + Radio data rate that the CCM shall run synchronous with 16 - 16 + 17 - read - Disabled - Read: channel disabled + 1Mbit + 1 Mbps 0 - Enabled - Read: channel enabled + 2Mbit + 2 Mbps 1 + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + LENGTH + Packet length configuration + 24 + 24 - write - Clear - Write: disable channel + Default + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + 0 + + + Extended + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 + + + + CNFPTR + Pointer to data structure holding AES key and NONCE vector + 0x508 + read-write + - CH17 - Channel 17 enable clear register. Writing '0' has no effect - 17 - 17 + CNFPTR + Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) + 0 + 31 + + + + + INPTR + Input pointer + 0x50C + read-write + + + INPTR + Input pointer + 0 + 31 + + + + + OUTPTR + Output pointer + 0x510 + read-write + + + OUTPTR + Output pointer + 0 + 31 + + + + + SCRATCHPTR + Pointer to data area used for temporary storage + 0x514 + read-write + + + SCRATCHPTR + Pointer to a scratch data area used for temporary storage during key-stream generation, + MIC generation and encryption/decryption. + 0 + 31 + + + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. + 0x518 + read-write + 0x000000FB + + + MAXPACKETSIZE + Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + 0 + 7 + + + + + RATEOVERRIDE + Data rate override setting. + 0x51C + read-write + 0x00000000 + + + RATEOVERRIDE + Data rate override setting. + 0 + 1 - read - Disabled - Read: channel disabled + 1Mbit + 1 Mbps 0 - Enabled - Read: channel enabled + 2Mbit + 2 Mbps 1 + + 125Kbps + 125 Kbps + 2 + + + 500Kbps + 500 Kbps + 3 + + + + + + + + WDT + Watchdog Timer + 0x40010000 + + 0 + 0x1000 + registers + + + WDT + 16 + + WDT + 0x20 + + + TASKS_START + Start the watchdog + 0x000 + write-only + + + TASKS_START + Start the watchdog + 0 + 0 - write - Clear - Write: disable channel + Trigger + Trigger task 1 + + + + EVENTS_TIMEOUT + Watchdog timeout + 0x100 + read-write + - CH18 - Channel 18 enable clear register. Writing '0' has no effect - 18 - 18 + EVENTS_TIMEOUT + Watchdog timeout + 0 + 0 - read - Disabled - Read: channel disabled + NotGenerated + Event not generated 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Generated + Event generated 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH19 - Channel 19 enable clear register. Writing '0' has no effect - 19 - 19 + TIMEOUT + Write '1' to enable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 write - Clear - Write: disable channel + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH20 - Channel 20 enable clear register. Writing '0' has no effect - 20 - 20 + TIMEOUT + Write '1' to disable interrupt for event TIMEOUT + 0 + 0 read Disabled - Read: channel disabled + Read: Disabled 0 Enabled - Read: channel enabled + Read: Enabled 1 @@ -33376,1231 +33250,1121 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: disable channel + Disable 1 + + + + RUNSTATUS + Run status + 0x400 + read-only + - CH21 - Channel 21 enable clear register. Writing '0' has no effect - 21 - 21 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - - CH22 - Channel 22 enable clear register. Writing '0' has no effect - 22 - 22 + RUNSTATUS + Indicates whether or not the watchdog is running + 0 + 0 - read - Disabled - Read: channel disabled + NotRunning + Watchdog not running 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + Running + Watchdog is running 1 + + + + REQSTATUS + Request status + 0x404 + read-only + 0x00000001 + - CH23 - Channel 23 enable clear register. Writing '0' has no effect - 23 - 23 + RR0 + Request status for RR[0] register + 0 + 0 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[0] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[0] register is enabled, and are not yet requesting reload 1 - CH24 - Channel 24 enable clear register. Writing '0' has no effect - 24 - 24 + RR1 + Request status for RR[1] register + 1 + 1 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[1] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[1] register is enabled, and are not yet requesting reload 1 - CH25 - Channel 25 enable clear register. Writing '0' has no effect - 25 - 25 + RR2 + Request status for RR[2] register + 2 + 2 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[2] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[2] register is enabled, and are not yet requesting reload 1 - CH26 - Channel 26 enable clear register. Writing '0' has no effect - 26 - 26 + RR3 + Request status for RR[3] register + 3 + 3 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[3] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[3] register is enabled, and are not yet requesting reload 1 - CH27 - Channel 27 enable clear register. Writing '0' has no effect - 27 - 27 + RR4 + Request status for RR[4] register + 4 + 4 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[4] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[4] register is enabled, and are not yet requesting reload 1 - CH28 - Channel 28 enable clear register. Writing '0' has no effect - 28 - 28 + RR5 + Request status for RR[5] register + 5 + 5 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[5] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[5] register is enabled, and are not yet requesting reload 1 - CH29 - Channel 29 enable clear register. Writing '0' has no effect - 29 - 29 + RR6 + Request status for RR[6] register + 6 + 6 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[6] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[6] register is enabled, and are not yet requesting reload 1 - CH30 - Channel 30 enable clear register. Writing '0' has no effect - 30 - 30 + RR7 + Request status for RR[7] register + 7 + 7 - read - Disabled - Read: channel disabled + DisabledOrRequested + RR[7] register is not enabled, or are already requesting reload 0 - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel + EnabledAndUnrequested + RR[7] register is enabled, and are not yet requesting reload 1 + + + + CRV + Counter reload value + 0x504 + read-write + 0xFFFFFFFF + - CH31 - Channel 31 enable clear register. Writing '0' has no effect - 31 + CRV + Counter reload value in number of cycles of the 32.768 kHz clock + 0 31 - - read - - Disabled - Read: channel disabled - 0 - - - Enabled - Read: channel enabled - 1 - - - - write - - Clear - Write: disable channel - 1 - - - - 20 - 0x008 - CH[%s] - PPI Channel - PPI_CH - 0x510 - - EEP - Description cluster[n]: Channel n event end-point - 0x000 - read-write - - - EEP - Pointer to event register. Accepts only addresses to registers from the Event group. - 0 - 31 - - - - - TEP - Description cluster[n]: Channel n task end-point - 0x004 - read-write - - - TEP - Pointer to task register. Accepts only addresses to registers from the Task group. - 0 - 31 - - - - - 0x6 - 0x4 - CHG[%s] - Description collection[n]: Channel group n - 0x800 + RREN + Enable register for reload request registers + 0x508 read-write + 0x00000001 - CH0 - Include or exclude channel 0 + RR0 + Enable or disable RR[0] register 0 0 - Excluded - Exclude + Disabled + Disable RR[0] register 0 - Included - Include + Enabled + Enable RR[0] register 1 - CH1 - Include or exclude channel 1 + RR1 + Enable or disable RR[1] register 1 1 - Excluded - Exclude + Disabled + Disable RR[1] register 0 - Included - Include + Enabled + Enable RR[1] register 1 - CH2 - Include or exclude channel 2 + RR2 + Enable or disable RR[2] register 2 2 - Excluded - Exclude + Disabled + Disable RR[2] register 0 - Included - Include + Enabled + Enable RR[2] register 1 - CH3 - Include or exclude channel 3 + RR3 + Enable or disable RR[3] register 3 3 - Excluded - Exclude + Disabled + Disable RR[3] register 0 - Included - Include + Enabled + Enable RR[3] register 1 - CH4 - Include or exclude channel 4 + RR4 + Enable or disable RR[4] register 4 4 - Excluded - Exclude + Disabled + Disable RR[4] register 0 - Included - Include + Enabled + Enable RR[4] register 1 - CH5 - Include or exclude channel 5 + RR5 + Enable or disable RR[5] register 5 5 - Excluded - Exclude + Disabled + Disable RR[5] register 0 - Included - Include + Enabled + Enable RR[5] register 1 - CH6 - Include or exclude channel 6 + RR6 + Enable or disable RR[6] register 6 6 - Excluded - Exclude + Disabled + Disable RR[6] register 0 - Included - Include + Enabled + Enable RR[6] register 1 - CH7 - Include or exclude channel 7 + RR7 + Enable or disable RR[7] register 7 7 - Excluded - Exclude + Disabled + Disable RR[7] register 0 - Included - Include + Enabled + Enable RR[7] register 1 + + + + CONFIG + Configuration register + 0x50C + read-write + 0x00000001 + - CH8 - Include or exclude channel 8 - 8 - 8 + SLEEP + Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + 0 + 0 - Excluded - Exclude + Pause + Pause watchdog while the CPU is sleeping 0 - Included - Include + Run + Keep the watchdog running while the CPU is sleeping 1 - CH9 - Include or exclude channel 9 - 9 - 9 + HALT + Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + 3 + 3 - Excluded - Exclude + Pause + Pause watchdog while the CPU is halted by the debugger 0 - Included - Include + Run + Keep the watchdog running while the CPU is halted by the debugger 1 + + + + 0x8 + 0x4 + RR[%s] + Description collection: Reload request n + 0x600 + write-only + - CH10 - Include or exclude channel 10 - 10 - 10 + RR + Reload request register + 0 + 31 - Excluded - Exclude - 0 - - - Included - Include - 1 + Reload + Value to request a reload of the watchdog timer + 0x6E524635 - - CH11 - Include or exclude channel 11 - 11 - 11 - - - Excluded - Exclude - 0 + + + + + + RTC1 + Real time counter 1 + 0x40011000 + + RTC1 + 17 + + + + QDEC + Quadrature Decoder + 0x40012000 + + 0 + 0x1000 + registers + + + QDEC + 18 + + QDEC + 0x20 + + + TASKS_START + Task starting the quadrature decoder + 0x000 + write-only + + + TASKS_START + Task starting the quadrature decoder + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only + + + TASKS_STOP + Task stopping the quadrature decoder + 0 + 0 + - Included - Include + Trigger + Trigger task 1 + + + + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only + - CH12 - Include or exclude channel 12 - 12 - 12 + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0 + 0 - Excluded - Exclude - 0 + Trigger + Trigger task + 1 + + + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + + + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 + - Included - Include + Trigger + Trigger task 1 + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + - CH13 - Include or exclude channel 13 - 13 - 13 + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 - Excluded - Exclude + Trigger + Trigger task + 1 + + + + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 + + + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + - CH14 - Include or exclude channel 14 - 14 - 14 + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + - CH15 - Include or exclude channel 15 - 15 - 15 + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + - CH16 - Include or exclude channel 16 - 16 - 16 + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + - CH17 - Include or exclude channel 17 - 17 - 17 + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 - Excluded - Exclude + NotGenerated + Event not generated 0 - Included - Include + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - CH18 - Include or exclude channel 18 - 18 - 18 + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH19 - Include or exclude channel 19 - 19 - 19 + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH20 - Include or exclude channel 20 - 20 - 20 + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH21 - Include or exclude channel 21 - 21 - 21 + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH22 - Include or exclude channel 22 - 22 - 22 + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH23 - Include or exclude channel 23 - 23 - 23 + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 - CH24 - Include or exclude channel 24 - 24 - 24 + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 - Excluded - Exclude + Disabled + Disable shortcut 0 - Included - Include + Enabled + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - CH25 - Include or exclude channel 25 - 25 - 25 + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY + 0 + 0 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH26 - Include or exclude channel 26 - 26 - 26 + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY + 1 + 1 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH27 - Include or exclude channel 27 - 27 - 27 + ACCOF + Write '1' to enable interrupt for event ACCOF + 2 + 2 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH28 - Include or exclude channel 28 - 28 - 28 + DBLRDY + Write '1' to enable interrupt for event DBLRDY + 3 + 3 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - CH29 - Include or exclude channel 29 - 29 - 29 + STOPPED + Write '1' to enable interrupt for event STOPPED + 4 + 4 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - CH30 - Include or exclude channel 30 - 30 - 30 + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH31 - Include or exclude channel 31 - 31 - 31 + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 + read - Excluded - Exclude + Disabled + Read: Disabled 0 - Included - Include - 1 - - - - - - - 32 - 0x004 - FORK[%s] - Fork - PPI_FORK - 0x910 - - TEP - Description cluster[n]: Channel n task end-point - 0x000 - read-write - - - TEP - Pointer to task register - 0 - 31 - - - - - - - - MWU - Memory Watch Unit - 0x40020000 - - 0 - 0x1000 - registers - - - MWU - 32 - - MWU - 0x20 - - - 4 - 0x008 - EVENTS_REGION[%s] - Unspecified - MWU_EVENTS_REGION - 0x100 - - WA - Description cluster[n]: Write access to region n detected - 0x000 - read-write - - - WA - 0 - 0 - - - - - RA - Description cluster[n]: Read access to region n detected - 0x004 - read-write - - - RA - 0 - 0 - - - - - - 2 - 0x008 - EVENTS_PREGION[%s] - Unspecified - MWU_EVENTS_PREGION - 0x160 - - WA - Description cluster[n]: Write access to peripheral region n detected - 0x000 - read-write - - - WA - 0 - 0 - - - - - RA - Description cluster[n]: Read access to peripheral region n detected - 0x004 - read-write - - - RA - 0 - 0 - - - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - - REGION0WA - Enable or disable interrupt for REGION[0].WA event - 0 - 0 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - REGION0RA - Enable or disable interrupt for REGION[0].RA event - 1 - 1 - - - Disabled - Disable - 0 - - - Enabled - Enable + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - REGION1WA - Enable or disable interrupt for REGION[1].WA event + ACCOF + Write '1' to disable interrupt for event ACCOF 2 2 + read Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - REGION1RA - Enable or disable interrupt for REGION[1].RA event - 3 - 3 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - REGION2WA - Enable or disable interrupt for REGION[2].WA event - 4 - 4 - - - Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - REGION2RA - Enable or disable interrupt for REGION[2].RA event - 5 - 5 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - REGION3WA - Enable or disable interrupt for REGION[3].WA event - 6 - 6 + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - REGION3RA - Enable or disable interrupt for REGION[3].RA event - 7 - 7 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - PREGION0WA - Enable or disable interrupt for PREGION[0].WA event - 24 - 24 + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - PREGION0RA - Enable or disable interrupt for PREGION[0].RA event - 25 - 25 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + - PREGION1WA - Enable or disable interrupt for PREGION[1].WA event - 26 - 26 + ENABLE + Enable or disable the quadrature decoder + 0 + 0 Disabled @@ -34614,20 +34378,28 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + - PREGION1RA - Enable or disable interrupt for PREGION[1].RA event - 27 - 27 + LEDPOL + LED output pin polarity + 0 + 0 - Disabled - Disable + ActiveLow + Led active on output pin low 0 - Enabled - Enable + ActiveHigh + Led active on output pin high 1 @@ -34635,331 +34407,554 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + SAMPLEPER + Sample period + 0x508 read-write - REGION0WA - Write '1' to enable interrupt for REGION[0].WA event + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample 0 - 0 + 3 - read - Disabled - Read: Disabled + 128us + 128 us 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + 256us + 256 us 1 - - - - REGION0RA - Write '1' to enable interrupt for REGION[0].RA event - 1 - 1 - - read - Disabled - Read: Disabled - 0 + 512us + 512 us + 2 - Enabled - Read: Enabled - 1 + 1024us + 1024 us + 3 - - - write - Set - Enable - 1 + 2048us + 2048 us + 4 - - - - REGION1WA - Write '1' to enable interrupt for REGION[1].WA event - 2 - 2 - - read - Disabled - Read: Disabled - 0 + 4096us + 4096 us + 5 - Enabled - Read: Enabled - 1 + 8192us + 8192 us + 6 - - - write - Set - Enable - 1 + 16384us + 16384 us + 7 - - - - REGION1RA - Write '1' to enable interrupt for REGION[1].RA event - 3 - 3 - - read - Disabled - Read: Disabled - 0 + 32ms + 32768 us + 8 - Enabled - Read: Enabled - 1 + 65ms + 65536 us + 9 - - - write - Set - Enable - 1 + 131ms + 131072 us + 10 + + + + SAMPLE + Motion sample value + 0x50C + read-only + int32_t + - REGION2WA - Write '1' to enable interrupt for REGION[2].WA event - 4 - 4 + SAMPLE + Last motion sample + 0 + 31 + + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + + + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + 0 + 3 - read - Disabled - Read: Disabled + 10Smpl + 10 samples / report 0 - Enabled - Read: Enabled + 40Smpl + 40 samples / report 1 - - - write - Set - Enable - 1 + 80Smpl + 80 samples / report + 2 - - - - REGION2RA - Write '1' to enable interrupt for REGION[2].RA event - 5 - 5 - - read - Disabled - Read: Disabled - 0 + 120Smpl + 120 samples / report + 3 - Enabled - Read: Enabled - 1 + 160Smpl + 160 samples / report + 4 - - - write - Set - Enable - 1 + 200Smpl + 200 samples / report + 5 - - - - REGION3WA - Write '1' to enable interrupt for REGION[3].WA event - 6 - 6 - - read - Disabled - Read: Disabled - 0 + 240Smpl + 240 samples / report + 6 - Enabled - Read: Enabled - 1 + 280Smpl + 280 samples / report + 7 - - - write - Set - Enable - 1 + 1Smpl + 1 sample / report + 8 + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + - REGION3RA - Write '1' to enable interrupt for REGION[3].RA event - 7 - 7 + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register + 0 + 31 + + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + + + ACCREAD + Snapshot of the ACC register. + 0 + 31 + + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 - read Disabled - Read: Disabled + Debounce input filters disabled 0 Enabled - Read: Enabled + Debounce input filters enabled 1 + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + COMP + Comparator + 0x40013000 + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + COMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + - PREGION0WA - Write '1' to enable interrupt for PREGION[0].WA event - 24 - 24 + TASKS_STOP + Stop comparator + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + EVENTS_READY + COMP is ready and output is valid + 0x100 + read-write + - PREGION0RA - Write '1' to enable interrupt for PREGION[0].RA event - 25 - 25 + EVENTS_READY + COMP is ready and output is valid + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + - PREGION1WA - Write '1' to enable interrupt for PREGION[1].WA event - 26 - 26 + EVENTS_DOWN + Downward crossing + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Generated + Event generated 1 + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + - PREGION1RA - Write '1' to enable interrupt for PREGION[1].RA event - 27 - 27 + EVENTS_UP + Upward crossing + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 @@ -34967,178 +34962,194 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENCLR - Disable interrupt - 0x308 + SHORTS + Shortcuts between local events and tasks + 0x200 read-write - REGION0WA - Write '1' to disable interrupt for REGION[0].WA event + READY_SAMPLE + Shortcut between event READY and task SAMPLE 0 0 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - REGION0RA - Write '1' to disable interrupt for REGION[0].RA event + READY_STOP + Shortcut between event READY and task STOP 1 1 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - REGION1WA - Write '1' to disable interrupt for REGION[1].WA event + DOWN_STOP + Shortcut between event DOWN and task STOP 2 2 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable shortcut 1 - REGION1RA - Write '1' to disable interrupt for REGION[1].RA event + UP_STOP + Shortcut between event UP and task STOP 3 3 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut 1 + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 - write - Clear - Disable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - REGION2WA - Write '1' to disable interrupt for REGION[2].WA event - 4 - 4 + READY + Enable or disable interrupt for event READY + 0 + 0 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + DOWN + Enable or disable interrupt for event DOWN + 1 + 1 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - REGION2RA - Write '1' to disable interrupt for REGION[2].RA event - 5 - 5 + UP + Enable or disable interrupt for event UP + 2 + 2 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + CROSS + Enable or disable interrupt for event CROSS + 3 + 3 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - REGION3WA - Write '1' to disable interrupt for REGION[3].WA event - 6 - 6 + READY + Write '1' to enable interrupt for event READY + 0 + 0 read @@ -35155,17 +35166,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - REGION3RA - Write '1' to disable interrupt for REGION[3].RA event - 7 - 7 + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 read @@ -35182,17 +35193,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - PREGION0WA - Write '1' to disable interrupt for PREGION[0].WA event - 24 - 24 + UP + Write '1' to enable interrupt for event UP + 2 + 2 read @@ -35209,17 +35220,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - PREGION0RA - Write '1' to disable interrupt for PREGION[0].RA event - 25 - 25 + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 read @@ -35236,17 +35247,25 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PREGION1WA - Write '1' to disable interrupt for PREGION[1].WA event - 26 - 26 + READY + Write '1' to disable interrupt for event READY + 0 + 0 read @@ -35270,10 +35289,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PREGION1RA - Write '1' to disable interrupt for PREGION[1].RA event - 27 - 27 + DOWN + Write '1' to disable interrupt for event DOWN + 1 + 1 read @@ -35296,109 +35315,99 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - NMIEN - Enable or disable non-maskable interrupt - 0x320 - read-write - - REGION0WA - Enable or disable non-maskable interrupt for REGION[0].WA event - 0 - 0 + UP + Write '1' to disable interrupt for event UP + 2 + 2 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - REGION0RA - Enable or disable non-maskable interrupt for REGION[0].RA event - 1 - 1 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 - REGION1WA - Enable or disable non-maskable interrupt for REGION[1].WA event - 2 - 2 + CROSS + Write '1' to disable interrupt for event CROSS + 3 + 3 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled 1 - - - REGION1RA - Enable or disable non-maskable interrupt for REGION[1].RA event - 3 - 3 + write - Disabled + Clear Disable - 0 - - - Enabled - Enable 1 + + + + RESULT + Compare result + 0x400 + read-only + - REGION2WA - Enable or disable non-maskable interrupt for REGION[2].WA event - 4 - 4 + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 - Disabled - Disable + Below + Input voltage is below the threshold (VIN+ &lt; VIN-) 0 - Enabled - Enable + Above + Input voltage is above the threshold (VIN+ &gt; VIN-) 1 + + + + ENABLE + COMP enable + 0x500 + read-write + - REGION2RA - Enable or disable non-maskable interrupt for REGION[2].RA event - 5 - 5 + ENABLE + Enable or disable COMP + 0 + 1 Disabled @@ -35408,114 +35417,230 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled Enable - 1 + 2 + + + + PSEL + Pin select + 0x504 + read-write + - REGION3WA - Enable or disable non-maskable interrupt for REGION[3].WA event - 6 - 6 + PSEL + Analog pin select + 0 + 2 - Disabled - Disable + AnalogInput0 + AIN0 selected as analog input 0 - Enabled - Enable + AnalogInput1 + AIN1 selected as analog input 1 - - - - REGION3RA - Enable or disable non-maskable interrupt for REGION[3].RA event - 7 - 7 - - Disabled - Disable - 0 + AnalogInput2 + AIN2 selected as analog input + 2 - Enabled - Enable - 1 + AnalogInput3 + AIN3 selected as analog input + 3 + + + AnalogInput4 + AIN4 selected as analog input + 4 + + + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + REFSEL + Reference source select for single-ended mode + 0x508 + read-write + 0x00000004 + - PREGION0WA - Enable or disable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + REFSEL + Reference select + 0 + 2 - Disabled - Disable + Int1V2 + VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) 0 - Enabled - Enable + Int1V8 + VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) 1 + + Int2V4 + VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) + 2 + + + VDD + VREF = VDD + 4 + + + ARef + VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + 5 + + + + + EXTREFSEL + External reference select + 0x50C + read-write + - PREGION0RA - Enable or disable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + EXTREFSEL + External analog reference select + 0 + 2 - Disabled - Disable + AnalogReference0 + Use AIN0 as external analog reference 0 - Enabled - Enable + AnalogReference1 + Use AIN1 as external analog reference 1 + + AnalogReference2 + Use AIN2 as external analog reference + 2 + + + AnalogReference3 + Use AIN3 as external analog reference + 3 + + + AnalogReference4 + Use AIN4 as external analog reference + 4 + + + AnalogReference5 + Use AIN5 as external analog reference + 5 + + + AnalogReference6 + Use AIN6 as external analog reference + 6 + + + AnalogReference7 + Use AIN7 as external analog reference + 7 + + + + + TH + Threshold configuration for hysteresis unit + 0x530 + read-write + 0x00000000 + + + THDOWN + VDOWN = (THDOWN+1)/64*VREF + 0 + 5 + - PREGION1WA - Enable or disable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + THUP + VUP = (THUP+1)/64*VREF + 8 + 13 + + + + + MODE + Mode configuration + 0x534 + read-write + + + SP + Speed and power modes + 0 + 1 - Disabled - Disable + Low + Low-power mode 0 - Enabled - Enable + Normal + Normal mode 1 + + High + High-speed mode + 2 + - PREGION1RA - Enable or disable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + MAIN + Main operation modes + 8 + 8 - Disabled - Disable + SE + Single-ended mode 0 - Enabled - Enable + Diff + Differential mode 1 @@ -35523,232 +35648,326 @@ POSSIBILITY OF SUCH DAMAGE.\n - NMIENSET - Enable non-maskable interrupt - 0x324 + HYST + Comparator hysteresis enable + 0x538 read-write - REGION0WA - Write '1' to enable non-maskable interrupt for REGION[0].WA event + HYST + Comparator hysteresis 0 0 - read - Disabled - Read: Disabled + NoHyst + Comparator hysteresis disabled 0 - Enabled - Read: Enabled + Hyst50mV + Comparator hysteresis enabled 1 + + + + + + + LPCOMP + Low Power Comparator + 0x40013000 + COMP + + 0 + 0x1000 + registers + + + COMP_LPCOMP + 19 + + LPCOMP + 0x20 + + + TASKS_START + Start comparator + 0x000 + write-only + + + TASKS_START + Start comparator + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + TASKS_STOP + Stop comparator + 0x004 + write-only + - REGION0RA - Write '1' to enable non-maskable interrupt for REGION[0].RA event - 1 - 1 + TASKS_STOP + Stop comparator + 0 + 0 - read - - Disabled - Read: Disabled - 0 - - Enabled - Read: Enabled + Trigger + Trigger task 1 + + + + + TASKS_SAMPLE + Sample comparator value + 0x008 + write-only + + + TASKS_SAMPLE + Sample comparator value + 0 + 0 - write - Set - Enable + Trigger + Trigger task 1 + + + + EVENTS_READY + LPCOMP is ready and output is valid + 0x100 + read-write + - REGION1WA - Write '1' to enable non-maskable interrupt for REGION[1].WA event - 2 - 2 + EVENTS_READY + LPCOMP is ready and output is valid + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_DOWN + Downward crossing + 0x104 + read-write + + + EVENTS_DOWN + Downward crossing + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_UP + Upward crossing + 0x108 + read-write + - REGION1RA - Write '1' to enable non-maskable interrupt for REGION[1].RA event - 3 - 3 + EVENTS_UP + Upward crossing + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + EVENTS_CROSS + Downward or upward crossing + 0x10C + read-write + + + EVENTS_CROSS + Downward or upward crossing + 0 + 0 - write - Set - Enable + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - REGION2WA - Write '1' to enable non-maskable interrupt for REGION[2].WA event - 4 - 4 + READY_SAMPLE + Shortcut between event READY and task SAMPLE + 0 + 0 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - REGION2RA - Write '1' to enable non-maskable interrupt for REGION[2].RA event - 5 - 5 + READY_STOP + Shortcut between event READY and task STOP + 1 + 1 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - REGION3WA - Write '1' to enable non-maskable interrupt for REGION[3].WA event - 6 - 6 + DOWN_STOP + Shortcut between event DOWN and task STOP + 2 + 2 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + Enable shortcut 1 - REGION3RA - Write '1' to enable non-maskable interrupt for REGION[3].RA event - 7 - 7 + UP_STOP + Shortcut between event UP and task STOP + 3 + 3 - read Disabled - Read: Disabled + Disable shortcut 0 Enabled - Read: Enabled + Enable shortcut 1 + + + CROSS_STOP + Shortcut between event CROSS and task STOP + 4 + 4 - write - Set - Enable + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PREGION0WA - Write '1' to enable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + READY + Write '1' to enable interrupt for event READY + 0 + 0 read @@ -35772,10 +35991,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PREGION0RA - Write '1' to enable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + DOWN + Write '1' to enable interrupt for event DOWN + 1 + 1 read @@ -35799,10 +36018,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PREGION1WA - Write '1' to enable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + UP + Write '1' to enable interrupt for event UP + 2 + 2 read @@ -35826,10 +36045,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - PREGION1RA - Write '1' to enable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + CROSS + Write '1' to enable interrupt for event CROSS + 3 + 3 read @@ -35855,14 +36074,14 @@ POSSIBILITY OF SUCH DAMAGE.\n - NMIENCLR - Disable non-maskable interrupt - 0x328 + INTENCLR + Disable interrupt + 0x308 read-write - REGION0WA - Write '1' to disable non-maskable interrupt for REGION[0].WA event + READY + Write '1' to disable interrupt for event READY 0 0 @@ -35888,8 +36107,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - REGION0RA - Write '1' to disable non-maskable interrupt for REGION[0].RA event + DOWN + Write '1' to disable interrupt for event DOWN 1 1 @@ -35915,8 +36134,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - REGION1WA - Write '1' to disable non-maskable interrupt for REGION[1].WA event + UP + Write '1' to disable interrupt for event UP 2 2 @@ -35942,8 +36161,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - REGION1RA - Write '1' to disable non-maskable interrupt for REGION[1].RA event + CROSS + Write '1' to disable interrupt for event CROSS 3 3 @@ -35968,3100 +36187,2081 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + RESULT + Compare result + 0x400 + read-only + - REGION2WA - Write '1' to disable non-maskable interrupt for REGION[2].WA event - 4 - 4 + RESULT + Result of last compare. Decision point SAMPLE task. + 0 + 0 - read - Disabled - Read: Disabled + Below + Input voltage is below the reference threshold (VIN+ &lt; VIN-). 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Above + Input voltage is above the reference threshold (VIN+ &gt; VIN-). 1 + + + + ENABLE + Enable LPCOMP + 0x500 + read-write + - REGION2RA - Write '1' to disable non-maskable interrupt for REGION[2].RA event - 5 - 5 + ENABLE + Enable or disable LPCOMP + 0 + 1 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Enable 1 + + + + PSEL + Input pin select + 0x504 + read-write + - REGION3WA - Write '1' to disable non-maskable interrupt for REGION[3].WA event - 6 - 6 + PSEL + Analog pin select + 0 + 2 - read - Disabled - Read: Disabled + AnalogInput0 + AIN0 selected as analog input 0 - Enabled - Read: Enabled + AnalogInput1 + AIN1 selected as analog input 1 - - - write - Clear - Disable - 1 + AnalogInput2 + AIN2 selected as analog input + 2 - - - - REGION3RA - Write '1' to disable non-maskable interrupt for REGION[3].RA event - 7 - 7 - - read - Disabled - Read: Disabled - 0 + AnalogInput3 + AIN3 selected as analog input + 3 - Enabled - Read: Enabled - 1 + AnalogInput4 + AIN4 selected as analog input + 4 - - - write - Clear - Disable - 1 + AnalogInput5 + AIN5 selected as analog input + 5 + + + AnalogInput6 + AIN6 selected as analog input + 6 + + + AnalogInput7 + AIN7 selected as analog input + 7 + + + + REFSEL + Reference select + 0x508 + read-write + 0x00000004 + - PREGION0WA - Write '1' to disable non-maskable interrupt for PREGION[0].WA event - 24 - 24 + REFSEL + Reference select + 0 + 3 - read - Disabled - Read: Disabled + Ref1_8Vdd + VDD * 1/8 selected as reference 0 - Enabled - Read: Enabled + Ref2_8Vdd + VDD * 2/8 selected as reference 1 - - - write - Clear - Disable - 1 + Ref3_8Vdd + VDD * 3/8 selected as reference + 2 + + + Ref4_8Vdd + VDD * 4/8 selected as reference + 3 + + + Ref5_8Vdd + VDD * 5/8 selected as reference + 4 + + + Ref6_8Vdd + VDD * 6/8 selected as reference + 5 + + + Ref7_8Vdd + VDD * 7/8 selected as reference + 6 + + + ARef + External analog reference selected + 7 + + + Ref1_16Vdd + VDD * 1/16 selected as reference + 8 + + + Ref3_16Vdd + VDD * 3/16 selected as reference + 9 + + + Ref5_16Vdd + VDD * 5/16 selected as reference + 10 + + + Ref7_16Vdd + VDD * 7/16 selected as reference + 11 + + + Ref9_16Vdd + VDD * 9/16 selected as reference + 12 + + + Ref11_16Vdd + VDD * 11/16 selected as reference + 13 + + + Ref13_16Vdd + VDD * 13/16 selected as reference + 14 + + + Ref15_16Vdd + VDD * 15/16 selected as reference + 15 + + + + EXTREFSEL + External reference select + 0x50C + read-write + - PREGION0RA - Write '1' to disable non-maskable interrupt for PREGION[0].RA event - 25 - 25 + EXTREFSEL + External analog reference select + 0 + 0 - read - Disabled - Read: Disabled + AnalogReference0 + Use AIN0 as external analog reference 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + AnalogReference1 + Use AIN1 as external analog reference 1 + + + + ANADETECT + Analog detect configuration + 0x520 + read-write + - PREGION1WA - Write '1' to disable non-maskable interrupt for PREGION[1].WA event - 26 - 26 + ANADETECT + Analog detect configuration + 0 + 1 - read - Disabled - Read: Disabled + Cross + Generate ANADETECT on crossing, both upward crossing and downward crossing 0 - Enabled - Read: Enabled + Up + Generate ANADETECT on upward crossing only 1 - - - write - Clear - Disable - 1 + Down + Generate ANADETECT on downward crossing only + 2 + + + + HYST + Comparator hysteresis enable + 0x538 + read-write + - PREGION1RA - Write '1' to disable non-maskable interrupt for PREGION[1].RA event - 27 - 27 + HYST + Comparator hysteresis enable + 0 + 0 - read Disabled - Read: Disabled + Comparator hysteresis disabled 0 Enabled - Read: Enabled + Comparator hysteresis enabled 1 + + + + + + + EGU0 + Event Generator Unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 - write - Clear - Disable + Trigger + Trigger task + 1 + + + + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + + + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED13 + Enable or disable interrupt for event TRIGGERED[13] + 13 + 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - 2 - 0x008 - PERREGION[%s] - Unspecified - MWU_PERREGION - 0x400 - - SUBSTATWA - Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching - 0x000 - read-write - oneToClear - - - SR0 - Subregion 0 in region n (write '1' to clear) - 0 - 0 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR1 - Subregion 1 in region n (write '1' to clear) - 1 - 1 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR2 - Subregion 2 in region n (write '1' to clear) - 2 - 2 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR3 - Subregion 3 in region n (write '1' to clear) - 3 - 3 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR4 - Subregion 4 in region n (write '1' to clear) - 4 - 4 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR5 - Subregion 5 in region n (write '1' to clear) - 5 - 5 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR6 - Subregion 6 in region n (write '1' to clear) - 6 - 6 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR7 - Subregion 7 in region n (write '1' to clear) - 7 - 7 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR8 - Subregion 8 in region n (write '1' to clear) - 8 - 8 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR9 - Subregion 9 in region n (write '1' to clear) - 9 - 9 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR10 - Subregion 10 in region n (write '1' to clear) - 10 - 10 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR11 - Subregion 11 in region n (write '1' to clear) - 11 - 11 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR12 - Subregion 12 in region n (write '1' to clear) - 12 - 12 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR13 - Subregion 13 in region n (write '1' to clear) - 13 - 13 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR14 - Subregion 14 in region n (write '1' to clear) - 14 - 14 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR15 - Subregion 15 in region n (write '1' to clear) - 15 - 15 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR16 - Subregion 16 in region n (write '1' to clear) - 16 - 16 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR17 - Subregion 17 in region n (write '1' to clear) - 17 - 17 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR18 - Subregion 18 in region n (write '1' to clear) - 18 - 18 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR19 - Subregion 19 in region n (write '1' to clear) - 19 - 19 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR20 - Subregion 20 in region n (write '1' to clear) - 20 - 20 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR21 - Subregion 21 in region n (write '1' to clear) - 21 - 21 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR22 - Subregion 22 in region n (write '1' to clear) - 22 - 22 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR23 - Subregion 23 in region n (write '1' to clear) - 23 - 23 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR24 - Subregion 24 in region n (write '1' to clear) - 24 - 24 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR25 - Subregion 25 in region n (write '1' to clear) - 25 - 25 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR26 - Subregion 26 in region n (write '1' to clear) - 26 - 26 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR27 - Subregion 27 in region n (write '1' to clear) - 27 - 27 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR28 - Subregion 28 in region n (write '1' to clear) - 28 - 28 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR29 - Subregion 29 in region n (write '1' to clear) - 29 - 29 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR30 - Subregion 30 in region n (write '1' to clear) - 30 - 30 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - SR31 - Subregion 31 in region n (write '1' to clear) - 31 - 31 - - - NoAccess - No write access occurred in this subregion - 0 - - - Access - Write access(es) occurred in this subregion - 1 - - - - - - - SUBSTATRA - Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching - 0x004 - read-write - oneToClear - - - SR0 - Subregion 0 in region n (write '1' to clear) - 0 - 0 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR1 - Subregion 1 in region n (write '1' to clear) - 1 - 1 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR2 - Subregion 2 in region n (write '1' to clear) - 2 - 2 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR3 - Subregion 3 in region n (write '1' to clear) - 3 - 3 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR4 - Subregion 4 in region n (write '1' to clear) - 4 - 4 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR5 - Subregion 5 in region n (write '1' to clear) - 5 - 5 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR6 - Subregion 6 in region n (write '1' to clear) - 6 - 6 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR7 - Subregion 7 in region n (write '1' to clear) - 7 - 7 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR8 - Subregion 8 in region n (write '1' to clear) - 8 - 8 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR9 - Subregion 9 in region n (write '1' to clear) - 9 - 9 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR10 - Subregion 10 in region n (write '1' to clear) - 10 - 10 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR11 - Subregion 11 in region n (write '1' to clear) - 11 - 11 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR12 - Subregion 12 in region n (write '1' to clear) - 12 - 12 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR13 - Subregion 13 in region n (write '1' to clear) - 13 - 13 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR14 - Subregion 14 in region n (write '1' to clear) - 14 - 14 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR15 - Subregion 15 in region n (write '1' to clear) - 15 - 15 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR16 - Subregion 16 in region n (write '1' to clear) - 16 - 16 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR17 - Subregion 17 in region n (write '1' to clear) - 17 - 17 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR18 - Subregion 18 in region n (write '1' to clear) - 18 - 18 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR19 - Subregion 19 in region n (write '1' to clear) - 19 - 19 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR20 - Subregion 20 in region n (write '1' to clear) - 20 - 20 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR21 - Subregion 21 in region n (write '1' to clear) - 21 - 21 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR22 - Subregion 22 in region n (write '1' to clear) - 22 - 22 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR23 - Subregion 23 in region n (write '1' to clear) - 23 - 23 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR24 - Subregion 24 in region n (write '1' to clear) - 24 - 24 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR25 - Subregion 25 in region n (write '1' to clear) - 25 - 25 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR26 - Subregion 26 in region n (write '1' to clear) - 26 - 26 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR27 - Subregion 27 in region n (write '1' to clear) - 27 - 27 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR28 - Subregion 28 in region n (write '1' to clear) - 28 - 28 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR29 - Subregion 29 in region n (write '1' to clear) - 29 - 29 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR30 - Subregion 30 in region n (write '1' to clear) - 30 - 30 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - SR31 - Subregion 31 in region n (write '1' to clear) - 31 - 31 - - - NoAccess - No read access occurred in this subregion - 0 - - - Access - Read access(es) occurred in this subregion - 1 - - - - - - - - REGIONEN - Enable/disable regions watch - 0x510 - read-write - - - RGN0WA - Enable/disable write access watch in region[0] - 0 - 0 - - - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 - - - - - RGN0RA - Enable/disable read access watch in region[0] - 1 - 1 - - - Disable - Disable read access watch in this region - 0 - - - Enable - Enable read access watch in this region - 1 - - - - - RGN1WA - Enable/disable write access watch in region[1] - 2 - 2 - - - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 - - - - - RGN1RA - Enable/disable read access watch in region[1] - 3 - 3 - - - Disable - Disable read access watch in this region - 0 - - - Enable - Enable read access watch in this region - 1 - - - - - RGN2WA - Enable/disable write access watch in region[2] - 4 - 4 - - - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 - - - - - RGN2RA - Enable/disable read access watch in region[2] - 5 - 5 - - - Disable - Disable read access watch in this region - 0 - - - Enable - Enable read access watch in this region - 1 - - - - - RGN3WA - Enable/disable write access watch in region[3] - 6 - 6 - - - Disable - Disable write access watch in this region - 0 - - - Enable - Enable write access watch in this region - 1 - - - - - RGN3RA - Enable/disable read access watch in region[3] - 7 - 7 - - - Disable - Disable read access watch in this region - 0 - - - Enable - Enable read access watch in this region - 1 - - - - - PRGN0WA - Enable/disable write access watch in PREGION[0] - 24 - 24 - - - Disable - Disable write access watch in this PREGION - 0 - - - Enable - Enable write access watch in this PREGION - 1 - - - - - PRGN0RA - Enable/disable read access watch in PREGION[0] - 25 - 25 - - - Disable - Disable read access watch in this PREGION - 0 - - - Enable - Enable read access watch in this PREGION - 1 - - - - - PRGN1WA - Enable/disable write access watch in PREGION[1] - 26 - 26 - - - Disable - Disable write access watch in this PREGION - 0 - - - Enable - Enable write access watch in this PREGION - 1 - - - - - PRGN1RA - Enable/disable read access watch in PREGION[1] - 27 - 27 - - - Disable - Disable read access watch in this PREGION - 0 - - - Enable - Enable read access watch in this PREGION - 1 - - - - - - - REGIONENSET - Enable regions watch - 0x514 - read-write - - - RGN0WA - Enable write access watch in region[0] - 0 - 0 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 - - - - - RGN0RA - Enable read access watch in region[0] - 1 - 1 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 - - - - - RGN1WA - Enable write access watch in region[1] - 2 - 2 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 - - - - - RGN1RA - Enable read access watch in region[1] - 3 - 3 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 - - - - - RGN2WA - Enable write access watch in region[2] - 4 - 4 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 - - - - - RGN2RA - Enable read access watch in region[2] - 5 - 5 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 - - - - - RGN3WA - Enable write access watch in region[3] - 6 - 6 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Set - Enable write access watch in this region - 1 - - - - - RGN3RA - Enable read access watch in region[3] - 7 - 7 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Set - Enable read access watch in this region - 1 - - - - - PRGN0WA - Enable write access watch in PREGION[0] - 24 - 24 - - read - - Disabled - Write access watch in this PREGION is disabled - 0 - - - Enabled - Write access watch in this PREGION is enabled - 1 - - - - write - - Set - Enable write access watch in this PREGION - 1 - - - - - PRGN0RA - Enable read access watch in PREGION[0] - 25 - 25 - - read - - Disabled - Read access watch in this PREGION is disabled - 0 - - - Enabled - Read access watch in this PREGION is enabled - 1 - - - - write - - Set - Enable read access watch in this PREGION - 1 - - - - - PRGN1WA - Enable write access watch in PREGION[1] - 26 - 26 - - read - - Disabled - Write access watch in this PREGION is disabled - 0 - - - Enabled - Write access watch in this PREGION is enabled - 1 - - - - write - - Set - Enable write access watch in this PREGION - 1 - - - - - PRGN1RA - Enable read access watch in PREGION[1] - 27 - 27 - - read - - Disabled - Read access watch in this PREGION is disabled - 0 - - - Enabled - Read access watch in this PREGION is enabled - 1 - - - - write - - Set - Enable read access watch in this PREGION - 1 - - - - - - - REGIONENCLR - Disable regions watch - 0x518 - read-write - - - RGN0WA - Disable write access watch in region[0] - 0 - 0 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Clear - Disable write access watch in this region - 1 - - - - - RGN0RA - Disable read access watch in region[0] - 1 - 1 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Clear - Disable read access watch in this region - 1 - - - - - RGN1WA - Disable write access watch in region[1] - 2 - 2 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Clear - Disable write access watch in this region - 1 - - - - - RGN1RA - Disable read access watch in region[1] - 3 - 3 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Clear - Disable read access watch in this region - 1 - - - - - RGN2WA - Disable write access watch in region[2] - 4 - 4 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Clear - Disable write access watch in this region - 1 - - - - - RGN2RA - Disable read access watch in region[2] - 5 - 5 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Clear - Disable read access watch in this region - 1 - - - - - RGN3WA - Disable write access watch in region[3] - 6 - 6 - - read - - Disabled - Write access watch in this region is disabled - 0 - - - Enabled - Write access watch in this region is enabled - 1 - - - - write - - Clear - Disable write access watch in this region - 1 - - - - - RGN3RA - Disable read access watch in region[3] - 7 - 7 - - read - - Disabled - Read access watch in this region is disabled - 0 - - - Enabled - Read access watch in this region is enabled - 1 - - - - write - - Clear - Disable read access watch in this region - 1 - - - - - PRGN0WA - Disable write access watch in PREGION[0] - 24 - 24 - - read - - Disabled - Write access watch in this PREGION is disabled - 0 - - - Enabled - Write access watch in this PREGION is enabled - 1 - - - - write - - Clear - Disable write access watch in this PREGION - 1 - - - - - PRGN0RA - Disable read access watch in PREGION[0] - 25 - 25 - - read - - Disabled - Read access watch in this PREGION is disabled - 0 - - - Enabled - Read access watch in this PREGION is enabled - 1 - - - - write - - Clear - Disable read access watch in this PREGION - 1 - - - - - PRGN1WA - Disable write access watch in PREGION[1] - 26 - 26 - - read - - Disabled - Write access watch in this PREGION is disabled - 0 - - - Enabled - Write access watch in this PREGION is enabled - 1 - - - - write - - Clear - Disable write access watch in this PREGION - 1 - - - - - PRGN1RA - Disable read access watch in PREGION[1] - 27 - 27 - - read - - Disabled - Read access watch in this PREGION is disabled - 0 - - - Enabled - Read access watch in this PREGION is enabled - 1 - - - - write - - Clear - Disable read access watch in this PREGION - 1 - - - - - - - 4 - 0x010 - REGION[%s] - Unspecified - MWU_REGION - 0x600 - - START - Description cluster[n]: Start address for region n - 0x000 - read-write - 0x00000000 - - - START - Start address for region - 0 - 31 - - - - - END - Description cluster[n]: End address of region n - 0x004 - read-write - - - END - End address of region. - 0 - 31 - - - - - - 2 - 0x010 - PREGION[%s] - Unspecified - MWU_PREGION - 0x6C0 - - START - Description cluster[n]: Reserved for future use - 0x000 - read-only - - - START - Reserved for future use - 0 - 31 - - - - - END - Description cluster[n]: Reserved for future use - 0x004 - read-only - - - END - Reserved for future use - 0 - 31 - - - - - SUBS - Description cluster[n]: Subregions of region n - 0x008 - read-write - 0x00000000 - - - SR0 - Include or exclude subregion 0 in region - 0 - 0 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR1 - Include or exclude subregion 1 in region - 1 - 1 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR2 - Include or exclude subregion 2 in region - 2 - 2 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR3 - Include or exclude subregion 3 in region - 3 - 3 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR4 - Include or exclude subregion 4 in region - 4 - 4 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR5 - Include or exclude subregion 5 in region - 5 - 5 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR6 - Include or exclude subregion 6 in region - 6 - 6 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR7 - Include or exclude subregion 7 in region - 7 - 7 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR8 - Include or exclude subregion 8 in region - 8 - 8 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR9 - Include or exclude subregion 9 in region - 9 - 9 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR10 - Include or exclude subregion 10 in region - 10 - 10 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR11 - Include or exclude subregion 11 in region - 11 - 11 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR12 - Include or exclude subregion 12 in region - 12 - 12 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR13 - Include or exclude subregion 13 in region - 13 - 13 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR14 - Include or exclude subregion 14 in region - 14 - 14 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR15 - Include or exclude subregion 15 in region - 15 - 15 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR16 - Include or exclude subregion 16 in region - 16 - 16 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR17 - Include or exclude subregion 17 in region - 17 - 17 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR18 - Include or exclude subregion 18 in region - 18 - 18 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR19 - Include or exclude subregion 19 in region - 19 - 19 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR20 - Include or exclude subregion 20 in region - 20 - 20 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR21 - Include or exclude subregion 21 in region - 21 - 21 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR22 - Include or exclude subregion 22 in region - 22 - 22 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR23 - Include or exclude subregion 23 in region - 23 - 23 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR24 - Include or exclude subregion 24 in region - 24 - 24 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR25 - Include or exclude subregion 25 in region - 25 - 25 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR26 - Include or exclude subregion 26 in region - 26 - 26 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR27 - Include or exclude subregion 27 in region - 27 - 27 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR28 - Include or exclude subregion 28 in region - 28 - 28 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR29 - Include or exclude subregion 29 in region - 29 - 29 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR30 - Include or exclude subregion 30 in region - 30 - 30 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - SR31 - Include or exclude subregion 31 in region - 31 - 31 - - - Exclude - Exclude - 0 - - - Include - Include - 1 - - - - - - - - PWM1 - Pulse width modulation unit 1 - 0x40021000 + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + - PWM1 - 33 + SWI0_EGU0 + 20 + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + - - PWM2 - Pulse width modulation unit 2 - 0x40022000 + + EGU1 + Event Generator Unit 1 + 0x40015000 - PWM2 - 34 + SWI1_EGU1 + 21 - - SPI2 - Serial Peripheral Interface 2 - 0x40023000 + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 - SPIM2_SPIS2_SPI2 - 35 + SWI1_EGU1 + 21 - - SPIM2 - Serial Peripheral Interface Master with EasyDMA 2 - 0x40023000 - SPI2 + + EGU2 + Event Generator Unit 2 + 0x40016000 - SPIM2_SPIS2_SPI2 - 35 + SWI2_EGU2 + 22 - - SPIS2 - SPI Slave 2 - 0x40023000 - SPI2 + + SWI2 + Software interrupt 2 + 0x40016000 + EGU2 - SPIM2_SPIS2_SPI2 - 35 + SWI2_EGU2 + 22 - - RTC2 - Real time counter 2 - 0x40024000 + + EGU3 + Event Generator Unit 3 + 0x40017000 - RTC2 - 36 + SWI3_EGU3 + 23 + + + + SWI3 + Software interrupt 3 + 0x40017000 + EGU3 + + SWI3_EGU3 + 23 + + + + EGU4 + Event Generator Unit 4 + 0x40018000 + + SWI4_EGU4 + 24 + + + + SWI4 + Software interrupt 4 + 0x40018000 + EGU4 + + SWI4_EGU4 + 24 + + + + EGU5 + Event Generator Unit 5 + 0x40019000 + + SWI5_EGU5 + 25 + + + + SWI5 + Software interrupt 5 + 0x40019000 + EGU5 + + SWI5_EGU5 + 25 + + + + TIMER3 + Timer/Counter 3 + 0x4001A000 + + TIMER3 + 26 + + + + TIMER4 + Timer/Counter 4 + 0x4001B000 + + TIMER4 + 27 - I2S - Inter-IC Sound - 0x40025000 + PWM0 + Pulse width modulation unit 0 + 0x4001C000 + PWM 0 0x1000 registers - I2S - 37 + PWM0 + 28 - I2S + PWM 0x20 - TASKS_START - Starts continuous I2S transfer. Also starts MCK generator when this is enabled. - 0x000 + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback + 0x004 write-only - TASKS_START + TASKS_STOP + Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0 0 + + + Trigger + Trigger task + 1 + + - TASKS_STOP - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. - 0x004 + 0x2 + 0x4 + TASKS_SEQSTART[%s] + Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. + 0x008 write-only - TASKS_STOP + TASKS_SEQSTART + Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0 0 + + + Trigger + Trigger task + 1 + + - EVENTS_RXPTRUPD - The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0x010 + write-only + + + TASKS_NEXTSTEP + Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write - EVENTS_RXPTRUPD + EVENTS_STOPPED + Response to STOP task, emitted when PWM pulses are no longer generated 0 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + - EVENTS_STOPPED - I2S transfer stopped. + 0x2 + 0x4 + EVENTS_SEQSTARTED[%s] + Description collection: First PWM period started on sequence n 0x108 read-write - EVENTS_STOPPED + EVENTS_SEQSTARTED + First PWM period started on sequence n + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + 0x2 + 0x4 + EVENTS_SEQEND[%s] + Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0x110 + read-write + + + EVENTS_SEQEND + Emitted at end of every sequence n, when last value from RAM has been applied to wave counter + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0x118 + read-write + + + EVENTS_PWMPERIODEND + Emitted at the end of each PWM period + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0x11C + read-write + + + EVENTS_LOOPSDONE + Concatenated sequences have been played the amount of times defined in LOOP.CNT + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + SEQEND0_STOP + Shortcut between event SEQEND[0] and task STOP 0 0 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + SEQEND1_STOP + Shortcut between event SEQEND[1] and task STOP + 1 + 1 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART0 + Shortcut between event LOOPSDONE and task SEQSTART[0] + 2 + 2 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_SEQSTART1 + Shortcut between event LOOPSDONE and task SEQSTART[1] + 3 + 3 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + LOOPSDONE_STOP + Shortcut between event LOOPSDONE and task STOP + 4 + 4 + + + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED0 + Enable or disable interrupt for event SEQSTARTED[0] + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + SEQSTARTED1 + Enable or disable interrupt for event SEQSTARTED[1] + 3 + 3 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - EVENTS_TXPTRUPD - The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. - 0x114 - read-write - - EVENTS_TXPTRUPD - 0 - 0 + SEQEND0 + Enable or disable interrupt for event SEQEND[0] + 4 + 4 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - RXPTRUPD - Enable or disable interrupt for RXPTRUPD event - 1 - 1 + SEQEND1 + Enable or disable interrupt for event SEQEND[1] + 5 + 5 Disabled @@ -39076,10 +38276,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Enable or disable interrupt for STOPPED event - 2 - 2 + PWMPERIODEND + Enable or disable interrupt for event PWMPERIODEND + 6 + 6 Disabled @@ -39094,10 +38294,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXPTRUPD - Enable or disable interrupt for TXPTRUPD event - 5 - 5 + LOOPSDONE + Enable or disable interrupt for event LOOPSDONE + 7 + 7 Disabled @@ -39120,8 +38320,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - RXPTRUPD - Write '1' to enable interrupt for RXPTRUPD event + STOPPED + Write '1' to enable interrupt for event STOPPED 1 1 @@ -39147,8 +38347,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to enable interrupt for STOPPED event + SEQSTARTED0 + Write '1' to enable interrupt for event SEQSTARTED[0] 2 2 @@ -39174,8 +38374,62 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXPTRUPD - Write '1' to enable interrupt for TXPTRUPD event + SEQSTARTED1 + Write '1' to enable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND0 + Write '1' to enable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + SEQEND1 + Write '1' to enable interrupt for event SEQEND[1] 5 5 @@ -39200,6 +38454,60 @@ POSSIBILITY OF SUCH DAMAGE.\n + + PWMPERIODEND + Write '1' to enable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + LOOPSDONE + Write '1' to enable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + @@ -39209,8 +38517,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - RXPTRUPD - Write '1' to disable interrupt for RXPTRUPD event + STOPPED + Write '1' to disable interrupt for event STOPPED 1 1 @@ -39236,8 +38544,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - STOPPED - Write '1' to disable interrupt for STOPPED event + SEQSTARTED0 + Write '1' to disable interrupt for event SEQSTARTED[0] 2 2 @@ -39263,8 +38571,62 @@ POSSIBILITY OF SUCH DAMAGE.\n - TXPTRUPD - Write '1' to disable interrupt for TXPTRUPD event + SEQSTARTED1 + Write '1' to disable interrupt for event SEQSTARTED[1] + 3 + 3 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND0 + Write '1' to disable interrupt for event SEQEND[0] + 4 + 4 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + SEQEND1 + Write '1' to disable interrupt for event SEQEND[1] 5 5 @@ -39289,24 +38651,78 @@ POSSIBILITY OF SUCH DAMAGE.\n + + PWMPERIODEND + Write '1' to disable interrupt for event PWMPERIODEND + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + LOOPSDONE + Write '1' to disable interrupt for event LOOPSDONE + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + ENABLE - Enable I2S module. + PWM module enable register 0x500 read-write 0x00000000 ENABLE - Enable I2S module. + Enable or disable PWM module 0 0 Disabled - Disable + Disabled 0 @@ -39318,478 +38734,910 @@ POSSIBILITY OF SUCH DAMAGE.\n - - CONFIG - Unspecified - I2S_CONFIG + + MODE + Selects operating mode of the wave counter 0x504 + read-write + 0x00000000 + + + UPDOWN + Selects up mode or up-and-down mode for the counter + 0 + 0 + + + Up + Up counter, edge-aligned PWM duty cycle + 0 + + + UpAndDown + Up and down counter, center-aligned PWM duty cycle + 1 + + + + + + + COUNTERTOP + Value up to which the pulse generator counter counts + 0x508 + read-write + 0x000003FF + + + COUNTERTOP + Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. + 0 + 14 + + + + + PRESCALER + Configuration for PWM_CLK + 0x50C + read-write + 0x00000000 + + + PRESCALER + Prescaler of PWM_CLK + 0 + 2 + + + DIV_1 + Divide by 1 (16 MHz) + 0 + + + DIV_2 + Divide by 2 (8 MHz) + 1 + + + DIV_4 + Divide by 4 (4 MHz) + 2 + + + DIV_8 + Divide by 8 (2 MHz) + 3 + + + DIV_16 + Divide by 16 (1 MHz) + 4 + + + DIV_32 + Divide by 32 (500 kHz) + 5 + + + DIV_64 + Divide by 64 (250 kHz) + 6 + + + DIV_128 + Divide by 128 (125 kHz) + 7 + + + + + + + DECODER + Configuration of the decoder + 0x510 + read-write + 0x00000000 + + + LOAD + How a sequence is read from RAM and spread to the compare register + 0 + 1 + + + Common + 1st half word (16-bit) used in all PWM channels 0..3 + 0 + + + Grouped + 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 + 1 + + + Individual + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 + 2 + + + WaveForm + 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP + 3 + + + + + MODE + Selects source for advancing the active sequence + 8 + 8 + + + RefreshCount + SEQ[n].REFRESH is used to determine loading internal compare registers + 0 + + + NextStep + NEXTSTEP task causes a new value to be loaded to internal compare registers + 1 + + + + + + + LOOP + Number of playbacks of a loop + 0x514 + read-write + 0x00000000 + + + CNT + Number of playbacks of pattern cycles + 0 + 15 + + + Disabled + Looping disabled (stop at the end of the sequence) + 0 + + + + + + + 2 + 0x020 + SEQ[%s] + Unspecified + PWM_SEQ + read-write + 0x520 - MODE - I2S mode. - 0x000 - read-write - 0x00000000 - - - MODE - I2S mode. - 0 - 0 - - - Master - Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. - 0 - - - Slave - Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx - 1 - - - - - - - RXEN - Reception (RX) enable. - 0x004 - read-write - 0x00000000 - - - RXEN - Reception (RX) enable. - 0 - 0 - - - Disabled - Reception disabled and now data will be written to the RXD.PTR address. - 0 - - - Enabled - Reception enabled. - 1 - - - - - - - TXEN - Transmission (TX) enable. - 0x008 - read-write - 0x00000001 - - - TXEN - Transmission (TX) enable. - 0 - 0 - - - Disabled - Transmission disabled and now data will be read from the RXD.TXD address. - 0 - - - Enabled - Transmission enabled. - 1 - - - - - - - MCKEN - Master clock generator enable. - 0x00C - read-write - 0x00000001 - - - MCKEN - Master clock generator enable. - 0 - 0 - - - Disabled - Master clock generator disabled and PSEL.MCK not connected(available as GPIO). - 0 - - - Enabled - Master clock generator running and MCK output on PSEL.MCK. - 1 - - - - - - - MCKFREQ - Master clock generator frequency. - 0x010 + PTR + Description cluster: Beginning address in RAM of this sequence + 0x000 read-write - 0x20000000 + 0x00000000 - MCKFREQ - Master clock generator frequency. + PTR + Beginning address in RAM of this sequence 0 31 - - - 32MDIV2 - 32 MHz / 2 = 16.0 MHz - 0x80000000 - - - 32MDIV3 - 32 MHz / 3 = 10.6666667 MHz - 0x50000000 - - - 32MDIV4 - 32 MHz / 4 = 8.0 MHz - 0x40000000 - - - 32MDIV5 - 32 MHz / 5 = 6.4 MHz - 0x30000000 - - - 32MDIV6 - 32 MHz / 6 = 5.3333333 MHz - 0x28000000 - - - 32MDIV8 - 32 MHz / 8 = 4.0 MHz - 0x20000000 - - - 32MDIV10 - 32 MHz / 10 = 3.2 MHz - 0x18000000 - - - 32MDIV11 - 32 MHz / 11 = 2.9090909 MHz - 0x16000000 - - - 32MDIV15 - 32 MHz / 15 = 2.1333333 MHz - 0x11000000 - - - 32MDIV16 - 32 MHz / 16 = 2.0 MHz - 0x10000000 - - - 32MDIV21 - 32 MHz / 21 = 1.5238095 - 0x0C000000 - - - 32MDIV23 - 32 MHz / 23 = 1.3913043 MHz - 0x0B000000 - - - 32MDIV30 - 32 MHz / 30 = 1.0666667 MHz - 0x08800000 - - - 32MDIV31 - 32 MHz / 31 = 1.0322581 MHz - 0x08400000 - - - 32MDIV32 - 32 MHz / 32 = 1.0 MHz - 0x08000000 - - - 32MDIV42 - 32 MHz / 42 = 0.7619048 MHz - 0x06000000 - - - 32MDIV63 - 32 MHz / 63 = 0.5079365 MHz - 0x04100000 - - - 32MDIV125 - 32 MHz / 125 = 0.256 MHz - 0x020C0000 - - - RATIO - MCK / LRCK ratio. - 0x014 + CNT + Description cluster: Number of values (duty cycles) in this sequence + 0x004 read-write - 0x00000006 + 0x00000000 - RATIO - MCK / LRCK ratio. + CNT + Number of values (duty cycles) in this sequence 0 - 3 + 14 - 32X - LRCK = MCK / 32 + Disabled + Sequence is disabled, and shall not be started as it is empty 0 - - 48X - LRCK = MCK / 48 - 1 - - - 64X - LRCK = MCK / 64 - 2 - - - 96X - LRCK = MCK / 96 - 3 - - - 128X - LRCK = MCK / 128 - 4 - - - 192X - LRCK = MCK / 192 - 5 - - - 256X - LRCK = MCK / 256 - 6 - - - 384X - LRCK = MCK / 384 - 7 - - - 512X - LRCK = MCK / 512 - 8 - - SWIDTH - Sample width. - 0x018 + REFRESH + Description cluster: Number of additional PWM periods between samples loaded into compare register + 0x008 read-write 0x00000001 - SWIDTH - Sample width. + CNT + Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) 0 - 1 + 23 - 8Bit - 8 bit. + Continuous + Update every PWM period 0 - - 16Bit - 16 bit. - 1 - - - 24Bit - 24 bit. - 2 - - ALIGN - Alignment of sample within a frame. - 0x01C + ENDDELAY + Description cluster: Time added after the sequence + 0x00C read-write 0x00000000 - ALIGN - Alignment of sample within a frame. + CNT + Time added after the sequence in PWM periods 0 - 0 - - - Left - Left-aligned. - 0 - - - Right - Right-aligned. - 1 - - + 23 + + + PSEL + Unspecified + PWM_PSEL + read-write + 0x560 - FORMAT - Frame format. - 0x020 + 0x4 + 0x4 + OUT[%s] + Description collection: Output pin select for PWM channel n + 0x000 read-write - 0x00000000 + 0xFFFFFFFF - FORMAT - Frame format. + PIN + Pin number 0 - 0 - - - I2S - Original I2S format. - 0 - - - Aligned - Alternate (left- or right-aligned) format. - 1 - - + 4 - - - - CHANNELS - Enable channels. - 0x024 - read-write - 0x00000000 - - CHANNELS - Enable channels. - 0 - 1 + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 - Stereo - Stereo. - 0 - - - Left - Left only. + Disconnected + Disconnect 1 - Right - Right only. - 2 + Connected + Connect + 0 - - RXD - Unspecified - I2S_RXD - 0x538 - - PTR - Receive buffer RAM start address. - 0x000 - read-write - 0x00000000 - - - PTR - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. - 0 - 31 - - - - - - TXD - Unspecified - I2S_TXD - 0x540 - - PTR - Transmit buffer RAM start address. - 0x000 - read-write - 0x00000000 - - - PTR - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. - 0 - 31 - - - - - - RXTXD - Unspecified - I2S_RXTXD - 0x550 - - MAXCNT - Size of RXD and TXD buffers. - 0x000 - read-write - 0x00000000 - - - MAXCNT - Size of RXD and TXD buffers in number of 32 bit words. - 0 - 13 - - - - + + + + PDM + Pulse Density Modulation (Digital Microphone) Interface + 0x4001D000 + + 0 + 0x1000 + registers + + + PDM + 29 + + PDM + 0x20 + + + TASKS_START + Starts continuous PDM transfer + 0x000 + write-only + + + TASKS_START + Starts continuous PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + TASKS_STOP + Stops PDM transfer + 0x004 + write-only + + + TASKS_STOP + Stops PDM transfer + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + EVENTS_STARTED + PDM transfer has started + 0x100 + read-write + + + EVENTS_STARTED + PDM transfer has started + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_STOPPED + PDM transfer has finished + 0x104 + read-write + + + EVENTS_STOPPED + PDM transfer has finished + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0x108 + read-write + + + EVENTS_END + The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + STARTED + Enable or disable interrupt for event STARTED + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + STOPPED + Enable or disable interrupt for event STOPPED + 1 + 1 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + END + Enable or disable interrupt for event END + 2 + 2 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + STARTED + Write '1' to enable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + STOPPED + Write '1' to enable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + END + Write '1' to enable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + + + INTENCLR + Disable interrupt + 0x308 + read-write + + + STARTED + Write '1' to disable interrupt for event STARTED + 0 + 0 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + STOPPED + Write '1' to disable interrupt for event STOPPED + 1 + 1 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + END + Write '1' to disable interrupt for event END + 2 + 2 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + + + + + ENABLE + PDM module enable register + 0x500 + read-write + 0x00000000 + + + ENABLE + Enable or disable PDM module + 0 + 0 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + PDMCLKCTRL + PDM clock generator control + 0x504 + read-write + 0x08400000 + + + FREQ + PDM_CLK frequency + 0 + 31 + + + 1000K + PDM_CLK = 32 MHz / 32 = 1.000 MHz + 0x08000000 + + + Default + PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. + 0x08400000 + + + 1067K + PDM_CLK = 32 MHz / 30 = 1.067 MHz + 0x08800000 + + + 1231K + PDM_CLK = 32 MHz / 26 = 1.231 MHz + 0x09800000 + + + 1280K + PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. + 0x0A000000 + + + 1333K + PDM_CLK = 32 MHz / 24 = 1.333 MHz + 0x0A800000 + + + + + + + MODE + Defines the routing of the connected PDM microphones' signals + 0x508 + read-write + 0x00000000 + + + OPERATION + Mono or stereo operation + 0 + 0 + + + Stereo + Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + 0 + + + Mono + Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + 1 + + + + + EDGE + Defines on which PDM_CLK edge Left (or mono) is sampled + 1 + 1 + + + LeftFalling + Left (or mono) is sampled on falling edge of PDM_CLK + 0 + + + LeftRising + Left (or mono) is sampled on rising edge of PDM_CLK + 1 + + + + + + + GAINL + Left output gain adjustment + 0x518 + read-write + 0x00000028 + + + GAINL + Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + GAINR + Right output gain adjustment + 0x51C + read-write + 0x00000028 + + + GAINR + Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) + 0 + 6 + + + MinGain + -20dB gain adjustment (minimum) + 0x00 + + + DefaultGain + 0dB gain adjustment + 0x28 + + + MaxGain + +20dB gain adjustment (maximum) + 0x50 + + + + + + + RATIO + Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. + 0x520 + read-write + 0x00000000 + + + RATIO + Selects the ratio between PDM_CLK and output sample rate + 0 + 0 + + + Ratio64 + Ratio of 64 + 0 + + + Ratio80 + Ratio of 80 + 1 + + + + + PSEL Unspecified - I2S_PSEL - 0x560 + PDM_PSEL + read-write + 0x540 - MCK - Pin select for MCK signal. + CLK + Pin number configuration for PDM CLK signal 0x000 read-write 0xFFFFFFFF @@ -39827,8 +39675,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - SCK - Pin select for SCK signal. + DIN + Pin number configuration for PDM DIN signal 0x004 read-write 0xFFFFFFFF @@ -39865,118 +39713,134 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + SAMPLE + Unspecified + PDM_SAMPLE + read-write + 0x560 - LRCK - Pin select for LRCK signal. - 0x008 + PTR + RAM address pointer to write samples to with EasyDMA + 0x000 read-write - 0xFFFFFFFF - PIN - Pin number + SAMPLEPTR + Address to write PDM samples to over DMA 0 - 4 + 31 + + + + MAXCNT + Number of samples to allocate memory for in EasyDMA mode + 0x004 + read-write + - PORT - Port number - 5 - 5 + BUFFSIZE + Length of DMA RAM allocation in number of samples + 0 + 14 + + + + + + + ACL + Access control lists + 0x4001E000 + + 0 + 0x1000 + registers + + ACL + 0x20 + + + 8 + 0x010 + ACL[%s] + Unspecified + ACL_ACL + read-write + 0x800 + + ADDR + Description cluster: Configure the word-aligned start address of region n to protect + 0x000 + read-writeonce + 0x00000000 + - CONNECT - Connection - 31 + ADDR + Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + 0 31 - - - Disconnected - Disconnect - 1 - - - Connected - Connect - 0 - - - SDIN - Pin select for SDIN signal. - 0x00C - read-write - 0xFFFFFFFF + SIZE + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + 0x004 + read-writeonce + 0x00000000 - PIN - Pin number + SIZE + Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. 0 - 4 - - - PORT - Port number - 5 - 5 + 31 + + + + PERM + Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE + 0x008 + read-writeonce + 0x00000000 + - CONNECT - Connection - 31 - 31 + WRITE + Configure write and erase permissions for region n. Write '0' has no effect. + 1 + 1 - Disconnected - Disconnect - 1 + Enable + Allow write and erase instructions to region n + 0 - Connected - Connect - 0 + Disable + Block write and erase instructions to region n + 1 - - - - SDOUT - Pin select for SDOUT signal. - 0x010 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - CONNECT - Connection - 31 - 31 + READ + Configure read permissions for region n. Write '0' has no effect. + 2 + 2 - Disconnected - Disconnect - 1 + Enable + Allow read instructions to region n + 0 - Connected - Connect - 0 + Disable + Block read instructions to region n + 1 @@ -39986,864 +39850,1815 @@ POSSIBILITY OF SUCH DAMAGE.\n - FPU - FPU - 0x40026000 + NVMC + Non Volatile Memory Controller + 0x4001E000 + ACL 0 0x1000 registers - - FPU - 38 - - FPU + NVMC 0x20 - UNUSED - Unused. - 0x000 - 0x00000000 + READY + Ready flag + 0x400 + read-only + 0x00000001 + + + READY + NVMC is ready or busy + 0 + 0 + + + Busy + NVMC is busy (on-going write or erase operation) + 0 + + + Ready + NVMC is ready + 1 + + + + + + + READYNEXT + Ready flag + 0x408 read-only + + + READYNEXT + NVMC can accept a new write operation + 0 + 0 + + + Busy + NVMC cannot accept any write operation + 0 + + + Ready + NVMC is ready + 1 + + + + + + + CONFIG + Configuration register + 0x504 + read-write + + + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + 0 + 1 + + + Ren + Read only access + 0 + + + Wen + Write enabled + 1 + + + Een + Erase enabled + 2 + + + + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + read-write + + + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x508 + read-write + ERASEPAGE + + + ERASEPCR1 + Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + read-write + + + ERASEALL + Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start chip erase + 1 + + + + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + 0x510 + read-write + + + ERASEPCR0 + Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + 0 + 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + read-write + + + ERASEUICR + Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 + + + NoOperation + No operation + 0 + + + Erase + Start erase of UICR + 1 + + + + + + + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + read-write + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + ICACHECNF + I-code cache configuration register. + 0x540 + read-write + 0x00000000 + + + CACHEEN + Cache enable + 0 + 0 + + + Disabled + Disable cache. Invalidates all cache entries. + 0 + + + Enabled + Enable cache + 1 + + + + + CACHEPROFEN + Cache profiling enable + 8 + 8 + + + Disabled + Disable cache profiling + 0 + + + Enabled + Enable cache profiling + 1 + + + + + + + IHIT + I-code cache hit counter. + 0x548 + read-write + + + HITS + Number of cache hits + 0 + 31 + + + + + IMISS + I-code cache miss counter. + 0x54C + read-write + + + MISSES + Number of cache misses + 0 + 31 + + - USBD - Universal serial bus device - 0x40027000 + PPI + Programmable Peripheral Interconnect + 0x4001F000 0 0x1000 registers - - USBD - 39 - - USBD + PPI 0x20 - - 0x8 - 0x4 - TASKS_STARTEPIN[%s] - Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host - 0x004 + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 + read-write - TASKS_STARTEPIN - 0 - 0 + CH0 + Enable or disable channel 0 + 0 + 0 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH1 + Enable or disable channel 1 + 1 + 1 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH2 + Enable or disable channel 2 + 2 + 2 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH3 + Enable or disable channel 3 + 3 + 3 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_STARTISOIN - Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint - 0x024 - write-only - - TASKS_STARTISOIN - 0 - 0 + CH4 + Enable or disable channel 4 + 4 + 4 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - 0x8 - 0x4 - TASKS_STARTEPOUT[%s] - Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host - 0x028 - write-only - - TASKS_STARTEPOUT - 0 - 0 + CH5 + Enable or disable channel 5 + 5 + 5 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_STARTISOOUT - Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint - 0x048 - write-only - - TASKS_STARTISOOUT - 0 - 0 + CH6 + Enable or disable channel 6 + 6 + 6 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_EP0RCVOUT - Allows OUT data stage on control endpoint 0 - 0x04C - write-only - - TASKS_EP0RCVOUT - 0 - 0 + CH7 + Enable or disable channel 7 + 7 + 7 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_EP0STATUS - Allows status stage on control endpoint 0 - 0x050 - write-only - - TASKS_EP0STATUS - 0 - 0 + CH8 + Enable or disable channel 8 + 8 + 8 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH9 + Enable or disable channel 9 + 9 + 9 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH10 + Enable or disable channel 10 + 10 + 10 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH11 + Enable or disable channel 11 + 11 + 11 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH12 + Enable or disable channel 12 + 12 + 12 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH13 + Enable or disable channel 13 + 13 + 13 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH14 + Enable or disable channel 14 + 14 + 14 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH15 + Enable or disable channel 15 + 15 + 15 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH16 + Enable or disable channel 16 + 16 + 16 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH17 + Enable or disable channel 17 + 17 + 17 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH18 + Enable or disable channel 18 + 18 + 18 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH19 + Enable or disable channel 19 + 19 + 19 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH20 + Enable or disable channel 20 + 20 + 20 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH21 + Enable or disable channel 21 + 21 + 21 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH22 + Enable or disable channel 22 + 22 + 22 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH23 + Enable or disable channel 23 + 23 + 23 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH24 + Enable or disable channel 24 + 24 + 24 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH25 + Enable or disable channel 25 + 25 + 25 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH26 + Enable or disable channel 26 + 26 + 26 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH27 + Enable or disable channel 27 + 27 + 27 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + + + + CH28 + Enable or disable channel 28 + 28 + 28 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_EP0STALL - Stalls data and status stage on control endpoint 0 - 0x054 - write-only - - TASKS_EP0STALL - 0 - 0 + CH29 + Enable or disable channel 29 + 29 + 29 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_DPDMDRIVE - Forces D+ and D- lines into the state defined in the DPDMVALUE register - 0x058 - write-only - - TASKS_DPDMDRIVE - 0 - 0 + CH30 + Enable or disable channel 30 + 30 + 30 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - - - - TASKS_DPDMNODRIVE - Stops forcing D+ and D- lines into any state (USB engine takes control) - 0x05C - write-only - - TASKS_DPDMNODRIVE - 0 - 0 + CH31 + Enable or disable channel 31 + 31 + 31 + + + Disabled + Disable channel + 0 + + + Enabled + Enable channel + 1 + + - EVENTS_USBRESET - Signals that a USB reset condition has been detected on USB lines - 0x100 + CHENSET + Channel enable set register + 0x504 read-write + oneToSet - EVENTS_USBRESET + CH0 + Channel 0 enable set register. Writing '0' has no effect 0 0 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_STARTED - Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register - 0x104 - read-write - - EVENTS_STARTED - 0 - 0 + CH1 + Channel 1 enable set register. Writing '0' has no effect + 1 + 1 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - 0x8 - 0x4 - EVENTS_ENDEPIN[%s] - Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x108 - read-write - - EVENTS_ENDEPIN - 0 - 0 + CH2 + Channel 2 enable set register. Writing '0' has no effect + 2 + 2 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_EP0DATADONE - An acknowledged data transfer has taken place on the control endpoint - 0x128 - read-write - - EVENTS_EP0DATADONE - 0 - 0 + CH3 + Channel 3 enable set register. Writing '0' has no effect + 3 + 3 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x12C - read-write - - EVENTS_ENDISOIN - 0 - 0 + CH4 + Channel 4 enable set register. Writing '0' has no effect + 4 + 4 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - 0x8 - 0x4 - EVENTS_ENDEPOUT[%s] - Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x130 - read-write - - EVENTS_ENDEPOUT - 0 - 0 + CH5 + Channel 5 enable set register. Writing '0' has no effect + 5 + 5 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. - 0x150 - read-write - - EVENTS_ENDISOOUT - 0 - 0 + CH6 + Channel 6 enable set register. Writing '0' has no effect + 6 + 6 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_SOF - Signals that a SOF (start of frame) condition has been detected on USB lines - 0x154 - read-write - - EVENTS_SOF - 0 - 0 + CH7 + Channel 7 enable set register. Writing '0' has no effect + 7 + 7 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_USBEVENT - An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. - 0x158 - read-write - - EVENTS_USBEVENT - 0 - 0 + CH8 + Channel 8 enable set register. Writing '0' has no effect + 8 + 8 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_EP0SETUP - A valid SETUP token has been received (and acknowledged) on the control endpoint - 0x15C - read-write - - EVENTS_EP0SETUP - 0 - 0 + CH9 + Channel 9 enable set register. Writing '0' has no effect + 9 + 9 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - EVENTS_EPDATA - A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register - 0x160 - read-write - - EVENTS_EPDATA - 0 - 0 + CH10 + Channel 10 enable set register. Writing '0' has no effect + 10 + 10 + + read + + Disabled + Read: channel disabled + 0 + + + Enabled + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel + 1 + + - - - - SHORTS - Shortcut register - 0x200 - read-write - - EP0DATADONE_STARTEPIN0 - Shortcut between EP0DATADONE event and STARTEPIN[0] task - 0 - 0 + CH11 + Channel 11 enable set register. Writing '0' has no effect + 11 + 11 + read Disabled - Disable shortcut + Read: channel disabled 0 Enabled - Enable shortcut + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - EP0DATADONE_STARTEPOUT0 - Shortcut between EP0DATADONE event and STARTEPOUT[0] task - 1 - 1 + CH12 + Channel 12 enable set register. Writing '0' has no effect + 12 + 12 + read Disabled - Disable shortcut + Read: channel disabled 0 Enabled - Enable shortcut + Read: channel enabled 1 - - - EP0DATADONE_EP0STATUS - Shortcut between EP0DATADONE event and EP0STATUS task - 2 - 2 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Set + Write: Enable channel 1 - ENDEPOUT0_EP0STATUS - Shortcut between ENDEPOUT[0] event and EP0STATUS task - 3 - 3 + CH13 + Channel 13 enable set register. Writing '0' has no effect + 13 + 13 + read Disabled - Disable shortcut + Read: channel disabled 0 Enabled - Enable shortcut + Read: channel enabled 1 - - - ENDEPOUT0_EP0RCVOUT - Shortcut between ENDEPOUT[0] event and EP0RCVOUT task - 4 - 4 + write - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut + Set + Write: Enable channel 1 - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - USBRESET - Enable or disable interrupt for USBRESET event - 0 - 0 + CH14 + Channel 14 enable set register. Writing '0' has no effect + 14 + 14 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - STARTED - Enable or disable interrupt for STARTED event - 1 - 1 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPIN0 - Enable or disable interrupt for ENDEPIN[0] event - 2 - 2 + CH15 + Channel 15 enable set register. Writing '0' has no effect + 15 + 15 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDEPIN1 - Enable or disable interrupt for ENDEPIN[1] event - 3 - 3 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPIN2 - Enable or disable interrupt for ENDEPIN[2] event - 4 - 4 + CH16 + Channel 16 enable set register. Writing '0' has no effect + 16 + 16 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDEPIN3 - Enable or disable interrupt for ENDEPIN[3] event - 5 - 5 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPIN4 - Enable or disable interrupt for ENDEPIN[4] event - 6 - 6 + CH17 + Channel 17 enable set register. Writing '0' has no effect + 17 + 17 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDEPIN5 - Enable or disable interrupt for ENDEPIN[5] event - 7 - 7 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPIN6 - Enable or disable interrupt for ENDEPIN[6] event - 8 - 8 + CH18 + Channel 18 enable set register. Writing '0' has no effect + 18 + 18 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDEPIN7 - Enable or disable interrupt for ENDEPIN[7] event - 9 - 9 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - EP0DATADONE - Enable or disable interrupt for EP0DATADONE event - 10 - 10 + CH19 + Channel 19 enable set register. Writing '0' has no effect + 19 + 19 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDISOIN - Enable or disable interrupt for ENDISOIN event - 11 - 11 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPOUT0 - Enable or disable interrupt for ENDEPOUT[0] event - 12 - 12 + CH20 + Channel 20 enable set register. Writing '0' has no effect + 20 + 20 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled 1 - - - ENDEPOUT1 - Enable or disable interrupt for ENDEPOUT[1] event - 13 - 13 + write - Disabled - Disable - 0 - - - Enabled - Enable + Set + Write: Enable channel 1 - ENDEPOUT2 - Enable or disable interrupt for ENDEPOUT[2] event - 14 - 14 + CH21 + Channel 21 enable set register. Writing '0' has no effect + 21 + 21 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDEPOUT3 - Enable or disable interrupt for ENDEPOUT[3] event - 15 - 15 + CH22 + Channel 22 enable set register. Writing '0' has no effect + 22 + 22 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDEPOUT4 - Enable or disable interrupt for ENDEPOUT[4] event - 16 - 16 + CH23 + Channel 23 enable set register. Writing '0' has no effect + 23 + 23 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDEPOUT5 - Enable or disable interrupt for ENDEPOUT[5] event - 17 - 17 + CH24 + Channel 24 enable set register. Writing '0' has no effect + 24 + 24 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDEPOUT6 - Enable or disable interrupt for ENDEPOUT[6] event - 18 - 18 + CH25 + Channel 25 enable set register. Writing '0' has no effect + 25 + 25 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDEPOUT7 - Enable or disable interrupt for ENDEPOUT[7] event - 19 - 19 + CH26 + Channel 26 enable set register. Writing '0' has no effect + 26 + 26 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - ENDISOOUT - Enable or disable interrupt for ENDISOOUT event - 20 - 20 + CH27 + Channel 27 enable set register. Writing '0' has no effect + 27 + 27 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - SOF - Enable or disable interrupt for SOF event - 21 - 21 + CH28 + Channel 28 enable set register. Writing '0' has no effect + 28 + 28 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - USBEVENT - Enable or disable interrupt for USBEVENT event - 22 - 22 + CH29 + Channel 29 enable set register. Writing '0' has no effect + 29 + 29 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - EP0SETUP - Enable or disable interrupt for EP0SETUP event - 23 - 23 + CH30 + Channel 30 enable set register. Writing '0' has no effect + 30 + 30 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 - EPDATA - Enable or disable interrupt for EPDATA event - 24 - 24 + CH31 + Channel 31 enable set register. Writing '0' has no effect + 31 + 31 + read Disabled - Disable + Read: channel disabled 0 Enabled - Enable + Read: channel enabled + 1 + + + + write + + Set + Write: Enable channel 1 @@ -40851,709 +41666,702 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTENSET - Enable interrupt - 0x304 + CHENCLR + Channel enable clear register + 0x508 read-write + oneToClear - USBRESET - Write '1' to enable interrupt for USBRESET event + CH0 + Channel 0 enable clear register. Writing '0' has no effect 0 0 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - STARTED - Write '1' to enable interrupt for STARTED event + CH1 + Channel 1 enable clear register. Writing '0' has no effect 1 1 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN0 - Write '1' to enable interrupt for ENDEPIN[0] event + CH2 + Channel 2 enable clear register. Writing '0' has no effect 2 2 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - - Set - Enable + + Clear + Write: disable channel 1 - ENDEPIN1 - Write '1' to enable interrupt for ENDEPIN[1] event + CH3 + Channel 3 enable clear register. Writing '0' has no effect 3 3 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN2 - Write '1' to enable interrupt for ENDEPIN[2] event + CH4 + Channel 4 enable clear register. Writing '0' has no effect 4 4 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN3 - Write '1' to enable interrupt for ENDEPIN[3] event + CH5 + Channel 5 enable clear register. Writing '0' has no effect 5 5 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN4 - Write '1' to enable interrupt for ENDEPIN[4] event + CH6 + Channel 6 enable clear register. Writing '0' has no effect 6 6 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN5 - Write '1' to enable interrupt for ENDEPIN[5] event + CH7 + Channel 7 enable clear register. Writing '0' has no effect 7 7 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN6 - Write '1' to enable interrupt for ENDEPIN[6] event + CH8 + Channel 8 enable clear register. Writing '0' has no effect 8 8 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPIN7 - Write '1' to enable interrupt for ENDEPIN[7] event + CH9 + Channel 9 enable clear register. Writing '0' has no effect 9 9 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - EP0DATADONE - Write '1' to enable interrupt for EP0DATADONE event + CH10 + Channel 10 enable clear register. Writing '0' has no effect 10 10 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDISOIN - Write '1' to enable interrupt for ENDISOIN event + CH11 + Channel 11 enable clear register. Writing '0' has no effect 11 11 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT0 - Write '1' to enable interrupt for ENDEPOUT[0] event + CH12 + Channel 12 enable clear register. Writing '0' has no effect 12 12 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT1 - Write '1' to enable interrupt for ENDEPOUT[1] event + CH13 + Channel 13 enable clear register. Writing '0' has no effect 13 13 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT2 - Write '1' to enable interrupt for ENDEPOUT[2] event + CH14 + Channel 14 enable clear register. Writing '0' has no effect 14 14 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT3 - Write '1' to enable interrupt for ENDEPOUT[3] event + CH15 + Channel 15 enable clear register. Writing '0' has no effect 15 15 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT4 - Write '1' to enable interrupt for ENDEPOUT[4] event + CH16 + Channel 16 enable clear register. Writing '0' has no effect 16 16 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT5 - Write '1' to enable interrupt for ENDEPOUT[5] event + CH17 + Channel 17 enable clear register. Writing '0' has no effect 17 17 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT6 - Write '1' to enable interrupt for ENDEPOUT[6] event + CH18 + Channel 18 enable clear register. Writing '0' has no effect 18 18 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDEPOUT7 - Write '1' to enable interrupt for ENDEPOUT[7] event + CH19 + Channel 19 enable clear register. Writing '0' has no effect 19 19 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - ENDISOOUT - Write '1' to enable interrupt for ENDISOOUT event + CH20 + Channel 20 enable clear register. Writing '0' has no effect 20 20 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - SOF - Write '1' to enable interrupt for SOF event + CH21 + Channel 21 enable clear register. Writing '0' has no effect 21 21 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - USBEVENT - Write '1' to enable interrupt for USBEVENT event + CH22 + Channel 22 enable clear register. Writing '0' has no effect 22 22 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - EP0SETUP - Write '1' to enable interrupt for EP0SETUP event + CH23 + Channel 23 enable clear register. Writing '0' has no effect 23 23 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - EPDATA - Write '1' to enable interrupt for EPDATA event + CH24 + Channel 24 enable clear register. Writing '0' has no effect 24 24 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 write - Set - Enable + Clear + Write: disable channel 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - USBRESET - Write '1' to disable interrupt for USBRESET event - 0 - 0 + CH25 + Channel 25 enable clear register. Writing '0' has no effect + 25 + 25 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41561,26 +42369,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - STARTED - Write '1' to disable interrupt for STARTED event - 1 - 1 + CH26 + Channel 26 enable clear register. Writing '0' has no effect + 26 + 26 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41588,26 +42396,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - ENDEPIN0 - Write '1' to disable interrupt for ENDEPIN[0] event - 2 - 2 + CH27 + Channel 27 enable clear register. Writing '0' has no effect + 27 + 27 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41615,26 +42423,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - ENDEPIN1 - Write '1' to disable interrupt for ENDEPIN[1] event - 3 - 3 + CH28 + Channel 28 enable clear register. Writing '0' has no effect + 28 + 28 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41642,26 +42450,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - ENDEPIN2 - Write '1' to disable interrupt for ENDEPIN[2] event - 4 - 4 + CH29 + Channel 29 enable clear register. Writing '0' has no effect + 29 + 29 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41669,26 +42477,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - ENDEPIN3 - Write '1' to disable interrupt for ENDEPIN[3] event - 5 - 5 + CH30 + Channel 30 enable clear register. Writing '0' has no effect + 30 + 30 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41696,26 +42504,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel 1 - ENDEPIN4 - Write '1' to disable interrupt for ENDEPIN[4] event - 6 - 6 + CH31 + Channel 31 enable clear register. Writing '0' has no effect + 31 + 31 read Disabled - Read: Disabled + Read: channel disabled 0 Enabled - Read: Enabled + Read: channel enabled 1 @@ -41723,592 +42531,630 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Disable + Write: disable channel + 1 + + + + + + + 20 + 0x008 + CH[%s] + PPI Channel + PPI_CH + read-write + 0x510 + + EEP + Description cluster: Channel n event end-point + 0x000 + read-write + + + EEP + Pointer to event register. Accepts only addresses to registers from the Event group. + 0 + 31 + + + + + TEP + Description cluster: Channel n task end-point + 0x004 + read-write + + + TEP + Pointer to task register. Accepts only addresses to registers from the Task group. + 0 + 31 + + + + + + 0x6 + 0x4 + CHG[%s] + Description collection: Channel group n + 0x800 + read-write + + + CH0 + Include or exclude channel 0 + 0 + 0 + + + Excluded + Exclude + 0 + + + Included + Include 1 - ENDEPIN5 - Write '1' to disable interrupt for ENDEPIN[5] event - 7 - 7 + CH1 + Include or exclude channel 1 + 1 + 1 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled + Included + Include + 1 + + + + + CH2 + Include or exclude channel 2 + 2 + 2 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH3 + Include or exclude channel 3 + 3 + 3 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH4 + Include or exclude channel 4 + 4 + 4 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH5 + Include or exclude channel 5 + 5 + 5 + + + Excluded + Exclude + 0 + + + Included + Include + 1 + + + + + CH6 + Include or exclude channel 6 + 6 + 6 + + + Excluded + Exclude + 0 + + + Included + Include 1 + + + CH7 + Include or exclude channel 7 + 7 + 7 - write - Clear - Disable + Excluded + Exclude + 0 + + + Included + Include 1 - ENDEPIN6 - Write '1' to disable interrupt for ENDEPIN[6] event + CH8 + Include or exclude channel 8 8 8 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPIN7 - Write '1' to disable interrupt for ENDEPIN[7] event + CH9 + Include or exclude channel 9 9 9 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - EP0DATADONE - Write '1' to disable interrupt for EP0DATADONE event + CH10 + Include or exclude channel 10 10 10 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDISOIN - Write '1' to disable interrupt for ENDISOIN event + CH11 + Include or exclude channel 11 11 11 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT0 - Write '1' to disable interrupt for ENDEPOUT[0] event + CH12 + Include or exclude channel 12 12 12 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT1 - Write '1' to disable interrupt for ENDEPOUT[1] event + CH13 + Include or exclude channel 13 13 13 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT2 - Write '1' to disable interrupt for ENDEPOUT[2] event + CH14 + Include or exclude channel 14 14 14 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT3 - Write '1' to disable interrupt for ENDEPOUT[3] event + CH15 + Include or exclude channel 15 15 15 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT4 - Write '1' to disable interrupt for ENDEPOUT[4] event + CH16 + Include or exclude channel 16 16 16 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT5 - Write '1' to disable interrupt for ENDEPOUT[5] event + CH17 + Include or exclude channel 17 17 17 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT6 - Write '1' to disable interrupt for ENDEPOUT[6] event + CH18 + Include or exclude channel 18 18 18 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDEPOUT7 - Write '1' to disable interrupt for ENDEPOUT[7] event + CH19 + Include or exclude channel 19 19 19 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - ENDISOOUT - Write '1' to disable interrupt for ENDISOOUT event + CH20 + Include or exclude channel 20 20 20 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - SOF - Write '1' to disable interrupt for SOF event + CH21 + Include or exclude channel 21 21 21 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - USBEVENT - Write '1' to disable interrupt for USBEVENT event + CH22 + Include or exclude channel 22 22 22 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable + Included + Include 1 - EP0SETUP - Write '1' to disable interrupt for EP0SETUP event + CH23 + Include or exclude channel 23 23 23 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled + Included + Include 1 + + + CH24 + Include or exclude channel 24 + 24 + 24 - write - Clear - Disable + Excluded + Exclude + 0 + + + Included + Include 1 - EPDATA - Write '1' to disable interrupt for EPDATA event - 24 - 24 + CH25 + Include or exclude channel 25 + 25 + 25 - read - Disabled - Read: Disabled + Excluded + Exclude 0 - Enabled - Read: Enabled + Included + Include 1 + + + CH26 + Include or exclude channel 26 + 26 + 26 - write - Clear - Disable + Excluded + Exclude + 0 + + + Included + Include 1 - - - - EVENTCAUSE - Details on what caused the USBEVENT event - 0x400 - read-write - oneToClear - - ISOOUTCRC - CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. - 0 - 0 + CH27 + Include or exclude channel 27 + 27 + 27 - NotDetected - No error detected + Excluded + Exclude 0 - Detected - Error detected + Included + Include 1 - SUSPEND - Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. - 8 - 8 + CH28 + Include or exclude channel 28 + 28 + 28 - NotDetected - Suspend not detected + Excluded + Exclude 0 - Detected - Suspend detected + Included + Include 1 - RESUME - Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. - 9 - 9 + CH29 + Include or exclude channel 29 + 29 + 29 - NotDetected - Resume not detected + Excluded + Exclude 0 - Detected - Resume detected + Included + Include 1 - USBWUALLOWED - USB MAC has been woken up and operational. Write '1' to clear. - 10 - 10 + CH30 + Include or exclude channel 30 + 30 + 30 - NotAllowed - Wake up not allowed + Excluded + Exclude 0 - Allowed - Wake up allowed + Included + Include 1 - READY - USB device is ready for normal operation. Write '1' to clear. - 11 - 11 + CH31 + Include or exclude channel 31 + 31 + 31 - NotDetected - USBEVENT was not issued due to USBD peripheral ready + Excluded + Exclude 0 - Ready - USBD peripheral is ready + Included + Include 1 @@ -42316,32 +43162,135 @@ POSSIBILITY OF SUCH DAMAGE.\n - HALTED - Unspecified - USBD_HALTED - 0x420 + 32 + 0x004 + FORK[%s] + Fork + PPI_FORK + read-write + 0x910 + + TEP + Description cluster: Channel n task end-point + 0x000 + read-write + + + TEP + Pointer to task register + 0 + 31 + + + + + + + + MWU + Memory Watch Unit + 0x40020000 + + 0 + 0x1000 + registers + + + MWU + 32 + + MWU + 0x20 + + + 4 + 0x008 + EVENTS_REGION[%s] + Peripheral events. + MWU_EVENTS_REGION + read-write + 0x100 + + WA + Description cluster: Write access to region n detected + 0x000 + read-write + + + WA + Write access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + RA + Description cluster: Read access to region n detected + 0x004 + read-write + + + RA + Read access to region n detected + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + + + + 2 + 0x008 + EVENTS_PREGION[%s] + Peripheral events. + MWU_EVENTS_PREGION + read-write + 0x160 - 0x8 - 0x4 - EPIN[%s] - Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + WA + Description cluster: Write access to peripheral region n detected 0x000 - read-only + read-write - GETSTATUS - IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + WA + Write access to peripheral region n detected 0 - 15 + 0 - NotHalted - Endpoint is not halted + NotGenerated + Event not generated 0 - Halted - Endpoint is halted + Generated + Event generated 1 @@ -42349,27 +43298,25 @@ POSSIBILITY OF SUCH DAMAGE.\n - 0x8 - 0x4 - EPOUT[%s] - Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. - 0x024 - read-only + RA + Description cluster: Read access to peripheral region n detected + 0x004 + read-write - GETSTATUS - OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + RA + Read access to peripheral region n detected 0 - 15 + 0 - NotHalted - Endpoint is not halted + NotGenerated + Event not generated 0 - Halted - Endpoint is halted + Generated + Event generated 1 @@ -42378,1212 +43325,1111 @@ POSSIBILITY OF SUCH DAMAGE.\n - EPSTATUS - Provides information on which endpoint's EasyDMA registers have been captured - 0x468 + INTEN + Enable or disable interrupt + 0x300 read-write - oneToClear - EPIN0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION0WA + Enable or disable interrupt for event REGION0WA 0 0 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION0RA + Enable or disable interrupt for event REGION0RA 1 1 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION1WA + Enable or disable interrupt for event REGION1WA 2 2 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION1RA + Enable or disable interrupt for event REGION1RA 3 3 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION2WA + Enable or disable interrupt for event REGION2WA 4 4 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION2RA + Enable or disable interrupt for event REGION2RA 5 5 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION3WA + Enable or disable interrupt for event REGION3WA 6 6 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. + REGION3RA + Enable or disable interrupt for event REGION3RA 7 7 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPIN8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 8 - 8 + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPOUT0 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 16 - 16 + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPOUT1 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 17 - 17 + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 - EPOUT2 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 18 - 18 + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Disable 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - EPOUT3 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 19 - 19 + REGION0WA + Write '1' to enable interrupt for event REGION0WA + 0 + 0 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPOUT4 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 20 - 20 + REGION0RA + Write '1' to enable interrupt for event REGION0RA + 1 + 1 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPOUT5 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 21 - 21 + REGION1WA + Write '1' to enable interrupt for event REGION1WA + 2 + 2 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPOUT6 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 22 - 22 + REGION1RA + Write '1' to enable interrupt for event REGION1RA + 3 + 3 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPOUT7 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 23 - 23 + REGION2WA + Write '1' to enable interrupt for event REGION2WA + 4 + 4 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPOUT8 - Captured state of endpoint's EasyDMA registers. Write '1' to clear. - 24 - 24 + REGION2RA + Write '1' to enable interrupt for event REGION2RA + 5 + 5 + read - NoData - EasyDMA registers have not been captured for this endpoint + Disabled + Read: Disabled 0 - DataDone - EasyDMA registers have been captured for this endpoint + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - EPDATASTATUS - Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) - 0x46C - read-write - oneToClear - - EPIN1 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 1 - 1 + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPIN2 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 2 - 2 + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPIN3 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 3 - 3 + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPIN4 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 4 - 4 + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + + read + + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - EPIN5 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 5 - 5 + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled 1 - - - EPIN6 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 6 - 6 + write - NotDone - No acknowledged data transfer on this endpoint - 0 - - - DataDone - Acknowledged data transfer on this endpoint has occurred + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - EPIN7 - Acknowledged data transfer on this IN endpoint. Write '1' to clear. - 7 - 7 + REGION0WA + Write '1' to disable interrupt for event REGION0WA + 0 + 0 + read - NotDone - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - DataDone - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled 1 - - - EPOUT1 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 17 - 17 + write - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred + Clear + Disable 1 - EPOUT2 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 18 - 18 + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + read - NotStarted - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - Started - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled 1 - - - EPOUT3 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 19 - 19 + write - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred + Clear + Disable 1 - EPOUT4 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 20 - 20 + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + read - NotStarted - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - Started - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled 1 - - - EPOUT5 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 21 - 21 + write - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred + Clear + Disable 1 - EPOUT6 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 22 - 22 + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + read - NotStarted - No acknowledged data transfer on this endpoint + Disabled + Read: Disabled 0 - Started - Acknowledged data transfer on this endpoint has occurred + Enabled + Read: Enabled 1 - - - EPOUT7 - Acknowledged data transfer on this OUT endpoint. Write '1' to clear. - 23 - 23 + write - NotStarted - No acknowledged data transfer on this endpoint - 0 - - - Started - Acknowledged data transfer on this endpoint has occurred + Clear + Disable 1 - - - - USBADDR - Device USB address - 0x470 - read-only - - - ADDR - Device USB address - 0 - 6 - - - - - BMREQUESTTYPE - SETUP data, byte 0, bmRequestType - 0x480 - read-only - 0x00000000 - - RECIPIENT - Data transfer type - 0 + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 4 + read - Device - Device + Disabled + Read: Disabled 0 - Interface - Interface + Enabled + Read: Enabled 1 + + + write - Endpoint - Endpoint - 2 - - - Other - Other - 3 + Clear + Disable + 1 - TYPE - Data transfer type + REGION2RA + Write '1' to disable interrupt for event REGION2RA 5 - 6 + 5 + read - Standard - Standard + Disabled + Read: Disabled 0 - Class - Class + Enabled + Read: Enabled 1 + + + write - Vendor - Vendor - 2 + Clear + Disable + 1 - DIRECTION - Data transfer direction - 7 - 7 + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + read - HostToDevice - Host-to-device + Disabled + Read: Disabled 0 - DeviceToHost - Device-to-host + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - BREQUEST - SETUP data, byte 1, bRequest - 0x484 - read-only - 0x00000000 - - BREQUEST - SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. - 0 + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 7 + read - STD_GET_STATUS - Standard request GET_STATUS + Disabled + Read: Disabled 0 - STD_CLEAR_FEATURE - Standard request CLEAR_FEATURE + Enabled + Read: Enabled 1 + + + write - STD_SET_FEATURE - Standard request SET_FEATURE - 3 - - - STD_SET_ADDRESS - Standard request SET_ADDRESS - 5 - - - STD_GET_DESCRIPTOR - Standard request GET_DESCRIPTOR - 6 - - - STD_SET_DESCRIPTOR - Standard request SET_DESCRIPTOR - 7 - - - STD_GET_CONFIGURATION - Standard request GET_CONFIGURATION - 8 - - - STD_SET_CONFIGURATION - Standard request SET_CONFIGURATION - 9 - - - STD_GET_INTERFACE - Standard request GET_INTERFACE - 10 - - - STD_SET_INTERFACE - Standard request SET_INTERFACE - 11 - - - STD_SYNCH_FRAME - Standard request SYNCH_FRAME - 12 + Clear + Disable + 1 - - - - WVALUEL - SETUP data, byte 2, LSB of wValue - 0x488 - read-only - 0x00000000 - - - WVALUEL - SETUP data, byte 2, LSB of wValue - 0 - 7 - - - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0x48C - read-only - 0x00000000 - - - WVALUEH - SETUP data, byte 3, MSB of wValue - 0 - 7 - - - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0x490 - read-only - 0x00000000 - - - WINDEXL - SETUP data, byte 4, LSB of wIndex - 0 - 7 - - - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0x494 - read-only - 0x00000000 - - - WINDEXH - SETUP data, byte 5, MSB of wIndex - 0 - 7 - - - - - WLENGTHL - SETUP data, byte 6, LSB of wLength - 0x498 - read-only - 0x00000000 - - - WLENGTHL - SETUP data, byte 6, LSB of wLength - 0 - 7 - - - - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0x49C - read-only - 0x00000000 - - - WLENGTHH - SETUP data, byte 7, MSB of wLength - 0 - 7 - - - - - SIZE - Unspecified - USBD_SIZE - 0x4A0 - - 0x8 - 0x4 - EPOUT[%s] - Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint - 0x000 - read-write - - - SIZE - Number of bytes received last in the data stage of this OUT endpoint - 0 - 6 - - - - - ISOOUT - Number of bytes received last on this ISO OUT data endpoint - 0x020 - read-only - 0x00010000 - - - SIZE - Number of bytes received last on this ISO OUT data endpoint - 0 - 9 - - - ZERO - Zero-length data packet received - 16 - 16 - - - Normal - No zero-length data received, use value in SIZE - 0 - - - ZeroData - Zero-length data received, ignore value in SIZE - 1 - - - - - - - - ENABLE - Enable USB - 0x500 - read-write - - ENABLE - Enable USB - 0 - 0 + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + read Disabled - USB peripheral is disabled + Read: Disabled 0 - Enabled - USB peripheral is enabled + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - USBPULLUP - Control of the USB pull-up - 0x504 - read-write - - CONNECT - Control of the USB pull-up on the D+ line - 0 - 0 + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 + read Disabled - Pull-up is disconnected + Read: Disabled 0 Enabled - Pull-up is connected to D+ + Read: Enabled 1 - - - - - DPDMVALUE - State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). - 0x508 - read-write - - - STATE - State D+ and D- lines will be forced into by the DPDMDRIVE task - 0 - 4 + write - Resume - D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + Clear + Disable 1 - - J - D+ forced high, D- forced low (J state) - 2 - - - K - D+ forced low, D- forced high (K state) - 4 - - - - - DTOGGLE - Data toggle control and status - 0x50C - read-write - 0x00000100 - - - EP - Select bulk endpoint number - 0 - 2 - - IO - Selects IN or OUT endpoint - 7 - 7 + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 + read - Out - Selects OUT endpoint + Disabled + Read: Disabled 0 - In - Selects IN endpoint + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - VALUE - Data toggle value - 8 - 9 + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + read - Nop - No action on data toggle when writing the register with this value + Disabled + Read: Disabled 0 - Data0 - Data toggle is DATA0 on endpoint set by EP and IO + Enabled + Read: Enabled 1 + + + write - Data1 - Data toggle is DATA1 on endpoint set by EP and IO - 2 + Clear + Disable + 1 - EPINEN - Endpoint IN enable - 0x510 + NMIEN + Enable or disable interrupt + 0x320 read-write - 0x00000001 - IN0 - Enable IN endpoint 0 + REGION0WA + Enable or disable interrupt for event REGION0WA 0 0 - Disable - Disable endpoint IN 0 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 0 (response to IN tokens) + Enabled + Enable 1 - IN1 - Enable IN endpoint 1 + REGION0RA + Enable or disable interrupt for event REGION0RA 1 1 - Disable - Disable endpoint IN 1 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 1 (response to IN tokens) + Enabled + Enable 1 - IN2 - Enable IN endpoint 2 + REGION1WA + Enable or disable interrupt for event REGION1WA 2 2 - Disable - Disable endpoint IN 2 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 2 (response to IN tokens) + Enabled + Enable 1 - IN3 - Enable IN endpoint 3 + REGION1RA + Enable or disable interrupt for event REGION1RA 3 3 - Disable - Disable endpoint IN 3 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 3 (response to IN tokens) + Enabled + Enable 1 - IN4 - Enable IN endpoint 4 + REGION2WA + Enable or disable interrupt for event REGION2WA 4 4 - Disable - Disable endpoint IN 4 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 4 (response to IN tokens) + Enabled + Enable 1 - IN5 - Enable IN endpoint 5 + REGION2RA + Enable or disable interrupt for event REGION2RA 5 5 - Disable - Disable endpoint IN 5 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 5 (response to IN tokens) + Enabled + Enable 1 - IN6 - Enable IN endpoint 6 + REGION3WA + Enable or disable interrupt for event REGION3WA 6 6 - Disable - Disable endpoint IN 6 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 6 (response to IN tokens) + Enabled + Enable 1 - IN7 - Enable IN endpoint 7 + REGION3RA + Enable or disable interrupt for event REGION3RA 7 7 - Disable - Disable endpoint IN 7 (no response to IN tokens) + Disabled + Disable 0 - Enable - Enable endpoint IN 7 (response to IN tokens) + Enabled + Enable 1 - ISOIN - Enable ISO IN endpoint - 8 - 8 + PREGION0WA + Enable or disable interrupt for event PREGION0WA + 24 + 24 - Disable - Disable ISO IN endpoint 8 + Disabled + Disable 0 - Enable - Enable ISO IN endpoint 8 + Enabled + Enable + 1 + + + + + PREGION0RA + Enable or disable interrupt for event PREGION0RA + 25 + 25 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1WA + Enable or disable interrupt for event PREGION1WA + 26 + 26 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + PREGION1RA + Enable or disable interrupt for event PREGION1RA + 27 + 27 + + + Disabled + Disable + 0 + + + Enabled + Enable 1 @@ -43591,170 +44437,331 @@ POSSIBILITY OF SUCH DAMAGE.\n - EPOUTEN - Endpoint OUT enable - 0x514 + NMIENSET + Enable interrupt + 0x324 read-write - 0x00000001 - OUT0 - Enable OUT endpoint 0 + REGION0WA + Write '1' to enable interrupt for event REGION0WA 0 0 + read - Disable - Disable endpoint OUT 0 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 0 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT1 - Enable OUT endpoint 1 + REGION0RA + Write '1' to enable interrupt for event REGION0RA 1 1 + read - Disable - Disable endpoint OUT 1 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 1 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT2 - Enable OUT endpoint 2 + REGION1WA + Write '1' to enable interrupt for event REGION1WA 2 2 + read - Disable - Disable endpoint OUT 2 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 2 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT3 - Enable OUT endpoint 3 + REGION1RA + Write '1' to enable interrupt for event REGION1RA 3 3 + read - Disable - Disable endpoint OUT 3 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 3 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT4 - Enable OUT endpoint 4 + REGION2WA + Write '1' to enable interrupt for event REGION2WA 4 4 + read - Disable - Disable endpoint OUT 4 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 4 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT5 - Enable OUT endpoint 5 + REGION2RA + Write '1' to enable interrupt for event REGION2RA 5 5 + read - Disable - Disable endpoint OUT 5 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 5 (response to OUT tokens) + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3WA + Write '1' to enable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + REGION3RA + Write '1' to enable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0WA + Write '1' to enable interrupt for event PREGION0WA + 24 + 24 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + PREGION0RA + Write '1' to enable interrupt for event PREGION0RA + 25 + 25 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - OUT6 - Enable OUT endpoint 6 - 6 - 6 + PREGION1WA + Write '1' to enable interrupt for event PREGION1WA + 26 + 26 + read - Disable - Disable endpoint OUT 6 (no response to OUT tokens) + Disabled + Read: Disabled 0 - Enable - Enable endpoint OUT 6 (response to OUT tokens) + Enabled + Read: Enabled 1 - - - OUT7 - Enable OUT endpoint 7 - 7 - 7 + write - Disable - Disable endpoint OUT 7 (no response to OUT tokens) - 0 - - - Enable - Enable endpoint OUT 7 (response to OUT tokens) + Set + Enable 1 - ISOOUT - Enable ISO OUT endpoint 8 - 8 - 8 + PREGION1RA + Write '1' to enable interrupt for event PREGION1RA + 27 + 27 + read - Disable - Disable ISO OUT endpoint 8 + Disabled + Read: Disabled 0 - Enable - Enable ISO OUT endpoint 8 + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 @@ -43762,488 +44769,259 @@ POSSIBILITY OF SUCH DAMAGE.\n - EPSTALL - STALL endpoints - 0x518 - write-only - 0x00000000 - modifyExternal + NMIENCLR + Disable interrupt + 0x328 + read-write - EP - Select endpoint number + REGION0WA + Write '1' to disable interrupt for event REGION0WA 0 - 2 - - - IO - Selects IN or OUT endpoint - 7 - 7 + 0 + read - Out - Selects OUT endpoint + Disabled + Read: Disabled 0 - In - Selects IN endpoint + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - STALL - Stall selected endpoint - 8 - 8 + REGION0RA + Write '1' to disable interrupt for event REGION0RA + 1 + 1 + read - UnStall - Don't stall selected endpoint + Disabled + Read: Disabled 0 - Stall - Stall selected endpoint + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ISOSPLIT - Controls the split of ISO buffers - 0x51C - read-write - - SPLIT - Controls the split of ISO buffers - 0 - 15 + REGION1WA + Write '1' to disable interrupt for event REGION1WA + 2 + 2 + read - OneDir - Full buffer dedicated to either iso IN or OUT - 0x0000 + Disabled + Read: Disabled + 0 - HalfIN - Lower half for IN, upper half for OUT - 0x0080 + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 - - - - FRAMECNTR - Returns the current value of the start of frame counter - 0x520 - read-only - - - FRAMECNTR - Returns the current value of the start of frame counter - 0 - 10 - - - - - LOWPOWER - Controls USBD peripheral low power mode during USB suspend - 0x52C - read-write - 0x00000000 - - LOWPOWER - Controls USBD peripheral low-power mode during USB suspend - 0 - 0 + REGION1RA + Write '1' to disable interrupt for event REGION1RA + 3 + 3 + read - ForceNormal - Software must write this value to exit low power mode and before performing a remote wake-up + Disabled + Read: Disabled 0 - LowPower - Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - ISOINCONFIG - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0x530 - read-write - - RESPONSE - Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent - 0 - 0 + REGION2WA + Write '1' to disable interrupt for event REGION2WA + 4 + 4 + read - NoResp - Endpoint does not respond in that case + Disabled + Read: Disabled 0 - ZeroData - Endpoint responds with a zero-length data packet in that case + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - 8 - 0x014 - EPIN[%s] - Unspecified - USBD_EPIN - 0x600 - - PTR - Description cluster[n]: Data pointer - 0x000 - read-write - - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 - - - - - MAXCNT - Description cluster[n]: Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 6 - - - - - AMOUNT - Description cluster[n]: Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 - - - - - - ISOIN - Unspecified - USBD_ISOIN - 0x6A0 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 - - - - - MAXCNT - Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - 8 - 0x014 - EPOUT[%s] - Unspecified - USBD_EPOUT - 0x700 - - PTR - Description cluster[n]: Data pointer - 0x000 - read-write - - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 - - - - - MAXCNT - Description cluster[n]: Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 6 - - - - - AMOUNT - Description cluster[n]: Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 6 - - - - - - ISOOUT - Unspecified - USBD_ISOOUT - 0x7A0 - - PTR - Data pointer - 0x000 - read-write - - - PTR - Data pointer. Accepts any address in Data RAM. - 0 - 31 - - - - - MAXCNT - Maximum number of bytes to transfer - 0x004 - read-write - - - MAXCNT - Maximum number of bytes to transfer - 0 - 9 - - - - - AMOUNT - Number of bytes transferred in the last transaction - 0x008 - read-only - - - AMOUNT - Number of bytes transferred in the last transaction - 0 - 9 - - - - - - - - UARTE1 - UART with EasyDMA 1 - 0x40028000 - - UARTE1 - 40 - - - - QSPI - External flash interface - 0x40029000 - - 0 - 0x1000 - registers - - - QSPI - 41 - - QSPI - 0x20 - - - TASKS_ACTIVATE - Activate QSPI interface - 0x000 - write-only - - - TASKS_ACTIVATE - 0 - 0 - - - - - TASKS_READSTART - Start transfer from external flash memory to internal RAM - 0x004 - write-only - - - TASKS_READSTART - 0 - 0 - - - - - TASKS_WRITESTART - Start transfer from internal RAM to external flash memory - 0x008 - write-only - - - TASKS_WRITESTART - 0 - 0 - - - - - TASKS_ERASESTART - Start external flash memory erase operation - 0x00C - write-only - - TASKS_ERASESTART - 0 - 0 + REGION2RA + Write '1' to disable interrupt for event REGION2RA + 5 + 5 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - - - - TASKS_DEACTIVATE - Deactivate QSPI interface - 0x010 - write-only - - TASKS_DEACTIVATE - 0 - 0 + REGION3WA + Write '1' to disable interrupt for event REGION3WA + 6 + 6 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - - - - EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to any QSPI task. - 0x100 - read-write - - EVENTS_READY - 0 - 0 + REGION3RA + Write '1' to disable interrupt for event REGION3RA + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + - - - - INTEN - Enable or disable interrupt - 0x300 - read-write - - READY - Enable or disable interrupt for READY event - 0 - 0 + PREGION0WA + Write '1' to disable interrupt for event PREGION0WA + 24 + 24 + read Disabled - Disable + Read: Disabled 0 Enabled - Enable + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - INTENSET - Enable interrupt - 0x304 - read-write - - READY - Write '1' to enable interrupt for READY event - 0 - 0 + PREGION0RA + Write '1' to disable interrupt for event PREGION0RA + 25 + 25 read @@ -44260,25 +45038,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - - - - INTENCLR - Disable interrupt - 0x308 - read-write - - READY - Write '1' to disable interrupt for READY event - 0 - 0 + PREGION1WA + Write '1' to disable interrupt for event PREGION1WA + 26 + 26 read @@ -44301,28 +45071,29 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - ENABLE - Enable QSPI peripheral and acquire the pins selected in PSELn registers - 0x500 - read-write - - ENABLE - Enable or disable QSPI - 0 - 0 + PREGION1RA + Write '1' to disable interrupt for event PREGION1RA + 27 + 27 + read Disabled - Disable QSPI + Read: Disabled 0 Enabled - Enable QSPI + Read: Enabled + 1 + + + + write + + Clear + Disable 1 @@ -44330,386 +45101,1178 @@ POSSIBILITY OF SUCH DAMAGE.\n - READ + 2 + 0x008 + PERREGION[%s] Unspecified - QSPI_READ - 0x504 + MWU_PERREGION + read-write + 0x400 - SRC - Flash memory source address + SUBSTATWA + Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching 0x000 read-write + oneToClear - SRC - Word-aligned flash memory source address. + SR0 + Subregion 0 in region n (write '1' to clear) 0 - 31 + 0 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + - - - - DST - RAM destination address - 0x004 - read-write - - DST - Word-aligned RAM destination address. - 0 - 31 + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + - - - - CNT - Read transfer length - 0x008 - read-write - - CNT - Read transfer length in number of bytes. The length must be a multiple of 4 bytes. - 0 + SR20 + Subregion 20 in region n (write '1' to clear) + 20 20 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + - - - - - WRITE - Unspecified - QSPI_WRITE - 0x510 - - DST - Flash destination address - 0x000 - read-write - - DST - Word-aligned flash destination address. - 0 + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + + + + SR31 + Subregion 31 in region n (write '1' to clear) + 31 31 + + + NoAccess + No write access occurred in this subregion + 0 + + + Access + Write access(es) occurred in this subregion + 1 + + - SRC - RAM source address + SUBSTATRA + Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching 0x004 read-write + oneToClear - SRC - Word-aligned RAM source address. + SR0 + Subregion 0 in region n (write '1' to clear) 0 - 31 + 0 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - - - - CNT - Write transfer length - 0x008 - read-write - - CNT - Write transfer length in number of bytes. The length must be a multiple of 4 bytes. - 0 - 20 + SR1 + Subregion 1 in region n (write '1' to clear) + 1 + 1 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - - - - - ERASE - Unspecified - QSPI_ERASE - 0x51C - - PTR - Start address of flash block to be erased - 0x000 - read-write - - PTR - Word-aligned start address of block to be erased. - 0 - 31 + SR2 + Subregion 2 in region n (write '1' to clear) + 2 + 2 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR3 + Subregion 3 in region n (write '1' to clear) + 3 + 3 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR4 + Subregion 4 in region n (write '1' to clear) + 4 + 4 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR5 + Subregion 5 in region n (write '1' to clear) + 5 + 5 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR6 + Subregion 6 in region n (write '1' to clear) + 6 + 6 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR7 + Subregion 7 in region n (write '1' to clear) + 7 + 7 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR8 + Subregion 8 in region n (write '1' to clear) + 8 + 8 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR9 + Subregion 9 in region n (write '1' to clear) + 9 + 9 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + + + + SR10 + Subregion 10 in region n (write '1' to clear) + 10 + 10 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - - - - LEN - Size of block to be erased. - 0x004 - read-write - - LEN - LEN - 0 - 1 + SR11 + Subregion 11 in region n (write '1' to clear) + 11 + 11 - 4KB - Erase 4 kB block (flash command 0x20) + NoAccess + No read access occurred in this subregion 0 - 64KB - Erase 64 kB block (flash command 0xD8) + Access + Read access(es) occurred in this subregion 1 - - All - Erase all (flash command 0xC7) - 2 - - - - - - PSEL - Unspecified - QSPI_PSEL - 0x524 - - SCK - Pin select for serial clock SCK - 0x000 - read-write - 0xFFFFFFFF - - - PIN - Pin number - 0 - 4 - - - PORT - Port number - 5 - 5 - - CONNECT - Connection - 31 - 31 + SR12 + Subregion 12 in region n (write '1' to clear) + 12 + 12 - Disconnected - Disconnect - 1 + NoAccess + No read access occurred in this subregion + 0 - Connected - Connect - 0 + Access + Read access(es) occurred in this subregion + 1 - - - - CSN - Pin select for chip select signal CSN. - 0x004 - read-write - 0xFFFFFFFF - - PIN - Pin number - 0 - 4 + SR13 + Subregion 13 in region n (write '1' to clear) + 13 + 13 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - PORT - Port number - 5 - 5 + SR14 + Subregion 14 in region n (write '1' to clear) + 14 + 14 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - CONNECT - Connection - 31 - 31 + SR15 + Subregion 15 in region n (write '1' to clear) + 15 + 15 - Disconnected - Disconnect + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion 1 + + + + SR16 + Subregion 16 in region n (write '1' to clear) + 16 + 16 + - Connected - Connect + NoAccess + No read access occurred in this subregion 0 + + Access + Read access(es) occurred in this subregion + 1 + - - - - IO0 - Pin select for serial data MOSI/IO0. - 0x00C - read-write - 0xFFFFFFFF - - PIN - Pin number - 0 - 4 + SR17 + Subregion 17 in region n (write '1' to clear) + 17 + 17 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - PORT - Port number - 5 - 5 + SR18 + Subregion 18 in region n (write '1' to clear) + 18 + 18 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - CONNECT - Connection - 31 - 31 + SR19 + Subregion 19 in region n (write '1' to clear) + 19 + 19 - Disconnected - Disconnect + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion 1 + + + + SR20 + Subregion 20 in region n (write '1' to clear) + 20 + 20 + - Connected - Connect + NoAccess + No read access occurred in this subregion 0 + + Access + Read access(es) occurred in this subregion + 1 + - - - - IO1 - Pin select for serial data MISO/IO1. - 0x010 - read-write - 0xFFFFFFFF - - PIN - Pin number - 0 - 4 + SR21 + Subregion 21 in region n (write '1' to clear) + 21 + 21 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - PORT - Port number - 5 - 5 + SR22 + Subregion 22 in region n (write '1' to clear) + 22 + 22 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - CONNECT - Connection - 31 - 31 + SR23 + Subregion 23 in region n (write '1' to clear) + 23 + 23 - Disconnected - Disconnect + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion 1 + + + + SR24 + Subregion 24 in region n (write '1' to clear) + 24 + 24 + - Connected - Connect + NoAccess + No read access occurred in this subregion 0 + + Access + Read access(es) occurred in this subregion + 1 + - - - - IO2 - Pin select for serial data IO2. - 0x014 - read-write - 0xFFFFFFFF - - PIN - Pin number - 0 - 4 + SR25 + Subregion 25 in region n (write '1' to clear) + 25 + 25 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - PORT - Port number - 5 - 5 + SR26 + Subregion 26 in region n (write '1' to clear) + 26 + 26 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - CONNECT - Connection - 31 - 31 + SR27 + Subregion 27 in region n (write '1' to clear) + 27 + 27 - Disconnected - Disconnect + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion 1 + + + + SR28 + Subregion 28 in region n (write '1' to clear) + 28 + 28 + - Connected - Connect + NoAccess + No read access occurred in this subregion 0 + + Access + Read access(es) occurred in this subregion + 1 + - - - - IO3 - Pin select for serial data IO3. - 0x018 - read-write - 0xFFFFFFFF - - PIN - Pin number - 0 - 4 + SR29 + Subregion 29 in region n (write '1' to clear) + 29 + 29 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - PORT - Port number - 5 - 5 + SR30 + Subregion 30 in region n (write '1' to clear) + 30 + 30 + + + NoAccess + No read access occurred in this subregion + 0 + + + Access + Read access(es) occurred in this subregion + 1 + + - CONNECT - Connection + SR31 + Subregion 31 in region n (write '1' to clear) 31 31 - Disconnected - Disconnect - 1 + NoAccess + No read access occurred in this subregion + 0 - Connected - Connect - 0 + Access + Read access(es) occurred in this subregion + 1 @@ -44717,502 +46280,555 @@ POSSIBILITY OF SUCH DAMAGE.\n - XIPOFFSET - Address offset into the external memory for Execute in Place operation. - 0x540 + REGIONEN + Enable/disable regions watch + 0x510 read-write - XIPOFFSET - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + RGN0WA + Enable/disable write access watch in region[0] 0 - 31 + 0 + + + Disable + Disable write access watch in this region + 0 + + + Enable + Enable write access watch in this region + 1 + + + + + RGN0RA + Enable/disable read access watch in region[0] + 1 + 1 + + + Disable + Disable read access watch in this region + 0 + + + Enable + Enable read access watch in this region + 1 + + - - - - IFCONFIG0 - Interface configuration. - 0x544 - read-write - - READOC - Configure number of data lines and opcode used for reading. - 0 + RGN1WA + Enable/disable write access watch in region[1] + 2 2 - FASTREAD - Single data line SPI. FAST_READ (opcode 0x0B). + Disable + Disable write access watch in this region 0 - READ2O - Dual data line SPI. READ2O (opcode 0x3B). + Enable + Enable write access watch in this region 1 + + + + RGN1RA + Enable/disable read access watch in region[1] + 3 + 3 + - READ2IO - Dual data line SPI. READ2IO (opcode 0xBB). - 2 - - - READ4O - Quad data line SPI. READ4O (opcode 0x6B). - 3 + Disable + Disable read access watch in this region + 0 - READ4IO - Quad data line SPI. READ4IO (opcode 0xEB). - 4 + Enable + Enable read access watch in this region + 1 - WRITEOC - Configure number of data lines and opcode used for writing. - 3 - 5 + RGN2WA + Enable/disable write access watch in region[2] + 4 + 4 - PP - Single data line SPI. PP (opcode 0x02). + Disable + Disable write access watch in this region 0 - PP2O - Dual data line SPI. PP2O (opcode 0xA2). + Enable + Enable write access watch in this region 1 + + + + RGN2RA + Enable/disable read access watch in region[2] + 5 + 5 + - PP4O - Quad data line SPI. PP4O (opcode 0x32). - 2 + Disable + Disable read access watch in this region + 0 - PP4IO - Quad data line SPI. PP4IO (opcode 0x38). - 3 + Enable + Enable read access watch in this region + 1 - ADDRMODE - Addressing mode. + RGN3WA + Enable/disable write access watch in region[3] 6 6 - 24BIT - 24-bit addressing. + Disable + Disable write access watch in this region 0 - 32BIT - 32-bit addressing. + Enable + Enable write access watch in this region 1 - DPMENABLE - Enable deep power-down mode (DPM) feature. + RGN3RA + Enable/disable read access watch in region[3] 7 7 Disable - Disable DPM feature. + Disable read access watch in this region 0 Enable - Enable DPM feature. + Enable read access watch in this region 1 - PPSIZE - Page size for commands PP, PP2O, PP4O and PP4IO. - 12 - 12 + PRGN0WA + Enable/disable write access watch in PREGION[0] + 24 + 24 - 256Bytes - 256 bytes. + Disable + Disable write access watch in this PREGION 0 - 512Bytes - 512 bytes. + Enable + Enable write access watch in this PREGION 1 - - - - IFCONFIG1 - Interface configuration. - 0x600 - read-write - 0x00040480 - - - SCKDELAY - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). - 0 - 7 - - DPMEN - Enter/exit deep power-down mode (DPM) for external flash memory. - 24 - 24 + PRGN0RA + Enable/disable read access watch in PREGION[0] + 25 + 25 - Exit - Exit DPM. + Disable + Disable read access watch in this PREGION 0 - Enter - Enter DPM. + Enable + Enable read access watch in this PREGION 1 - SPIMODE - Select SPI mode. - 25 - 25 + PRGN1WA + Enable/disable write access watch in PREGION[1] + 26 + 26 - MODE0 - Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). + Disable + Disable write access watch in this PREGION 0 - MODE3 - Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). + Enable + Enable write access watch in this PREGION 1 - SCKFREQ - SCK frequency is given as 32 MHz / (SCKFREQ + 1). - 28 - 31 + PRGN1RA + Enable/disable read access watch in PREGION[1] + 27 + 27 + + + Disable + Disable read access watch in this PREGION + 0 + + + Enable + Enable read access watch in this PREGION + 1 + + - STATUS - Status register. - 0x604 - read-only + REGIONENSET + Enable regions watch + 0x514 + read-write - DPM - Deep power-down mode (DPM) status of external flash. - 2 - 2 + RGN0WA + Enable write access watch in region[0] + 0 + 0 + read Disabled - External flash is not in DPM. + Write access watch in this region is disabled 0 Enabled - External flash is in DPM. + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region 1 - READY - Ready status. - 3 - 3 + RGN0RA + Enable read access watch in region[0] + 1 + 1 + read - READY - QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + Disabled + Read access watch in this region is disabled + 0 + + + Enabled + Read access watch in this region is enabled 1 + + + write - BUSY - QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. - 0 + Set + Enable read access watch in this region + 1 - SREG - Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. - 24 - 31 - - - - - DPMDUR - Set the duration required to enter/exit deep power-down mode (DPM). - 0x614 - read-write - 0xFFFFFFFF - - - ENTER - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. - 0 - 15 - - - EXIT - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. - 16 - 31 - - - - - ADDRCONF - Extended address configuration. - 0x624 - read-write - 0x000000B7 - - - OPCODE - Opcode that enters the 32-bit addressing mode. - 0 - 7 - - - BYTE0 - Byte 0 following opcode. - 8 - 15 - - - BYTE1 - Byte 1 following byte 0. - 16 - 23 - - - MODE - Extended addressing mode. - 24 - 25 + RGN1WA + Enable write access watch in region[1] + 2 + 2 + read - NoInstr - Do not send any instruction. + Disabled + Write access watch in this region is disabled 0 - Opcode - Send opcode. + Enabled + Write access watch in this region is enabled 1 + + + write - OpByte0 - Send opcode, byte0. - 2 - - - All - Send opcode, byte0, byte1. - 3 + Set + Enable write access watch in this region + 1 - WIPWAIT - Wait for write complete before sending command. - 26 - 26 + RGN1RA + Enable read access watch in region[1] + 3 + 3 + read - Disable - No wait. + Disabled + Read access watch in this region is disabled 0 - Enable - Wait. + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Set + Enable read access watch in this region 1 - WREN - Send WREN (write enable opcode 0x06) before instruction. - 27 - 27 + RGN2WA + Enable write access watch in region[2] + 4 + 4 + read - Disable - Do not send WREN. + Disabled + Write access watch in this region is disabled 0 - Enable - Send WREN. + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Set + Enable write access watch in this region 1 - - - - - CINSTRCONF - Custom instruction configuration register. - 0x634 - read-write - 0x00002000 - - - OPCODE - Opcode of Custom instruction. - 0 - 7 - LENGTH - Length of custom instruction in number of bytes. - 8 - 11 + RGN2RA + Enable read access watch in region[2] + 5 + 5 + read - 1B - Send opcode only. - 1 + Disabled + Read access watch in this region is disabled + 0 - 2B - Send opcode, CINSTRDAT0.BYTE0. - 2 + Enabled + Read access watch in this region is enabled + 1 + + + write - 3B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. - 3 + Set + Enable read access watch in this region + 1 + + + + RGN3WA + Enable write access watch in region[3] + 6 + 6 + + read - 4B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. - 4 + Disabled + Write access watch in this region is disabled + 0 - 5B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. - 5 + Enabled + Write access watch in this region is enabled + 1 + + + write - 6B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. - 6 + Set + Enable write access watch in this region + 1 + + + + RGN3RA + Enable read access watch in region[3] + 7 + 7 + + read - 7B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. - 7 + Disabled + Read access watch in this region is disabled + 0 - 8B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. - 8 + Enabled + Read access watch in this region is enabled + 1 + + + write - 9B - Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. - 9 + Set + Enable read access watch in this region + 1 - LIO2 - Level of the IO2 pin (if connected) during transmission of custom instruction. - 12 - 12 - - - LIO3 - Level of the IO3 pin (if connected) during transmission of custom instruction. - 13 - 13 + PRGN0WA + Enable write access watch in PREGION[0] + 24 + 24 + + read + + Disabled + Write access watch in this PREGION is disabled + 0 + + + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION + 1 + + - WIPWAIT - Wait for write complete before sending command. - 14 - 14 + PRGN0RA + Enable read access watch in PREGION[0] + 25 + 25 + read - Disable - No wait. + Disabled + Read access watch in this PREGION is disabled 0 - Enable - Wait. + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable read access watch in this PREGION 1 - WREN - Send WREN (write enable opcode 0x06) before instruction. - 15 - 15 + PRGN1WA + Enable write access watch in PREGION[1] + 26 + 26 + read - Disable - Do not send WREN. + Disabled + Write access watch in this PREGION is disabled 0 - Enable - Send WREN. + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Set + Enable write access watch in this PREGION 1 - LFEN - Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. - 16 - 16 + PRGN1RA + Enable read access watch in PREGION[1] + 27 + 27 + read - Disable - Long frame mode disabled + Disabled + Read access watch in this PREGION is disabled 0 - Enable - Long frame mode enabled + Enabled + Read access watch in this PREGION is enabled 1 - - - LFSTOP - Stop (finalize) long frame transaction - 17 - 17 + write - Stop - Stop + Set + Enable read access watch in this PREGION 1 @@ -45220,1568 +46836,2725 @@ POSSIBILITY OF SUCH DAMAGE.\n - CINSTRDAT0 - Custom instruction data register 0. - 0x638 - read-write - - - BYTE0 - Data byte 0 - 0 - 7 - - - BYTE1 - Data byte 1 - 8 - 15 - - - BYTE2 - Data byte 2 - 16 - 23 - - - BYTE3 - Data byte 3 - 24 - 31 - - - - - CINSTRDAT1 - Custom instruction data register 1. - 0x63C - read-write - - - BYTE4 - Data byte 4 - 0 - 7 - - - BYTE5 - Data byte 5 - 8 - 15 - - - BYTE6 - Data byte 6 - 16 - 23 - - - BYTE7 - Data byte 7 - 24 - 31 - - - - - IFTIMING - SPI interface timing. - 0x640 - read-write - 0x00000200 - - - RXDELAY - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. - 8 - 10 - - - - - - - PWM3 - Pulse width modulation unit 3 - 0x4002D000 - - PWM3 - 45 - - - - SPIM3 - Serial Peripheral Interface Master with EasyDMA 3 - 0x4002F000 - - SPIM3 - 47 - - - - P0 - GPIO Port 1 - 0x50000000 - GPIO - - 0 - 0x1000 - registers - - GPIO - 0x20 - - - OUT - Write GPIO port - 0x504 + REGIONENCLR + Disable regions watch + 0x518 read-write - PIN0 - Pin 0 + RGN0WA + Disable write access watch in region[0] 0 0 + read - Low - Pin driver is low + Disabled + Write access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region 1 - PIN1 - Pin 1 + RGN0RA + Disable read access watch in region[0] 1 1 + read - Low - Pin driver is low + Disabled + Read access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region 1 - PIN2 - Pin 2 + RGN1WA + Disable write access watch in region[1] 2 2 + read - Low - Pin driver is low + Disabled + Write access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region 1 - PIN3 - Pin 3 + RGN1RA + Disable read access watch in region[1] 3 3 + read - Low - Pin driver is low + Disabled + Read access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region 1 - PIN4 - Pin 4 + RGN2WA + Disable write access watch in region[2] 4 4 + read - Low - Pin driver is low + Disabled + Write access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region 1 - PIN5 - Pin 5 + RGN2RA + Disable read access watch in region[2] 5 5 + read - Low - Pin driver is low + Disabled + Read access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region 1 - PIN6 - Pin 6 + RGN3WA + Disable write access watch in region[3] 6 6 + read - Low - Pin driver is low + Disabled + Write access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this region is enabled + 1 + + + + write + + Clear + Disable write access watch in this region 1 - PIN7 - Pin 7 + RGN3RA + Disable read access watch in region[3] 7 7 + read - Low - Pin driver is low + Disabled + Read access watch in this region is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this region is enabled + 1 + + + + write + + Clear + Disable read access watch in this region 1 - PIN8 - Pin 8 - 8 - 8 + PRGN0WA + Disable write access watch in PREGION[0] + 24 + 24 + read - Low - Pin driver is low + Disabled + Write access watch in this PREGION is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION 1 - PIN9 - Pin 9 - 9 - 9 + PRGN0RA + Disable read access watch in PREGION[0] + 25 + 25 + read - Low - Pin driver is low + Disabled + Read access watch in this PREGION is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION 1 - PIN10 - Pin 10 - 10 - 10 + PRGN1WA + Disable write access watch in PREGION[1] + 26 + 26 + read - Low - Pin driver is low + Disabled + Write access watch in this PREGION is disabled 0 - High - Pin driver is high + Enabled + Write access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable write access watch in this PREGION 1 - PIN11 - Pin 11 - 11 - 11 + PRGN1RA + Disable read access watch in PREGION[1] + 27 + 27 + read - Low - Pin driver is low + Disabled + Read access watch in this PREGION is disabled 0 - High - Pin driver is high + Enabled + Read access watch in this PREGION is enabled + 1 + + + + write + + Clear + Disable read access watch in this PREGION 1 + + + + 4 + 0x010 + REGION[%s] + Unspecified + MWU_REGION + read-write + 0x600 + + START + Description cluster: Start address for region n + 0x000 + read-write + 0x00000000 + + + START + Start address for region + 0 + 31 + + + + + END + Description cluster: End address of region n + 0x004 + read-write + + + END + End address of region. + 0 + 31 + + + + + + 2 + 0x010 + PREGION[%s] + Unspecified + MWU_PREGION + read-write + 0x6C0 + + START + Description cluster: Reserved for future use + 0x000 + read-only + + + START + Reserved for future use + 0 + 31 + + + + + END + Description cluster: Reserved for future use + 0x004 + read-only + + + END + Reserved for future use + 0 + 31 + + + + + SUBS + Description cluster: Subregions of region n + 0x008 + read-write + 0x00000000 + + + SR0 + Include or exclude subregion 0 in region + 0 + 0 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR1 + Include or exclude subregion 1 in region + 1 + 1 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR2 + Include or exclude subregion 2 in region + 2 + 2 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR3 + Include or exclude subregion 3 in region + 3 + 3 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR4 + Include or exclude subregion 4 in region + 4 + 4 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR5 + Include or exclude subregion 5 in region + 5 + 5 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR6 + Include or exclude subregion 6 in region + 6 + 6 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR7 + Include or exclude subregion 7 in region + 7 + 7 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR8 + Include or exclude subregion 8 in region + 8 + 8 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR9 + Include or exclude subregion 9 in region + 9 + 9 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR10 + Include or exclude subregion 10 in region + 10 + 10 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR11 + Include or exclude subregion 11 in region + 11 + 11 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR12 + Include or exclude subregion 12 in region + 12 + 12 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR13 + Include or exclude subregion 13 in region + 13 + 13 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR14 + Include or exclude subregion 14 in region + 14 + 14 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR15 + Include or exclude subregion 15 in region + 15 + 15 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR16 + Include or exclude subregion 16 in region + 16 + 16 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR17 + Include or exclude subregion 17 in region + 17 + 17 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR18 + Include or exclude subregion 18 in region + 18 + 18 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR19 + Include or exclude subregion 19 in region + 19 + 19 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR20 + Include or exclude subregion 20 in region + 20 + 20 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR21 + Include or exclude subregion 21 in region + 21 + 21 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR22 + Include or exclude subregion 22 in region + 22 + 22 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR23 + Include or exclude subregion 23 in region + 23 + 23 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR24 + Include or exclude subregion 24 in region + 24 + 24 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR25 + Include or exclude subregion 25 in region + 25 + 25 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR26 + Include or exclude subregion 26 in region + 26 + 26 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR27 + Include or exclude subregion 27 in region + 27 + 27 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR28 + Include or exclude subregion 28 in region + 28 + 28 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR29 + Include or exclude subregion 29 in region + 29 + 29 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR30 + Include or exclude subregion 30 in region + 30 + 30 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + SR31 + Include or exclude subregion 31 in region + 31 + 31 + + + Exclude + Exclude + 0 + + + Include + Include + 1 + + + + + + + + + + PWM1 + Pulse width modulation unit 1 + 0x40021000 + + PWM1 + 33 + + + + PWM2 + Pulse width modulation unit 2 + 0x40022000 + + PWM2 + 34 + + + + SPI2 + Serial Peripheral Interface 2 + 0x40023000 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIM2 + Serial Peripheral Interface Master with EasyDMA 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + SPIS2 + SPI Slave 2 + 0x40023000 + SPI2 + + SPIM2_SPIS2_SPI2 + 35 + + + + RTC2 + Real time counter 2 + 0x40024000 + + RTC2 + 36 + + + + I2S + Inter-IC Sound + 0x40025000 + + 0 + 0x1000 + registers + + + I2S + 37 + + I2S + 0x20 + + + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0x000 + write-only + - PIN12 - Pin 12 - 12 - 12 + TASKS_START + Starts continuous I2S transfer. Also starts MCK generator when this is enabled. + 0 + 0 - Low - Pin driver is low - 0 - - - High - Pin driver is high + Trigger + Trigger task 1 + + + + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0x004 + write-only + - PIN13 - Pin 13 - 13 - 13 + TASKS_STOP + Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. + 0 + 0 - Low - Pin driver is low - 0 - - - High - Pin driver is high + Trigger + Trigger task 1 + + + + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0x104 + read-write + - PIN14 - Pin 14 - 14 - 14 + EVENTS_RXPTRUPD + The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. + 0 + 0 - Low - Pin driver is low + NotGenerated + Event not generated 0 - High - Pin driver is high + Generated + Event generated 1 + + + + EVENTS_STOPPED + I2S transfer stopped. + 0x108 + read-write + - PIN15 - Pin 15 - 15 - 15 + EVENTS_STOPPED + I2S transfer stopped. + 0 + 0 - Low - Pin driver is low + NotGenerated + Event not generated 0 - High - Pin driver is high + Generated + Event generated 1 + + + + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0x114 + read-write + - PIN16 - Pin 16 - 16 - 16 + EVENTS_TXPTRUPD + The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. + 0 + 0 - Low - Pin driver is low + NotGenerated + Event not generated 0 - High - Pin driver is high + Generated + Event generated 1 + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + - PIN17 - Pin 17 - 17 - 17 + RXPTRUPD + Enable or disable interrupt for event RXPTRUPD + 1 + 1 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN18 - Pin 18 - 18 - 18 + STOPPED + Enable or disable interrupt for event STOPPED + 2 + 2 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 - PIN19 - Pin 19 - 19 - 19 + TXPTRUPD + Enable or disable interrupt for event TXPTRUPD + 5 + 5 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PIN20 - Pin 20 - 20 - 20 + RXPTRUPD + Write '1' to enable interrupt for event RXPTRUPD + 1 + 1 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled 1 - - - PIN21 - Pin 21 - 21 - 21 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high + Set + Enable 1 - PIN22 - Pin 22 - 22 - 22 + STOPPED + Write '1' to enable interrupt for event STOPPED + 2 + 2 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled 1 - - - PIN23 - Pin 23 - 23 - 23 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high + Set + Enable 1 - PIN24 - Pin 24 - 24 - 24 + TXPTRUPD + Write '1' to enable interrupt for event TXPTRUPD + 5 + 5 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled 1 - - - PIN25 - Pin 25 - 25 - 25 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PIN26 - Pin 26 - 26 - 26 + RXPTRUPD + Write '1' to disable interrupt for event RXPTRUPD + 1 + 1 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled 1 - - - PIN27 - Pin 27 - 27 - 27 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high + Clear + Disable 1 - PIN28 - Pin 28 - 28 - 28 + STOPPED + Write '1' to disable interrupt for event STOPPED + 2 + 2 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled 1 - - - PIN29 - Pin 29 - 29 - 29 + write - Low - Pin driver is low - 0 - - - High - Pin driver is high + Clear + Disable 1 - PIN30 - Pin 30 - 30 - 30 + TXPTRUPD + Write '1' to disable interrupt for event TXPTRUPD + 5 + 5 + read - Low - Pin driver is low + Disabled + Read: Disabled 0 - High - Pin driver is high + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 + + + + ENABLE + Enable I2S module. + 0x500 + read-write + 0x00000000 + - PIN31 - Pin 31 - 31 - 31 + ENABLE + Enable I2S module. + 0 + 0 - Low - Pin driver is low + Disabled + Disable 0 - High - Pin driver is high + Enabled + Enable 1 + + CONFIG + Unspecified + I2S_CONFIG + read-write + 0x504 + + MODE + I2S mode. + 0x000 + read-write + 0x00000000 + + + MODE + I2S mode. + 0 + 0 + + + Master + Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. + 0 + + + Slave + Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx + 1 + + + + + + + RXEN + Reception (RX) enable. + 0x004 + read-write + 0x00000000 + + + RXEN + Reception (RX) enable. + 0 + 0 + + + Disabled + Reception disabled and now data will be written to the RXD.PTR address. + 0 + + + Enabled + Reception enabled. + 1 + + + + + + + TXEN + Transmission (TX) enable. + 0x008 + read-write + 0x00000001 + + + TXEN + Transmission (TX) enable. + 0 + 0 + + + Disabled + Transmission disabled and now data will be read from the RXD.TXD address. + 0 + + + Enabled + Transmission enabled. + 1 + + + + + + + MCKEN + Master clock generator enable. + 0x00C + read-write + 0x00000001 + + + MCKEN + Master clock generator enable. + 0 + 0 + + + Disabled + Master clock generator disabled and PSEL.MCK not connected(available as GPIO). + 0 + + + Enabled + Master clock generator running and MCK output on PSEL.MCK. + 1 + + + + + + + MCKFREQ + Master clock generator frequency. + 0x010 + read-write + 0x20000000 + + + MCKFREQ + Master clock generator frequency. + 0 + 31 + + + 32MDIV8 + 32 MHz / 8 = 4.0 MHz + 0x20000000 + + + 32MDIV10 + 32 MHz / 10 = 3.2 MHz + 0x18000000 + + + 32MDIV11 + 32 MHz / 11 = 2.9090909 MHz + 0x16000000 + + + 32MDIV15 + 32 MHz / 15 = 2.1333333 MHz + 0x11000000 + + + 32MDIV16 + 32 MHz / 16 = 2.0 MHz + 0x10000000 + + + 32MDIV21 + 32 MHz / 21 = 1.5238095 + 0x0C000000 + + + 32MDIV23 + 32 MHz / 23 = 1.3913043 MHz + 0x0B000000 + + + 32MDIV30 + 32 MHz / 30 = 1.0666667 MHz + 0x08800000 + + + 32MDIV31 + 32 MHz / 31 = 1.0322581 MHz + 0x08400000 + + + 32MDIV32 + 32 MHz / 32 = 1.0 MHz + 0x08000000 + + + 32MDIV42 + 32 MHz / 42 = 0.7619048 MHz + 0x06000000 + + + 32MDIV63 + 32 MHz / 63 = 0.5079365 MHz + 0x04100000 + + + 32MDIV125 + 32 MHz / 125 = 0.256 MHz + 0x020C0000 + + + + + + + RATIO + MCK / LRCK ratio. + 0x014 + read-write + 0x00000006 + + + RATIO + MCK / LRCK ratio. + 0 + 3 + + + 32X + LRCK = MCK / 32 + 0 + + + 48X + LRCK = MCK / 48 + 1 + + + 64X + LRCK = MCK / 64 + 2 + + + 96X + LRCK = MCK / 96 + 3 + + + 128X + LRCK = MCK / 128 + 4 + + + 192X + LRCK = MCK / 192 + 5 + + + 256X + LRCK = MCK / 256 + 6 + + + 384X + LRCK = MCK / 384 + 7 + + + 512X + LRCK = MCK / 512 + 8 + + + + + + + SWIDTH + Sample width. + 0x018 + read-write + 0x00000001 + + + SWIDTH + Sample width. + 0 + 1 + + + 8Bit + 8 bit. + 0 + + + 16Bit + 16 bit. + 1 + + + 24Bit + 24 bit. + 2 + + + + + + + ALIGN + Alignment of sample within a frame. + 0x01C + read-write + 0x00000000 + + + ALIGN + Alignment of sample within a frame. + 0 + 0 + + + Left + Left-aligned. + 0 + + + Right + Right-aligned. + 1 + + + + + + + FORMAT + Frame format. + 0x020 + read-write + 0x00000000 + + + FORMAT + Frame format. + 0 + 0 + + + I2S + Original I2S format. + 0 + + + Aligned + Alternate (left- or right-aligned) format. + 1 + + + + + + + CHANNELS + Enable channels. + 0x024 + read-write + 0x00000000 + + + CHANNELS + Enable channels. + 0 + 1 + + + Stereo + Stereo. + 0 + + + Left + Left only. + 1 + + + Right + Right only. + 2 + + + + + + + + RXD + Unspecified + I2S_RXD + read-write + 0x538 + + PTR + Receive buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + TXD + Unspecified + I2S_TXD + read-write + 0x540 + + PTR + Transmit buffer RAM start address. + 0x000 + read-write + 0x00000000 + + + PTR + Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. + 0 + 31 + + + + + + RXTXD + Unspecified + I2S_RXTXD + read-write + 0x550 + + MAXCNT + Size of RXD and TXD buffers. + 0x000 + read-write + 0x00000000 + + + MAXCNT + Size of RXD and TXD buffers in number of 32 bit words. + 0 + 13 + + + + + + PSEL + Unspecified + I2S_PSEL + read-write + 0x560 + + MCK + Pin select for MCK signal. + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SCK + Pin select for SCK signal. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + LRCK + Pin select for LRCK signal. + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDIN + Pin select for SDIN signal. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + SDOUT + Pin select for SDOUT signal. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + + + FPU + FPU + 0x40026000 + + 0 + 0x1000 + registers + + + FPU + 38 + + FPU + 0x20 + - OUTSET - Set individual bits in GPIO port - 0x508 - read-write - oneToSet - - - PIN0 - Pin 0 - 0 - 0 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN1 - Pin 1 - 1 - 1 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN2 - Pin 2 - 2 - 2 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN3 - Pin 3 - 3 - 3 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN4 - Pin 4 - 4 - 4 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN5 - Pin 5 - 5 - 5 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN6 - Pin 6 - 6 - 6 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN7 - Pin 7 - 7 - 7 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN8 - Pin 8 - 8 - 8 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN9 - Pin 9 - 9 - 9 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - - - PIN10 - Pin 10 - 10 - 10 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 - - - + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + USBD + Universal serial bus device + 0x40027000 + + 0 + 0x1000 + registers + + + USBD + 39 + + USBD + 0x20 + + + 0x8 + 0x4 + TASKS_STARTEPIN[%s] + Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0x004 + write-only + - PIN11 - Pin 11 - 11 - 11 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_STARTEPIN + Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0x024 + write-only + - PIN12 - Pin 12 - 12 - 12 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_STARTISOIN + Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + 0x8 + 0x4 + TASKS_STARTEPOUT[%s] + Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0x028 + write-only + - PIN13 - Pin 13 - 13 - 13 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_STARTEPOUT + Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0x048 + write-only + - PIN14 - Pin 14 - 14 - 14 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_STARTISOOUT + Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0x04C + write-only + - PIN15 - Pin 15 - 15 - 15 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_EP0RCVOUT + Allows OUT data stage on control endpoint 0 + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0x050 + write-only + - PIN16 - Pin 16 - 16 - 16 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_EP0STATUS + Allows status stage on control endpoint 0 + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0x054 + write-only + - PIN17 - Pin 17 - 17 - 17 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_EP0STALL + Stalls data and status stage on control endpoint 0 + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0x058 + write-only + - PIN18 - Pin 18 - 18 - 18 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_DPDMDRIVE + Forces D+ and D- lines into the state defined in the DPDMVALUE register + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0x05C + write-only + - PIN19 - Pin 19 - 19 - 19 - - read - - Low - Read: pin driver is low - 0 - - - High - Read: pin driver is high - 1 - - + TASKS_DPDMNODRIVE + Stops forcing D+ and D- lines into any state (USB engine takes control) + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Trigger + Trigger task 1 + + + + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0x100 + read-write + - PIN20 - Pin 20 - 20 - 20 + EVENTS_USBRESET + Signals that a USB reset condition has been detected on USB lines + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0x104 + read-write + - PIN21 - Pin 21 - 21 - 21 + EVENTS_STARTED + Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + 0x8 + 0x4 + EVENTS_ENDEPIN[%s] + Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + 0x108 + read-write + - PIN22 - Pin 22 - 22 - 22 + EVENTS_ENDEPIN + The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0x128 + read-write + - PIN23 - Pin 23 - 23 - 23 + EVENTS_EP0DATADONE + An acknowledged data transfer has taken place on the control endpoint + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + 0x12C + read-write + - PIN24 - Pin 24 - 24 - 24 + EVENTS_ENDISOIN + The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + 0x8 + 0x4 + EVENTS_ENDEPOUT[%s] + Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + 0x130 + read-write + - PIN25 - Pin 25 - 25 - 25 + EVENTS_ENDEPOUT + The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + 0x150 + read-write + - PIN26 - Pin 26 - 26 - 26 + EVENTS_ENDISOOUT + The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0x154 + read-write + - PIN27 - Pin 27 - 27 - 27 + EVENTS_SOF + Signals that a SOF (start of frame) condition has been detected on USB lines + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high - 1 - - - - write - - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Generated + Event generated 1 + + + + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0x158 + read-write + - PIN28 - Pin 28 - 28 - 28 + EVENTS_USBEVENT + An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high + Generated + Event generated 1 + + + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0x15C + read-write + + + EVENTS_EP0SETUP + A valid SETUP token has been received (and acknowledged) on the control endpoint + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + NotGenerated + Event not generated + 0 + + + Generated + Event generated 1 + + + + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0x160 + read-write + - PIN29 - Pin 29 - 29 - 29 + EVENTS_EPDATA + A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register + 0 + 0 - read - Low - Read: pin driver is low + NotGenerated + Event not generated 0 - High - Read: pin driver is high + Generated + Event generated 1 + + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + + + EP0DATADONE_STARTEPIN0 + Shortcut between event EP0DATADONE and task STARTEPIN[0] + 0 + 0 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 - PIN30 - Pin 30 - 30 - 30 + EP0DATADONE_STARTEPOUT0 + Shortcut between event EP0DATADONE and task STARTEPOUT[0] + 1 + 1 - read - Low - Read: pin driver is low + Disabled + Disable shortcut 0 - High - Read: pin driver is high + Enabled + Enable shortcut 1 + + + EP0DATADONE_EP0STATUS + Shortcut between event EP0DATADONE and task EP0STATUS + 2 + 2 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 - PIN31 - Pin 31 - 31 - 31 + ENDEPOUT0_EP0STATUS + Shortcut between event ENDEPOUT[0] and task EP0STATUS + 3 + 3 - read - Low - Read: pin driver is low + Disabled + Disable shortcut 0 - High - Read: pin driver is high + Enabled + Enable shortcut 1 + + + ENDEPOUT0_EP0RCVOUT + Shortcut between event ENDEPOUT[0] and task EP0RCVOUT + 4 + 4 - write - Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Disabled + Disable shortcut + 0 + + + Enabled + Enable shortcut 1 @@ -46789,1456 +49562,1140 @@ POSSIBILITY OF SUCH DAMAGE.\n - OUTCLR - Clear individual bits in GPIO port - 0x50C + INTEN + Enable or disable interrupt + 0x300 read-write - oneToClear - PIN0 - Pin 0 + USBRESET + Enable or disable interrupt for event USBRESET 0 0 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN1 - Pin 1 + STARTED + Enable or disable interrupt for event STARTED 1 1 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN2 - Pin 2 + ENDEPIN0 + Enable or disable interrupt for event ENDEPIN[0] 2 2 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN3 - Pin 3 + ENDEPIN1 + Enable or disable interrupt for event ENDEPIN[1] 3 3 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN4 - Pin 4 + ENDEPIN2 + Enable or disable interrupt for event ENDEPIN[2] 4 4 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN5 - Pin 5 + ENDEPIN3 + Enable or disable interrupt for event ENDEPIN[3] 5 5 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN6 - Pin 6 + ENDEPIN4 + Enable or disable interrupt for event ENDEPIN[4] 6 6 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN7 - Pin 7 + ENDEPIN5 + Enable or disable interrupt for event ENDEPIN[5] 7 7 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN8 - Pin 8 + ENDEPIN6 + Enable or disable interrupt for event ENDEPIN[6] 8 8 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN9 - Pin 9 + ENDEPIN7 + Enable or disable interrupt for event ENDEPIN[7] 9 9 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN10 - Pin 10 + EP0DATADONE + Enable or disable interrupt for event EP0DATADONE 10 10 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN11 - Pin 11 + ENDISOIN + Enable or disable interrupt for event ENDISOIN 11 11 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN12 - Pin 12 + ENDEPOUT0 + Enable or disable interrupt for event ENDEPOUT[0] 12 12 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN13 - Pin 13 + ENDEPOUT1 + Enable or disable interrupt for event ENDEPOUT[1] 13 13 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN14 - Pin 14 + ENDEPOUT2 + Enable or disable interrupt for event ENDEPOUT[2] 14 14 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN15 - Pin 15 + ENDEPOUT3 + Enable or disable interrupt for event ENDEPOUT[3] 15 15 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN16 - Pin 16 + ENDEPOUT4 + Enable or disable interrupt for event ENDEPOUT[4] 16 16 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN17 - Pin 17 + ENDEPOUT5 + Enable or disable interrupt for event ENDEPOUT[5] 17 17 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN18 - Pin 18 + ENDEPOUT6 + Enable or disable interrupt for event ENDEPOUT[6] 18 18 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN19 - Pin 19 + ENDEPOUT7 + Enable or disable interrupt for event ENDEPOUT[7] 19 19 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN20 - Pin 20 + ENDISOOUT + Enable or disable interrupt for event ENDISOOUT 20 20 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN21 - Pin 21 + SOF + Enable or disable interrupt for event SOF 21 21 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN22 - Pin 22 + USBEVENT + Enable or disable interrupt for event USBEVENT 22 22 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN23 - Pin 23 + EP0SETUP + Enable or disable interrupt for event EP0SETUP 23 23 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 - PIN24 - Pin 24 + EPDATA + Enable or disable interrupt for event EPDATA 24 24 - read - Low - Read: pin driver is low + Disabled + Disable 0 - High - Read: pin driver is high - 1 - - - - write - - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PIN25 - Pin 25 - 25 - 25 + USBRESET + Write '1' to enable interrupt for event USBRESET + 0 + 0 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN26 - Pin 26 - 26 - 26 + STARTED + Write '1' to enable interrupt for event STARTED + 1 + 1 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN27 - Pin 27 - 27 - 27 + ENDEPIN0 + Write '1' to enable interrupt for event ENDEPIN[0] + 2 + 2 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN28 - Pin 28 - 28 - 28 + ENDEPIN1 + Write '1' to enable interrupt for event ENDEPIN[1] + 3 + 3 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN29 - Pin 29 - 29 - 29 + ENDEPIN2 + Write '1' to enable interrupt for event ENDEPIN[2] + 4 + 4 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN30 - Pin 30 - 30 - 30 + ENDEPIN3 + Write '1' to enable interrupt for event ENDEPIN[3] + 5 + 5 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - PIN31 - Pin 31 - 31 - 31 + ENDEPIN4 + Write '1' to enable interrupt for event ENDEPIN[4] + 6 + 6 read - Low - Read: pin driver is low + Disabled + Read: Disabled 0 - High - Read: pin driver is high + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Set + Enable 1 - - - - IN - Read GPIO port - 0x510 - read-only - - PIN0 - Pin 0 - 0 - 0 + ENDEPIN5 + Write '1' to enable interrupt for event ENDEPIN[5] + 7 + 7 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN1 - Pin 1 - 1 - 1 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN2 - Pin 2 - 2 - 2 + ENDEPIN6 + Write '1' to enable interrupt for event ENDEPIN[6] + 8 + 8 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN3 - Pin 3 - 3 - 3 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN4 - Pin 4 - 4 - 4 + ENDEPIN7 + Write '1' to enable interrupt for event ENDEPIN[7] + 9 + 9 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN5 - Pin 5 - 5 - 5 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN6 - Pin 6 - 6 - 6 + EP0DATADONE + Write '1' to enable interrupt for event EP0DATADONE + 10 + 10 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN7 - Pin 7 - 7 - 7 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN8 - Pin 8 - 8 - 8 + ENDISOIN + Write '1' to enable interrupt for event ENDISOIN + 11 + 11 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN9 - Pin 9 - 9 - 9 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN10 - Pin 10 - 10 - 10 + ENDEPOUT0 + Write '1' to enable interrupt for event ENDEPOUT[0] + 12 + 12 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN11 - Pin 11 - 11 - 11 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN12 - Pin 12 - 12 - 12 + ENDEPOUT1 + Write '1' to enable interrupt for event ENDEPOUT[1] + 13 + 13 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN13 - Pin 13 - 13 - 13 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN14 - Pin 14 + ENDEPOUT2 + Write '1' to enable interrupt for event ENDEPOUT[2] 14 14 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - PIN15 - Pin 15 + ENDEPOUT3 + Write '1' to enable interrupt for event ENDEPOUT[3] 15 15 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - PIN16 - Pin 16 + ENDEPOUT4 + Write '1' to enable interrupt for event ENDEPOUT[4] 16 16 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - PIN17 - Pin 17 + ENDEPOUT5 + Write '1' to enable interrupt for event ENDEPOUT[5] 17 17 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - PIN18 - Pin 18 + ENDEPOUT6 + Write '1' to enable interrupt for event ENDEPOUT[6] 18 18 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN19 - Pin 19 - 19 - 19 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN20 - Pin 20 - 20 - 20 + ENDEPOUT7 + Write '1' to enable interrupt for event ENDEPOUT[7] + 19 + 19 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN21 - Pin 21 - 21 - 21 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN22 - Pin 22 - 22 - 22 + ENDISOOUT + Write '1' to enable interrupt for event ENDISOOUT + 20 + 20 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN23 - Pin 23 - 23 - 23 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN24 - Pin 24 - 24 - 24 + SOF + Write '1' to enable interrupt for event SOF + 21 + 21 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN25 - Pin 25 - 25 - 25 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN26 - Pin 26 - 26 - 26 + USBEVENT + Write '1' to enable interrupt for event USBEVENT + 22 + 22 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN27 - Pin 27 - 27 - 27 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN28 - Pin 28 - 28 - 28 + EP0SETUP + Write '1' to enable interrupt for event EP0SETUP + 23 + 23 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN29 - Pin 29 - 29 - 29 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 - PIN30 - Pin 30 - 30 - 30 + EPDATA + Write '1' to enable interrupt for event EPDATA + 24 + 24 + read - Low - Pin input is low + Disabled + Read: Disabled 0 - High - Pin input is high + Enabled + Read: Enabled 1 - - - PIN31 - Pin 31 - 31 - 31 + write - Low - Pin input is low - 0 - - - High - Pin input is high + Set + Enable 1 @@ -48246,1456 +50703,1530 @@ POSSIBILITY OF SUCH DAMAGE.\n - DIR - Direction of GPIO pins - 0x514 + INTENCLR + Disable interrupt + 0x308 read-write - PIN0 - Pin 0 + USBRESET + Write '1' to disable interrupt for event USBRESET 0 0 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN1 - Pin 1 - 1 - 1 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN2 - Pin 2 - 2 - 2 + STARTED + Write '1' to disable interrupt for event STARTED + 1 + 1 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN3 - Pin 3 - 3 - 3 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN4 - Pin 4 - 4 - 4 + ENDEPIN0 + Write '1' to disable interrupt for event ENDEPIN[0] + 2 + 2 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN5 - Pin 5 - 5 - 5 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN6 - Pin 6 - 6 - 6 + ENDEPIN1 + Write '1' to disable interrupt for event ENDEPIN[1] + 3 + 3 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN7 - Pin 7 - 7 - 7 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN8 - Pin 8 - 8 - 8 + ENDEPIN2 + Write '1' to disable interrupt for event ENDEPIN[2] + 4 + 4 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN9 - Pin 9 - 9 - 9 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN10 - Pin 10 - 10 - 10 + ENDEPIN3 + Write '1' to disable interrupt for event ENDEPIN[3] + 5 + 5 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN11 - Pin 11 - 11 - 11 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN12 - Pin 12 - 12 - 12 + ENDEPIN4 + Write '1' to disable interrupt for event ENDEPIN[4] + 6 + 6 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - PIN13 - Pin 13 - 13 - 13 + ENDEPIN5 + Write '1' to disable interrupt for event ENDEPIN[5] + 7 + 7 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN14 - Pin 14 - 14 - 14 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN15 - Pin 15 - 15 - 15 + ENDEPIN6 + Write '1' to disable interrupt for event ENDEPIN[6] + 8 + 8 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN16 - Pin 16 - 16 - 16 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN17 - Pin 17 - 17 - 17 + ENDEPIN7 + Write '1' to disable interrupt for event ENDEPIN[7] + 9 + 9 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN18 - Pin 18 - 18 - 18 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN19 - Pin 19 - 19 - 19 + EP0DATADONE + Write '1' to disable interrupt for event EP0DATADONE + 10 + 10 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN20 - Pin 20 - 20 - 20 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN21 - Pin 21 - 21 - 21 + ENDISOIN + Write '1' to disable interrupt for event ENDISOIN + 11 + 11 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN22 - Pin 22 - 22 - 22 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN23 - Pin 23 - 23 - 23 + ENDEPOUT0 + Write '1' to disable interrupt for event ENDEPOUT[0] + 12 + 12 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN24 - Pin 24 - 24 - 24 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN25 - Pin 25 - 25 - 25 + ENDEPOUT1 + Write '1' to disable interrupt for event ENDEPOUT[1] + 13 + 13 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN26 - Pin 26 - 26 - 26 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN27 - Pin 27 - 27 - 27 + ENDEPOUT2 + Write '1' to disable interrupt for event ENDEPOUT[2] + 14 + 14 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN28 - Pin 28 - 28 - 28 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN29 - Pin 29 - 29 - 29 + ENDEPOUT3 + Write '1' to disable interrupt for event ENDEPOUT[3] + 15 + 15 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled 1 - - - PIN30 - Pin 30 - 30 - 30 + write - Input - Pin set as input - 0 - - - Output - Pin set as output + Clear + Disable 1 - PIN31 - Pin 31 - 31 - 31 + ENDEPOUT4 + Write '1' to disable interrupt for event ENDEPOUT[4] + 16 + 16 + read - Input - Pin set as input + Disabled + Read: Disabled 0 - Output - Pin set as output + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - - - - DIRSET - DIR set register - 0x518 - read-write - oneToSet - - PIN0 - Set as output pin 0 - 0 - 0 + ENDEPOUT5 + Write '1' to disable interrupt for event ENDEPOUT[5] + 17 + 17 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN1 - Set as output pin 1 - 1 - 1 + ENDEPOUT6 + Write '1' to disable interrupt for event ENDEPOUT[6] + 18 + 18 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN2 - Set as output pin 2 - 2 - 2 + ENDEPOUT7 + Write '1' to disable interrupt for event ENDEPOUT[7] + 19 + 19 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN3 - Set as output pin 3 - 3 - 3 + ENDISOOUT + Write '1' to disable interrupt for event ENDISOOUT + 20 + 20 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN4 - Set as output pin 4 - 4 - 4 + SOF + Write '1' to disable interrupt for event SOF + 21 + 21 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN5 - Set as output pin 5 - 5 - 5 + USBEVENT + Write '1' to disable interrupt for event USBEVENT + 22 + 22 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN6 - Set as output pin 6 - 6 - 6 + EP0SETUP + Write '1' to disable interrupt for event EP0SETUP + 23 + 23 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 - PIN7 - Set as output pin 7 - 7 - 7 + EPDATA + Write '1' to disable interrupt for event EPDATA + 24 + 24 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Clear + Disable 1 + + + + EVENTCAUSE + Details on what caused the USBEVENT event + 0x400 + read-write + oneToClear + - PIN8 - Set as output pin 8 - 8 - 8 + ISOOUTCRC + CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. + 0 + 0 - read - Input - Read: pin set as input + NotDetected + No error detected 0 - Output - Read: pin set as output + Detected + Error detected 1 + + + SUSPEND + Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. + 8 + 8 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotDetected + Suspend not detected + 0 + + + Detected + Suspend detected 1 - PIN9 - Set as output pin 9 + RESUME + Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. 9 9 - read - Input - Read: pin set as input + NotDetected + Resume not detected 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Detected + Resume detected 1 - PIN10 - Set as output pin 10 + USBWUALLOWED + USB MAC has been woken up and operational. Write '1' to clear. 10 10 - read - Input - Read: pin set as input + NotAllowed + Wake up not allowed 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Allowed + Wake up allowed 1 - PIN11 - Set as output pin 11 + READY + USB device is ready for normal operation. Write '1' to clear. 11 11 - read - Input - Read: pin set as input + NotDetected + USBEVENT was not issued due to USBD peripheral ready 0 - Output - Read: pin set as output + Ready + USBD peripheral is ready 1 + + + + + HALTED + Unspecified + USBD_HALTED + read-write + 0x420 + + 0x8 + 0x4 + EPIN[%s] + Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x000 + read-only + + + GETSTATUS + IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + 0x8 + 0x4 + EPOUT[%s] + Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0x024 + read-only + + + GETSTATUS + OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. + 0 + 15 + + + NotHalted + Endpoint is not halted + 0 + + + Halted + Endpoint is halted + 1 + + + + + + + + EPSTATUS + Provides information on which endpoint's EasyDMA registers have been captured + 0x468 + read-write + oneToClear + + + EPIN0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 0 + 0 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN12 - Set as output pin 12 - 12 - 12 + EPIN1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 1 + 1 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPIN2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 2 + 2 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN13 - Set as output pin 13 - 13 - 13 + EPIN3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 3 + 3 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPIN4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 4 + 4 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN14 - Set as output pin 14 - 14 - 14 + EPIN5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 5 + 5 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPIN6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 6 + 6 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN15 - Set as output pin 15 - 15 - 15 + EPIN7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 7 + 7 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPIN8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 8 + 8 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN16 - Set as output pin 16 + EPOUT0 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 16 16 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN17 - Set as output pin 17 + EPOUT1 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 17 17 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN18 - Set as output pin 18 + EPOUT2 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 18 18 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN19 - Set as output pin 19 + EPOUT3 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. 19 19 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPOUT4 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 20 + 20 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN20 - Set as output pin 20 - 20 - 20 + EPOUT5 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 21 + 21 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPOUT6 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 22 + 22 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 - PIN21 - Set as output pin 21 - 21 - 21 + EPOUT7 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 23 + 23 - read - Input - Read: pin set as input + NoData + EasyDMA registers have not been captured for this endpoint 0 - Output - Read: pin set as output + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + EPOUT8 + Captured state of endpoint's EasyDMA registers. Write '1' to clear. + 24 + 24 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NoData + EasyDMA registers have not been captured for this endpoint + 0 + + + DataDone + EasyDMA registers have been captured for this endpoint 1 + + + + EPDATASTATUS + Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) + 0x46C + read-write + oneToClear + - PIN22 - Set as output pin 22 - 22 - 22 + EPIN1 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 1 + 1 - read - Input - Read: pin set as input + NotDone + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + DataDone + Acknowledged data transfer on this endpoint has occurred 1 + + + EPIN2 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 2 + 2 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred 1 - PIN23 - Set as output pin 23 - 23 - 23 + EPIN3 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 3 + 3 - read - Input - Read: pin set as input + NotDone + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + DataDone + Acknowledged data transfer on this endpoint has occurred 1 + + + EPIN4 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 4 + 4 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred 1 - PIN24 - Set as output pin 24 - 24 - 24 + EPIN5 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 5 + 5 - read - Input - Read: pin set as input + NotDone + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + DataDone + Acknowledged data transfer on this endpoint has occurred 1 + + + EPIN6 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 6 + 6 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotDone + No acknowledged data transfer on this endpoint + 0 + + + DataDone + Acknowledged data transfer on this endpoint has occurred 1 - PIN25 - Set as output pin 25 - 25 - 25 + EPIN7 + Acknowledged data transfer on this IN endpoint. Write '1' to clear. + 7 + 7 - read - Input - Read: pin set as input + NotDone + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + DataDone + Acknowledged data transfer on this endpoint has occurred 1 + + + EPOUT1 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 17 + 17 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred 1 - PIN26 - Set as output pin 26 - 26 - 26 + EPOUT2 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 18 + 18 - read - Input - Read: pin set as input + NotStarted + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + Started + Acknowledged data transfer on this endpoint has occurred 1 + + + EPOUT3 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 19 + 19 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred 1 - PIN27 - Set as output pin 27 - 27 - 27 + EPOUT4 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 20 + 20 - read - Input - Read: pin set as input + NotStarted + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + Started + Acknowledged data transfer on this endpoint has occurred 1 + + + EPOUT5 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 21 + 21 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred 1 - PIN28 - Set as output pin 28 - 28 - 28 + EPOUT6 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 22 + 22 - read - Input - Read: pin set as input + NotStarted + No acknowledged data transfer on this endpoint 0 - Output - Read: pin set as output + Started + Acknowledged data transfer on this endpoint has occurred 1 + + + EPOUT7 + Acknowledged data transfer on this OUT endpoint. Write '1' to clear. + 23 + 23 - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + NotStarted + No acknowledged data transfer on this endpoint + 0 + + + Started + Acknowledged data transfer on this endpoint has occurred 1 + + + + USBADDR + Device USB address + 0x470 + read-only + - PIN29 - Set as output pin 29 - 29 - 29 + ADDR + Device USB address + 0 + 6 + + + + + BMREQUESTTYPE + SETUP data, byte 0, bmRequestType + 0x480 + read-only + 0x00000000 + + + RECIPIENT + Data transfer type + 0 + 4 - read - Input - Read: pin set as input + Device + Device 0 - Output - Read: pin set as output + Interface + Interface 1 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Endpoint + Endpoint + 2 + + + Other + Other + 3 - PIN30 - Set as output pin 30 - 30 - 30 + TYPE + Data transfer type + 5 + 6 - read - Input - Read: pin set as input + Standard + Standard 0 - Output - Read: pin set as output + Class + Class 1 - - - write - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + Vendor + Vendor + 2 - PIN31 - Set as output pin 31 - 31 - 31 + DIRECTION + Data transfer direction + 7 + 7 - read - Input - Read: pin set as input + HostToDevice + Host-to-device 0 - Output - Read: pin set as output - 1 - - - - write - - Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + DeviceToHost + Device-to-host 1 @@ -49703,810 +52234,1289 @@ POSSIBILITY OF SUCH DAMAGE.\n - DIRCLR - DIR clear register - 0x51C - read-write - oneToClear + BREQUEST + SETUP data, byte 1, bRequest + 0x484 + read-only + 0x00000000 - PIN0 - Set as input pin 0 + BREQUEST + SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. 0 - 0 + 7 - read - Input - Read: pin set as input + STD_GET_STATUS + Standard request GET_STATUS 0 - Output - Read: pin set as output + STD_CLEAR_FEATURE + Standard request CLEAR_FEATURE 1 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + STD_SET_FEATURE + Standard request SET_FEATURE + 3 - - - - PIN1 - Set as input pin 1 - 1 - 1 - - read - Input - Read: pin set as input - 0 + STD_SET_ADDRESS + Standard request SET_ADDRESS + 5 - Output - Read: pin set as output - 1 + STD_GET_DESCRIPTOR + Standard request GET_DESCRIPTOR + 6 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + STD_SET_DESCRIPTOR + Standard request SET_DESCRIPTOR + 7 + + + STD_GET_CONFIGURATION + Standard request GET_CONFIGURATION + 8 + + + STD_SET_CONFIGURATION + Standard request SET_CONFIGURATION + 9 + + + STD_GET_INTERFACE + Standard request GET_INTERFACE + 10 + + + STD_SET_INTERFACE + Standard request SET_INTERFACE + 11 + + + STD_SYNCH_FRAME + Standard request SYNCH_FRAME + 12 + + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0x488 + read-only + 0x00000000 + + + WVALUEL + SETUP data, byte 2, LSB of wValue + 0 + 7 + + + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0x48C + read-only + 0x00000000 + + + WVALUEH + SETUP data, byte 3, MSB of wValue + 0 + 7 + + + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0x490 + read-only + 0x00000000 + + + WINDEXL + SETUP data, byte 4, LSB of wIndex + 0 + 7 + + + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0x494 + read-only + 0x00000000 + + + WINDEXH + SETUP data, byte 5, MSB of wIndex + 0 + 7 + + + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0x498 + read-only + 0x00000000 + + + WLENGTHL + SETUP data, byte 6, LSB of wLength + 0 + 7 + + + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0x49C + read-only + 0x00000000 + + + WLENGTHH + SETUP data, byte 7, MSB of wLength + 0 + 7 + + + + + SIZE + Unspecified + USBD_SIZE + read-write + 0x4A0 + + 0x8 + 0x4 + EPOUT[%s] + Description collection: Number of bytes received last in the data stage of this OUT endpoint + 0x000 + read-write + + + SIZE + Number of bytes received last in the data stage of this OUT endpoint + 0 + 6 + + + + + ISOOUT + Number of bytes received last on this ISO OUT data endpoint + 0x020 + read-only + 0x00010000 + + + SIZE + Number of bytes received last on this ISO OUT data endpoint + 0 + 9 + + + ZERO + Zero-length data packet received + 16 + 16 + + + Normal + No zero-length data received, use value in SIZE + 0 + + + ZeroData + Zero-length data received, ignore value in SIZE + 1 + + + + + + + + ENABLE + Enable USB + 0x500 + read-write + - PIN2 - Set as input pin 2 - 2 - 2 + ENABLE + Enable USB + 0 + 0 - read - Input - Read: pin set as input + Disabled + USB peripheral is disabled 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enabled + USB peripheral is enabled 1 + + + + USBPULLUP + Control of the USB pull-up + 0x504 + read-write + - PIN3 - Set as input pin 3 - 3 - 3 + CONNECT + Control of the USB pull-up on the D+ line + 0 + 0 - read - Input - Read: pin set as input + Disabled + Pull-up is disconnected 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enabled + Pull-up is connected to D+ 1 + + + + DPDMVALUE + State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). + 0x508 + read-write + - PIN4 - Set as input pin 4 - 4 + STATE + State D+ and D- lines will be forced into by the DPDMDRIVE task + 0 4 - read - Input - Read: pin set as input - 0 + Resume + D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) + 1 - Output - Read: pin set as output - 1 + J + D+ forced high, D- forced low (J state) + 2 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + K + D+ forced low, D- forced high (K state) + 4 + + + + DTOGGLE + Data toggle control and status + 0x50C + read-write + 0x00000100 + - PIN5 - Set as input pin 5 - 5 - 5 + EP + Select bulk endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 - read - Input - Read: pin set as input + Out + Selects OUT endpoint 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + In + Selects IN endpoint 1 - PIN6 - Set as input pin 6 - 6 - 6 + VALUE + Data toggle value + 8 + 9 - read - Input - Read: pin set as input + Nop + No action on data toggle when writing the register with this value 0 - Output - Read: pin set as output + Data0 + Data toggle is DATA0 on endpoint set by EP and IO 1 - - - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + Data1 + Data toggle is DATA1 on endpoint set by EP and IO + 2 + + + + EPINEN + Endpoint IN enable + 0x510 + read-write + 0x00000001 + - PIN7 - Set as input pin 7 - 7 - 7 + IN0 + Enable IN endpoint 0 + 0 + 0 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 0 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 0 (response to IN tokens) 1 - PIN8 - Set as input pin 8 - 8 - 8 + IN1 + Enable IN endpoint 1 + 1 + 1 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 1 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 1 (response to IN tokens) 1 - PIN9 - Set as input pin 9 - 9 - 9 + IN2 + Enable IN endpoint 2 + 2 + 2 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 2 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 2 (response to IN tokens) 1 - PIN10 - Set as input pin 10 - 10 - 10 + IN3 + Enable IN endpoint 3 + 3 + 3 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 3 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 3 (response to IN tokens) 1 - PIN11 - Set as input pin 11 - 11 - 11 + IN4 + Enable IN endpoint 4 + 4 + 4 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 4 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 4 (response to IN tokens) 1 - PIN12 - Set as input pin 12 - 12 - 12 + IN5 + Enable IN endpoint 5 + 5 + 5 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 5 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 5 (response to IN tokens) 1 - PIN13 - Set as input pin 13 - 13 - 13 + IN6 + Enable IN endpoint 6 + 6 + 6 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 6 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 6 (response to IN tokens) 1 - PIN14 - Set as input pin 14 - 14 - 14 + IN7 + Enable IN endpoint 7 + 7 + 7 - read - Input - Read: pin set as input + Disable + Disable endpoint IN 7 (no response to IN tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint IN 7 (response to IN tokens) 1 - PIN15 - Set as input pin 15 - 15 - 15 + ISOIN + Enable ISO IN endpoint + 8 + 8 - read - Input - Read: pin set as input + Disable + Disable ISO IN endpoint 8 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable ISO IN endpoint 8 1 + + + + EPOUTEN + Endpoint OUT enable + 0x514 + read-write + 0x00000001 + - PIN16 - Set as input pin 16 - 16 - 16 + OUT0 + Enable OUT endpoint 0 + 0 + 0 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 0 (no response to OUT tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint OUT 0 (response to OUT tokens) 1 - PIN17 - Set as input pin 17 - 17 - 17 + OUT1 + Enable OUT endpoint 1 + 1 + 1 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 1 (no response to OUT tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint OUT 1 (response to OUT tokens) 1 - PIN18 - Set as input pin 18 - 18 - 18 + OUT2 + Enable OUT endpoint 2 + 2 + 2 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 2 (no response to OUT tokens) 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enable + Enable endpoint OUT 2 (response to OUT tokens) 1 - PIN19 - Set as input pin 19 - 19 - 19 + OUT3 + Enable OUT endpoint 3 + 3 + 3 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 3 (no response to OUT tokens) 0 - Output - Read: pin set as output + Enable + Enable endpoint OUT 3 (response to OUT tokens) 1 + + + OUT4 + Enable OUT endpoint 4 + 4 + 4 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Disable + Disable endpoint OUT 4 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 4 (response to OUT tokens) 1 - PIN20 - Set as input pin 20 - 20 - 20 + OUT5 + Enable OUT endpoint 5 + 5 + 5 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 5 (no response to OUT tokens) 0 - Output - Read: pin set as output + Enable + Enable endpoint OUT 5 (response to OUT tokens) 1 + + + OUT6 + Enable OUT endpoint 6 + 6 + 6 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Disable + Disable endpoint OUT 6 (no response to OUT tokens) + 0 + + + Enable + Enable endpoint OUT 6 (response to OUT tokens) 1 - PIN21 - Set as input pin 21 - 21 - 21 + OUT7 + Enable OUT endpoint 7 + 7 + 7 - read - Input - Read: pin set as input + Disable + Disable endpoint OUT 7 (no response to OUT tokens) 0 - Output - Read: pin set as output + Enable + Enable endpoint OUT 7 (response to OUT tokens) 1 + + + ISOOUT + Enable ISO OUT endpoint 8 + 8 + 8 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Disable + Disable ISO OUT endpoint 8 + 0 + + + Enable + Enable ISO OUT endpoint 8 1 + + + + EPSTALL + STALL endpoints + 0x518 + write-only + 0x00000000 + modifyExternal + - PIN22 - Set as input pin 22 - 22 - 22 + EP + Select endpoint number + 0 + 2 + + + IO + Selects IN or OUT endpoint + 7 + 7 - read - Input - Read: pin set as input + Out + Selects OUT endpoint 0 - Output - Read: pin set as output + In + Selects IN endpoint 1 + + + STALL + Stall selected endpoint + 8 + 8 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + UnStall + Don't stall selected endpoint + 0 + + + Stall + Stall selected endpoint 1 + + + + ISOSPLIT + Controls the split of ISO buffers + 0x51C + read-write + - PIN23 - Set as input pin 23 - 23 - 23 + SPLIT + Controls the split of ISO buffers + 0 + 15 - read - Input - Read: pin set as input - 0 + OneDir + Full buffer dedicated to either iso IN or OUT + 0x0000 - Output - Read: pin set as output - 1 + HalfIN + Lower half for IN, upper half for OUT + 0x0080 + + + + + FRAMECNTR + Returns the current value of the start of frame counter + 0x520 + read-only + + + FRAMECNTR + Returns the current value of the start of frame counter + 0 + 10 + + + + + LOWPOWER + Controls USBD peripheral low power mode during USB suspend + 0x52C + read-write + 0x00000000 + + + LOWPOWER + Controls USBD peripheral low-power mode during USB suspend + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + ForceNormal + Software must write this value to exit low power mode and before performing a remote wake-up + 0 + + + LowPower + Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral 1 + + + + ISOINCONFIG + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0x530 + read-write + - PIN24 - Set as input pin 24 - 24 - 24 + RESPONSE + Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent + 0 + 0 - read - Input - Read: pin set as input + NoResp + Endpoint does not respond in that case 0 - Output - Read: pin set as output + ZeroData + Endpoint responds with a zero-length data packet in that case 1 + + + + + 8 + 0x014 + EPIN[%s] + Unspecified + USBD_EPIN + read-write + 0x600 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer. Accepts any address in Data RAM. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOIN + Unspecified + USBD_ISOIN + read-write + 0x6A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer. Accepts any address in Data RAM. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + 8 + 0x014 + EPOUT[%s] + Unspecified + USBD_EPOUT + read-write + 0x700 + + PTR + Description cluster: Data pointer + 0x000 + read-write + + + PTR + Data pointer. Accepts any address in Data RAM. + 0 + 31 + + + + + MAXCNT + Description cluster: Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 6 + + + + + AMOUNT + Description cluster: Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 6 + + + + + + ISOOUT + Unspecified + USBD_ISOOUT + read-write + 0x7A0 + + PTR + Data pointer + 0x000 + read-write + + + PTR + Data pointer. Accepts any address in Data RAM. + 0 + 31 + + + + + MAXCNT + Maximum number of bytes to transfer + 0x004 + read-write + + + MAXCNT + Maximum number of bytes to transfer + 0 + 9 + + + + + AMOUNT + Number of bytes transferred in the last transaction + 0x008 + read-only + + + AMOUNT + Number of bytes transferred in the last transaction + 0 + 9 + + + + + + + + UARTE1 + UART with EasyDMA 1 + 0x40028000 + + UARTE1 + 40 + + + + QSPI + External flash interface + 0x40029000 + + 0 + 0x1000 + registers + + + QSPI + 41 + + QSPI + 0x20 + + + TASKS_ACTIVATE + Activate QSPI interface + 0x000 + write-only + + + TASKS_ACTIVATE + Activate QSPI interface + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0x004 + write-only + - PIN25 - Set as input pin 25 - 25 - 25 + TASKS_READSTART + Start transfer from external flash memory to internal RAM + 0 + 0 - read - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output + Trigger + Trigger task 1 + + + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0x008 + write-only + + + TASKS_WRITESTART + Start transfer from internal RAM to external flash memory + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Trigger + Trigger task 1 + + + + TASKS_ERASESTART + Start external flash memory erase operation + 0x00C + write-only + - PIN26 - Set as input pin 26 - 26 - 26 + TASKS_ERASESTART + Start external flash memory erase operation + 0 + 0 - read - - Input - Read: pin set as input - 0 - - Output - Read: pin set as output + Trigger + Trigger task 1 + + + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0x010 + write-only + + + TASKS_DEACTIVATE + Deactivate QSPI interface + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Trigger + Trigger task 1 + + + + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0x100 + read-write + - PIN27 - Set as input pin 27 - 27 - 27 + EVENTS_READY + QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + 0 + 0 - read - Input - Read: pin set as input + NotGenerated + Event not generated 0 - Output - Read: pin set as output + Generated + Event generated 1 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + READY + Enable or disable interrupt for event READY + 0 + 0 - write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Disabled + Disable + 0 + + + Enabled + Enable 1 + + + + INTENSET + Enable interrupt + 0x304 + read-write + - PIN28 - Set as input pin 28 - 28 - 28 + READY + Write '1' to enable interrupt for event READY + 0 + 0 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 write - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Set + Enable 1 + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - PIN29 - Set as input pin 29 - 29 - 29 + READY + Write '1' to disable interrupt for event READY + 0 + 0 read - Input - Read: pin set as input + Disabled + Read: Disabled 0 - Output - Read: pin set as output + Enabled + Read: Enabled 1 @@ -50514,826 +53524,1014 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Disable 1 + + + + ENABLE + Enable QSPI peripheral and acquire the pins selected in PSELn registers + 0x500 + read-write + - PIN30 - Set as input pin 30 - 30 - 30 + ENABLE + Enable or disable QSPI + 0 + 0 - read - Input - Read: pin set as input + Disabled + Disable QSPI 0 - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Enabled + Enable QSPI 1 + + + + READ + Unspecified + QSPI_READ + read-write + 0x504 + + SRC + Flash memory source address + 0x000 + read-write + + + SRC + Word-aligned flash memory source address. + 0 + 31 + + + + + DST + RAM destination address + 0x004 + read-write + + + DST + Word-aligned RAM destination address. + 0 + 31 + + + + + CNT + Read transfer length + 0x008 + read-write + + + CNT + Read transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + WRITE + Unspecified + QSPI_WRITE + read-write + 0x510 + + DST + Flash destination address + 0x000 + read-write + + + DST + Word-aligned flash destination address. + 0 + 31 + + + + + SRC + RAM source address + 0x004 + read-write + + + SRC + Word-aligned RAM source address. + 0 + 31 + + + + + CNT + Write transfer length + 0x008 + read-write + + + CNT + Write transfer length in number of bytes. The length must be a multiple of 4 bytes. + 0 + 17 + + + + + + ERASE + Unspecified + QSPI_ERASE + read-write + 0x51C + + PTR + Start address of flash block to be erased + 0x000 + read-write + + + PTR + Word-aligned start address of block to be erased. + 0 + 31 + + + + + LEN + Size of block to be erased. + 0x004 + read-write + + + LEN + LEN + 0 + 1 + + + 4KB + Erase 4 kB block (flash command 0x20) + 0 + + + 64KB + Erase 64 kB block (flash command 0xD8) + 1 + + + All + Erase all (flash command 0xC7) + 2 + + + + + + + + PSEL + Unspecified + QSPI_PSEL + read-write + 0x524 + + SCK + Pin select for serial clock SCK + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + CSN + Pin select for chip select signal CSN. + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO0 + Pin select for serial data MOSI/IO0. + 0x00C + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO1 + Pin select for serial data MISO/IO1. + 0x010 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO2 + Pin select for serial data IO2. + 0x014 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + IO3 + Pin select for serial data IO3. + 0x018 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + PORT + Port number + 5 + 5 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + XIPOFFSET + Address offset into the external memory for Execute in Place operation. + 0x540 + read-write + - PIN31 - Set as input pin 31 - 31 + XIPOFFSET + Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. + 0 31 - - read - - Input - Read: pin set as input - 0 - - - Output - Read: pin set as output - 1 - - - - write - - Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 - - - LATCH - Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers - 0x520 + IFCONFIG0 + Interface configuration. + 0x544 read-write - PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + READOC + Configure number of data lines and opcode used for reading. 0 - 0 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. - 1 - 1 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. - 2 2 - NotLatched - Criteria has not been met + FASTREAD + Single data line SPI. FAST_READ (opcode 0x0B). 0 - Latched - Criteria has been met + READ2O + Dual data line SPI. READ2O (opcode 0x3B). 1 - - - - PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. - 3 - 3 - - - NotLatched - Criteria has not been met - 0 - - Latched - Criteria has been met - 1 + READ2IO + Dual data line SPI. READ2IO (opcode 0xBB). + 2 - - - - PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. - 4 - 4 - - NotLatched - Criteria has not been met - 0 + READ4O + Quad data line SPI. READ4O (opcode 0x6B). + 3 - Latched - Criteria has been met - 1 + READ4IO + Quad data line SPI. READ4IO (opcode 0xEB). + 4 - PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. - 5 + WRITEOC + Configure number of data lines and opcode used for writing. + 3 5 - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. - 6 - 6 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. - 7 - 7 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. - 8 - 8 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. - 9 - 9 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. - 10 - 10 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. - 11 - 11 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. - 12 - 12 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. - 13 - 13 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. - 14 - 14 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. - 15 - 15 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. - 16 - 16 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. - 17 - 17 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. - 18 - 18 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. - 19 - 19 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. - 20 - 20 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. - 21 - 21 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. - 22 - 22 - - - NotLatched - Criteria has not been met - 0 - - - Latched - Criteria has been met - 1 - - - - - PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. - 23 - 23 - - - NotLatched - Criteria has not been met + PP + Single data line SPI. PP (opcode 0x02). 0 - Latched - Criteria has been met + PP2O + Dual data line SPI. PP2O (opcode 0xA2). 1 - - - - PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. - 24 - 24 - - NotLatched - Criteria has not been met - 0 + PP4O + Quad data line SPI. PP4O (opcode 0x32). + 2 - Latched - Criteria has been met - 1 + PP4IO + Quad data line SPI. PP4IO (opcode 0x38). + 3 - - PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. - 25 - 25 + + ADDRMODE + Addressing mode. + 6 + 6 - NotLatched - Criteria has not been met + 24BIT + 24-bit addressing. 0 - Latched - Criteria has been met + 32BIT + 32-bit addressing. 1 - PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. - 26 - 26 + DPMENABLE + Enable deep power-down mode (DPM) feature. + 7 + 7 - NotLatched - Criteria has not been met + Disable + Disable DPM feature. 0 - Latched - Criteria has been met + Enable + Enable DPM feature. 1 - PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. - 27 - 27 + PPSIZE + Page size for commands PP, PP2O, PP4O and PP4IO. + 12 + 12 - NotLatched - Criteria has not been met + 256Bytes + 256 bytes. 0 - Latched - Criteria has been met + 512Bytes + 512 bytes. 1 + + + + IFCONFIG1 + Interface configuration. + 0x600 + read-write + 0x00040480 + + + SCKDELAY + Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). + 0 + 7 + - PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. - 28 - 28 + DPMEN + Enter/exit deep power-down mode (DPM) for external flash memory. + 24 + 24 - NotLatched - Criteria has not been met + Exit + Exit DPM. 0 - Latched - Criteria has been met + Enter + Enter DPM. 1 - PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. - 29 - 29 + SPIMODE + Select SPI mode. + 25 + 25 - NotLatched - Criteria has not been met + MODE0 + Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). 0 - Latched - Criteria has been met + MODE3 + Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). 1 - PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. - 30 - 30 + SCKFREQ + SCK frequency is given as 32 MHz / (SCKFREQ + 1). + 28 + 31 + + + + + STATUS + Status register. + 0x604 + read-only + + + DPM + Deep power-down mode (DPM) status of external flash. + 2 + 2 - NotLatched - Criteria has not been met + Disabled + External flash is not in DPM. 0 - Latched - Criteria has been met + Enabled + External flash is in DPM. 1 - PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. - 31 - 31 + READY + Ready status. + 3 + 3 - NotLatched - Criteria has not been met - 0 + READY + QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. + 1 - Latched - Criteria has been met - 1 + BUSY + QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. + 0 + + SREG + Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. + 24 + 31 + - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode - 0x524 + DPMDUR + Set the duration required to enter/exit deep power-down mode (DPM). + 0x614 read-write + 0xFFFFFFFF - DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + ENTER + Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. 0 - 0 - - - Default - DETECT directly connected to PIN DETECT signals - 0 - - - LDETECT - Use the latched LDETECT behaviour - 1 - - + 15 + + + EXIT + Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. + 16 + 31 - 0x20 - 0x4 - PIN_CNF[%s] - Description collection[n]: Configuration of GPIO pins - 0x700 + ADDRCONF + Extended address configuration. + 0x624 read-write - 0x00000002 + 0x000000B7 - DIR - Pin direction. Same physical register as DIR register + OPCODE + Opcode that enters the 32-bit addressing mode. 0 - 0 + 7 + + + BYTE0 + Byte 0 following opcode. + 8 + 15 + + + BYTE1 + Byte 1 following byte 0. + 16 + 23 + + + MODE + Extended addressing mode. + 24 + 25 - Input - Configure pin as an input pin + NoInstr + Do not send any instruction. 0 - Output - Configure pin as an output pin + Opcode + Send opcode. 1 + + OpByte0 + Send opcode, byte0. + 2 + + + All + Send opcode, byte0, byte1. + 3 + - INPUT - Connect or disconnect input buffer - 1 - 1 + WIPWAIT + Wait for write complete before sending command. + 26 + 26 - Connect - Connect input buffer + Disable + No wait. 0 - Disconnect - Disconnect input buffer + Enable + Wait. 1 - PULL - Pull configuration - 2 - 3 + WREN + Send WREN (write enable opcode 0x06) before instruction. + 27 + 27 - Disabled - No pull + Disable + Do not send WREN. 0 - Pulldown - Pull down on pin + Enable + Send WREN. 1 - - Pullup - Pull up on pin - 3 - + + + + CINSTRCONF + Custom instruction configuration register. + 0x634 + read-write + 0x00002000 + + + OPCODE + Opcode of Custom instruction. + 0 + 7 + - DRIVE - Drive configuration + LENGTH + Length of custom instruction in number of bytes. 8 - 10 + 11 - S0S1 - Standard '0', standard '1' - 0 - - - H0S1 - High drive '0', standard '1' + 1B + Send opcode only. 1 - S0H1 - Standard '0', high drive '1' + 2B + Send opcode, CINSTRDAT0.BYTE0. 2 - H0H1 - High drive '0', high 'drive '1'' + 3B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. 3 - D0S1 - Disconnect '0' standard '1' (normally used for wired-or connections) + 4B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. 4 - D0H1 - Disconnect '0', high drive '1' (normally used for wired-or connections) + 5B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. 5 - S0D1 - Standard '0'. disconnect '1' (normally used for wired-and connections) + 6B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. 6 - H0D1 - High drive '0', disconnect '1' (normally used for wired-and connections) + 7B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. 7 + + 8B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. + 8 + + + 9B + Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. + 9 + - SENSE - Pin sensing mechanism + LIO2 + Level of the IO2 pin (if connected) during transmission of custom instruction. + 12 + 12 + + + LIO3 + Level of the IO3 pin (if connected) during transmission of custom instruction. + 13 + 13 + + + WIPWAIT + Wait for write complete before sending command. + 14 + 14 + + + Disable + No wait. + 0 + + + Enable + Wait. + 1 + + + + + WREN + Send WREN (write enable opcode 0x06) before instruction. + 15 + 15 + + + Disable + Do not send WREN. + 0 + + + Enable + Send WREN. + 1 + + + + + LFEN + Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. 16 - 17 + 16 - Disabled - Disabled + Disable + Long frame mode disabled 0 - High - Sense for high level - 2 + Enable + Long frame mode enabled + 1 + + + + LFSTOP + Stop (finalize) long frame transaction + 17 + 17 + - Low - Sense for low level - 3 + Stop + Stop + 1 + + CINSTRDAT0 + Custom instruction data register 0. + 0x638 + read-write + + + BYTE0 + Data byte 0 + 0 + 7 + + + BYTE1 + Data byte 1 + 8 + 15 + + + BYTE2 + Data byte 2 + 16 + 23 + + + BYTE3 + Data byte 3 + 24 + 31 + + + + + CINSTRDAT1 + Custom instruction data register 1. + 0x63C + read-write + + + BYTE4 + Data byte 4 + 0 + 7 + + + BYTE5 + Data byte 5 + 8 + 15 + + + BYTE6 + Data byte 6 + 16 + 23 + + + BYTE7 + Data byte 7 + 24 + 31 + + + + + IFTIMING + SPI interface timing. + 0x640 + read-write + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + + - - P1 - GPIO Port 2 - 0x50000300 - P0 - CC_HOST_RGF CRYPTOCELL HOST_RGF interface @@ -51558,5 +54756,23 @@ POSSIBILITY OF SUCH DAMAGE.\n + + PWM3 + Pulse width modulation unit 3 + 0x4002D000 + + PWM3 + 45 + + + + SPIM3 + Serial Peripheral Interface Master with EasyDMA 3 + 0x4002F000 + + SPIM3 + 47 + + \ No newline at end of file diff --git a/mdk/nrf52840_bitfields.h b/mdk/nrf52840_bitfields.h index 6d1990bb1..99cce73c2 100644 --- a/mdk/nrf52840_bitfields.h +++ b/mdk/nrf52840_bitfields.h @@ -41,56 +41,64 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_TASKS_START */ /* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ -/* Bit 0 : */ +/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ #define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_TASKS_STOP */ /* Description: Stop resolving addresses */ -/* Bit 0 : */ +/* Bit 0 : Stop resolving addresses */ #define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: AAR_EVENTS_END */ /* Description: Address resolution procedure complete */ -/* Bit 0 : */ +/* Bit 0 : Address resolution procedure complete */ #define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_RESOLVED */ /* Description: Address resolved */ -/* Bit 0 : */ +/* Bit 0 : Address resolved */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ #define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_EVENTS_NOTRESOLVED */ /* Description: Address not resolved */ -/* Bit 0 : */ +/* Bit 0 : Address not resolved */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ #define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ +#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for END event */ +/* Bit 0 : Write '1' to enable interrupt for event END */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -100,21 +108,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for NOTRESOLVED event */ +/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RESOLVED event */ +/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for END event */ +/* Bit 0 : Write '1' to disable interrupt for event END */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -170,21 +178,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster[n]: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ /* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: ACL_ACL_PERM */ -/* Description: Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ +/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ /* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ @@ -205,56 +213,66 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_TASKS_KSGEN */ /* Description: Start generation of key-stream. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ +#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_CRYPT */ /* Description: Start encryption/decryption. This operation will stop by itself when completed. */ -/* Bit 0 : */ +/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ #define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ +#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_STOP */ /* Description: Stop encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Stop encryption/decryption */ #define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_TASKS_RATEOVERRIDE */ /* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ -/* Bit 0 : */ +/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ +#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ /* Description: Key-stream generation complete */ -/* Bit 0 : */ +/* Bit 0 : Key-stream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ENDCRYPT */ /* Description: Encrypt/decrypt complete */ -/* Bit 0 : */ +/* Bit 0 : Encrypt/decrypt complete */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ #define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ /* Register: CCM_EVENTS_ERROR */ /* Description: Deprecated register - CCM error event */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - CCM error event */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: CCM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ +/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ @@ -263,21 +281,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for ERROR event */ +/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -287,21 +305,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for ERROR event */ +/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ENDCRYPT event */ +/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDKSGEN event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -469,133 +487,152 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_TASKS_HFCLKSTART */ /* Description: Start HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Start HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ /* Description: Stop HFXO crystal oscillator */ -/* Bit 0 : */ +/* Bit 0 : Stop HFXO crystal oscillator */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTART */ /* Description: Start LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Start LFCLK */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTOP */ /* Description: Stop LFCLK */ -/* Bit 0 : */ +/* Bit 0 : Stop LFCLK */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CAL */ /* Description: Start calibration of LFRC */ -/* Bit 0 : */ +/* Bit 0 : Start calibration of LFRC */ #define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ +#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTART */ /* Description: Start calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Start calibration timer */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ #define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ +#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_CTSTOP */ /* Description: Stop calibration timer */ -/* Bit 0 : */ +/* Bit 0 : Stop calibration timer */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ #define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ +#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFXO crystal oscillator started */ -/* Bit 0 : */ +/* Bit 0 : HFXO crystal oscillator started */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_LFCLKSTARTED */ /* Description: LFCLK started */ -/* Bit 0 : */ +/* Bit 0 : LFCLK started */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_DONE */ /* Description: Calibration of LFRC completed */ -/* Bit 0 : */ +/* Bit 0 : Calibration of LFRC completed */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTTO */ /* Description: Calibration timer timeout */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer timeout */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ #define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTARTED */ /* Description: Calibration timer has been started and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ #define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_CTSTOPPED */ /* Description: Calibration timer has been stopped and is ready to process new tasks */ -/* Bit 0 : */ +/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ #define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 11 : Write '1' to enable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ #define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ #define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CTTO event */ +/* Bit 4 : Write '1' to enable interrupt for event CTTO */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DONE event */ +/* Bit 3 : Write '1' to enable interrupt for event DONE */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -605,42 +642,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 11 : Write '1' to disable interrupt for CTSTOPPED event */ +/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ #define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CTSTARTED event */ +/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ #define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CTTO event */ +/* Bit 4 : Write '1' to disable interrupt for event CTTO */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DONE event */ +/* Bit 3 : Write '1' to disable interrupt for event DONE */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for LFCLKSTARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for HFCLKSTARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -784,80 +821,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: COMP_EVENTS_READY */ /* Description: COMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : COMP is ready and output is valid */ #define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: COMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: COMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -866,25 +914,25 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 3 : Enable or disable interrupt for CROSS event */ +/* Bit 3 : Enable or disable interrupt for event CROSS */ #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for UP event */ +/* Bit 2 : Enable or disable interrupt for event UP */ #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for DOWN event */ +/* Bit 1 : Enable or disable interrupt for event DOWN */ #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -893,28 +941,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -924,28 +972,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1068,42 +1116,48 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_TASKS_STARTECB */ /* Description: Start ECB block encrypt */ -/* Bit 0 : */ +/* Bit 0 : Start ECB block encrypt */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ #define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ +#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_TASKS_STOPECB */ /* Description: Abort a possible executing ECB operation */ -/* Bit 0 : */ +/* Bit 0 : Abort a possible executing ECB operation */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ #define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ +#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ /* Register: ECB_EVENTS_ENDECB */ /* Description: ECB block encrypt complete */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt complete */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ #define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_EVENTS_ERRORECB */ /* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ -/* Bit 0 : */ +/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ #define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ +#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to enable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1113,14 +1167,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to disable interrupt for ERRORECB event */ +/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for ENDECB event */ +/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1139,113 +1193,116 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Event Generator Unit 0 */ /* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event */ +/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ -/* Bit 0 : */ +/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ /* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task */ +/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ -/* Bit 0 : */ +/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ @@ -1254,112 +1311,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to enable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1369,112 +1426,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to disable interrupt for TRIGGERED[15] event */ +/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for TRIGGERED[14] event */ +/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for TRIGGERED[13] event */ +/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for TRIGGERED[12] event */ +/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for TRIGGERED[11] event */ +/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for TRIGGERED[10] event */ +/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for TRIGGERED[9] event */ +/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for TRIGGERED[8] event */ +/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TRIGGERED[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for TRIGGERED[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for TRIGGERED[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TRIGGERED[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TRIGGERED[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for TRIGGERED[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for TRIGGERED[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TRIGGERED[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1500,21 +1557,21 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection[n]: Device identifier */ +/* Description: Description collection: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection[n]: Encryption root, word n */ +/* Description: Description collection: Encryption root, word n */ /* Bits 31..0 : Encryption root, word n */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection[n]: Identity Root, word n */ +/* Description: Description collection: Identity Root, word n */ /* Bits 31..0 : Identity Root, word n */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ @@ -1530,7 +1587,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection[n]: Device address n */ +/* Description: Description collection: Device address n */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1596,7 +1653,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_PRODTEST */ -/* Description: Description collection[n]: Production test signature n */ +/* Description: Description collection: Production test signature n */ /* Bits 31..0 : Production test signature n */ #define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ @@ -1860,100 +1917,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: GPIO Tasks and Events */ /* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ +/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ -/* Bit 0 : */ +/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ /* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL */ +/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ -/* Bit 0 : */ +/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_EVENTS_PORT */ /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ -/* Bit 0 : */ +/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to enable interrupt for PORT event */ +/* Bit 31 : Write '1' to enable interrupt for event PORT */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -1963,63 +2027,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to disable interrupt for PORT event */ +/* Bit 31 : Write '1' to disable interrupt for event PORT */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for IN[7] event */ +/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for IN[6] event */ +/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for IN[5] event */ +/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for IN[4] event */ +/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for IN[3] event */ +/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for IN[2] event */ +/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for IN[1] event */ +/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for IN[0] event */ +/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -2027,7 +2091,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2065,56 +2129,66 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_TASKS_START */ /* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_TASKS_STOP */ -/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. */ +/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ -/* Bit 0 : */ +/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_EVENTS_RXPTRUPD */ /* Description: The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ -/* Bit 0 : */ +/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_STOPPED */ /* Description: I2S transfer stopped. */ -/* Bit 0 : */ +/* Bit 0 : I2S transfer stopped. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: I2S_EVENTS_TXPTRUPD */ /* Description: The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ -/* Bit 0 : */ +/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ /* Register: I2S_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ +/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for STOPPED event */ +/* Bit 2 : Enable or disable interrupt for event STOPPED */ #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ +/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ @@ -2123,21 +2197,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ -/* Bit 5 : Write '1' to enable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2147,21 +2221,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 5 : Write '1' to disable interrupt for TXPTRUPD event */ +/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for RXPTRUPD event */ +/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2232,11 +2306,6 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ /* Register: I2S_CONFIG_RATIO */ /* Description: MCK / LRCK ratio. */ @@ -2405,80 +2474,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_TASKS_START */ /* Description: Start comparator */ -/* Bit 0 : */ +/* Bit 0 : Start comparator */ #define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_STOP */ /* Description: Stop comparator */ -/* Bit 0 : */ +/* Bit 0 : Stop comparator */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_TASKS_SAMPLE */ /* Description: Sample comparator value */ -/* Bit 0 : */ +/* Bit 0 : Sample comparator value */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: LPCOMP_EVENTS_READY */ /* Description: LPCOMP is ready and output is valid */ -/* Bit 0 : */ +/* Bit 0 : LPCOMP is ready and output is valid */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_DOWN */ /* Description: Downward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward crossing */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ #define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_UP */ /* Description: Upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Upward crossing */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ #define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_EVENTS_CROSS */ /* Description: Downward or upward crossing */ -/* Bit 0 : */ +/* Bit 0 : Downward or upward crossing */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ #define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ +#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ /* Register: LPCOMP_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between CROSS event and STOP task */ +/* Bit 4 : Shortcut between event CROSS and task STOP */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between UP event and STOP task */ +/* Bit 3 : Shortcut between event UP and task STOP */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DOWN event and STOP task */ +/* Bit 2 : Shortcut between event DOWN and task STOP */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between READY event and STOP task */ +/* Bit 1 : Shortcut between event READY and task STOP */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and SAMPLE task */ +/* Bit 0 : Shortcut between event READY and task SAMPLE */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -2487,28 +2567,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for CROSS event */ +/* Bit 3 : Write '1' to enable interrupt for event CROSS */ #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for UP event */ +/* Bit 2 : Write '1' to enable interrupt for event UP */ #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for DOWN event */ +/* Bit 1 : Write '1' to enable interrupt for event DOWN */ #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2518,28 +2598,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for CROSS event */ +/* Bit 3 : Write '1' to disable interrupt for event CROSS */ #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for UP event */ +/* Bit 2 : Write '1' to disable interrupt for event UP */ #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for DOWN event */ +/* Bit 1 : Write '1' to disable interrupt for event DOWN */ #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2635,103 +2715,111 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Memory Watch Unit */ /* Register: MWU_EVENTS_REGION_WA */ -/* Description: Description cluster[n]: Write access to region n detected */ +/* Description: Description cluster: Write access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to region n detected */ #define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_REGION_RA */ -/* Description: Description cluster[n]: Read access to region n detected */ +/* Description: Description cluster: Read access to region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to region n detected */ #define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_WA */ -/* Description: Description cluster[n]: Write access to peripheral region n detected */ +/* Description: Description cluster: Write access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Write access to peripheral region n detected */ #define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ #define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ +#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */ /* Register: MWU_EVENTS_PREGION_RA */ -/* Description: Description cluster[n]: Read access to peripheral region n detected */ +/* Description: Description cluster: Read access to peripheral region n detected */ -/* Bit 0 : */ +/* Bit 0 : Read access to peripheral region n detected */ #define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ #define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ +#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ +#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */ /* Register: MWU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ @@ -2740,84 +2828,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2827,84 +2915,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2912,161 +3000,161 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_NMIEN */ -/* Description: Enable or disable non-maskable interrupt */ +/* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Enable or disable interrupt for event REGION3RA */ #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Enable or disable interrupt for event REGION3WA */ #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Enable or disable interrupt for event REGION2RA */ #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Enable or disable interrupt for event REGION2WA */ #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Enable or disable interrupt for event REGION1RA */ #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Enable or disable interrupt for event REGION1WA */ #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Enable or disable interrupt for event REGION0RA */ #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Enable or disable interrupt for event REGION0WA */ #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ /* Register: MWU_NMIENSET */ -/* Description: Enable non-maskable interrupt */ +/* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3074,86 +3162,86 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ /* Register: MWU_NMIENCLR */ -/* Description: Disable non-maskable interrupt */ +/* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable non-maskable interrupt for PREGION[1].RA event */ +/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable non-maskable interrupt for PREGION[1].WA event */ +/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable non-maskable interrupt for PREGION[0].RA event */ +/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable non-maskable interrupt for PREGION[0].WA event */ +/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable non-maskable interrupt for REGION[3].RA event */ +/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable non-maskable interrupt for REGION[3].WA event */ +/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable non-maskable interrupt for REGION[2].RA event */ +/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable non-maskable interrupt for REGION[2].WA event */ +/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable non-maskable interrupt for REGION[1].RA event */ +/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable non-maskable interrupt for REGION[1].WA event */ +/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable non-maskable interrupt for REGION[0].RA event */ +/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable non-maskable interrupt for REGION[0].WA event */ +/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3161,7 +3249,7 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3356,7 +3444,7 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ /* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ /* Bit 31 : Subregion 31 in region n (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -3800,35 +3888,35 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ /* Register: MWU_REGION_START */ -/* Description: Description cluster[n]: Start address for region n */ +/* Description: Description cluster: Start address for region n */ /* Bits 31..0 : Start address for region */ #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_REGION_END */ -/* Description: Description cluster[n]: End address of region n */ +/* Description: Description cluster: End address of region n */ /* Bits 31..0 : End address of region. */ #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_START */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_PREGION_END */ -/* Description: Description cluster[n]: Reserved for future use */ +/* Description: Description cluster: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster[n]: Subregions of region n */ +/* Description: Description cluster: Subregions of region n */ /* Bit 31 : Include or exclude subregion 31 in region */ #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -4029,173 +4117,210 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_TASKS_ACTIVATE */ /* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ -/* Bit 0 : */ +/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_DISABLE */ /* Description: Disable NFCT peripheral */ -/* Bit 0 : */ +/* Bit 0 : Disable NFCT peripheral */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_SENSE */ /* Description: Enable NFC sense field mode, change state to sense mode */ -/* Bit 0 : */ +/* Bit 0 : Enable NFC sense field mode, change state to sense mode */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ #define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ +#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_STARTTX */ /* Description: Start transmission of an outgoing frame, change state to transmit */ -/* Bit 0 : */ +/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_ENABLERXDATA */ /* Description: Initializes the EasyDMA for receive. */ -/* Bit 0 : */ +/* Bit 0 : Initializes the EasyDMA for receive. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ #define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ +#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOIDLE */ /* Description: Force state machine to IDLE state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to IDLE state */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ #define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ +#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_TASKS_GOSLEEP */ /* Description: Force state machine to SLEEP_A state */ -/* Bit 0 : */ +/* Bit 0 : Force state machine to SLEEP_A state */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ #define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ +#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */ /* Register: NFCT_EVENTS_READY */ /* Description: The NFCT peripheral is ready to receive and send frames */ -/* Bit 0 : */ +/* Bit 0 : The NFCT peripheral is ready to receive and send frames */ #define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDDETECTED */ /* Description: Remote NFC field detected */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field detected */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ #define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_FIELDLOST */ /* Description: Remote NFC field lost */ -/* Bit 0 : */ +/* Bit 0 : Remote NFC field lost */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ #define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMESTART */ /* Description: Marks the start of the first symbol of a transmitted frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the start of the first symbol of a transmitted frame */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ #define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_TXFRAMEEND */ /* Description: Marks the end of the last transmitted on-air symbol of a frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ #define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMESTART */ /* Description: Marks the end of the first symbol of a received frame */ -/* Bit 0 : */ +/* Bit 0 : Marks the end of the first symbol of a received frame */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ #define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXFRAMEEND */ /* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ #define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ERROR */ /* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_RXERROR */ /* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ -/* Bit 0 : */ +/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ #define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDRX */ /* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ -/* Bit 0 : */ +/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_ENDTX */ /* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ -/* Bit 0 : */ +/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ /* Description: Auto collision resolution process has started */ -/* Bit 0 : */ +/* Bit 0 : Auto collision resolution process has started */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ #define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_COLLISION */ /* Description: NFC auto collision resolution error reported. */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution error reported. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ #define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_SELECTED */ /* Description: NFC auto collision resolution successfully completed */ -/* Bit 0 : */ +/* Bit 0 : NFC auto collision resolution successfully completed */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ #define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_EVENTS_STARTED */ /* Description: EasyDMA is ready to receive or send frames. */ -/* Bit 0 : */ +/* Bit 0 : EasyDMA is ready to receive or send frames. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: NFCT_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ +/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ +/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */ #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ +/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ @@ -4204,91 +4329,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 20 : Enable or disable interrupt for STARTED event */ +/* Bit 20 : Enable or disable interrupt for event STARTED */ #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for SELECTED event */ +/* Bit 19 : Enable or disable interrupt for event SELECTED */ #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for COLLISION event */ +/* Bit 18 : Enable or disable interrupt for event COLLISION */ #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDTX event */ +/* Bit 12 : Enable or disable interrupt for event ENDTX */ #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDRX event */ +/* Bit 11 : Enable or disable interrupt for event ENDRX */ #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for RXERROR event */ +/* Bit 10 : Enable or disable interrupt for event RXERROR */ #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ERROR event */ +/* Bit 7 : Enable or disable interrupt for event ERROR */ #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ +/* Bit 2 : Enable or disable interrupt for event FIELDLOST */ #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -4297,105 +4422,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 20 : Write '1' to enable interrupt for STARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event STARTED */ #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to enable interrupt for event SELECTED */ #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to enable interrupt for event COLLISION */ #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDTX */ #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDRX */ #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to enable interrupt for event RXERROR */ #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ERROR event */ +/* Bit 7 : Write '1' to enable interrupt for event ERROR */ #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4405,105 +4530,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 20 : Write '1' to disable interrupt for STARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event STARTED */ #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for SELECTED event */ +/* Bit 19 : Write '1' to disable interrupt for event SELECTED */ #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COLLISION event */ +/* Bit 18 : Write '1' to disable interrupt for event COLLISION */ #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for AUTOCOLRESSTARTED event */ +/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDTX */ #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDRX */ #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for RXERROR event */ +/* Bit 10 : Write '1' to disable interrupt for event RXERROR */ #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ERROR event */ +/* Bit 7 : Write '1' to disable interrupt for event ERROR */ #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for RXFRAMEEND event */ +/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for RXFRAMESTART event */ +/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for TXFRAMEEND event */ +/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for TXFRAMESTART event */ +/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for FIELDLOST event */ +/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for FIELDDETECTED event */ +/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -6615,7 +6740,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection[n]: Configuration of GPIO pins */ +/* Description: Description collection: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -6662,54 +6787,62 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_TASKS_START */ /* Description: Starts continuous PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Starts continuous PDM transfer */ #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_TASKS_STOP */ /* Description: Stops PDM transfer */ -/* Bit 0 : */ +/* Bit 0 : Stops PDM transfer */ #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PDM_EVENTS_STARTED */ /* Description: PDM transfer has started */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has started */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_STOPPED */ /* Description: PDM transfer has finished */ -/* Bit 0 : */ +/* Bit 0 : PDM transfer has finished */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PDM_EVENTS_END */ /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ -/* Bit 0 : */ +/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 2 : Enable or disable interrupt for END event */ +/* Bit 2 : Enable or disable interrupt for event END */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -6718,21 +6851,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for END event */ +/* Bit 2 : Write '1' to enable interrupt for event END */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6742,21 +6875,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for END event */ +/* Bit 2 : Write '1' to disable interrupt for event END */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6884,98 +7017,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_TASKS_CONSTLAT */ /* Description: Enable constant latency mode */ -/* Bit 0 : */ +/* Bit 0 : Enable constant latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ /* Description: Enable low power mode (variable latency) */ -/* Bit 0 : */ +/* Bit 0 : Enable low power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_EVENTS_POFWARN */ /* Description: Power failure warning */ -/* Bit 0 : */ +/* Bit 0 : Power failure warning */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPENTER */ /* Description: CPU entered WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU entered WFI/WFE sleep */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPEXIT */ /* Description: CPU exited WFI/WFE sleep */ -/* Bit 0 : */ +/* Bit 0 : CPU exited WFI/WFE sleep */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBDETECTED */ /* Description: Voltage supply detected on VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply detected on VBUS */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ #define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBREMOVED */ /* Description: Voltage supply removed from VBUS */ -/* Bit 0 : */ +/* Bit 0 : Voltage supply removed from VBUS */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ #define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ /* Register: POWER_EVENTS_USBPWRRDY */ /* Description: USB 3.3 V supply ready */ -/* Bit 0 : */ +/* Bit 0 : USB 3.3 V supply ready */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ #define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ +#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to enable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -6985,42 +7132,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to disable interrupt for USBPWRRDY event */ +/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for USBREMOVED event */ +/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for USBDETECTED event */ +/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for SLEEPEXIT event */ +/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SLEEPENTER event */ +/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for POFWARN event */ +/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -7221,7 +7368,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster[n]: RAMn power control register */ +/* Description: Description cluster: RAMn power control register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7416,7 +7563,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster[n]: RAMn power control set register */ +/* Description: Description cluster: RAMn power control set register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7579,7 +7726,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster[n]: RAMn power control clear register */ +/* Description: Description cluster: RAMn power control clear register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7746,18 +7893,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Programmable Peripheral Interconnect */ /* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster[n]: Enable channel group n */ +/* Description: Description cluster: Enable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Enable channel group n */ #define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ +#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster[n]: Disable channel group n */ +/* Description: Description cluster: Disable channel group n */ -/* Bit 0 : */ +/* Bit 0 : Disable channel group n */ #define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ #define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ +#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ /* Register: PPI_CHEN */ /* Description: Channel enable register */ @@ -8409,21 +8558,21 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster[n]: Channel n event end-point */ +/* Description: Description cluster: Channel n event end-point */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection[n]: Channel group n */ +/* Description: Description collection: Channel group n */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -8618,7 +8767,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster[n]: Channel n task end-point */ +/* Description: Description cluster: Channel n task end-point */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8631,87 +8780,100 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_TASKS_STOP */ /* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ -/* Bit 0 : */ +/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ +/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_TASKS_NEXTSTEP */ /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ -/* Bit 0 : */ +/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ /* Register: PWM_EVENTS_STOPPED */ /* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ -/* Bit 0 : */ +/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection[n]: First PWM period started on sequence n */ +/* Description: Description collection: First PWM period started on sequence n */ -/* Bit 0 : */ +/* Bit 0 : First PWM period started on sequence n */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ +/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ -/* Bit 0 : */ +/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_PWMPERIODEND */ /* Description: Emitted at the end of each PWM period */ -/* Bit 0 : */ +/* Bit 0 : Emitted at the end of each PWM period */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ /* Register: PWM_EVENTS_LOOPSDONE */ /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ -/* Bit 0 : */ +/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ /* Register: PWM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ +/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ +/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ +/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ +/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ +/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -8720,43 +8882,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ +/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ +/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ +/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -8765,49 +8927,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to enable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8817,49 +8979,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to disable interrupt for LOOPSDONE event */ +/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for PWMPERIODEND event */ +/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for SEQEND[1] event */ +/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for SEQEND[0] event */ +/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for SEQSTARTED[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for SEQSTARTED[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8932,14 +9094,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[n]: Beginning address in RAM of this sequence */ +/* Description: Description cluster: Beginning address in RAM of this sequence */ /* Bits 31..0 : Beginning address in RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[n]: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster: Number of values (duty cycles) in this sequence */ /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8947,7 +9109,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[n]: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ @@ -8955,14 +9117,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster[n]: Time added after the sequence */ +/* Description: Description cluster: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection[n]: Output pin select for PWM channel n */ +/* Description: Description collection: Output pin select for PWM channel n */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -8985,113 +9147,128 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_TASKS_START */ /* Description: Task starting the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task starting the quadrature decoder */ #define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_STOP */ /* Description: Task stopping the quadrature decoder */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the quadrature decoder */ #define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_READCLRACC */ /* Description: Read and clear ACC and ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC and ACCDBL */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ #define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRACC */ /* Description: Read and clear ACC */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACC */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ #define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_TASKS_RDCLRDBL */ /* Description: Read and clear ACCDBL */ -/* Bit 0 : */ +/* Bit 0 : Read and clear ACCDBL */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ #define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ /* Register: QDEC_EVENTS_SAMPLERDY */ /* Description: Event being generated for every new sample value written to the SAMPLE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ #define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_REPORTRDY */ /* Description: Non-null report ready */ -/* Bit 0 : */ +/* Bit 0 : Non-null report ready */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ #define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_ACCOF */ /* Description: ACC or ACCDBL register overflow */ -/* Bit 0 : */ +/* Bit 0 : ACC or ACCDBL register overflow */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ #define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_DBLRDY */ /* Description: Double displacement(s) detected */ -/* Bit 0 : */ +/* Bit 0 : Double displacement(s) detected */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ #define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ /* Register: QDEC_EVENTS_STOPPED */ /* Description: QDEC has been stopped */ -/* Bit 0 : */ +/* Bit 0 : QDEC has been stopped */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: QDEC_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between DBLRDY event and STOP task */ +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ @@ -9100,35 +9277,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9138,35 +9315,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for DBLRDY event */ +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ACCOF event */ +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for REPORTRDY event */ +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for SAMPLERDY event */ +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9334,49 +9511,56 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_TASKS_ACTIVATE */ /* Description: Activate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Activate QSPI interface */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ #define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ +#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_READSTART */ /* Description: Start transfer from external flash memory to internal RAM */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from external flash memory to internal RAM */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ #define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ +#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_WRITESTART */ /* Description: Start transfer from internal RAM to external flash memory */ -/* Bit 0 : */ +/* Bit 0 : Start transfer from internal RAM to external flash memory */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ #define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ +#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_ERASESTART */ /* Description: Start external flash memory erase operation */ -/* Bit 0 : */ +/* Bit 0 : Start external flash memory erase operation */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ #define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ +#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_TASKS_DEACTIVATE */ /* Description: Deactivate QSPI interface */ -/* Bit 0 : */ +/* Bit 0 : Deactivate QSPI interface */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ #define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ +#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */ /* Register: QSPI_EVENTS_READY */ /* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ -/* Bit 0 : */ +/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: QSPI_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 0 : Enable or disable interrupt for READY event */ +/* Bit 0 : Enable or disable interrupt for event READY */ #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -9385,7 +9569,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9395,7 +9579,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9428,9 +9612,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_READ_CNT */ /* Description: Read transfer length */ -/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_WRITE_DST */ /* Description: Flash destination address */ @@ -9449,9 +9633,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_WRITE_CNT */ /* Description: Write transfer length */ -/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_ERASE_PTR */ /* Description: Start address of flash block to be erased */ @@ -9808,360 +9992,417 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TASKS_TXEN */ /* Description: Enable RADIO in TX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in TX mode */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ #define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ +#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RXEN */ /* Description: Enable RADIO in RX mode */ -/* Bit 0 : */ +/* Bit 0 : Enable RADIO in RX mode */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ #define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ +#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_START */ /* Description: Start RADIO */ -/* Bit 0 : */ +/* Bit 0 : Start RADIO */ #define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_STOP */ /* Description: Stop RADIO */ -/* Bit 0 : */ +/* Bit 0 : Stop RADIO */ #define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_DISABLE */ /* Description: Disable RADIO */ -/* Bit 0 : */ +/* Bit 0 : Disable RADIO */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ #define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ +#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTART */ /* Description: Start the RSSI and take one single sample of the receive signal strength */ -/* Bit 0 : */ +/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ #define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ +#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_RSSISTOP */ /* Description: Stop the RSSI measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the RSSI measurement */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ #define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ +#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTART */ /* Description: Start the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Start the bit counter */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ #define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ +#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_BCSTOP */ /* Description: Stop the bit counter */ -/* Bit 0 : */ +/* Bit 0 : Stop the bit counter */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ #define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ +#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTART */ /* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ #define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ +#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_EDSTOP */ /* Description: Stop the energy detect measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop the energy detect measurement */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ #define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ +#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTART */ /* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ -/* Bit 0 : */ +/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ #define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ +#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_TASKS_CCASTOP */ /* Description: Stop the clear channel assessment */ -/* Bit 0 : */ +/* Bit 0 : Stop the clear channel assessment */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ #define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ +#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ /* Register: RADIO_EVENTS_READY */ /* Description: RADIO has ramped up and is ready to be started */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started */ #define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_ADDRESS */ /* Description: Address sent or received */ -/* Bit 0 : */ +/* Bit 0 : Address sent or received */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ #define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PAYLOAD */ /* Description: Packet payload sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet payload sent or received */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ #define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_END */ /* Description: Packet sent or received */ -/* Bit 0 : */ +/* Bit 0 : Packet sent or received */ #define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DISABLED */ /* Description: RADIO has been disabled */ -/* Bit 0 : */ +/* Bit 0 : RADIO has been disabled */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ #define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMATCH */ /* Description: A device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : A device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ #define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_DEVMISS */ /* Description: No device address match occurred on the last received packet */ -/* Bit 0 : */ +/* Bit 0 : No device address match occurred on the last received packet */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ #define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RSSIEND */ /* Description: Sampling of receive signal strength complete */ -/* Bit 0 : */ +/* Bit 0 : Sampling of receive signal strength complete */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ #define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_BCMATCH */ /* Description: Bit counter reached bit count value */ -/* Bit 0 : */ +/* Bit 0 : Bit counter reached bit count value */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ #define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCOK */ /* Description: Packet received with CRC ok */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC ok */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ #define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CRCERROR */ /* Description: Packet received with CRC error */ -/* Bit 0 : */ +/* Bit 0 : Packet received with CRC error */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ #define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_FRAMESTART */ /* Description: IEEE 802.15.4 length field received */ -/* Bit 0 : */ +/* Bit 0 : IEEE 802.15.4 length field received */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ /* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDSTOPPED */ /* Description: The sampling of energy detection has stopped */ -/* Bit 0 : */ +/* Bit 0 : The sampling of energy detection has stopped */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ #define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCAIDLE */ /* Description: Wireless medium in idle - clear to send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium in idle - clear to send */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ #define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCABUSY */ /* Description: Wireless medium busy - do not send */ -/* Bit 0 : */ +/* Bit 0 : Wireless medium busy - do not send */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ #define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_CCASTOPPED */ /* Description: The CCA has stopped */ -/* Bit 0 : */ +/* Bit 0 : The CCA has stopped */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ #define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RATEBOOST */ /* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ -/* Bit 0 : */ +/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ #define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_TXREADY */ /* Description: RADIO has ramped up and is ready to be started TX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ #define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_RXREADY */ /* Description: RADIO has ramped up and is ready to be started RX path */ -/* Bit 0 : */ +/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_MHRMATCH */ /* Description: MAC header match found */ -/* Bit 0 : */ +/* Bit 0 : MAC header match found */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. */ +/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ -/* Bit 0 : */ +/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ /* Register: RADIO_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 21 : Shortcut between PHYEND event and START task */ +/* Bit 21 : Shortcut between event PHYEND and task START */ #define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ #define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 20 : Shortcut between PHYEND event and DISABLE task */ +/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ #define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ #define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 19 : Shortcut between RXREADY event and START task */ +/* Bit 19 : Shortcut between event RXREADY and task START */ #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 18 : Shortcut between TXREADY event and START task */ +/* Bit 18 : Shortcut between event TXREADY and task START */ #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ +/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 16 : Shortcut between EDEND event and DISABLE task */ +/* Bit 16 : Shortcut between event EDEND and task DISABLE */ #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 15 : Shortcut between READY event and EDSTART task */ +/* Bit 15 : Shortcut between event READY and task EDSTART */ #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ +/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ +/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ +/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ +/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ +/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ +/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between END event and START task */ +/* Bit 5 : Shortcut between event END and task START */ #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ +/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between DISABLED event and RXEN task */ +/* Bit 3 : Shortcut between event DISABLED and task RXEN */ #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between DISABLED event and TXEN task */ +/* Bit 2 : Shortcut between event DISABLED and task TXEN */ #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between END event and DISABLE task */ +/* Bit 1 : Shortcut between event END and task DISABLE */ #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between READY event and START task */ +/* Bit 0 : Shortcut between event READY and task START */ #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ @@ -10170,154 +10411,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ #define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for EDEND event */ +/* Bit 15 : Write '1' to enable interrupt for event EDEND */ #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for END event */ +/* Bit 3 : Write '1' to enable interrupt for event END */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for READY event */ +/* Bit 0 : Write '1' to enable interrupt for event READY */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10327,154 +10568,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for PHYEND event */ +/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ #define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for MHRMATCH event */ +/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for RXREADY event */ +/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for TXREADY event */ +/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for RATEBOOST event */ +/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CCASTOPPED event */ +/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CCABUSY event */ +/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CCAIDLE event */ +/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for EDSTOPPED event */ +/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for EDEND event */ +/* Bit 15 : Write '1' to disable interrupt for event EDEND */ #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for FRAMESTART event */ +/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CRCERROR event */ +/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CRCOK event */ +/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for BCMATCH event */ +/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for RSSIEND event */ +/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for DEVMISS event */ +/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for DEVMATCH event */ +/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for DISABLED event */ +/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for END event */ +/* Bit 3 : Write '1' to disable interrupt for event END */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for PAYLOAD event */ +/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for ADDRESS event */ +/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for READY event */ +/* Bit 0 : Write '1' to disable interrupt for event READY */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10561,12 +10802,12 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -10839,14 +11080,14 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection[n]: Device address base segment n */ +/* Description: Description collection: Device address base segment n */ /* Bits 31..0 : Device address base segment n */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection[n]: Device address prefix n */ +/* Description: Description collection: Device address prefix n */ /* Bits 15..0 : Device address prefix n */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ @@ -10935,6 +11176,20 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ +/* Register: RADIO_MHRMATCHCONF */ +/* Description: Search pattern configuration */ + +/* Bits 31..0 : Search pattern configuration */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ +#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ + +/* Register: RADIO_MHRMATCHMAS */ +/* Description: Pattern mask */ + +/* Bits 31..0 : Pattern mask */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ +#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ + /* Register: RADIO_MODECNF0 */ /* Description: Radio mode configuration register 0 */ @@ -10948,8 +11203,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Radio ramp-up time */ #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ -#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -11012,28 +11267,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_TASKS_START */ /* Description: Task starting the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task starting the random number generator */ #define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_TASKS_STOP */ /* Description: Task stopping the random number generator */ -/* Bit 0 : */ +/* Bit 0 : Task stopping the random number generator */ #define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RNG_EVENTS_VALRDY */ /* Description: Event being generated for every new random number written to the VALUE register */ -/* Bit 0 : */ +/* Bit 0 : Event being generated for every new random number written to the VALUE register */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ #define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ +#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ /* Register: RNG_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 0 : Shortcut between VALRDY event and STOP task */ +/* Bit 0 : Shortcut between event VALRDY and task STOP */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -11042,7 +11301,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11052,7 +11311,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for VALRDY event */ +/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11082,91 +11341,101 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_TASKS_START */ /* Description: Start RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Start RTC COUNTER */ #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_STOP */ /* Description: Stop RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Stop RTC COUNTER */ #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_CLEAR */ /* Description: Clear RTC COUNTER */ -/* Bit 0 : */ +/* Bit 0 : Clear RTC COUNTER */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_TASKS_TRIGOVRFLW */ /* Description: Set COUNTER to 0xFFFFF0 */ -/* Bit 0 : */ +/* Bit 0 : Set COUNTER to 0xFFFFF0 */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ /* Register: RTC_EVENTS_TICK */ /* Description: Event on COUNTER increment */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER increment */ #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_OVRFLW */ /* Description: Event on COUNTER overflow */ -/* Bit 0 : */ +/* Bit 0 : Event on COUNTER overflow */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ /* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for TICK event */ +/* Bit 0 : Write '1' to enable interrupt for event TICK */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11176,42 +11445,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for OVRFLW event */ +/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for TICK event */ +/* Bit 0 : Write '1' to disable interrupt for event TICK */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11221,81 +11490,81 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ -/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ +/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ -/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ +/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ -/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ +/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ -/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ +/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ -/* Bit 1 : Enable or disable event routing for OVRFLW event */ +/* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ -/* Bit 0 : Enable or disable event routing for TICK event */ +/* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to enable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable event routing for TICK event */ +/* Bit 0 : Write '1' to enable event routing for event TICK */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11305,42 +11574,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to disable event routing for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable event routing for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable event routing for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable event routing for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable event routing for OVRFLW event */ +/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable event routing for TICK event */ +/* Bit 0 : Write '1' to disable event routing for event TICK */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11362,7 +11631,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection[n]: Compare register n */ +/* Description: Description collection: Compare register n */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -11375,217 +11644,237 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_TASKS_START */ /* Description: Starts the SAADC and prepares the result buffer in RAM */ -/* Bit 0 : */ +/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_SAMPLE */ /* Description: Takes one SAADC sample */ -/* Bit 0 : */ +/* Bit 0 : Takes one SAADC sample */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ /* Description: Stops the SAADC and terminates all on-going conversions */ -/* Bit 0 : */ +/* Bit 0 : Stops the SAADC and terminates all on-going conversions */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_CALIBRATEOFFSET */ /* Description: Starts offset auto-calibration */ -/* Bit 0 : */ +/* Bit 0 : Starts offset auto-calibration */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_EVENTS_STARTED */ /* Description: The SAADC has started */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has started */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_END */ /* Description: The SAADC has filled up the result buffer */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has filled up the result buffer */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_DONE */ /* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ -/* Bit 0 : */ +/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ /* Description: Result ready for transfer to RAM */ -/* Bit 0 : */ +/* Bit 0 : Result ready for transfer to RAM */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CALIBRATEDONE */ /* Description: Calibration is complete */ -/* Bit 0 : */ +/* Bit 0 : Calibration is complete */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_STOPPED */ /* Description: The SAADC has stopped */ -/* Bit 0 : */ +/* Bit 0 : The SAADC has stopped */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH */ +/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW */ +/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */ -/* Bit 0 : */ +/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for STOPPED event */ +/* Bit 5 : Enable or disable interrupt for event STOPPED */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ +/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for DONE event */ +/* Bit 2 : Enable or disable interrupt for event DONE */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for END event */ +/* Bit 1 : Enable or disable interrupt for event END */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for STARTED event */ +/* Bit 0 : Enable or disable interrupt for event STARTED */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -11594,154 +11883,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for DONE event */ +/* Bit 2 : Write '1' to enable interrupt for event DONE */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for STARTED event */ +/* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11751,154 +12040,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for CH[7].LIMITL event */ +/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for CH[7].LIMITH event */ +/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for CH[6].LIMITL event */ +/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for CH[6].LIMITH event */ +/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for CH[5].LIMITL event */ +/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for CH[5].LIMITH event */ +/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for CH[4].LIMITL event */ +/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for CH[4].LIMITH event */ +/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for CH[3].LIMITL event */ +/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for CH[3].LIMITH event */ +/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for CH[2].LIMITL event */ +/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for CH[2].LIMITH event */ +/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for CH[1].LIMITL event */ +/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for CH[1].LIMITH event */ +/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for CH[0].LIMITL event */ +/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for CH[0].LIMITH event */ +/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for CALIBRATEDONE event */ +/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for RESULTDONE event */ +/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for DONE event */ +/* Bit 2 : Write '1' to disable interrupt for event DONE */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for STARTED event */ +/* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -11924,7 +12213,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster[n]: Input positive pin selection for CH[n] */ +/* Description: Description cluster: Input positive pin selection for CH[n] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -11942,7 +12231,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster[n]: Input negative pin selection for CH[n] */ +/* Description: Description cluster: Input negative pin selection for CH[n] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -11960,7 +12249,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster[n]: Input configuration for CH[n] */ +/* Description: Description cluster: Input configuration for CH[n] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -12019,7 +12308,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster[n]: High/low limits for event monitoring of a channel */ +/* Description: Description cluster: High/low limits for event monitoring of a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -12097,14 +12386,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_EVENTS_READY */ /* Description: TXD byte sent and RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TXD byte sent and RXD byte received */ #define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ +#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ +#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ /* Register: SPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for READY event */ +/* Bit 2 : Write '1' to enable interrupt for event READY */ #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12114,7 +12405,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for READY event */ +/* Bit 2 : Write '1' to disable interrupt for event READY */ #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12237,70 +12528,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_TASKS_START */ /* Description: Start SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Start SPI transaction */ #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_STOP */ /* Description: Stop SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop SPI transaction */ #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_SUSPEND */ /* Description: Suspend SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend SPI transaction */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_RESUME */ /* Description: Resume SPI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume SPI transaction */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: SPIM_EVENTS_STOPPED */ /* Description: SPI transaction has stopped */ -/* Bit 0 : */ +/* Bit 0 : SPI transaction has stopped */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_END */ /* Description: End of RXD buffer and TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer and TXD buffer reached */ #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDTX */ /* Description: End of TXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of TXD buffer reached */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_STARTED */ /* Description: Transaction started */ -/* Bit 0 : */ +/* Bit 0 : Transaction started */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: SPIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 17 : Shortcut between END event and START task */ +/* Bit 17 : Shortcut between event END and task START */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ @@ -12309,35 +12614,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for STARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event STARTED */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for END event */ +/* Bit 6 : Write '1' to enable interrupt for event END */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12347,35 +12652,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for STARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event STARTED */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for END event */ +/* Bit 6 : Write '1' to disable interrupt for event END */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12632,42 +12937,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_TASKS_ACQUIRE */ /* Description: Acquire SPI semaphore */ -/* Bit 0 : */ +/* Bit 0 : Acquire SPI semaphore */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_TASKS_RELEASE */ /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ -/* Bit 0 : */ +/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ /* Register: SPIS_EVENTS_END */ /* Description: Granted transaction completed */ -/* Bit 0 : */ +/* Bit 0 : Granted transaction completed */ #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ -/* Bit 0 : */ +/* Bit 0 : End of RXD buffer reached */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ACQUIRED */ /* Description: Semaphore acquired */ -/* Bit 0 : */ +/* Bit 0 : Semaphore acquired */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ /* Register: SPIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 2 : Shortcut between END event and ACQUIRE task */ +/* Bit 2 : Shortcut between event END and task ACQUIRE */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ @@ -12676,21 +12989,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to enable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for END event */ +/* Bit 1 : Write '1' to enable interrupt for event END */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12700,21 +13013,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to disable interrupt for ACQUIRED event */ +/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for END event */ +/* Bit 1 : Write '1' to disable interrupt for event END */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -12847,6 +13160,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -12868,6 +13190,15 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: SPIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -12910,28 +13241,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_TASKS_START */ /* Description: Start temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Start temperature measurement */ #define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_TASKS_STOP */ /* Description: Stop temperature measurement */ -/* Bit 0 : */ +/* Bit 0 : Stop temperature measurement */ #define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TEMP_EVENTS_DATARDY */ /* Description: Temperature measurement complete, data ready */ -/* Bit 0 : */ +/* Bit 0 : Temperature measurement complete, data ready */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ #define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ +#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -12941,7 +13276,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for DATARDY event */ +/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -13081,122 +13416,130 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_TASKS_START */ /* Description: Start Timer */ -/* Bit 0 : */ +/* Bit 0 : Start Timer */ #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_STOP */ /* Description: Stop Timer */ -/* Bit 0 : */ +/* Bit 0 : Stop Timer */ #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_COUNT */ /* Description: Increment Timer (Counter mode only) */ -/* Bit 0 : */ +/* Bit 0 : Increment Timer (Counter mode only) */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CLEAR */ /* Description: Clear time */ -/* Bit 0 : */ +/* Bit 0 : Clear time */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_SHUTDOWN */ /* Description: Deprecated register - Shut down timer */ -/* Bit 0 : */ +/* Bit 0 : Deprecated field - Shut down timer */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection[n]: Capture Timer value to CC[n] register */ +/* Description: Description collection: Capture Timer value to CC[n] register */ -/* Bit 0 : */ +/* Bit 0 : Capture Timer value to CC[n] register */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ /* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection[n]: Compare event on CC[n] match */ +/* Description: Description collection: Compare event on CC[n] match */ -/* Bit 0 : */ +/* Bit 0 : Compare event on CC[n] match */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ /* Register: TIMER_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ +/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ +/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ +/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ +/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ +/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ +/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ +/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ +/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ +/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ +/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ +/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ +/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ @@ -13205,42 +13548,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13250,42 +13593,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for COMPARE[5] event */ +/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for COMPARE[4] event */ +/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for COMPARE[3] event */ +/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for COMPARE[2] event */ +/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for COMPARE[1] event */ +/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for COMPARE[0] event */ +/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13321,7 +13664,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection[n]: Capture/Compare register n */ +/* Description: Description collection: Capture/Compare register n */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ @@ -13334,90 +13677,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWI_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_RXDREADY */ /* Description: TWI RXD byte received */ -/* Bit 0 : */ +/* Bit 0 : TWI RXD byte received */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ #define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_TXDSENT */ /* Description: TWI TXD byte sent */ -/* Bit 0 : */ +/* Bit 0 : TWI TXD byte sent */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ #define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_BB */ /* Description: TWI byte boundary, generated before each byte that is sent or received */ -/* Bit 0 : */ +/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ #define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ #define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ +#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ /* Register: TWI_EVENTS_SUSPENDED */ /* Description: TWI entered the suspended state */ -/* Bit 0 : */ +/* Bit 0 : TWI entered the suspended state */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWI_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 1 : Shortcut between BB event and STOP task */ +/* Bit 1 : Shortcut between event BB and task STOP */ #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between BB event and SUSPEND task */ +/* Bit 0 : Shortcut between event BB and task SUSPEND */ #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -13426,42 +13786,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for BB event */ +/* Bit 14 : Write '1' to enable interrupt for event BB */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13471,42 +13831,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for BB event */ +/* Bit 14 : Write '1' to disable interrupt for event BB */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDSENT event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDREADY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13615,121 +13975,140 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_TASKS_STARTRX */ /* Description: Start TWI receive sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI receive sequence */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ -/* Bit 0 : */ +/* Bit 0 : Start TWI transmit sequence */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STOP */ /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIM_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ /* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : */ +/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTRX */ /* Description: Byte boundary, starting to receive the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to receive the last byte */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTTX */ /* Description: Byte boundary, starting to transmit the last byte */ -/* Bit 0 : */ +/* Bit 0 : Byte boundary, starting to transmit the last byte */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ /* Register: TWIM_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 12 : Shortcut between LASTRX event and STOP task */ +/* Bit 12 : Shortcut between event LASTRX and task STOP */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between LASTRX event and SUSPEND task */ +/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ #define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ #define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ +/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between LASTTX event and STOP task */ +/* Bit 9 : Shortcut between event LASTTX and task STOP */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ +/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ +/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -13738,43 +14117,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for LASTTX event */ +/* Bit 24 : Enable or disable interrupt for event LASTTX */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for LASTRX event */ +/* Bit 23 : Enable or disable interrupt for event LASTRX */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ +/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -13783,49 +14162,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13835,49 +14214,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for LASTTX event */ +/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for LASTRX event */ +/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for SUSPENDED event */ +/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14032,90 +14411,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_TASKS_STOP */ /* Description: Stop TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Stop TWI transaction */ #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Suspend TWI transaction */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_RESUME */ /* Description: Resume TWI transaction */ -/* Bit 0 : */ +/* Bit 0 : Resume TWI transaction */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARERX */ /* Description: Prepare the TWI slave to respond to a write command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a write command */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARETX */ /* Description: Prepare the TWI slave to respond to a read command */ -/* Bit 0 : */ +/* Bit 0 : Prepare the TWI slave to respond to a read command */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ /* Register: TWIS_EVENTS_STOPPED */ /* Description: TWI stopped */ -/* Bit 0 : */ +/* Bit 0 : TWI stopped */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_ERROR */ /* Description: TWI error */ -/* Bit 0 : */ +/* Bit 0 : TWI error */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ -/* Bit 0 : */ +/* Bit 0 : Receive sequence started */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ -/* Bit 0 : */ +/* Bit 0 : Transmit sequence started */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_WRITE */ /* Description: Write command received */ -/* Bit 0 : */ +/* Bit 0 : Write command received */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_READ */ /* Description: Read command received */ -/* Bit 0 : */ +/* Bit 0 : Read command received */ #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ /* Register: TWIS_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 14 : Shortcut between READ event and SUSPEND task */ +/* Bit 14 : Shortcut between event READ and task SUSPEND */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ +/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -14124,37 +14520,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 26 : Enable or disable interrupt for READ event */ +/* Bit 26 : Enable or disable interrupt for event READ */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for WRITE event */ +/* Bit 25 : Enable or disable interrupt for event WRITE */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STOPPED event */ +/* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -14163,42 +14559,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to enable interrupt for READ event */ +/* Bit 26 : Write '1' to enable interrupt for event READ */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for WRITE event */ +/* Bit 25 : Write '1' to enable interrupt for event WRITE */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14208,42 +14604,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to disable interrupt for READ event */ +/* Bit 26 : Write '1' to disable interrupt for event READ */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for WRITE event */ +/* Bit 25 : Write '1' to disable interrupt for event WRITE */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STOPPED event */ +/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14342,6 +14738,15 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_RXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -14363,8 +14768,17 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +/* Register: TWIS_TXD_LIST */ +/* Description: EasyDMA list type */ + +/* Bits 1..0 : List type */ +#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ +#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ +#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ + /* Register: TWIS_ADDRESS */ -/* Description: Description collection[n]: TWI slave address n */ +/* Description: Description collection: TWI slave address n */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -14399,90 +14813,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UART_TASKS_SUSPEND */ /* Description: Suspend UART */ -/* Bit 0 : */ +/* Bit 0 : Suspend UART */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ +#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ /* Register: UART_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXDRDY */ /* Description: Data received in RXD */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UART_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UART_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between NCTS event and STOPRX task */ +/* Bit 4 : Shortcut between event NCTS and task STOPRX */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between CTS event and STARTRX task */ +/* Bit 3 : Shortcut between event CTS and task STARTRX */ #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14491,42 +14922,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENSET */ /* Description: Enable interrupt */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14536,42 +14967,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14724,6 +15155,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_CONFIG */ /* Description: Configuration of parity and hardware flow control */ +/* Bit 4 : Stop bits */ +#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ +#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ +#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ +#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ + /* Bits 3..1 : Parity */ #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ @@ -14743,125 +15180,152 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_TASKS_STARTRX */ /* Description: Start UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Start UART receiver */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPRX */ /* Description: Stop UART receiver */ -/* Bit 0 : */ +/* Bit 0 : Stop UART receiver */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STARTTX */ /* Description: Start UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Start UART transmitter */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPTX */ /* Description: Stop UART transmitter */ -/* Bit 0 : */ +/* Bit 0 : Stop UART transmitter */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_FLUSHRX */ /* Description: Flush RX FIFO into RX buffer */ -/* Bit 0 : */ +/* Bit 0 : Flush RX FIFO into RX buffer */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ /* Register: UARTE_EVENTS_CTS */ /* Description: CTS is activated (set low). Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ -/* Bit 0 : */ +/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXDRDY */ /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ -/* Bit 0 : */ +/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDRX */ /* Description: Receive buffer is filled up */ -/* Bit 0 : */ +/* Bit 0 : Receive buffer is filled up */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ -/* Bit 0 : */ +/* Bit 0 : Data sent from TXD */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDTX */ /* Description: Last TX byte transmitted */ -/* Bit 0 : */ +/* Bit 0 : Last TX byte transmitted */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ERROR */ /* Description: Error detected */ -/* Bit 0 : */ +/* Bit 0 : Error detected */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXTO */ /* Description: Receiver timeout */ -/* Bit 0 : */ +/* Bit 0 : Receiver timeout */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXSTARTED */ /* Description: UART receiver has started */ -/* Bit 0 : */ +/* Bit 0 : UART receiver has started */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTARTED */ /* Description: UART transmitter has started */ -/* Bit 0 : */ +/* Bit 0 : UART transmitter has started */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTOPPED */ /* Description: Transmitter stopped */ -/* Bit 0 : */ +/* Bit 0 : Transmitter stopped */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ /* Register: UARTE_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ +/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ +/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14870,67 +15334,67 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ +/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ +/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ +/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for RXTO event */ +/* Bit 17 : Enable or disable interrupt for event RXTO */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ERROR event */ +/* Bit 9 : Enable or disable interrupt for event ERROR */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDTX event */ +/* Bit 8 : Enable or disable interrupt for event ENDTX */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +/* Bit 7 : Enable or disable interrupt for event TXDRDY */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDRX event */ +/* Bit 4 : Enable or disable interrupt for event ENDRX */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +/* Bit 2 : Enable or disable interrupt for event RXDRDY */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for NCTS event */ +/* Bit 1 : Enable or disable interrupt for event NCTS */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for CTS event */ +/* Bit 0 : Enable or disable interrupt for event CTS */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ @@ -14939,77 +15403,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to enable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for RXTO event */ +/* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ERROR event */ +/* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for NCTS event */ +/* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for CTS event */ +/* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15019,77 +15483,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to disable interrupt for TXSTOPPED event */ +/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for TXSTARTED event */ +/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for RXSTARTED event */ +/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for RXTO event */ +/* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ERROR event */ +/* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDTX event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for TXDRDY event */ +/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDRX event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for RXDRDY event */ +/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for NCTS event */ +/* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for CTS event */ +/* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15293,28 +15757,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: User information configuration registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection[n]: Reserved for Nordic firmware design */ +/* Description: Description collection: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection[n]: Reserved for Nordic hardware design */ +/* Description: Description collection: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection[n]: Reserved for customer */ +/* Description: Description collection: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection[n]: Mapping of the nRESET function */ +/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -15326,7 +15790,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ #define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ +/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ @@ -15382,173 +15846,204 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Universal serial bus device */ /* Register: USBD_TASKS_STARTEPIN */ -/* Description: Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ +/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ #define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ +#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOIN */ /* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ #define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ +#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTEPOUT */ -/* Description: Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ +/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ -/* Bit 0 : */ +/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ #define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ +#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_STARTISOOUT */ /* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ -/* Bit 0 : */ +/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ #define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ +#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0RCVOUT */ /* Description: Allows OUT data stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows OUT data stage on control endpoint 0 */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ #define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ +#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STATUS */ /* Description: Allows status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Allows status stage on control endpoint 0 */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ #define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ +#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_EP0STALL */ /* Description: Stalls data and status stage on control endpoint 0 */ -/* Bit 0 : */ +/* Bit 0 : Stalls data and status stage on control endpoint 0 */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ #define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ +#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMDRIVE */ /* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ -/* Bit 0 : */ +/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ #define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ +#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_TASKS_DPDMNODRIVE */ /* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ -/* Bit 0 : */ +/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ #define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ +#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ /* Register: USBD_EVENTS_USBRESET */ /* Description: Signals that a USB reset condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ #define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_STARTED */ /* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ -/* Bit 0 : */ +/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0DATADONE */ /* Description: An acknowledged data transfer has taken place on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOIN */ /* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOOUT */ /* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : */ +/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_SOF */ /* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ -/* Bit 0 : */ +/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ #define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ #define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ +#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_USBEVENT */ /* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ -/* Bit 0 : */ +/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ #define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EP0SETUP */ /* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ -/* Bit 0 : */ +/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ #define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_EPDATA */ /* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ -/* Bit 0 : */ +/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ #define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ +#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ /* Register: USBD_SHORTS */ -/* Description: Shortcut register */ +/* Description: Shortcuts between local events and tasks */ -/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ +/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ +/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ +/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ +/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ +/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ @@ -15557,151 +16052,151 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for EPDATA event */ +/* Bit 24 : Enable or disable interrupt for event EPDATA */ #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ +/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ -/* Bit 22 : Enable or disable interrupt for USBEVENT event */ +/* Bit 22 : Enable or disable interrupt for event USBEVENT */ #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ -/* Bit 21 : Enable or disable interrupt for SOF event */ +/* Bit 21 : Enable or disable interrupt for event SOF */ #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ +/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ +/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ +/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for STARTED event */ +/* Bit 1 : Enable or disable interrupt for event STARTED */ #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for USBRESET event */ +/* Bit 0 : Enable or disable interrupt for event USBRESET */ #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ @@ -15710,175 +16205,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for SOF event */ +/* Bit 21 : Write '1' to enable interrupt for event SOF */ #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for STARTED event */ +/* Bit 1 : Write '1' to enable interrupt for event STARTED */ #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -15888,175 +16383,175 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for EPDATA event */ +/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for EP0SETUP event */ +/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for USBEVENT event */ +/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for SOF event */ +/* Bit 21 : Write '1' to disable interrupt for event SOF */ #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for ENDISOOUT event */ +/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for ENDEPOUT[7] event */ +/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for ENDEPOUT[6] event */ +/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for ENDEPOUT[5] event */ +/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for ENDEPOUT[4] event */ +/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for ENDEPOUT[3] event */ +/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for ENDEPOUT[2] event */ +/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for ENDEPOUT[1] event */ +/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for ENDEPOUT[0] event */ +/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for ENDISOIN event */ +/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for EP0DATADONE event */ +/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for ENDEPIN[7] event */ +/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for ENDEPIN[6] event */ +/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for ENDEPIN[5] event */ +/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for ENDEPIN[4] event */ +/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for ENDEPIN[3] event */ +/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for ENDEPIN[2] event */ +/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for ENDEPIN[1] event */ +/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for ENDEPIN[0] event */ +/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for STARTED event */ +/* Bit 1 : Write '1' to disable interrupt for event STARTED */ #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for USBRESET event */ +/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16097,7 +16592,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ /* Register: USBD_HALTED_EPIN */ -/* Description: Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16106,7 +16601,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ /* Register: USBD_HALTED_EPOUT */ -/* Description: Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16404,7 +16899,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ /* Register: USBD_SIZE_EPOUT */ -/* Description: Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint */ +/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ /* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -16639,21 +17134,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ /* Register: USBD_EPIN_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPIN_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPIN_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16681,21 +17176,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: USBD_EPOUT_PTR */ -/* Description: Description cluster[n]: Data pointer */ +/* Description: Description cluster: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPOUT_MAXCNT */ -/* Description: Description cluster[n]: Maximum number of bytes to transfer */ +/* Description: Description cluster: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPOUT_AMOUNT */ -/* Description: Description cluster[n]: Number of bytes transferred in the last transaction */ +/* Description: Description cluster: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -16729,21 +17224,24 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_TASKS_START */ /* Description: Start the watchdog */ -/* Bit 0 : */ +/* Bit 0 : Start the watchdog */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_EVENTS_TIMEOUT */ /* Description: Watchdog timeout */ -/* Bit 0 : */ +/* Bit 0 : Watchdog timeout */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16753,7 +17251,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for TIMEOUT event */ +/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -16894,7 +17392,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection[n]: Reload request n */ +/* Description: Description collection: Reload request n */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/mdk/nrf52_to_nrf52810.h b/mdk/nrf52_to_nrf52810.h index 943c454b2..11adfb027 100644 --- a/mdk/nrf52_to_nrf52810.h +++ b/mdk/nrf52_to_nrf52810.h @@ -44,50 +44,107 @@ POSSIBILITY OF SUCH DAMAGE. /* Interrupt service routines handlers. Note that handlers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler and SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler are not redefined since functionality is not equivalent. */ -#define UARTE0_UART0_IRQHandler UARTE0_IRQHandler -#define COMP_LPCOMP_IRQHandler COMP_IRQHandler -#define SWI2_EGU2_IRQHandler SWI2_IRQHandler -#define SWI3_EGU3_IRQHandler SWI3_IRQHandler -#define SWI4_EGU4_IRQHandler SWI4_IRQHandler -#define SWI5_EGU5_IRQHandler SWI5_IRQHandler +#ifndef COMP_LPCOMP_IRQHandler + #define COMP_LPCOMP_IRQHandler COMP_IRQHandler +#endif +#ifndef SWI2_EGU2_IRQHandler + #define SWI2_EGU2_IRQHandler SWI2_IRQHandler +#endif +#ifndef SWI3_EGU3_IRQHandler + #define SWI3_EGU3_IRQHandler SWI3_IRQHandler +#endif +#ifndef SWI4_EGU4_IRQHandler + #define SWI4_EGU4_IRQHandler SWI4_IRQHandler +#endif +#ifndef SWI5_EGU5_IRQHandler + #define SWI5_EGU5_IRQHandler SWI5_IRQHandler +#endif /* Interrupt service routines index. Note that indexes SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn and SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn are not redefined since functionality is not equivalent. */ -#define UARTE0_UART0_IRQn UARTE0_IRQn -#define COMP_LPCOMP_IRQn COMP_IRQn -#define SWI2_EGU2_IRQn SWI2_IRQn -#define SWI3_EGU3_IRQn SWI3_IRQn -#define SWI4_EGU4_IRQn SWI4_IRQn -#define SWI5_EGU5_IRQn SWI5_IRQn - +#ifndef COMP_LPCOMP_IRQn + #define COMP_LPCOMP_IRQn COMP_IRQn +#endif +#ifndef SWI2_EGU2_IRQn + #define SWI2_EGU2_IRQn SWI2_IRQn +#endif +#ifndef SWI3_EGU3_IRQn + #define SWI3_EGU3_IRQn SWI3_IRQn +#endif +#ifndef SWI4_EGU4_IRQn + #define SWI4_EGU4_IRQn SWI4_IRQn +#endif +#ifndef SWI5_EGU5_IRQn + #define SWI5_EGU5_IRQn SWI5_IRQn +#endif /* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ /* I2S */ /* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ -#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled -#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled -#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master -#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave -#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled -#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled -#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled -#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled -#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled -#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled -#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit -#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left -#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right -#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned -#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo -#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left -#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif /* LPCOMP */ /* Corrected typo in RESULT register. */ -#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif /*lint --flb "Leave library region" */ diff --git a/mdk/nrf52_to_nrf52840.h b/mdk/nrf52_to_nrf52840.h index 67345cc4a..958776662 100644 --- a/mdk/nrf52_to_nrf52840.h +++ b/mdk/nrf52_to_nrf52840.h @@ -44,50 +44,106 @@ POSSIBILITY OF SUCH DAMAGE. /* UART */ /* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ -#define PSELRTS PSEL.RTS -#define PSELTXD PSEL.TXD -#define PSELCTS PSEL.CTS -#define PSELRXD PSEL.RXD +#ifndef PSELRTS + #define PSELRTS PSEL.RTS +#endif +#ifndef PSELTXD + #define PSELTXD PSEL.TXD +#endif +#ifndef PSELCTS + #define PSELCTS PSEL.CTS +#endif +#ifndef PSELRXD + #define PSELRXD PSEL.RXD +#endif /* TWI */ /* The registers PSELSCL, PSELSDA were restructured into a struct. */ -#define PSELSCL PSEL.SCL -#define PSELSDA PSEL.SDA +#ifndef PSELSCL + #define PSELSCL PSEL.SCL +#endif +#ifndef PSELSDA + #define PSELSDA PSEL.SDA +#endif /* LPCOMP */ /* The hysteresis control enumerated values has changed name for nRF52840 devices. */ -#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled -#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#ifndef LPCOMP_HYST_HYST_NoHyst + #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled +#endif +#ifndef LPCOMP_HYST_HYST_Hyst50mV + #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled +#endif /* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ /* I2S */ /* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ -#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled -#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled -#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master -#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave -#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled -#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled -#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled -#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled -#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled -#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled -#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit -#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit -#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left -#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right -#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned -#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo -#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left -#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#ifndef I2S_ENABLE_ENABLE_DISABLE + #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#endif +#ifndef I2S_ENABLE_ENABLE_ENABLE + #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#endif +#ifndef I2S_CONFIG_MODE_MODE_MASTER + #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#endif +#ifndef I2S_CONFIG_MODE_MODE_SLAVE + #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE + #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#endif +#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE + #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE + #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#endif +#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE + #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE + #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#endif +#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE + #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#endif +#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT + #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT + #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#endif +#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT + #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#endif +#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED + #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO + #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT + #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#endif +#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT + #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right +#endif /* LPCOMP */ /* Corrected typo in RESULT register. */ -#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#ifndef LPCOMP_RESULT_RESULT_Bellow + #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#endif /*lint --flb "Leave library region" */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 26c91c17d..c8d3eea1a 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -30,10 +30,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 03. December 2018 - * @note Generated by SVDConv V3.3.18 on Monday, 03.12.2018 11:18:26 + * @date 17. January 2019 + * @note Generated by SVDConv V3.3.18 on Thursday, 17.01.2019 17:25:40 * from File 'nrf9160.svd', - * last modified on Monday, 03.12.2018 10:18:21 + * last modified on Thursday, 17.01.2019 16:25:35 */ @@ -843,8 +843,8 @@ typedef struct { /*!< (@ 0x40004000) REGULATORS_N */ typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ - __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ - __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK source */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK source */ __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ __IM uint32_t RESERVED[28]; diff --git a/mdk/nrf9160.svd b/mdk/nrf9160.svd index e9523868a..22befbbc6 100644 --- a/mdk/nrf9160.svd +++ b/mdk/nrf9160.svd @@ -3281,13 +3281,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTART - Start HFCLK crystal oscillator + Start HFCLK source 0x000 write-only TASKS_HFCLKSTART - Start HFCLK crystal oscillator + Start HFCLK source 0 0 @@ -3302,13 +3302,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_HFCLKSTOP - Stop HFCLK crystal oscillator + Stop HFCLK source 0x004 write-only TASKS_HFCLKSTOP - Stop HFCLK crystal oscillator + Stop HFCLK source 0 0 diff --git a/mdk/nrf9160_bitfields.h b/mdk/nrf9160_bitfields.h index 1dbc7a516..a68ff80fc 100644 --- a/mdk/nrf9160_bitfields.h +++ b/mdk/nrf9160_bitfields.h @@ -39,17 +39,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Clock management 0 */ /* Register: CLOCK_TASKS_HFCLKSTART */ -/* Description: Start HFCLK crystal oscillator */ +/* Description: Start HFCLK source */ -/* Bit 0 : Start HFCLK crystal oscillator */ +/* Bit 0 : Start HFCLK source */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ -/* Description: Stop HFCLK crystal oscillator */ +/* Description: Stop HFCLK source */ -/* Bit 0 : Stop HFCLK crystal oscillator */ +/* Bit 0 : Stop HFCLK source */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ diff --git a/mdk/nrf9160_peripherals.h b/mdk/nrf9160_peripherals.h index aff5763a4..6817184b8 100644 --- a/mdk/nrf9160_peripherals.h +++ b/mdk/nrf9160_peripherals.h @@ -44,10 +44,6 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PRESENT #define POWER_COUNT 1 -/* Memory Watch Unit */ -#define MWU_PRESENT -#define MWU_COUNT 1 - /* GPIO */ #define GPIO_PRESENT #define GPIO_COUNT 1 diff --git a/mdk/nrf_peripherals.h b/mdk/nrf_peripherals.h index 8f51b8c93..14eb9b2fe 100644 --- a/mdk/nrf_peripherals.h +++ b/mdk/nrf_peripherals.h @@ -48,6 +48,8 @@ POSSIBILITY OF SUCH DAMAGE. #elif defined(NRF52810_XXAA) #include "nrf52810_peripherals.h" + #elif defined(NRF52811_XXAA) + #include "nrf52811_peripherals.h" #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) #include "nrf52832_peripherals.h" #elif defined(NRF52840_XXAA) diff --git a/mdk/ses_startup_nrf52810.s b/mdk/ses_startup_nrf52810.s index a039ce362..1cac950be 100644 --- a/mdk/ses_startup_nrf52810.s +++ b/mdk/ses_startup_nrf52810.s @@ -121,14 +121,14 @@ Dummy_Handler: .weak RADIO_IRQHandler .thumb_set RADIO_IRQHandler, Dummy_Handler -.weak UARTE0_IRQHandler -.thumb_set UARTE0_IRQHandler, Dummy_Handler +.weak UARTE0_UART0_IRQHandler +.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler -.weak TWIM0_TWIS0_IRQHandler -.thumb_set TWIM0_TWIS0_IRQHandler, Dummy_Handler +.weak TWIM0_TWIS0_TWI0_IRQHandler +.thumb_set TWIM0_TWIS0_TWI0_IRQHandler, Dummy_Handler -.weak SPIM0_SPIS0_IRQHandler -.thumb_set SPIM0_SPIS0_IRQHandler, Dummy_Handler +.weak SPIM0_SPIS0_SPI0_IRQHandler +.thumb_set SPIM0_SPIS0_SPI0_IRQHandler, Dummy_Handler .weak GPIOTE_IRQHandler .thumb_set GPIOTE_IRQHandler, Dummy_Handler @@ -238,9 +238,9 @@ _vectors: /* External Interrupts */ .word POWER_CLOCK_IRQHandler .word RADIO_IRQHandler - .word UARTE0_IRQHandler - .word TWIM0_TWIS0_IRQHandler - .word SPIM0_SPIS0_IRQHandler + .word UARTE0_UART0_IRQHandler + .word TWIM0_TWIS0_TWI0_IRQHandler + .word SPIM0_SPIS0_SPI0_IRQHandler .word 0 /*Reserved */ .word GPIOTE_IRQHandler .word SAADC_IRQHandler diff --git a/mdk/ses_startup_nrf52811.s b/mdk/ses_startup_nrf52811.s new file mode 100644 index 000000000..966e74cc4 --- /dev/null +++ b/mdk/ses_startup_nrf52811.s @@ -0,0 +1,360 @@ +/*********************************************************************************** + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + *********************************************************************************** + * * + * (c) 2014 - 2018 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + *********************************************************************************** + * * + * All rights reserved. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * conditions are met: * + * * + * - Redistributions of source code must retain the above copyright * + * notice, this list of conditions and the following disclaimer. * + * * + * - Neither the name of SEGGER Microcontroller GmbH * + * nor the names of its contributors may be used to endorse or * + * promote products derived from this software without specific * + * prior written permission. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. * + * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ***********************************************************************************/ + +/************************************************************************************ + * Preprocessor Definitions * + * ------------------------ * + * VECTORS_IN_RAM * + * * + * If defined, an area of RAM will large enough to store the vector table * + * will be reserved. * + * * + ************************************************************************************/ + + .syntax unified + .code 16 + + .section .init, "ax" + .align 0 + +/************************************************************************************ + * Default Exception Handlers * + ************************************************************************************/ + + + .thumb_func + .weak NMI_Handler +NMI_Handler: + b . + + .thumb_func + .weak HardFault_Handler +HardFault_Handler: + b . + + .thumb_func + .weak MemoryManagement_Handler +MemoryManagement_Handler: + b . + + .thumb_func + .weak BusFault_Handler +BusFault_Handler: + b . + + .thumb_func + .weak UsageFault_Handler +UsageFault_Handler: + b . + + .thumb_func + .weak SVC_Handler +SVC_Handler: + b . + + .thumb_func + .weak DebugMon_Handler +DebugMon_Handler: + b . + + .thumb_func + .weak PendSV_Handler +PendSV_Handler: + b . + + .thumb_func + .weak SysTick_Handler +SysTick_Handler: + b . + + .thumb_func + .weak Dummy_Handler +Dummy_Handler: + b . + +/************************************************************************************ + * Default Interrupt Handlers * + ************************************************************************************/ + +.weak POWER_CLOCK_IRQHandler +.thumb_set POWER_CLOCK_IRQHandler, Dummy_Handler + +.weak RADIO_IRQHandler +.thumb_set RADIO_IRQHandler, Dummy_Handler + +.weak UARTE0_UART0_IRQHandler +.thumb_set UARTE0_UART0_IRQHandler, Dummy_Handler + +.weak TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +.thumb_set TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler, Dummy_Handler + +.weak SPIM0_SPIS0_SPI0_IRQHandler +.thumb_set SPIM0_SPIS0_SPI0_IRQHandler, Dummy_Handler + +.weak GPIOTE_IRQHandler +.thumb_set GPIOTE_IRQHandler, Dummy_Handler + +.weak SAADC_IRQHandler +.thumb_set SAADC_IRQHandler, Dummy_Handler + +.weak TIMER0_IRQHandler +.thumb_set TIMER0_IRQHandler, Dummy_Handler + +.weak TIMER1_IRQHandler +.thumb_set TIMER1_IRQHandler, Dummy_Handler + +.weak TIMER2_IRQHandler +.thumb_set TIMER2_IRQHandler, Dummy_Handler + +.weak RTC0_IRQHandler +.thumb_set RTC0_IRQHandler, Dummy_Handler + +.weak TEMP_IRQHandler +.thumb_set TEMP_IRQHandler, Dummy_Handler + +.weak RNG_IRQHandler +.thumb_set RNG_IRQHandler, Dummy_Handler + +.weak ECB_IRQHandler +.thumb_set ECB_IRQHandler, Dummy_Handler + +.weak CCM_AAR_IRQHandler +.thumb_set CCM_AAR_IRQHandler, Dummy_Handler + +.weak WDT_IRQHandler +.thumb_set WDT_IRQHandler, Dummy_Handler + +.weak RTC1_IRQHandler +.thumb_set RTC1_IRQHandler, Dummy_Handler + +.weak QDEC_IRQHandler +.thumb_set QDEC_IRQHandler, Dummy_Handler + +.weak COMP_IRQHandler +.thumb_set COMP_IRQHandler, Dummy_Handler + +.weak SWI0_EGU0_IRQHandler +.thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler + +.weak SWI1_EGU1_IRQHandler +.thumb_set SWI1_EGU1_IRQHandler, Dummy_Handler + +.weak SWI2_IRQHandler +.thumb_set SWI2_IRQHandler, Dummy_Handler + +.weak SWI3_IRQHandler +.thumb_set SWI3_IRQHandler, Dummy_Handler + +.weak SWI4_IRQHandler +.thumb_set SWI4_IRQHandler, Dummy_Handler + +.weak SWI5_IRQHandler +.thumb_set SWI5_IRQHandler, Dummy_Handler + +.weak PWM0_IRQHandler +.thumb_set PWM0_IRQHandler, Dummy_Handler + +.weak PDM_IRQHandler +.thumb_set PDM_IRQHandler, Dummy_Handler + +/************************************************************************************ + * Reset Handler Extensions * + ************************************************************************************/ + + .extern Reset_Handler + .global nRFInitialize + + .thumb_func +nRFInitialize: + bx lr + + +/************************************************************************************ + * Vector Table * + ************************************************************************************/ + + .section .vectors, "ax" + .align 0 + .global _vectors + .extern __stack_end__ + +_vectors: + .word __stack_end__ + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemoryManagement_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word SVC_Handler + .word DebugMon_Handler + .word 0 /*Reserved */ + .word PendSV_Handler + .word SysTick_Handler + +/* External Interrupts */ + .word POWER_CLOCK_IRQHandler + .word RADIO_IRQHandler + .word UARTE0_UART0_IRQHandler + .word TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler + .word SPIM0_SPIS0_SPI0_IRQHandler + .word 0 /*Reserved */ + .word GPIOTE_IRQHandler + .word SAADC_IRQHandler + .word TIMER0_IRQHandler + .word TIMER1_IRQHandler + .word TIMER2_IRQHandler + .word RTC0_IRQHandler + .word TEMP_IRQHandler + .word RNG_IRQHandler + .word ECB_IRQHandler + .word CCM_AAR_IRQHandler + .word WDT_IRQHandler + .word RTC1_IRQHandler + .word QDEC_IRQHandler + .word COMP_IRQHandler + .word SWI0_EGU0_IRQHandler + .word SWI1_EGU1_IRQHandler + .word SWI2_IRQHandler + .word SWI3_IRQHandler + .word SWI4_IRQHandler + .word SWI5_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word PWM0_IRQHandler + .word PDM_IRQHandler + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ + .word 0 /*Reserved */ +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" + .align 0 + .global _vectors_ram + +_vectors_ram: + .space _vectors_end - _vectors, 0 +#endif diff --git a/mdk/system_nrf51.c b/mdk/system_nrf51.c index e34244119..e31f2fe0f 100644 --- a/mdk/system_nrf51.c +++ b/mdk/system_nrf51.c @@ -58,7 +58,7 @@ void SystemInit(void) /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required to enable the use of peripherals" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. The side effect of executing these instructions in the devices + https://www.nordicsemi.com/DocLib The side effect of executing these instructions in the devices that do not need it is that the new peripherals in the second generation devices (LPCOMP for example) will not be available. */ if (is_manual_peripheral_setup_needed()) @@ -69,7 +69,7 @@ void SystemInit(void) /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG register is incorrect" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ + https://www.nordicsemi.com/DocLib There is no side effect of using these instruction if not needed. */ if (is_disabled_in_debug_needed()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; @@ -77,7 +77,7 @@ void SystemInit(void) /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document - for your device found at https://www.nordicsemi.com/. */ + for your device found at https://www.nordicsemi.com/DocLib */ if (is_peripheral_domain_setup_needed()){ if (*(uint32_t volatile *)0x4006EC00 != 1){ *(uint32_t volatile *)0x4006EC00 = 0x9375; diff --git a/mdk/system_nrf52.c b/mdk/system_nrf52.c index d9d684cc1..be6abbf2d 100644 --- a/mdk/system_nrf52.c +++ b/mdk/system_nrf52.c @@ -81,31 +81,31 @@ void SystemInit(void) #endif /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_12()){ *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; } /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_16()){ *(volatile uint32_t *)0x4007C074 = 3131961357ul; } /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_31()){ *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; } /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_32()){ CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; } /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_36()){ NRF_CLOCK->EVENTS_DONE = 0; NRF_CLOCK->EVENTS_CTTO = 0; @@ -113,13 +113,13 @@ void SystemInit(void) } /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_37()){ *(volatile uint32_t *)0x400005A0 = 0x3; } /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_57()){ *(volatile uint32_t *)0x40005610 = 0x00000005; *(volatile uint32_t *)0x40005688 = 0x00000001; @@ -128,7 +128,7 @@ void SystemInit(void) } /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_66()){ NRF_TEMP->A0 = NRF_FICR->TEMP.A0; NRF_TEMP->A1 = NRF_FICR->TEMP.A1; @@ -150,13 +150,13 @@ void SystemInit(void) } /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_108()){ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; } /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_136()){ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; @@ -164,7 +164,7 @@ void SystemInit(void) } /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_182()){ *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); } diff --git a/mdk/system_nrf52810.c b/mdk/system_nrf52810.c index 327b70d95..26ef79b7d 100644 --- a/mdk/system_nrf52810.c +++ b/mdk/system_nrf52810.c @@ -86,7 +86,7 @@ void SystemInit(void) #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document - for nRF52832 device located at https://infocenter.nordicsemi.com/ */ + for nRF52832 device located at https://www.nordicsemi.com/DocLib */ if (errata_12()){ *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; } @@ -94,28 +94,28 @@ void SystemInit(void) #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document - for nRF52832 device located at https://infocenter.nordicsemi.com/ */ + for nRF52832 device located at https://www.nordicsemi.com/DocLib */ if (errata_16()){ *(volatile uint32_t *)0x4007C074 = 3131961357ul; } #endif /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_31()){ *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; } #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document - for nRF52832 device located at https://infocenter.nordicsemi.com/ */ + for nRF52832 device located at https://www.nordicsemi.com/DocLib */ if (errata_32()){ CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; } #endif /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_36()){ NRF_CLOCK->EVENTS_DONE = 0; NRF_CLOCK->EVENTS_CTTO = 0; @@ -124,7 +124,7 @@ void SystemInit(void) #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_37()){ *(volatile uint32_t *)0x400005A0 = 0x3; } @@ -132,7 +132,7 @@ void SystemInit(void) #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_57()){ *(volatile uint32_t *)0x40005610 = 0x00000005; *(volatile uint32_t *)0x40005688 = 0x00000001; @@ -142,7 +142,7 @@ void SystemInit(void) #endif /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_66()){ NRF_TEMP->A0 = NRF_FICR->TEMP.A0; NRF_TEMP->A1 = NRF_FICR->TEMP.A1; @@ -164,21 +164,21 @@ void SystemInit(void) } /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_103()){ NRF_CCM->MAXPACKETSIZE = 0xFBul; } #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_108()){ *(volatile uint32_t *)0x40000EE4 = *(volatile uint32_t *)0x10000258 & 0x0000004F; } #endif /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_136()){ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; @@ -187,7 +187,7 @@ void SystemInit(void) #if defined (DEVELOP_IN_NRF52832) /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_182()){ *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); } diff --git a/mdk/system_nrf52811.c b/mdk/system_nrf52811.c new file mode 100644 index 000000000..ddf76ed43 --- /dev/null +++ b/mdk/system_nrf52811.c @@ -0,0 +1,168 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +/* NOTE: Template files (including this one) are application specific and therefore expected to + be copied into the application project folder prior to its use! */ + +#include +#include +#include "nrf.h" +#include "system_nrf52811.h" + +/*lint ++flb "Enter library region" */ + +#define __SYSTEM_CLOCK_64M (64000000UL) + +static bool errata_31(void); +static bool errata_36(void); +static bool errata_66(void); +static bool errata_136(void); + + +#if defined ( __CC_ARM ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#elif defined ( __ICCARM__ ) + __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; +#elif defined ( __GNUC__ ) + uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; +#endif + +void SystemCoreClockUpdate(void) +{ + SystemCoreClock = __SYSTEM_CLOCK_64M; +} + +void SystemInit(void) +{ + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ + if (errata_136()){ + if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ + NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; + } + } + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + SystemCoreClockUpdate(); +} + +static bool errata_31(void) +{ + #if !defined (DISABLE_WORKAROUND_31) + if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + #endif + + return false; +} + +static bool errata_36(void) +{ + #if !defined (DISABLE_WORKAROUND_36) + if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + #endif + + return false; +} + +static bool errata_66(void) +{ + #if !defined (DISABLE_WORKAROUND_66) + if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + #endif + + return false; +} + +static bool errata_136(void) +{ + #if !defined (DISABLE_WORKAROUND_136) + if ((*(uint32_t *)0x10000130ul == 0xEul) && (*(uint32_t *)0x10000134ul == 0x0ul)){ + return true; + } + #endif + + return false; +} + + + + +/*lint --flb "Leave library region" */ diff --git a/mdk/system_nrf52811.h b/mdk/system_nrf52811.h new file mode 100644 index 000000000..20d87694b --- /dev/null +++ b/mdk/system_nrf52811.h @@ -0,0 +1,61 @@ +/* + +Copyright (c) 2009-2018 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52811_H +#define SYSTEM_NRF52811_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52811_H */ diff --git a/mdk/system_nrf52840.c b/mdk/system_nrf52840.c index 206c7f6be..bd84aa20e 100644 --- a/mdk/system_nrf52840.c +++ b/mdk/system_nrf52840.c @@ -77,7 +77,7 @@ void SystemInit(void) #endif /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_36()){ NRF_CLOCK->EVENTS_DONE = 0; NRF_CLOCK->EVENTS_CTTO = 0; @@ -85,7 +85,7 @@ void SystemInit(void) } /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_66()){ NRF_TEMP->A0 = NRF_FICR->TEMP.A0; NRF_TEMP->A1 = NRF_FICR->TEMP.A1; @@ -107,31 +107,31 @@ void SystemInit(void) } /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_98()){ *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; } /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_103()){ NRF_CCM->MAXPACKETSIZE = 0xFBul; } /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_115()){ *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); } /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_120()){ *(volatile uint32_t *)0x40029640ul = 0x200ul; } /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_136()){ if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index a4f972cde..70e35ecfc 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -44,6 +44,8 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /* Errata are only handled in secure mode since they usually need access to FICR. */ #if !defined(NRF_TRUSTZONE_NONSECURE) + static bool uicr_HFXOSRC_erased(void); + static bool uicr_HFXOCNT_erased(void); static bool errata_6(void); static bool errata_14(void); static bool errata_15(void); @@ -78,8 +80,8 @@ void SystemInit(void) #endif } - /* Make sure UICR->HFXOSRC is set */ - if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + /* Set UICR->HFXOSRC and UICR->HFXOCNT to working defaults if UICR was erased */ + if (uicr_HFXOSRC_erased() || uicr_HFXOCNT_erased()) { /* Wait for pending NVMC operations to finish */ while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); @@ -87,9 +89,17 @@ void SystemInit(void) NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); - /* Write new value to UICR->HFXOSRC */ - NRF_UICR_S->HFXOSRC = (NRF_UICR_S->HFXOSRC & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; - while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + if (uicr_HFXOSRC_erased()){ + /* Write default value to UICR->HFXOSRC */ + NRF_UICR_S->HFXOSRC = (NRF_UICR_S->HFXOSRC & ~UICR_HFXOSRC_HFXOSRC_Msk) | UICR_HFXOSRC_HFXOSRC_TCXO; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } + + if (uicr_HFXOCNT_erased()){ + /* Write default value to UICR->HFXOCNT */ + NRF_UICR_S->HFXOCNT = (NRF_UICR_S->HFXOCNT & ~UICR_HFXOCNT_HFXOCNT_Msk) | 0x20; + while (NRF_NVMC_S->READY != NVMC_READY_READY_Ready); + } /* Enable read mode in NVMC */ NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren; @@ -99,16 +109,22 @@ void SystemInit(void) NVIC_SystemReset(); } + /* Workaround for Errata 6 "POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_6()){ NRF_POWER_S->EVENTS_SLEEPENTER = (POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos); NRF_POWER_S->EVENTS_SLEEPEXIT = (POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos); } + /* Workaround for Errata 14 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_14()){ *(uint32_t *)0x50004A38 = 0x01ul; NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; } + /* Workaround for Errata 15 "REGULATORS: LDO mode at startup" found at the Errata document + for your device located at https://www.nordicsemi.com/DocLib */ if (errata_15()){ *(uint32_t *)0x50004A38 = 0x00ul; NRF_REGULATORS_S->DCDCEN = REGULATORS_DCDCEN_DCDCEN_Enabled << REGULATORS_DCDCEN_DCDCEN_Pos; @@ -133,6 +149,25 @@ void SystemInit(void) #if !defined(NRF_TRUSTZONE_NONSECURE) + + bool uicr_HFXOCNT_erased() + { + if (NRF_UICR_S->HFXOCNT == 0xFFFFFFFFul) { + return true; + } + return false; + } + + + bool uicr_HFXOSRC_erased() + { + if ((NRF_UICR_S->HFXOSRC & UICR_HFXOSRC_HFXOSRC_Msk) != UICR_HFXOSRC_HFXOSRC_TCXO) { + return true; + } + return false; + } + + bool errata_6() { if (*(uint32_t *)0x00FF0130 == 0x9ul){ diff --git a/nrfx.h b/nrfx.h index 1f1f40df8..ae1d51d02 100644 --- a/nrfx.h +++ b/nrfx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_atomic.c b/soc/nrfx_atomic.c index 118386f78..f75800620 100644 --- a/soc/nrfx_atomic.c +++ b/soc/nrfx_atomic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_atomic.h b/soc/nrfx_atomic.h index 5b68a314e..c01d041e6 100644 --- a/soc/nrfx_atomic.h +++ b/soc/nrfx_atomic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_atomic_internal.h b/soc/nrfx_atomic_internal.h index e528e4f39..eedec48bb 100644 --- a/soc/nrfx_atomic_internal.h +++ b/soc/nrfx_atomic_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index b9d093ffe..541646254 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -49,7 +49,7 @@ #elif defined(NRF51) #define NRFX_DELAY_CPU_FREQ_MHZ 16 #define NRFX_DELAY_DWT_PRESENT 0 -#elif defined(NRF52810_XXAA) +#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) #define NRFX_DELAY_CPU_FREQ_MHZ 64 #define NRFX_DELAY_DWT_PRESENT 0 #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) @@ -133,7 +133,7 @@ __STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) 0xd8fd, // BHI .-2 0x4770 // BX LR }; - #elif defined(NRF52810_XXAA) + #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 flash wait states for each instruction. static const uint16_t delay_bytecode[] = { 0x3807, // SUBS r0, #7 diff --git a/soc/nrfx_irqs.h b/soc/nrfx_irqs.h index 9eefb0e1e..09612bcd6 100644 --- a/soc/nrfx_irqs.h +++ b/soc/nrfx_irqs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -36,6 +36,8 @@ #include #elif defined(NRF52810_XXAA) #include +#elif defined(NRF52811_XXAA) + #include #elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) #include #elif defined(NRF52840_XXAA) diff --git a/soc/nrfx_irqs_nrf51.h b/soc/nrfx_irqs_nrf51.h index 3c6aedaab..03ca34d48 100644 --- a/soc/nrfx_irqs_nrf51.h +++ b/soc/nrfx_irqs_nrf51.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_irqs_nrf52810.h b/soc/nrfx_irqs_nrf52810.h index 9ce92e46e..a293d813d 100644 --- a/soc/nrfx_irqs_nrf52810.h +++ b/soc/nrfx_irqs_nrf52810.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -42,23 +42,30 @@ extern "C" { // RADIO_IRQn -// UARTE0_IRQn -#define nrfx_uarte_0_irq_handler UARTE0_IRQHandler +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif -// TWIM0_TWIS0_IRQn +// TWIM0_TWIS0_TWI0_IRQn #if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_IRQHandler +#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler #else -#define nrfx_twim_0_irq_handler TWIM0_TWIS0_IRQHandler -#define nrfx_twis_0_irq_handler TWIM0_TWIS0_IRQHandler +#define nrfx_twim_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler #endif -// SPIM0_SPIS0_IRQn +// SPIM0_SPIS0_SPI0_IRQn #if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) -#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_IRQHandler +#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_SPI0_IRQHandler #else -#define nrfx_spim_0_irq_handler SPIM0_SPIS0_IRQHandler -#define nrfx_spis_0_irq_handler SPIM0_SPIS0_IRQHandler +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler #endif // GPIOTE_IRQn diff --git a/soc/nrfx_irqs_nrf52811.h b/soc/nrfx_irqs_nrf52811.h new file mode 100644 index 000000000..884e6172e --- /dev/null +++ b/soc/nrfx_irqs_nrf52811.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF52811_H__ +#define NRFX_IRQS_NRF52811_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQ +#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#else +#define nrfx_twim_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#define nrfx_twis_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#define nrfx_twi_0_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#define nrfx_spim_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#define nrfx_spis_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#define nrfx_spi_1_irq_handler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler +#endif + +// SPIM0_SPIS0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// COMP_IRQn +#define nrfx_comp_irq_handler COMP_IRQHandler + +// SWI0_EGU0_IRQn +#define nrfx_swi_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_swi_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_IRQn +#define nrfx_swi_2_irq_handler SWI2_IRQHandler + +// SWI3_IRQn +#define nrfx_swi_3_irq_handler SWI3_IRQHandler + +// SWI4_IRQn +#define nrfx_swi_4_irq_handler SWI4_IRQHandler + +// SWI5_IRQn +#define nrfx_swi_5_irq_handler SWI5_IRQHandler + +// PWM0_IRQn +#define nrfx_pwm_0_irq_handler PWM0_IRQHandler + +// PDM_IRQn +#define nrfx_pdm_irq_handler PDM_IRQHandler + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52811_H__ diff --git a/soc/nrfx_irqs_nrf52832.h b/soc/nrfx_irqs_nrf52832.h index 0ad4b68a8..84a8373b6 100644 --- a/soc/nrfx_irqs_nrf52832.h +++ b/soc/nrfx_irqs_nrf52832.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_irqs_nrf52840.h b/soc/nrfx_irqs_nrf52840.h index 37dc39db2..b4030630c 100644 --- a/soc/nrfx_irqs_nrf52840.h +++ b/soc/nrfx_irqs_nrf52840.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/soc/nrfx_irqs_nrf9160.h b/soc/nrfx_irqs_nrf9160.h index c96fa2694..1927add94 100644 --- a/soc/nrfx_irqs_nrf9160.h +++ b/soc/nrfx_irqs_nrf9160.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/templates/nRF52810/nrfx_config.h b/templates/nRF52810/nrfx_config.h index 9490fb0c9..97b00ec96 100644 --- a/templates/nRF52810/nrfx_config.h +++ b/templates/nRF52810/nrfx_config.h @@ -538,19 +538,6 @@ #define NRFX_PRS_BOX_2_ENABLED 1 #endif -// NRFX_PRS_BOX_3_ENABLED - Enables box 3 in the module. - - -#ifndef NRFX_PRS_BOX_3_ENABLED -#define NRFX_PRS_BOX_3_ENABLED 1 -#endif - -// NRFX_PRS_BOX_4_ENABLED - Enables box 4 in the module. - - -#ifndef NRFX_PRS_BOX_4_ENABLED -#define NRFX_PRS_BOX_4_ENABLED 1 -#endif // NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. //========================================================== @@ -1391,6 +1378,97 @@ // +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 1 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 1 +#endif + + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + // NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator //========================================================== #ifndef NRFX_SWI_ENABLED @@ -1861,6 +1939,104 @@ // +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 1 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 1 +#endif + + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + // NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver //========================================================== #ifndef NRFX_UARTE_ENABLED @@ -1982,6 +2158,127 @@ // +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 1 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 1 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + // NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver //========================================================== #ifndef NRFX_WDT_ENABLED diff --git a/templates/nRF52811/nrfx_config.h b/templates/nRF52811/nrfx_config.h new file mode 100644 index 000000000..961785959 --- /dev/null +++ b/templates/nRF52811/nrfx_config.h @@ -0,0 +1,2399 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +// <<< Use Configuration Wizard in Context Menu >>>\n + +// nRF_Drivers + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 1 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support + +#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED +#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 1 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 1 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 1 +#endif +// NRFX_PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE 1 +#endif + +// NRFX_PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE 0 +#endif + +// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 1 +#endif +// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 1 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module +//========================================================== +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 1 +#endif +// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. + + +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 1 +#endif + +// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. + + +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 1 +#endif + +// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. + + +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 1 +#endif + + +// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 1 +#endif +// NRFX_PWM0_ENABLED - Enable PWM0 instance + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 1 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 1 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 1 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 1 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 1 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 1 +#endif + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 1 +#endif +// NRFX_SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION 1 +#endif + +// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE 0 +#endif + +// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 1 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 1 +#endif + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 1 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 1 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 1 +#endif + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 1 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 1 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 1 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 1 +#endif + + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 1 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 1 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver + + +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 1 +#endif + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 1 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 1 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 1 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 1 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 1 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 1 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 1 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 1 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 1 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 1 +#endif + + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 1 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 1 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 1 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 1 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 1 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// + +#endif // NRFX_CONFIG_H__ diff --git a/templates/nrfx_glue.h b/templates/nrfx_glue.h index 891d2b19a..004d61dec 100644 --- a/templates/nrfx_glue.h +++ b/templates/nrfx_glue.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/templates/nrfx_log.h b/templates/nrfx_log.h index d671867c3..a2710bee0 100644 --- a/templates/nrfx_log.h +++ b/templates/nrfx_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA * All rights reserved. * * Redistribution and use in source and binary forms, with or without