diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 000000000000..feb875abd4c0 --- /dev/null +++ b/AUTHORS @@ -0,0 +1,62 @@ +This file contains the names of people who contributed in one way or another to +the development of OPAE. + +Please DO NOT contact the people below directly to report bugs or issues with +OPAE. + +General documentation on OPAE can be found at: + + http://01.org/OPAE + +The OPAE mailing list is available at: + + http://lists.01.org/mailman/listinfo/opae + +The OPAE SDK source code is hosted at: + + http://github.com/OPAE/opae-sdk + +Please use the issue tracker at: + + http://github.com/OPAE/opae-sdk/issues + +to report bugs. + +------------------------------------------------------------------------------- + +The following is a (probably incomplete) list of the much-appreciated +contributors to the OPAE Linux API, library and tools source code. + + Abelardo Jara-Berrocal + Ananda Ravuri + Deepak Unnikrishnan + Dipti Sherlekar + Enno Luebbers + Gabriel Southern + Michael Adler + Omkar Hegde + Rahul Sharma + Robert Lacasse + Rodrigo Rojo + Ru Pan + Shiva Rao + Tim Whisonant + Zhang Zhang + + +Special thanks to the people who contributed to the discussions about OPAE's +software architecture, API, and usage models: + + Aaron Grier + Alan Cox + Brent Thomas + Christopher Rauer + Henry Mitchel + Joe Grecco + Josh Fender + Matthew Gerlach + Sundar Nadathur + + +This list does not cover the contributors to the Intel FPGA driver for Linux - +please refer to the respective driver source files for a list of authors. diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 000000000000..4b0afb359d89 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,283 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +cmake_minimum_required(VERSION 2.8.11) +project(opae) + +############################################################################ +## Add 'versioning' library ################################################ +############################################################################ + +set(INTEL_FPGA_API_VER_MAJOR 0 CACHE STRING "Intel FPGA API major version") +set(INTEL_FPGA_API_VER_MINOR 9 CACHE STRING "Intel FPGA API minor version") +set(INTEL_FPGA_API_VER_REV 0 CACHE STRING "Intel FPGA API revision version") +set(INTEL_FPGA_API_VERSION ${INTEL_FPGA_API_VER_MAJOR}.${INTEL_FPGA_API_VER_MINOR}.${INTEL_FPGA_API_VER_REV}) + +############################################################################ +## Compilation configuration ############################################### +############################################################################ + +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_SOURCE_DIR}/cmake/modules") + +include(compiler_config) +include(libraries_config) +include(fpga_functions) + +############################################################################ +## Target configuration #################################################### +############################################################################ + +# Place all executables and libraries under same directories +set(EXECUTABLE_OUTPUT_PATH ${CMAKE_BINARY_DIR}/bin CACHE PATH "Build directory" FORCE) +set(LIBRARY_OUTPUT_PATH ${CMAKE_BINARY_DIR}/lib CACHE PATH "Build directory" FORCE) + +############################################################################ +## Compilation configuration ############################################### +############################################################################ + +set(COMMON_DIR ${CMAKE_SOURCE_DIR}/common) +set(OPAE_INCLUDE_DIR ${COMMON_DIR}/include) +add_custom_target(copy-common-opae-header-files ALL + COMMAND cmake -E copy_directory ${OPAE_INCLUDE_DIR} ${CMAKE_BINARY_DIR}/include) + +# Install common header files +install(DIRECTORY common/include/opae + DESTINATION include + COMPONENT libopaeheaders) + +############################################################################ +## Sub-projects ############################################################ +############################################################################ + +add_subdirectory(safe_string) + +option(BUILD_LIBOPAE_C "Enable building of libopae-c. This is the default OPAE API implementation." ON) +mark_as_advanced(BUILD_LIBOPAE_C) +if(BUILD_LIBOPAE_C) + add_subdirectory(libopae) +endif() + +add_subdirectory(tools/userclk) +add_subdirectory(tools/fpgad) +add_subdirectory(tools/mmlink) +add_subdirectory(tools/fpgaconf) +add_subdirectory(tools/fpgainfo) +add_subdirectory(tools/c++utils) +add_subdirectory(tools/libopae++) +add_subdirectory(tools/fpgadiag) + +option(BUILD_ASE "Enable ASE compilation" OFF) +mark_as_advanced(BUILD_ASE) +if(BUILD_ASE) + add_subdirectory(ase/api) + add_subdirectory(ase) +endif() + +if (NOT BUILD_ASE AND NOT BUILD_LIBOPAE_C) + message(FATAL_ERROR "Not building any OPAE libraries") +endif() + +find_package(Threads REQUIRED) + +############################################################################ +## Add 'samples' ################################################### +############################################################################ +add_subdirectory(samples) + +############################################################################ +## RPATH Handling ########################################################## +############################################################################ +set(CMAKE_SKIP_BUILD_RPATH FALSE) +set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) +set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") +set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) + + +############################################################################ +## Packaging ############################################################### +############################################################################ + +option(HASH_ARCHIVES "Add git commit hash to archive names" OFF) +mark_as_advanced(HASH_ARCHIVES) + +find_program(GIT_EXECUTABLE git) +if(EXISTS ${GIT_EXECUTABLE}) + execute_process(COMMAND ${GIT_EXECUTABLE} log -1 --format=%h + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} + OUTPUT_VARIABLE GIT_COMMIT_HASH + OUTPUT_STRIP_TRAILING_WHITESPACE) +else(EXISTS ${GIT_EXECUTABLE}) + set(GIT_COMMIT_HASH unknown) +endif(EXISTS ${GIT_EXECUTABLE}) + +set(CPACK_COMPONENT_OPAECLIB_GROUP "libs") + +set(CPACK_COMPONENT_LIBOPAEHEADERS_GROUP "devel") +set(CPACK_COMPONENT_DOCHTML_GROUP "devel") +set(CPACK_COMPONENT_DOCLATEX_GROUP "devel") +set(CPACK_COMPONENT_DOCRTF_GROUP "devel") +set(CPACK_COMPONENT_DOCMAN_GROUP "devel") +set(CPACK_COMPONENT_DOCXML_GROUP "devel") +set(CPACK_COMPONENT_SAMPLESRC_GROUP "devel") + +set(CPACK_COMPONENT_TOOLUSERCLK_GROUP "tools") +set(CPACK_COMPONENT_TOOLFPGAD_GROUP "tools") +set(CPACK_COMPONENT_TOOLRAS_GROUP "tools") +set(CPACK_COMPONENT_TOOLMMLINK_GROUP "tools") +set(CPACK_COMPONENT_TOOLCOREIDLE_GROUP "tools") +set(CPACK_COMPONENT_TOOLFPGACONF_GROUP "tools") +set(CPACK_COMPONENT_TOOLFPGADIAG_GROUP "tools") +set(CPACK_COMPONENT_TOOLFPGADIAGAPPS_GROUP "tools") +set(CPACK_COMPONENT_TOOLFPGAINFO_GROUP "tools") +set(CPACK_COMPONENT_OPAECXXUTILS_GROUP "tools") +set(CPACK_COMPONENT_OPAECXXLIB_GROUP "tools") +set(CPACK_COMPONENT_OPAECXXNLB_GROUP "tools") + +set(CPACK_COMPONENT_OPAECASE_GROUP "ase") +set(CPACK_COMPONENT_ASERTL_GROUP "ase") +set(CPACK_COMPONENT_ASESW_GROUP "ase") +set(CPACK_COMPONENT_ASESCRIPTS_GROUP "ase") +set(CPACK_COMPONENT_ASESAMPLECONFIG_GROUP "ase") +set(CPACK_COMPONENT_ASEEXTRA_GROUP "ase") + +set(CPACK_COMPONENT_GROUP_LIBS_DESCRIPTION + "libopae-c") +set(CPACK_COMPONENT_GROUP_DEVEL_DESCRIPTION + "OPAE headers, sample source, and documentation") +set(CPACK_COMPONENT_GROUP_TOOLS_DESCRIPTION + "OPAE tool binaries") +set(CPACK_COMPONENT_GROUP_ASE_DESCRIPTION + "OPAE AFU Simulation Environment") +set(CPACK_COMPONENT_GROUP_ALL_DESCRIPTION + "OPAE meta package") + +set(CPACK_COMPONENT_GROUP_DEVEL_DEPENDS libs) +set(CPACK_COMPONENT_GROUP_TOOLS_DEPENDS libs) +set(CPACK_COMPONENT_GROUP_ASE_DEPENDS devel) +set(CPACK_COMPONENT_GROUP_ALL_DEPENDS devel tools ase) + +set(CPACK_COMPONENTS_GROUPING ONE_PER_GROUP) +set(CPACK_COMPONENT_GROUPS_ALL libs devel tools ase all) + +SET(CPACK_PACKAGE_DESCRIPTION_SUMMARY "Open Programmable Acceleration Engine") +SET(CPACK_PACKAGE_VENDOR "Intel Corporation") +set(CPACK_PACKAGE_VERSION_MAJOR "${INTEL_FPGA_API_VER_MAJOR}") +set(CPACK_PACKAGE_VERSION_MINOR "${INTEL_FPGA_API_VER_MINOR}") +set(CPACK_PACKAGE_VERSION_PATCH "${INTEL_FPGA_API_VER_REV}") +set(CPACK_PACKAGE_RELEASE 1) + +if (HASH_ARCHIVES) + set(CPACK_RPM_LIBS_FILE_NAME "${CMAKE_PROJECT_NAME}-libs-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64_git${GIT_COMMIT_HASH}.rpm") + set(CPACK_RPM_DEVEL_FILE_NAME "${CMAKE_PROJECT_NAME}-devel-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64_git${GIT_COMMIT_HASH}.rpm") + set(CPACK_RPM_TOOLS_FILE_NAME "${CMAKE_PROJECT_NAME}-tools-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64_git${GIT_COMMIT_HASH}.rpm") + set(CPACK_RPM_ASE_FILE_NAME "${CMAKE_PROJECT_NAME}-ase-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64_git${GIT_COMMIT_HASH}.rpm") +else(HASH_ARCHIVES) + set(CPACK_RPM_LIBS_FILE_NAME "${CMAKE_PROJECT_NAME}-libs-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64.rpm") + set(CPACK_RPM_DEVEL_FILE_NAME "${CMAKE_PROJECT_NAME}-devel-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64.rpm") + set(CPACK_RPM_TOOLS_FILE_NAME "${CMAKE_PROJECT_NAME}-tools-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64.rpm") + set(CPACK_RPM_ASE_FILE_NAME "${CMAKE_PROJECT_NAME}-ase-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}-${CPACK_PACKAGE_RELEASE}.x86_64.rpm") +endif(HASH_ARCHIVES) + +# Source code packaging target +set(CPACK_SOURCE_GENERATOR "TGZ") +if (HASH_ARCHIVES) + set(CPACK_SOURCE_PACKAGE_FILE_NAME + "${CMAKE_PROJECT_NAME}-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}_git${GIT_COMMIT_HASH}") + set(DEFINE_RPM_NAME "%define _rpmfilename %%{ARCH}/%%{NAME}-%%{VERSION}-%%{RELEASE}_git${GIT_COMMIT_HASH}.%%{ARCH}.rpm") +else(HASH_ARCHIVES) + set(CPACK_SOURCE_PACKAGE_FILE_NAME + "${CMAKE_PROJECT_NAME}-${CPACK_PACKAGE_VERSION_MAJOR}.${CPACK_PACKAGE_VERSION_MINOR}.${CPACK_PACKAGE_VERSION_PATCH}") + set(DEFINE_RPM_NAME "") +endif(HASH_ARCHIVES) + +set(CPACK_SOURCE_IGNORE_FILES + "coverage.cmake" + "/mybuild/" + "/build/" + "/.git" + "~$" + ${CPACK_SOURCE_IGNORE_FILES}) + +# Binary packaging target +set(CPACK_PACKAGE_CONTACT "opae@lists.01.org") +set(CPACK_RPM_COMPONENT_INSTALL ON) +set(CPACK_DEB_COMPONENT_INSTALL ON) +set(CPACK_RPM_PACKAGE_COMPONENT ON) +set(CPACK_PACKAGE_VERSION ${INTEL_FPGA_API_VERSION}) +set(CPACK_GENERATOR "RPM") +set(CPACK_PACKAGE_NAME ${CMAKE_PROJECT_NAME}) +set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${CPACK_PACKAGE_VERSION}-${CPACK_PACKAGE_RELEASE}.${CMAKE_SYSTEM_PROCESSOR}") +set(CPACK_RPM_PACKAGE_REQUIRES "libuuid, libuuid-devel") + +# /usr, /usr/lib are already present in CPACK_RPM_EXCLUDE_FROM_AUTO_FILELIST, +# but some Linux distributions complain without this explicit suppression +set(CPACK_RPM_SPEC_MORE_DEFINE "%define ignore \#") +set(CPACK_RPM_USER_FILELIST + "%ignore /" + "%ignore /usr" + "%ignore /usr/bin" + "%ignore /usr/lib" + "%ignore /usr/share" + "%ignore /usr/include" + "%ignore /usr/src" + "%ignore /usr/doc") +set(CPACK_RPM_EXCLUDE_FROM_AUTO_FILELIST + "/" + "/usr" + "/usr/bin" + "/usr/lib" + "/usr/share" + "/usr/include" + "/usr/src" + "/usr/doc") + +include(CPack) +add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) + +############################################################################ +## Meta Package RPM ######################################################## +############################################################################ +set(PACKAGE_PACKAGER_NAME "The OPAE Development Team") +set(PACKAGE_PACKAGER_EMAIL ${CPACK_PACKAGE_CONTACT}) +set(MODULE_NAME libopae-all) +set(PACKAGE_NAME opae-all) +set(PACKAGE_VERSION ${CPACK_PACKAGE_VERSION}) +set(PACKAGE_SUMMARY "OPAE meta-package") +set(PACKAGE_DESCRIPTION "OPAE meta-package") +set(PACKAGE_VENDOR "Intel Corporation") +set(PACKAGE_URL http://www.intel.com) +set(PACKAGE_SRC_TAR_NAME ${CPACK_SOURCE_PACKAGE_FILE_NAME}) + +set(CONFIG_TEMPLATE_PATH "${CMAKE_SOURCE_DIR}/cmake/config") +configure_file(${CONFIG_TEMPLATE_PATH}/libopae-all.spec.in + ${CMAKE_CURRENT_BINARY_DIR}/libopae-all.spec @ONLY) + +find_program(RPMBUILD_EXECUTABLE rpmbuild) +if(EXISTS ${RPMBUILD_EXECUTABLE}) + add_custom_target(metarpm + COMMAND ${RPMBUILD_EXECUTABLE} -bb libopae-all.spec + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) +endif(EXISTS ${RPMBUILD_EXECUTABLE}) diff --git a/COPYING b/COPYING new file mode 100644 index 000000000000..fca8ab6c2eed --- /dev/null +++ b/COPYING @@ -0,0 +1,68 @@ +If not otherwise noted in the individual file header, the OPAE SDK source code, +located in the directories + + * ase, + * cmake, + * common/include/opae, + * doc, + * libopae, + * samples, and + * tools, + +is distributed under the following license: + + Copyright(c) 2017, Intel Corporation + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Intel Corporation nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + +This repository also contains a copy of the safe_string library in the +directories + + * common/include/safe_string and + * safe_string, + +which is distributed under the following license: + + Permission is hereby granted, free of charge, to any person + obtaining a copy of this software and associated documentation + files (the "Software"), to deal in the Software without + restriction, including without limitation the rights to use, + copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following + conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + OTHER DEALINGS IN THE SOFTWARE. \ No newline at end of file diff --git a/README b/README new file mode 100644 index 000000000000..1ccfc459e2e6 --- /dev/null +++ b/README @@ -0,0 +1,18 @@ +Welcome to the OPAE SDK source code repository +============================================== + +OPAE is the Open Programmable Acceleration Engine, a software framework for +managing and accessing programmable accelerators (FPGAs). + +The OPAE SDK is a collection of libraries and tools to facilitate the +development of software applications and accelerators using OPAE. + +General documentation on OPAE can be found at . + +The OPAE mailing list is available at +. + +The OPAE SDK source code is hosted at . + +Please use the issue tracker at to +report bugs. diff --git a/RELEASE_NOTES b/RELEASE_NOTES new file mode 100644 index 000000000000..553630dea84c --- /dev/null +++ b/RELEASE_NOTES @@ -0,0 +1,75 @@ +Open Programmable Acceleration Engine (OPAE) 0.9.0 Release Notes +================================================================ + +This document provides the Release Notes for the Open Programmable Acceleration +Engine (OPAE) 0.9.0 release. + + +System Compatibility +-------------------- + +* Hardware: tightly coupled FPGA products and programmable FPGA acceleration + cards for Intel(R) Xeon(R) processors (to be released) +* Operating System: tested on RedHat 7.3, Linux kernels 3.10 through 4.7 +* FIM (FPGA Interface Manager): 6.3.0 + + +Known Issues +------------ + +* Partial reconfiguration with SR-IOV + + If using OPAE in a virtualized environment with SR-IOV enabled, we recommend + disabling SR-IOV before performing partial reconfiguration. See "Partial + Reconfiguration" in the "OPAE Intel FPGA Linux Device Driver Architecture" + document for more information + + +* fpgaAssignToInterface() and fpgaReleaseFromInterface() not supported + + The OPAE C API provides functions to assign individual AFCs to host interfaces + (i.e. a virtual or physical function). Due to the internal implementation of + fpga_token, these functions are not yet supported. Instead, we provide a + simplified call fpgaAssignPortToInterface() that can assign a port by number + to either the physical function (PF) or virtual function (VF). This function + will eventually be replaced by the more generic implementation of + fpgaAssignToInterface() and fpgaReleaseFromInterface() in a future release. + + +* UMsgs are not supported on BBS 6.3.0 + + The 6.3.0 blue bitstream for the Xeon Processor with Integrated FPGA exposes + UMsg functionality, but does not fully support it. We recommend not using UMsg + functionality with a 6.3.0 bitstream, although software will report is as + being supported. + + +* Driver RPM uninstallation does not clean up initrd on CentOS + + When removing the driver RPM on CentOS, the package may leave the compiled + FPGA driver modules in initrd. + + +* Allocation of multiple 1 GiB buffers on VT-d-enabled system may sporadially + fail + + In certain configurations, allocating multiple 1 GiB huge pages on a + non-virtualized system with VT-d turned on and an activated IOMMU may result + in system instability. As an alternative, try disabling VT-d or the IOMMU, or + running in a virtual machine. + + +* Virtualized applications with frequent MMIO accesses may sporadically fail + + In certain configuration, high-frequency MMIO accesses from a virtual machine + with a passed-through virtual function (VF) may trigger system instability. + + +* Parallel partial reconfiguration on multiple FPGAs using fpgaconf may fail + + When programing multiple FPGAs concurrently using the 'fpgaconf' tool, single + configurations may fail with the message "device enumeration failed". This is + due to a collision of enumeration with a partial reconfiguration process, and + is a recoverable error; either clear the PORT errors of the respective FPGA, + or to attempt another reconfiguration using 'fpgaconf'. + diff --git a/ase/CMakeLists.txt b/ase/CMakeLists.txt new file mode 100644 index 000000000000..db16c6a1d803 --- /dev/null +++ b/ase/CMakeLists.txt @@ -0,0 +1,39 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +install(DIRECTORY rtl DESTINATION share/opae/ase COMPONENT asertl) +install(DIRECTORY sw DESTINATION share/opae/ase COMPONENT asesw) +install(DIRECTORY scripts DESTINATION share/opae/ase COMPONENT asescripts) +install(DIRECTORY sample_config DESTINATION share/opae/ase COMPONENT asesampleconfig) + +set(EXTRA_ASE_FILES + Makefile + ase.cfg + ase_regress.sh) + +install(FILES ${EXTRA_ASE_FILES} + DESTINATION share/opae/ase + COMPONENT aseextra) diff --git a/ase/Makefile b/ase/Makefile new file mode 100644 index 000000000000..5cfc0667264e --- /dev/null +++ b/ase/Makefile @@ -0,0 +1,512 @@ +# ############################################################################# +# Copyright(c) 2011-2016, Intel Corporation +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# * Neither the name of Intel Corporation nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# ############################################################################# +# +# Module Info: +# Language : System{Verilog} | C/C++ +# Owner : Rahul R Sharma +# rahul.r.sharma@intel.com +# Intel Corporation +# +# ASE environment build - Makefile +# +######################################################################### +# Provides a template for compiling ASE with RTL CAFU sources in VCS +# and Questasim +# For a full experience, roll your own Makefile +# +########################################################################## + +include ase_sources.mk + +############################################################### +## ## +## ASE Platform value (selection method) ## +## ## +## * FPGA_PLATFORM_INTG_XEON: ## +## Sets ASE to emulate one socket of Integrated ## +## platform ## +## * FPGA_PLATFORM_DISCRETE: ## +## Sets ASE to emulate a discrete PCIe attached FPGA ## +## ## +## Operation: ## +## - FPGA_PLATFORM_INTG_XEON or FPGA_PLATFORM_DISCRETE ## +## selection drives compiler macros to the individual SV ## +## and C components ## +## - ASE_PLATFORM will be used as the differentiating macro ## +## during the compilation stage ## +## - This methos allows for newer platforms to be added as ## +## ASE_PLATFORM, reduces accidental settings failure ## +## ## +############################################################### +ASE_PLATFORM?=FPGA_PLATFORM_INTG_XEON + +############################################################### +# ASE switches (disabling logger and checker may speed up # +# simulation in assumption that protocol errors don't exist # +# in design # +############################################################### +ASE_DISABLE_LOGGER ?= 0 +ASE_DISABLE_CHECKER ?= 0 + +######################################################################### +# Enable Altera gates library in ASE # +######################################################################### +# Enable Altera Gates +GLS_SIM = 1 + +# ASE GLS_SIM path check test +GLS_SAMPLE_LIB = $(QUARTUS_HOME)/eda/sim_lib/altera_primitives.v + +# Gate level libraries to add to simulation +GLS_VERILOG_OPT = $(QUARTUS_HOME)/eda/sim_lib/altera_primitives.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/220model.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/sgate.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/altera_mf.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/stratixv_hssi_atoms.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/stratixv_pcie_hip_atoms.v +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/altera_lnsim.sv + +# add required files for local memory model +ifeq ($(ASE_PLATFORM), FPGA_PLATFORM_DISCRETE) +GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/twentynm_atoms.v +ifeq ($(SIMULATOR), VCS) + GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/synopsys/twentynm_atoms_ncrypt.v +endif +ifeq ($(SIMULATOR), QUESTA) + GLS_VERILOG_OPT+= $(QUARTUS_HOME)/eda/sim_lib/mentor/twentynm_atoms_ncrypt.v +endif +endif + +######################################################################### +# ASE location settings # +######################################################################### +# Work directory +WORK = work + +# ASE Source directory +ASE_SRCDIR = $(shell pwd) +OPAE_BASEDIR ?= $(ASE_SRCDIR)/../ +ASE_WORKDIR = $(PWD)/$(WORK) + +# Configuration & regression file inputs +ASE_CONFIG ?= $(PWD)/ase.cfg +ASE_SCRIPT ?= $(PWD)/ase_regress.sh + +# Configuration for discrete Memory Model +ASE_MEM_SRC = $(ASE_SRCDIR)/rtl/device_models/dcp_emif_model + +######################################################################### +# ASE HW/SW settings # +######################################################################## +## Timescale +TIMESCALE = 1ps/1ps + +## ASE HW file setup +ASEHW_FILE_LIST = -F $(ASE_SRCDIR)/rtl/sources.txt + +## ASE platform-specific HW +ASE_PLATFORM_FILE_LIST ?= +ifeq ($(ASE_PLATFORM), FPGA_PLATFORM_DISCRETE) + ASE_PLATFORM_FILE_LIST += -F $(ASE_MEM_SRC)/sources.txt +endif + +## ASE SW file setup +ASESW_FILE_LIST = \ + $(ASE_SRCDIR)/sw/ase_ops.c \ + $(ASE_SRCDIR)/sw/ipc_mgmt_ops.c \ + $(ASE_SRCDIR)/sw/mem_model.c \ + $(ASE_SRCDIR)/sw/protocol_backend.c \ + $(ASE_SRCDIR)/sw/tstamp_ops.c \ + $(ASE_SRCDIR)/sw/mqueue_ops.c \ + $(ASE_SRCDIR)/sw/error_report.c \ + $(ASE_SRCDIR)/sw/linked_list_ops.c \ + $(ASE_SRCDIR)/sw/randomness_control.c \ + +## Safe string sources +SAFESTR_SRC_LIST = $(wildcard ${OPAE_BASEDIR}/safe_string/*.c) + +## ASE top level module +ASE_TOP = ase_top + +######################################################################### +# Build options # +######################################################################### +## Choice of VCS or QUESTA ## +SIMULATOR?=VCS +CC=gcc + +## RTL command +SNPS_COMMAND = $(shell command -v vcs) +MENT_COMMAND = $(shell command -v vsim) + +## GCC version +GCC_VERSION_GT_49 = $(shell gcc -dumpversion | gawk '{print $$1>=4.9?"1":"0"}') + +## For ModelSim figure out whether it is the 32 bit starter edition +CC_INT_SIZE=-m64 +ifeq ($(SIMULATOR), QUESTA) + ifdef MENT_COMMAND + MENT_VERSION=$(shell vsim -version) + ifneq (,$(findstring STARTER EDITION, $(MENT_VERSION))) + CC_INT_SIZE=-m32 + endif + endif +endif + +## C Compiler options +CC_OPT?= +CC_OPT+= -g $(CC_INT_SIZE) -fPIC -D SIM_SIDE=1 -I $(ASE_SRCDIR)/sw/ -I $(OPAE_BASEDIR)/common/include/ +CC_OPT+= -D SIMULATOR=$(SIMULATOR) -D $(ASE_PLATFORM) +CC_OPT+= -Wall -Wformat -Wformat-security +CC_OPT+= -O2 -D_FORTIFY_SOURCE=2 +ifeq ($(GCC_VERSION_GT_49),1) + CC_OPT+= -fstack-protector-strong + CC_OPT+= -z noexecstack -z relro -z now +else + CC_OPT+= -fstack-protector-all +endif +## CC_OPT, simulator specific include paths +ifeq ($(SIMULATOR), VCS) + CC_OPT+= -I $(VCS_HOME)/include/ +endif +ifeq ($(SIMULATOR), QUESTA) + CC_OPT+= -I $(MTI_HOME)/include/ +endif + +## Print information ## + $(info SIMULATOR=$(SIMULATOR)) + $(info CC=$(CC)) + +## ASE Link options +ASE_LD_SWITCHES?= +ASE_LD_SWITCHES+= -lrt -lpthread + +## Library names +ASE_SHOBJ_NAME = ase_libs +ASE_SHOBJ_SO = $(ASE_SHOBJ_NAME).so + +######################################################################### +# VCS Build Switches # +######################################################################### +## VHDL compile +SNPS_VHDLAN_OPT?= +SNPS_VHDLAN_OPT+= -nc -verbose -full64 +SNPS_VHDLAN_OPT+= -work $(WORK) + +## Verilog compile +SNPS_VLOGAN_OPT?= +SNPS_VLOGAN_OPT+= -nc -V -full64 +v2k -sverilog +define+$(SIMULATOR) +SNPS_VLOGAN_OPT+= +incdir+$(DUT_INCDIR) +SNPS_VLOGAN_OPT+= +librescan -work $(WORK) -override_timescale=$(TIMESCALE) +SNPS_VLOGAN_OPT+= +define+$(ASE_PLATFORM) +SNPS_VLOGAN_OPT+= +lint=all,noVCDE,noNS,NCEID,CAWM,TFIPC,IPDP,PCWM +ifeq ($(ASE_DISABLE_LOGGER), 1) + SNPS_VLOGAN_OPT+= +define+ASE_DISABLE_LOGGER=1 +endif +ifeq ($(ASE_DISABLE_CHECKER), 1) + SNPS_VLOGAN_OPT+= +define+ASE_DISABLE_CHECKER=1 +endif +ifeq ($(GLS_SIM), 1) + SNPS_VLOGAN_OPT+= $(GLS_VERILOG_OPT) +endif + +## VCS elaboration +SNPS_VCS_OPT?= +SNPS_VCS_OPT+= -nc -V +vcs+lic+wait -full64 -debug_pp -Mupdate -lca +SNPS_VCS_OPT+= -j 4 +SNPS_VCS_OPT+= -l vcs_elab.log +vhdllib+$(WORK) -Mlib=$(WORK) +lint=TFIPC-L +SNPS_VCS_OPT+= -override_timescale=$(TIMESCALE) -o $(WORK)/ase_simv +# SNPS_VCS_OPT+= -LDFLAGS="-m64" # !!! DO NOT EDIT !!! + +## Simulation options +SNPS_SIM_OPT+= -ucli -do $(PWD)/vcs_run.tcl +# SNPS_SIM_OPT+= -l run.log +SNPS_SIM_OPT+= +ntb_random_seed=1234 + + +######################################################################### +# Questa Build Switches # +######################################################################### +## VHDL compile +MENT_VCOM_OPT?= +MENT_VCOM_OPT+= -nologo -work $(WORK) + +## VLOG compile +# MENT_VLOG_OPT = -64 +MENT_VLOG_OPT?= +MENT_VLOG_OPT+= -nologo +librescan -work $(WORK) +define+$(SIMULATOR) -novopt +MENT_VLOG_OPT+= -dpiheader work/dpiheader.h +incdir+$(DUT_INCDIR)+$(WORK) +MENT_VLOG_OPT+= -sv -timescale $(TIMESCALE) -l vlog.log +MENT_VLOG_OPT+= +define+$(ASE_PLATFORM) +ifeq ($(GLS_SIM), 1) + MENT_VLOG_OPT+= $(GLS_VERILOG_OPT) +endif + +## VSIM elaboration, and run options +# MENT_VSIM_OPT = -64 +MENT_VSIM_OPT?= +MENT_VSIM_OPT+= -c -l run.log -dpioutoftheblue 1 -novopt +MENT_VSIM_OPT+= -sv_lib $(ASE_SHOBJ_NAME) -do $(PWD)/vsim_run.tcl +MENT_VSIM_OPT+= -sv_seed 1234 +# -voptargs="+acc" + + +######################################################################### +# Build Targets # +######################################################################### +# Default +all: check build + +# Check +check: header +# Check that only INTG_XEON or DISCRETE is selected, not both or neither +ifeq ($(ASE_PLATFORM), FPGA_PLATFORM_INTG_XEON) + @echo "ASE platform set to INTG_XEON mode" +else + ifeq ($(ASE_PLATFORM), FPGA_PLATFORM_DISCRETE) + @echo "ASE platform set to DISCRETE mode" + else + @echo "ASE platform set to '$(ASE_PLATFORM)' -- this is an illegal value" + @echo " Valid values - {FPGA_PLATFORM_INTG_XEON, FPGA_PLATFORM_DISCRETE}" + exit 1 + endif +endif +# Ensure GCC is available +ifneq ($(CC), gcc) + @echo "# #" + @echo "# CC=$(CC) not supported #" + @echo "# Run 'make help' for more information #" + @echo "# #" + @echo "############################################################" + exit 1 +endif +# Echo simulator setting +ifneq ($(SIMULATOR), VCS) + ifneq ($(SIMULATOR), QUESTA) + @echo "# #" + @echo "# SIMULATOR=$(SIMULATOR) not supported #" + @echo "# Run 'make help' for more information #" + @echo "# #" + @echo "############################################################" + exit 1 + endif +endif +# Check gate simulation libraries +ifeq ($(GLS_SIM), 1) + ifndef QUARTUS_HOME + @echo "** ERROR **: env(QUARTUS_HOME) has not been set." + @echo "** ERROR **: GLS_SIM needs QUARTUS_HOME environment variable to be set." + ifdef QUARTUS_ROOT + @echo "** ERROR **: env(QUARTUS_ROOT) is set up. Please set env(QUARTUS_HOME) to same location." + @echo "** ERROR **: This makefile references libraries based on env(QUARTUS_HOME)." + endif + else + ifeq ($(wildcard $(GLS_SAMPLE_LIB)),) + @echo "** ERROR **: env(QUARTUS_HOME) not set up correctly." + @echo "** ERROR **: Cannot find Quartus library files in known locations" + endif + endif +endif +# Check if some RTL simulator exists +ifeq ($(SIMULATOR), VCS) + ifndef VCS_HOME + @echo "**ERROR** : env(VCS_HOME) is not set ! svdpi.h cannot be found !" + endif + ifndef SNPS_COMMAND + @echo "**ERROR** : Synopsys commands (vlogan, vcs) not found !" + endif +else + ifeq ($(SIMULATOR), QUESTA) + ifndef MTI_HOME + @echo "**ERROR** : env(MTI_HOME) is not set ! svdpi.h cannot be found !" + endif + ifndef MENT_COMMAND + @echo "**ERROR** : Modelsim commands (vlog, vsim) not found !" + endif + else + @echo "**ERROR**: Unknown RTL simulator tool in use --- this is unsupported !" + endif +endif + +# Print version number +header: + @echo "#################################################################" + @echo "# #" + @echo "# OPAE Intel(R) Xeon(R) + FPGA Library #" + @echo "# AFU Simulation Environment (ASE) #" + @echo "# #" + @echo "#################################################################" + +# Help information +help: header + @echo "# | #" + @echo "# COMMAND | DESCRIPTION #" + @echo "# --------------------|---------------------------------------- #" + @echo "# make | Build the HW Model using RTL supplied #" + @echo "# | #" + @echo "# make sim | Run simulator #" + @echo "# | - ASE can be run in one of 4 modes set #" + @echo "# | in ase.cfg #" + @echo "# | - A regression mode can be enabled by #" + @echo "# | writing ASE_MODE = 4 in ase.cfg and #" + @echo "# | supplying an ase_regress.sh script #" + @echo "# | #" + @echo "# make wave | Open the waveform (if created) #" + @echo "# | To be run after simulation completes #" + @echo "# | #" + @echo "# make clean | Clean simulation files #" + @echo "# | #" + @echo "# make distclean | Clean ASE sub-distribution #" + @echo "# | #" + @echo "# ====================|======================================== #" + @echo "# Makefile switch | DESCRIPTION #" + @echo "# --------------------|---------------------------------------- #" + @echo "# ASE_CONFIG | Directly input an ASE configuration #" + @echo "# | file path (ase.cfg) #" + @echo "# | #" + @echo "# ASE_SCRIPT | Directly input an ASE regression file #" + @echo "# | path (ase_regress.sh, for ASE_MODE=4) #" + @echo "# | #" + @echo "# SIMULATOR | Directly input a simulator brand #" + @echo "# | (select between 'VCS' or 'QUESTA') #" + @echo "# | #" + @echo "# ASE_DISABLE_CHECKER | Disable CCI-P protocol checker module #" + @echo "# | (set to '1' might speed up simulation) #" + @echo "# | **WARNING** => NO warnings on hazards, #" + @echo "# | protocol checks, timeouts will be #" + @echo "# | generated. This option must be ONLY #" + @echo "# | used if the design is already CCI-P #" + @echo "# | compliant and fast simulation of #" + @echo "# | app-specific logic is needed #" + @echo "# | #" + @echo "#################################################################" + +## Build ASE Software objects and shared library ## +sw_build: + make header + mkdir -p $(WORK) + cd $(WORK) ; $(CC) $(CC_OPT) -c $(SAFESTR_SRC_LIST) || exit 1 ; cd - + cd $(WORK) ; $(CC) $(CC_OPT) -c $(ASESW_FILE_LIST) || exit 1 ; cd - + cd $(WORK) ; $(CC) $(CC_INT_SIZE) -g -shared -o $(ASE_SHOBJ_SO) `ls *.o` $(ASE_LD_SWITCHES) ; cd - + nm $(WORK)/$(ASE_SHOBJ_SO) > $(WORK)/$(ASE_SHOBJ_NAME).nm + +## VCS build template ## +vcs_build: sw_build + @echo "############################################################" + @echo "# #" + @echo "# VCS-GCC build initiated #" + @echo "# #" + @echo "############################################################" +ifeq ($(ASE_PLATFORM), FPGA_PLATFORM_DISCRETE) + cp -f $(ASE_MEM_SRC)/*.hex $(ASE_WORKDIR) + vlogan $(SNPS_VLOGAN_OPT) $(ASEHW_FILE_LIST) $(ASE_PLATFORM_FILE_LIST) -l vlogan-ase.log +else + vlogan $(SNPS_VLOGAN_OPT) $(ASEHW_FILE_LIST) -l vlogan-ase.log +endif + +ifdef DUT_VHD_SRC_LIST + vhdlan $(SNPS_VHDLAN_OPT) -F $(DUT_VHD_SRC_LIST) +endif +ifdef DUT_VLOG_SRC_LIST + vlogan $(SNPS_VLOGAN_OPT) -F $(DUT_VLOG_SRC_LIST) -l vlogan-afu.log +endif +ifeq ($(CC), gcc) + vcs $(SNPS_VCS_OPT) $(ASE_TOP) $(WORK)/$(ASE_SHOBJ_SO) $(ASE_LD_SWITCHES) +endif + +## Questasim template ## +questa_build: sw_build + @echo "############################################################" + @echo "# #" + @echo "# QuestaSim-GCC build initiated #" + @echo "# #" + @echo "############################################################" + cd $(WORK) ; vlib $(WORK) ; vmap work $(WORK) ; cd - + cp -f $(ASE_MEM_SRC)/*.hex $(ASE_WORKDIR) + cd $(WORK) ; vlog $(MENT_VLOG_OPT) $(ASEHW_FILE_LIST) $(ASE_PLATFORM_FILE_LIST) -l vlog-ase.log ; cd - +ifdef DUT_VHD_SRC_LIST + cd $(WORK) ; vcom $(MENT_VCOM_OPT) -F $(DUT_VHD_SRC_LIST) -l vcom-afu.log ; cd - +endif +ifdef DUT_VLOG_SRC_LIST + cd $(WORK) ; vlog $(MENT_VLOG_OPT) -F $(DUT_VLOG_SRC_LIST) -l vlog-afu.log ; cd - +endif + +## Build Simulator objects ## +build: +ifeq ($(SIMULATOR), VCS) + make vcs_build +else + ifeq ($(SIMULATOR), QUESTA) + make questa_build + else + @echo "############################################################" + @echo "# SIMULATOR=$(SIMULATOR) not supported #" + @echo "############################################################" + endif +endif + +## Run ASE Simulator ## +sim: check +ifeq ($(SIMULATOR), VCS) + cd $(ASE_WORKDIR) ; ./ase_simv $(SNPS_SIM_OPT) +CONFIG=$(ASE_CONFIG) +SCRIPT=$(ASE_SCRIPT) ; cd - +else + ifeq ($(SIMULATOR), QUESTA) + cd $(ASE_WORKDIR) ; vsim $(MENT_VSIM_OPT) +CONFIG=$(ASE_CONFIG) +SCRIPT=$(ASE_SCRIPT) $(ASE_TOP) ; cd - + else + @echo "############################################################" + @echo "# SIMULATOR=$(SIMULATOR) not supported #" + @echo "############################################################" + endif +endif + +# Open Wave file +wave: check +ifeq ($(SIMULATOR), VCS) + dve -vpd `find . -name inter.vpd` || dve -vpd `find . -name inter.vpd` -full64 +else + ifeq ($(SIMULATOR), QUESTA) + vsim -view `find . -name vsim.wlf` + endif +endif + + +######################################################################### +# Clean all # +######################################################################### +clean: header + rm -rf work/ *.log *.tsv AN.DB/ || echo "make: Didn't clean up work" + rm -rf csrc/ vc_hdrs.h .vlogansetup.* *.vpd app_build/ + rm -rf transcript modelsim.ini vsim.wlf ucli.key vsim_stacktrace.vstf + rm -rf profile* simprofile* scanbuild-app scanbuild-sim DVEfiles/ csrc/ + rm -rf .ase_* *.o ase_seed.txt warnings.txt + rm -rf transcript *.log .ase_ipc_local ase_seed.txt + rm -rf vsim.wlf *_smq __hdl_xmr.tab + +distclean: header clean + ./distclean.sh diff --git a/ase/api/CMakeLists.txt b/ase/api/CMakeLists.txt new file mode 100644 index 000000000000..e436333cd470 --- /dev/null +++ b/ase/api/CMakeLists.txt @@ -0,0 +1,67 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +cmake_minimum_required(VERSION 2.8.11) + +project("opae-c-ase") +find_package(Threads REQUIRED) +set(API_DIR ${PROJECT_SOURCE_DIR}) +set(ASEAPI_SRC + ${API_DIR}/../sw/tstamp_ops.c + ${API_DIR}/../sw/ase_ops.c + ${API_DIR}/../sw/app_backend.c + ${API_DIR}/../sw/mqueue_ops.c + ${API_DIR}/../sw/error_report.c + ${API_DIR}/src/common.c + ${API_DIR}/src/buffer.c + ${API_DIR}/src/close.c + ${API_DIR}/src/enum.c + ${API_DIR}/src/event.c + ${API_DIR}/src/manage.c + ${API_DIR}/src/reconf.c + ${API_DIR}/src/mmio.c + ${API_DIR}/src/open.c + ${API_DIR}/src/umsg.c) + +add_library(opae-c-ase SHARED ${ASEAPI_SRC}) +target_link_libraries(opae-c-ase rt safestr) + +# Define headers for this library. PUBLIC headers are used for +# compiling the library, and will be added to consumers' build +# paths. Keep current directory private. +target_include_directories(opae-c-ase PUBLIC + $ + $ + PRIVATE src + $) + +set_target_properties(opae-c-ase PROPERTIES + VERSION ${INTEL_FPGA_API_VERSION} + SOVERSION ${INTEL_FPGA_API_VER_MAJOR}) + +install(TARGETS opae-c-ase + LIBRARY DESTINATION lib + COMPONENT opaecase) diff --git a/ase/api/src/buffer.c b/ase/api/src/buffer.c new file mode 100755 index 000000000000..4f52ab9af19b --- /dev/null +++ b/ase/api/src/buffer.c @@ -0,0 +1,138 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include "common_int.h" +#include + +#include +#include /* malloc */ +#include /* exit */ +#include /* printf */ +#include /* memcpy */ +#include /* getpid */ +#include /* pid_t */ +#include /* ioctl */ +#include /* mmap & munmap */ +#include /* struct timeval */ + + +fpga_result __FPGA_API__ fpgaPrepareBuffer(fpga_handle handle, + uint64_t len, void **buf_addr, + uint64_t *wsid, int flags) +{ + struct buffer_t *buf; + uint64_t pg_size; + fpga_result result = FPGA_NOT_FOUND; + + if (flags & FPGA_BUF_PREALLOCATED) { + return FPGA_INVALID_PARAM; + } + pg_size = (uint64_t) sysconf(_SC_PAGE_SIZE); + /* round up to nearest page boundary */ + if (!len || (len & (pg_size - 1))) { + len = pg_size + (len & ~(pg_size - 1)); + } + uint64_t *inp_buf_addr; + + buf = (struct buffer_t *) ase_malloc(sizeof(struct buffer_t)); + buf->memsize = (uint32_t) len; + + inp_buf_addr = (uint64_t *) (*buf_addr); + + // Allocate buffer (ASE call) + allocate_buffer(buf, inp_buf_addr); + + if ((ASE_BUFFER_VALID != buf->valid) || + (MAP_FAILED == (void *) buf->vbase) || + (0 == buf->fake_paddr)) { + printf("Error Allocating ASE buffer ... EXITING\n"); + result = FPGA_NO_MEMORY; + } else { + result = FPGA_OK; + } + + *wsid = buf->index; + + *buf_addr = (void **) buf->vbase; + + return result; +} + + +fpga_result __FPGA_API__ fpgaReleaseBuffer(fpga_handle handle, + uint64_t wsid) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *) handle; + fpga_result result = FPGA_NOT_FOUND; + + if (!_handle) { + FPGA_MSG("Handle is NULL"); + return FPGA_INVALID_PARAM; + } + + if (!wsid) + result = FPGA_NOT_FOUND; + else { + if (wsid < 2) { + result = FPGA_INVALID_PARAM; + } else { + // Call deallocate_buffer_by_WSID + if (!deallocate_buffer_by_index(wsid)) + result = FPGA_INVALID_PARAM; + else + result = FPGA_OK; + } + } + return result; +} + + +fpga_result __FPGA_API__ fpgaGetIOAddress(fpga_handle handle, uint64_t wsid, + uint64_t *iova) +{ + + struct buffer_t *iova_match_buf; + + fpga_result result; + + iova_match_buf = find_buffer_by_index(wsid); + + if (iova_match_buf != NULL) { + result = FPGA_OK; + *iova = iova_match_buf->fake_paddr; + } else { + result = FPGA_NOT_FOUND; + *iova = (uint64_t) NULL; + } + + return result; +} diff --git a/ase/api/src/close.c b/ase/api/src/close.c new file mode 100755 index 000000000000..fe60c1cc0c49 --- /dev/null +++ b/ase/api/src/close.c @@ -0,0 +1,56 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include "common_int.h" +#include + +#include +#include +#include + +fpga_result __FPGA_API__ fpgaClose(fpga_handle handle) +{ + fpga_result result; + if (NULL == handle) { + FPGA_MSG("Handle is NULL"); + return FPGA_INVALID_PARAM; + } + + struct _fpga_handle *_handle = (struct _fpga_handle *) handle; + + + // ASE Release + session_deinit(); + + free(_handle); + result = FPGA_OK; + return result; +} diff --git a/ase/api/src/common.c b/ase/api/src/common.c new file mode 100644 index 000000000000..ebfbbf9314fa --- /dev/null +++ b/ase/api/src/common.c @@ -0,0 +1,144 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include + +#include +#include "common_int.h" + +// Buffer Allocation constants +#define KB 1024 +#define MB (1024 * KB) +#define GB (1024 * MB) + +#ifndef MAP_HUGETLB +#define MAP_HUGETLB 0x40000 +#endif +#ifndef MAP_HUGE_SHIFT +#define MAP_HUGE_SHIFT 26 +#endif + +#define MAP_1G_HUGEPAGE (0x1e << MAP_HUGE_SHIFT) + +#define PROTECTION (PROT_READ | PROT_WRITE) +#ifdef __ia64__ +#define ADDR (void *)(0x8000000000000000UL) +#define FLAGS (MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB | MAP_FIXED) +#define FLAGS_1G (FLAGS | MAP_1G_HUGEPAGE) +#else +#define ADDR (void *)(0x0UL) +#define FLAGS (MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB) +#define FLAGS_1G (FLAGS | MAP_1G_HUGEPAGE) +#endif + +/* global list of tokens we've seen */ +static struct token_map *token_root; +/* global loglevel */ +static int g_loglevel = FPGA_LOG_UNDEFINED; + +const char __FPGA_API__ *fpgaErrStr(fpga_result e) +{ + switch (e) { + case FPGA_OK: + return "success"; + case FPGA_INVALID_PARAM: + return "invalid parameter"; + case FPGA_BUSY: + return "resource busy"; + case FPGA_EXCEPTION: + return "exception"; + case FPGA_NOT_FOUND: + return "not found"; + case FPGA_NO_MEMORY: + return "no memory"; + case FPGA_NOT_SUPPORTED: + return "not supported"; + case FPGA_NO_DRIVER: + return "no driver available"; + case FPGA_NO_ACCESS: + return "insufficient privileges"; + default: + return "unknown error"; + } +} + +void fpga_print(int loglevel, char *fmt, ...) +{ + FILE *fp = stdout; + // FIXME: not thread-safe (may interleave output from different threads) + + if (g_loglevel < 0) { /* loglevel not yet set? */ + + /* try to read loglevel from environment */ + char *s = getenv("LIBFPGA_LOG"); + if (s) + g_loglevel = atoi(s); +#ifndef LIBFGPA_DEBUG + if (g_loglevel >= FPGA_LOG_DEBUG) + fprintf(stderr, + "WARNING: Environment variable LIBFPGA_LOG is " + "set to output debug\nmessages, " + "but libfpga was not built with debug " + "information.\n"); +#endif + } + + if (g_loglevel < 0) /* loglevel still not set? */ + g_loglevel = FPGA_DEFAULT_LOGLEVEL; + + if (loglevel > g_loglevel) + return; + + if (loglevel == FPGA_LOG_ERROR) + fp = stderr; + + va_list argp; + va_start(argp, fmt); + vfprintf(fp, fmt, argp); + va_end(argp); + + return; +} + +struct _fpga_token *token_get_parent(struct _fpga_token *_t) +{ + if (_t == NULL) { + printf(" Token is NULL"); + } + + if (0 == memcmp(_t->accelerator_id, FPGA_FME_GUID, sizeof(fpga_guid))) { + return NULL; + } else { + return &aseToken[0]; + } +} diff --git a/ase/api/src/common_int.h b/ase/api/src/common_int.h new file mode 100644 index 000000000000..c976521a1a41 --- /dev/null +++ b/ase/api/src/common_int.h @@ -0,0 +1,124 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_COMMON_INT_H__ +#define __FPGA_COMMON_INT_H__ + +#include +#include /* bool type */ +#include /* malloc */ +#include /* exit */ +#include /* printf */ +#include /* memcpy */ +#include /* getpid */ +#include /* pid_t */ +#include /* ioctl */ +#include /* mmap & munmap */ +#include /* struct timeval */ + +#include +#include "types_int.h" + +/* Macro for defining symbol visibility */ +#define __FPGA_API__ __attribute__((visibility("default"))) +#define ASSERT_NOT_NULL_MSG(arg, msg) \ + do { \ + if (!arg) { \ + FPGA_MSG(msg); \ + return FPGA_INVALID_PARAM; \ + } \ + } while (0); + +#define ASSERT_NOT_NULL(arg) \ + ASSERT_NOT_NULL_MSG(arg, #arg " is NULL") +static const fpga_guid FPGA_FME_GUID = { + 0xbf, 0xaf, 0x2a, 0xe9, 0x4a, 0x52, 0x46, 0xe3, 0x82, 0xfe, + 0x38, 0xf0, 0xf9, 0xe1, 0x77, 0x64 +}; + +/* + * Logging functions + */ +enum fpga_loglevel { + FPGA_LOG_UNDEFINED = -1, /* loglevel not set */ + FPGA_LOG_ERROR = 0, /* critical errors (always print) */ + FPGA_LOG_MESSAGE, /* information (i.e. explain return code */ + FPGA_LOG_DEBUG /* debugging (also needs #define DEBUG 1) */ +}; + +#define FPGA_DEFAULT_LOGLEVEL 0 +/* + * Convenience macros for printing messages and errors. + */ +#ifdef __SHORT_FILE__ +#undef __SHORT_FILE__ +#endif // __SHORT_FILE__ +#define __SHORT_FILE__ \ +({ const char *file = __FILE__; \ + const char *p = file; \ + while (*p) \ + ++p; \ + while ((p > file) && \ + ('/' != *p) && \ + ('\\' != *p)) \ + --p; \ + if (p > file) \ + ++p; \ + p; \ +}) + +#ifdef FPGA_MSG +#undef FPGA_MSG +#endif // FPGA_MSG +#define FPGA_MSG(format, ...)\ + fpga_print(FPGA_LOG_MESSAGE, "libfpga %s:%u:%s() : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) + +#ifdef FPGA_ERR +#undef FPGA_ERR +#endif // FPGA_ERR +#define FPGA_ERR(format, ...)\ + fpga_print(FPGA_LOG_ERROR, "libfpga %s:%u:%s() **ERROR** : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) + +#ifdef FPGA_DBG +#undef FPGA_DBG +#endif // FPGA_DBG +#ifdef LIBFPGA_DEBUG +#define FPGA_DBG(format, ...)\ + fpga_print(FPGA_LOG_DEBUG, "libfpga %s:%u:%s() *DEBUG* : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) +#else +#define FPGA_DBG(format, ...) {} +#endif // LIBFPGA_DEBUG + +static struct _fpga_token aseToken[2] = { + { 0x46504741544f4b40, 0, FPGA_DEVICE }, + { 0x46504741544f4b40, 0, FPGA_ACCELERATOR} +}; +void fpga_print(int loglevel, char *fmt, ...); +struct _fpga_token *token_get_parent(struct _fpga_token *); +#endif // ___FPGA_COMMON_INT_H__ diff --git a/ase/api/src/enum.c b/ase/api/src/enum.c new file mode 100644 index 000000000000..5d3beebe9986 --- /dev/null +++ b/ase/api/src/enum.c @@ -0,0 +1,1010 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include "properties_int.h" +#include "common_int.h" +#include +#include +#include +#include "ase_common.h" +uint32_t session_exist_status = NOT_ESTABLISHED; + +#include +#include +#include +#include +#include +#define ASE_ID 0xA5EA5E +#define ASE_FME_ID 0x3345678UL +#define BBSID 0x63000023b637277UL +#define FPGA_NUM_SLOTS 1 +#define BBS_VERSION_MAJOR 6 +#define BBS_VERSION_MINOR 3 +#define BBS_VERSION_PATCH 0 + +extern ssize_t readlink(const char *, char *, size_t); + +void api_guid_to_fpga(uint64_t guidh, uint64_t guidl, uint8_t *guid) +{ + uint32_t i; + uint32_t s; + + // The API expects the MSB of the GUID at [0] and the LSB at [15]. + s = 64; + for (i = 0; i < 8; ++i) { + s -= 8; + guid[i] = (uint8_t) ((guidh >> s) & 0xff); + } + + s = 64; + for (i = 0; i < 8; ++i) { + s -= 8; + guid[8 + i] = (uint8_t) ((guidl >> s) & 0xff); + } +} + +struct dev_list { + fpga_objtype objtype; + fpga_guid guid; + uint8_t bus; + uint8_t device; + uint8_t function; + uint8_t socket_id; + + uint32_t fpga_num_slots; + uint64_t fpga_bitstream_id; + fpga_version fpga_bbs_version; + + fpga_accelerator_state accelerator_state; + uint32_t accelerator_num_mmios; + uint32_t accelerator_num_irqs; + struct dev_list *next; + struct dev_list *parent; + struct dev_list *fme; +}; + + static bool +matches_filters(const fpga_properties *filter, uint32_t num_filter, + fpga_token *token, uint64_t *j) +{ + uint32_t i; + if (filter == NULL) + return true; + struct _fpga_properties *_filter = (struct _fpga_properties *)*filter; + struct _fpga_token *_tok = (struct _fpga_token *)token; + if (!num_filter) // no filter == match everything + return true; + + if (_filter->valid_fields == 0) + return true; + + if (FIELD_VALID(_filter, FPGA_PROPERTY_DEVICE)) { + return true; + + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_FUNCTION)) { + return true; + } + + for (i = 0; i < num_filter; ++i) { + if (FIELD_VALID(_filter, FPGA_PROPERTY_PARENT)) { + if (_filter->parent == NULL) + return false; + + if (((struct _fpga_token *)_filter->parent)->ase_objtype == FPGA_ACCELERATOR) + return false; + else + *j = 1; + } + + if (_filter->objtype != _tok->ase_objtype) + return false; + + if (FIELD_VALID(_filter, FPGA_PROPERTY_GUID)) { + if (0 != memcmp(_tok->accelerator_id, _filter->guid, + sizeof(fpga_guid))) { + BEGIN_RED_FONTCOLOR; + printf(" [APP] Filter mismatch\n"); + END_RED_FONTCOLOR; + return false; + } + } + _filter++; + + } + return true; +} + + +fpga_result __FPGA_API__ +fpgaEnumerate(const fpga_properties *filters, uint32_t num_filters, + fpga_token *tokens, uint32_t max_tokens, + uint32_t *num_matches) +{ + uint64_t i; + aseToken[0].ase_objtype = FPGA_DEVICE; + aseToken[1].ase_objtype = FPGA_ACCELERATOR; + if ((num_filters > 0) && (NULL == (filters))) { + return FPGA_INVALID_PARAM; + } + + if (NULL == num_matches) { + return FPGA_INVALID_PARAM; + } + + if ((max_tokens > 0) && (NULL == tokens)) { + return FPGA_INVALID_PARAM; + } + + uint64_t afuid_data[2]; + fpga_guid readback_afuid; + + if (session_exist_status == NOT_ESTABLISHED) { + session_init(); + ase_memcpy(&aseToken[0].accelerator_id, FPGA_FME_GUID, sizeof(fpga_guid)); + + mmio_read64(0x8, &afuid_data[0]); + mmio_read64(0x10, &afuid_data[1]); + // Convert afuid_data to readback_afuid + // e.g.: readback{0x5037b187e5614ca2, 0xad5bd6c7816273c2} -> "5037B187-E561-4CA2-AD5B-D6C7816273C2" + api_guid_to_fpga(afuid_data[1], afuid_data[0], readback_afuid); + ase_memcpy(&aseToken[1].accelerator_id, readback_afuid, sizeof(fpga_guid)); + } + + *num_matches = 0; + for (i = 0; i < 2; i++) { + if (matches_filters(filters, num_filters, (void **)&aseToken[i], &i)) { + if (*num_matches < max_tokens) { + + + if (FPGA_OK != fpgaCloneToken(&aseToken[i], &tokens[*num_matches])) + FPGA_MSG("Error cloning token"); + } + ++*num_matches; + } + } + return FPGA_OK; + +} + +fpga_result __FPGA_API__ fpgaDestroyToken(fpga_token * token) +{ + if (NULL == token || NULL == *token) { + FPGA_MSG("Invalid token pointer"); + return FPGA_INVALID_PARAM; + } + + struct _fpga_token *_token = (struct _fpga_token *)*token; + + if (_token->magic != ASE_TOKEN_MAGIC) { + FPGA_MSG("Invalid token"); + return FPGA_INVALID_PARAM; + } + + // invalidate magic (just in case) + _token->magic = FPGA_INVALID_MAGIC; + + free(*token); + *token = NULL; + return FPGA_OK; + +} + +fpga_result __FPGA_API__ fpgaGetProperties(fpga_token token, + fpga_properties * prop) +{ + struct _fpga_properties *_prop; + fpga_result result = FPGA_OK; + ASSERT_NOT_NULL(prop); + //ASSERT_NOT_NULL(token); + _prop = malloc(sizeof(struct _fpga_properties)); + if (NULL == _prop) { + FPGA_MSG("Failed to allocate memory for properties"); + return FPGA_NO_MEMORY; + } + memset(_prop, 0, sizeof(struct _fpga_properties)); + // mark data structure as valid + _prop->magic = FPGA_PROPERTY_MAGIC; + + if (token) { + result = fpgaUpdateProperties(token, _prop); + if (result != FPGA_OK) { + goto out_free; + } + } + + *prop = (fpga_properties) _prop; + return result; +out_free: + free(_prop); + return result; +} + +/* FIXME: make thread-safe? */ +fpga_result __FPGA_API__ fpgaCloneProperties(fpga_properties src, + fpga_properties * dst) +{ + struct _fpga_properties *_src = (struct _fpga_properties *) src; + struct _fpga_properties *_dst; + + if (NULL == src || NULL == dst) + return FPGA_INVALID_PARAM; + + if (_src->magic != FPGA_PROPERTY_MAGIC) { + FPGA_MSG("Invalid properties object"); + return FPGA_INVALID_PARAM; + } + _dst = malloc(sizeof(struct _fpga_properties)); + if (NULL == _dst) { + FPGA_MSG("Failed to allocate memory for properties"); + return FPGA_NO_MEMORY; + } + + ase_memcpy(_dst, _src, sizeof(struct _fpga_properties)); + + *dst = _dst; + return FPGA_OK; + +} + +fpga_result __FPGA_API__ fpgaClearProperties(fpga_properties prop) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + + if (NULL == prop) + return FPGA_INVALID_PARAM; + + _prop->valid_fields = 0; + + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaDestroyProperties(fpga_properties * prop) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)*prop; + + if (NULL == _prop) { + FPGA_ERR("Attempting to free NULL pointer"); + return FPGA_INVALID_PARAM; + } else { + _prop->magic = FPGA_INVALID_MAGIC; + free(*prop); + *prop = NULL; + return FPGA_OK; + } +} + +fpga_result __FPGA_API__ +fpgaUpdateProperties(fpga_token token, fpga_properties prop) +{ + struct _fpga_token *_token = (struct _fpga_token *) token; + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + + struct _fpga_properties _iprop; + + if (NULL == token) + return FPGA_INVALID_PARAM; + + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + FPGA_MSG("Invalid properties object"); + return FPGA_INVALID_PARAM; + } + + if (ASE_TOKEN_MAGIC != _token->magic) + return FPGA_INVALID_PARAM; + + //clear fpga_properties buffer + memset(&_iprop, 0, sizeof(struct _fpga_properties)); + _iprop.magic = FPGA_PROPERTY_MAGIC; + if (ASE_TOKEN_MAGIC == _token->magic) { + // The input token is either an FME or an AFU. + if (0 == memcmp(_token->accelerator_id, FPGA_FME_GUID, sizeof(fpga_guid))) { + _iprop.objtype = FPGA_DEVICE; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_OBJTYPE); + _iprop.device_id = ASE_ID; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_DEVICEID); + } else { + _iprop.parent = (fpga_token) token_get_parent(_token); + if (NULL != _iprop.parent) + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_PARENT); + _iprop.objtype = FPGA_ACCELERATOR; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_OBJTYPE); + + } + } + + *_prop = _iprop; + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetParent(const fpga_properties prop, fpga_token * parent) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == parent) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_PARENT)) { + result = fpgaCloneToken(_prop->parent, parent); + if (FPGA_OK != result) + FPGA_MSG("Error cloning token from property"); + } else { + FPGA_MSG("No parent"); + result = FPGA_NOT_FOUND; + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetParent(fpga_properties prop, fpga_token parent) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + + _prop->parent = parent; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_PARENT); + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetObjectType(const fpga_properties prop, + fpga_objtype *objtype) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == objtype) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE)) { + *objtype = _prop->objtype; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetObjectType(fpga_properties prop, fpga_objtype objtype) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + + + if (_prop->magic != FPGA_PROPERTY_MAGIC) + return FPGA_INVALID_PARAM; + + _prop->objtype = objtype; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE); + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaPropertiesGetBus(const fpga_properties prop, + uint8_t *bus) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == bus) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_BUS)) { + *bus = _prop->bus; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + + return result; +} + + +fpga_result __FPGA_API__ fpgaPropertiesSetBus(fpga_properties prop, + uint8_t bus) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + _prop->bus = bus; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BUS); + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetDevice(const fpga_properties prop, uint8_t *device) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + + if (NULL == _prop || NULL == device) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return FPGA_INVALID_PARAM; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_DEVICE)) { + *device = _prop->device; + return FPGA_OK; + } else { + return FPGA_NOT_FOUND; + } +} + +fpga_result __FPGA_API__ fpgaPropertiesSetDevice(fpga_properties prop, + uint8_t device) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + _prop->device = device; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_DEVICE); + return FPGA_OK; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetFunction(const fpga_properties prop, uint8_t *function) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == function) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_FUNCTION)) { + *function = _prop->function; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesSetFunction(fpga_properties prop, uint8_t function) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + _prop->function = function; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_FUNCTION); + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetSocketID(const fpga_properties prop, uint8_t *socket_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_OK; + + if (NULL == _prop || NULL == socket_id) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return FPGA_INVALID_PARAM; + } + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + result = FPGA_INVALID_PARAM; + } + + if (FIELD_VALID(_prop, FPGA_PROPERTY_SOCKETID)) { + *socket_id = _prop->socket_id; + } else { + result = FPGA_NOT_FOUND; + } + + printf(" ASE doesnt support Socket ID \n"); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetSocketID(fpga_properties prop, uint8_t socket_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_OK; + + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + result = FPGA_INVALID_PARAM; + } + + _prop->socket_id = socket_id; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_SOCKETID); + printf(" ASE doesnt support Socket ID\n"); + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetDeviceID(const fpga_properties prop, uint32_t *device_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + + if (NULL == _prop) { + return FPGA_INVALID_PARAM; + } + + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + return FPGA_INVALID_PARAM; + } + + if (FIELD_VALID(_prop, FPGA_PROPERTY_DEVICEID)) { + *device_id = _prop->device_id; + } else { + return FPGA_NOT_FOUND; + } + + + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetDeviceID(fpga_properties prop, uint32_t device_id) +{ + printf(" ASE doesnt support Device ID \n"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumSlots(const fpga_properties prop, uint32_t *num_slots) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == num_slots) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_SLOTS)) { + *num_slots = _prop->u.fpga.num_slots; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get num_slots from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumSlots(fpga_properties prop, uint32_t num_slots) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_SLOTS); + _prop->u.fpga.num_slots = num_slots; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set num_slots from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetBBSID(const fpga_properties prop, uint64_t *bbs_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == bbs_id) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_BBSID)) { + *bbs_id = _prop->u.fpga.bbs_id; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get bbs_id from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetBBSID(fpga_properties prop, uint64_t bbs_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BBSID); + _prop->u.fpga.bbs_id = bbs_id; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set bbs_id from invalid object type: %d", + _prop->objtype); + } + + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetBBSVersion(const fpga_properties prop, + fpga_version *bbs_version) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == bbs_version) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_BBSVERSION)) { + *bbs_version = _prop->u.fpga.bbs_version; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get bbs_version from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetBBSVersion(fpga_properties prop, fpga_version bbs_version) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BBSVERSION); + _prop->u.fpga.bbs_version = bbs_version; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set bbs_version from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetVendorID(const fpga_properties prop, uint16_t *vendor_id) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetVendorID(fpga_properties prop, uint16_t vendor_id) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetModel(const fpga_properties prop, char *model) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetModel(fpga_properties prop, char *model) +{ + return FPGA_NOT_SUPPORTED; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetLocalMemorySize(const fpga_properties prop, + uint64_t *local_memory_size) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetLocalMemorySize(fpga_properties prop, + uint64_t local_memory_size) +{ + return FPGA_NOT_SUPPORTED; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetCapabilities(const fpga_properties prop, + uint64_t *capabilities) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetCapabilities(fpga_properties prop, uint64_t capabilities) +{ + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ fpgaPropertiesGetGUID(const fpga_properties prop, + fpga_guid *guid) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == guid) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + FPGA_MSG("Invalid properties object"); + return FPGA_INVALID_PARAM; + } + + if (FIELD_VALID(_prop, FPGA_PROPERTY_GUID)) { + ase_memcpy(*guid, _prop->guid, 16); + result = FPGA_OK; + } else { + FPGA_MSG("No GUID"); + result = FPGA_NOT_FOUND; + } + return result; +} + +fpga_result __FPGA_API__ fpgaPropertiesSetGUID(fpga_properties prop, + fpga_guid guid) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } else { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_GUID); + ase_memcpy(_prop->guid, guid, 16); + result = FPGA_OK; + } + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumMMIO(const fpga_properties prop, + uint32_t *mmio_spaces) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == mmio_spaces) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_MMIO)) { + *mmio_spaces = _prop->u.accelerator.num_mmio; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get status from invalid object type: %d", + _prop->objtype); + } + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumMMIO(fpga_properties prop, uint32_t mmio_spaces) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_MMIO); + _prop->u.accelerator.num_mmio = mmio_spaces; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set status from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumInterrupts(const fpga_properties prop, + uint32_t *num_interrupts) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == num_interrupts) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_INTERRUPTS)) { + *num_interrupts = _prop->u.accelerator.num_interrupts; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get status from invalid object type: %d", + _prop->objtype); + } + return result; +} + +fpga_result __FPGA_API__ fpgaCloneToken(fpga_token src, + fpga_token *dst) +{ + struct _fpga_token *_src = (struct _fpga_token *)src; + struct _fpga_token *_dst; + + if (NULL == src || NULL == dst) { + FPGA_MSG("src or dst in NULL"); + return FPGA_INVALID_PARAM; + } + + if (_src->magic != ASE_TOKEN_MAGIC) { + FPGA_MSG("Invalid src"); + return FPGA_INVALID_PARAM; + } + + _dst = malloc(sizeof(struct _fpga_token)); + if (NULL == _dst) { + FPGA_MSG("Failed to allocate memory for token"); + return FPGA_NO_MEMORY; + } + + _dst->magic = _src->magic; + ase_memcpy(_dst->accelerator_id, _src->accelerator_id, sizeof(fpga_guid)); + _dst->ase_objtype = _src->ase_objtype; + *dst = _dst; + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumInterrupts(fpga_properties prop, + uint32_t num_interrupts) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_INTERRUPTS); + _prop->u.accelerator.num_interrupts = num_interrupts; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set status from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetAcceleratorState(const fpga_properties prop, + fpga_accelerator_state *state) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop || NULL == state) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_ACCELERATOR_STATE)) { + *state = _prop->u.accelerator.state; + result = FPGA_OK; + } else { + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get state from invalid object type: %d", + _prop->objtype); + } + + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetAcceleratorState(fpga_properties prop, fpga_accelerator_state state) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *) prop; + fpga_result result = FPGA_INVALID_PARAM; + if (NULL == _prop) { + FPGA_ERR("Attempting to dereference NULL pointer(s)"); + return result; + } + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_ACCELERATOR_STATE); + _prop->u.accelerator.state = state; + result = FPGA_OK; + } else { + FPGA_ERR + ("Attempting to set state from invalid object type: %d", + _prop->objtype); + } + + return result; +} + + diff --git a/ase/api/src/event.c b/ase/api/src/event.c new file mode 100644 index 000000000000..cf4d9859f143 --- /dev/null +++ b/ase/api/src/event.c @@ -0,0 +1,65 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include "common_int.h" + + +fpga_result __FPGA_API__ fpgaCreateEventHandle(fpga_event_handle *handle) +{ + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} + +fpga_result __FPGA_API__ fpgaDestroyEventHandle(fpga_event_handle *handle) +{ + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} + +fpga_result __FPGA_API__ fpgaRegisterEvent(fpga_handle handle, + fpga_event_type type, + fpga_event_handle event_handle, + uint32_t flags) +{ + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} + +fpga_result __FPGA_API__ fpgaUnregisterEvent(fpga_handle handle, + fpga_event_type event_type) +{ + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} diff --git a/ase/api/src/manage.c b/ase/api/src/manage.c new file mode 100644 index 000000000000..9721c14e16fc --- /dev/null +++ b/ase/api/src/manage.c @@ -0,0 +1,56 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include "common_int.h" + +fpga_result __FPGA_API__ fpgaAssignToInterface(fpga_handle fpga, fpga_token accelerator, + uint32_t host_interface, int flags) +{ + fpga_result result = FPGA_NOT_FOUND; + + return result; +} + +fpga_result __FPGA_API__ fpgaReleaseFromInterface(fpga_handle fpga, fpga_token accelerator) +{ + fpga_result result = FPGA_NOT_FOUND; + + return result; +} + +fpga_result __FPGA_API__ fpgaReconfigureContext(fpga_handle accelerator, + const uint8_t *bitstream, + size_t bitstream_len, int flags) +{ + fpga_result result = FPGA_NOT_FOUND; + + return result; +} diff --git a/ase/api/src/mmio.c b/ase/api/src/mmio.c new file mode 100755 index 000000000000..13c3b9911e94 --- /dev/null +++ b/ase/api/src/mmio.c @@ -0,0 +1,204 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include "common_int.h" +#include "ase_common.h" + +#include +#include /* malloc */ +#include /* exit */ +#include /* printf */ +#include /* memcpy */ +#include /* getpid */ +#include /* pid_t */ +#include /* ioctl */ +#include /* mmap & munmap */ +#include /* struct timeval */ + +bool fpgaMMIO_is_mapped; + +fpga_result __FPGA_API__ fpgaWriteMMIO32(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, uint32_t value) +{ + if (NULL == handle) { + FPGA_MSG("handle is NULL"); + return FPGA_INVALID_PARAM; + } + + if (NULL == mmio_afu_vbase) { + return FPGA_NOT_FOUND; + } else { + if (offset % sizeof(uint32_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } else { + if (offset > MMIO_AFU_OFFSET) { + FPGA_MSG("Offset out of bounds"); + return FPGA_INVALID_PARAM; + } + + mmio_write32(offset, value); + return FPGA_OK; + } + } + + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaReadMMIO32(fpga_handle handle, + uint32_t mmio_num, uint64_t offset, + uint32_t *value) +{ + if (NULL == mmio_afu_vbase) { + return FPGA_NOT_FOUND; + } else { + if (offset % sizeof(uint32_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } else { + if (offset > MMIO_AFU_OFFSET) { + FPGA_MSG("offset out of bounds"); + return FPGA_INVALID_PARAM; + } + + mmio_read32(offset, value); + return FPGA_OK; + } + } + +} + + +fpga_result __FPGA_API__ fpgaWriteMMIO64(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, uint64_t value) +{ + + if (NULL == mmio_afu_vbase) { + return FPGA_NOT_FOUND; + } else { + if (offset % sizeof(uint64_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } else { + if (offset > MMIO_AFU_OFFSET) { + FPGA_MSG("Offset out of bounds"); + return FPGA_INVALID_PARAM; + } + mmio_write64(offset, value); + return FPGA_OK; + } + } + +} + +fpga_result __FPGA_API__ fpgaReadMMIO64(fpga_handle handle, + uint32_t mmio_num, uint64_t offset, + uint64_t *value) +{ + + if (NULL == mmio_afu_vbase) { + return FPGA_NOT_FOUND; + } else { + if (offset % sizeof(uint64_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } else { + if (offset > MMIO_AFU_OFFSET) { + FPGA_MSG("Offset out of bounds"); + return FPGA_INVALID_PARAM; + } + mmio_read64(offset, (uint64_t *) value); + return FPGA_OK; + } + } + +} + +fpga_result __FPGA_API__ fpgaMapMMIO(fpga_handle handle, uint32_t mmio_num, + uint64_t **mmio_ptr) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *) handle; + fpga_result result = FPGA_OK; + + //check handle + if (!_handle) { + FPGA_MSG("Invalid handle"); + return FPGA_INVALID_PARAM; + } + // TODO: check mmio_num? + + // Record that MapMMIO was called + fpgaMMIO_is_mapped = true; + + if (mmio_ptr) { + BEGIN_YELLOW_FONTCOLOR; + printf + (" [APP] ** WARNING ** => ASE does not support pointer access to MMIO, use mmio{Read,Write}{32,64} functions\n"); + END_YELLOW_FONTCOLOR; + result = FPGA_NOT_SUPPORTED; + } + return result; +} + +fpga_result __FPGA_API__ fpgaUnmapMMIO(fpga_handle handle, + uint32_t mmio_num) +{ + // TODO: check handle? + // TODO: check mmio_num? + + if (fpgaMMIO_is_mapped) { + fpgaMMIO_is_mapped = false; + return FPGA_OK; + } else { + return FPGA_INVALID_PARAM; + } +} + +fpga_result __FPGA_API__ fpgaReset(fpga_handle handle) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *) handle; + if (_handle == NULL) { + FPGA_ERR("handle is NULL"); + return FPGA_INVALID_PARAM; + } + + if (_handle->magic != FPGA_HANDLE_MAGIC) { + FPGA_MSG("Invalid handle object"); + return FPGA_INVALID_PARAM; + } + + send_swreset(); + + return FPGA_OK; +} diff --git a/ase/api/src/open.c b/ase/api/src/open.c new file mode 100755 index 000000000000..7a3b7e498b87 --- /dev/null +++ b/ase/api/src/open.c @@ -0,0 +1,97 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include "common_int.h" +#include "types_int.h" +#include + +#include +#include +#include +#include + +fpga_result __FPGA_API__ fpgaOpen(fpga_token token, fpga_handle *handle, int flags) +{ + fpga_result result = FPGA_NOT_FOUND; + struct _fpga_handle *_handle; + struct _fpga_token *_token; + if (NULL == token) { + FPGA_MSG("token is NULL"); + return FPGA_INVALID_PARAM; + } + + if (NULL == handle) { + FPGA_MSG("handle is NULL"); + return FPGA_INVALID_PARAM; + } + + if (flags & ~FPGA_OPEN_SHARED) { + FPGA_MSG("Unrecognized flags"); + return FPGA_INVALID_PARAM; + } + + if (flags & FPGA_OPEN_SHARED) { + FPGA_MSG("Flag \"FPGA_OPEN_SHARED\" is not supported by ASE\n"); + BEGIN_RED_FONTCOLOR; + printf(" [APP] Flag \"FPGA_OPEN_SHARED\" is not supported by ASE\n"); + END_RED_FONTCOLOR; + return FPGA_NOT_SUPPORTED; + } + + _token = (struct _fpga_token *)token; + + if (_token->magic != ASE_TOKEN_MAGIC) { + FPGA_MSG("Invalid token"); + return FPGA_INVALID_PARAM; + } + + // ASE Session Initialization + session_init(); + + _handle = malloc(sizeof(struct _fpga_handle)); + if (NULL == _handle) { + FPGA_MSG("Failed to allocate memory for handle"); + return FPGA_NO_MEMORY; + } + + memset(_handle, 0, sizeof(*_handle)); + + _handle->token = token; + _handle->magic = FPGA_HANDLE_MAGIC; + // Init MMIO table + _handle->mmio_root = NULL; + // set handle return value + *handle = (void *)_handle; + + result = FPGA_OK; + return result; +} diff --git a/ase/api/src/properties_int.h b/ase/api/src/properties_int.h new file mode 100644 index 000000000000..a646636f8af5 --- /dev/null +++ b/ase/api/src/properties_int.h @@ -0,0 +1,69 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_PROPERTIES_INT_H__ +#define __FPGA_PROPERTIES_INT_H__ + +/** Fields common across all object types */ + +#define FPGA_PROPERTY_PARENT 0 +#define FPGA_PROPERTY_OBJTYPE 1 +#define FPGA_PROPERTY_BUS 2 +#define FPGA_PROPERTY_DEVICE 3 +#define FPGA_PROPERTY_FUNCTION 4 +#define FPGA_PROPERTY_SUBDEV 5 +#define FPGA_PROPERTY_SOCKETID 6 +#define FPGA_PROPERTY_PERMISSIONS 7 +#define FPGA_PROPERTY_DEVICEID 8 +#define FPGA_PROPERTY_GUID 9 + + +/** Fields for FPGA objects */ +#define FPGA_PROPERTY_NUM_SLOTS 32 +#define FPGA_PROPERTY_BBSID 33 +#define FPGA_PROPERTY_BBSVERSION 34 +#define FPGA_PROPERTY_VENDORID 35 +#define FPGA_PROPERTY_MODEL 36 +#define FPGA_PROPERTY_LOCAL_MEMORY 37 +#define FPGA_PROPERTY_CAPABILITIES 38 + + +/** Fields for accelerator objects */ +#define FPGA_PROPERTY_ACCELERATOR_STATE 32 +#define FPGA_PROPERTY_NUM_MMIO 33 +#define FPGA_PROPERTY_NUM_INTERRUPTS 34 + + +#define FIELD_VALID(P, F) (((P)->valid_fields >> (F)) & 1) + +#define SET_FIELD_VALID(P, F)\ + ((P)->valid_fields = (P)->valid_fields | ((uint64_t)1 << (F))) + +#define CLEAR_FIELD_VALID(P, F)\ + ((P)->valid_fields = (P)->valid_fields & ~((uint64_t)1 << (F))) + +#endif // __FPGA_PROPERTIES_INT_H__ + diff --git a/ase/api/src/reconf.c b/ase/api/src/reconf.c new file mode 100644 index 000000000000..7d6bfc332a83 --- /dev/null +++ b/ase/api/src/reconf.c @@ -0,0 +1,40 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "common_int.h" + +fpga_result __FPGA_API__ fpgaReconfigureSlot(fpga_handle fpga, + uint32_t slot, + const uint8_t *bitstream, + size_t bitstream_len, + int flags) +{ + return FPGA_OK; +} diff --git a/ase/api/src/types_int.h b/ase/api/src/types_int.h new file mode 100644 index 000000000000..76476707b970 --- /dev/null +++ b/ase/api/src/types_int.h @@ -0,0 +1,151 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * \brief Internal type definitions for FPGA API + */ + +#ifndef __FPGA_TYPES_INT_H__ +#define __FPGA_TYPES_INT_H__ + +#include +#include +#include +#include + +#define FPGA_BBS_VER_MAJOR(i) (((i) >> 56) & 0xf) +#define FPGA_BBS_VER_MINOR(i) (((i) >> 52) & 0xf) +#define FPGA_BBS_VER_PATCH(i) (((i) >> 48) & 0xf) + +#define DEV_PATH_MAX 256 + +// FPGA token magic (FPGATOKN) +#define FPGA_TOKEN_MAGIC 0x46504741544f4b4e +// FPGA handle magic (FPGAHNDL) +#define FPGA_HANDLE_MAGIC 0x46504741484e444c +// FPGA property magic (FPGAPROP) +#define FPGA_PROPERTY_MAGIC 0x4650474150524f50 +// FPGA invalid magic (FPGAINVL) +#define FPGA_INVALID_MAGIC 0x46504741494e564c +// ASE token Magic (FPGATOKN) +#define ASE_TOKEN_MAGIC 0x46504741544f4b40 +/** System-wide unique FPGA resource identifier */ +struct _fpga_token { + uint64_t magic; + fpga_guid accelerator_id; + fpga_objtype ase_objtype; +}; + +/** Process-wide unique FPGA handle */ +struct _fpga_handle { + pthread_mutex_t lock; + uint64_t magic; + fpga_token token; + int fddev; // file descriptor for the device. + struct wsid_map *wsid_root; // wsid information (list) + struct wsid_map *mmio_root; // MMIO information (list) + void *umsg_virt; // umsg Virtual Memory pointer + uint64_t umsg_size; // umsg Virtual Memory Size + uint64_t *umsg_iova; // umsg IOVA from driver +}; + +/** Object property struct + Intent is for property struct to be created dynamically */ +struct _fpga_properties { + pthread_mutex_t lock; + uint64_t magic; + /* Common properties */ + uint64_t valid_fields; // bitmap of valid fields + // valid here means the field has been set using the API + // bit 0x00 - parent field is valid + // bit 0x01 - objtype field is valid + // bit 0x02 - bus field is valid + // ... + // up to bit 0x1F + fpga_guid guid; // Applies only to accelerator types + fpga_token parent; + fpga_objtype objtype; + uint8_t bus; + uint8_t device; + uint8_t function; + uint8_t socket_id; + uint64_t device_id; + + /* Object-specific properties + * bitfields start as 0x20 + */ + union { + + /* fpga object properties + * */ + struct { + uint32_t num_slots; + uint64_t bbs_id; + fpga_version bbs_version; + // TODO uint16_t vendor_id; + // TODO char model[FPGA_MODEL_LENGTH]; + // TODO uint64_t local_memory_size; + // TODO uint64_t capabilities; #<{(| bitfield (HSSI, iommu, ...) |)}># + } fpga; + + /* accelerator object properties + * */ + struct { + fpga_accelerator_state state; + uint32_t num_mmio; + uint32_t num_interrupts; + } accelerator; + + } u; + +}; + +/* + * Global list to store wsid/physptr/length vectors + */ +struct wsid_map { + uint64_t wsid; + uint64_t addr; + uint64_t phys; + uint64_t len; + uint64_t offset; + uint32_t index; + int flags; + struct wsid_map *next; +}; + +/* + * Global list to store tokens received during enumeration + * Since tokens as seen by the API are only void*, we need to keep the actual + * structs somewhere. + */ +struct token_map { + struct _fpga_token _token; + struct token_map *next; +}; + + +#endif // __FPGA_TYPES_INT_H__ diff --git a/ase/api/src/umsg.c b/ase/api/src/umsg.c new file mode 100644 index 000000000000..98c699779c5b --- /dev/null +++ b/ase/api/src/umsg.c @@ -0,0 +1,78 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include +#include +#include "common_int.h" +#include "ase_common.h" + +#include +#include +#include +#include +#include +#include +#include +#include + + +// Get number of Umsgs +fpga_result __FPGA_API__ fpgaGetNumUmsg(fpga_handle handle, uint64_t *value) +{ + fpga_result result = FPGA_OK; + // Get Umsg Number + *value = NUM_UMSG_PER_AFU; + result = FPGA_OK; + + return result; +} + +// Set Umsg Attributes +fpga_result __FPGA_API__ fpgaSetUmsgAttributes(fpga_handle handle, uint64_t value) +{ + fpga_result result; + // Send UMSG setup (call ASE) + umsg_set_attribute(value); + result = FPGA_OK; + + return result; +} + +// Gets Umsg address +fpga_result __FPGA_API__ fpgaGetUmsgPtr(fpga_handle handle, uint64_t **umsg_ptr) +{ + fpga_result result = FPGA_OK; + + *umsg_ptr = umsg_umas_vbase; + + if (*umsg_ptr == NULL) { + + result = FPGA_NO_MEMORY; + } else { + result = FPGA_OK; + } + return result; +} diff --git a/ase/ase.cfg b/ase/ase.cfg new file mode 100644 index 000000000000..60bd7e27401c --- /dev/null +++ b/ase/ase.cfg @@ -0,0 +1,86 @@ +## Copyright(c) 2014-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +######################################################################## +# +# ASE configuration file +# Author: Rahul R Sharma +# Purpose: Configures ASE runtime behaviour (feature control, logging +# levels, verbosity, etc.) +# +# SYNTAX: +# * Empty line and line beginning with # is ignored +# * Unknown settings are ignored, WARNINGs issued when parsing. +# +######################################################################## + +# Set up ASE behavior +# Choose between daemon, single-shot, timeout settings, regression modes +# Select exit and timeout behavior from following settings +# +# ASE_MODE | ASE_TIMEOUT | ASE_NUM_TESTS | DESCRIPTION +# ----------------------------------------------------------------------- +# 1 | n/a | n/a | Server-Client mode +# | | | SIMKILL: CTRL-C keyboard input +# | | | +# 2 | tkill | n/a | Server-Client mode w/ SIMKILL +# | | | SIMKILL: Simulation is killed +# | | | after'tkill' clock cycles +# | | | +# 3 | n/a | n/a | Server-Client mode w/ SW SIMKILL +# | | | (used for long runs) +# | | | SIMKILL: Killed by Software +# | | | +# 4 | n/a | num_tests | Regression mode +# | | | Reads ase_regress.sh for tests +# | | | SIMKILL: Killed after 'num_tests' +# | | | applications are run +# | | | +# > 5 | n/a | n/a | ** ILLEGAL ** +# | | | Revert to ASE_MODE = 1 +# | | | +ASE_MODE = 1 +ASE_TIMEOUT = 50000 +ASE_NUM_TESTS = 4 + +# Enable reuse of ASE seed +# Re-create a previous session using this switch (addresses will be re-doable) +# DEFAULT: set to '0' +ENABLE_REUSE_SEED = 1 +ASE_SEED = 1234 + +# Enable printing each transaction: This will print every transaction on stdout +# DEFAULT: Set to '1' +ENABLE_CL_VIEW = 1 + +# Configurable User Clock (Read by simulator as float) +# DEFAULT: Set to '312.500' +USR_CLK_MHZ = 312.500000 + +# Physical memory available +# Helps in porting from CCI-S to CCI-P +PHYS_MEMORY_AVAILABLE_GB = 128 + + diff --git a/ase/ase_regress.sh b/ase/ase_regress.sh new file mode 100755 index 000000000000..03430013898b --- /dev/null +++ b/ase/ase_regress.sh @@ -0,0 +1,42 @@ +#!/bin/bash +## Copyright(c) 2015-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## ************************************************************************** + +if [ $MYINST_DIR == "" ]; +then + echo "env(MYINST_DIR) has not been set -- please set it to OPAE install directory" +fi + +LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${MYINST_DIR}/lib/ + +cd $MYINST_DIR/bin +LD_PRELOAD=libopae-c-ase.so ./fpgadiag -t ase -m lpbk1 -b 16 +LD_PRELOAD=libopae-c-ase.so ./fpgadiag -t ase -m lpbk1 -b 32 +LD_PRELOAD=libopae-c-ase.so ./fpgadiag -t ase -m lpbk1 -b 64 +LD_PRELOAD=libopae-c-ase.so ./fpgadiag -t ase -m lpbk1 -b 80 + + diff --git a/ase/distclean.sh b/ase/distclean.sh new file mode 100755 index 000000000000..1440562bf927 --- /dev/null +++ b/ase/distclean.sh @@ -0,0 +1,31 @@ +#!/bin/bash +## Copyright(c) 2014-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +rm -rf ase_sources.mk ase_files.files synopsys_sim.setup vlog_files.list vhdl_files.list ucli.key +rm -rf scripts/*.pyc vcs_run.tcl vsim_run.tcl +rm -rf DVEfiles/ ase_seed.txt + diff --git a/ase/rtl/ase_pkg.sv b/ase/rtl/ase_pkg.sv new file mode 100644 index 000000000000..fc905dcb9127 --- /dev/null +++ b/ase/rtl/ase_pkg.sv @@ -0,0 +1,977 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * ASE generics (SystemVerilog header file) + * + * Description: + * This file contains definitions and parameters for the DPI + * module. The intent of this file is that the user should not modify + * the DPI source files. **Only** this header file must be modified if + * any DPI parameters need to be changed. + * + */ + +package ase_pkg; + + import ccip_if_pkg::*; + + // ASE modes + parameter ASE_MODE_DAEMON = 1; + parameter ASE_MODE_TIMEOUT_SIMKILL = 2; + parameter ASE_MODE_SW_SIMKILL = 3; + parameter ASE_MODE_REGRESSION = 4; + + + // Include platform.vh if not already + `ifndef _PLATFORM_VH_ + `include "platform.vh" + `endif + + // Address widths + parameter PHYSCLADDR_WIDTH = 42; + + + /* + * CCI specifications + */ + parameter CCIP_DATA_WIDTH = 512; + parameter CCIP_CFG_RDDATA_WIDTH = 64; + + /* + * Sub-structures + * Request type, response types, VC types + */ + // Request types {channel_id, ccip_if_pkg::req_type} + typedef enum logic [3:0] { + `ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_REQ = 4'h7, + `endif + ASE_RDLINE_S = 4'h1, + ASE_RDLINE_I = 4'h2, + ASE_WRLINE_I = 4'h3, + ASE_WRLINE_M = 4'h4, + ASE_WRPUSH = 4'h5, + ASE_WRFENCE = 4'h6 + // ASE_ATOMIC_REQ = 4'h8 + } ccip_reqtype_t; + + // Response types + typedef enum logic [3:0] { + `ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_RSP = 4'h3, + `endif + `ifdef ASE_ENABLE_UMSG_FEATURE + ASE_UMSG = 4'h6, + `endif + ASE_RD_RSP = 4'h1, + ASE_WR_RSP = 4'h2, + ASE_WRFENCE_RSP = 4'h4 + // ASE_ATOMIC_RSP = 4'h5, + } ccip_resptype_t; + + // Virtual channel type + typedef enum logic [1:0] { + VC_VA = 2'b00, + VC_VL0 = 2'b01, + VC_VH0 = 2'b10, + VC_VH1 = 2'b11 + } ccip_vc_t; + + // Length type + typedef enum logic [1:0] { + ASE_1CL = 2'b00, + ASE_2CL = 2'b01, + ASE_3CL = 2'b10, + ASE_4CL = 2'b11 + } ccip_len_t; + + + /* *********************************************************** + * CCI-P headers + * RxHdr, TxHdr, CCIP Packets + * ***********************************************************/ + // RxHdr + typedef struct packed { + //--------- CCIP standard header --------- // + ccip_vc_t vc_used; // 27:26 // Virtual channel select + logic rsvd25; // 25 // Poison bit + logic hitmiss; // 24 // Hit/miss indicator + logic format; // 23 // Multi-CL enable (write packing only) + logic rsvd22; // 22 // X + ccip_len_t clnum; // 21:20 // Cache line number + ccip_resptype_t resptype; // 19:16 // Response type + logic [15:0] mdata; // 15:0 // Metadata + } RxHdr_t; + parameter CCIP_RX_HDR_WIDTH = $bits(RxHdr_t); + + typedef logic [CCIP_RX_HDR_WIDTH-1:0] logic_cast_RxHdr_t; + + + // TxHdr + typedef struct packed { + //--------- CCIP standard header --------- // + logic [79:77] qword_idx; // 79:77 // Qword start (no end, sets a cmp QW index) + logic [76:74] rsvd76_74; // 76:74 // X + ccip_vc_t vc; // 73:72 // Virtual channel select + logic sop; // 71 // Start of packet + logic rsvd70; // 70 // X + ccip_len_t len; // 69:68 // Length + ccip_reqtype_t reqtype; // 67:64 // Request Type + logic [5:0] rsvd63_58; // 63:58 // X + logic [41:0] addr; // 57:16 // Address + logic [15:0] mdata; // 15:0 // Metadata + } TxHdr_t; + parameter CCIP_TX_HDR_WIDTH = $bits(TxHdr_t); + + typedef logic [CCIP_TX_HDR_WIDTH-1:0] logic_cast_TxHdr_t; + + + /* + * Config MMIO Header + */ + // MMIO Header specifics + parameter int CCIP_CFGHDR_ADDR_WIDTH = 18; + parameter int CCIP_CFGHDR_INDEX_WIDTH = 16; + parameter int CCIP_CFGHDR_TID_WIDTH = 9; + + // CfgHdr + typedef struct packed { + logic [CCIP_CFGHDR_INDEX_WIDTH-1:0] index; // 27:12 + logic [1:0] len; // 11:10 + logic rsvd9; // 9 + logic [CCIP_CFGHDR_TID_WIDTH-1:0] tid; // 8:0 + } CfgHdr_t; + parameter CCIP_CFG_HDR_WIDTH = $bits(CfgHdr_t); + + typedef logic [CCIP_CFG_HDR_WIDTH-1:0] logic_cast_CfgHdr_t; + + + // MMIO header + typedef struct packed { + logic [8:0] tid; + } MMIOHdr_t; + parameter CCIP_MMIO_TID_WIDTH = $bits(MMIOHdr_t); + + typedef logic [CCIP_MMIO_TID_WIDTH-1:0] logic_cast_MMIOHdr_t; + + + /* + * Umsg header (received when UMsg is received) + * Enabled only for integrated + */ + `ifdef ASE_ENABLE_UMSG_FEATURE + typedef struct packed { + logic [1:0] rsvd_27_26; // 27:26 // Reserved + logic rsvd25; // 25 // Poison bit + logic [4:0] rsvd_24_20; // 24:20 // Reserved + logic [3:0] resp_type; // 19:16 // Response type + logic umsg_type; // 15 // Umsg type + logic [8:0] rsvd_14_6; // 14:6 // Reserved + logic [5:0] umsg_id; // 5:0 // Umsg Id + } UMsgHdr_t; + parameter ASE_UMSG_HDR_WIDTH = $bits(UMsgHdr_t); + + typedef logic [ASE_UMSG_HDR_WIDTH-1:0] logic_cast_UMsgHdr_t; + `endif + + + // CmpXchg header (received from a Compare-Exchange operation) + // typedef struct packed { + // ccip_vc_t vc_used; // 27:26 + // logic rsvd25; // 25 + // logic hitmiss; // 24 + // logic success; // 23 + // logic [2:0] rsvd_22_20; // 22:20 + // ccip_resptype_t resptype; // 19:16 + // logic [15:0] mdata; // 15:0 + // } Atomics_t; + // parameter CCIP_CMPXCHG_HDR_WIDTH = $bits(Atomics_t); + + // Config channel + parameter CCIP_MMIO_ADDR_WIDTH = 16; + parameter CCIP_MMIO_INDEX_WIDTH = 14; + parameter CCIP_MMIO_RDDATA_WIDTH = 64; + + + /* + * Interrupt request and response headers specific to ASE + */ + // `ifdef ASE_ENABLE_INTR_FEATURE + // // Interrupt request header + // typedef struct packed { + // logic [11:0] rsvd_79_68; // 79:68 // Reserved + // ccip_reqtype_t req_type; // 67:64 // Type + // logic [60:0] rsvd_63_3; // 63:3 // reserved + // logic [2:0] id; // 2:0 // Intr vector + // } IntrReq_t; + + // // Interrupt response header + // typedef struct packed { + // logic [7:0] rsvd1; // 27:20 // reserved, don't care + // ccip_resptype_t resp_type; // 19:16 // Response type + // logic [12:0] rsvd_15_3; // 15:3 // reserved, don't care + // logic [2:0] id; // 2:0 // Vector + // } IntrRsp_t; + // `endif + + + /* + * Wrapped headers with channel Id + * ASE's internal datatype used for bookkeeping + */ + // Wrap TxHdr_t with channel_id + typedef struct packed { + logic channel_id; + TxHdr_t txhdr; + } ASETxHdr_t; + parameter ASE_TX_HDR_WIDTH = $bits(ASETxHdr_t); + + // Wrap RxHdr_t with channel_id + typedef struct packed { + logic channel_id; + RxHdr_t rxhdr; + } ASERxHdr_t; + parameter ASE_RX_HDR_WIDTH = $bits(ASERxHdr_t); + + + /* + * FIFO depth bit-width + * Enter 'n' here, where n = log_2(FIFO_DEPTH) & n is an integer + */ + parameter ASE_FIFO_DEPTH_NUMBITS = 8; + + + /* + * Latency Scoreboard generics + */ + // Number of transactions in latency scoreboard + parameter LATBUF_NUM_TRANSACTIONS = 32; + // Radix of latency scoreboard radix + parameter LATBUF_COUNT_WIDTH = $clog2(LATBUF_NUM_TRANSACTIONS) + 1; + // ASE_fifo full threshold inside latency scoreboard + parameter LATBUF_FULL_THRESHOLD = LATBUF_NUM_TRANSACTIONS - 5; + // Radix of ASE_fifo (subcomponent in latency scoreboard) + parameter LATBUF_DEPTH_BASE2 = $clog2(LATBUF_NUM_TRANSACTIONS); + // Wait station timer width + parameter LATBUF_TIMER_WIDTH = 9; + // Latency buffer TID width + parameter LATBUF_TID_WIDTH = 32; + + // ASE Response FIFO specifics + parameter ASE_RSPFIFO_DEPTH = 256; + parameter ASE_RSPFIFO_COUNT_WIDTH = $clog2(ASE_RSPFIFO_DEPTH); + parameter ASE_RSPFIFO_ALMFULL_THRESH = ASE_RSPFIFO_DEPTH - 10; + + + /* + * CCI Transaction packet + */ + typedef struct { + int mode; + int qw_start; + int mdata; + longint cl_addr; + longint qword[8]; + int resp_channel; + int intr_id; + int success; + } cci_pkt; + + parameter CCIPKT_WRITE_MODE = 32'h1010; + parameter CCIPKT_READ_MODE = 32'h2020; + parameter CCIPKT_WRFENCE_MODE = 32'hFFFF; + parameter CCIPKT_ATOMIC_MODE = 32'h8080; + parameter CCIPKT_INTR_MODE = 32'h4040; + + + /* + * ASE config structure + * This will reflect ase.cfg + */ + typedef struct { + int ase_mode; + int ase_timeout; + int ase_num_tests; + int enable_reuse_seed; + int ase_seed; + int enable_cl_view; + int usr_tps; + int phys_memory_available_gb; + } ase_cfg_t; + ase_cfg_t cfg; + + /* + * MMIO packet + */ + typedef struct { + int tid; + int write_en; + int width; + int addr; + longint qword[8]; + int resp_en; + } mmio_t; + + // Request types + parameter int MMIO_WRITE_REQ = 32'hAA88; + parameter int MMIO_READ_REQ = 32'hBB88; + + // Length + parameter int MMIO_WIDTH_32 = 32; + parameter int MMIO_WIDTH_64 = 64; + + + /* + * UMSG Hint/Data state machine + * - Data structure defined to control UMsg behavior + * Enabled only for integrated configuration + */ + `ifdef ASE_ENABLE_UMSG_FEATURE + // Number of UMSGs per AFU + parameter int NUM_UMSG_PER_AFU = 8; + + // Umsg command packet + typedef struct { + int id; + int hint; + longint qword[8] ; + } umsgcmd_t; + + + // UMSG control states + typedef enum {UMsgIdle, UMsgHintWait, UMsgSendHint, UMsgDataWait, UMsgSendData} + UMsg_StateEnum; + + // UMSG control structure + typedef struct { + logic [`UMSG_DELAY_TIMER_LOG2-1:0] hint_timer; + logic [`UMSG_DELAY_TIMER_LOG2-1:0] data_timer; + logic line_accessed; + logic hint_enable; + logic hint_ready; + logic hint_pop; + logic data_ready; + logic data_pop; + UMsg_StateEnum state; + } umsg_t; + + `endif + + + /* + * FUNCTION: Unpack qwords[0:7] to data vector + */ + function logic [CCIP_DATA_WIDTH-1:0] unpack_ccipkt_to_vector (input cci_pkt pkt); + logic [CCIP_DATA_WIDTH-1:0] ret; + int i; + begin + ret[ 63:00 ] = pkt.qword[0] ; + ret[ 127:64 ] = pkt.qword[1] ; + ret[ 191:128 ] = pkt.qword[2] ; + ret[ 255:192 ] = pkt.qword[3] ; + ret[ 319:256 ] = pkt.qword[4] ; + ret[ 383:320 ] = pkt.qword[5] ; + ret[ 447:384 ] = pkt.qword[6] ; + ret[ 511:448 ] = pkt.qword[7] ; + return ret; + end + endfunction + + /* + * FUNCTION: Pack data vector into qwords[0:7] + */ + // function automatic void pack_vector_to_ccipkt (input [511:0] vec, + // ref cci_pkt pkt); + // begin + // pkt.qword[0] = vec[ 63:00 ]; + // pkt.qword[1] = vec[ 127:64 ]; + // pkt.qword[2] = vec[ 191:128 ]; + // pkt.qword[3] = vec[ 255:192 ]; + // pkt.qword[4] = vec[ 319:256 ]; + // pkt.qword[5] = vec[ 383:320 ]; + // pkt.qword[6] = vec[ 447:384 ]; + // pkt.qword[7] = vec[ 511:448 ]; + // end + // endfunction + + + /* + * FUNCTION: conv_gbsize_to_num_bytes + * Converts GB size to num_bytes + */ + function automatic longint conv_gbsize_to_num_bytes(int gb_size); + begin + return (gb_size*1024*1024*1024); + end + endfunction + + + /* + * FUNCTION: Return absolute value + */ + function automatic int abs_val(int num); + begin + return (num < 0) ? ~num : num; + end + endfunction + + + /* + * CCI-P package specific request/response type check functions + * ------------------------------------------------------------ + * - These functions are meant only for CCI-P header types + */ + // Is a Read Request + function logic isCCIPRdLineRequest(t_ccip_c0_req req); + begin + if ((req == eREQ_RDLINE_I)||(req == eREQ_RDLINE_S)) + return 1; + else + return 0; + end + endfunction + + // Is a Write Request + function logic isCCIPWrLineRequest(t_ccip_c1_req req); + begin + if ((req == eREQ_WRLINE_I)||(req == eREQ_WRLINE_M)||(req == eREQ_WRPUSH_I)) + return 1; + else + return 0; + end + endfunction + + // Is a Write Fence Request + function logic isCCIPWrFenceRequest(t_ccip_c1_req req); + begin + if (req == eREQ_WRFENCE) + return 1; + else + return 0; + end + endfunction + + // Is a Intr Request + function logic isCCIPIntrRequest(t_ccip_c1_req req); + begin + if (req == eREQ_INTR) + return 1; + else + return 0; + end + endfunction + + // Is a Read Response + function logic isCCIPRdLineResponse(t_ccip_c0_rsp rsp); + begin + if (rsp == eRSP_RDLINE) + return 1; + else + return 0; + end + endfunction + + // Is a Umsg Response (integrated only) +`ifdef ASE_ENABLE_UMSG_FEATURE + function logic isCCIPUmsgResponse(t_ccip_c0_rsp rsp); + begin + if (rsp == eRSP_UMSG) + return 1; + else + return 0; + end + endfunction +`endif + + // Is a Write Response + function logic isCCIPWrLineResponse(t_ccip_c1_rsp rsp); + begin + if (rsp == eRSP_WRLINE) + return 1; + else + return 0; + end + endfunction + + // Is a Write Fence Response + function logic isCCIPWrFenceResponse(t_ccip_c1_rsp rsp); + begin + if (rsp == eRSP_WRFENCE) + return 1; + else + return 0; + end + endfunction + + /* + * Interrupt functions, enabled on discrete only + */ +`ifdef ASE_ENABLE_INTR_FEATURE + // isCCIPInterruptRequest + function automatic logic isCCIPInterruptRequest(t_ccip_c1_req req); + begin + if (req == eREQ_INTR) + return 1; + else + return 0; + end + endfunction // isInterruptRequest + + // isCCIPInterruptResponse + function automatic logic isCCIPInterruptResponse(t_ccip_c1_rsp resp); + begin + if (resp == eRSP_INTR) + return 1; + else + return 0; + end + endfunction // isInterruptResponse + +`endif + + + /* + * ASE Read/Write Request/Response type checks + * -------------------------------------------- + * - These functions can only by ASE specific headers + * + */ + // isReadRequest + function automatic logic isReadRequest(TxHdr_t hdr); + begin + if ((hdr.reqtype == ASE_RDLINE_I)||(hdr.reqtype == ASE_RDLINE_S)) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isReadRequest + + // isReadResponse + function automatic logic isReadResponse(RxHdr_t hdr); + begin + if (hdr.resptype == ASE_RD_RSP ) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isReadResponse + + // isWriteRequest + function automatic logic isWriteRequest(TxHdr_t hdr); + begin + if ((hdr.reqtype == ASE_WRLINE_I)||(hdr.reqtype == ASE_WRLINE_M)||(hdr.reqtype == ASE_WRPUSH)) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isWriteRequest + + // isWriteResponse + function automatic logic isWriteResponse(RxHdr_t hdr); + begin + if (hdr.resptype == ASE_WR_RSP ) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isWriteResponse + + // isWrFenceRequest + function automatic logic isWrFenceRequest(TxHdr_t hdr); + begin + if (hdr.reqtype == ASE_WRFENCE) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isWrFenceRequest + + // isWrFenceResponse + function automatic logic isWrFenceResponse(RxHdr_t hdr); + begin + if (hdr.resptype == ASE_WRFENCE_RSP) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isWrFenceResponse + +`ifdef ASE_ENABLE_INTR_FEATURE + // isIntrRequest + function automatic logic isIntrRequest(TxHdr_t hdr); + begin + if (hdr.reqtype == ASE_INTR_REQ) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isIntrResponse + function automatic logic isIntrResponse(RxHdr_t hdr); + begin + if (hdr.resptype == ASE_INTR_RSP) begin + return 1; + end + else begin + return 0; + end + end + endfunction + +`endif + + // ------------------------------------------- // + // Virtual channel ease functions + // ------------------------------------------- // + // isVL0Request + function automatic logic isVL0Request(TxHdr_t hdr); + begin + if (hdr.vc == VC_VL0) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVHxRequest + function automatic logic isVHxRequest(TxHdr_t hdr); + begin + if ((hdr.vc == VC_VH0)||(hdr.vc == VC_VH1)) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVH0Request + function automatic logic isVH0Request(TxHdr_t hdr); + begin + if (hdr.vc == VC_VH0) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVH1Request + function automatic logic isVH1Request(TxHdr_t hdr); + begin + if (hdr.vc == VC_VH1) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVARequest + function automatic logic isVARequest(TxHdr_t hdr); + begin + if (hdr.vc == VC_VA) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVL0Response + function automatic logic isVL0Response(RxHdr_t hdr); + begin + if (hdr.vc_used == VC_VL0) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVHxResponse + function automatic logic isVHxResponse(RxHdr_t hdr); + begin + if ((hdr.vc_used == VC_VH0)||(hdr.vc_used == VC_VH1)) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVH0Response + function automatic logic isVH0Response(RxHdr_t hdr); + begin + if (hdr.vc_used == VC_VH0) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + // isVH1Response + function automatic logic isVH1Response(RxHdr_t hdr); + begin + if (hdr.vc_used == VC_VH1) begin + return 1; + end + else begin + return 0; + end + end + endfunction + + + /* + * Pretty print TXHdr & RxHdr + */ + // Print channel (Debug) + function string ase_channel_type (ccip_vc_t vc_sel); + begin + case (vc_sel) + VC_VA : return "VA "; + VC_VL0 : return "VL0"; + VC_VH0 : return "VH0"; + VC_VH1 : return "VH1"; + endcase + end + endfunction // ase_channel_type + + // Print clnum (Debug) + function string ase_print_clnum (ccip_len_t num); + begin + case (num) + ASE_1CL: return "#1CL"; + ASE_2CL: return "#2CL"; + ASE_3CL: return "#3CL"; + ASE_4CL: return "#4CL"; + endcase + end + endfunction // ase_print_clnum + + // Print pack status (Debug) + function string ase_pack_status(logic rx_fmt); + begin + case (rx_fmt) + 0 : return "nopack"; + 1 : return "pack"; + endcase + end + endfunction // ase_pack_status + + // Print Reqtype (Debug) + function string ase_print_reqtype(ccip_reqtype_t req); + begin + case (req) +`ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_REQ: return "Intr"; +`endif + ASE_RDLINE_S : return "RdS"; + ASE_RDLINE_I : return "RdI"; + ASE_WRLINE_I : return "WrI"; + ASE_WRLINE_M : return "WrM"; + ASE_WRPUSH : return "WrP"; + ASE_WRFENCE : return "WrF"; + default : return "**FAIL**"; + endcase + end + endfunction // ase_print_reqtype + + // Print Resptype (Debug) + function string ase_print_resptype(ccip_resptype_t resp); + begin + case (resp) +`ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_RSP : return "Intr"; +`endif +`ifdef ASE_ENABLE_UMSG_FEATURE + ASE_UMSG : return "UMsg"; +`endif + ASE_RD_RSP : return "Rd"; + ASE_WR_RSP : return "Wr"; + ASE_WRFENCE_RSP: return "WrF"; + default : return "**FAIL**"; + endcase + end + endfunction + + // TxHdr print + function automatic string return_txhdr(TxHdr_t hdr); + string str; + begin + $sformat(str, "TxHdr = {%s,%s,%s,%x,%04x}", ase_print_reqtype(hdr.reqtype), ase_print_clnum(hdr.len), ase_channel_type(hdr.vc), hdr.addr, hdr.mdata); + return str; + end + endfunction + + // RxHdr print + function automatic string return_rxhdr(RxHdr_t hdr); + string str; + begin + $sformat(str, "RxHdr = {%s,%s,%s,%04x,%s}", ase_print_resptype(hdr.resptype), ase_print_clnum(hdr.clnum), ase_channel_type(hdr.vc_used), hdr.mdata, ase_pack_status(hdr.format)); + return str; + end + endfunction + + + /* + * Transaction count management + */ + // VC Count struct + typedef struct packed { + int va; + int vl0; + int vh0; + int vh1; + } txn_vc_counts; + + // MCL count struct + typedef struct packed { + int mcl0; + int mcl1; + int mcl3; + } txn_mcl_counts; + + + /* + * Hazard checker interface + */ + // Hazard event packet + typedef struct packed { + logic [LATBUF_TID_WIDTH-1:0] tid; + logic valid; + TxHdr_t hdr; + } ase_haz_pkt; + + + // Unified interface for read/write insert/delete + typedef struct packed { + ase_haz_pkt read_in; + ase_haz_pkt read_out; + ase_haz_pkt write_in; + ase_haz_pkt write_out; + } ase_haz_if; + + + /* + * ASE protocol sniff codes + */ + // parameter SNIFF_CODE_WIDTH = 5; + parameter SNIFF_VECTOR_WIDTH = 32; + // 2**SNIFF_CODE_WIDTH; + + // Error code indices + typedef enum { + SNIFF_NO_ERROR = 0, + // ------------ C2TX -------------- // + MMIO_RDRSP_TIMEOUT = 1, + MMIO_RDRSP_UNSOLICITED = 2, + MMIO_RDRSP_RESET_IGNORED_WARN = 3, + MMIO_RDRSP_XZ_FOUND_WARN = 4, + // ------------ C0TX ------------ // + SNIFF_C0TX_INVALID_REQTYPE = 5, + SNIFF_C0TX_OVERFLOW = 6, + SNIFF_C0TX_ADDRALIGN_2_ERROR = 7, + SNIFF_C0TX_ADDRALIGN_4_ERROR = 8, + SNIFF_C0TX_RESET_IGNORED_WARN = 9, + SNIFF_C0TX_XZ_FOUND_WARN = 10, + SNIFF_C0TX_3CL_REQUEST = 11, + SNIFF_C0TX_ADDR_ZERO_WARN = 12, + SNIFF_C0TX_UNEXP_ADDR = 13, + // ------------ C1TX -------------- // + SNIFF_C1TX_INVALID_REQTYPE = 14, + SNIFF_C1TX_OVERFLOW = 15, + SNIFF_C1TX_ADDRALIGN_2_ERROR = 16, + SNIFF_C1TX_ADDRALIGN_4_ERROR = 17, + SNIFF_C1TX_RESET_IGNORED_WARN = 18, + SNIFF_C1TX_XZ_FOUND_WARN = 19, + SNIFF_C1TX_UNEXP_VCSEL = 20, + SNIFF_C1TX_UNEXP_MDATA = 21, + SNIFF_C1TX_UNEXP_ADDR = 22, + SNIFF_C1TX_UNEXP_CLLEN = 23, + SNIFF_C1TX_UNEXP_REQTYPE = 24, + SNIFF_C1TX_SOP_NOT_SET = 25, + SNIFF_C1TX_SOP_SET_MCL1TO3 = 26, + SNIFF_C1TX_3CL_REQUEST = 27, + SNIFF_C1TX_WRFENCE_IN_MCL1TO3 = 28, + SNIFF_C1TX_ADDR_ZERO_WARN = 29, + SNIFF_C1TX_WRFENCE_SOP_SET = 30 + // --------------------------------- // + } sniff_code_t; + + /* + * outoforder_wrf_channel Transaction checker block + */ + `ifdef ASE_DEBUG + typedef struct packed { + logic [0:3] rxout_valid; + ccip_vc_t virt_channel; + } ccip_txn_t; + `endif + + /* + * Other Macros + */ + // Get random number from range + `define get_random_from_range(low, high)\ + ($random() % (high + 1 - low) + low) + + +endpackage diff --git a/ase/rtl/ase_svfifo.sv b/ase/rtl/ase_svfifo.sv new file mode 100644 index 000000000000..067854a69c98 --- /dev/null +++ b/ase/rtl/ase_svfifo.sv @@ -0,0 +1,141 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Name: ase_svfifo + * A systemverilog built-in compatible SVFIFO, that is + * potentially faster + * Language : System{Verilog} + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * FIFO implementation for use in ASE only + * Generics: + * - DEPTH_BASE2 : Radix of element array, used for counting elements + * - ALMFULL_THRESH : AlmostFull threshold + * + * Description: + * - WRITE: Data is written when write_enable is HIGH + * - READ : Data is available in next clock it is in RAM + * Empty is an ASYNC signal & must be check + * read_enable must be used asynchronously with EMPTY signal + * - Overflow and underflow signals are asserted + * + */ + +module ase_svfifo + #( + parameter int DATA_WIDTH = 64, + parameter int DEPTH_BASE2 = 8, + parameter int ALMFULL_THRESH = 5 + ) + ( + input logic clk, + input logic rst, + input logic wr_en, + input logic [DATA_WIDTH-1:0] data_in, + input logic rd_en, + output logic [DATA_WIDTH-1:0] data_out, + output logic data_out_v, + output logic alm_full, + output logic full, + output logic empty, + output logic [DEPTH_BASE2:0] count, + output logic overflow, + output logic underflow + ); + + // Calculate depth + parameter int DEPTH = 2**DEPTH_BASE2; + + // FIFO instance + logic [DATA_WIDTH-1:0] fifo[$:DEPTH-1]; + + always @(posedge clk) begin + if (wr_en) begin + fifo.push_back(data_in); + end + end + + // Empty signal + always @(posedge clk) begin + if (fifo.size() == 0) begin + empty <= 1; + end + else begin + empty <= 0; + end + end + + // Full signal + always @(posedge clk) begin + if (fifo.size() == (DEPTH-1)) begin + full <= 1; + end + else begin + full <= 0; + end + end + + // Almfull signal + always @(posedge clk) begin + if (fifo.size() >= (DEPTH - ALMFULL_THRESH)) begin + alm_full <= 1; + end + else begin + alm_full <= 0; + end + end + + // Read process + always @(posedge clk) begin + if (rst) begin + data_out_v <= 0; + end + else if (rd_en && (fifo.size() != 0)) begin + data_out_v <= 1; + data_out <= fifo.pop_front(); + end + else begin + data_out_v <= 0; + end + end + + // Overflow + assign overflow = full & wr_en; + + // Underflow + assign underflow = empty & rd_en; + + // Count + always @(posedge clk) begin + count <= fifo.size(); + end + +endmodule diff --git a/ase/rtl/ase_top.sv b/ase/rtl/ase_top.sv new file mode 100644 index 000000000000..b9e810666f18 --- /dev/null +++ b/ase/rtl/ase_top.sv @@ -0,0 +1,173 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: ASE top-level + * (hides ASE machinery, makes finding cci_std_afu easy) + * Language : System{Verilog} + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * **************************************************************************/ + +import ccip_if_pkg::*; + +`timescale 1ns/1ns + +module ase_top(); + + + logic pClkDiv4; + logic pClkDiv2; + logic pClk; + logic pck_cp2af_softReset; + + logic uClk_usr; + logic uClk_usrDiv2; + + t_if_ccip_Tx pck_af2cp_sTx; + t_if_ccip_Rx pck_cp2af_sRx; + + logic [1:0] pck_cp2af_pwrState; // CCI-P AFU Power State + logic pck_cp2af_error; // CCI-P Protocol Error Detected + +`ifdef FPGA_PLATFORM_DISCRETE + wire ddr4a_clk; + + wire ddr4a_waitrequest_n; + wire [511:0] ddr4a_readdata; + wire ddr4a_readdatavalid; + wire [6:0] ddr4a_burstcount; + wire [511:0] ddr4a_writedata; + wire [25:0] ddr4a_address; + wire ddr4a_write; + wire ddr4a_read; + wire [63:0] ddr4a_byteenable; + wire [1:0] DDR4a_response; + wire DDR4a_writeresponsevalid; + + wire ddr4b_waitrequest_n; + wire [511:0] ddr4b_readdata; + wire ddr4b_readdatavalid; + wire [6:0] ddr4b_burstcount; + wire [511:0] ddr4b_writedata; + wire [25:0] ddr4b_address; + wire ddr4b_write; + wire ddr4b_read; + wire [63:0] ddr4b_byteenable; + wire [1:0] ddr4b_response; + wire ddr4b_writeresponsevalid; +`endif + + // CCI-P emulator + ccip_emulator ccip_emulator + ( + .pClkDiv4 (pClkDiv4 ), + .pClkDiv2 (pClkDiv2 ), + .pClk (pClk ), + .uClk_usr (uClk_usr ), + .uClk_usrDiv2 (uClk_usrDiv2 ), + .pck_cp2af_softReset (pck_cp2af_softReset ), + .pck_cp2af_pwrState (pck_cp2af_pwrState ), + .pck_cp2af_error (pck_cp2af_error ), + .pck_af2cp_sTx (pck_af2cp_sTx ), + .pck_cp2af_sRx (pck_cp2af_sRx ) + ); + + + // CCIP AFU + ccip_std_afu ccip_std_afu + ( + .pClkDiv4 (pClkDiv4 ), + .pClkDiv2 (pClkDiv2 ), + .pClk (pClk ), + .uClk_usr (uClk_usr ), + .uClk_usrDiv2 (uClk_usrDiv2 ), + .pck_cp2af_softReset (pck_cp2af_softReset ), + .pck_cp2af_pwrState (pck_cp2af_pwrState ), + .pck_cp2af_error (pck_cp2af_error ), +`ifdef FPGA_PLATFORM_DISCRETE + .DDR4_USERCLK (ddr4a_clk ), + .DDR4a_writedata (ddr4a_writedata ), + .DDR4a_readdata (ddr4a_readdata ), + .DDR4a_address (ddr4a_address ), + .DDR4a_waitrequest (~ddr4a_waitrequest_n), + .DDR4a_write (ddr4a_write ), + .DDR4a_read (ddr4a_read ), + .DDR4a_byteenable (ddr4a_byteenable ), + .DDR4a_burstcount (ddr4a_burstcount ), + .DDR4a_readdatavalid (ddr4a_readdatavalid ), + + .DDR4b_writedata (ddr4b_writedata ), + .DDR4b_readdata (ddr4b_readdata ), + .DDR4b_address (ddr4b_address ), + .DDR4b_waitrequest (~ddr4b_waitrequest_n), + .DDR4b_write (ddr4b_write ), + .DDR4b_read (ddr4b_read ), + .DDR4b_byteenable (ddr4b_byteenable ), + .DDR4b_burstcount (ddr4b_burstcount ), + .DDR4b_readdatavalid (ddr4b_readdatavalid ), +`endif + .pck_af2cp_sTx (pck_af2cp_sTx ), + .pck_cp2af_sRx (pck_cp2af_sRx ) + ); + + // t_ccip_c0_RspAtomicHdr DBG_C0RxAtomic; + // assign DBG_C0RxAtomic = t_ccip_c0_RspAtomicHdr'(pck_cp2af_sRx.c0.hdr); + +`ifdef FPGA_PLATFORM_DISCRETE + // emif model + ed_sim ed_sim ( + .ddr4a_waitrequest_n (ddr4a_waitrequest_n), + .ddr4a_read (ddr4a_read ), + .ddr4a_write (ddr4a_write ), + .ddr4a_address (ddr4a_address ), + .ddr4a_readdata (ddr4a_readdata ), + .ddr4a_writedata (ddr4a_writedata ), + .ddr4a_burstcount (ddr4a_burstcount ), + .ddr4a_byteenable (ddr4a_byteenable ), + .ddr4a_readdatavalid (ddr4a_readdatavalid), + .ddr4a_userclk_clk (ddr4a_clk ), + + .ddr4b_waitrequest_n (ddr4b_waitrequest_n), + .ddr4b_read (ddr4b_read ), + .ddr4b_write (ddr4b_write ), + .ddr4b_address (ddr4b_address ), + .ddr4b_readdata (ddr4b_readdata ), + .ddr4b_writedata (ddr4b_writedata ), + .ddr4b_burstcount (ddr4b_burstcount ), + .ddr4b_byteenable (ddr4b_byteenable ), + .ddr4b_readdatavalid (ddr4b_readdatavalid) + ); +`endif + + t_ccip_c0_ReqMmioHdr DBG_C0RxMMIO; + assign DBG_C0RxMMIO = t_ccip_c0_ReqMmioHdr'(pck_cp2af_sRx.c0.hdr); + +endmodule // ase_top diff --git a/ase/rtl/ccip_checker.sv b/ase/rtl/ccip_checker.sv new file mode 100644 index 000000000000..f2c7b7c08075 --- /dev/null +++ b/ase/rtl/ccip_checker.sv @@ -0,0 +1,1282 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: CCI Sniffer (Rules checker, Hazard detector and warning) + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * Description: + * ************ + * XZ checker: + * Checks the TX signals in AFU to see if 'X' or 'z' is validated. ASE + * does not validated 'X', 'z' on RX channels, these will not be + * checked. When a violation is discovered, it will be printed in a + * message, + * + * Hazard sniffer: + * In the strictest sense, if there are multiple transactions to a + * certain cache line + * + * All warnings are logged in ccip_warning_and_errors.txt + */ + +import ase_pkg::*; +import ccip_if_pkg::*; +`include "platform.vh" + +// `define STANDALONE_DEBUG + +module ccip_checker + #( + parameter ERR_LOGNAME = "ccip_warning_and_errors.txt" + ) + ( + // Configure enable + input logic finish_logger, + input logic init_sniffer, + input logic ase_reset, + // -------------------------------------------------------- // + // Channel overflow/realfull checks + input logic cf2as_ch0_realfull, + input logic cf2as_ch1_realfull, + // -------------------------------------------------------- // + // Hazard/Indicator Signals // + input ase_haz_if haz_if, + output logic [SNIFF_VECTOR_WIDTH-1:0] error_code, + // -------------------------------------------------------- // + // CCI-P interface // + input logic clk, + input logic SoftReset, + input t_if_ccip_Rx ccip_rx, + input t_if_ccip_Tx ccip_tx + ); + logic [SNIFF_VECTOR_WIDTH-1:0] error_code_q; + + /* + * Function Request type checker + */ + // isCCIPReadRequest + function automatic logic isCCIPReadRequest(t_ccip_c0_ReqMemHdr hdr); + begin + if (hdr.req_type inside {eREQ_RDLINE_S, eREQ_RDLINE_I}) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isCCIPReadRequest + + + // isCCIPWriteRequest + function automatic logic isCCIPWriteRequest(t_ccip_c1_ReqMemHdr hdr); + begin + if (hdr.req_type inside {eREQ_WRLINE_M, eREQ_WRLINE_I, eREQ_WRPUSH_I}) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isCCIPWriteRequest + + + // isCCIPWrFenceRequest + function automatic logic isCCIPWrFenceRequest(t_ccip_c1_ReqMemHdr hdr); + begin + if (ccip_tx.c1.hdr.req_type == eREQ_WRFENCE) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isCCIPWrFenceRequest + + + // isEqualsXorZ + function automatic logic isEqualsXorZ(reg inp); + begin + if ((inp === 1'bX)||(inp === 1'bx)) begin + return 1; + end + else begin + return 0; + end + end + endfunction // isEqualsXorZ + + + /* + * File descriptors, codes etc + */ + int fd_errlog; + logic logfile_created; + logic init_sniffer_q; + + // Watch init_sniffer + always @(posedge clk) begin + init_sniffer_q <= init_sniffer; + end + + // Initialize sniffer + always @(posedge clk) begin + + // Indicate logfile created + if (init_sniffer) begin + logfile_created <= 0; + error_code_q[SNIFF_NO_ERROR]=1'b0; + end + else + decode_error_code(0, SNIFF_NO_ERROR); + + // Print that checker is running + if (~init_sniffer && init_sniffer_q) begin + $display (" [SIM] Protocol Checker initialized"); + end + end + + // FD open + function automatic void open_logfile(); + begin + fd_errlog = $fopen(ERR_LOGNAME, "w"); + logfile_created = 1; + end + endfunction + + // Watch logfile and close until finished + initial begin + // Wait until logfile exists + wait (logfile_created == 1); + + // Wait until finish logger + wait (finish_logger == 1); + + // Close loggers + $display (" [SIM] Closing Protocol checker"); + $fclose(fd_errlog); + end + + + /* + * Controlled kill of simulation + */ + logic simkill_en = 0; + int simkill_cnt; + + // Print and simkill + function void print_and_simkill(); + begin + `BEGIN_RED_FONTCOLOR; + $display(" [ERROR] %d : Simulation will end now", $time); + `END_RED_FONTCOLOR; + $fwrite(fd_errlog, " [ERROR] %d : Simulation will end now\n", $time); + simkill_en = 1; + end + endfunction + + // Enumeration of simulation states + typedef enum { + SimkillIdle, + SimkillCountdown, + SimkillNow + } SimkillEnumStates; + SimkillEnumStates simkill_state; + + // Simkill countdown and issue simkill + always @(posedge clk) begin + if (ase_reset) begin + simkill_cnt <= 20; + simkill_state <= SimkillIdle; + end + else begin + case (simkill_state) + + SimkillIdle: + begin + simkill_cnt <= 20; + if (simkill_en) begin + simkill_state <= SimkillCountdown; + end + else begin + simkill_state <= SimkillIdle; + end + end + + SimkillCountdown: + begin + simkill_cnt <= simkill_cnt - 1; + if (simkill_cnt <= 0) begin + simkill_state <= SimkillNow; + end + else begin + simkill_state <= SimkillCountdown; + end + end + + SimkillNow: + begin + simkill_state <= SimkillNow; +`ifndef STANDALONE_DEBUG + start_simkill_countdown(); +`endif + end + + default: + begin + simkill_state <= SimkillIdle; + end + + endcase + end + end + + /* + * Helper functions + */ + // Print string and write to file + function void print_message_and_log(input logic warn_only, + input string logstr); + begin + // If logfile doesnt exist it, create it + // always@(error) + if (logfile_created == 0) begin + open_logfile(); + end + // Write log + if (warn_only == 1) begin + `BEGIN_RED_FONTCOLOR; + $display(" [WARN] %d : %s", $time, logstr); + `END_RED_FONTCOLOR; + $fwrite(fd_errlog, " [WARN] %d : %s\n", $time, logstr); + end + else begin + `BEGIN_RED_FONTCOLOR; + $display(" [ERROR] %d : %s", $time, logstr); + `END_RED_FONTCOLOR; + $fwrite(fd_errlog, " [ERROR] %d : %s\n", $time, logstr); + print_and_simkill(); + end + end + endfunction + + + // Trigger Error bit by index + always@(posedge clk) + begin + if (SoftReset) + error_code=32'b0; + else + error_code=error_code_q; + end + + // Error code enumeration + task decode_error_code( + input logic init, + input sniff_code_t code + ); + string errcode_str; + string log_str; + begin + if (init) begin + error_code_q[code]=1'b0; + end + else begin + errcode_str = code.name; + case (code) + // C0TX - Invalid request type + SNIFF_C0TX_INVALID_REQTYPE: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr was issued with an invalid reqtype !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - Overflow check + SNIFF_C0TX_OVERFLOW: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] Overflow detected on CCI-P Channel 0 !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - 2CL address alignment check + SNIFF_C0TX_ADDRALIGN_2_ERROR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr Multi-line address request is not aligned 2-CL aligned (C0TxHdr.addr[0] != 1'b0) !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - 4CL address alignment check + SNIFF_C0TX_ADDRALIGN_4_ERROR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr Multi-line address request is not aligned 4-CL aligned (C0TxHdr.addr[1:0] != 2'b00) !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - Reset ignored + SNIFF_C0TX_RESET_IGNORED_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr was issued when AFU Reset is HIGH !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C0TX - X or Z found [Warning only] + SNIFF_C0TX_XZ_FOUND_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr request contained a 'Z' or 'X' !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C0TX - 3CL Read Request + SNIFF_C0TX_3CL_REQUEST: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr 3-CL request issued. This is illegal !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - Address found to be zero + SNIFF_C0TX_ADDR_ZERO_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C0TxHdr address was ZERO.. this will cause simulation failure", errcode_str); + print_message_and_log(1, log_str); + end + SNIFF_C0TX_UNEXP_ADDR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] Unexpected C0TxHdr address . this will cause simulation failure", errcode_str); + print_message_and_log(1, log_str); + end + // C1TX - Invalid request type + SNIFF_C1TX_INVALID_REQTYPE: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr was issued with an invalid reqtype !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - Overflow check + SNIFF_C1TX_OVERFLOW: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] Overflow detected on CCI-P Channel 1 !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - 2CL address alignment check + SNIFF_C1TX_ADDRALIGN_2_ERROR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr Multi-line address request is not aligned 2-CL aligned (C1TxHdr.addr[0] != 1'b0) !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - 4CL address alignment check + SNIFF_C1TX_ADDRALIGN_4_ERROR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr Multi-line address request is not aligned 4-CL aligned (C1TxHdr.addr[1:0] != 2'b00) !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - Reset ignored + SNIFF_C1TX_RESET_IGNORED_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr was issued when AFU Reset is HIGH !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C1TX - X or Z found [Warning only] + SNIFF_C1TX_XZ_FOUND_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr request contained a 'Z' or 'X' !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C1Tx - Unexpected VC changes + SNIFF_C1TX_UNEXP_VCSEL: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr VC-selection must not change in between multi-line beat !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C1Tx - Unexpected MDATA changes [Warning only] + SNIFF_C1TX_UNEXP_MDATA: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr MDATA changed between multi-line beat !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C1Tx - Unexpected address changes + SNIFF_C1TX_UNEXP_ADDR: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr multi-line beat found unexpected address - addr[1:0] must increment by 1 !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1Tx - Unexpected cl_len change [Warning only] + SNIFF_C1TX_UNEXP_CLLEN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr cl_len field changed between multi-line beat !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C1Tx - unexpected request type change + SNIFF_C1TX_UNEXP_REQTYPE: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr multi-line beat found unexpected Request type change !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1Tx - SOP field not set + SNIFF_C1TX_SOP_NOT_SET: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr First transaction of multi-line beat must set SOP field to HIGH !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1Tx - SOP field set for subsequent transactions + SNIFF_C1TX_SOP_SET_MCL1TO3: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr Subsequent transaction of multi-line beat must set SOP field to LOW !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C0TX - 3CL Request check + SNIFF_C1TX_3CL_REQUEST: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr 3-CL request issued. This is illegal !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1Tx - Write fence observered between CL1-CL3 in MCL request + SNIFF_C1TX_WRFENCE_IN_MCL1TO3: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr cannot issue a WriteFence in between a multi-line transaction !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - Write Fence observed with SOP set. + SNIFF_C1TX_WRFENCE_SOP_SET: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr cannot issue a WriteFence with SOP bit Set High !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C1TX - Address found to be zero + SNIFF_C1TX_ADDR_ZERO_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] C1TxHdr address was ZERO.. this will cause simulation failure", errcode_str); + print_message_and_log(1, log_str); + end + + // C2Tx - MMIO Read Response timeout + MMIO_RDRSP_TIMEOUT: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] MMIO Read Response timed out. AFU must respond to MMIO Read responses within %d clocks !\n", errcode_str, `MMIO_RESPONSE_TIMEOUT); + print_message_and_log(0, log_str); + end + + // C2TX - MMIO Read Response was unsolicited + MMIO_RDRSP_UNSOLICITED: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] ASE detected an unsolicited MMIO Response. In system, this can cause unexpected behavior !\n", errcode_str); + print_message_and_log(0, log_str); + end + + // C2TX - X or Z found + MMIO_RDRSP_XZ_FOUND_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] MMIO Response contained a 'Z' or 'X' !\n", errcode_str); + print_message_and_log(1, log_str); + end + + // C2TX - Reset ignored + MMIO_RDRSP_RESET_IGNORED_WARN: + begin + error_code_q[code] = 1'b1; + $sformat(log_str, "[%s] MMIO Response was issued when SoftReset signal was HIGH !\n", errcode_str); + print_message_and_log(1, log_str); + end + + SNIFF_NO_ERROR: + begin + error_code_q[code] = 1'b0; + end + // Unknown type -- this must not happen + default: + begin + print_message_and_log(1, "** ASE Internal Error **: Undefined Error code found !"); + end + + endcase + end + end + endtask + + + /* + * Reset ignorance check + */ + always @(posedge clk) begin + if (SoftReset && ccip_tx.c0.valid) begin + decode_error_code(0, SNIFF_C0TX_RESET_IGNORED_WARN); + end + else + error_code_q[SNIFF_C0TX_RESET_IGNORED_WARN]=1'b0; + + if (SoftReset && ccip_tx.c1.valid) begin + decode_error_code(0, SNIFF_C1TX_RESET_IGNORED_WARN); + end + else + error_code_q[SNIFF_C1TX_RESET_IGNORED_WARN]=1'b0; + + if (SoftReset && ccip_tx.c2.mmioRdValid) begin + decode_error_code(0, MMIO_RDRSP_RESET_IGNORED_WARN); + end + else + error_code_q[MMIO_RDRSP_RESET_IGNORED_WARN]=1'b0; + end + + + /* + * Cast MMIO Header + */ + t_ccip_c0_ReqMmioHdr C0RxCfg; + assign C0RxCfg = t_ccip_c0_ReqMmioHdr'(ccip_rx.c0.hdr); + + + /* + * UNDEF & HIIMP checker + */ + // Z and X flags + reg xz_tx0_flag; + reg xz_tx1_flag; + reg xz_tx2_flag; + + // XZ flags check + assign xz_tx0_flag = ^{ccip_tx.c0.hdr.vc_sel, ccip_tx.c0.hdr.cl_len, ccip_tx.c0.hdr.req_type, ccip_tx.c0.hdr.address, ccip_tx.c0.hdr.mdata}; + + assign xz_tx1_flag = ^{ccip_tx.c1.hdr.vc_sel, ccip_tx.c1.hdr.sop, ccip_tx.c1.hdr.cl_len, ccip_tx.c1.hdr.req_type, ccip_tx.c1.hdr.address, ccip_tx.c1.hdr.mdata, ccip_tx.c1.data}; + + assign xz_tx2_flag = ^{ccip_tx.c2.hdr.tid, ccip_tx.c2.data}; + + // Trigger XZ warnings + always @(posedge clk) begin + // ------------------------------------------------- // + if (ccip_tx.c0.valid && isEqualsXorZ(xz_tx0_flag)) begin + decode_error_code(0, SNIFF_C0TX_XZ_FOUND_WARN); + end + else + error_code_q[SNIFF_C0TX_XZ_FOUND_WARN]=1'b0; + + // ------------------------------------------------- // + if (ccip_tx.c1.valid && isEqualsXorZ(xz_tx1_flag) && isCCIPWriteRequest(ccip_tx.c1.hdr)) begin + decode_error_code(0, SNIFF_C1TX_XZ_FOUND_WARN); + end + else + error_code_q[SNIFF_C1TX_XZ_FOUND_WARN]=1'b0; + + // ------------------------------------------------- // + if (ccip_tx.c2.mmioRdValid && isEqualsXorZ(xz_tx2_flag)) begin + decode_error_code(0, MMIO_RDRSP_XZ_FOUND_WARN); + end + else + error_code_q[ MMIO_RDRSP_XZ_FOUND_WARN]=1'b0; + // ------------------------------------------------- // + end + + + /* + * Full {0,1} signaling + */ + always @(posedge clk) begin + // ------------------------------------------------- // + // Channel 0 overflow check + if (cf2as_ch0_realfull && ccip_tx.c0.valid) begin + decode_error_code(0, SNIFF_C0TX_OVERFLOW); + end + else + error_code_q[ SNIFF_C0TX_OVERFLOW]=1'b0; + + // ------------------------------------------------- // + // Channel 1 overflow check + if (cf2as_ch1_realfull && ccip_tx.c1.valid) begin + decode_error_code(0, SNIFF_C1TX_OVERFLOW); + end + else + error_code_q[ SNIFF_C1TX_OVERFLOW]=1'b0; + // ------------------------------------------------- // + end + + + /* + * Illegal transaction checker + */ + always @(posedge clk) begin : illegal_reqproc + // ------------------------------------------------- // + // C0TxHdr reqtype + if (ccip_tx.c0.valid) begin + if (ccip_tx.c0.hdr.req_type inside {eREQ_RDLINE_S, eREQ_RDLINE_I}) begin + error_code_q[ SNIFF_C0TX_INVALID_REQTYPE]=1'b0; + end + else begin + decode_error_code(0, SNIFF_C0TX_INVALID_REQTYPE); + end + end + else + error_code_q[ SNIFF_C0TX_INVALID_REQTYPE]=1'b0; + + // ------------------------------------------------- // + // C1TxHdr reqtype + if (ccip_tx.c1.valid) begin + if (ccip_tx.c1.hdr.req_type inside {eREQ_WRLINE_M +`ifdef ASE_ENABLE_INTR_FEATURE + , eREQ_INTR +`endif + , eREQ_WRLINE_I + , eREQ_WRFENCE + , eREQ_WRPUSH_I}) begin + error_code_q[SNIFF_C1TX_INVALID_REQTYPE]=1'b0; + end + else begin + decode_error_code(0, SNIFF_C1TX_INVALID_REQTYPE); + end + end + else + error_code_q[SNIFF_C1TX_INVALID_REQTYPE]=1'b0; + + // ------------------------------------------------- // + end + + + /* + * C0Tx Multi-line Request checker + */ + // 3CL and Address alignment checker + always @(posedge clk) begin : c0tx_mcl_checker + if (ccip_tx.c0.valid && isCCIPReadRequest(ccip_tx.c0.hdr)) begin + + // -------------------------------------------------------- // + // Invalid length - 3 CL checks + if (ccip_tx.c0.hdr.cl_len == 2'b10) begin + decode_error_code(0, SNIFF_C0TX_3CL_REQUEST); + end + else + error_code_q[ SNIFF_C0TX_3CL_REQUEST]=1'b0; + + // -------------------------------------------------------- // + // Address alignment checks + if ((ccip_tx.c0.hdr.cl_len == 2'b01) && (ccip_tx.c0.hdr.address[0] != 1'b0)) begin + decode_error_code(0, SNIFF_C0TX_ADDRALIGN_2_ERROR); + decode_error_code(0, SNIFF_C0TX_UNEXP_ADDR); + error_code_q[SNIFF_C0TX_ADDRALIGN_4_ERROR]=1'b0; + end + else if ((ccip_tx.c0.hdr.cl_len == 2'b11) && (ccip_tx.c0.hdr.address[1:0] != 2'b00)) begin + decode_error_code(0, SNIFF_C0TX_ADDRALIGN_4_ERROR); + error_code_q[SNIFF_C0TX_ADDRALIGN_2_ERROR]=1'b0; + decode_error_code(0, SNIFF_C0TX_UNEXP_ADDR); + end + else + begin + error_code_q[SNIFF_C0TX_UNEXP_ADDR]=1'b0; + error_code_q[SNIFF_C0TX_ADDRALIGN_2_ERROR]=1'b0; + error_code_q[SNIFF_C0TX_ADDRALIGN_4_ERROR]=1'b0; + end + + // -------------------------------------------------------- // + // Address zero warning + if (ccip_tx.c0.hdr.address == t_ccip_clAddr'(0)) begin + decode_error_code(0, SNIFF_C0TX_ADDR_ZERO_WARN); + end + else + error_code_q[SNIFF_C0TX_ADDR_ZERO_WARN]=1'b0; + end + else + begin + error_code_q[SNIFF_C0TX_UNEXP_ADDR]=1'b0; + error_code_q[SNIFF_C0TX_ADDRALIGN_2_ERROR]=1'b0; + error_code_q[SNIFF_C0TX_ADDRALIGN_4_ERROR]=1'b0; + error_code_q[SNIFF_C0TX_ADDR_ZERO_WARN]=1'b0; + error_code_q[SNIFF_C0TX_3CL_REQUEST]=1'b0; + end + end + + + /* + * C1Tx Multi-line Request checker + */ + typedef enum { + Exp_1CL_WrFence, + Exp_2CL, + Exp_3CL, + Exp_4CL + } ExpTxState; + ExpTxState exp_c1state,exp_c1state_q; + + logic [15:0] base_c1mdata; + logic [1:0] base_c1addr_low2; + t_ccip_vc base_c1vc; + logic [1:0] base_c1len; + t_ccip_c1_req base_c1reqtype; + logic [1:0] mcl_address; + logic c1tx_1to3_flag; + logic sop_mcl_flag; + logic wrfence_flag; + logic mcl_flag; + logic mcl_1to3_wrfence; + + // Base signal sampling + always @(posedge clk) begin + if (SoftReset) begin + base_c1addr_low2 <= 0; + base_c1vc <= t_ccip_vc'(0); + base_c1len <= 0; + base_c1mdata <= 0; + base_c1reqtype <= t_ccip_c1_req'(0); + end + else + begin + if (ccip_tx.c1.hdr.sop && ccip_tx.c1.valid ) begin + base_c1addr_low2 <= ccip_tx.c1.hdr.address[1:0]; + base_c1vc <= ccip_tx.c1.hdr.vc_sel; + base_c1len <= ccip_tx.c1.hdr.cl_len; + base_c1mdata <= ccip_tx.c1.hdr.mdata; + base_c1reqtype <= ccip_tx.c1.hdr.req_type; + end + end + end + + // Transaction Checker FSM + always @(posedge clk) begin + if (SoftReset) begin + exp_c1state = Exp_1CL_WrFence; + end + else + begin + if(ccip_tx.c1.valid) + begin + exp_c1state = exp_c1state_q; + end + end + end + + always@(* ) begin + case (exp_c1state) + + // ==================================================== // + // 1st line in MCL request OR Write Fence Request + Exp_1CL_WrFence: + begin + mcl_flag=0; + c1tx_1to3_flag = 0; + mcl_address=2'b00; + error_code_q[SNIFF_C1TX_UNEXP_ADDR]=1'b0; + + // ----------------------------------------- // + // SOP check + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ~ccip_tx.c1.hdr.sop) + sop_mcl_flag=1; + else + sop_mcl_flag=0; + + // ----------------------------------------- // + // 3CL transaction check + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.cl_len == 2'b10) && ccip_tx.c1.hdr.sop) + decode_error_code(0, SNIFF_C1TX_3CL_REQUEST); + else + error_code_q[SNIFF_C1TX_3CL_REQUEST]=1'b0; + + // ----------------------------------------- // + // Address alignment checks + if (ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.cl_len == 2'b01) && (ccip_tx.c1.hdr.address[0] != 1'b0)) + begin + decode_error_code(0, SNIFF_C1TX_ADDRALIGN_2_ERROR); + error_code_q[SNIFF_C1TX_ADDRALIGN_4_ERROR]=1'b0; + end + else if (ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.cl_len == 2'b11) && (ccip_tx.c1.hdr.address[1:0] != 2'b00)) + begin + decode_error_code(0, SNIFF_C1TX_ADDRALIGN_4_ERROR); + error_code_q[SNIFF_C1TX_ADDRALIGN_2_ERROR]=1'b0; + end + else + begin + error_code_q[SNIFF_C1TX_ADDRALIGN_2_ERROR]=1'b0; + error_code_q[SNIFF_C1TX_ADDRALIGN_4_ERROR]=1'b0; + end + + // -------------------------------------------------------- // + // Address zero warning + if (ccip_tx.c1.valid && (ccip_tx.c1.hdr.address == t_ccip_clAddr'(0)) && isCCIPWriteRequest(ccip_tx.c1.hdr)) + decode_error_code(0, SNIFF_C1TX_ADDR_ZERO_WARN); + else + error_code_q[SNIFF_C1TX_ADDR_ZERO_WARN]=1'b0; + + // ----------------------------------------- // + // State Transition + if (ccip_tx.c1.valid && isWrFenceRequest(ccip_tx.c1.hdr)) begin + mcl_1to3_wrfence=0; + exp_c1state_q = Exp_1CL_WrFence; + end + else if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && (ccip_tx.c1.hdr.cl_len == 2'b00)) begin + mcl_1to3_wrfence=0; + exp_c1state_q = Exp_1CL_WrFence; + end + else if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && (ccip_tx.c1.hdr.cl_len == 2'b01)) begin + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_2CL; + end + else if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && (ccip_tx.c1.hdr.cl_len == 2'b11)) begin + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_2CL; + end + else begin + mcl_1to3_wrfence=0; + c1tx_1to3_flag = 0; + exp_c1state_q = Exp_1CL_WrFence; + end + end + + // ==================================================== // + // 2nd line in MCL request + Exp_2CL: + begin + sop_mcl_flag=0; + mcl_address=base_c1addr_low2 + 1; + /*if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.address[1:0] != (base_c1addr_low2 + 1))) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_ADDR); + end + else + error_code_q[SNIFF_C1TX_UNEXP_ADDR]=1'b0;*/ + // ----------------------------------------- // + + // ----------------------------------------- // + // State transition + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (base_c1len == 2'b11)) begin + mcl_flag=1; + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_3CL; + end + else if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (base_c1len == 2'b01)||(base_c1len == 2'b00)) begin + mcl_flag=1; + mcl_1to3_wrfence=0; + exp_c1state_q = Exp_1CL_WrFence; + end + else + begin + mcl_flag=0; + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_2CL; + end + + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && ((base_c1len == 2'b11)||(base_c1len == 2'b01))) + c1tx_1to3_flag = 1; + else + c1tx_1to3_flag = 0; + end + + // ==================================================== // + // 3rd line in MCL request + Exp_3CL: + begin + sop_mcl_flag=0; + mcl_address=base_c1addr_low2 + 2; + /* if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.address[1:0] != (base_c1addr_low2 + 2))) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_ADDR); + end + else + error_code_q[SNIFF_C1TX_UNEXP_ADDR]=1'b0;*/ + // ----------------------------------------- // + + // ----------------------------------------- // + // State transition + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (base_c1len == 2'b11)) begin + mcl_flag=1; + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_4CL; + end + else + begin + mcl_flag=0; + mcl_1to3_wrfence=1; + exp_c1state_q = Exp_3CL; + end + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && (base_c1len == 2'b11)) + c1tx_1to3_flag = 1; + else + c1tx_1to3_flag = 0; + end + + // ==================================================== // + // 4th line in MCL request + Exp_4CL: + begin + sop_mcl_flag=0; + mcl_address=base_c1addr_low2 + 3; + /* if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.address[1:0] != (base_c1addr_low2 + 3))) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_ADDR); + end + else + error_code_q[SNIFF_C1TX_UNEXP_ADDR]=1'b0;*/ + // ----------------------------------------- // + + // ----------------------------------------- // + // State transition + if (ccip_tx.c1.valid && isCCIPWrFenceRequest(ccip_tx.c1.hdr)) begin + exp_c1state_q =Exp_4CL; + mcl_1to3_wrfence=1; + mcl_flag =0; + end + else + begin + mcl_1to3_wrfence=0; + exp_c1state_q =Exp_1CL_WrFence; + mcl_flag=1; + end + + if (ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && ccip_tx.c1.hdr.sop && (base_c1len == 2'b11)) + c1tx_1to3_flag = 1; + else + c1tx_1to3_flag = 0; + end + + // ==================================================== // + // Lala-land + default: + begin + mcl_address=2'b00; + mcl_flag=0; + c1tx_1to3_flag = 0; + sop_mcl_flag =0; + exp_c1state_q = Exp_1CL_WrFence; + end + endcase + end + + /* + * Subsequent line checks + */ + always @(posedge clk) begin + // ----------------------------------------- // + //Check for unexpected Errors in C1Tx + if (mcl_flag && ccip_tx.c1.valid && isCCIPWriteRequest(ccip_tx.c1.hdr) && (ccip_tx.c1.hdr.address[1:0] != (mcl_address))) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_ADDR); + end + else + error_code_q[SNIFF_C1TX_UNEXP_ADDR]=1'b0; + + //Check if SOP is set or not for the 1st MCL + if(sop_mcl_flag) + decode_error_code(0, SNIFF_C1TX_SOP_NOT_SET); + else + error_code_q[SNIFF_C1TX_SOP_NOT_SET]=1'b0; + + // Write Fence must not be seen here + if (isCCIPWrFenceRequest(ccip_tx.c1.hdr)&& ccip_tx.c1.valid && mcl_1to3_wrfence) begin + decode_error_code(0, SNIFF_C1TX_WRFENCE_IN_MCL1TO3); + end + else + error_code_q[SNIFF_C1TX_WRFENCE_IN_MCL1TO3]=1'b0; + + // ----------------------------------------- // + // C1TX 1to3 SOP check + if (~(isCCIPWrFenceRequest(ccip_tx.c1.hdr)) && c1tx_1to3_flag && ccip_tx.c1.valid && ccip_tx.c1.hdr.sop) begin + decode_error_code(0, SNIFF_C1TX_SOP_SET_MCL1TO3); + end + else + error_code_q[SNIFF_C1TX_SOP_SET_MCL1TO3]=1'b0; + + // ----------------------------------------- // + // CL_LEN modification check [Warning only] + if (mcl_flag &&~(isCCIPWrFenceRequest(ccip_tx.c1.hdr)) && ~ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && (ccip_tx.c1.hdr.cl_len != base_c1len)) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_CLLEN); + end + else + error_code_q[SNIFF_C1TX_UNEXP_CLLEN]=1'b0; + + // ----------------------------------------- // + // VC modification check + if (mcl_flag &&~(isCCIPWrFenceRequest(ccip_tx.c1.hdr))&& ~ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && (ccip_tx.c1.hdr.vc_sel != base_c1vc)) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_VCSEL); + end + else + error_code_q[SNIFF_C1TX_UNEXP_VCSEL]=1'b0; + + // ----------------------------------------- // + // MDATA modification check + if (mcl_flag &&~(isCCIPWrFenceRequest(ccip_tx.c1.hdr))&& ~ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && (ccip_tx.c1.hdr.mdata != base_c1mdata)) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_MDATA); + end + else + error_code_q[SNIFF_C1TX_UNEXP_MDATA]=1'b0; + + // ----------------------------------------- // + // Write Fence and SOP bit set modification check + if (isCCIPWrFenceRequest(ccip_tx.c1.hdr)&& ccip_tx.c1.valid && ccip_tx.c1.hdr.sop) begin + decode_error_code(0, SNIFF_C1TX_WRFENCE_SOP_SET); + end + else + error_code_q[SNIFF_C1TX_WRFENCE_SOP_SET]=1'b0; + + // ----------------------------------------- // + // Request Type modification check + if (mcl_flag && ~ccip_tx.c1.hdr.sop && ccip_tx.c1.valid && (ccip_tx.c1.hdr.req_type != base_c1reqtype)) begin + decode_error_code(0, SNIFF_C1TX_UNEXP_REQTYPE); + end + else + error_code_q[SNIFF_C1TX_UNEXP_REQTYPE]=1'b0; + end + + + /* + * Check memory transactions in flight, maintain active list + */ + longint rd_active_addr_array[*]; + longint wr_active_addr_array[*]; + + string waw_haz_str; + string raw_haz_str; + string war_haz_str; + logic hazard_found; + + // ------------------------------------------- // + // Hazard check process + // - Take in address, check if exists in + // ------------------------------------------- // + always @(posedge clk) begin + // ------------------------------------------- // + // Read in (unroll necessary) + // ------------------------------------------- // + if (haz_if.read_in.valid) begin + for (int ii = 0; ii <= haz_if.read_in.hdr.len ; ii = ii + 1) begin : read_channel_haz_monitor + rd_active_addr_array[ haz_if.read_in.hdr.addr + ii ] = haz_if.read_in.hdr.addr + ii; + + // Check for outstanding write request + if (wr_active_addr_array.exists(haz_if.read_in.hdr.addr + ii)) begin + $sformat(war_haz_str, + "%d | Potential for Write-after-Read hazard with potential for C0TxHdr=%s arriving earlier than write to same address\n", + $time, + return_txhdr(haz_if.read_in.hdr)); + print_message_and_log(1, war_haz_str); + end + end + end + + // ------------------------------------------- // + // Write in + // ------------------------------------------- // + if (haz_if.write_in.valid) begin + // Check for outstanding read + if (rd_active_addr_array.exists(haz_if.write_in.hdr.addr)) begin : write_channel_haz_monitor + $sformat(raw_haz_str, + "%d | Potential for Read-after-Write hazard with potential for C1TxHdr=%s arriving earlier than write to same address\n", + $time, + return_txhdr(haz_if.write_in.hdr)); + print_message_and_log(1, raw_haz_str); + end + // Check for outstanding write + else if (wr_active_addr_array.exists(haz_if.write_in.hdr.addr)) begin + $sformat(waw_haz_str, + "%d | Potential for Write-after-Write hazard with potential for C1TxHdr=%s arriving earlier than write to same address\n", + $time, + return_txhdr(haz_if.write_in.hdr)); + print_message_and_log(1, waw_haz_str); + end + // If not, store + else begin + wr_active_addr_array[haz_if.write_in.hdr.addr] = haz_if.write_in.hdr.addr; + end + end + + // ------------------------------------------- // + // Read out (delete from active list) + // ------------------------------------------- // + if (haz_if.read_out.valid) begin + if (rd_active_addr_array.exists( haz_if.read_out.hdr.addr )) begin + rd_active_addr_array.delete( haz_if.read_out.hdr.addr ); + end + end + + // ------------------------------------------- // + // Write out (delete from active list) + // ------------------------------------------- // + if (haz_if.write_out.valid) begin + if (wr_active_addr_array.exists( haz_if.write_out.hdr.addr )) begin + wr_active_addr_array.delete( haz_if.write_out.hdr.addr ); + end + end + end + + //Making sure error_code doesnt go into an undetermined state when only one channel is Active + always@(*) + begin + error_code_q[31:30]=2'b0; + if((ccip_rx.c0.mmioRdValid || ccip_tx.c2.mmioRdValid)&& ~ccip_tx.c1.valid && ~ccip_tx.c0.valid) begin + error_code_q[31:5]=28'b0; + error_code_q[0]=1'b0; + end + else if(ccip_tx.c1.valid && ~ccip_tx.c0.valid && ~(ccip_rx.c0.mmioRdValid || ccip_tx.c2.mmioRdValid) ) begin + error_code_q[13:0]=13'b0; + end + else if(ccip_tx.c0.valid && ~(ccip_rx.c0.mmioRdValid || ccip_tx.c2.mmioRdValid) && ~ccip_tx.c1.valid ) begin + error_code_q[4:0]=4'b0; + error_code_q[31:14]=17'b0; + end + end + + /* + * Multiple outstandind MMIO Response tracking + * - Maintains `MMIO_MAX_OUTSTANDING records tracking activity + * - Tracking key = MMIO TID + */ + parameter int MMIO_TRACKER_DEPTH = 2**CCIP_CFGHDR_TID_WIDTH; + + // Tracker structure + typedef struct { + // Status management + logic [`MMIO_RESPONSE_TIMEOUT_RADIX-1:0] timer_val; + logic timeout; + logic active; + } mmioread_track_t; + mmioread_track_t mmioread_tracker[0:MMIO_TRACKER_DEPTH-1]; + + // Push/pop control process + task update_mmio_activity( + logic clear, + logic mmio_request, + logic mmio_response, + logic [CCIP_CFGHDR_TID_WIDTH-1:0] tid + ); + begin + if (clear) begin + mmioread_tracker[tid].active = 0; + error_code_q[MMIO_RDRSP_UNSOLICITED]=1'b0; + end + else begin + // If pop occured when not active + if (~mmioread_tracker[tid].active && mmio_response) begin + decode_error_code(0, MMIO_RDRSP_UNSOLICITED); + end + else + error_code_q[MMIO_RDRSP_UNSOLICITED]=1'b0; + // Active management + if (mmio_request) begin + mmioread_tracker[tid].active = 1; + end + else if (mmio_response) begin + mmioread_tracker[tid].active = 0; + end + end + end + endtask + + // Push/pop glue + always @(posedge clk) begin + if (SoftReset) begin + + for (int track_i = 0; track_i < MMIO_TRACKER_DEPTH ; track_i = track_i + 1) begin + update_mmio_activity(1, 0, 0, track_i); + end + end + else begin + // Push transaction to checker (mmioRead Request) + if (ccip_rx.c0.mmioRdValid) begin + update_mmio_activity(0, ccip_rx.c0.mmioRdValid, 0, C0RxCfg.tid); + end + // Pop transaction from checker (mmioRead Response) + if (ccip_tx.c2.mmioRdValid) begin + update_mmio_activity(0, 0, ccip_tx.c2.mmioRdValid, ccip_tx.c2.hdr.tid); + end + end + end + + // Tracker block + generate + for (genvar ii = 0; ii < MMIO_TRACKER_DEPTH ; ii = ii + 1) begin : mmio_tracker_block + // Counter value + always @(posedge clk) begin + if (ase_reset) begin + mmioread_tracker[ii].timer_val <= 0; + end + else begin + if (~mmioread_tracker[ii].active) begin + mmioread_tracker[ii].timer_val <= 0; + end + else if (mmioread_tracker[ii].active) begin + if(mmioread_tracker[ii].timer_val >= (`MMIO_RESPONSE_TIMEOUT )) + begin + end + else + mmioread_tracker[ii].timer_val <= mmioread_tracker[ii].timer_val + 1; + end + end + end // always @ (posedge clk) + + // Timeout flag + always @(posedge clk) begin + if (ase_reset|~mmioread_tracker[ii].active) begin + mmioread_tracker[ii].timeout <= 0; + error_code_q[MMIO_RDRSP_TIMEOUT]=1'b0; + end + else if (mmioread_tracker[ii].timer_val >= (`MMIO_RESPONSE_TIMEOUT )) + begin + mmioread_tracker[ii].timeout <= 1; + decode_error_code(0, MMIO_RDRSP_TIMEOUT); + end + else + error_code_q[MMIO_RDRSP_TIMEOUT]=1'b0; + end + end + endgenerate + +endmodule // cci_sniffer diff --git a/ase/rtl/ccip_emulator.sv b/ase/rtl/ccip_emulator.sv new file mode 100644 index 000000000000..b30b7bbfbc32 --- /dev/null +++ b/ase/rtl/ccip_emulator.sv @@ -0,0 +1,2748 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: CCI Emulation top-level - SystemVerilog Module + * Language : System{Verilog} + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * MAJOR UPGRADES: + * Wed Aug 10 22:17:28 PDT 2011 | Completed FIFO'ing all channels in all directions + * Tue Jun 17 16:46:06 PDT 2014 | Started cleaning up code to add latency model + * | Connect up new transactions CCI 1.8 + * Tue Dec 23 11:01:28 PST 2014 | Optimizing ASE for performance + * | Added return path FIFOs for marshalling + * Tue Oct 21 13:33:34 PDT 2015 | CCIP migration + * + */ + +import ase_pkg::*; +import ccip_if_pkg::*; + +`include "platform.vh" + +// CCI to Memory translator module +module ccip_emulator + ( + // CCI-P Clocks and Resets + output logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + output logic pClkDiv2, // 200MHz - CCI-P clock domain. + output logic pClkDiv4, // 100MHz - CCI-P clock domain. + // User clocks + output logic uClk_usr, // User clock domain. Refer to clock programming guide + output logic uClk_usrDiv2, // User clock domain. Half the programmed frequency + // Power & error states + output logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + output logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + output logic pck_cp2af_error, // CCI-P Protocol Error Detected + // Interface structures + output t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + input t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port + ); + + + // Power and error state + assign pck_cp2af_pwrState = 2'b0; + assign pck_cp2af_error = 1'b0; + + + /* + * CCIP breakout + */ + // Clock/reset + logic Clk16UI ; + logic Clk32UI ; + logic Clk64UI ; + logic SoftReset; + // Tx0 & bookkeeper + ASETxHdr_t ASE_C0TxHdr; + TxHdr_t C0TxHdr; + logic C0TxValid; + // Tx1 & bookkeeper + ASETxHdr_t ASE_C1TxHdr; + TxHdr_t C1TxHdr; + logic [CCIP_DATA_WIDTH-1:0] C1TxData; + logic C1TxValid; + // Tx2 + MMIOHdr_t C2TxHdr; + logic C2TxMmioRdValid; + logic [CCIP_MMIO_RDDATA_WIDTH-1:0] C2TxData; + // Rx0 & bookkeeper + logic C0RxMmioWrValid; + logic C0RxMmioRdValid; + logic [CCIP_DATA_WIDTH-1:0] C0RxData; + RxHdr_t C0RxHdr; + logic C0RxRspValid; + // Rx1 & bookkeeper + RxHdr_t C1RxHdr; + logic C1RxRspValid; + // Almost full signals + logic C0TxAlmFull; + logic C1TxAlmFull; + + + // Internal 800 Mhz clock (for creating synchronized clocks) + logic Clk8UI; + logic clk ; + + // Real Full ch2as + logic cf2as_ch0_realfull; + logic cf2as_ch1_realfull; + + /* + * Reset lockdown flag + * - Stop taking any more requests if ase_reset was requested + */ + logic reset_lockdown = 0; + + // Disable settings + logic ase_logger_disable; + logic ase_checker_disable; + + + /* + * Local valid/debug breakout signals + */ + logic C0RxRdValid; + logic C0RxUMsgValid; + logic C1RxWrValid; + logic C1RxIntrValid; + + /* + * Request/Response Type conversion functions + */ + // ccip_tx0_to_ase_tx0: Convert from CCIP -> ASE Tx0 + function ASETxHdr_t ccip_tx0_to_ase_tx0(t_ccip_c0_ReqMemHdr inhdr); + ASETxHdr_t txasehdr; + begin + txasehdr.txhdr = TxHdr_t'(inhdr); + txasehdr.channel_id = 0; + case (inhdr.req_type) + eREQ_RDLINE_I : txasehdr.txhdr.reqtype = ASE_RDLINE_I; + eREQ_RDLINE_S : txasehdr.txhdr.reqtype = ASE_RDLINE_S; + endcase // case (inhdr.req_type) + return txasehdr; + end + endfunction + + // ccip_tx1_to_ase_tx1: Convert from CCIP -> ASE Tx1 + function ASETxHdr_t ccip_tx1_to_ase_tx1(t_ccip_c1_ReqMemHdr inhdr); + ASETxHdr_t txasehdr; + logic [41:0] c1tx_mcl_baseaddr; + ccip_reqtype_t c1tx_mcl_basetype; + ccip_len_t c1tx_mcl_baselen; + logic [15:0] c1tx_mcl_basemdata; + ccip_vc_t c1tx_mcl_basevc; + begin + txasehdr.txhdr = TxHdr_t'(inhdr); + txasehdr.channel_id = 1; + // Request type remap to ASE internal types + case (inhdr.req_type) + eREQ_WRLINE_I : txasehdr.txhdr.reqtype = ASE_WRLINE_I; + eREQ_WRLINE_M : txasehdr.txhdr.reqtype = ASE_WRLINE_M; + eREQ_WRFENCE : txasehdr.txhdr.reqtype = ASE_WRFENCE; + eREQ_WRPUSH_I : txasehdr.txhdr.reqtype = ASE_WRPUSH; +`ifdef ASE_ENABLE_INTR_FEATURE + eREQ_INTR : txasehdr.txhdr.reqtype = ASE_INTR_REQ; +`endif + endcase // case (inhdr.req_type) + // Accomodating MCL addr[41:2]=X when SOP=0 + if ( (txasehdr.txhdr.reqtype == ASE_WRLINE_I) || (txasehdr.txhdr.reqtype == ASE_WRLINE_M) || (txasehdr.txhdr.reqtype == ASE_WRPUSH) ) begin + if (inhdr.sop) begin + c1tx_mcl_baseaddr = txasehdr.txhdr.addr; + c1tx_mcl_basetype = txasehdr.txhdr.reqtype; + c1tx_mcl_baselen = txasehdr.txhdr.len; + c1tx_mcl_basemdata = txasehdr.txhdr.mdata; + c1tx_mcl_basevc = txasehdr.txhdr.vc; + end + else begin + txasehdr.txhdr.reqtype = c1tx_mcl_basetype; + case (c1tx_mcl_baselen) + ASE_2CL: txasehdr.txhdr.addr = {c1tx_mcl_baseaddr[41:1], inhdr.address[0]}; + ASE_4CL: txasehdr.txhdr.addr = {c1tx_mcl_baseaddr[41:2], inhdr.address[1:0]}; + endcase // case (c1tx_mcl_baselen) + txasehdr.txhdr.mdata = c1tx_mcl_basemdata; + txasehdr.txhdr.vc = c1tx_mcl_basevc; + end + end + return txasehdr; + end + endfunction + + // ase_rx0_to_ccip_rx0: Convert from ASE -> CCIP RX0 + function t_ccip_c0_RspMemHdr ase_rx0_to_ccip_rx0(ASERxHdr_t inhdr); + t_ccip_c0_RspMemHdr rxasehdr; + begin + rxasehdr = RxHdr_t'(inhdr.rxhdr); + case (inhdr.rxhdr.resptype) + ASE_RD_RSP : rxasehdr.resp_type = eRSP_RDLINE; +`ifdef ASE_ENABLE_UMSG_FEATURE + ASE_UMSG : rxasehdr.resp_type = eRSP_UMSG; +`endif + endcase + case (inhdr.rxhdr.vc_used) + VC_VA : rxasehdr.vc_used = eVC_VA; + VC_VL0 : rxasehdr.vc_used = eVC_VL0; + VC_VH0 : rxasehdr.vc_used = eVC_VH0; + VC_VH1 : rxasehdr.vc_used = eVC_VH1; + endcase + return rxasehdr; + end + endfunction + + // ase_rx1_to_ccip_rx1: Convert from ASE -> CCIP RX1 + function t_ccip_c1_RspMemHdr ase_rx1_to_ccip_rx1(ASERxHdr_t inhdr); + t_ccip_c1_RspMemHdr rxasehdr; + begin + rxasehdr = RxHdr_t'(inhdr.rxhdr); + case (inhdr.rxhdr.resptype) + ASE_WR_RSP : rxasehdr.resp_type = eRSP_WRLINE; + ASE_WRFENCE_RSP : rxasehdr.resp_type = eRSP_WRFENCE; +`ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_RSP : rxasehdr.resp_type = eRSP_INTR; +`endif + endcase // case (inhdr.rxhdr.resptype) + case (inhdr.rxhdr.vc_used) + VC_VA : rxasehdr.vc_used = eVC_VA; + VC_VL0 : rxasehdr.vc_used = eVC_VL0; + VC_VH0 : rxasehdr.vc_used = eVC_VH0; + VC_VH1 : rxasehdr.vc_used = eVC_VH1; + endcase + return rxasehdr; + end + endfunction + + + // ASE's internal reset signal + logic ase_reset = 1; + logic init_reset = 1; + + + /* + * Remapping ASE CCIP to cvl_pkg struct + */ + // Clocks 16ui, 32ui, 64ui + assign pClk = Clk16UI; + assign pClkDiv2 = Clk32UI; + assign pClkDiv4 = Clk64UI; + // Reset out + assign pck_cp2af_softReset = SoftReset; + + + // Rx/Tx mapping from ccip_if_pkg to ASE's internal format + always @(*) begin : ccip2ase_remap + // Rx OUT (CH0) + // If MMIO RDWR request, cast directly to interface format + if (C0RxMmioRdValid|C0RxMmioWrValid) begin + pck_cp2af_sRx.c0.hdr <= t_ccip_c0_RspMemHdr'(C0RxHdr); + end + // Else, cast via function, changing resptype(s) + else begin + pck_cp2af_sRx.c0.hdr <= ase_rx0_to_ccip_rx0(t_ccip_c0_RspMemHdr'(C0RxHdr)); + end + pck_cp2af_sRx.c0.data <= t_ccip_clData'(C0RxData); + pck_cp2af_sRx.c0.rspValid <= C0RxRspValid; + pck_cp2af_sRx.c0.mmioRdValid <= C0RxMmioRdValid; + pck_cp2af_sRx.c0.mmioWrValid <= C0RxMmioWrValid; + // Rx OUT (CH1) + pck_cp2af_sRx.c1.hdr <= ase_rx1_to_ccip_rx1(t_ccip_c1_RspMemHdr'(C1RxHdr)); + pck_cp2af_sRx.c1.rspValid <= C1RxRspValid; + // Tx OUT (CH0) + ASE_C0TxHdr <= ccip_tx0_to_ase_tx0( pck_af2cp_sTx.c0.hdr ); + C0TxHdr <= ASE_C0TxHdr.txhdr; + C0TxValid <= pck_af2cp_sTx.c0.valid; + // Tx OUT (CH1) + ASE_C1TxHdr <= ccip_tx1_to_ase_tx1(pck_af2cp_sTx.c1.hdr); + C1TxHdr <= ASE_C1TxHdr.txhdr; + C1TxData <= pck_af2cp_sTx.c1.data; + C1TxValid <= pck_af2cp_sTx.c1.valid; + // Tx OUT (CH2) + C2TxHdr <= MMIOHdr_t'(pck_af2cp_sTx.c2.hdr); + C2TxData <= pck_af2cp_sTx.c2.data; + C2TxMmioRdValid <= pck_af2cp_sTx.c2.mmioRdValid; + // Almost full signals + pck_cp2af_sRx.c0TxAlmFull <= C0TxAlmFull | reset_lockdown; + pck_cp2af_sRx.c1TxAlmFull <= C1TxAlmFull | reset_lockdown; + end + + + /* + * DPI import/export functions + */ + // Scope function + import "DPI-C" function void scope_function(); + + // ASE Initialize function + import "DPI-C" context task ase_init(); + + // Indication that ASE is ready + import "DPI-C" function void ase_ready(); + + // Global listener function + import "DPI-C" context task ase_listener(); + + // ASE config data exchange (read from ase.cfg) + export "DPI-C" task ase_config_dex; + + // Unordered message dispatch +`ifdef ASE_ENABLE_UMSG_FEATURE + export "DPI-C" task umsg_dispatch; +`endif + + // MMIO dispatch + export "DPI-C" task mmio_dispatch; + + // Start simulation structures teardown + import "DPI-C" context task start_simkill_countdown(); + + // Signal to kill simulation + export "DPI-C" task simkill; + + // Transaction count update ping/pong + export "DPI-C" task count_error_flag_ping; + import "DPI-C" function void count_error_flag_pong(int flag); + + // ASE instance check + import "DPI-C" function int ase_instance_running(); + + // Global dealloc allowed flag + import "DPI-C" function void update_glbl_dealloc(int flag); + + // CONFIG, SCRIPT DEX operations + import "DPI-C" function void sv2c_config_dex(string str); + import "DPI-C" function void sv2c_script_dex(string str); + + // Data exchange for READ, WRITE system + import "DPI-C" function void rd_memline_dex(inout cci_pkt foo ); + import "DPI-C" function void wr_memline_dex(inout cci_pkt foo ); + + // Get ASE seed + import "DPI-C" function int get_ase_seed(); + // int ase_seed; + + // MMIO response + import "DPI-C" function void mmio_response(inout mmio_t mmio_pkt); + mmio_t mmio_rdrsp_pkt; + mmio_t mmio_wrrsp_pkt; + + // Software controlled process - run clocks + export "DPI-C" task run_clocks; + + // Software controlled process - Run AFU Reset + export "DPI-C" task afu_softreset_trig; + + // Simulator global reset (issued at simulator start, or session end) + export "DPI-C" task ase_reset_trig; + + // Software controlled reset response + import "DPI-C" function void sw_reset_response(); + + // cci_logger buffer message + export "DPI-C" task buffer_msg_inject; + + // Page table called status + logic rd_memline_dex_called; + logic wr_memline_dex_called; + + // Scope generator + initial scope_function(); + + // Ready PID + int ase_ready_pid; + + // Finish logger command + logic finish_trigger = 0; + + + /* + * Credit control system + */ + int glbl_dealloc_credit; + int glbl_dealloc_credit_q; + + // Individual credit counts + int rd_credit; + int wr_credit; + int mmiowr_credit; + int mmiord_credit; + int umsg_credit; + + logic [ASE_RSPFIFO_COUNT_WIDTH:0] rdrsp_fifo_cnt; + logic [ASE_RSPFIFO_COUNT_WIDTH:0] wrrsp_fifo_cnt; + + /* + * CH0 and CH1 latbuf + */ + // cf2as_latbuf_ch0 signals + TxHdr_t cf2as_latbuf_tx0hdr; + RxHdr_t cf2as_latbuf_rx0hdr; + logic cf2as_latbuf_ch0_empty; + logic cf2as_latbuf_ch0_read; + int cf2as_latbuf_ch0_count; + logic cf2as_latbuf_ch0_valid; + + // cf2as_latbuf_ch1 signals + logic [CCIP_DATA_WIDTH-1:0] cf2as_latbuf_tx1data; + TxHdr_t cf2as_latbuf_tx1hdr; + RxHdr_t cf2as_latbuf_rx1hdr; + logic cf2as_latbuf_ch1_empty; + logic cf2as_latbuf_ch1_read; + int cf2as_latbuf_ch1_count; + logic cf2as_latbuf_ch1_valid; + + // Hazard checker signals + ase_haz_if haz_if; + + + /* + * ASE Simulator reset + * - Use sparingly, only for initialization and reset between session_init(s) + */ + task ase_reset_trig(); + begin + reset_lockdown = 1; + wait (glbl_dealloc_credit == 0); + @(posedge clk); + ase_reset = 1; + run_clocks(20); + ase_reset = 0; + run_clocks(20); + reset_lockdown = 0; + end + endtask // ase_reset_trig + + + /* + * Issue Simulation Finish trigger + */ + task issue_finish_trig(); + begin + finish_trigger = 1; + @(posedge clk); + finish_trigger = 0; + @(posedge clk); + end + endtask // issue_finish_trig + + + /* + * Multi-instance multi-user +CONFIG,+SCRIPT instrumentation + * RUN => + * cd + * ./ +CONFIG= +SCRIPT= + * + */ + string config_filepath; + string script_filepath; +`ifdef ASE_DEBUG + initial begin + if ($value$plusargs("CONFIG=%S", config_filepath)) begin + `BEGIN_YELLOW_FONTCOLOR; + $display(" [DEBUG] Config = %s", config_filepath); + `END_YELLOW_FONTCOLOR; + end + end + + initial begin + if ($value$plusargs("SCRIPT=%S", script_filepath)) begin + `BEGIN_YELLOW_FONTCOLOR; + $display(" [DEBUG] Script = %s", script_filepath); + `END_YELLOW_FONTCOLOR; + end + end +`else + initial $value$plusargs("CONFIG=%S", config_filepath); + initial $value$plusargs("SCRIPT=%S", script_filepath); +`endif + + + /* + * Overflow/underflow signal checks + */ + logic tx0_underflow; + logic tx1_underflow; + logic tx0_overflow; + logic tx1_overflow; + + /* + * Fabric Clock, pClk{*} + */ + logic [2:0] ase_clk_rollover = 3'b111; + + // ASE clock + assign clk = Clk16UI; + assign Clk16UI = ase_clk_rollover[0]; + assign Clk32UI = ase_clk_rollover[1]; + assign Clk64UI = ase_clk_rollover[2]; + + // 800 Mhz internal reference clock + initial begin : clk8ui_proc + begin + Clk8UI = 0; + forever begin + #(`CLK_8UI_TIME/2); + Clk8UI = 0; + #(`CLK_8UI_TIME/2); + Clk8UI = 1; + end + end + end + + // 200 Mhz clock + always @(posedge Clk8UI) begin : clk_rollover_ctr + ase_clk_rollover <= ase_clk_rollover - 1; + end + + // Reset management + logic sw_reset_trig = 1; + logic app_reset_trig; + logic app_reset_trig_q; + int rst_timeout_counter; + int rst_counter; + + // Register app_reset_trig + always @(posedge clk) begin + app_reset_trig_q <= app_reset_trig; + end + + // Reset states + typedef enum { + ResetIdle, + ResetHoldHigh, + ResetHoldLow, + ResetWait + } ResetStateEnum; + ResetStateEnum rst_state; + + + // AFU Soft Reset Trigger + task afu_softreset_trig(int init, int value ); + begin + if (init) begin + app_reset_trig = 0; + end + else begin + app_reset_trig = value[0]; + end + end + endtask + + // Reset FSM + always @(posedge clk) begin + if (ase_reset) begin + rst_state <= ResetIdle; + rst_counter <= 0; + rst_timeout_counter <= 0; + end + else begin + case (rst_state) + ResetIdle: + begin + rst_timeout_counter <= 0; + // 0 -> 1 + if (~app_reset_trig_q && app_reset_trig) begin + rst_state <= ResetHoldHigh; + end + // 1 -> 0 + else if (app_reset_trig_q && ~app_reset_trig) begin + rst_state <= ResetHoldLow; + end + else begin + rst_state <= ResetIdle; + end + end + + // Set to 1 + ResetHoldHigh: + begin + if (glbl_dealloc_credit != 0) begin + if (rst_timeout_counter < `RESET_TIMEOUT_DURATION) begin + rst_timeout_counter <= rst_timeout_counter + 1; + rst_state <= ResetHoldHigh; + end + else begin + `BEGIN_RED_FONTCOLOR; + $display(" [SIM] Reset request timed out... Behavior maybe undefined !"); + `END_RED_FONTCOLOR; + sw_reset_trig <= 1; + rst_state <= ResetWait; + end + end + else begin + sw_reset_trig <= 1; + rst_state <= ResetWait; + end + end + + // Set to 0 + ResetHoldLow: + begin + sw_reset_trig <= 0; + rst_state <= ResetWait; + end + + // Wait few cycles + ResetWait: + begin + if (rst_counter < `SOFT_RESET_DURATION) begin + rst_counter <= rst_counter + 1; + rst_state <= ResetWait; + end + else begin + rst_counter <= 0; + rst_state <= ResetIdle; + sw_reset_response(); + end + end + + default: + begin + rst_state <= ResetIdle; + end + + endcase + end + end + + + /* + * User clock, uclk{*} + */ + logic usrClk; + logic usrClkDiv2 = 0; + int usrClk_delay = 3200; + + // Function: Update usrclk_delay + function void update_usrclk_delay(int delay); + begin + usrClk_delay = delay; + end + endfunction + + // User clock process + initial begin : usrclk_proc + begin + usrClk = 0; + forever begin + #(usrClk_delay/2); + usrClk = ~usrClk; + end + end + end + + + // Div2 output + always @(posedge usrClk) begin : usrclkdiv2_proc + usrClkDiv2 = ~usrClkDiv2; + end + + // UCLK interface + assign uClk_usr = usrClk; + assign uClk_usrDiv2 = usrClkDiv2; + + + /* + * AFU reset - software & system resets + */ + // + // 0 | 0 0 | + // 1 | 0 1 | + // 1 | 1 0 | + // 1 | 1 1 | Initial reset + + assign SoftReset = ase_reset | sw_reset_trig; + + + /* ****************************************************************** + * + * run_clocks : Run 'n' clocks + * Software controlled event trigger for watching signals + * + * *****************************************************************/ + task run_clocks (int num_clks); + int clk_iter; + begin + for (clk_iter = 0; clk_iter <= num_clks; clk_iter = clk_iter + 1) begin + @(posedge clk); + end + end + endtask + + + /* *************************************************************************** + * Buffer message injection into ccip_logger + * --------------------------------------------------------------------------- + * Task sets buffer message to be posted into ccip_transactions.tsv log + * + * ***************************************************************************/ + string buffer_msg; + logic buffer_msg_en; + logic buffer_msg_tstamp_en; + + // Inject task + task buffer_msg_inject (int timestamp_en, string logstr); + begin + buffer_msg = logstr; + buffer_msg_en = 1; + buffer_msg_tstamp_en = timestamp_en[0]; + @(posedge clk); + buffer_msg_en = 0; + @(posedge clk); + end + endtask + + + /* ****************************************************************** + * + * MMIO block + * CSR Write/Read is managed through this interface. + * + * *****************************************************************/ + // TID:Address tuple storage + int unsigned tid_array[*]; + + /* + * CSR Read/Write infrastructure + * csr_write_dispatch: A Single task to dispatch CSR Writes + * Storage format = + * + */ + parameter int MMIOREQ_FIFO_WIDTH = 2 + CCIP_CFG_HDR_WIDTH + CCIP_DATA_WIDTH; + + logic [MMIOREQ_FIFO_WIDTH-1:0] mmioreq_din; + logic mmioreq_write; + logic mmioreq_read; + logic mmioreq_valid; + logic mmioreq_full; + logic mmioreq_empty; + logic [4:0] mmioreq_count; + + logic [CCIP_CFG_HDR_WIDTH-1:0] cwlp_header; + logic [CCIP_DATA_WIDTH-1:0] cwlp_data; + logic cwlp_wrvalid; + logic cwlp_rdvalid; + + logic mmio_wrvalid; + logic mmio_rdvalid; + logic [CCIP_DATA_WIDTH-1:0] mmio_data512; + logic [CCIP_CFG_HDR_WIDTH-1:0] mmio_hdrvec; + + logic mmio_dispatch_lock; + + // MMIO dispatch unit + task mmio_dispatch (int initialize, mmio_t mmio_pkt); + CfgHdr_t hdr; + begin + if (initialize) begin + cwlp_wrvalid = 0; + cwlp_rdvalid = 0; + cwlp_header = 0; + cwlp_data = 0; + mmio_dispatch_lock = 0; + end + else begin + while(mmio_dispatch_lock != 0); + mmio_dispatch_lock = 1; + @(posedge clk); + hdr.index = mmio_pkt.addr[CCIP_CFGHDR_ADDR_WIDTH-1:2]; + hdr.rsvd9 = 1'b0; + hdr.tid = mmio_pkt.tid[CCIP_CFGHDR_TID_WIDTH-1:0]; + // Set MMIO Width + if (mmio_pkt.width == MMIO_WIDTH_32) begin + hdr.len = 2'b00; + end + else if (mmio_pkt.width == MMIO_WIDTH_64) begin + hdr.len = 2'b01; + end + // Set MMIO Read/Write behavior + if (mmio_pkt.write_en == MMIO_WRITE_REQ) begin + if (mmio_pkt.width == MMIO_WIDTH_32) begin + cwlp_data = {480'b0, mmio_pkt.qword[0][31:0]}; + end + else if (mmio_pkt.width == MMIO_WIDTH_64) begin + cwlp_data = {448'b0, mmio_pkt.qword[0][63:0]}; + end + cwlp_header = logic_cast_CfgHdr_t'(hdr); + cwlp_wrvalid = 1; + cwlp_rdvalid = 0; + mmio_pkt.resp_en = 1; + end // if (mmio_pkt.write_en == MMIO_WRITE_REQ) + else if (mmio_pkt.write_en == MMIO_READ_REQ) begin + cwlp_data = 0; + cwlp_header = logic_cast_CfgHdr_t'(hdr); + cwlp_wrvalid = 0; + cwlp_rdvalid = 1; + mmio_pkt.resp_en = 1; + end // if (mmio_pkt.write_en == MMIO_READ_REQ) + @(posedge clk); + cwlp_wrvalid = 0; + cwlp_rdvalid = 0; + @(posedge clk); + mmio_dispatch_lock = 0; + run_clocks (`MMIO_LATENCY); + end // else: !if(initialize) + end + endtask + + // CSR readreq/write FIFO data + assign mmioreq_din = {cwlp_wrvalid, cwlp_rdvalid, cwlp_header, cwlp_data}; + assign mmioreq_write = cwlp_wrvalid | cwlp_rdvalid; + + // Request staging + ase_svfifo + #( + .DATA_WIDTH ( MMIOREQ_FIFO_WIDTH ), + .DEPTH_BASE2 ( 4 ), + .ALMFULL_THRESH ( 12 ) + ) + mmioreq_fifo + ( + .clk ( clk ), + .rst ( ase_reset ), + .wr_en ( mmioreq_write ), + .data_in ( mmioreq_din ), + .rd_en ( mmioreq_read ), + .data_out ( {mmio_wrvalid, mmio_rdvalid, mmio_hdrvec, mmio_data512} ), + .data_out_v ( mmioreq_valid ), + .alm_full ( mmioreq_full ), + .full ( ), + .empty ( mmioreq_empty ), + .count ( mmioreq_count ), + .overflow ( ), + .underflow ( ) + ); + + // Debug config header + CfgHdr_t DBG_cfgheader; + logic DBG_cfgvld; + assign DBG_cfgheader = CfgHdr_t'(C0RxHdr); + assign DBG_cfgvld = C0RxMmioWrValid | C0RxMmioRdValid; + + + /* + * MMIO Read response + */ + parameter int MMIORESP_FIFO_WIDTH = CCIP_MMIO_TID_WIDTH + CCIP_MMIO_RDDATA_WIDTH; + + logic [CCIP_MMIO_RDDATA_WIDTH-1:0] mmioresp_dout; + logic [CCIP_MMIO_TID_WIDTH-1:0] mmioresp_tid; + + logic mmioresp_read; + logic mmioresp_valid; + logic mmioresp_full; + logic mmioresp_empty; + logic [3:0] mmioresp_count; + + // Response staging FIFO + ase_svfifo + #( + .DATA_WIDTH ( MMIORESP_FIFO_WIDTH ), + .DEPTH_BASE2 ( 3 ), + .ALMFULL_THRESH ( 5 ) + ) + mmioresp_fifo + ( + .clk ( clk ), + .rst ( ase_reset ), + .wr_en ( C2TxMmioRdValid ), + .data_in ( {logic_cast_MMIOHdr_t'(C2TxHdr), C2TxData} ), + .rd_en ( mmioresp_read & ~mmioresp_empty ), + .data_out ( {mmioresp_tid, mmioresp_dout} ), + .data_out_v ( mmioresp_valid ), + .alm_full ( mmioresp_full ), + .full ( ), + .empty ( mmioresp_empty ), + .count ( mmioresp_count ), + .overflow ( ), + .underflow ( ) + ); + + // MMIO Response mask (act by reference) + function automatic void mmio_rdrsp_mask( ); + begin + // TID + mmio_rdrsp_pkt.tid = mmioresp_tid; + // Write Enable + mmio_rdrsp_pkt.write_en = MMIO_READ_REQ; + // Data (use only lower int) + mmio_rdrsp_pkt.qword[0] = mmioresp_dout; + if (mmio_rdrsp_pkt.width == 32) begin + mmio_rdrsp_pkt.qword[0][63:32] = 32'b0; + end + mmio_rdrsp_pkt.qword[1] = 0; + mmio_rdrsp_pkt.qword[2] = 0; + mmio_rdrsp_pkt.qword[3] = 0; + mmio_rdrsp_pkt.qword[4] = 0; + mmio_rdrsp_pkt.qword[5] = 0; + mmio_rdrsp_pkt.qword[6] = 0; + mmio_rdrsp_pkt.qword[7] = 0; + // Response flag + mmio_rdrsp_pkt.resp_en = 1; + // Return + mmio_response ( mmio_rdrsp_pkt ); + end + endfunction + + // MMIO Response trigger + always @(posedge clk) begin : mmio_read_proc + mmioresp_read <= ~mmioresp_empty; + end + + // FIFO writes to memory + always @(posedge clk) begin : dpi_mmio_response + if (mmioresp_valid) begin + mmio_rdrsp_mask (); + end + end + + + /* + * MMIO Write response + */ + // Function to tie Write Response + function automatic void mmio_wrrsp_mask(); + begin + // TID + mmio_wrrsp_pkt.tid = DBG_cfgheader.tid; + // Write Enable + mmio_wrrsp_pkt.write_en = MMIO_WRITE_REQ; + // Data packing + mmio_wrrsp_pkt.qword[0] = C0RxData[ 63:00 ]; + mmio_wrrsp_pkt.qword[1] = C0RxData[ 127:64 ]; + mmio_wrrsp_pkt.qword[2] = C0RxData[ 191:128 ]; + mmio_wrrsp_pkt.qword[3] = C0RxData[ 255:192 ]; + mmio_wrrsp_pkt.qword[4] = C0RxData[ 319:256 ]; + mmio_wrrsp_pkt.qword[5] = C0RxData[ 383:320 ]; + mmio_wrrsp_pkt.qword[6] = C0RxData[ 447:384 ]; + mmio_wrrsp_pkt.qword[7] = C0RxData[ 511:448 ]; + // Address + mmio_wrrsp_pkt.addr = DBG_cfgheader.index; + // Response flag + mmio_wrrsp_pkt.resp_en = 1; + // Return + mmio_response ( mmio_wrrsp_pkt ); + end + endfunction + + // Response to MMIO write (credit control only) + always @(posedge clk) begin + if (C0RxMmioWrValid) begin + mmio_wrrsp_mask( ); + end + end + + + /* ****************************************************************** + * + * Unordered Messages Engine + * umsg_dispatch: Single push process triggering UMSG machinery + * This feature is only available in integrated configuration + * + * *****************************************************************/ + logic umsgfifo_write; + logic umsgfifo_read; + logic umsgfifo_valid; + logic umsgfifo_full; + logic umsgfifo_empty; + + // Enabled only in integrated configuration +`ifdef ASE_ENABLE_UMSG_FEATURE + parameter int UMSG_FIFO_WIDTH = CCIP_RX_HDR_WIDTH + CCIP_DATA_WIDTH; + + UMsgHdr_t umsgfifo_hdr_in; + logic [CCIP_DATA_WIDTH-1:0] umsgfifo_data_in; + + logic [CCIP_DATA_WIDTH-1:0] umsgfifo_data_out; + logic [ASE_UMSG_HDR_WIDTH-1:0] umsgfifo_hdrvec_out; + + + // Data store + logic [CCIP_DATA_WIDTH-1:0] umsg_latest_data_array [0:NUM_UMSG_PER_AFU-1]; + + // Umsg engine + umsg_t umsg_array[NUM_UMSG_PER_AFU]; + + // UMSG dispatch function + task umsg_dispatch (int init, umsgcmd_t umsg_pkt); + int ii; + begin + if (init) begin + for (ii = 0; ii < NUM_UMSG_PER_AFU; ii = ii + 1) begin + umsg_latest_data_array[ii] <= {CCIP_DATA_WIDTH{1'b0}}; + umsg_array[ii].line_accessed <= 0; + umsg_array[ii].hint_enable <= 0; + end + end + else begin + umsg_array[ umsg_pkt.id ].line_accessed = 1; + umsg_array[ umsg_pkt.id ].hint_enable = umsg_pkt.hint; + umsg_latest_data_array[umsg_pkt.id][ 63:00 ] = umsg_pkt.qword[0] ; + umsg_latest_data_array[umsg_pkt.id][ 127:64 ] = umsg_pkt.qword[1] ; + umsg_latest_data_array[umsg_pkt.id][ 191:128 ] = umsg_pkt.qword[2] ; + umsg_latest_data_array[umsg_pkt.id][ 255:192 ] = umsg_pkt.qword[3] ; + umsg_latest_data_array[umsg_pkt.id][ 319:256 ] = umsg_pkt.qword[4] ; + umsg_latest_data_array[umsg_pkt.id][ 383:320 ] = umsg_pkt.qword[5] ; + umsg_latest_data_array[umsg_pkt.id][ 447:384 ] = umsg_pkt.qword[6] ; + umsg_latest_data_array[umsg_pkt.id][ 511:448 ] = umsg_pkt.qword[7] ; + run_clocks(1); + umsg_array[ umsg_pkt.id ].line_accessed = 0; + end + end + endtask + + // Umsg slot/hint selector + int umsg_data_slot; + int umsg_hint_slot; + int umsg_data_slot_old = 255; + int umsg_hint_slot_old = 255; + + logic [0:NUM_UMSG_PER_AFU-1] umsg_hint_enable_array; + logic [0:NUM_UMSG_PER_AFU-1] umsg_data_enable_array; + + logic [4:0] umsgfifo_cnt_tmp; + logic [4:0] umsgfifo_cnt; + + // UMSG Hint-to-Data time emulator (toaster style) + // New Umsg hints to same location are ignored + // If Data is same, hints dont get generated + generate + for (genvar ii = 0; ii < NUM_UMSG_PER_AFU; ii = ii + 1 ) begin : umsg_engine + + // Status board + always @(*) begin + umsg_hint_enable_array[ii] <= umsg_array[ii].hint_ready; + umsg_data_enable_array[ii] <= umsg_array[ii].data_ready; + end + + + // State machine + always @(posedge clk) begin + if (ase_reset) begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_timer <= 0; + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + umsg_array[ii].state <= UMsgIdle; + end + else begin + case (umsg_array[ii].state) + // Wait here until activated + UMsgIdle: + begin + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + if (umsg_array[ii].line_accessed && umsg_array[ii].hint_enable) begin + umsg_array[ii].hint_timer <= $urandom_range(`UMSG_START2HINT_LATRANGE); + umsg_array[ii].data_timer <= 0; + umsg_array[ii].state <= UMsgHintWait; + end + else if (umsg_array[ii].line_accessed && ~umsg_array[ii].hint_enable) begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_timer <= $urandom_range(`UMSG_START2DATA_LATRANGE); + umsg_array[ii].state <= UMsgDataWait; + end + else begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_timer <= 0; + umsg_array[ii].state <= UMsgIdle; + end + end + + // Wait to send out hint, go to UMsgSendHint after t_hint ticks + UMsgHintWait: + begin + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + umsg_array[ii].data_timer <= 0; + if (umsg_array[ii].hint_timer <= 0) begin + umsg_array[ii].state <= UMsgSendHint; + end + else begin + umsg_array[ii].hint_timer <= umsg_array[ii].hint_timer - 1; + umsg_array[ii].state <= UMsgHintWait; + end + end + + // Wait until hint popped by event queue + UMsgSendHint: + begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_ready <= 0; + if (umsg_array[ii].hint_pop) begin + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_timer <= $urandom_range(`UMSG_HINT2DATA_LATRANGE); + umsg_array[ii].state <= UMsgDataWait; + end + else begin + umsg_array[ii].hint_ready <= 1; + umsg_array[ii].data_timer <= 0; + umsg_array[ii].state <= UMsgSendHint; + end + end + + // Wait to send out data, go to UMsgSendData after t_data ticks + UMsgDataWait: + begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + if (umsg_array[ii].data_timer <= 0) begin + umsg_array[ii].state <= UMsgSendData; + end + else begin + umsg_array[ii].data_timer <= umsg_array[ii].data_timer - 1; + umsg_array[ii].state <= UMsgDataWait; + end + end + + // Wait until popped by event queue + UMsgSendData: + begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_timer <= 0; + if (umsg_array[ii].data_pop) begin + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + umsg_array[ii].state <= UMsgIdle; + end + else begin + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 1; + umsg_array[ii].state <= UMsgSendData; + end + end + + // lala-land + default: + begin + umsg_array[ii].hint_timer <= 0; + umsg_array[ii].data_timer <= 0; + umsg_array[ii].hint_ready <= 0; + umsg_array[ii].data_ready <= 0; + umsg_array[ii].state <= UMsgIdle; + end + endcase + end + end + + end + endgenerate + + + // Find UMSG Hintable slot + function int find_umsg_hint (); + int ret_hint_slot; + int slot; + int start_iter; + int end_iter; + begin + start_iter = 0; + end_iter = start_iter + NUM_UMSG_PER_AFU; + ret_hint_slot = 255; + for (slot = start_iter ; slot < end_iter ; slot = slot + 1) begin + if (umsg_array[slot].hint_ready && ~umsg_array[slot].data_ready) begin + ret_hint_slot = slot; + umsg_hint_slot_old = ret_hint_slot; + break; + end + end + return ret_hint_slot; + end + endfunction + + // Find UMSG Data slot to send + function int find_umsg_data(); + int ret_data_slot; + int slot; + int start_iter; + int end_iter; + begin + start_iter = 0; + end_iter = start_iter + NUM_UMSG_PER_AFU; + ret_data_slot = 255; + for (slot = start_iter ; slot < end_iter ; slot = slot + 1) begin + if (umsg_array[slot].data_ready) begin + ret_data_slot = slot; + umsg_data_slot_old = ret_data_slot; + break; + end + end + return ret_data_slot; + end + endfunction + + // Calculate slots for UMSGs + always @(posedge clk) begin : umsg_slot_finder_proc + umsg_data_slot <= find_umsg_data(); + umsg_hint_slot <= find_umsg_hint(); + end + + // Pop HINT/DATA + typedef enum {UPopIdle, UPopHint, UPopData, UPopWait, UPopSleep} UmsgPopStateMachine; + UmsgPopStateMachine upop_state; + + always @(posedge clk) begin : umsgfifo_pop_write + if (ase_reset) begin + umsgfifo_hdr_in <= {ASE_UMSG_HDR_WIDTH{1'b0}}; + umsgfifo_data_in <= {UMSG_FIFO_WIDTH{1'b0}}; + umsgfifo_write <= 0; + for(int jj = 0; jj < NUM_UMSG_PER_AFU; jj = jj + 1) begin + umsg_array[jj].hint_pop <= 0; + umsg_array[jj].data_pop <= 0; + end + upop_state <= UPopIdle; + end + else begin + case (upop_state) + // UMsg Pop idle + UPopIdle: + begin + umsgfifo_write <= 0; + for(int jj = 0; jj < NUM_UMSG_PER_AFU; jj = jj + 1) begin + umsg_array[jj].hint_pop <= 0; + umsg_array[jj].data_pop <= 0; + end + if (~umsgfifo_full && (umsg_hint_slot != 255)) begin + upop_state <= UPopHint; + end + else if (~umsgfifo_full && (umsg_data_slot != 255)) begin + upop_state <= UPopData; + end + else begin + upop_state <= UPopIdle; + end + end + + // Pop UMsg hint + UPopHint: + begin + umsgfifo_hdr_in.rsvd25 <= 0; + umsgfifo_hdr_in.resp_type <= ASE_UMSG; + umsgfifo_hdr_in.umsg_type <= 1; + umsgfifo_hdr_in.umsg_id <= umsg_hint_slot; + umsgfifo_data_in <= {CCIP_DATA_WIDTH{1'b0}}; + umsgfifo_write <= 1; + umsg_array[umsg_hint_slot].hint_pop <= 1; + upop_state <= UPopWait; + end + + // Pop Umsg data + UPopData: + begin + umsgfifo_hdr_in.rsvd25 <= 0; + umsgfifo_hdr_in.resp_type <= ASE_UMSG; + umsgfifo_hdr_in.umsg_type <= 0; + umsgfifo_hdr_in.umsg_id <= umsg_data_slot; + umsgfifo_data_in <= umsg_latest_data_array[umsg_data_slot]; + umsgfifo_write <= 1; + umsg_array[umsg_data_slot].data_pop <= 1; + upop_state <= UPopWait; + end + + // UMsg wait machine + UPopWait: + begin + umsgfifo_write <= 0; + for(int jj = 0; jj < NUM_UMSG_PER_AFU; jj = jj + 1) begin + umsg_array[jj].hint_pop <= 0; + umsg_array[jj].data_pop <= 0; + end + upop_state <= UPopSleep; + end + + // Stabilize, before moving on + UPopSleep: + begin + umsgfifo_write <= 0; + upop_state <= UPopIdle; + end + + default: + begin + umsgfifo_write <= 0; + for(int jj = 0; jj < NUM_UMSG_PER_AFU; jj = jj + 1) begin + umsg_array[jj].hint_pop <= 0; + umsg_array[jj].data_pop <= 0; + end + upop_state <= UPopIdle; + end + + endcase + end + end + + // UMSG events queue + ase_svfifo + #( + .DATA_WIDTH (UMSG_FIFO_WIDTH), + .DEPTH_BASE2 (4), + .ALMFULL_THRESH (12) + ) + umsg_fifo + ( + .clk ( clk ), + .rst ( ase_reset ), + .wr_en ( umsgfifo_write ), + .data_in ( { logic_cast_UMsgHdr_t'(umsgfifo_hdr_in), umsgfifo_data_in} ), + .rd_en ( umsgfifo_read & ~umsgfifo_empty ), + .data_out ( { umsgfifo_hdrvec_out, umsgfifo_data_out} ), + .data_out_v ( umsgfifo_valid ), + .alm_full ( umsgfifo_full ), + .full ( ), + .empty ( umsgfifo_empty ), + .count ( umsgfifo_cnt_tmp ), + .overflow ( ), + .underflow ( ) + ); + + // UMSG Debug header + UMsgHdr_t C0RxUMsgHdr; + assign C0RxUMsgHdr = UMsgHdr_t'(C0RxHdr); + + // Register UMSG fifo count + always @(posedge clk) begin + if (ase_reset) begin + umsgfifo_cnt <= 0; + end + else begin + umsgfifo_cnt <= umsgfifo_cnt_tmp; + end + end +`endif // `ifdef ASE_ENABLE_UMSG_FEATURE + + + /* ****************************************************************** + * + * Config data exchange - Supplied by ase.cfg + * Configuration of ASE managed by a text file, modifiable runtime + * + * *****************************************************************/ + task ase_config_dex(ase_cfg_t cfg_in); + begin + // Cfg transfer + cfg.ase_mode = cfg_in.ase_mode ; + cfg.ase_timeout = cfg_in.ase_timeout ; + cfg.ase_num_tests = cfg_in.ase_num_tests ; + cfg.enable_reuse_seed = cfg_in.enable_reuse_seed ; + cfg.ase_seed = cfg_in.ase_seed ; + cfg.enable_cl_view = cfg_in.enable_cl_view ; + cfg.usr_tps = cfg_in.usr_tps ; + cfg.phys_memory_available_gb = cfg_in.phys_memory_available_gb ; + // Set UsrClk + update_usrclk_delay( cfg.usr_tps ); + end + endtask + + + /* ****************************************************************** + * Count transactions + * Live count of transactions to be printed at end of simulation + * + * ******************************************************************/ + // MMIO Activity counts + int ase_rx0_mmiowrreq_cnt ; + int ase_rx0_mmiordreq_cnt ; + int ase_tx2_mmiordrsp_cnt ; + // Read counts + int ase_tx0_rdvalid_cnt ; + int ase_rx0_rdvalid_cnt ; + // Write counts + int ase_tx1_wrvalid_cnt ; + int ase_rx1_wrvalid_cnt ; + // Write Fence counts + int ase_tx1_wrfence_cnt ; + int ase_rx1_wrfence_cnt ; + // Umsg counts (only available in integrated configuration) +`ifdef ASE_ENABLE_UMSG_FEATURE + int ase_rx0_umsghint_cnt ; + int ase_rx0_umsgdata_cnt ; +`endif + // Interrupt counts (only available in discrete configuration) +`ifdef ASE_ENABLE_INTR_FEATURE + int ase_tx1_intrreq_cnt ; + int ase_rx1_intrrsp_cnt ; +`endif + + + // Remap UmsgHdr for count purposes +`ifdef ASE_ENABLE_UMSG_FEATURE + UMsgHdr_t ase_umsghdr_map; + assign ase_umsghdr_map = UMsgHdr_t'(C0RxHdr); +`endif + + // Count increment macro +`define incr_cnt(condition, counter_val)\ + if (condition == 1) counter_val <= counter_val + 1 + + + /* + * Transaction counts + */ + // Channel count structures + txn_vc_counts rdreq_vc_cnt , rdrsp_vc_cnt; + txn_vc_counts wrreq_vc_cnt , wrrsp_vc_cnt; + txn_vc_counts wrfreq_vc_cnt , wrfrsp_vc_cnt; + + txn_mcl_counts rdreq_mcl_cnt ; + txn_mcl_counts wrreq_mcl_cnt , wrrsp_mcl_cnt; + + // Transaction count process + always @(posedge clk) begin : transact_cnt_proc + // ===================================================== // + // Intiialization + // ===================================================== // + if (init_reset) begin + // ------------------------------------ // + // MMIO + // ------------------------------------ // + ase_rx0_mmiowrreq_cnt <= 0 ; + ase_rx0_mmiordreq_cnt <= 0 ; + ase_tx2_mmiordrsp_cnt <= 0 ; + // ------------------------------------ // + // Umsg counts + // ------------------------------------ // +`ifdef ASE_ENABLE_UMSG_FEATURE + ase_rx0_umsghint_cnt <= 0 ; + ase_rx0_umsgdata_cnt <= 0 ; +`endif + // ------------------------------------ // + // Read transactions + // ------------------------------------ // + rdreq_vc_cnt <= '{0, 0, 0, 0}; + rdrsp_vc_cnt <= '{0, 0, 0, 0}; + rdreq_mcl_cnt <= '{0, 0, 0}; + // Total read counts + ase_tx0_rdvalid_cnt <= 0 ; + ase_rx0_rdvalid_cnt <= 0 ; + // ------------------------------------ // + // Write transactions + // ------------------------------------ // + wrreq_vc_cnt <= '{0, 0, 0, 0}; + wrrsp_vc_cnt <= '{0, 0, 0, 0}; + wrreq_mcl_cnt <= '{0, 0, 0}; + wrrsp_mcl_cnt <= '{0, 0, 0}; + // Total write counts + ase_tx1_wrvalid_cnt <= 0 ; + ase_rx1_wrvalid_cnt <= 0 ; + // ------------------------------------ // + // WriteFence transactions + // ------------------------------------ // + wrfreq_vc_cnt <= '{0, 0, 0, 0}; + wrfrsp_vc_cnt <= '{0, 0, 0, 0}; + // WriteFence Counts + ase_tx1_wrfence_cnt <= 0 ; + ase_rx1_wrfence_cnt <= 0 ; + // ------------------------------------ // + // Interrupt transactions + // ------------------------------------ // +`ifdef ASE_ENABLE_INTR_FEATURE + ase_tx1_intrreq_cnt <= 0; + ase_rx1_intrrsp_cnt <= 0; +`endif + end // if (init_reset) + // ===================================================== // + // Active counts + // ===================================================== // + else begin + // ------------------------------------ // + // MMIO counts + // ------------------------------------ // + `incr_cnt (C0RxMmioWrValid, ase_rx0_mmiowrreq_cnt); + `incr_cnt (C0RxMmioRdValid, ase_rx0_mmiordreq_cnt); + `incr_cnt (C2TxMmioRdValid, ase_tx2_mmiordrsp_cnt); + // ------------------------------------ // + // UMsg counts + // ------------------------------------ // +`ifdef ASE_ENABLE_UMSG_FEATURE + `incr_cnt ( (C0RxUMsgValid && ase_umsghdr_map.umsg_type) , ase_rx0_umsghint_cnt); + `incr_cnt ( (C0RxUMsgValid && ~ase_umsghdr_map.umsg_type), ase_rx0_umsgdata_cnt); +`endif + // ------------------------------------ // + // Interrupt counts + // ------------------------------------ // +`ifdef ASE_ENABLE_INTR_FEATURE + `incr_cnt ( (C1TxValid && isIntrRequest(C1TxHdr)) , ase_tx1_intrreq_cnt); + `incr_cnt ( (C1RxRspValid && isIntrResponse(C1RxHdr)), ase_rx1_intrrsp_cnt); +`endif + // ------------------------------------ // + // Read counts + // ------------------------------------ // + // Total counts + if (C0TxValid && isReadRequest(C0TxHdr)) + ase_tx0_rdvalid_cnt <= ase_tx0_rdvalid_cnt + (C0TxHdr.len + 1); + `incr_cnt ( (C0RxRspValid && isReadResponse(C0RxHdr)), ase_rx0_rdvalid_cnt); + // C0Tx granular counts + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.vc == VC_VA )), rdreq_vc_cnt.va); + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.vc == VC_VL0)), rdreq_vc_cnt.vl0); + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.vc == VC_VH0)), rdreq_vc_cnt.vh0); + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.vc == VC_VH1)), rdreq_vc_cnt.vh1); + // C0Tx MCL granular counts + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.len == ASE_1CL)), rdreq_mcl_cnt.mcl0); + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.len == ASE_2CL)), rdreq_mcl_cnt.mcl1); + `incr_cnt ( (C0TxValid && isReadRequest(C0TxHdr) && (C0TxHdr.len == ASE_4CL)), rdreq_mcl_cnt.mcl3); + // C0Rx VC granular counts + `incr_cnt ( (C0RxRspValid && isReadResponse(C0RxHdr) && (C0RxHdr.vc_used == VC_VA)), rdrsp_vc_cnt.va); + `incr_cnt ( (C0RxRspValid && isReadResponse(C0RxHdr) && (C0RxHdr.vc_used == VC_VL0)), rdrsp_vc_cnt.vl0); + `incr_cnt ( (C0RxRspValid && isReadResponse(C0RxHdr) && (C0RxHdr.vc_used == VC_VH0)), rdrsp_vc_cnt.vh0); + `incr_cnt ( (C0RxRspValid && isReadResponse(C0RxHdr) && (C0RxHdr.vc_used == VC_VH1)), rdrsp_vc_cnt.vh1); + // ------------------------------------ // + // Write counts + // ------------------------------------ // + `incr_cnt ( (C1TxValid && isWriteRequest(C1TxHdr)) , ase_tx1_wrvalid_cnt); + if (C1RxRspValid && isWriteResponse(C1RxHdr)) begin + if (isVL0Response(C1RxHdr)) begin + ase_rx1_wrvalid_cnt <= ase_rx1_wrvalid_cnt + 1; + end + else if (isVHxResponse(C1RxHdr) && C1RxHdr.format) begin + ase_rx1_wrvalid_cnt <= ase_rx1_wrvalid_cnt + (C1RxHdr.clnum + 1); + end + end + // C1Tx VC granular counts + `incr_cnt ( (C1TxValid && isWriteRequest(C1TxHdr) && (C1TxHdr.vc == VC_VA) ), wrreq_vc_cnt.va); + `incr_cnt ( (C1TxValid && isWriteRequest(C1TxHdr) && (C1TxHdr.vc == VC_VL0)), wrreq_vc_cnt.vl0); + `incr_cnt ( (C1TxValid && isWriteRequest(C1TxHdr) && (C1TxHdr.vc == VC_VH0)), wrreq_vc_cnt.vh0); + `incr_cnt ( (C1TxValid && isWriteRequest(C1TxHdr) && (C1TxHdr.vc == VC_VH1)), wrreq_vc_cnt.vh1); + // C1Tx MCL granular counts + `incr_cnt ( (C1TxValid && C1TxHdr.sop && isWriteRequest(C1TxHdr) && (C1TxHdr.len == ASE_1CL)), wrreq_mcl_cnt.mcl0); + `incr_cnt ( (C1TxValid && C1TxHdr.sop && isWriteRequest(C1TxHdr) && (C1TxHdr.len == ASE_2CL)), wrreq_mcl_cnt.mcl1); + `incr_cnt ( (C1TxValid && C1TxHdr.sop && isWriteRequest(C1TxHdr) && (C1TxHdr.len == ASE_4CL)), wrreq_mcl_cnt.mcl3); + // C1Rx VC granular counts + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VA)), wrrsp_vc_cnt.va); + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VL0)), wrrsp_vc_cnt.vl0); + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VH0)), wrrsp_vc_cnt.vh0); + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VH1)), wrrsp_vc_cnt.vh1); + // C1Tx MCL granular counts + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (~C1RxHdr.format||(C1RxHdr.format && (C1RxHdr.clnum == ASE_1CL)))), wrrsp_mcl_cnt.mcl0); + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.clnum == ASE_2CL) && C1RxHdr.format), wrrsp_mcl_cnt.mcl1); + `incr_cnt ( (C1RxRspValid && isWriteResponse(C1RxHdr) && (C1RxHdr.clnum == ASE_4CL) && C1RxHdr.format), wrrsp_mcl_cnt.mcl3); + // ------------------------------------ // + // WriteFence counts + // ------------------------------------ // + `incr_cnt ( (C1TxValid && isWrFenceRequest(C1TxHdr)) , ase_tx1_wrfence_cnt); + `incr_cnt ( (C1RxRspValid && isWrFenceResponse(C1RxHdr)), ase_rx1_wrfence_cnt); + // C1Tx WrF VC granular counts + `incr_cnt ( (C1TxValid && isWrFenceRequest(C1TxHdr) && (C1TxHdr.vc == VC_VA) ), wrfreq_vc_cnt.va ); + `incr_cnt ( (C1TxValid && isWrFenceRequest(C1TxHdr) && (C1TxHdr.vc == VC_VL0)), wrfreq_vc_cnt.vl0); + `incr_cnt ( (C1TxValid && isWrFenceRequest(C1TxHdr) && (C1TxHdr.vc == VC_VH0)), wrfreq_vc_cnt.vh0); + `incr_cnt ( (C1TxValid && isWrFenceRequest(C1TxHdr) && (C1TxHdr.vc == VC_VH1)), wrfreq_vc_cnt.vh1); + // C1Rx WrF VC granular counts + `incr_cnt ( (C1RxRspValid && isWrFenceResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VA) ), wrfrsp_vc_cnt.va ); + `incr_cnt ( (C1RxRspValid && isWrFenceResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VL0)), wrfrsp_vc_cnt.vl0 ); + `incr_cnt ( (C1RxRspValid && isWrFenceResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VH0)), wrfrsp_vc_cnt.vh0 ); + `incr_cnt ( (C1RxRspValid && isWrFenceResponse(C1RxHdr) && (C1RxHdr.vc_used == VC_VH1)), wrfrsp_vc_cnt.vh1 ); + end + end + + + /* + * Count error flag + */ + int count_error_flag; + always @(posedge clk) begin + if (init_reset) begin + count_error_flag <= 0; + end + else begin + if (ase_tx0_rdvalid_cnt != ase_rx0_rdvalid_cnt) + count_error_flag <= 1; + else if (ase_tx1_wrvalid_cnt != ase_rx1_wrvalid_cnt) + count_error_flag <= 1; + else if (ase_tx2_mmiordrsp_cnt != ase_rx0_mmiordreq_cnt) + count_error_flag <= 1; + else if (ase_tx1_wrfence_cnt != ase_rx1_wrvalid_cnt) + count_error_flag <= 1; + else + count_error_flag <= 0; + end + end // always @ (posedge clk) + + + // Ping to get error flag + task count_error_flag_ping(); + begin + count_error_flag_pong(glbl_dealloc_credit); + end + endtask + + + /* ******************************************************************* + * + * Unified message watcher daemon + * - Looks for MMIO Requests, buffer requests + * + * *******************************************************************/ + always @(posedge clk) begin : daemon_proc + ase_listener(); + end + + + /* ******************************************************************* + * + * TX to RX channel FULFILLMENT + * + * ------------------------------------------------------------------- + * stg0 | stg1 | stg2 + * ------------------------------------- + * latbuf_out | cast & DEX | Response + * | tx_pkt | tx_pkt_q + * + * *******************************************************************/ + // Read response staging signals + logic [CCIP_RX_HDR_WIDTH-1:0] rdrsp_hdr_out_vec; + logic [CCIP_DATA_WIDTH-1:0] rdrsp_data_in, rdrsp_data_out; + RxHdr_t rdrsp_hdr_in, rdrsp_hdr_out; + logic rdrsp_write; + logic rdrsp_read; + logic rdrsp_full; + logic rdrsp_empty; + logic rdrsp_valid; + + // Atomics response staging signals + // logic [CCIP_RX_HDR_WIDTH-1:0] atomics_hdr_out_vec; + // logic [CCIP_DATA_WIDTH-1:0] atomics_data_in, atomics_data_out; + // Atomics_t atomics_hdr_in, atomics_hdr_out; + // logic atomics_write; + // logic atomics_read; + // logic atomics_full; + // logic atomics_empty; + // logic atomics_valid; + + // Pre-packed signals + logic [CCIP_RX_HDR_WIDTH-1:0] wrrsp_hdr_out_vec; + RxHdr_t wrrsp_hdr_in, wrrsp_hdr_out; + logic wrrsp_write; + logic wrrsp_read; + logic wrrsp_full; + logic wrrsp_empty; + logic wrrsp_valid; + + // Write response 1 staging signals + // logic [CCIP_RX_HDR_WIDTH-1:0] pp_wrrsp_hdr_out_vec; + RxHdr_t pp_wrrsp_hdr; + logic pp_wrrsp_write; + + + /* + * FUNCTION: Cast TxHdr_t to cci_pkt + */ + function automatic void cast_txhdr_to_ccipkt (ref cci_pkt pkt, + input TxHdr_t txhdr, + input [CCIP_DATA_WIDTH-1:0] txdata); + t_ccip_c1_ReqIntrHdr ccip_intr_txhdr; + begin + case (txhdr.reqtype) + ASE_RDLINE_S: + begin + pkt.mode = CCIPKT_READ_MODE; + pkt.resp_channel = 0; + end + ASE_RDLINE_I: + begin + pkt.mode = CCIPKT_READ_MODE; + pkt.resp_channel = 0; + end + ASE_WRLINE_M: + begin + pkt.mode = CCIPKT_WRITE_MODE; + pkt.resp_channel = 1; + end + ASE_WRLINE_I: + begin + pkt.mode = CCIPKT_WRITE_MODE; + pkt.resp_channel = 1; + end + ASE_WRPUSH: + begin + pkt.mode = CCIPKT_WRITE_MODE; + pkt.resp_channel = 1; + end + ASE_WRFENCE: + begin + pkt.mode = CCIPKT_WRFENCE_MODE; + pkt.resp_channel = 1; + end +`ifdef ASE_ENABLE_INTR_FEATURE + ASE_INTR_REQ: + begin + pkt.mode = CCIPKT_INTR_MODE; + pkt.resp_channel = 1; + end +`endif + // ASE_ATOMIC_REQ: + // begin + // pkt.mode = CCIPKT_ATOMIC_MODE; + // pkt.resp_channel = 0; + // end + endcase + // Metadata + pkt.mdata = int'(txhdr.mdata); + // cache line address + pkt.cl_addr = longint'(txhdr.addr); + // Qword assignment + pkt.qword[0] = txdata[ 63:00 ]; + pkt.qword[1] = txdata[ 127:64 ]; + pkt.qword[2] = txdata[ 191:128 ]; + pkt.qword[3] = txdata[ 255:192 ]; + pkt.qword[4] = txdata[ 319:256 ]; + pkt.qword[5] = txdata[ 383:320 ]; + pkt.qword[6] = txdata[ 447:384 ]; + pkt.qword[7] = txdata[ 511:448 ]; + // Interrupt ID set + ccip_intr_txhdr = t_ccip_c1_ReqIntrHdr'(txhdr); + pkt.intr_id = ccip_intr_txhdr.id; + // Response enable + end + endfunction + + + /* + * CAFU->ASE CH0 (TX0) + * Formed as {TxHdr_t} + * Latency scoreboard (for latency modeling and shuffling) + */ + `FORWARDING_CHANNEL + #( + .DEBUG_LOGNAME ("latbuf_ch0.log"), + .NUM_WAIT_STATIONS (LATBUF_NUM_TRANSACTIONS), + .NUM_STATIONS_FULL_THRESH (LATBUF_FULL_THRESHOLD), + .COUNT_WIDTH (LATBUF_COUNT_WIDTH), + .VISIBLE_DEPTH_BASE2 (8), + .VISIBLE_FULL_THRESH (220), + .LATBUF_MAX_TXN (1), + .WRITE_CHANNEL (0) + ) + cf2as_latbuf_ch0 + ( + .clk ( clk ), + .rst ( ase_reset ), + .finish_trigger ( finish_trigger ), + .hdr_in ( C0TxHdr ), + .data_in ( {CCIP_DATA_WIDTH{1'b0}} ), + .write_en ( C0TxValid ), + .txhdr_out ( cf2as_latbuf_tx0hdr ), + .rxhdr_out ( cf2as_latbuf_rx0hdr ), + .data_out ( ), + .valid_out ( cf2as_latbuf_ch0_valid ), + .read_en ( cf2as_latbuf_ch0_read ), + .empty ( cf2as_latbuf_ch0_empty ), + .almfull ( C0TxAlmFull ), + .full ( cf2as_ch0_realfull ), + .overflow_error ( ), + .hazpkt_in ( haz_if.read_in ), + .hazpkt_out ( haz_if.read_out ) + ); + + // Read TX0 + always @(posedge clk) begin + if (ase_reset) begin + cf2as_latbuf_ch0_read <= 0; + end + else if (~cf2as_latbuf_ch0_empty && ~rdrsp_full) begin + cf2as_latbuf_ch0_read <= 1; + end + else begin + cf2as_latbuf_ch0_read <= 0; + end + end + + // TASK: cf2as_ch0_to_rdrsp_fifo + task cf2as_ch0_to_rdrsp_fifo(); + cci_pkt Tx0_pkt; + begin + // Cast ccipkt from txhdr + cast_txhdr_to_ccipkt( Tx0_pkt, cf2as_latbuf_tx0hdr, {CCIP_DATA_WIDTH{1'b0}} ); + // Read line fulfillment + rd_memline_dex(Tx0_pkt); + // Write to rdrsp_fifo + rdrsp_data_in <= unpack_ccipkt_to_vector(Tx0_pkt); + rdrsp_hdr_in <= cf2as_latbuf_rx0hdr; + // $display(" ** DEBUG **: %d => cf2as_latbuf_rx0hdr.mdata = %x", $time, cf2as_latbuf_rx0hdr); + end + endtask + + // Glue process + always @(posedge clk) begin + if (ase_reset) begin + rdrsp_write <= 0; + end + else if (cf2as_latbuf_ch0_valid) begin + cf2as_ch0_to_rdrsp_fifo(); + rdrsp_write <= 1; + end + else begin + rdrsp_write <= 0; + end + end + + + /* + * CAFU->ASE CH1 (TX1) + * Formed as {TxHdr_t, } + * Latency scoreboard (latency modeling and shuffling) + */ + `FORWARDING_CHANNEL + #( + .DEBUG_LOGNAME ("latbuf_ch1.log"), + .NUM_WAIT_STATIONS (LATBUF_NUM_TRANSACTIONS), + .NUM_STATIONS_FULL_THRESH (LATBUF_FULL_THRESHOLD), + .COUNT_WIDTH (LATBUF_COUNT_WIDTH), + .VISIBLE_DEPTH_BASE2 (8), + .VISIBLE_FULL_THRESH (220), + .LATBUF_MAX_TXN (4), + .WRITE_CHANNEL (1) + ) + cf2as_latbuf_ch1 + ( + .clk ( clk ), + .rst ( ase_reset ), + .finish_trigger ( finish_trigger ), + .hdr_in ( C1TxHdr ), + .data_in ( C1TxData ), + .write_en ( C1TxValid ), + .txhdr_out ( cf2as_latbuf_tx1hdr ), + .rxhdr_out ( cf2as_latbuf_rx1hdr ), + .data_out ( cf2as_latbuf_tx1data ), + .valid_out ( cf2as_latbuf_ch1_valid), + .read_en ( cf2as_latbuf_ch1_read ), + .empty ( cf2as_latbuf_ch1_empty ), + .almfull ( C1TxAlmFull ), + .full ( cf2as_ch1_realfull ), + .overflow_error ( ), + .hazpkt_in ( haz_if.write_in ), + .hazpkt_out ( haz_if.write_out ) + ); + + + // Read TX1 + always @(posedge clk) begin + if (ase_reset) begin + cf2as_latbuf_ch1_read <= 0; + end + else if (~cf2as_latbuf_ch1_empty && ~wrrsp_full) begin + cf2as_latbuf_ch1_read <= 1; + end + else begin + cf2as_latbuf_ch1_read <= 0; + end + end + + // TASK: cf2as_latbuf_to_wrrsp_fifo + task cf2as_latbuf_to_wrrsp_fifo(); + cci_pkt Tx1_pkt; + begin + // Cast ccipkt from txhdr + cast_txhdr_to_ccipkt(Tx1_pkt, cf2as_latbuf_tx1hdr, cf2as_latbuf_tx1data); + // Write memory + wr_memline_dex(Tx1_pkt); + // Write to wrrsp_fifo + pp_wrrsp_hdr = cf2as_latbuf_rx1hdr; + // $display(" ** DEBUG **: %d => cf2as_latbuf_rx1hdr.mdata = %x", $time, cf2as_latbuf_rx1hdr); + end + endtask + + + /* + * WrResp Coalescer + * -------------------------------------------- + * - If cf2as_latbuf_ch1_valid is HIGH + * - If cf2as_latbuf_rx1hdr.fmt is HIGH + * - If cf2as_latbuf_rx1hdr.fmt is LOW + * - Fullfill request and passthru + */ + + // Packing states + typedef enum { + PassThru_Pack1CL, + Pack2CL, + Pack3CL, + Pack4CL, + PackError + } c1rx_pack_state; + + c1rx_pack_state pack_state; + + RxHdr_t pack_hdr; + logic pack_hdr_valid; + + // Packing input register +`ifdef VCS + always @(posedge clk) begin + pack_hdr <= pp_wrrsp_hdr; + pack_hdr_valid <= pp_wrrsp_write; + end +`else + `ifdef QUESTA + assign pack_hdr = pp_wrrsp_hdr; + assign pack_hdr_valid = pp_wrrsp_write; + `else + // Compile time error goes here ?? + unsupported rtl compiler found + `endif +`endif + + // Packing state machine + always @(posedge clk) begin + if (ase_reset) begin + pack_state <= PassThru_Pack1CL; + wrrsp_write <= 0; + wrrsp_hdr_in <= RxHdr_t'(0); + end + else begin + case (pack_state) + // ---------------------------------------- // + // Pack 1CL if format enable, else passthru + // ---------------------------------------- // + PassThru_Pack1CL: + begin + if (pack_hdr_valid) begin + if (pack_hdr.format) begin + if (pack_hdr.clnum == ASE_1CL) begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 1; + pack_state <= PassThru_Pack1CL; + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack2CL; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 1; + pack_state <= PassThru_Pack1CL; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PassThru_Pack1CL; + end + end + + // ---------------------------------------- // + // Pack 2CL/4CL if format enable, else ERROR + // ---------------------------------------- // + Pack2CL: + begin + if (pack_hdr_valid) begin + if (pack_hdr.format) begin + if (pack_hdr.clnum == ASE_2CL) begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 1; + pack_state <= PassThru_Pack1CL; + end + else if (pack_hdr.clnum == ASE_4CL) begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack3CL; + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PackError; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PackError; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack2CL; + end + end + + // ---------------------------------------- // + // Pack 3CL if format enable, else ERROR + // ---------------------------------------- // + Pack3CL: + begin + if (pack_hdr_valid) begin + if (pack_hdr.format) begin + if (pack_hdr.clnum == ASE_4CL) begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack4CL; + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PackError; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PackError; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack3CL; + end + end + + // ---------------------------------------- // + // Pack 4CL if format enable, else ERROR + // ---------------------------------------- // + Pack4CL: + begin + if (pack_hdr_valid) begin + if (pack_hdr.format && pack_hdr.clnum == ASE_4CL) begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 1; + pack_state <= PassThru_Pack1CL; + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PackError; + end + end + else begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= Pack4CL; + end + end + + // --------------------------------------------------- // + // Packing ERROR, bail out | ASE should not reach here + // --------------------------------------------------- // + PackError: + begin + `BEGIN_RED_FONTCOLOR; + $display("** ERROR ** : %d => Unexpected formatting order found --- packing cannot proceed, EXITING", $time); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + + // --------------------------------------------------- // + // Default + // --------------------------------------------------- // + default: + begin + wrrsp_hdr_in <= pack_hdr; + wrrsp_write <= 0; + pack_state <= PassThru_Pack1CL; + end + endcase + end + end + + + // latbuf_ch1 -> pack logic + always @(posedge clk) begin + if (ase_reset) begin + pp_wrrsp_write <= 0; + end + else if (cf2as_latbuf_ch1_valid) begin + cf2as_latbuf_to_wrrsp_fifo(); + pp_wrrsp_write <= 1; + end + else begin + pp_wrrsp_write <= 0; + end + end + + + /* ******************************************************************* + * RESPONSE PATHS + * ------------------------------------------------------------------- + * as2cf_rdresp_fifo | Read Response staging + * as2cf_wrresp_fifo | Write Response staging + * as2cf_umsg_fifo | Unordered message staging + * + * *******************************************************************/ + /* + * RX0 Read Response staging + */ + ase_svfifo + #( + .DATA_WIDTH ( CCIP_RX_HDR_WIDTH + CCIP_DATA_WIDTH ), + .DEPTH_BASE2 ( ASE_RSPFIFO_COUNT_WIDTH ), + .ALMFULL_THRESH ( ASE_RSPFIFO_ALMFULL_THRESH ) + ) + rdrsp_fifo + ( + .clk ( clk ), + .rst ( ase_reset ), + .wr_en ( rdrsp_write ), + .data_in ( { logic_cast_RxHdr_t'(rdrsp_hdr_in), rdrsp_data_in } ), + .rd_en ( ~rdrsp_empty && rdrsp_read ), + .data_out ( { rdrsp_hdr_out_vec, rdrsp_data_out } ), + .data_out_v ( rdrsp_valid ), + .alm_full ( rdrsp_full ), + .full (), + .empty ( rdrsp_empty ), + .count ( rdrsp_fifo_cnt ), + .overflow (), + .underflow () + ); + + assign rdrsp_hdr_out = RxHdr_t'(rdrsp_hdr_out_vec); + + + /* + * RX1 Write Response staging + */ + ase_svfifo + #( + .DATA_WIDTH ( CCIP_RX_HDR_WIDTH ), + .DEPTH_BASE2 ( ASE_RSPFIFO_COUNT_WIDTH ), + .ALMFULL_THRESH ( ASE_RSPFIFO_ALMFULL_THRESH ) + ) + wrrsp_fifo + ( + .clk ( clk ), + .rst ( ase_reset ), + .wr_en ( wrrsp_write ), + .data_in ( logic_cast_RxHdr_t'(wrrsp_hdr_in) ), + .rd_en ( ~wrrsp_empty && wrrsp_read ), + .data_out ( wrrsp_hdr_out_vec ), + .data_out_v ( wrrsp_valid ), + .alm_full ( wrrsp_full ), + .full (), + .empty ( wrrsp_empty ), + .count ( wrrsp_fifo_cnt ), + .overflow (), + .underflow () + ); + + assign wrrsp_hdr_out = RxHdr_t'(wrrsp_hdr_out_vec); + + + /* ******************************************************************* + * RX0 Channel management + * ------------------------------------------------------------------- + * - MMIO Request management + * When request is seen in mmioreq_fifo, it is forwarded to + * CCIP-RX0 + * - Read Response + * When response is seen in as2cf_rdresp_fifo, it is forwarded to + * CCIP-RX0 + * - Write response + * When response is seen in as2cf_wrresp_fifo & tx2rx_chsel == 0, it + * is forwarded to CCIP-RX0 + * + * *******************************************************************/ + // Read from staging FIFOs + always @(posedge clk) begin + if (ase_reset) begin + mmioreq_read <= 0; + rdrsp_read <= 0; + umsgfifo_read <= 0; + end + else if (~mmioreq_empty) begin + mmioreq_read <= 1; + rdrsp_read <= 0; + umsgfifo_read <= 0; + end + else if (~umsgfifo_empty) begin + mmioreq_read <= 0; + rdrsp_read <= 0; + umsgfifo_read <= 1; + end + else if (~rdrsp_empty) begin + mmioreq_read <= 0; + rdrsp_read <= 1; + umsgfifo_read <= 0; + end + else begin + mmioreq_read <= 0; + rdrsp_read <= 0; + umsgfifo_read <= 0; + end + end + + // Output channel + always @(posedge clk) begin + if (SoftReset) begin + C0RxMmioWrValid <= 0; + C0RxMmioRdValid <= 0; + C0RxRdValid <= 0; + C0RxUMsgValid <= 0; + C0RxHdr <= RxHdr_t'({CCIP_RX_HDR_WIDTH{1'b0}}); + C0RxData <= {CCIP_DATA_WIDTH{1'b0}}; + end + else if (mmioreq_valid) begin + C0RxMmioWrValid <= mmio_wrvalid; + C0RxMmioRdValid <= mmio_rdvalid; + C0RxRdValid <= 0; + C0RxUMsgValid <= 0; + C0RxHdr <= RxHdr_t'(mmio_hdrvec); + C0RxData <= mmio_data512; + end +`ifdef ASE_ENABLE_UMSG_FEATURE + else if (umsgfifo_valid) begin + C0RxMmioWrValid <= 0; + C0RxMmioRdValid <= 0; + C0RxRdValid <= 0; + C0RxUMsgValid <= umsgfifo_valid; + C0RxHdr <= RxHdr_t'(umsgfifo_hdrvec_out); + C0RxData <= umsgfifo_data_out; + end +`endif + else if (rdrsp_valid) begin + C0RxMmioWrValid <= 0; + C0RxMmioRdValid <= 0; + C0RxRdValid <= rdrsp_valid; + C0RxUMsgValid <= 0; + C0RxHdr <= rdrsp_hdr_out; + C0RxData <= rdrsp_data_out; + end + else begin + C0RxMmioWrValid <= 0; + C0RxMmioRdValid <= 0; + C0RxRdValid <= 0; + C0RxUMsgValid <= 0; + C0RxHdr <= RxHdr_t'({CCIP_RX_HDR_WIDTH{1'b0}}); + C0RxData <= {CCIP_DATA_WIDTH{1'b0}}; + end + end + + // C0Rx Valid aggregate + assign C0RxRspValid = C0RxRdValid | C0RxUMsgValid; + + + /* ******************************************************************* + * RX1 Channel management + * -------------------------------------------------------------- + * - Write response + * When response is seen in as2cf_wrresp_fifo & tx2rx_chsel == 1, it + * is forwarded to CCIP-RX1 + * + * *******************************************************************/ + // Read from staging FIFOs + always @(posedge clk) begin + if (ase_reset) begin + wrrsp_read <= 0 ; + end + else if (~wrrsp_empty) begin + wrrsp_read <= 1 ; + end + else begin + wrrsp_read <= 0 ; + end + end + + // Output register + always @(posedge clk) begin + if (SoftReset) begin + C1RxHdr <= {CCIP_RX_HDR_WIDTH{1'b0}}; + C1RxWrValid <= 0; + C1RxIntrValid <= 0; + end + else if (wrrsp_valid) begin + C1RxHdr <= RxHdr_t'(wrrsp_hdr_out); + C1RxWrValid <= wrrsp_valid; + C1RxIntrValid <= 0; + end + else begin + C1RxHdr <= {CCIP_RX_HDR_WIDTH{1'b0}}; + C1RxWrValid <= 0; + C1RxIntrValid <= 0; + end + end + + // Rx1 aggregate valid + assign C1RxRspValid = C1RxWrValid | C1RxIntrValid; + + + /* ******************************************************************* + * Inactivity management block + * + * DESCRIPTION: Running ASE simulations for too long can cause + * large dump-files to be formed. To prevent this, the + * inactivity counter will close down the simulation + * when CCI transactions are not seen for a long + * duration of time. + * + * This feature can be disabled, if desired. + * + * *******************************************************************/ + logic first_transaction_seen; + int inactivity_counter; + logic any_valid; + logic inactivity_found; + + + // Inactivity management - Sense first transaction + always @(posedge clk) begin : any_valid_proc + if (ase_reset) begin + any_valid <= 0; + end + else begin + any_valid <= pck_cp2af_sRx.c0.rspValid | + pck_cp2af_sRx.c0.mmioRdValid | + pck_cp2af_sRx.c0.mmioWrValid | + pck_cp2af_sRx.c1.rspValid | + pck_af2cp_sTx.c0.valid | + pck_af2cp_sTx.c1.valid | + pck_af2cp_sTx.c2.mmioRdValid; + end + end + + // First transaction seen + always @(posedge clk) begin : first_txn_watcher + if (ase_reset) begin + first_transaction_seen <= 0; + end + else if ( ~first_transaction_seen && any_valid ) begin + first_transaction_seen <= 1; + end + end + + // Inactivity watchdog counter + always @(posedge clk) begin : inact_ctr + if (cfg.ase_mode != ASE_MODE_TIMEOUT_SIMKILL) begin + inactivity_counter <= 0; + end + else begin + // Watchdog countdown + if (first_transaction_seen && any_valid) begin + inactivity_counter <= 0; + end + else if (first_transaction_seen && ~any_valid) begin + inactivity_counter <= inactivity_counter + 1; + end + end + end + + // Inactivity management - killswitch + always @(posedge clk) begin : call_simkill_countdown + if ( (inactivity_counter > cfg.ase_timeout) && (cfg.ase_mode == ASE_MODE_TIMEOUT_SIMKILL) ) begin + $display(" [SIM] Inactivity timeout reached !!\n"); + start_simkill_countdown(); + end + end + + + /* + * Initialization procedure + * + * DESCRIPTION: This procedural block is called when ./simv is + * kicked off, helps put the simulation in a known + * state. + * + * STEPS: + * - Print startup info + * - Send initial system reset, cleaning up state machines + * - Initialize ASE (ase_init executes in SW) + * - Set up message queues for IPC (done in SW) + * - Set up memory management structure (called in SW) + * - If ENABLED, start the CA-private memory region (emulated with + * software + * - Then set up the QLP InitDone signal to go indicate readiness + * - SIMULATION is ready to begin + * + */ + initial begin : ase_entry_point + init_reset <= 1; + $display(" [SIM] Simulator started..."); + + // Check if simulator is already running in this directory: + // If YES, kill simulator, post message + // If NO, continue + ase_ready_pid = ase_instance_running(); + if (ase_ready_pid != 0) begin + `BEGIN_RED_FONTCOLOR; + $display(" [SIM] An ASE instance is probably still running in current directory !"); + $display(" [SIM] Check for PID %d", ase_ready_pid); + $display(" [SIM] Simulation will exit... you may use a SIGKILL to kill the simulation process."); + $display(" [SIM] Also check if '.ase_ready.pid' file is removed before proceeding."); + `END_RED_FONTCOLOR; + $finish; + end + + // AFU reset + init_reset <= 0; + afu_softreset_trig(1, 0 ); + + // Initialize mmio_dispatch function (both integrated & discrete) + mmio_dispatch (1, '{0, 0, 0, 0, '{0,0,0,0,0,0,0,0}, 0}); + + // Initialize umsg_dispatch function (integrated only) +`ifdef ASE_ENABLE_UMSG_FEATURE + umsg_dispatch (1, '{0, 0, '{0,0,0,0,0,0,0,0}}); +`endif + + // Globally write CONFIG, SCRIPT paths + if (config_filepath.len() != 0) begin + sv2c_config_dex(config_filepath); + end + if (script_filepath.len() != 0) begin + sv2c_script_dex(script_filepath); + end + + // Initialize SW side of ASE + ase_init(); + + // Read seed and print + $display(" [SIM] ASE running with seed => %d", cfg.ase_seed); + // $srandom(cfg.ase_seed); + // $urandom(cfg.ase_seed); + + // Initial signal values + $display(" [SIM] Sending initial reset..."); + ase_reset_trig(); + + sw_reset_trig <= 0; + run_clocks(20); + + // Indicate to APP that ASE is ready + ase_ready(); + end + + + /* + * ASE Flow control error monitoring + */ + // Flow simkill + task flowerror_simkill(int sim_time, int channel) ; + begin + `BEGIN_RED_FONTCOLOR; + $display(" [SIM] ASE has detected a possible OVERFLOW or UNDERFLOW error."); + $display(" [SIM] Check simulation around time, t = %d in Channel %d", sim_time, channel); + $display(" [SIM] Simulation will end now"); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + endtask + + + /* + * CCI-P Checker + * Aggregate point for all ASE checkers + * - XZ checker + * - Data hazard warning + */ +`ifndef ASE_DISABLE_CHECKER + + assign ase_checker_disable = 0; + + // ccip_checker instance + ccip_checker ccip_checker + ( + // ----------------------------------------- // + // Logger control + .finish_logger (finish_trigger ), + .init_sniffer (ase_reset ), + .ase_reset (ase_reset ), + // ----------------------------------------- // + // CCIP ports + .clk ( clk ), + .SoftReset ( SoftReset ), + .ccip_rx ( pck_cp2af_sRx ), + .ccip_tx ( pck_af2cp_sTx ), + // ----------------------------------------- // + // Hazard checker interface + .haz_if ( haz_if ), + .error_code ( ), + // ----------------------------------------- // + // Overflow check signals + .cf2as_ch0_realfull ( cf2as_ch0_realfull ), + .cf2as_ch1_realfull ( cf2as_ch1_realfull ) + ); +`else + assign ase_checker_disable = 1; +`endif + + + /* + * CCI Logger module + */ +`ifndef ASE_DISABLE_LOGGER + + assign ase_logger_disable = 0; + + // ccip_logger instance + ccip_logger + #( + .LOGNAME ("ccip_transactions.tsv") + ) + ccip_logger + ( + // Logger control + .finish_logger ( finish_trigger ), + .stdout_en ( cfg.enable_cl_view[0]), + // Buffer message injection + .log_string_en ( buffer_msg_en ), + .log_timestamp_en ( buffer_msg_tstamp_en ), + .log_string ( buffer_msg ), + // CCIP ports + .clk ( clk ), + .SoftReset ( SoftReset ), + .ccip_rx ( pck_cp2af_sRx ), + .ccip_tx ( pck_af2cp_sTx ) + ); +`else + assign ase_logger_disable = 1; +`endif // `ifndef ASE_DISABLE_LOGGER + + /* + * Transaction drop checker + */ +`ifdef ASE_DEBUG + longint rdtxn_array[*]; + longint wrtxn_array[*]; + longint wrf_array[*]; + + logic [1:0] c1tx_mcl; + + // Check and delete by key + function automatic void ccip_txn_check_delete(longint key, ref longint assoc_array [*] ); + begin + if (assoc_array.exists( key )) begin + assoc_array.delete( key); + end + else begin + `BEGIN_RED_FONTCOLOR; + $display(" ** ERROR ** ccip_emulator checker couldnt find key=%x", key); + `END_RED_FONTCOLOR; + end + end + endfunction + + // Iterate-print + // function automatic void print_assoc_array(ref longint assoc_array[*]); + // longint temp; + // begin + // if (assoc_array.first(temp)) + // do + // $display("( %05x : %12x) ", temp, assoc_array[temp] ); + // while (assoc_array.next(temp)); + // end + // endfunction + + // c1tx_mcl + always @(*) begin + if (C1TxHdr.sop) begin + c1tx_mcl = C1TxHdr.len; + end + end + +`endif + + + /* ****************************************************************** + * + * This call is made on ERRORs requiring a shutdown + * simkill is called from software, and is the final step before + * graceful closedown + * + * *****************************************************************/ + // Flag + logic simkill_started = 0; + +`ifdef ASE_PROFILE + int hist_ch0_fd, hist_ch1_fd; +`endif + + // Simkill progress + task simkill(); + string print_str; + begin + simkill_started = 1; + $display(" [SIM] Simulation kill command received..."); + // Print transactions + `BEGIN_YELLOW_FONTCOLOR; + $display(" Transaction count \t| %8s %8s %8s %8s | %8s %8s %8s", "VA", "VL0", "VH0", "VH1", "MCL-1", "MCL-2", "MCL-4"); + $display(" ========================================================================================"); + $display(" MMIOWrReq %d | ", ase_rx0_mmiowrreq_cnt ); + $display(" MMIORdReq %d | ", ase_rx0_mmiordreq_cnt ); + $display(" MMIORdRsp %d | ", ase_tx2_mmiordrsp_cnt ); +`ifdef ASE_ENABLE_UMSG_FEATURE + $display(" UMsgHint %d | ", ase_rx0_umsghint_cnt ); + $display(" UMsgData %d | ", ase_rx0_umsgdata_cnt ); +`endif +`ifdef ASE_ENABLE_INTR_FEATURE + $display(" IntrReq %d | ", ase_tx1_intrreq_cnt ); + $display(" IntrResp %d | ", ase_rx1_intrrsp_cnt ); +`endif + $display(" RdReq %d | %8d %8d %8d %8d | %8d %8d %8d", + ase_tx0_rdvalid_cnt, rdreq_vc_cnt.va, rdreq_vc_cnt.vl0, rdreq_vc_cnt.vh0, rdreq_vc_cnt.vh1, rdreq_mcl_cnt.mcl0, rdreq_mcl_cnt.mcl1, rdreq_mcl_cnt.mcl3); + $display(" RdResp %d | %8d %8d %8d %8d | ", + ase_rx0_rdvalid_cnt, rdrsp_vc_cnt.va, rdrsp_vc_cnt.vl0, rdrsp_vc_cnt.vh0, rdrsp_vc_cnt.vh1); + $display(" WrReq %d | %8d %8d %8d %8d | %8d %8d %8d", + ase_tx1_wrvalid_cnt, wrreq_vc_cnt.va, wrreq_vc_cnt.vl0, wrreq_vc_cnt.vh0, wrreq_vc_cnt.vh1, wrreq_mcl_cnt.mcl0, wrreq_mcl_cnt.mcl1, wrreq_mcl_cnt.mcl3); + $display(" WrResp %d | %8d %8d %8d %8d | %8d %8d %8d", + ase_rx1_wrvalid_cnt, wrrsp_vc_cnt.va, wrrsp_vc_cnt.vl0, wrrsp_vc_cnt.vh0, wrrsp_vc_cnt.vh1, wrrsp_mcl_cnt.mcl0, wrrsp_mcl_cnt.mcl1, wrrsp_mcl_cnt.mcl3); + $display(" WrFence %d | %8d %8d %8d %8d | ", + ase_tx1_wrfence_cnt, wrfreq_vc_cnt.va, wrfreq_vc_cnt.vl0, wrfreq_vc_cnt.vh0, wrfreq_vc_cnt.vh1); + $display(" WrFenRsp %d | %8d %8d %8d %8d | ", + ase_rx1_wrfence_cnt, wrfrsp_vc_cnt.va, wrfrsp_vc_cnt.vl0, wrfrsp_vc_cnt.vh0, wrfrsp_vc_cnt.vh1); + `END_YELLOW_FONTCOLOR; + + // Valid Count +`ifdef ASE_DEBUG + // Print errors + `BEGIN_RED_FONTCOLOR; + if (ase_tx0_rdvalid_cnt != ase_rx0_rdvalid_cnt) + $display("\tREADs : Response counts dont match request count !!"); + if (ase_tx1_wrvalid_cnt != ase_rx1_wrvalid_cnt) + $display("\tWRITEs : Response counts dont match request count !!"); + if (ase_tx2_mmiordrsp_cnt != ase_rx0_mmiordreq_cnt) + $display("\tMMIORd : Response counts dont match request count !!"); + if (ase_tx1_wrfence_cnt != ase_rx1_wrfence_cnt) + $display("\tWrFence : Response counts dont match request count !!"); + `END_RED_FONTCOLOR; + // Dropped transactions + `BEGIN_YELLOW_FONTCOLOR; + $display("-----------------------------------------------------------------"); + $display("cf2as_latbuf_ch0 contents =>"); + $display(ase_top.ccip_emulator.cf2as_latbuf_ch0.check_hdr_array); + $display("cf2as_latbuf_ch1 contents =>"); + $display(ase_top.ccip_emulator.cf2as_latbuf_ch1.check_hdr_array); + $display("-----------------------------------------------------------------"); + `END_YELLOW_FONTCOLOR; +`endif + + // Histogram dump generator +`ifdef ASE_PROFILE + `BEGIN_YELLOW_FONTCOLOR; + $display("Generating Latency distribution histograms... cf2as_latbuf_ch0"); + hist_ch0_fd = $fopen("latbuf_ch0.hist.dat", "w"); + for(int ii = 0; ii < `ASE_MAX_LATENCY; ii = ii + 1) begin + $fwrite(hist_ch0_fd, "%d\t%d\n", ii, ase_top.ccip_emulator.cf2as_latbuf_ch0.histogram_stats[ii]); + end + $fclose(hist_ch0_fd); + $display("Generating Latency distribution histograms... cf2as_latbuf_ch1"); + hist_ch1_fd = $fopen("latbuf_ch1.hist.dat", "w"); + for(int ii = 0; ii < `ASE_MAX_LATENCY; ii = ii + 1) begin + $fwrite(hist_ch1_fd, "%d\t%d\n", ii, ase_top.ccip_emulator.cf2as_latbuf_ch1.histogram_stats[ii]); + end + $fclose(hist_ch0_fd); + `END_YELLOW_FONTCOLOR; +`endif + // Finish command issue + // issue_finish_trig(); + + // Command to close logfd + $finish; + end + // endfunction + endtask + + + + /* *************************************************************************** + * Memory deallocation lock + * -------------------------------------------------------------------------- + * Problem: Due to reordering nature of ASE (guaranteed unordered + * transactions, DSMs can get unordered, resulting in applications + * deallocating memory + * + * Potential solution: + * - Count credits running in ASE, { (Tx0, RX0), (Tx1, Rx1), Umsg + * outstanding, CsrWrite, (Rx0MMIORd, C2tx) } + * - If total credit count is non-zero, a lock variable will be set, back + * pressuring any deallocate_buffer requests + * - Dellocate requests will be queued but not executed + * **************************************************************************/ + always @(posedge clk) begin + if (ase_reset) begin + rd_credit <= 0; + wr_credit <= 0; + mmiowr_credit <= 0; + mmiord_credit <= 0; + // atomic_credit <= 0; + end + else begin + // ---------------------------------------------------- // + // Read credit counter + rd_credit <= ase_tx0_rdvalid_cnt - ase_rx0_rdvalid_cnt; + // ---------------------------------------------------- // + // Write credit counter + wr_credit <= ase_tx1_wrvalid_cnt - ase_rx1_wrvalid_cnt; + // ---------------------------------------------------- // + // MMIO Writevalid counter + case ( {cwlp_wrvalid, C0RxMmioWrValid} ) + 2'b10 : mmiowr_credit <= mmiowr_credit + 1; + 2'b01 : mmiowr_credit <= mmiowr_credit - 1; + default : mmiowr_credit <= mmiowr_credit; + endcase // case ( {cwlp_wrvalid, C0RxMmioWrValid} ) + // ---------------------------------------------------- // + // MMIO readvalid counter + case ( {cwlp_rdvalid, mmioresp_valid} ) + 2'b10 : mmiord_credit <= mmiord_credit + 1; + 2'b01 : mmiord_credit <= mmiord_credit - 1; + default : mmiord_credit <= mmiord_credit; + endcase // case ( {cwlp_rdvalid, mmioresp_valid} ) + // ---------------------------------------------------- // + // Umsg valid counter +`ifdef ASE_ENABLE_UMSG_FEATURE + umsg_credit <= $countones(umsg_hint_enable_array) + $countones(umsg_data_enable_array) + umsgfifo_cnt; +`endif + // ---------------------------------------------------- // + // Atomics CmpXchg counter + // case ( { (C1TxValid && (C1TxHdr.reqtype==ASE_ATOMIC_REQ)), (C0RxRdValid && (C0RxHdr.resptype==ASE_ATOMIC_RSP)) } ) + // 2'b10 : atomic_credit <= atomic_credit + 1; + // 2'b01 : atomic_credit <= atomic_credit - 1; + // default : atomic_credit <= atomic_credit; + // endcase + // ---------------------------------------------------- // + end + end + + // Global dealloc flag enable + always @(posedge clk) begin + glbl_dealloc_credit <= wr_credit + rd_credit + mmiord_credit + mmiowr_credit + umsg_credit + mmioreq_count + rdrsp_fifo_cnt + wrrsp_fifo_cnt ; + end + + // Register for changes + always @(posedge clk) begin + glbl_dealloc_credit_q <= glbl_dealloc_credit; + end + + // Update process + always @(posedge clk) begin + if ((glbl_dealloc_credit_q == 0) && (glbl_dealloc_credit != 0)) begin + update_glbl_dealloc(0); + end + else if ((glbl_dealloc_credit_q != 0) && (glbl_dealloc_credit == 0)) begin + update_glbl_dealloc(1); + end + else if (glbl_dealloc_credit == 0) begin + update_glbl_dealloc(1); + end + else if ((glbl_dealloc_credit_q == 0) && (glbl_dealloc_credit == 0)) begin + update_glbl_dealloc(0); + end + end + + + +endmodule // cci_emulator diff --git a/ase/rtl/ccip_if_pkg.sv b/ase/rtl/ccip_if_pkg.sv new file mode 100644 index 000000000000..306fa101668d --- /dev/null +++ b/ase/rtl/ccip_if_pkg.sv @@ -0,0 +1,281 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +// Date: 02/2/2016 +// Compliant with CCI-P spec v0.7 +package ccip_if_pkg; +//===================================================================== +// CCI-P interface defines +//===================================================================== +parameter CCIP_VERSION_NUMBER = 12'h070; + +parameter CCIP_CLADDR_WIDTH = 42; +parameter CCIP_CLDATA_WIDTH = 512; + +parameter CCIP_MMIOADDR_WIDTH = 16; +parameter CCIP_MMIODATA_WIDTH = 64; +parameter CCIP_TID_WIDTH = 9; + +parameter CCIP_MDATA_WIDTH = 16; + + +// Number of requests that can be accepted after almost full is asserted. +parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8; + +parameter CCIP_MMIO_RD_TIMEOUT = 512; + +parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset + +// Base types +//---------------------------------------------------------------------- +typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr; +typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData; + + +typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr; +typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData; +typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid; + + +typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata; +typedef logic [1:0] t_ccip_clNum; +typedef logic [2:0] t_ccip_qwIdx; + + +// Request Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid + eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared +} t_ccip_c0_req; + +// Channel 1 +typedef enum logic [3:0] { + eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid + eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified + eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint + eREQ_WRFENCE = 4'h4, // Memory Write Fence +// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY ** + eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_req; + +// Response Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eRSP_RDLINE = 4'h0, // Memory Read + eRSP_UMSG = 4'h4 // UMsg received +// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr +} t_ccip_c0_rsp; + +// Channel 1 +typedef enum logic [3:0] { + eRSP_WRLINE = 4'h0, // Memory Write + eRSP_WRFENCE = 4'h4, // Memory Write Fence + eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_rsp; + +// +// Virtual Channel Select +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eVC_VA = 2'b00, + eVC_VL0 = 2'b01, + eVC_VH0 = 2'b10, + eVC_VH1 = 2'b11 +} t_ccip_vc; + +// Multi-CL Memory Request +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eCL_LEN_1 = 2'b00, + eCL_LEN_2 = 2'b01, + eCL_LEN_4 = 2'b11 +} t_ccip_clLen; + +// +// Structures for Request and Response headers +//---------------------------------------------------------------------- +typedef struct packed { + t_ccip_vc vc_sel; + logic [1:0] rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c0_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c0_ReqMemHdr; +parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; + t_ccip_vc vc_sel; + logic sop; + logic rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c1_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c1_ReqMemHdr; +parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; // reserved, drive 0 + t_ccip_vc vc_sel; + logic [3:0] rsvd1; // reserved, drive 0 + t_ccip_c1_req req_type; + logic [47:0] rsvd0; // reserved, drive 0 + t_ccip_mdata mdata; +}t_ccip_c1_ReqFenceHdr; + +typedef struct packed { + logic [11:0] rsvd1; // reserved, drive 0 + t_ccip_c1_req req_type; + logic [60:0] rsvd0; // reserved, drive 0 + logic [2:0] id; +}t_ccip_c1_ReqIntrHdr; + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic [1:0] rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c0_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c0_RspMemHdr; +parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr); + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic format; + logic rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspMemHdr; +parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr); + +typedef struct packed { + logic [7:0] rsvd0; // reserved, don't care + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspFenceHdr; + +typedef struct packed { + logic [7:0] rsvd1; // reserved, don't care + t_ccip_c1_rsp resp_type; + logic [12:0] rsvd0; // reserved, don't care + logic [2:0] id; +} t_ccip_c1_RspIntrHdr; + + +// Alternate Channel 0 MMIO request from host : +// MMIO requests arrive on the same channel as read responses, sharing +// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set +// the message is an MMIO request and should be processed by casting +// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr. +typedef struct packed { + t_ccip_mmioAddr address; // 4B aligned Mmio address + logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B + logic rsvd; // reserved, don't care + t_ccip_tid tid; +} t_ccip_c0_ReqMmioHdr; +parameter CCIP_C0RX_MMIOHDR_WIDTH = $bits(t_ccip_c0_ReqMmioHdr); + +typedef struct packed { + t_ccip_tid tid; // Returned back from ReqMmioHdr +} t_ccip_c2_RspMmioHdr; +parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr); + +//------------------------------------------------------------------------ +// CCI-P Input & Output bus structures +// +// Users are encouraged to use these for AFU development +//------------------------------------------------------------------------ +// Channel 0 : Memory Reads +typedef struct packed { + t_ccip_c0_ReqMemHdr hdr; // Request Header + logic valid; // Request Valid +} t_if_ccip_c0_Tx; + + +// Channel 1 : Memory Writes, Interrupts, CmpXchg +typedef struct packed { + t_ccip_c1_ReqMemHdr hdr; // Request Header + t_ccip_clData data; // Request Data + logic valid; // Request Wr Valid +} t_if_ccip_c1_Tx; + +// Channel 2 : MMIO Read response +typedef struct packed { + t_ccip_c2_RspMmioHdr hdr; // Response Header + logic mmioRdValid; // Response Read Valid + t_ccip_mmioData data; // Response Data +} t_if_ccip_c2_Tx; + +// Wrap all Tx channels +typedef struct packed { + t_if_ccip_c0_Tx c0; + t_if_ccip_c1_Tx c1; + t_if_ccip_c2_Tx c2; +} t_if_ccip_Tx; + + +// Channel 0: Memory Read response, MMIO Request +typedef struct packed { + t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header + t_ccip_clData data; // Rd Data / MMIO req Data + // Only one of valid, mmioRdValid and mmioWrValid may be set + // in a cycle. When either mmioRdValid or mmioWrValid are true + // the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr + // above. + logic rspValid; // Rd Response Valid + logic mmioRdValid; // MMIO Read Valid + logic mmioWrValid; // MMIO Write Valid +} t_if_ccip_c0_Rx; + +// Channel 1: Memory Writes +typedef struct packed { + t_ccip_c1_RspMemHdr hdr; // Response Header + logic rspValid; // Response Valid +} t_if_ccip_c1_Rx; + +// Wrap all channels +typedef struct packed { + logic c0TxAlmFull; // C0 Request Channel Almost Full + logic c1TxAlmFull; // C1 Request Channel Almost Full + + t_if_ccip_c0_Rx c0; + t_if_ccip_c1_Rx c1; +} t_if_ccip_Rx; + +endpackage diff --git a/ase/rtl/ccip_logger.sv b/ase/rtl/ccip_logger.sv new file mode 100644 index 000000000000..8fe0ad3da844 --- /dev/null +++ b/ase/rtl/ccip_logger.sv @@ -0,0 +1,493 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: CCI Transactions Logger + * Language : System{Verilog} + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + +import ase_pkg::*; +import ccip_if_pkg::*; + +`include "platform.vh" + +module ccip_logger + #( + parameter LOGNAME = "CHANGE_MY_NAME.log" + ) + ( + // Configure enable + input logic finish_logger, + input logic stdout_en, + // Buffer message injection + input logic log_timestamp_en, + input logic log_string_en, + ref string log_string, + ////////////////////////////////////////////////////////// + // CCI interface + input logic clk, + input logic SoftReset, + input t_if_ccip_Rx ccip_rx, + input t_if_ccip_Tx ccip_tx + ); + + + /* + * ASE Hardware Interface (CCI) logger + * - Logs CCI transaction into a transactions.tsv file + * - Watch for "*valid", and write transaction to log name + */ + // Log file descriptor + int log_fd; + + // Reset management + logic SoftReset_q; + + // AlmostFull management + logic C0TxAlmFull_q; + logic C1TxAlmFull_q; + + + // Registers for comparing previous states + always @(posedge clk) begin + SoftReset_q <= SoftReset; + C0TxAlmFull_q <= ccip_rx.c0TxAlmFull; + C1TxAlmFull_q <= ccip_rx.c1TxAlmFull; + end + + // Config header + t_ccip_c0_ReqMmioHdr C0RxMmioHdr; + assign C0RxMmioHdr = t_ccip_c0_ReqMmioHdr'(ccip_rx.c0.hdr); + + // Umsg header +`ifdef ASE_ENABLE_UMSG_FEATURE + UMsgHdr_t C0RxUMsgHdr; + assign C0RxUMsgHdr = UMsgHdr_t'(ccip_rx.c0.hdr); +`endif + + // Intr header (cast to ccip_if_pkg types) +`ifdef ASE_ENABLE_INTR_FEATURE + t_ccip_c1_ReqIntrHdr C1TxIntrReqHdr; + assign C1TxIntrReqHdr = t_ccip_c1_ReqIntrHdr'(ccip_tx.c1.hdr); + + t_ccip_c1_RspIntrHdr C1RxIntrRspHdr; + assign C1RxIntrRspHdr = t_ccip_c1_RspIntrHdr'(ccip_rx.c1.hdr); + +`endif + + + /* + * Buffer channels, request and response types + */ + // Print Channel function + function string print_channel (t_ccip_vc vc_sel); + begin + case (vc_sel) + eVC_VA : return "VA "; + eVC_VL0 : return "VL0"; + eVC_VH0 : return "VH0"; + eVC_VH1 : return "VH1"; + endcase + end + endfunction + + // Print Req Type - CH0 + function string print_c0_reqtype (t_ccip_c0_ReqMemHdr req); + begin + case (req) + eREQ_RDLINE_S : return "Rd_S "; + eREQ_RDLINE_I : return "Rd_I "; + default : return "** ERROR %m : eREQ-CH0 unindentified **" ; + endcase + end + endfunction + + // Print req type - CH1 + function string print_c1_reqtype (t_ccip_c1_ReqMemHdr req); + begin + case (req) + eREQ_WRLINE_I : return "Wr_I "; + eREQ_WRLINE_M : return "Wr_M "; + eREQ_WRPUSH_I : return "WrPush_I "; + eREQ_WRFENCE : return "WrFence "; + eREQ_INTR : return "IntrReq "; + default : return "** ERROR %m : eREQ-CH1 unindentified **" ; + endcase + end + endfunction + + // Print CH0 response type + function string print_c0_resptype (t_ccip_c0_rsp resp); + begin + case (resp) + eRSP_RDLINE : return "RdResp "; + default : return "** ERROR %m : eRSP-CH0 unindentified **" ; + endcase + end + endfunction + + // Print CH1 response type + function string print_c1_resptype (t_ccip_c1_rsp resp); + begin + case (resp) + eRSP_WRLINE : return "WrResp "; + eRSP_WRFENCE : return "WrFenceResp"; + eRSP_INTR : return "IntrResp "; + default : return "** ERROR %m : eRSP-CH1 unindentified **" ; + endcase + end + endfunction + + + // Print CL number (in Request) + function string print_cllen (t_ccip_clLen len); + begin + case (len) + eCL_LEN_1 : return "#1CL"; + eCL_LEN_2 : return "#2CL"; + eCL_LEN_4 : return "#4CL"; + default : return "** ERROR %m : clLen unindentified **" ; + endcase + end + endfunction + + + // Print CL number (in Response) + function string print_clnum (t_ccip_clNum num); + begin + case (num) + 2'b00 : return "#1CL"; + 2'b01 : return "#2CL"; + 2'b10 : return "#3CL"; + 2'b11 : return "#4CL"; + endcase + end + endfunction + + + // Print CSR data + function string csr_data(int num_bytes, logic [CCIP_DATA_WIDTH-1:0] rx0_data); + string str_4; + string str_8; + string str_64; + begin + case (num_bytes) + 4 : + begin + str_4.hextoa(rx0_data[31:0]); + return str_4; + end + 8 : + begin + str_8.hextoa(rx0_data[63:0]); + return str_8; + end + 64 : + begin + str_64.hextoa(rx0_data[511:0]); + return str_64; + end + endcase + end + endfunction + + + // MMIO Request length + function int mmioreq_length (logic [1:0] mmio_len); + begin + case (mmio_len) + 2'b00 : return 4; + 2'b01 : return 8; + 2'b10 : return 64; + endcase + end + endfunction // mmioreq_length + + + // Space generator - formatting help + function string ret_spaces (int num); + string spaces; + int ii; + begin + spaces = ""; + for (ii = 0; ii < num; ii = ii + 1) begin + spaces = {spaces, " "}; + end + return spaces; + end + endfunction + + + /* + * FUNCTION: print_and_post_log wrapper function to simplify logging + */ + function void print_and_post_log(string formatted_string); + begin + if (stdout_en) + $display(formatted_string); + $fwrite(log_fd, formatted_string); + $fflush(); + end + endfunction // print_and_post_log + + // Placeholder strings + string softreset_str; + string c0TxAlmFull_str; + string c1TxAlmFull_str; + string c0rx_str; + string c1rx_str; + string c0tx_str; + string c1tx_str; + string c2tx_str; + + + /* + * Watcher process + */ + initial begin : logger_proc + // Display + $display(" [SIM] Transaction Logger started"); + + // Open transactions.tsv file + log_fd = $fopen(LOGNAME, "w"); + + // Watch CCI port + forever begin + // -------------------------------------------------- // + // Indicate Software controlled reset + // -------------------------------------------------- // + if (SoftReset_q != SoftReset) begin + $sformat(softreset_str, + "%d\tSoftReset toggled from %b to %b\n", + $time, + SoftReset_q, + SoftReset); + print_and_post_log(softreset_str); + end + // -------------------------------------------------- // + // Track C0TxAlmFull transitions + // -------------------------------------------------- // + if (C0TxAlmFull_q != ccip_rx.c0TxAlmFull) begin + $sformat(c0TxAlmFull_str, + "%d\tC0Tx AlmFull toggled from %b to %b\n", + $time, + C0TxAlmFull_q, + ccip_rx.c0TxAlmFull); + print_and_post_log(c0TxAlmFull_str); + end + // -------------------------------------------------- // + // Track C1TxAlmFull transitions + // -------------------------------------------------- // + if (C1TxAlmFull_q != ccip_rx.c1TxAlmFull) begin + $sformat(c1TxAlmFull_str, + "%d\tC1Tx AlmFull toggled from %b to %b\n", + $time, + C1TxAlmFull_q, + ccip_rx.c1TxAlmFull); + print_and_post_log(c1TxAlmFull_str); + end + // -------------------------------------------------- // + // Buffer messages + // -------------------------------------------------- // + if (log_string_en) begin + if (log_timestamp_en) begin + $fwrite(log_fd, "-----------------------------------------------------\n"); + $fwrite(log_fd, "%d\t%s\n", $time, log_string); + end + else begin + $fwrite(log_fd, "-----------------------------------------------------\n"); + $fwrite(log_fd, "%s\n", log_string); + end + end + // -------------------------------------------------- // + // C0Rx Channel activity + // -------------------------------------------------- // + // MMIO Write Request + if (ccip_rx.c0.mmioWrValid) begin + $sformat(c0rx_str, + "%d\t \tMMIOWrReq \t \t%x\t%d bytes\t%s\n", + $time, + C0RxMmioHdr.address, + mmioreq_length(C0RxMmioHdr.length), + csr_data(mmioreq_length(C0RxMmioHdr.length), ccip_rx.c0.data) ); + print_and_post_log(c0rx_str); + end + // MMIO Read Request + else if (ccip_rx.c0.mmioRdValid) begin + $sformat(c0rx_str, + "%d\t \tMMIORdReq \t%x\t%x\t%d bytes\n", + $time, + C0RxMmioHdr.tid, + C0RxMmioHdr.address, + mmioreq_length(C0RxMmioHdr.length)); + print_and_post_log(c0rx_str); + end // if (ccip_rx.c0.mmioRdValid) + // Read Response + else if (ccip_rx.c0.rspValid && isCCIPRdLineResponse(ccip_rx.c0.hdr.resp_type)) begin + $sformat(c0rx_str, + "%d\t%s\t%s\t%x\t%s\t%x\n", + $time, + print_channel(ccip_rx.c0.hdr.vc_used), + print_c0_resptype(ccip_rx.c0.hdr.resp_type), + ccip_rx.c0.hdr.mdata, + print_clnum(ccip_rx.c0.hdr.cl_num), + ccip_rx.c0.data); + print_and_post_log(c0rx_str); + end // if (ccip_tx.c0.rspValid && (ccip_rx.c0.hdr.resptype == eRSP_RDLINE)) + /*************** SW -> MEM -> AFU Unordered Message *************/ +`ifdef ASE_ENABLE_UMSG_FEATURE + else if (ccip_rx.c0.rspValid && isCCIPUmsgResponse(ccip_rx.c0.hdr.resp_type)) begin + if (C0RxUMsgHdr.umsg_type) begin + $sformat(c0rx_str, + "%d\t \tUMsgHint \t%d\n", + $time, + C0RxUMsgHdr.umsg_id); + print_and_post_log(c0rx_str); + end + else if (~C0RxUMsgHdr.umsg_type) begin + $sformat(c0rx_str, + "%d\t \tUMsgData \t%d\t%x\n", + $time, + C0RxUMsgHdr.umsg_id, + ccip_rx.c0.data); + print_and_post_log(c0rx_str); + end + end +`endif + // -------------------------------------------------- // + // C1Rx Channel activity + // -------------------------------------------------- // + // Write response + if (ccip_rx.c1.rspValid && isCCIPWrLineResponse(ccip_rx.c1.hdr.resp_type)) begin + $sformat(c1rx_str, + "%d\t%s\t%s\t%x\t%s\n", + $time, + print_channel(ccip_rx.c1.hdr.vc_used), + print_c1_resptype(ccip_rx.c1.hdr.resp_type), + ccip_rx.c1.hdr.mdata, + print_clnum(ccip_rx.c1.hdr.cl_num)); + print_and_post_log(c1rx_str); + end + // Write Fence Response + else if (ccip_rx.c1.rspValid && isCCIPWrFenceResponse(ccip_rx.c1.hdr.resp_type)) begin + $sformat(c1rx_str, + "%d\t%s\tWrFenceRsp\t%x\n", + $time, + print_channel(ccip_rx.c1.hdr.vc_used), + ccip_rx.c1.hdr.mdata); + print_and_post_log(c1rx_str); + end +`ifdef ASE_ENABLE_INTR_FEATURE + else if (ccip_rx.c1.rspValid && isCCIPInterruptResponse(ccip_rx.c1.hdr.resp_type)) begin + $sformat(c1rx_str, + "%d\tInterrupt response on ID = %d\n", + $time, + C1RxIntrRspHdr.id); + print_and_post_log(c1rx_str); + end +`endif + // -------------------------------------------------- // + // C0Tx Channel activity + // -------------------------------------------------- // + // AFU -> MEM Read Request + if (ccip_tx.c0.valid && isCCIPRdLineRequest(ccip_tx.c0.hdr.req_type) ) begin + $sformat(c0tx_str, + "%d\t%s\t%s\t%x\t%x\t%s\n", + $time, + print_channel(ccip_tx.c0.hdr.vc_sel), + print_c0_reqtype(ccip_tx.c0.hdr.req_type), + ccip_tx.c0.hdr.mdata, + ccip_tx.c0.hdr.address, + print_cllen(ccip_tx.c0.hdr.cl_len)); + print_and_post_log(c0tx_str); + end + // -------------------------------------------------- // + // C1Tx Channel activity + // -------------------------------------------------- // + // Write Request + if (ccip_tx.c1.valid && isCCIPWrLineRequest(ccip_tx.c1.hdr.req_type)) begin + $sformat(c1tx_str, + "%d\t%s\t%s\t%x\t%x\t%x\t%s\n", + $time, + print_channel(ccip_tx.c1.hdr.vc_sel), + print_c1_reqtype(ccip_tx.c1.hdr.req_type), + ccip_tx.c1.hdr.mdata, + ccip_tx.c1.hdr.address, + ccip_tx.c1.data, + print_clnum(ccip_tx.c1.hdr.cl_len)); + print_and_post_log(c1tx_str); + end // if (ccip_tx.c1.valid && (ccip_tx.c1.hdr.req_type != eREQ_WRFENCE)) + // Write Fence + else if (ccip_tx.c1.valid && isCCIPWrFenceRequest(ccip_tx.c1.hdr.req_type)) begin + $sformat(c1tx_str, + "%d\t%s\tWrFence \t%x\n", + $time, + print_channel(ccip_tx.c1.hdr.vc_sel), + ccip_tx.c1.hdr.mdata); + print_and_post_log(c1tx_str); + end +`ifdef ASE_ENABLE_INTR_FEATURE + else if (ccip_tx.c1.valid && isCCIPInterruptRequest(ccip_tx.c1.hdr.req_type)) begin + $sformat(c1tx_str, + "%d\tInterrupt Requested with ID = %d\n", + $time, + C1TxIntrReqHdr.id + ); + print_and_post_log(c1tx_str); + end +`endif + // -------------------------------------------------- // + // C2Tx Channel activity + // -------------------------------------------------- // + if (ccip_tx.c2.mmioRdValid) begin + $sformat(c2tx_str, + "%d\t \tMMIORdRsp \t%x\t%x\n", + $time, + ccip_tx.c2.hdr.tid, + ccip_tx.c2.data); + print_and_post_log(c2tx_str); + end + // -------------------------------------------------- // + // FINISH command + // -------------------------------------------------- // + if (finish_logger == 1) begin + $fclose(log_fd); + end + // -------------------------------------------------- // + // Wait till next clock + // -------------------------------------------------- // + $fflush(log_fd); + @(posedge clk); + end + end + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_avalon_clock_source.sv b/ase/rtl/device_models/dcp_emif_model/altera_avalon_clock_source.sv new file mode 100644 index 000000000000..dc50130edd43 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_avalon_clock_source.sv @@ -0,0 +1,108 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $File: //acds/rel/17.0/ip/sopc/components/verification/altera_avalon_clock_source/altera_avalon_clock_source.sv $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ +// Clock generator + +`timescale 1ps / 1ps + +module altera_avalon_clock_source (clk); + output clk; + + parameter int unsigned CLOCK_RATE = 10; // clock rate in MHz / kHz / Hz depends on the clock unit + parameter CLOCK_UNIT = 1000000; // clock unit MHz / kHz / Hz + +// synthesis translate_off + import verbosity_pkg::*; + + localparam time HALF_CLOCK_PERIOD = 1000000000000.000000/(CLOCK_RATE*CLOCK_UNIT*2); // half clock period in ps + + logic clk = 1'b0; + + string message = "*uninitialized*"; + string freq_unit = (CLOCK_UNIT == 1)? "Hz" : + (CLOCK_UNIT == 1000)? "kHz" : "MHz"; + bit run_state = 1'b1; + + function automatic void __hello(); + $sformat(message, "%m: - Hello from altera_clock_source."); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Revision: #1 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Date: 2017/02/12 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - CLOCK_RATE = %0d %s", CLOCK_RATE, freq_unit); + print(VERBOSITY_INFO, message); + print_divider(VERBOSITY_INFO); + endfunction + + function automatic string get_version(); // public + // Return BFM version as a string of three integers separated by periods. + // For example, version 9.1 sp1 is encoded as "9.1.1". + string ret_version = "17.0"; + return ret_version; + endfunction + + task automatic clock_start(); // public + // Turn the clock on. By default the clock is initially turned on. + $sformat(message, "%m: Clock started"); + print(VERBOSITY_INFO, message); + run_state = 1; + endtask + + task automatic clock_stop(); // public + // Turn the clock off. + $sformat(message, "%m: Clock stopped"); + print(VERBOSITY_INFO, message); + run_state = 0; + endtask + + function automatic get_run_state(); // public + // Return the state of the clock source: running=1, stopped=0 + return run_state; + endfunction + + initial begin + __hello(); + end + + always begin + #HALF_CLOCK_PERIOD; + clk = run_state; + + #HALF_CLOCK_PERIOD; + clk = 1'b0; + end +// synthesis translate_on + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_avalon_mm_bridge.v b/ase/rtl/device_models/dcp_emif_model/altera_avalon_mm_bridge.v new file mode 100644 index 000000000000..ec1bc1ffbfff --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_avalon_mm_bridge.v @@ -0,0 +1,315 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/rel/17.0/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ +// -------------------------------------- +// Avalon-MM pipeline bridge +// +// Optionally registers Avalon-MM command and response signals +// -------------------------------------- + +`timescale 1 ns / 1 ns +module altera_avalon_mm_bridge +#( + parameter DATA_WIDTH = 32, + parameter SYMBOL_WIDTH = 8, + parameter RESPONSE_WIDTH = 2, + parameter HDL_ADDR_WIDTH = 10, + parameter BURSTCOUNT_WIDTH = 1, + + parameter PIPELINE_COMMAND = 1, + parameter PIPELINE_RESPONSE = 1, + + // -------------------------------------- + // Derived parameters + // -------------------------------------- + parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH +) +( + input clk, + input reset, + + output s0_waitrequest, + output [DATA_WIDTH-1:0] s0_readdata, + output s0_readdatavalid, + output [RESPONSE_WIDTH-1:0] s0_response, + input [BURSTCOUNT_WIDTH-1:0] s0_burstcount, + input [DATA_WIDTH-1:0] s0_writedata, + input [HDL_ADDR_WIDTH-1:0] s0_address, + input s0_write, + input s0_read, + input [BYTEEN_WIDTH-1:0] s0_byteenable, + input s0_debugaccess, + + input m0_waitrequest, + input [DATA_WIDTH-1:0] m0_readdata, + input m0_readdatavalid, + input [RESPONSE_WIDTH-1:0] m0_response, + output [BURSTCOUNT_WIDTH-1:0] m0_burstcount, + output [DATA_WIDTH-1:0] m0_writedata, + output [HDL_ADDR_WIDTH-1:0] m0_address, + output m0_write, + output m0_read, + output [BYTEEN_WIDTH-1:0] m0_byteenable, + output m0_debugaccess +); + // -------------------------------------- + // Registers & signals + // -------------------------------------- + reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount; + reg [DATA_WIDTH-1:0] cmd_writedata; + reg [HDL_ADDR_WIDTH-1:0] cmd_address; + reg cmd_write; + reg cmd_read; + reg [BYTEEN_WIDTH-1:0] cmd_byteenable; + wire cmd_waitrequest; + reg cmd_debugaccess; + + reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount; + reg [DATA_WIDTH-1:0] wr_writedata; + reg [HDL_ADDR_WIDTH-1:0] wr_address; + reg wr_write; + reg wr_read; + reg [BYTEEN_WIDTH-1:0] wr_byteenable; + reg wr_debugaccess; + + reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount; + reg [DATA_WIDTH-1:0] wr_reg_writedata; + reg [HDL_ADDR_WIDTH-1:0] wr_reg_address; + reg wr_reg_write; + reg wr_reg_read; + reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable; + reg wr_reg_waitrequest; + reg wr_reg_debugaccess; + + reg use_reg; + wire wait_rise; + + reg [DATA_WIDTH-1:0] rsp_readdata; + reg rsp_readdatavalid; + reg [RESPONSE_WIDTH-1:0] rsp_response; + + // -------------------------------------- + // Command pipeline + // + // Registers all command signals, including waitrequest + // -------------------------------------- + generate if (PIPELINE_COMMAND == 1) begin + + // -------------------------------------- + // Waitrequest Pipeline Stage + // + // Output waitrequest is delayed by one cycle, which means + // that a master will see waitrequest assertions one cycle + // too late. + // + // Solution: buffer the command when waitrequest transitions + // from low->high. As an optimization, we can safely assume + // waitrequest is low by default because downstream logic + // in the bridge ensures this. + // + // Note: this implementation buffers idle cycles should + // waitrequest transition on such cycles. This is a potential + // cause for throughput loss, but ye olde pipeline bridge did + // the same for years and no one complained. Not buffering idle + // cycles costs logic on the waitrequest path. + // -------------------------------------- + assign s0_waitrequest = wr_reg_waitrequest; + assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest; + + always @(posedge clk, posedge reset) begin + if (reset) begin + wr_reg_waitrequest <= 1'b1; + // -------------------------------------- + // Bit of trickiness here, deserving of a long comment. + // + // On the first cycle after reset, the pass-through + // must not be used or downstream logic may sample + // the same command twice because of the delay in + // transmitting a falling waitrequest. + // + // Using the registered command works on the condition + // that downstream logic deasserts waitrequest + // immediately after reset, which is true of the + // next stage in this bridge. + // -------------------------------------- + use_reg <= 1'b1; + + wr_reg_burstcount <= 1'b1; + wr_reg_writedata <= 0; + wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}}; + wr_reg_address <= 0; + wr_reg_write <= 1'b0; + wr_reg_read <= 1'b0; + wr_reg_debugaccess <= 1'b0; + end else begin + wr_reg_waitrequest <= cmd_waitrequest; + + if (wait_rise) begin + wr_reg_writedata <= s0_writedata; + wr_reg_byteenable <= s0_byteenable; + wr_reg_address <= s0_address; + wr_reg_write <= s0_write; + wr_reg_read <= s0_read; + wr_reg_burstcount <= s0_burstcount; + wr_reg_debugaccess <= s0_debugaccess; + end + + // stop using the buffer when waitrequest is low + if (~cmd_waitrequest) + use_reg <= 1'b0; + else if (wait_rise) begin + use_reg <= 1'b1; + end + + end + end + + always @* begin + wr_burstcount = s0_burstcount; + wr_writedata = s0_writedata; + wr_address = s0_address; + wr_write = s0_write; + wr_read = s0_read; + wr_byteenable = s0_byteenable; + wr_debugaccess = s0_debugaccess; + + if (use_reg) begin + wr_burstcount = wr_reg_burstcount; + wr_writedata = wr_reg_writedata; + wr_address = wr_reg_address; + wr_write = wr_reg_write; + wr_read = wr_reg_read; + wr_byteenable = wr_reg_byteenable; + wr_debugaccess = wr_reg_debugaccess; + end + end + + // -------------------------------------- + // Master-Slave Signal Pipeline Stage + // + // One notable detail is that cmd_waitrequest is deasserted + // when this stage is idle. This allows us to make logic + // optimizations in the waitrequest pipeline stage. + // + // Also note that cmd_waitrequest is deasserted during reset, + // which is not spec-compliant, but is ok for an internal + // signal. + // -------------------------------------- + wire no_command; + assign no_command = ~(cmd_read || cmd_write); + assign cmd_waitrequest = m0_waitrequest & ~no_command; + + always @(posedge clk, posedge reset) begin + if (reset) begin + cmd_burstcount <= 1'b1; + cmd_writedata <= 0; + cmd_byteenable <= {BYTEEN_WIDTH{1'b1}}; + cmd_address <= 0; + cmd_write <= 1'b0; + cmd_read <= 1'b0; + cmd_debugaccess <= 1'b0; + end + else begin + if (~cmd_waitrequest) begin + cmd_writedata <= wr_writedata; + cmd_byteenable <= wr_byteenable; + cmd_address <= wr_address; + cmd_write <= wr_write; + cmd_read <= wr_read; + cmd_burstcount <= wr_burstcount; + cmd_debugaccess <= wr_debugaccess; + end + end + end + + end // conditional command pipeline + else begin + + assign s0_waitrequest = m0_waitrequest; + + always @* begin + cmd_burstcount = s0_burstcount; + cmd_writedata = s0_writedata; + cmd_address = s0_address; + cmd_write = s0_write; + cmd_read = s0_read; + cmd_byteenable = s0_byteenable; + cmd_debugaccess = s0_debugaccess; + end + + end + endgenerate + + assign m0_burstcount = cmd_burstcount; + assign m0_writedata = cmd_writedata; + assign m0_address = cmd_address; + assign m0_write = cmd_write; + assign m0_read = cmd_read; + assign m0_byteenable = cmd_byteenable; + assign m0_debugaccess = cmd_debugaccess; + + // -------------------------------------- + // Response pipeline + // + // Registers all response signals + // -------------------------------------- + generate if (PIPELINE_RESPONSE == 1) begin + + always @(posedge clk, posedge reset) begin + if (reset) begin + rsp_readdatavalid <= 1'b0; + rsp_readdata <= 0; + rsp_response <= 0; + end + else begin + rsp_readdatavalid <= m0_readdatavalid; + rsp_readdata <= m0_readdata; + rsp_response <= m0_response; + end + end + + end // conditional response pipeline + else begin + + always @* begin + rsp_readdatavalid = m0_readdatavalid; + rsp_readdata = m0_readdata; + rsp_response = m0_response; + end + end + endgenerate + + assign s0_readdatavalid = rsp_readdatavalid; + assign s0_readdata = rsp_readdata; + assign s0_response = rsp_response; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_avalon_reset_source.sv b/ase/rtl/device_models/dcp_emif_model/altera_avalon_reset_source.sv new file mode 100644 index 000000000000..f5f2aa15195c --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_avalon_reset_source.sv @@ -0,0 +1,117 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $File: //acds/rel/17.0/ip/sopc/components/verification/altera_avalon_reset_source/altera_avalon_reset_source.sv $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ +// Reset generator + +`timescale 1ps / 1ps + +module altera_avalon_reset_source ( + clk, + reset + ); + input clk; + output reset; + + parameter ASSERT_HIGH_RESET = 1; // reset assertion level is high by default + parameter INITIAL_RESET_CYCLES = 0; // deassert after number of clk cycles + +// synthesis translate_off + import verbosity_pkg::*; + + logic reset = ASSERT_HIGH_RESET ? 1'b0 : 1'b1; + + string message = "*uninitialized*"; + + int clk_ctr = 0; + + always @(posedge clk) begin + clk_ctr <= clk_ctr + 1; + end + + always @(*) + if (clk_ctr == INITIAL_RESET_CYCLES) + reset_deassert(); + + + function automatic void __hello(); + $sformat(message, "%m: - Hello from altera_reset_source"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Revision: #1 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - $Date: 2017/02/12 $"); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - ASSERT_HIGH_RESET = %0d", ASSERT_HIGH_RESET); + print(VERBOSITY_INFO, message); + $sformat(message, "%m: - INITIAL_RESET_CYCLES = %0d", INITIAL_RESET_CYCLES); + print(VERBOSITY_INFO, message); + print_divider(VERBOSITY_INFO); + endfunction + + function automatic string get_version(); // public + // Return BFM version as a string of three integers separated by periods. + // For example, version 9.1 sp1 is encoded as "9.1.1". + string ret_version = "17.0"; + return ret_version; + endfunction + + task automatic reset_assert(); // public + $sformat(message, "%m: Reset asserted"); + print(VERBOSITY_INFO, message); + + if (ASSERT_HIGH_RESET > 0) begin + reset = 1'b1; + end else begin + reset = 1'b0; + end + endtask + + task automatic reset_deassert(); // public + $sformat(message, "%m: Reset deasserted"); + print(VERBOSITY_INFO, message); + + if (ASSERT_HIGH_RESET > 0) begin + reset = 1'b0; + end else begin + reset = 1'b1; + end + endtask + + initial begin + __hello(); + if (INITIAL_RESET_CYCLES > 0) + reset_assert(); + end +// synthesis translate_on + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_abphy_mux.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_abphy_mux.sv new file mode 100644 index 000000000000..79746e52cba1 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_abphy_mux.sv @@ -0,0 +1,446 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// abstract phy mux +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_abphy_mux #( + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter PINS_PER_LANE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter LANES_IN_RTL_TILES = 1 +) ( + output logic phy_reset_n, // Async reset signal from reset circuitry in the tile + output logic phy_fb_clk_to_pll, // PHY feedback clock (to PLL) + output logic [1:0] core_clks_from_cpa_pri, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri, // Core clock locked signals from the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + output logic ctl2core_avl_cmd_ready_0, + output logic ctl2core_avl_cmd_ready_1, + output logic [12:0] ctl2core_avl_rdata_id_0, + output logic [12:0] ctl2core_avl_rdata_id_1, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat, + output logic [25:0] t2c_afi, + output logic [13:0] ctl2core_sideband_0, + output logic [13:0] ctl2core_sideband_1, + output logic [33:0] ctl2core_mmr_0, + output logic [33:0] ctl2core_mmr_1, + output logic [PINS_IN_RTL_TILES-1:0] l2b_data, // lane-to-buffer data + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe, // lane-to-buffer output-enable + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc, // lane-to-buffer dynamic-termination-control + output logic pa_dprio_block_select, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + + output logic global_reset_n_int_iotile_in, + output logic pll_locked_iotile_in, + output logic pll_dll_clk_iotile_in, + output logic [7:0] phy_clk_phs_iotile_in, + output logic [1:0] phy_clk_iotile_in, + output logic phy_fb_clk_to_tile_iotile_in, + output logic [1:0] core_clks_fb_to_cpa_pri_iotile_in, + output logic [1:0] core_clks_fb_to_cpa_sec_iotile_in, + output logic [59:0] core2ctl_avl_0_iotile_in, + output logic [59:0] core2ctl_avl_1_iotile_in, + output logic core2ctl_avl_rd_data_ready_0_iotile_in, + output logic core2ctl_avl_rd_data_ready_1_iotile_in, + output logic core2l_wr_data_vld_ast_0_iotile_in, + output logic core2l_wr_data_vld_ast_1_iotile_in, + output logic core2l_rd_data_rdy_ast_0_iotile_in, + output logic core2l_rd_data_rdy_ast_1_iotile_in, + output logic [12:0] core2l_wr_ecc_info_0_iotile_in, + output logic [12:0] core2l_wr_ecc_info_1_iotile_in, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data_iotile_in, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe_iotile_in, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full_iotile_in, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read_iotile_in, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write_iotile_in, + output logic [16:0] c2t_afi_iotile_in, + output logic [41:0] core2ctl_sideband_0_iotile_in, + output logic [41:0] core2ctl_sideband_1_iotile_in, + output logic [50:0] core2ctl_mmr_0_iotile_in, + output logic [50:0] core2ctl_mmr_1_iotile_in, + output logic [PINS_IN_RTL_TILES-1:0] b2l_data_iotile_in, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqs_iotile_in, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb_iotile_in, + output logic cal_bus_clk_iotile_in, + output logic cal_bus_avl_read_iotile_in, + output logic cal_bus_avl_write_iotile_in, + output logic [19:0] cal_bus_avl_address_iotile_in, + output logic [31:0] cal_bus_avl_write_data_iotile_in, + output logic pa_dprio_clk_iotile_in, + output logic pa_dprio_read_iotile_in, + output logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr_iotile_in, + output logic pa_dprio_rst_n_iotile_in, + output logic pa_dprio_write_iotile_in, + output logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata_iotile_in, + + input logic phy_reset_n_abphy, + input logic phy_fb_clk_to_pll_abphy, + input logic [1:0] core_clks_from_cpa_pri_abphy, // Core clock signals from the CPA of primary interface + input logic [1:0] core_clks_locked_cpa_pri_abphy, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_from_cpa_sec_abphy, // Core clock signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_locked_cpa_sec_abphy, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic ctl2core_avl_cmd_ready_0_abphy, + input logic ctl2core_avl_cmd_ready_1_abphy, + input logic [12:0] ctl2core_avl_rdata_id_0_abphy, + input logic [12:0] ctl2core_avl_rdata_id_1_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_abphy, + input logic [25:0] t2c_afi_abphy, + input logic [13:0] ctl2core_sideband_0_abphy, + input logic [13:0] ctl2core_sideband_1_abphy, + input logic [33:0] ctl2core_mmr_0_abphy, + input logic [33:0] ctl2core_mmr_1_abphy, + input logic [PINS_IN_RTL_TILES-1:0] l2b_data_abphy, + input logic [PINS_IN_RTL_TILES-1:0] l2b_oe_abphy, + input logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_abphy, + input logic pa_dprio_block_select_abphy, + input logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_abphy, + + input logic phy_reset_n_nonabphy, // Async reset signal from reset circuitry in the tile + input logic phy_fb_clk_to_pll_nonabphy, // PHY feedback clock (to PLL) + input logic [1:0] core_clks_from_cpa_pri_nonabphy, // Core clock signals from the CPA of primary interface + input logic [1:0] core_clks_locked_cpa_pri_nonabphy, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_from_cpa_sec_nonabphy, // Core clock signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_locked_cpa_sec_nonabphy, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic ctl2core_avl_cmd_ready_0_nonabphy, + input logic ctl2core_avl_cmd_ready_1_nonabphy, + input logic [12:0] ctl2core_avl_rdata_id_0_nonabphy, + input logic [12:0] ctl2core_avl_rdata_id_1_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_nonabphy, + input logic [25:0] t2c_afi_nonabphy, + input logic [13:0] ctl2core_sideband_0_nonabphy, + input logic [13:0] ctl2core_sideband_1_nonabphy, + input logic [33:0] ctl2core_mmr_0_nonabphy, + input logic [33:0] ctl2core_mmr_1_nonabphy, + input logic [PINS_IN_RTL_TILES-1:0] l2b_data_nonabphy, // lane-to-buffer data + input logic [PINS_IN_RTL_TILES-1:0] l2b_oe_nonabphy, // lane-to-buffer output-enable + input logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_nonabphy, // lane-to-buffer dynamic-termination-control + input logic pa_dprio_block_select_nonabphy, + input logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_nonabphy, + + input logic global_reset_n_int, + input logic pll_locked, + input logic pll_dll_clk, + input logic [7:0] phy_clk_phs, + input logic [1:0] phy_clk, + input logic phy_fb_clk_to_tile, + input logic [1:0] core_clks_fb_to_cpa_pri, + input logic [1:0] core_clks_fb_to_cpa_sec, + input logic [59:0] core2ctl_avl_0, + input logic [59:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + input logic core2l_wr_data_vld_ast_0, + input logic core2l_wr_data_vld_ast_1, + input logic core2l_rd_data_rdy_ast_0, + input logic core2l_rd_data_rdy_ast_1, + input logic [12:0] core2l_wr_ecc_info_0, + input logic [12:0] core2l_wr_ecc_info_1, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write, + input [16:0] c2t_afi, + input logic [41:0] core2ctl_sideband_0, + input logic [41:0] core2ctl_sideband_1, + input logic [50:0] core2ctl_mmr_0, + input logic [50:0] core2ctl_mmr_1, + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, + input logic cal_bus_clk, + input logic cal_bus_avl_read, + input logic cal_bus_avl_write, + input logic [19:0] cal_bus_avl_address, + input logic [31:0] cal_bus_avl_write_data, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + + input logic runAbstractPhySim +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (DIAG_USE_ABSTRACT_PHY == 0) + begin : nonabphy_connections + + assign phy_reset_n = phy_reset_n_nonabphy; + assign ctl2core_avl_rdata_id_1 = ctl2core_avl_rdata_id_1_nonabphy; + assign ctl2core_avl_rdata_id_0 = ctl2core_avl_rdata_id_0_nonabphy; + assign ctl2core_mmr_0 = ctl2core_mmr_0_nonabphy; + assign l2core_afi_wlat = l2core_afi_wlat_nonabphy; + assign l2core_data = l2core_data_nonabphy; + assign l2b_dtc = l2b_dtc_nonabphy; + assign ctl2core_mmr_1 = ctl2core_mmr_1_nonabphy; + assign l2b_data = l2b_data_nonabphy; + assign l2core_rd_data_vld_avl0 = l2core_rd_data_vld_avl0_nonabphy; + assign ctl2core_avl_cmd_ready_0 = ctl2core_avl_cmd_ready_0_nonabphy; + assign phy_fb_clk_to_pll = phy_fb_clk_to_pll_nonabphy; + assign l2b_oe = l2b_oe_nonabphy; + assign ctl2core_sideband_0 = ctl2core_sideband_0_nonabphy; + assign l2core_wb_pointer_for_ecc = l2core_wb_pointer_for_ecc_nonabphy; + assign t2c_afi = t2c_afi_nonabphy; + assign pa_dprio_block_select = pa_dprio_block_select_nonabphy; + assign ctl2core_sideband_1 = ctl2core_sideband_1_nonabphy; + assign core_clks_locked_cpa_pri = core_clks_locked_cpa_pri_nonabphy; + assign core_clks_locked_cpa_sec = core_clks_locked_cpa_sec_nonabphy; + assign core_clks_from_cpa_pri = core_clks_from_cpa_pri_nonabphy; + assign core_clks_from_cpa_sec = core_clks_from_cpa_sec_nonabphy; + assign l2core_rdata_valid = l2core_rdata_valid_nonabphy; + assign ctl2core_avl_cmd_ready_1 = ctl2core_avl_cmd_ready_1_nonabphy; + assign l2core_afi_rlat = l2core_afi_rlat_nonabphy; + assign l2core_wr_data_rdy_ast = l2core_wr_data_rdy_ast_nonabphy; + assign pa_dprio_readdata = pa_dprio_readdata_nonabphy; + + assign global_reset_n_int_iotile_in = global_reset_n_int; + assign pll_locked_iotile_in = pll_locked; + assign pll_dll_clk_iotile_in = pll_dll_clk; + assign phy_clk_phs_iotile_in = phy_clk_phs; + assign phy_clk_iotile_in = phy_clk; + assign phy_fb_clk_to_tile_iotile_in = phy_fb_clk_to_tile; + assign core_clks_fb_to_cpa_pri_iotile_in = core_clks_fb_to_cpa_pri; + assign core_clks_fb_to_cpa_sec_iotile_in = core_clks_fb_to_cpa_sec; + assign core2ctl_avl_0_iotile_in = core2ctl_avl_0; + assign core2ctl_avl_1_iotile_in = core2ctl_avl_1; + assign core2ctl_avl_rd_data_ready_0_iotile_in = core2ctl_avl_rd_data_ready_0; + assign core2ctl_avl_rd_data_ready_1_iotile_in = core2ctl_avl_rd_data_ready_1; + assign core2l_wr_data_vld_ast_0_iotile_in = core2l_wr_data_vld_ast_0; + assign core2l_wr_data_vld_ast_1_iotile_in = core2l_wr_data_vld_ast_1; + assign core2l_rd_data_rdy_ast_0_iotile_in = core2l_rd_data_rdy_ast_0; + assign core2l_rd_data_rdy_ast_1_iotile_in = core2l_rd_data_rdy_ast_1; + assign core2l_wr_ecc_info_0_iotile_in = core2l_wr_ecc_info_0; + assign core2l_wr_ecc_info_1_iotile_in = core2l_wr_ecc_info_1; + assign core2l_data_iotile_in = core2l_data; + assign core2l_oe_iotile_in = core2l_oe; + assign core2l_rdata_en_full_iotile_in = core2l_rdata_en_full; + assign core2l_mrnk_read_iotile_in = core2l_mrnk_read; + assign core2l_mrnk_write_iotile_in = core2l_mrnk_write; + assign c2t_afi_iotile_in = c2t_afi; + assign core2ctl_sideband_0_iotile_in = core2ctl_sideband_0; + assign core2ctl_sideband_1_iotile_in = core2ctl_sideband_1; + assign core2ctl_mmr_0_iotile_in = core2ctl_mmr_0; + assign core2ctl_mmr_1_iotile_in = core2ctl_mmr_1; + assign b2l_data_iotile_in = b2l_data; + assign b2t_dqs_iotile_in = b2t_dqs; + assign b2t_dqsb_iotile_in = b2t_dqsb; + assign cal_bus_clk_iotile_in = cal_bus_clk; + assign cal_bus_avl_read_iotile_in = cal_bus_avl_read; + assign cal_bus_avl_write_iotile_in = cal_bus_avl_write; + assign cal_bus_avl_address_iotile_in = cal_bus_avl_address; + assign cal_bus_avl_write_data_iotile_in = cal_bus_avl_write_data; + assign pa_dprio_clk_iotile_in = pa_dprio_clk; + assign pa_dprio_read_iotile_in = pa_dprio_read; + assign pa_dprio_reg_addr_iotile_in = pa_dprio_reg_addr; + assign pa_dprio_rst_n_iotile_in = pa_dprio_rst_n; + assign pa_dprio_write_iotile_in = pa_dprio_write; + assign pa_dprio_writedata_iotile_in = pa_dprio_writedata; + + end + else begin : abphy_connections + always @ ( * ) begin + if ( runAbstractPhySim==0 ) begin + phy_reset_n = phy_reset_n_nonabphy; + ctl2core_avl_rdata_id_1 = ctl2core_avl_rdata_id_1_nonabphy; + ctl2core_avl_rdata_id_0 = ctl2core_avl_rdata_id_0_nonabphy; + ctl2core_mmr_0 = ctl2core_mmr_0_nonabphy; + l2core_afi_wlat = l2core_afi_wlat_nonabphy; + l2core_data = l2core_data_nonabphy; + l2b_dtc = l2b_dtc_nonabphy; + ctl2core_mmr_1 = ctl2core_mmr_1_nonabphy; + l2b_data = l2b_data_nonabphy; + l2core_rd_data_vld_avl0 = l2core_rd_data_vld_avl0_nonabphy; + ctl2core_avl_cmd_ready_0 = ctl2core_avl_cmd_ready_0_nonabphy; + phy_fb_clk_to_pll = phy_fb_clk_to_pll_nonabphy; + l2b_oe = l2b_oe_nonabphy; + ctl2core_sideband_0 = ctl2core_sideband_0_nonabphy; + l2core_wb_pointer_for_ecc = l2core_wb_pointer_for_ecc_nonabphy; + t2c_afi = t2c_afi_nonabphy; + pa_dprio_block_select = pa_dprio_block_select_nonabphy; + ctl2core_sideband_1 = ctl2core_sideband_1_nonabphy; + core_clks_locked_cpa_pri = core_clks_locked_cpa_pri_nonabphy; + core_clks_locked_cpa_sec = core_clks_locked_cpa_sec_nonabphy; + core_clks_from_cpa_pri = core_clks_from_cpa_pri_nonabphy; + core_clks_from_cpa_sec = core_clks_from_cpa_sec_nonabphy; + l2core_rdata_valid = l2core_rdata_valid_nonabphy; + ctl2core_avl_cmd_ready_1 = ctl2core_avl_cmd_ready_1_nonabphy; + l2core_afi_rlat = l2core_afi_rlat_nonabphy; + l2core_wr_data_rdy_ast = l2core_wr_data_rdy_ast_nonabphy; + pa_dprio_readdata = pa_dprio_readdata_nonabphy; + + global_reset_n_int_iotile_in = global_reset_n_int; + pll_locked_iotile_in = pll_locked; + pll_dll_clk_iotile_in = pll_dll_clk; + phy_clk_phs_iotile_in = phy_clk_phs; + phy_clk_iotile_in = phy_clk; + phy_fb_clk_to_tile_iotile_in = phy_fb_clk_to_tile; + core_clks_fb_to_cpa_pri_iotile_in = core_clks_fb_to_cpa_pri; + core_clks_fb_to_cpa_sec_iotile_in = core_clks_fb_to_cpa_sec; + core2ctl_avl_0_iotile_in = core2ctl_avl_0; + core2ctl_avl_1_iotile_in = core2ctl_avl_1; + core2ctl_avl_rd_data_ready_0_iotile_in = core2ctl_avl_rd_data_ready_0; + core2ctl_avl_rd_data_ready_1_iotile_in = core2ctl_avl_rd_data_ready_1; + core2l_wr_data_vld_ast_0_iotile_in = core2l_wr_data_vld_ast_0; + core2l_wr_data_vld_ast_1_iotile_in = core2l_wr_data_vld_ast_1; + core2l_rd_data_rdy_ast_0_iotile_in = core2l_rd_data_rdy_ast_0; + core2l_rd_data_rdy_ast_1_iotile_in = core2l_rd_data_rdy_ast_1; + core2l_wr_ecc_info_0_iotile_in = core2l_wr_ecc_info_0; + core2l_wr_ecc_info_1_iotile_in = core2l_wr_ecc_info_1; + core2l_data_iotile_in = core2l_data; + core2l_oe_iotile_in = core2l_oe; + core2l_rdata_en_full_iotile_in = core2l_rdata_en_full; + core2l_mrnk_read_iotile_in = core2l_mrnk_read; + core2l_mrnk_write_iotile_in = core2l_mrnk_write; + c2t_afi_iotile_in = c2t_afi; + core2ctl_sideband_0_iotile_in = core2ctl_sideband_0; + core2ctl_sideband_1_iotile_in = core2ctl_sideband_1; + core2ctl_mmr_0_iotile_in = core2ctl_mmr_0; + core2ctl_mmr_1_iotile_in = core2ctl_mmr_1; + b2l_data_iotile_in = b2l_data; + b2t_dqs_iotile_in = b2t_dqs; + b2t_dqsb_iotile_in = b2t_dqsb; + cal_bus_clk_iotile_in = cal_bus_clk; + cal_bus_avl_read_iotile_in = cal_bus_avl_read; + cal_bus_avl_write_iotile_in = cal_bus_avl_write; + cal_bus_avl_address_iotile_in = cal_bus_avl_address; + cal_bus_avl_write_data_iotile_in = cal_bus_avl_write_data; + pa_dprio_clk_iotile_in = pa_dprio_clk; + pa_dprio_read_iotile_in = pa_dprio_read; + pa_dprio_reg_addr_iotile_in = pa_dprio_reg_addr; + pa_dprio_rst_n_iotile_in = pa_dprio_rst_n; + pa_dprio_write_iotile_in = pa_dprio_write; + pa_dprio_writedata_iotile_in = pa_dprio_writedata; + end + else begin + phy_reset_n = phy_reset_n_abphy; + ctl2core_avl_rdata_id_1 = ctl2core_avl_rdata_id_1_abphy; + ctl2core_avl_rdata_id_0 = ctl2core_avl_rdata_id_0_abphy; + ctl2core_mmr_0 = ctl2core_mmr_0_abphy; + l2core_afi_wlat = l2core_afi_wlat_abphy; + l2core_data = l2core_data_abphy; + l2b_dtc = l2b_dtc_abphy; + ctl2core_mmr_1 = ctl2core_mmr_1_abphy; + l2b_data = l2b_data_abphy; + l2core_rd_data_vld_avl0 = l2core_rd_data_vld_avl0_abphy; + ctl2core_avl_cmd_ready_0 = ctl2core_avl_cmd_ready_0_abphy; + phy_fb_clk_to_pll = phy_fb_clk_to_pll_abphy; + l2b_oe = l2b_oe_abphy; + ctl2core_sideband_0 = ctl2core_sideband_0_abphy; + l2core_wb_pointer_for_ecc = l2core_wb_pointer_for_ecc_abphy; + t2c_afi = t2c_afi_abphy; + pa_dprio_block_select = pa_dprio_block_select_abphy; + ctl2core_sideband_1 = ctl2core_sideband_1_abphy; + core_clks_locked_cpa_pri = core_clks_locked_cpa_pri_abphy; + core_clks_locked_cpa_sec = core_clks_locked_cpa_sec_abphy; + core_clks_from_cpa_pri = core_clks_from_cpa_pri_abphy; + core_clks_from_cpa_sec = core_clks_from_cpa_sec_abphy; + l2core_rdata_valid = l2core_rdata_valid_abphy; + ctl2core_avl_cmd_ready_1 = ctl2core_avl_cmd_ready_1_abphy; + l2core_afi_rlat = l2core_afi_rlat_abphy; + l2core_wr_data_rdy_ast = l2core_wr_data_rdy_ast_abphy; + pa_dprio_readdata = pa_dprio_readdata_abphy; + + global_reset_n_int_iotile_in = 'd0; + pll_locked_iotile_in = 'd0; + pll_dll_clk_iotile_in = 'd0; + phy_clk_phs_iotile_in = 'd0; + phy_clk_iotile_in = 'd0; + phy_fb_clk_to_tile_iotile_in = 'd0; + core_clks_fb_to_cpa_pri_iotile_in = 'd0; + core_clks_fb_to_cpa_sec_iotile_in = 'd0; + core2ctl_avl_0_iotile_in = 'd0; + core2ctl_avl_1_iotile_in = 'd0; + core2ctl_avl_rd_data_ready_0_iotile_in = 'd0; + core2ctl_avl_rd_data_ready_1_iotile_in = 'd0; + core2l_wr_data_vld_ast_0_iotile_in = 'd0; + core2l_wr_data_vld_ast_1_iotile_in = 'd0; + core2l_rd_data_rdy_ast_0_iotile_in = 'd0; + core2l_rd_data_rdy_ast_1_iotile_in = 'd0; + core2l_wr_ecc_info_0_iotile_in = 'd0; + core2l_wr_ecc_info_1_iotile_in = 'd0; + core2l_data_iotile_in = 'd0; + core2l_oe_iotile_in = 'd0; + core2l_rdata_en_full_iotile_in = 'd0; + core2l_mrnk_read_iotile_in = 'd0; + core2l_mrnk_write_iotile_in = 'd0; + c2t_afi_iotile_in = 'd0; + core2ctl_sideband_0_iotile_in = 'd0; + core2ctl_sideband_1_iotile_in = 'd0; + core2ctl_mmr_0_iotile_in = 'd0; + core2ctl_mmr_1_iotile_in = 'd0; + b2l_data_iotile_in = 'd0; + b2t_dqs_iotile_in = 'd0; + b2t_dqsb_iotile_in = 'd0; + cal_bus_clk_iotile_in = 'd0; + cal_bus_avl_read_iotile_in = 'd0; + cal_bus_avl_write_iotile_in = 'd0; + cal_bus_avl_address_iotile_in = 'd0; + cal_bus_avl_write_data_iotile_in = 'd0; + pa_dprio_clk_iotile_in = 'd0; + pa_dprio_read_iotile_in = 'd0; + pa_dprio_reg_addr_iotile_in = 'd0; + pa_dprio_rst_n_iotile_in = 'd0; + pa_dprio_write_iotile_in = 'd0; + pa_dprio_writedata_iotile_in = 'd0; + end + end + end + endgenerate + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_afi_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_afi_if.sv new file mode 100644 index 000000000000..8f18ec0c3c48 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_afi_if.sv @@ -0,0 +1,963 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the AFI interface through which +// a soft controller interacts with the memory interface PHY inside the tile. +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) + +`define _core2l_afi(_loc, _port_i, _phase_i) core2l_data\ + [`_get_tile(_loc, _port_i)]\ + [`_get_lane(_loc, _port_i)]\ + [(`_get_pin(_loc, _port_i) * 8) + _phase_i] + +`define _core2l_oe(_loc, _port_i, _phase_i) core2l_oe\ + [`_get_tile(_loc, _port_i)]\ + [`_get_lane(_loc, _port_i)]\ + [(`_get_pin(_loc, _port_i) * 4) + _phase_i] + +`define _l2core_afi(_loc, _port_i, _phase_i) l2core_data\ + [`_get_tile(_loc, _port_i)]\ + [`_get_lane(_loc, _port_i)]\ + [(`_get_pin(_loc, _port_i) * 8) + _phase_i] + +`define _unused_core2l_afi(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +`define _unused_core2l_oe(_pin_i) core2l_oe\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 4) +: 4] + +`define _connect_out(_loc, _mem_port_width, _afi_port_width, _afi_port, _afi_oe_port_width, _afi_oe_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : oport \ + for (phase_i = 0; phase_i < 8; ++phase_i) begin : data_phase \ + if (phase_i < _afi_port_width / _mem_port_width) begin \ + assign `_core2l_afi(_loc, port_i, phase_i) = _afi_port[_mem_port_width * phase_i + port_i]; \ + end else begin \ + assign `_core2l_afi(_loc, port_i, phase_i) = 1'b0; \ + end \ + end \ + for (phase_i = 0; phase_i < 4; ++phase_i) begin : oe_phase \ + if (phase_i < SDR_RATIO) begin \ + assign `_core2l_oe(_loc, port_i, phase_i) = _afi_oe_port[(port_i / (_mem_port_width / (_afi_oe_port_width / SDR_RATIO))) * SDR_RATIO + phase_i]; \ + end else begin \ + assign `_core2l_oe(_loc, port_i, phase_i) = 1'b0; \ + end \ + end \ + end + +`define _connect_out_with_regs(_loc, _mem_port_width, _afi_port_width, _afi_port, _afi_oe_port_width, _afi_oe_port) \ + logic [_afi_port_width-1:0] sr_o; \ + altera_emif_arch_nf_regs # ( \ + .REGISTER (REGISTER_AFI), \ + .WIDTH (_afi_port_width) \ + ) afi_regs_o ( \ + .clk (afi_clk), \ + .reset_n (1'b1), \ + .data_in (_afi_port), \ + .data_out (sr_o) \ + ); \ + `_connect_out(_loc, _mem_port_width, _afi_port_width, sr_o, _afi_oe_port_width, _afi_oe_port) + +`define _connect_in(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : iport \ + for (phase_i = 0; phase_i < _afi_port_width / _mem_port_width; ++phase_i) begin : data_phase \ + assign _afi_port[_mem_port_width * phase_i + port_i] = `_l2core_afi(_loc, port_i, phase_i); \ + end \ + end + +`define _connect_in_with_regs(_loc, _mem_port_width, _afi_port_width, _afi_port) \ + logic [_afi_port_width-1:0] sr_i; \ + `_connect_in(_loc, _mem_port_width, _afi_port_width, sr_i) \ + altera_emif_arch_nf_regs # ( \ + .REGISTER (REGISTER_AFI), \ + .WIDTH (_afi_port_width) \ + ) afi_regs_i ( \ + .clk (afi_clk), \ + .reset_n (1'b1), \ + .data_in (sr_i), \ + .data_out (_afi_port) \ + ); + +module altera_emif_arch_nf_afi_if #( + + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter REGISTER_AFI = 0, + parameter PORT_AFI_ADDR_WIDTH = 1, + parameter PORT_AFI_BA_WIDTH = 1, + parameter PORT_AFI_BG_WIDTH = 1, + parameter PORT_AFI_C_WIDTH = 1, + parameter PORT_AFI_CKE_WIDTH = 1, + parameter PORT_AFI_CS_N_WIDTH = 1, + parameter PORT_AFI_RM_WIDTH = 1, + parameter PORT_AFI_ODT_WIDTH = 1, + parameter PORT_AFI_RAS_N_WIDTH = 1, + parameter PORT_AFI_CAS_N_WIDTH = 1, + parameter PORT_AFI_WE_N_WIDTH = 1, + parameter PORT_AFI_RST_N_WIDTH = 1, + parameter PORT_AFI_ACT_N_WIDTH = 1, + parameter PORT_AFI_PAR_WIDTH = 1, + parameter PORT_AFI_CA_WIDTH = 1, + parameter PORT_AFI_REF_N_WIDTH = 1, + parameter PORT_AFI_WPS_N_WIDTH = 1, + parameter PORT_AFI_RPS_N_WIDTH = 1, + parameter PORT_AFI_DOFF_N_WIDTH = 1, + parameter PORT_AFI_LD_N_WIDTH = 1, + parameter PORT_AFI_RW_N_WIDTH = 1, + parameter PORT_AFI_LBK0_N_WIDTH = 1, + parameter PORT_AFI_LBK1_N_WIDTH = 1, + parameter PORT_AFI_CFG_N_WIDTH = 1, + parameter PORT_AFI_AP_WIDTH = 1, + parameter PORT_AFI_AINV_WIDTH = 1, + parameter PORT_AFI_DM_WIDTH = 1, + parameter PORT_AFI_DM_N_WIDTH = 1, + parameter PORT_AFI_BWS_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DINV_WIDTH = 1, + parameter PORT_AFI_WDATA_DINV_WIDTH = 1, + parameter PORT_AFI_DQS_BURST_WIDTH = 1, + parameter PORT_AFI_WDATA_VALID_WIDTH = 1, + parameter PORT_AFI_WDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 1, + parameter PORT_AFI_RDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_VALID_WIDTH = 1, + parameter PORT_AFI_RRANK_WIDTH = 1, + parameter PORT_AFI_WRANK_WIDTH = 1, + parameter PORT_AFI_ALERT_N_WIDTH = 1, + parameter PORT_AFI_PE_N_WIDTH = 1, + + // Definition of port widths for "mem" interface (auto-generated) + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + parameter PORT_MEM_CK_PINLOC = 10'b0000000000, + parameter PORT_MEM_CK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_A_PINLOC = 10'b0000000000, + parameter PORT_MEM_BA_PINLOC = 10'b0000000000, + parameter PORT_MEM_BG_PINLOC = 10'b0000000000, + parameter PORT_MEM_C_PINLOC = 10'b0000000000, + parameter PORT_MEM_CKE_PINLOC = 10'b0000000000, + parameter PORT_MEM_CS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RM_PINLOC = 10'b0000000000, + parameter PORT_MEM_ODT_PINLOC = 10'b0000000000, + parameter PORT_MEM_RAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WE_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RESET_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ACT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PAR_PINLOC = 10'b0000000000, + parameter PORT_MEM_CA_PINLOC = 10'b0000000000, + parameter PORT_MEM_REF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DOFF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK0_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK1_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CFG_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_AP_PINLOC = 10'b0000000000, + parameter PORT_MEM_AINV_PINLOC = 10'b0000000000, + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVB_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ALERT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PE_N_PINLOC = 10'b0000000000, + + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter LANES_USAGE = 1'b0, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0, + + // Parameter indicating if the OE is inverted or not + parameter PINS_INVERT_OE = 1'b0, + + parameter MEM_DATA_MASK_EN = 1, + parameter PHY_HMC_CLK_RATIO = 1 + +) ( + input logic afi_clk, + input logic afi_reset_n, + + input logic [PORT_AFI_ADDR_WIDTH-1:0] afi_addr, + input logic [PORT_AFI_BA_WIDTH-1:0] afi_ba, + input logic [PORT_AFI_BG_WIDTH-1:0] afi_bg, + input logic [PORT_AFI_C_WIDTH-1:0] afi_c, + input logic [PORT_AFI_CKE_WIDTH-1:0] afi_cke, + input logic [PORT_AFI_CS_N_WIDTH-1:0] afi_cs_n, + input logic [PORT_AFI_RM_WIDTH-1:0] afi_rm, + input logic [PORT_AFI_ODT_WIDTH-1:0] afi_odt, + input logic [PORT_AFI_RAS_N_WIDTH-1:0] afi_ras_n, + input logic [PORT_AFI_CAS_N_WIDTH-1:0] afi_cas_n, + input logic [PORT_AFI_WE_N_WIDTH-1:0] afi_we_n, + input logic [PORT_AFI_RST_N_WIDTH-1:0] afi_rst_n, + input logic [PORT_AFI_ACT_N_WIDTH-1:0] afi_act_n, + input logic [PORT_AFI_PAR_WIDTH-1:0] afi_par, + input logic [PORT_AFI_CA_WIDTH-1:0] afi_ca, + input logic [PORT_AFI_REF_N_WIDTH-1:0] afi_ref_n, + input logic [PORT_AFI_WPS_N_WIDTH-1:0] afi_wps_n, + input logic [PORT_AFI_RPS_N_WIDTH-1:0] afi_rps_n, + input logic [PORT_AFI_DOFF_N_WIDTH-1:0] afi_doff_n, + input logic [PORT_AFI_LD_N_WIDTH-1:0] afi_ld_n, + input logic [PORT_AFI_RW_N_WIDTH-1:0] afi_rw_n, + input logic [PORT_AFI_LBK0_N_WIDTH-1:0] afi_lbk0_n, + input logic [PORT_AFI_LBK1_N_WIDTH-1:0] afi_lbk1_n, + input logic [PORT_AFI_CFG_N_WIDTH-1:0] afi_cfg_n, + input logic [PORT_AFI_AP_WIDTH-1:0] afi_ap, + input logic [PORT_AFI_AINV_WIDTH-1:0] afi_ainv, + input logic [PORT_AFI_DM_WIDTH-1:0] afi_dm, + input logic [PORT_AFI_DM_N_WIDTH-1:0] afi_dm_n, + input logic [PORT_AFI_BWS_N_WIDTH-1:0] afi_bws_n, + output logic [PORT_AFI_RDATA_DBI_N_WIDTH-1:0] afi_rdata_dbi_n, + input logic [PORT_AFI_WDATA_DBI_N_WIDTH-1:0] afi_wdata_dbi_n, + output logic [PORT_AFI_RDATA_DINV_WIDTH-1:0] afi_rdata_dinv, + input logic [PORT_AFI_WDATA_DINV_WIDTH-1:0] afi_wdata_dinv, + input logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst, + input logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid, + input logic [PORT_AFI_WDATA_WIDTH-1:0] afi_wdata, + input logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full, + output logic [PORT_AFI_RDATA_WIDTH-1:0] afi_rdata, + output logic [PORT_AFI_RDATA_VALID_WIDTH-1:0] afi_rdata_valid, + input logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank, + input logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank, + output logic [PORT_AFI_ALERT_N_WIDTH-1:0] afi_alert_n, + output logic [PORT_AFI_PE_N_WIDTH-1:0] afi_pe_n, + + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid +); + timeunit 1ns; + timeprecision 1ps; + + // Enum that defines whether a lane is used or not, and in what mode. + // This enum type is used to encode the LANES_USAGE_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + localparam SDR_RATIO = PHY_HMC_CLK_RATIO; + localparam DDR_RATIO = SDR_RATIO * 2; + + localparam NUM_OF_LOGICAL_RANKS = PORT_AFI_RRANK_WIDTH / SDR_RATIO; + + logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank_r; + logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank_r; + logic [15:0] afi_rrank_r_padded; + logic [15:0] afi_wrank_r_padded; + + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_RRANK_WIDTH) + ) afi_rrank_regs ( + .clk (afi_clk), + .reset_n (afi_reset_n), + .data_in (afi_rrank), + .data_out (afi_rrank_r) + ); + + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_WRANK_WIDTH) + ) afi_wrank_regs ( + .clk (afi_clk), + .reset_n (afi_reset_n), + .data_in (afi_wrank), + .data_out (afi_wrank_r) + ); + + generate + genvar r; + genvar t; + + for (t = 0; t < 4; ++t) begin: timeslot + for (r = 0; r < 4; ++r) begin : rank + if (t >= SDR_RATIO || r >= NUM_OF_LOGICAL_RANKS) begin + assign afi_rrank_r_padded[t * 4 + r] = 1'b0; + assign afi_wrank_r_padded[t * 4 + r] = 1'b0; + end else begin + assign afi_rrank_r_padded[t * 4 + r] = afi_rrank_r[t * NUM_OF_LOGICAL_RANKS + r]; + assign afi_wrank_r_padded[t * 4 + r] = afi_wrank_r[t * NUM_OF_LOGICAL_RANKS + r]; + end + end + end + endgenerate + + assign core2l_mrnk_read = {(NUM_OF_RTL_TILES * LANES_PER_TILE){afi_rrank_r_padded}}; + assign core2l_mrnk_write = {(NUM_OF_RTL_TILES * LANES_PER_TILE){afi_wrank_r_padded}}; + + assign afi_alert_n = '0; + assign afi_pe_n = '0; + + generate + genvar port_i; + genvar phase_i; + genvar tile_i; + genvar lane_i; + genvar pin_i; + genvar i; + + //////////////////////////////////////////////////////////////////////////// + // Connection for read control signals afi_rdata_en_full and afi_rdata_valid + //////////////////////////////////////////////////////////////////////////// + + // Register and duplicate the afi_rdata_en_full signal for timing closure + logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full_r; + + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH) + ) afi_rdata_en_full_regs ( + .clk (afi_clk), + .reset_n (afi_reset_n), + .data_in (afi_rdata_en_full), + .data_out (afi_rdata_en_full_r) + ); + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : dual_port + + // External memory has dual data ports (i.e. DQA and DQB, as in QDR-IV) + // Split afi_rdata_en_full based on which port the signal belongs to. + // This special code path relies on the location of QKA/QKB pins to identify + // the read lanes for each data port. + logic [3:0] afi_rdata_en_full_r_padded_a; + logic [3:0] afi_rdata_en_full_r_padded_b; + + if (SDR_RATIO < 4) begin + assign afi_rdata_en_full_r_padded_a = {'0, afi_rdata_en_full_r[SDR_RATIO-1:0]}; + assign afi_rdata_en_full_r_padded_b = {'0, afi_rdata_en_full_r[PORT_AFI_RDATA_EN_FULL_WIDTH-1:SDR_RATIO]}; + end else begin + assign afi_rdata_en_full_r_padded_a = afi_rdata_en_full_r[SDR_RATIO-1:0]; + assign afi_rdata_en_full_r_padded_b = afi_rdata_en_full_r[PORT_AFI_RDATA_EN_FULL_WIDTH-1:SDR_RATIO]; + end + + // afi_rdata_en_full for port A + for (port_i = 0; port_i < PORT_MEM_QKA_WIDTH; ++port_i) begin : port_a + assign core2l_rdata_en_full[`_get_tile(PORT_MEM_QKA_PINLOC, port_i)][`_get_lane(PORT_MEM_QKA_PINLOC, port_i)] = afi_rdata_en_full_r_padded_a; + if (MEM_TTL_DATA_WIDTH / MEM_TTL_NUM_OF_READ_GROUPS == 18) begin + assign core2l_rdata_en_full[`_get_tile(PORT_MEM_QKA_PINLOC, port_i)][`_get_lane(PORT_MEM_QKA_PINLOC, port_i)-1] = afi_rdata_en_full_r_padded_a; + end + end + + // afi_rdata_en_full for port B + for (port_i = 0; port_i < PORT_MEM_QKB_WIDTH; ++port_i) begin : port_b + assign core2l_rdata_en_full[`_get_tile(PORT_MEM_QKB_PINLOC, port_i)][`_get_lane(PORT_MEM_QKB_PINLOC, port_i)] = afi_rdata_en_full_r_padded_b; + if (MEM_TTL_DATA_WIDTH / MEM_TTL_NUM_OF_READ_GROUPS == 18) begin + assign core2l_rdata_en_full[`_get_tile(PORT_MEM_QKB_PINLOC, port_i)][`_get_lane(PORT_MEM_QKB_PINLOC, port_i)-1] = afi_rdata_en_full_r_padded_b; + end + end + + // Tie off for non-read-data-lanes to avoid synthesis warnings + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) begin : tile + for (lane_i = 0; lane_i < LANES_PER_TILE; ++lane_i) begin : lane + if (`_get_lane_usage(tile_i, lane_i) != LANE_USAGE_RDATA && `_get_lane_usage(tile_i, lane_i) != LANE_USAGE_WRDATA) + assign core2l_rdata_en_full[tile_i][lane_i] = '0; + end + end + + // Connection for afi_rdata_valid + logic [PORT_AFI_RDATA_VALID_WIDTH/2-1:0] afi_rdata_valid_a; + logic [PORT_AFI_RDATA_VALID_WIDTH/2-1:0] afi_rdata_valid_b; + + assign afi_rdata_valid_a = l2core_rdata_valid[`_get_tile(PORT_MEM_QKA_PINLOC, 0)][`_get_lane(PORT_MEM_QKA_PINLOC, 0)][PORT_AFI_RDATA_VALID_WIDTH/2-1:0]; + assign afi_rdata_valid_b = l2core_rdata_valid[`_get_tile(PORT_MEM_QKB_PINLOC, 0)][`_get_lane(PORT_MEM_QKB_PINLOC, 0)][PORT_AFI_RDATA_VALID_WIDTH/2-1:0]; + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_RDATA_VALID_WIDTH) + ) afi_rdata_valid_regs ( + .clk (afi_clk), + .reset_n (afi_reset_n), + .data_in ({afi_rdata_valid_b, afi_rdata_valid_a}), + .data_out (afi_rdata_valid) + ); + + end else begin : single_port + + // External memory has single port. + // This general code path works for non QDR-IV protocols. + logic [3:0] afi_rdata_en_full_r_padded; + + if (PORT_AFI_RDATA_EN_FULL_WIDTH < 4) + assign afi_rdata_en_full_r_padded = {'0, afi_rdata_en_full_r}; + else + assign afi_rdata_en_full_r_padded = afi_rdata_en_full_r; + + assign core2l_rdata_en_full = {(NUM_OF_RTL_TILES * LANES_PER_TILE){afi_rdata_en_full_r_padded}}; + + // Connection for afi_rdata_valid + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_RDATA_VALID_WIDTH) + ) afi_rdata_valid_regs ( + .clk (afi_clk), + .reset_n (afi_reset_n), + .data_in (l2core_rdata_valid[PRI_RDATA_TILE_INDEX][PRI_RDATA_LANE_INDEX][PORT_AFI_RDATA_VALID_WIDTH-1:0]), + .data_out (afi_rdata_valid) + ); + end + + // Generate constant OE signal for output-only ports + localparam OE_ON_WIDTH = SDR_RATIO; + logic [OE_ON_WIDTH-1:0] oe_on; + assign oe_on = '1; + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to output-only pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_A_PINLOC) != 0) begin : mem_a + `_connect_out_with_regs(PORT_MEM_A_PINLOC, PORT_MEM_A_WIDTH, PORT_AFI_ADDR_WIDTH, afi_addr, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_BA_PINLOC) != 0) begin : mem_ba + `_connect_out_with_regs(PORT_MEM_BA_PINLOC, PORT_MEM_BA_WIDTH, PORT_AFI_BA_WIDTH, afi_ba, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_BG_PINLOC) != 0) begin : mem_bg + `_connect_out_with_regs(PORT_MEM_BG_PINLOC, PORT_MEM_BG_WIDTH, PORT_AFI_BG_WIDTH, afi_bg, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_C_PINLOC) != 0) begin : mem_c + `_connect_out_with_regs(PORT_MEM_C_PINLOC, PORT_MEM_C_WIDTH, PORT_AFI_C_WIDTH, afi_c, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CKE_PINLOC) != 0) begin : mem_cke + `_connect_out_with_regs(PORT_MEM_CKE_PINLOC, PORT_MEM_CKE_WIDTH, PORT_AFI_CKE_WIDTH, afi_cke, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CS_N_PINLOC) != 0) begin : mem_cs_n + `_connect_out_with_regs(PORT_MEM_CS_N_PINLOC, PORT_MEM_CS_N_WIDTH, PORT_AFI_CS_N_WIDTH, afi_cs_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_RM_PINLOC) != 0) begin : mem_rm + `_connect_out_with_regs(PORT_MEM_RM_PINLOC, PORT_MEM_RM_WIDTH, PORT_AFI_RM_WIDTH, afi_rm, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_ODT_PINLOC) != 0) begin : mem_odt + `_connect_out_with_regs(PORT_MEM_ODT_PINLOC, PORT_MEM_ODT_WIDTH, PORT_AFI_ODT_WIDTH, afi_odt, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_RAS_N_PINLOC) != 0) begin : mem_ras_n + `_connect_out_with_regs(PORT_MEM_RAS_N_PINLOC, PORT_MEM_RAS_N_WIDTH, PORT_AFI_RAS_N_WIDTH, afi_ras_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CAS_N_PINLOC) != 0) begin : mem_cas_n + `_connect_out_with_regs(PORT_MEM_CAS_N_PINLOC, PORT_MEM_CAS_N_WIDTH, PORT_AFI_CAS_N_WIDTH, afi_cas_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_WE_N_PINLOC) != 0) begin : mem_we_n + `_connect_out_with_regs(PORT_MEM_WE_N_PINLOC, PORT_MEM_WE_N_WIDTH, PORT_AFI_WE_N_WIDTH, afi_we_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_RESET_N_PINLOC) != 0) begin : mem_reset_n + `_connect_out_with_regs(PORT_MEM_RESET_N_PINLOC, PORT_MEM_RESET_N_WIDTH, PORT_AFI_RST_N_WIDTH, afi_rst_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_ACT_N_PINLOC) != 0) begin : mem_act_n + `_connect_out_with_regs(PORT_MEM_ACT_N_PINLOC, PORT_MEM_ACT_N_WIDTH, PORT_AFI_ACT_N_WIDTH, afi_act_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_PAR_PINLOC) != 0) begin : mem_par + `_connect_out_with_regs(PORT_MEM_PAR_PINLOC, PORT_MEM_PAR_WIDTH, PORT_AFI_PAR_WIDTH, afi_par, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CA_PINLOC) != 0) begin : mem_ca + `_connect_out_with_regs(PORT_MEM_CA_PINLOC, PORT_MEM_CA_WIDTH, PORT_AFI_CA_WIDTH, afi_ca, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_REF_N_PINLOC) != 0) begin : mem_ref_n + `_connect_out_with_regs(PORT_MEM_REF_N_PINLOC, PORT_MEM_REF_N_WIDTH, PORT_AFI_REF_N_WIDTH, afi_ref_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_WPS_N_PINLOC) != 0) begin : mem_wps_n + `_connect_out_with_regs(PORT_MEM_WPS_N_PINLOC, PORT_MEM_WPS_N_WIDTH, PORT_AFI_WPS_N_WIDTH, afi_wps_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_RPS_N_PINLOC) != 0) begin : mem_rps_n + `_connect_out_with_regs(PORT_MEM_RPS_N_PINLOC, PORT_MEM_RPS_N_WIDTH, PORT_AFI_RPS_N_WIDTH, afi_rps_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_DOFF_N_PINLOC) != 0) begin : mem_doff_n + `_connect_out_with_regs(PORT_MEM_DOFF_N_PINLOC, PORT_MEM_DOFF_N_WIDTH, PORT_AFI_DOFF_N_WIDTH, afi_doff_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0 && `_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : mem_ldab_n + logic [PORT_AFI_LD_N_WIDTH/2-1:0] afi_lda_n, afi_ldb_n; + assign afi_lda_n = afi_ld_n[0 +: PORT_AFI_LD_N_WIDTH / 2]; + assign afi_ldb_n = afi_ld_n[PORT_AFI_LD_N_WIDTH / 2 +: PORT_AFI_LD_N_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_LDA_N_PINLOC, PORT_MEM_LDA_N_WIDTH, (PORT_AFI_LD_N_WIDTH / 2), afi_lda_n, OE_ON_WIDTH, oe_on) + end + if (`_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_LDB_N_PINLOC, PORT_MEM_LDB_N_WIDTH, (PORT_AFI_LD_N_WIDTH / 2), afi_ldb_n, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0 && `_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : mem_rwab_n + logic [PORT_AFI_RW_N_WIDTH/2-1:0] afi_rwa_n, afi_rwb_n; + + assign afi_rwa_n = afi_rw_n[0 +: PORT_AFI_RW_N_WIDTH / 2]; + assign afi_rwb_n = afi_rw_n[PORT_AFI_RW_N_WIDTH / 2 +: PORT_AFI_RW_N_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_RWA_N_PINLOC, PORT_MEM_RWA_N_WIDTH, (PORT_AFI_RW_N_WIDTH / 2), afi_rwa_n, OE_ON_WIDTH, oe_on) + end + if (`_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_RWB_N_PINLOC, PORT_MEM_RWB_N_WIDTH, (PORT_AFI_RW_N_WIDTH / 2), afi_rwb_n, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_LBK0_N_PINLOC) != 0) begin : mem_lbk0_n + `_connect_out_with_regs(PORT_MEM_LBK0_N_PINLOC, PORT_MEM_LBK0_N_WIDTH, PORT_AFI_LBK0_N_WIDTH, afi_lbk0_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_LBK1_N_PINLOC) != 0) begin : mem_lbk1_n + `_connect_out_with_regs(PORT_MEM_LBK1_N_PINLOC, PORT_MEM_LBK1_N_WIDTH, PORT_AFI_LBK1_N_WIDTH, afi_lbk1_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CFG_N_PINLOC) != 0) begin : mem_cfg_n + `_connect_out_with_regs(PORT_MEM_CFG_N_PINLOC, PORT_MEM_CFG_N_WIDTH, PORT_AFI_CFG_N_WIDTH, afi_cfg_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_AP_PINLOC) != 0) begin : mem_ap + `_connect_out_with_regs(PORT_MEM_AP_PINLOC, PORT_MEM_AP_WIDTH, PORT_AFI_AP_WIDTH, afi_ap, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_AINV_PINLOC) != 0) begin : mem_ainv + `_connect_out_with_regs(PORT_MEM_AINV_PINLOC, PORT_MEM_AINV_WIDTH, PORT_AFI_AINV_WIDTH, afi_ainv, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0) begin : mem_dm + `_connect_out_with_regs(PORT_MEM_DM_PINLOC, PORT_MEM_DM_WIDTH, PORT_AFI_DM_WIDTH, ~afi_dm, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_BWS_N_PINLOC) != 0) begin : mem_bws_n + `_connect_out_with_regs(PORT_MEM_BWS_N_PINLOC, PORT_MEM_BWS_N_WIDTH, PORT_AFI_BWS_N_WIDTH, ~afi_bws_n, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_D_PINLOC) != 0) begin : mem_d + `_connect_out_with_regs(PORT_MEM_D_PINLOC, PORT_MEM_D_WIDTH, PORT_AFI_WDATA_WIDTH, afi_wdata, OE_ON_WIDTH, oe_on) + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to input-only pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_Q_PINLOC) != 0) begin : mem_q + `_connect_in_with_regs(PORT_MEM_Q_PINLOC, PORT_MEM_Q_WIDTH, PORT_AFI_RDATA_WIDTH, afi_rdata) + + logic [PORT_MEM_Q_WIDTH-1:0] zeros; + assign zeros = '0; + // Switching OE on read pins as we switch OE_INVERT in the IP + `_connect_out(PORT_MEM_Q_PINLOC, PORT_MEM_Q_WIDTH, PORT_MEM_Q_WIDTH, zeros, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_ALERT_N_PINLOC) != 0) begin : mem_alert_n + logic [PORT_MEM_ALERT_N_WIDTH-1:0] zeros; + assign zeros = '0; + `_connect_out(PORT_MEM_ALERT_N_PINLOC, PORT_MEM_ALERT_N_WIDTH, PORT_MEM_ALERT_N_WIDTH, zeros, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_PE_N_PINLOC) != 0) begin : mem_pe_n + logic [PORT_MEM_PE_N_WIDTH-1:0] zeros; + assign zeros = '0; + + logic [OE_ON_WIDTH-1:0] oe_off; + assign oe_off = '0; + `_connect_out(PORT_MEM_PE_N_PINLOC, PORT_MEM_PE_N_WIDTH, PORT_MEM_PE_N_WIDTH, zeros, OE_ON_WIDTH, oe_off) + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to bidirectional pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 || `_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : mem_sp_bidir_data + + // Replicate per-interface afi_wdata_valid to be per-group to help timing closure + localparam PORT_AFI_WDATA_VALID_ALL_GRPS_WIDTH = PORT_AFI_WDATA_VALID_WIDTH * MEM_TTL_NUM_OF_WRITE_GROUPS; + logic [PORT_AFI_WDATA_VALID_ALL_GRPS_WIDTH-1:0] afi_wdata_valid_all_grps_r; + + for (i = 0; i < MEM_TTL_NUM_OF_WRITE_GROUPS; ++i) begin : wgrp + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_WDATA_VALID_WIDTH) + ) afi_wdata_valid_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_wdata_valid), + .data_out (afi_wdata_valid_all_grps_r[i * PORT_AFI_WDATA_VALID_WIDTH +: PORT_AFI_WDATA_VALID_WIDTH]) + ); + end + + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0) begin : mem_dq + `_connect_out_with_regs(PORT_MEM_DQ_PINLOC, PORT_MEM_DQ_WIDTH, PORT_AFI_WDATA_WIDTH, afi_wdata, PORT_AFI_WDATA_VALID_ALL_GRPS_WIDTH, afi_wdata_valid_all_grps_r) + `_connect_in_with_regs(PORT_MEM_DQ_PINLOC, PORT_MEM_DQ_WIDTH, PORT_AFI_RDATA_WIDTH, afi_rdata) + end + + if (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : mem_dbi_n + if (MEM_DATA_MASK_EN) begin : dm + `_connect_out_with_regs(PORT_MEM_DBI_N_PINLOC, PORT_MEM_DBI_N_WIDTH, PORT_AFI_DM_N_WIDTH, afi_dm_n, PORT_AFI_WDATA_VALID_ALL_GRPS_WIDTH, afi_wdata_valid_all_grps_r) + end else begin : wdbi + logic [PORT_MEM_DBI_N_WIDTH-1:0] zeros; + assign zeros = '0; + `_connect_out(PORT_MEM_DBI_N_PINLOC, PORT_MEM_DBI_N_WIDTH, PORT_MEM_DBI_N_WIDTH, zeros, PORT_AFI_WDATA_VALID_ALL_GRPS_WIDTH, afi_wdata_valid_all_grps_r) + end + end + end + + assign afi_rdata_dbi_n = '1; + + if ((`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) || (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0)) begin : mem_dp_bidir_data + + localparam MEM_NUM_OF_WRITE_GROUPS_PER_PORT = MEM_TTL_NUM_OF_WRITE_GROUPS / 2; + localparam PORT_AFI_WDATA_VALID_PER_PORT_WIDTH = PORT_AFI_WDATA_VALID_WIDTH / 2; + localparam PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH = PORT_AFI_WDATA_VALID_PER_PORT_WIDTH * MEM_NUM_OF_WRITE_GROUPS_PER_PORT; + + logic [PORT_AFI_WDATA_VALID_PER_PORT_WIDTH-1:0] afi_wdata_valid_a, afi_wdata_valid_b; + assign afi_wdata_valid_a = afi_wdata_valid[0 +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]; + assign afi_wdata_valid_b = afi_wdata_valid[PORT_AFI_WDATA_VALID_PER_PORT_WIDTH +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]; + + // Replicate per-interface afi_wdata_valid to be per-group to help timing closure + logic [PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH-1:0] afi_wdata_valid_a_all_grps_r, afi_wdata_valid_b_all_grps_r; + + for (i = 0; i < MEM_NUM_OF_WRITE_GROUPS_PER_PORT; ++i) begin : wgrp + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_WDATA_VALID_PER_PORT_WIDTH) + ) afi_wdata_valid_a_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_wdata_valid_a), + .data_out (afi_wdata_valid_a_all_grps_r[i * PORT_AFI_WDATA_VALID_PER_PORT_WIDTH +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]) + ); + + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_WDATA_VALID_PER_PORT_WIDTH) + ) afi_wdata_valid_b_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_wdata_valid_b), + .data_out (afi_wdata_valid_b_all_grps_r[i * PORT_AFI_WDATA_VALID_PER_PORT_WIDTH +: PORT_AFI_WDATA_VALID_PER_PORT_WIDTH]) + ); + end + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : mem_dqab + + logic [PORT_AFI_RDATA_WIDTH/2-1:0] afi_rdata_a , afi_rdata_b; + logic [PORT_AFI_WDATA_WIDTH/2-1:0] afi_wdata_a , afi_wdata_b; + + assign afi_rdata[0 +: PORT_AFI_RDATA_WIDTH / 2] = afi_rdata_a; + assign afi_wdata_a = afi_wdata[0 +: PORT_AFI_WDATA_WIDTH / 2]; + + assign afi_rdata[PORT_AFI_RDATA_WIDTH / 2 +: PORT_AFI_RDATA_WIDTH / 2] = afi_rdata_b; + assign afi_wdata_b = afi_wdata[PORT_AFI_RDATA_WIDTH / 2 +: PORT_AFI_WDATA_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_DQA_PINLOC, PORT_MEM_DQA_WIDTH, (PORT_AFI_WDATA_WIDTH / 2), afi_wdata_a, PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH, afi_wdata_valid_a_all_grps_r) + `_connect_in_with_regs(PORT_MEM_DQA_PINLOC, PORT_MEM_DQA_WIDTH, (PORT_AFI_RDATA_WIDTH / 2), afi_rdata_a) + end + + if (`_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_DQB_PINLOC, PORT_MEM_DQB_WIDTH, (PORT_AFI_WDATA_WIDTH / 2), afi_wdata_b, PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH, afi_wdata_valid_b_all_grps_r) + `_connect_in_with_regs(PORT_MEM_DQB_PINLOC, PORT_MEM_DQB_WIDTH, (PORT_AFI_RDATA_WIDTH / 2), afi_rdata_b) + end + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0) begin : mem_dinvab + + logic [PORT_AFI_RDATA_DINV_WIDTH/2-1:0] afi_rdata_dinv_a , afi_rdata_dinv_b; + logic [PORT_AFI_WDATA_DINV_WIDTH/2-1:0] afi_wdata_dinv_a , afi_wdata_dinv_b; + + assign afi_rdata_dinv[0 +: PORT_AFI_RDATA_DINV_WIDTH / 2] = afi_rdata_dinv_a; + assign afi_wdata_dinv_a = afi_wdata_dinv[0 +: PORT_AFI_RDATA_DINV_WIDTH / 2]; + + assign afi_rdata_dinv[PORT_AFI_RDATA_DINV_WIDTH / 2 +: PORT_AFI_RDATA_DINV_WIDTH / 2] = afi_rdata_dinv_b; + assign afi_wdata_dinv_b = afi_wdata_dinv[PORT_AFI_RDATA_DINV_WIDTH / 2 +: PORT_AFI_RDATA_DINV_WIDTH / 2]; + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : a + `_connect_out_with_regs(PORT_MEM_DINVA_PINLOC, PORT_MEM_DINVA_WIDTH, (PORT_AFI_WDATA_DINV_WIDTH / 2), afi_wdata_dinv_a, PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH, afi_wdata_valid_a_all_grps_r) + `_connect_in_with_regs(PORT_MEM_DINVA_PINLOC, PORT_MEM_DINVA_WIDTH, (PORT_AFI_RDATA_DINV_WIDTH / 2), afi_rdata_dinv_a) + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : b + `_connect_out_with_regs(PORT_MEM_DINVB_PINLOC, PORT_MEM_DINVB_WIDTH, (PORT_AFI_WDATA_DINV_WIDTH / 2), afi_wdata_dinv_b, PORT_AFI_WDATA_VALID_PER_PORT_ALL_GRPS_WIDTH, afi_wdata_valid_b_all_grps_r) + `_connect_in_with_regs(PORT_MEM_DINVB_PINLOC, PORT_MEM_DINVB_WIDTH, (PORT_AFI_RDATA_DINV_WIDTH / 2), afi_rdata_dinv_b) + end + end else begin : no_mem_dinvab + assign afi_rdata_dinv = '0; + end + end else begin : no_mem_dp_bidir_data + assign afi_rdata_dinv = '0; + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to bidir strobe pins + //////////////////////////////////////////////////////////////////////////// + if (`_get_pin_count(PORT_MEM_DQS_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DQS_N_PINLOC) != 0) begin : mem_dqs_pair + logic [(PORT_MEM_DQS_WIDTH * DDR_RATIO)-1:0] disable_dqs; + assign disable_dqs = '0; + + logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst_r; + + (* altera_attribute = {"-name MAX_FANOUT 1; -name ADV_NETLIST_OPT_ALLOWED ALWAYS_ALLOW"}*) + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (PORT_AFI_DQS_BURST_WIDTH) + ) afi_dqs_burst_regs ( + .clk (afi_clk), + .reset_n (1'b1), + .data_in (afi_dqs_burst), + .data_out (afi_dqs_burst_r) + ); + + if (`_get_pin_count(PORT_MEM_DQS_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_DQS_PINLOC, PORT_MEM_DQS_WIDTH, (PORT_MEM_DQS_WIDTH * DDR_RATIO), disable_dqs, PORT_AFI_DQS_BURST_WIDTH, afi_dqs_burst_r) + end + + if (`_get_pin_count(PORT_MEM_DQS_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_DQS_N_PINLOC, PORT_MEM_DQS_N_WIDTH, (PORT_MEM_DQS_N_WIDTH * DDR_RATIO), disable_dqs, PORT_AFI_DQS_BURST_WIDTH, afi_dqs_burst_r) + end + end + + //////////////////////////////////////////////////////////////////////////// + // Connection for AFI signals that go to output-only clock pins + //////////////////////////////////////////////////////////////////////////// + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0 && `_get_pin_count(PORT_MEM_CK_N_PINLOC) != 0) begin : mem_ck_pair + logic [(PORT_MEM_CK_WIDTH * DDR_RATIO)-1:0] disable_ck; + assign disable_ck = '0; + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_CK_PINLOC, PORT_MEM_CK_WIDTH, (PORT_MEM_CK_WIDTH * DDR_RATIO), disable_ck, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_CK_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_CK_N_PINLOC, PORT_MEM_CK_N_WIDTH, (PORT_MEM_CK_N_WIDTH * DDR_RATIO), disable_ck, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DK_N_PINLOC) != 0) begin : mem_dk_pair + logic [(PORT_MEM_DK_WIDTH * DDR_RATIO)-1:0] disable_dk; + assign disable_dk = '0; + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_DK_PINLOC, PORT_MEM_DK_WIDTH, (PORT_MEM_DK_WIDTH * DDR_RATIO), disable_dk, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_DK_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_DK_N_PINLOC, PORT_MEM_DK_N_WIDTH, (PORT_MEM_DK_N_WIDTH * DDR_RATIO), disable_dk, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKA_N_PINLOC) != 0) begin : mem_dka_pair + logic [(PORT_MEM_DKA_WIDTH * DDR_RATIO)-1:0] disable_dka; + assign disable_dka = '0; + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_DKA_PINLOC, PORT_MEM_DKA_WIDTH, (PORT_MEM_DKA_WIDTH * DDR_RATIO), disable_dka, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_DKA_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_DKA_N_PINLOC, PORT_MEM_DKA_N_WIDTH, (PORT_MEM_DKA_N_WIDTH * DDR_RATIO), disable_dka, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0 && `_get_pin_count(PORT_MEM_DKB_N_PINLOC) != 0) begin : mem_dkb_pair + logic [(PORT_MEM_DKB_WIDTH * DDR_RATIO)-1:0] disable_dkb; + assign disable_dkb = '0; + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_DKB_PINLOC, PORT_MEM_DKB_WIDTH, (PORT_MEM_DKB_WIDTH * DDR_RATIO), disable_dkb, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_DKB_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_DKB_N_PINLOC, PORT_MEM_DKB_N_WIDTH, (PORT_MEM_DKB_N_WIDTH * DDR_RATIO), disable_dkb, OE_ON_WIDTH, oe_on) + end + end + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0 && `_get_pin_count(PORT_MEM_K_N_PINLOC) != 0) begin : mem_k_pair + logic [(PORT_MEM_K_WIDTH * DDR_RATIO)-1:0] disable_k; + assign disable_k = '0; + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0) begin : p + `_connect_out_with_regs(PORT_MEM_K_PINLOC, PORT_MEM_K_WIDTH, (PORT_MEM_K_WIDTH * DDR_RATIO), disable_k, OE_ON_WIDTH, oe_on) + end + + if (`_get_pin_count(PORT_MEM_K_N_PINLOC) != 0) begin : n + `_connect_out_with_regs(PORT_MEM_K_N_PINLOC, PORT_MEM_K_N_WIDTH, (PORT_MEM_K_N_WIDTH * DDR_RATIO), disable_k, OE_ON_WIDTH, oe_on) + end + end + + //////////////////////////////////////////////////////////////////////////// + // Tie off core2l_data for unused connections + ////////////////////////////////////////////////////////////////////////////// + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) begin + assign `_unused_core2l_afi(pin_i) = '0; + if (PINS_INVERT_OE[pin_i] == 1'b0) begin + assign `_unused_core2l_oe(pin_i) = '1; + end else begin + assign `_unused_core2l_oe(pin_i) = '0; + end + end + + + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_df.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_df.sv new file mode 100644 index 000000000000..c1830d6e5ca5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_df.sv @@ -0,0 +1,162 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_bdir_df #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + inout tri io, + inout tri iobar, + output logic ibuf_o, + input logic obuf_i, + input logic obuf_ibar, + input logic obuf_oe, + input logic obuf_oebar, + input logic obuf_dtc, + input logic obuf_dtcbar, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + logic pdiff_out_o; + logic pdiff_out_obar; + logic pdiff_out_oe; + logic pdiff_out_oebar; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + logic pdiff_out_dtc; + logic pdiff_out_dtcbar; + + twentynm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(io), + .ibar(iobar), + .o(ibuf_o), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol() + ); + + twentynm_pseudo_diff_out # ( + .feedthrough ("true") + ) pdiff_out ( + .i(obuf_i), + .ibar(obuf_ibar), + .oein(obuf_oe), + .oebin(obuf_oebar), + .dtcin(obuf_dtc), + .dtcbarin(obuf_dtcbar), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtc(pdiff_out_dtc), + .dtcbar(pdiff_out_dtcbar) + ); + + twentynm_io_obuf obuf ( + .i(pdiff_out_o), + .o(io), + .oe(pdiff_out_oe), + .dynamicterminationcontrol(pdiff_out_dtc), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .obar(), + .devoe() + ); + + twentynm_io_obuf obuf_bar ( + .i(pdiff_out_obar), + .o(iobar), + .oe(pdiff_out_oebar), + .dynamicterminationcontrol(pdiff_out_dtcbar), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .obar(), + .devoe() + ); + end else + begin : no_oct + twentynm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(io), + .ibar(iobar), + .o(ibuf_o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + twentynm_pseudo_diff_out # ( + .feedthrough ("true") + ) pdiff_out ( + .i(obuf_i), + .ibar(obuf_ibar), + .oein(obuf_oe), + .oebin(obuf_oebar), + .dtcin(), + .dtcbarin(), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtc(), + .dtcbar() + ); + + twentynm_io_obuf obuf ( + .i(pdiff_out_o), + .o(io), + .oe(pdiff_out_oe), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + + twentynm_io_obuf obuf_bar ( + .i(pdiff_out_obar), + .o(iobar), + .oe(pdiff_out_oebar), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_se.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_se.sv new file mode 100644 index 000000000000..c035df11ec84 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_bdir_se.sv @@ -0,0 +1,90 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_bdir_se #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + inout tri io, + output logic ibuf_o, + input logic obuf_i, + input logic obuf_oe, + input logic obuf_dtc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_ibuf ibuf( + .i(io), + .o(ibuf_o), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol(), + .ibar() + ); + + twentynm_io_obuf obuf ( + .i(obuf_i), + .o(io), + .oe(obuf_oe), + .dynamicterminationcontrol(obuf_dtc), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .obar(), + .devoe() + ); + end else + begin : no_oct + twentynm_io_ibuf ibuf( + .i(io), + .o(ibuf_o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .ibar() + ); + + twentynm_io_obuf obuf ( + .i(obuf_i), + .o(io), + .oe(obuf_oe), + .dynamicterminationcontrol(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_cp_i.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_cp_i.sv new file mode 100644 index 000000000000..80091163ed4f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_cp_i.sv @@ -0,0 +1,85 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_udir_cp_i # ( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + output logic obar, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_ibuf ibuf( + .i(i), + .o(o), + .ibar(), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol() + ); + + twentynm_io_ibuf ibuf_bar( + .i(ibar), + .o(obar), + .ibar(), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + twentynm_io_ibuf ibuf( + .i(i), + .o(o), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + + twentynm_io_ibuf ibuf_bar( + .i(ibar), + .o(obar), + .ibar(), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_i.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_i.sv new file mode 100644 index 000000000000..b3fe81f47524 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_i.sv @@ -0,0 +1,70 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_udir_df_i # ( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(i), + .ibar(ibar), + .o(o), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + twentynm_io_ibuf # ( + .differential_mode ("true") + ) ibuf ( + .i(i), + .ibar(ibar), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_o.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_o.sv new file mode 100644 index 000000000000..b518804a5c14 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_df_o.sv @@ -0,0 +1,116 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_udir_df_o #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + input logic ibar, + output logic o, + output logic obar, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + logic pdiff_out_o; + logic pdiff_out_obar; + + logic pdiff_out_oe; + logic pdiff_out_oebar; + + twentynm_pseudo_diff_out # ( + .feedthrough("true") + ) pdiff_out ( + .i(i), + .ibar(ibar), + .o(pdiff_out_o), + .obar(pdiff_out_obar), + .oein(1'b1), + .oebin(1'b1), + .oeout(pdiff_out_oe), + .oebout(pdiff_out_oebar), + .dtcin(), + .dtcbarin(), + .dtc(), + .dtcbar() + ); + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_obuf obuf ( + .i(pdiff_out_o), + .o(o), + .oe(pdiff_out_oe), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + + twentynm_io_obuf obuf_bar ( + .i(pdiff_out_obar), + .o(obar), + .oe(pdiff_out_oebar), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + end else + begin : no_oct + twentynm_io_obuf obuf ( + .i(pdiff_out_o), + .o(o), + .oe(pdiff_out_oe), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + + twentynm_io_obuf obuf_bar ( + .i(pdiff_out_obar), + .o(obar), + .oe(pdiff_out_oebar), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .dynamicterminationcontrol(), + .obar(), + .devoe() + ); + end + endgenerate + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_i.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_i.sv new file mode 100644 index 000000000000..e9377c8c3d6f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_i.sv @@ -0,0 +1,65 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_udir_se_i #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + output logic o, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_ibuf ibuf( + .i(i), + .o(o), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .ibar(), + .dynamicterminationcontrol() + ); + end else + begin : no_oct + twentynm_io_ibuf ibuf( + .i(i), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .ibar(), + .dynamicterminationcontrol() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_o.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_o.sv new file mode 100644 index 000000000000..b1ec44424b34 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_udir_se_o.sv @@ -0,0 +1,69 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_udir_se_o #( + parameter OCT_CONTROL_WIDTH = 1, + parameter CALIBRATED_OCT = 1 +) ( + input logic i, + output logic o, + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + if (CALIBRATED_OCT) + begin : cal_oct + twentynm_io_obuf obuf ( + .i(i), + .o(o), + .seriesterminationcontrol(oct_stc), + .parallelterminationcontrol(oct_ptc), + .obar(), + .oe(), + .dynamicterminationcontrol(), + .devoe() + ); + end else + begin : no_oct + twentynm_io_obuf obuf ( + .i(i), + .o(o), + .seriesterminationcontrol(), + .parallelterminationcontrol(), + .obar(), + .oe(), + .dynamicterminationcontrol(), + .devoe() + ); + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_unused.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_unused.sv new file mode 100644 index 000000000000..f4df2c493d8a --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_buf_unused.sv @@ -0,0 +1,37 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_arch_nf_buf_unused ( + output logic o +); + timeunit 1ns; + timeprecision 1ps; + + assign o = 1'b0; +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_bufs.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_bufs.sv new file mode 100644 index 000000000000..da6770cbaaff --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_bufs.sv @@ -0,0 +1,1270 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +module altera_emif_arch_nf_bufs #( + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter PINS_PER_LANE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter OCT_CONTROL_WIDTH = 1, + parameter DQS_BUS_MODE_ENUM = "", + parameter UNUSED_MEM_PINS_PINLOC = 10'b0000000000, + parameter UNUSED_DQS_BUSES_LANELOC = 10'b0000000000, + + // Definition of port widths for "mem" interface (auto-generated) + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + // Definition of parameters describing logical pin allocation + //AUTOGEN_BEGIN: Definition of memory port pinlocs + parameter PORT_MEM_CK_PINLOC = 10'b0000000000, + parameter PORT_MEM_CK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_PINLOC = 10'b0000000000, + parameter PORT_MEM_DK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_PINLOC = 10'b0000000000, + parameter PORT_MEM_K_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_A_PINLOC = 10'b0000000000, + parameter PORT_MEM_BA_PINLOC = 10'b0000000000, + parameter PORT_MEM_BG_PINLOC = 10'b0000000000, + parameter PORT_MEM_C_PINLOC = 10'b0000000000, + parameter PORT_MEM_CKE_PINLOC = 10'b0000000000, + parameter PORT_MEM_CS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RM_PINLOC = 10'b0000000000, + parameter PORT_MEM_ODT_PINLOC = 10'b0000000000, + parameter PORT_MEM_RAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CAS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WE_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RESET_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ACT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PAR_PINLOC = 10'b0000000000, + parameter PORT_MEM_CA_PINLOC = 10'b0000000000, + parameter PORT_MEM_REF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_WPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RPS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DOFF_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LDB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_RWB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK0_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_LBK1_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CFG_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_AP_PINLOC = 10'b0000000000, + parameter PORT_MEM_AINV_PINLOC = 10'b0000000000, + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQB_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVA_PINLOC = 10'b0000000000, + parameter PORT_MEM_DINVB_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQS_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_PINLOC = 10'b0000000000, + parameter PORT_MEM_QK_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKA_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_PINLOC = 10'b0000000000, + parameter PORT_MEM_QKB_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_CQ_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_ALERT_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_PE_N_PINLOC = 10'b0000000000, + + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_AC_CALIBRATED_OCT = 1, + parameter PHY_CK_CALIBRATED_OCT = 1, + parameter PHY_DATA_CALIBRATED_OCT = 1 +) ( + input logic [PINS_IN_RTL_TILES-1:0] l2b_data, + input logic [PINS_IN_RTL_TILES-1:0] l2b_oe, + input logic [PINS_IN_RTL_TILES-1:0] l2b_dtc, + output logic [PINS_IN_RTL_TILES-1:0] b2l_data, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, + output logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, + + // Ports for "mem" interface + //AUTOGEN_BEGIN: Definition of memory ports + output logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + output logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + output logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + output logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + output logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + output logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + output logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + output logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + output logic [PORT_MEM_K_WIDTH-1:0] mem_k, + output logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + output logic [PORT_MEM_A_WIDTH-1:0] mem_a, + output logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + output logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + output logic [PORT_MEM_C_WIDTH-1:0] mem_c, + output logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + output logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + output logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + output logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + output logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + output logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + output logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + output logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + output logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + output logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + output logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + output logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + output logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + output logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + output logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + output logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + output logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + output logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + output logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + output logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + output logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + output logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + output logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + output logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + output logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + output logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + input logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + input logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + input logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + input logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + input logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + input logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + input logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + input logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + input logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n, + input logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + + input logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + input logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + generate + genvar port_i; + + for (port_i = 0; port_i < `_get_pin_count(UNUSED_MEM_PINS_PINLOC); ++port_i) + begin : unused_pin + altera_emif_arch_nf_buf_unused ub (.o(b2l_data[`_get_pin_index(UNUSED_MEM_PINS_PINLOC, port_i)])); + end + + for (port_i = 0; port_i < `_get_pin_count(UNUSED_DQS_BUSES_LANELOC); ++port_i) + begin : unused_dqs_bus + altera_emif_arch_nf_buf_unused ub0 (.o(b2t_dqs[`_get_pin_index(UNUSED_DQS_BUSES_LANELOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2t_dqsb[`_get_pin_index(UNUSED_DQS_BUSES_LANELOC, port_i)])); + end + + if (`_get_pin_count(PORT_MEM_CK_PINLOC) != 0) begin : gen_mem_ck + for (port_i = 0; port_i < PORT_MEM_CK_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_CK_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CK_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_CK_N_PINLOC, port_i)]), + .o(mem_ck[port_i]), + .obar(mem_ck_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_CK_PINLOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_CK_N_PINLOC, port_i)])); + end + end else begin : no_mem_ck + assign {mem_ck, mem_ck_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DK_PINLOC) != 0) begin : gen_mem_dk + for (port_i = 0; port_i < PORT_MEM_DK_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DK_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DK_N_PINLOC, port_i)]), + .o(mem_dk[port_i]), + .obar(mem_dk_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DK_PINLOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DK_N_PINLOC, port_i)])); + end + end else begin : no_mem_dk + assign {mem_dk, mem_dk_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DKA_PINLOC) != 0) begin : gen_mem_dka + for (port_i = 0; port_i < PORT_MEM_DKA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DKA_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DKA_N_PINLOC, port_i)]), + .o(mem_dka[port_i]), + .obar(mem_dka_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKA_PINLOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKA_N_PINLOC, port_i)])); + end + end else begin : no_mem_dka + assign {mem_dka, mem_dka_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_DKB_PINLOC) != 0) begin : gen_mem_dkb + for (port_i = 0; port_i < PORT_MEM_DKB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DKB_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_DKB_N_PINLOC, port_i)]), + .o(mem_dkb[port_i]), + .obar(mem_dkb_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKB_PINLOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DKB_N_PINLOC, port_i)])); + end + end else begin : no_mem_dkb + assign {mem_dkb, mem_dkb_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_K_PINLOC) != 0) begin : gen_mem_k + for (port_i = 0; port_i < PORT_MEM_K_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_df_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_CK_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_K_PINLOC, port_i)]), + .ibar(l2b_data[`_get_pin_index(PORT_MEM_K_N_PINLOC, port_i)]), + .o(mem_k[port_i]), + .obar(mem_k_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ub0 (.o(b2l_data[`_get_pin_index(PORT_MEM_K_PINLOC, port_i)])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_K_N_PINLOC, port_i)])); + end + end else begin : no_mem_k + assign {mem_k, mem_k_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_A_PINLOC) != 0) begin : gen_mem_a + for (port_i = 0; port_i < PORT_MEM_A_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_A_PINLOC, port_i)]), + .o(mem_a[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_A_PINLOC, port_i)])); + end + end else begin : no_mem_a + assign mem_a = '0; + end + + if (`_get_pin_count(PORT_MEM_BA_PINLOC) != 0) begin : gen_mem_ba + for (port_i = 0; port_i < PORT_MEM_BA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BA_PINLOC, port_i)]), + .o(mem_ba[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BA_PINLOC, port_i)])); + end + end else begin : no_mem_ba + assign mem_ba = '0; + end + + if (`_get_pin_count(PORT_MEM_BG_PINLOC) != 0) begin : gen_mem_bg + for (port_i = 0; port_i < PORT_MEM_BG_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BG_PINLOC, port_i)]), + .o(mem_bg[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BG_PINLOC, port_i)])); + end + end else begin : no_mem_bg + assign mem_bg = '0; + end + + if (`_get_pin_count(PORT_MEM_C_PINLOC) != 0) begin : gen_mem_c + for (port_i = 0; port_i < PORT_MEM_C_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_C_PINLOC, port_i)]), + .o(mem_c[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_C_PINLOC, port_i)])); + end + end else begin : no_mem_c + assign mem_c = '0; + end + + if (`_get_pin_count(PORT_MEM_CKE_PINLOC) != 0) begin : gen_mem_cke + for (port_i = 0; port_i < PORT_MEM_CKE_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CKE_PINLOC, port_i)]), + .o(mem_cke[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CKE_PINLOC, port_i)])); + end + end else begin : no_mem_cke + assign mem_cke = '0; + end + + if (`_get_pin_count(PORT_MEM_CS_N_PINLOC) != 0) begin : gen_mem_cs_n + for (port_i = 0; port_i < PORT_MEM_CS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CS_N_PINLOC, port_i)]), + .o(mem_cs_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CS_N_PINLOC, port_i)])); + end + end else begin : no_mem_cs_n + assign mem_cs_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RM_PINLOC) != 0) begin : gen_mem_rm + for (port_i = 0; port_i < PORT_MEM_RM_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RM_PINLOC, port_i)]), + .o(mem_rm[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RM_PINLOC, port_i)])); + end + end else begin : no_mem_rm + assign mem_rm = '1; + end + + if (`_get_pin_count(PORT_MEM_ODT_PINLOC) != 0) begin : gen_mem_odt + for (port_i = 0; port_i < PORT_MEM_ODT_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_ODT_PINLOC, port_i)]), + .o(mem_odt[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_ODT_PINLOC, port_i)])); + end + end else begin : no_mem_odt + assign mem_odt = '0; + end + + if (`_get_pin_count(PORT_MEM_RAS_N_PINLOC) != 0) begin : gen_mem_ras_n + for (port_i = 0; port_i < PORT_MEM_RAS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RAS_N_PINLOC, port_i)]), + .o(mem_ras_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RAS_N_PINLOC, port_i)])); + end + end else begin : no_mem_ras_n + assign mem_ras_n = '1; + end + + if (`_get_pin_count(PORT_MEM_CAS_N_PINLOC) != 0) begin : gen_mem_cas_n + for (port_i = 0; port_i < PORT_MEM_CAS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CAS_N_PINLOC, port_i)]), + .o(mem_cas_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CAS_N_PINLOC, port_i)])); + end + end else begin : no_mem_cas_n + assign mem_cas_n = '1; + end + + if (`_get_pin_count(PORT_MEM_WE_N_PINLOC) != 0) begin : gen_mem_we_n + for (port_i = 0; port_i < PORT_MEM_WE_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_WE_N_PINLOC, port_i)]), + .o(mem_we_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_WE_N_PINLOC, port_i)])); + end + end else begin : no_mem_we_n + assign mem_we_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RESET_N_PINLOC) != 0) begin : gen_mem_reset_n + for (port_i = 0; port_i < PORT_MEM_RESET_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(0) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RESET_N_PINLOC, port_i)]), + .o(mem_reset_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RESET_N_PINLOC, port_i)])); + end + end else begin : no_mem_reset_n + assign mem_reset_n = '1; + end + + if (`_get_pin_count(PORT_MEM_ACT_N_PINLOC) != 0) begin : gen_mem_act_n + for (port_i = 0; port_i < PORT_MEM_ACT_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_ACT_N_PINLOC, port_i)]), + .o(mem_act_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_ACT_N_PINLOC, port_i)])); + end + end else begin : no_mem_act_n + assign mem_act_n = '1; + end + + if (`_get_pin_count(PORT_MEM_PAR_PINLOC) != 0) begin : gen_mem_par + for (port_i = 0; port_i < PORT_MEM_PAR_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_PAR_PINLOC, port_i)]), + .o(mem_par[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_PAR_PINLOC, port_i)])); + end + end else begin : no_mem_par + assign mem_par = '0; + end + + if (`_get_pin_count(PORT_MEM_CA_PINLOC) != 0) begin : gen_mem_ca + for (port_i = 0; port_i < PORT_MEM_CA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CA_PINLOC, port_i)]), + .o(mem_ca[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CA_PINLOC, port_i)])); + end + end else begin : no_mem_ca + assign mem_ca = '0; + end + + if (`_get_pin_count(PORT_MEM_REF_N_PINLOC) != 0) begin : gen_mem_ref_n + for (port_i = 0; port_i < PORT_MEM_REF_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_REF_N_PINLOC, port_i)]), + .o(mem_ref_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_REF_N_PINLOC, port_i)])); + end + end else begin : no_mem_ref_n + assign mem_ref_n = '1; + end + + if (`_get_pin_count(PORT_MEM_WPS_N_PINLOC) != 0) begin : gen_mem_wps_n + for (port_i = 0; port_i < PORT_MEM_WPS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_WPS_N_PINLOC, port_i)]), + .o(mem_wps_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_WPS_N_PINLOC, port_i)])); + end + end else begin : no_mem_wps_n + assign mem_wps_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RPS_N_PINLOC) != 0) begin : gen_mem_rps_n + for (port_i = 0; port_i < PORT_MEM_RPS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RPS_N_PINLOC, port_i)]), + .o(mem_rps_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RPS_N_PINLOC, port_i)])); + end + end else begin : no_mem_rps_n + assign mem_rps_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0) begin : gen_mem_lda_n + for (port_i = 0; port_i < PORT_MEM_LDA_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LDA_N_PINLOC, port_i)]), + .o(mem_lda_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LDA_N_PINLOC, port_i)])); + end + end else begin : no_mem_lda_n + assign mem_lda_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : gen_mem_ldb_n + for (port_i = 0; port_i < PORT_MEM_LDB_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LDB_N_PINLOC, port_i)]), + .o(mem_ldb_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LDB_N_PINLOC, port_i)])); + end + end else begin : no_mem_ldb_n + assign mem_ldb_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0) begin : gen_mem_rwa_n + for (port_i = 0; port_i < PORT_MEM_RWA_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RWA_N_PINLOC, port_i)]), + .o(mem_rwa_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RWA_N_PINLOC, port_i)])); + end + end else begin : no_mem_rwa_n + assign mem_rwa_n = '1; + end + + if (`_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : gen_mem_rwb_n + for (port_i = 0; port_i < PORT_MEM_RWB_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_RWB_N_PINLOC, port_i)]), + .o(mem_rwb_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_RWB_N_PINLOC, port_i)])); + end + end else begin : no_mem_rwb_n + assign mem_rwb_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LBK0_N_PINLOC) != 0) begin : gen_mem_lbk0_n + for (port_i = 0; port_i < PORT_MEM_LBK0_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LBK0_N_PINLOC, port_i)]), + .o(mem_lbk0_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LBK0_N_PINLOC, port_i)])); + end + end else begin : no_mem_lbk0_n + assign mem_lbk0_n = '1; + end + + if (`_get_pin_count(PORT_MEM_LBK1_N_PINLOC) != 0) begin : gen_mem_lbk1_n + for (port_i = 0; port_i < PORT_MEM_LBK1_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_LBK1_N_PINLOC, port_i)]), + .o(mem_lbk1_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_LBK1_N_PINLOC, port_i)])); + end + end else begin : no_mem_lbk1_n + assign mem_lbk1_n = '1; + end + + if (`_get_pin_count(PORT_MEM_AP_PINLOC) != 0) begin : gen_mem_ap + for (port_i = 0; port_i < PORT_MEM_AP_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_AP_PINLOC, port_i)]), + .o(mem_ap[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_AP_PINLOC, port_i)])); + end + end else begin : no_mem_ap + assign mem_ap = '1; + end + + if (`_get_pin_count(PORT_MEM_AINV_PINLOC) != 0) begin : gen_mem_ainv + for (port_i = 0; port_i < PORT_MEM_AINV_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_AINV_PINLOC, port_i)]), + .o(mem_ainv[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_AINV_PINLOC, port_i)])); + end + end else begin : no_mem_ainv + assign mem_ainv = '1; + end + + if (`_get_pin_count(PORT_MEM_CFG_N_PINLOC) != 0) begin : gen_mem_cfg_n + for (port_i = 0; port_i < PORT_MEM_CFG_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_CFG_N_PINLOC, port_i)]), + .o(mem_cfg_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_CFG_N_PINLOC, port_i)])); + end + end else begin : no_mem_cfg_n + assign mem_cfg_n = '1; + end + + if (`_get_pin_count(PORT_MEM_DOFF_N_PINLOC) != 0) begin : gen_mem_doff_n + for (port_i = 0; port_i < PORT_MEM_DOFF_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_AC_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DOFF_N_PINLOC, port_i)]), + .o(mem_doff_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_DOFF_N_PINLOC, port_i)])); + end + end else begin : no_mem_doff_n + assign mem_doff_n = '1; + end + + if ((`_get_pin_count(PORT_MEM_DM_PINLOC) != 0) && (MEM_FORMAT_ENUM != "MEM_FORMAT_LRDIMM")) begin : gen_mem_dm + for (port_i = 0; port_i < PORT_MEM_DM_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_DM_PINLOC, port_i)]), + .o(mem_dm[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_DM_PINLOC, port_i)])); + end + end else begin : no_mem_dm + assign mem_dm = '0; + end + + if (`_get_pin_count(PORT_MEM_BWS_N_PINLOC) != 0) begin : gen_mem_bws_n + for (port_i = 0; port_i < PORT_MEM_BWS_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_BWS_N_PINLOC, port_i)]), + .o(mem_bws_n[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_BWS_N_PINLOC, port_i)])); + end + end else begin : no_mem_bws_n + assign mem_bws_n = '1; + end + + if (`_get_pin_count(PORT_MEM_D_PINLOC) != 0) begin : gen_mem_d + for (port_i = 0; port_i < PORT_MEM_D_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_o # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(l2b_data[`_get_pin_index(PORT_MEM_D_PINLOC, port_i)]), + .o(mem_d[port_i]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + altera_emif_arch_nf_buf_unused ubuf (.o(b2l_data[`_get_pin_index(PORT_MEM_D_PINLOC, port_i)])); + end + end else begin : no_mem_d + assign mem_d = '0; + end + + if (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0) begin : gen_mem_dq + for (port_i = 0; port_i < PORT_MEM_DQ_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dq[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQ_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dq + assign mem_dq = '0; + end + + if (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0) begin : gen_mem_dbi_n + for (port_i = 0; port_i < PORT_MEM_DBI_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dbi_n[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DBI_N_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dbi_n + assign mem_dbi_n = '0; + end + + if (`_get_pin_count(PORT_MEM_DQA_PINLOC) != 0) begin : gen_mem_dqa + for (port_i = 0; port_i < PORT_MEM_DQA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqa[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQA_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dqa + assign mem_dqa = '0; + end + + if (`_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : gen_mem_dqb + for (port_i = 0; port_i < PORT_MEM_DQB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqb[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQB_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dqb + assign mem_dqb = '0; + end + + if (`_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : gen_mem_dinva + for (port_i = 0; port_i < PORT_MEM_DINVA_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dinva[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DINVA_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dinva + assign mem_dinva = '0; + end + + if (`_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0) begin : gen_mem_dinvb + for (port_i = 0; port_i < PORT_MEM_DINVB_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_bdir_se # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dinvb[port_i]), + .ibuf_o(b2l_data[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DINVB_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end else begin : no_mem_dinvb + assign mem_dinvb = '0; + end + + if (`_get_pin_count(PORT_MEM_Q_PINLOC) != 0) begin : gen_mem_q + for (port_i = 0; port_i < PORT_MEM_Q_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_q[port_i]), + .o(b2l_data[`_get_pin_index(PORT_MEM_Q_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end + + if (`_get_pin_count(PORT_MEM_ALERT_N_PINLOC) != 0) begin : gen_mem_alert_n + for (port_i = 0; port_i < PORT_MEM_ALERT_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT((PROTOCOL_ENUM == "PROTOCOL_DDR4") ? 0 : PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_alert_n[port_i]), + .o(b2l_data[`_get_pin_index(PORT_MEM_ALERT_N_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end + + if (`_get_pin_count(PORT_MEM_PE_N_PINLOC) != 0) begin : gen_mem_pe_n + for (port_i = 0; port_i < PORT_MEM_PE_N_WIDTH; ++port_i) + begin : inst + altera_emif_arch_nf_buf_udir_se_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_pe_n[port_i]), + .o(b2l_data[`_get_pin_index(PORT_MEM_PE_N_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + end + end + + if (`_get_pin_count(PORT_MEM_DQS_PINLOC) != 0) begin : gen_mem_dqs + for (port_i = 0; port_i < PORT_MEM_DQS_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_nf_buf_bdir_df # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .io(mem_dqs[port_i]), + .iobar(mem_dqs_n[port_i]), + .ibuf_o(sig), + .obuf_i(l2b_data[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_ibar(l2b_data[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]), + .obuf_oe(l2b_oe[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_oebar(l2b_oe[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]), + .obuf_dtc(l2b_dtc[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)]), + .obuf_dtcbar(l2b_dtc[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)]), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + if (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") begin : gen_x4 + if ((`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) % PINS_PER_LANE) < (PINS_PER_LANE / 2)) begin : a + assign b2t_dqs[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + end else begin : b + assign b2t_dqsb[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + end + end else begin : gen_x8 + assign b2t_dqs[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i) / PINS_PER_LANE] = sig; + altera_emif_arch_nf_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i) / PINS_PER_LANE])); + end + + assign b2l_data[`_get_pin_index(PORT_MEM_DQS_PINLOC, port_i)] = sig; + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_DQS_N_PINLOC, port_i)])); + end + end else begin : no_mem_dqs + assign {mem_dqs, mem_dqs_n} = '0; + end + + if (`_get_pin_count(PORT_MEM_QK_PINLOC) != 0) begin : gen_mem_qk + for (port_i = 0; port_i < PORT_MEM_QK_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_nf_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qk[port_i]), + .ibar(mem_qk_n[port_i]), + .o(sig), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QK_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QK_PINLOC, port_i)] = sig; + + altera_emif_arch_nf_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QK_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QK_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_QKA_PINLOC) != 0) begin : gen_mem_qka + for (port_i = 0; port_i < PORT_MEM_QKA_WIDTH; ++port_i) + begin : inst + logic sig; + + altera_emif_arch_nf_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qka[port_i]), + .ibar(mem_qka_n[port_i]), + .o(sig), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QKA_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QKA_PINLOC, port_i)] = sig; + + altera_emif_arch_nf_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QKA_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QKA_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_QKB_PINLOC) != 0) begin : gen_mem_qkb + for (port_i = 0; port_i < PORT_MEM_QKB_WIDTH; ++port_i) + begin : inst + logic sig; + + // For QDR-IV, connect mem_qkb to the negative input of the differential buffer, + // and qkb_n to the positive input, to reverse the polarity of QKB. This is required + // for proper capture of DQB data. + altera_emif_arch_nf_buf_udir_df_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_qkb_n[port_i]), + .ibar(mem_qkb[port_i]), + .o(sig), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_QKB_PINLOC, port_i) / PINS_PER_LANE] = sig; + assign b2l_data[`_get_pin_index(PORT_MEM_QKB_PINLOC, port_i)] = sig; + + altera_emif_arch_nf_buf_unused ub0 (.o(b2t_dqsb[`_get_pin_index(PORT_MEM_QKB_N_PINLOC, port_i) / PINS_PER_LANE])); + altera_emif_arch_nf_buf_unused ub1 (.o(b2l_data[`_get_pin_index(PORT_MEM_QKB_N_PINLOC, port_i)])); + end + end + + if (`_get_pin_count(PORT_MEM_CQ_PINLOC) != 0) begin : gen_mem_cq + for (port_i = 0; port_i < PORT_MEM_CQ_WIDTH; ++port_i) + begin : inst + logic sig_p; + logic sig_n; + + altera_emif_arch_nf_buf_udir_cp_i # ( + .OCT_CONTROL_WIDTH(OCT_CONTROL_WIDTH), + .CALIBRATED_OCT(PHY_DATA_CALIBRATED_OCT) + ) b ( + .i(mem_cq[port_i]), + .ibar(mem_cq_n[port_i]), + .o(sig_p), + .obar(sig_n), + .oct_stc(oct_stc), + .oct_ptc(oct_ptc) + ); + + assign b2t_dqs[`_get_pin_index(PORT_MEM_CQ_PINLOC, port_i) / PINS_PER_LANE] = sig_p; + assign b2t_dqsb[`_get_pin_index(PORT_MEM_CQ_N_PINLOC, port_i) / PINS_PER_LANE] = sig_n; + + assign b2l_data[`_get_pin_index(PORT_MEM_CQ_PINLOC, port_i)] = sig_p; + assign b2l_data[`_get_pin_index(PORT_MEM_CQ_N_PINLOC, port_i)] = sig_n; + end + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_cal_counter.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_cal_counter.sv new file mode 100644 index 000000000000..c80b67846f2c --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_cal_counter.sv @@ -0,0 +1,126 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +module altera_emif_arch_nf_cal_counter ( + input logic pll_ref_clk_int, + input logic global_reset_n_int, + input logic afi_cal_in_progress +); + timeunit 1ps; + timeprecision 1ps; + + logic done; + logic [31:0] clk_counter; + + logic reset_n_sync; + logic cal_in_progress_sync; + + altera_std_synchronizer_nocut + inst_sync_reset_n ( + .clk (pll_ref_clk_int), + .reset_n (1'b1), + .din (global_reset_n_int), + .dout (reset_n_sync) + ); + + altera_std_synchronizer_nocut + inst_sync_cal_in_progress ( + .clk (pll_ref_clk_int), + .reset_n (1'b1), + .din (afi_cal_in_progress), + .dout (cal_in_progress_sync) + ); + + enum { + INIT, + IDLE, + COUNT_CAL, + STOP + } counter_state; + + assign done = ((counter_state == STOP) ? 1'b1 : 1'b0); + + always_ff @(posedge pll_ref_clk_int) begin + if(reset_n_sync == 1'b0) begin + counter_state <= INIT; + end + else begin + case(counter_state) + INIT: + begin + clk_counter <= 32'h0; + counter_state <= IDLE; + end + + IDLE: + begin + if (cal_in_progress_sync == 1'b1) + begin + counter_state <= COUNT_CAL; + end + end + + COUNT_CAL: + begin + clk_counter[31:0] <= clk_counter[31:0] + 32'h0000_0001; + + if (cal_in_progress_sync == 1'b0) + begin + counter_state <= STOP; + end + end + + STOP: + begin + counter_state <= STOP; + end + + default: + begin + counter_state <= INIT; + end + endcase + end + end + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALC"), + .probe_width (33), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_counter_issp ( + .probe ({done, clk_counter[31:0]}) + ); +`endif + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_core_clks_rsts.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_core_clks_rsts.sv new file mode 100644 index 000000000000..e1be3e33c503 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_core_clks_rsts.sv @@ -0,0 +1,748 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation and wiring of the core clock/reset signals. +// +/////////////////////////////////////////////////////////////////////////////// + +// altera message_off 10036 + + module altera_emif_arch_nf_core_clks_rsts #( + parameter PHY_CONFIG_ENUM = "", + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter IS_VID = 0, + parameter PHY_PING_PONG_EN = 0, + parameter C2P_P2C_CLK_RATIO = 1, + parameter USER_CLK_RATIO = 1, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 32, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 32, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 1, + parameter DIAG_SYNTH_FOR_SIM = 1, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 1 +) ( + // For a master interface, the PLL ref clock and the global reset signal + // come from an external source from user logic, via the following ports. + // For slave interfaces, they come from the master via the sharing interface. + // The connectivity ensures that all interfaces in a master/slave + // configuration share the same ref clock and global reset, which is + // one of the requirements for core-clock sharing. + input logic pll_ref_clk, + input logic global_reset_n, + + // This signal is connected to the SmartVID controller, and signals EMIF to + // only calibrate after SmartVID is done voltage calibration. + input logic vid_cal_done_persist, + + // For a master interface, core clocks come from the clock phase alignment + // block of the current interface, via the following ports. Note that the + // CPA block also expects feedback signals after the clock signals have + // propagated through core clock networks. + // For slave interfaces, the core clock signals come from the master + // via the sharing interface. + input logic [1:0] core_clks_from_cpa_pri, + input logic [1:0] core_clks_locked_cpa_pri, + output logic [1:0] core_clks_fb_to_cpa_pri, + + input logic [1:0] core_clks_from_cpa_sec, + input logic [1:0] core_clks_locked_cpa_sec, + output logic [1:0] core_clks_fb_to_cpa_sec, + + // Since CPA clocks are generated from VCOPH clocks, which aren't stable + // until after duty-cycle-correction circuitry has stablized, we must gate + // core until using the follwing signal from the sequencer. + input logic dcc_stable, + + // PLL lock signal + input logic pll_locked, + + // PLL c-counters + input logic [8:0] pll_c_counters, + + // For a master interface, the core reset signal is generated by synchronizing + // the deassertion of the async reset coming from the hard PHY via the following + // port, to the core clock signal. + // For slave interfaces, the core reset signal comes from the master + // via the sharing interface. + input logic phy_reset_n, + + // The following is the master/slave sharing interfaces. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // The following are the actual pll ref clock and global reset signals that + // will be used internally by the rest of the IP. + output logic pll_ref_clk_int, + output logic global_reset_n_int, + + // The following are all the possible core clock/reset signals. + // afi_* only exists in PHY-only mode (or if soft controller is used). + // emif_usr_* only exists if hard memory controller is used. + output logic afi_clk, + output logic afi_half_clk, + output logic afi_reset_n, + + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n, + + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic emif_usr_reset_n_sec, + + // The calibration slave core clock domain is used by core logic that serves + // as Avalon slaves for the sequencer CPU. The clock comes directly from PLL C-counter + // instead of from the CPA. + output logic cal_slave_clk, + output logic cal_slave_reset_n, + + // The calibration master core clock domain is used by core logic that serves + // as Avalon masters for the sequencer calbus. The clock comes directly from PLL C-counter + // instead of from the CPA. + output logic cal_master_clk, + output logic cal_master_reset_n, + + // DFT + output logic [PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // This is the length of the core reset synchronizer chain. + // It is set higher than the length of the reset chain + // in the periphery (5+), to avoid the core from getting out of reset + // earlier than the hard PHY/sequencer/controller. + // This is for extra safety, but isn't actually necessary, because + // soft logic must either wait for the hard controller's assertion of + // the ready signal, or, in case the hard controller isn't used, + // for the sequencer to assert the afi_cal_success, prior to accessing + // the hard circuitries. The minimal requirement for reset deassertion + // is a guarantee that the core clock is stable. + localparam CPA_RESET_SYNC_LENGTH = 7; + + // Reset synchronizer chain length for PLL-based core clocks + localparam PLL_RESET_SYNC_LENGTH = 3; + + ///////////////////////////////////////////////////////////// + // Get signals to/from the master/slave sharing interface. + logic pll_locked_int; + logic phy_reset_n_int; + logic dcc_stable_int; + logic counter_lock; + logic cpa_lock_pri; + logic cpa_lock_sec; + logic async_reset_n_pri; + logic async_reset_n_sec; + logic issp_reset_n; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("TGR"), + .probe_width (0), + .source_width (1), + .source_initial_value ("1"), + .enable_metastability ("NO") + ) core_reset_n_issp ( + .source (issp_reset_n) + ); +`else + assign issp_reset_n = 1'b1; +`endif + + assign async_reset_n_pri = (DIAG_USE_CPA_LOCK ? cpa_lock_pri : counter_lock) & dcc_stable_int & issp_reset_n; + assign async_reset_n_sec = (DIAG_USE_CPA_LOCK ? cpa_lock_sec : counter_lock) & dcc_stable_int & issp_reset_n; + + logic pll_ref_clk_slave_in; + logic pll_locked_slave_in; + logic global_reset_n_slave_in; + logic cpa_lock_pri_slave_in; + logic cpa_lock_sec_slave_in; + logic phy_reset_n_slave_in; + logic dcc_stable_slave_in; + logic afi_clk_slave_in; + logic afi_half_clk_slave_in; + logic afi_reset_n_pre_reg_slave_in; + logic afi_reset_n_pre_reg; + logic counter_lock_slave_in; + logic emif_usr_clk_slave_in; + logic emif_usr_half_clk_slave_in; + logic emif_usr_reset_n_pri_pre_reg_slave_in; + logic emif_usr_reset_n_pri_pre_reg; + logic emif_usr_clk_sec_slave_in; + logic emif_usr_half_clk_sec_slave_in; + logic emif_usr_reset_n_sec_pre_reg_slave_in; + logic emif_usr_reset_n_sec_pre_reg; + logic cal_slave_clk_slave_in; + logic cal_master_clk_slave_in; + logic cal_master_reset_n_slave_in; + + ///////////////////////////////////////////////////////////// + // Generate connectivity for PLL ref clk and reset. + generate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : slave + assign pll_ref_clk_int = pll_ref_clk_slave_in; + assign pll_locked_int = pll_locked_slave_in; + assign global_reset_n_int = global_reset_n_slave_in; + assign phy_reset_n_int = phy_reset_n_slave_in; + assign dcc_stable_int = dcc_stable_slave_in; + + assign pll_ref_clk_slave_in = clks_sharing_slave_in[0]; + assign global_reset_n_slave_in = clks_sharing_slave_in[1]; + assign phy_reset_n_slave_in = clks_sharing_slave_in[2]; + assign cpa_lock_pri_slave_in = clks_sharing_slave_in[3]; + assign afi_clk_slave_in = clks_sharing_slave_in[4]; + assign afi_half_clk_slave_in = clks_sharing_slave_in[5]; + assign afi_reset_n_pre_reg_slave_in = clks_sharing_slave_in[6]; + assign counter_lock_slave_in = clks_sharing_slave_in[7]; + assign emif_usr_clk_slave_in = clks_sharing_slave_in[8]; + assign cal_slave_clk_slave_in = clks_sharing_slave_in[9]; + assign emif_usr_reset_n_pri_pre_reg_slave_in = clks_sharing_slave_in[10]; + assign emif_usr_half_clk_slave_in = clks_sharing_slave_in[11]; + assign pll_locked_slave_in = clks_sharing_slave_in[12]; + assign cpa_lock_sec_slave_in = clks_sharing_slave_in[13]; + assign emif_usr_clk_sec_slave_in = clks_sharing_slave_in[14]; + assign emif_usr_reset_n_sec_pre_reg_slave_in = clks_sharing_slave_in[15]; + assign emif_usr_half_clk_sec_slave_in = clks_sharing_slave_in[16]; + assign cal_master_clk_slave_in = clks_sharing_slave_in[17]; + assign cal_master_reset_n_slave_in = clks_sharing_slave_in[18]; + assign dcc_stable_slave_in = clks_sharing_slave_in[19]; + + assign clks_sharing_master_out = '0; + end else + begin : master + + logic probe_global_reset_n; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("RSTN"), + .probe_width (0), + .source_width (1), + .source_initial_value ("1"), + .enable_metastability ("NO") + ) global_reset_n_issp ( + .source (probe_global_reset_n) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PALP"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cpa_lock_pri_issp ( + .probe (cpa_lock_pri) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PALS"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cpa_lock_sec_issp ( + .probe (cpa_lock_sec) + ); +`else + assign probe_global_reset_n = 1'b1; +`endif + + assign phy_reset_n_int = phy_reset_n; + assign pll_ref_clk_int = pll_ref_clk; + assign pll_locked_int = pll_locked; + assign dcc_stable_int = dcc_stable; + + if (IS_VID) begin : use_vid_persist_reset + assign global_reset_n_int = global_reset_n & probe_global_reset_n & vid_cal_done_persist; + end else begin : default_reset + assign global_reset_n_int = global_reset_n & probe_global_reset_n; + end + + assign clks_sharing_master_out[0] = pll_ref_clk_int; + assign clks_sharing_master_out[1] = global_reset_n_int; + assign clks_sharing_master_out[2] = phy_reset_n_int; + assign clks_sharing_master_out[3] = cpa_lock_pri; + assign clks_sharing_master_out[4] = afi_clk; + assign clks_sharing_master_out[5] = afi_half_clk; + assign clks_sharing_master_out[6] = afi_reset_n_pre_reg; + assign clks_sharing_master_out[7] = counter_lock; + assign clks_sharing_master_out[8] = emif_usr_clk; + assign clks_sharing_master_out[9] = cal_slave_clk; + assign clks_sharing_master_out[10] = emif_usr_reset_n_pri_pre_reg; + assign clks_sharing_master_out[11] = emif_usr_half_clk; + assign clks_sharing_master_out[12] = pll_locked; + assign clks_sharing_master_out[13] = cpa_lock_sec; + assign clks_sharing_master_out[14] = emif_usr_clk_sec; + assign clks_sharing_master_out[15] = emif_usr_reset_n_sec_pre_reg; + assign clks_sharing_master_out[16] = emif_usr_half_clk_sec; + assign clks_sharing_master_out[17] = cal_master_clk; + assign clks_sharing_master_out[18] = cal_master_reset_n; + assign clks_sharing_master_out[19] = dcc_stable_int; + + assign clks_sharing_master_out[PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:20] = '0; + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate core clock lock signal if CPA lock isn't used + generate + if (DIAG_USE_CPA_LOCK) + begin : use_cpa_lock + assign counter_lock = 1'b0; + end + else + begin : use_counter_lock + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : counter_lock_gen_slave + assign counter_lock = counter_lock_slave_in; + end else + begin : counter_lock_gen_master + + // Synchronize PLL lock signal to PLL ref clock domain. + // This may not be necessary but we do it for extra safety. + logic pll_ref_clk_reset_n; + logic pll_ref_clk_reset_n_sync_r; + logic pll_ref_clk_reset_n_sync_rr; + logic pll_ref_clk_reset_n_sync_rrr; + + assign pll_ref_clk_reset_n = pll_ref_clk_reset_n_sync_rrr; + + always_ff @(posedge pll_ref_clk_int or negedge pll_locked_int) begin + if (~pll_locked_int) begin + pll_ref_clk_reset_n_sync_r <= 1'b0; + pll_ref_clk_reset_n_sync_rr <= 1'b0; + pll_ref_clk_reset_n_sync_rrr <= 1'b0; + end else begin + pll_ref_clk_reset_n_sync_r <= 1'b1; + pll_ref_clk_reset_n_sync_rr <= pll_ref_clk_reset_n_sync_r; + pll_ref_clk_reset_n_sync_rrr <= pll_ref_clk_reset_n_sync_rr; + end + end + + // CPA takes ~50k core clock cycles to lock. Obviously we can't use a potentially + // unstable core clock to clock the counter. We need to use the ref clock instead. + // The fastest legal ref clock can run at the same rate as core clock, so we simply + // count 64k PLL ref clock cycles. + logic [16:0] cpa_count_to_lock; + + // The following is evaluated for simulation. Don't wait too long during simulation. + // synthesis translate_off + localparam COUNTER_LOCK_EXP = 9; + // synthesis translate_on + + // The following is evaluated for synthesis. Don't wait too long when DIAG_SYNTH_FOR_SIM enabled. + // synthesis read_comments_as_HDL on + // localparam COUNTER_LOCK_EXP = DIAG_SYNTH_FOR_SIM ? 9 : 16; + // synthesis read_comments_as_HDL off + + always_ff @(posedge pll_ref_clk_int or negedge pll_ref_clk_reset_n) begin + if (~pll_ref_clk_reset_n) begin + cpa_count_to_lock <= '0; + counter_lock <= 1'b0; + end else begin + if (~cpa_count_to_lock[COUNTER_LOCK_EXP]) begin + cpa_count_to_lock <= cpa_count_to_lock + 1'b1; + end + counter_lock <= cpa_count_to_lock[COUNTER_LOCK_EXP]; + end + end + end + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate CPA-based core clock signals + logic [1:0] core_clks_from_cpa_pri_buffered; + logic [1:0] core_clks_from_cpa_sec_buffered; + + ///////////////////////////////////////////////////////////// + // Assign signals for DFT + assign dft_core_clk_locked = DIAG_USE_CPA_LOCK ? core_clks_locked_cpa_pri : {2{counter_lock}}; + assign dft_core_clk_buf_out = core_clks_from_cpa_pri_buffered; + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") + begin : clk_gen_hmc + + // If HMC is used, there's no AFI clock + assign afi_half_clk = 1'b0; + assign afi_clk = 1'b0; + + if (USER_CLK_RATIO == 2 && C2P_P2C_CLK_RATIO == 4) + begin : bridge_2x + // For 2x-bridge mode, expose two core clocks: + // 0) A half-rate clock (i.e. emif_usr_clk) + // 1) A quarter-rate clock (i.e. emif_usr_half_clk) + + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {emif_usr_half_clk_slave_in, emif_usr_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = {emif_usr_half_clk_sec_slave_in, emif_usr_clk_sec_slave_in}; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_clk_buf ( + .inclk (core_clks_from_cpa_pri[0]), + .outclk (core_clks_from_cpa_pri_buffered[0]), + .ena (1'b1), + .enaout () + ); + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_half_clk_buf ( + .inclk (core_clks_from_cpa_pri[1]), + .outclk (core_clks_from_cpa_pri_buffered[1]), + .ena (1'b1), + .enaout () + ); + + assign cpa_lock_pri = core_clks_locked_cpa_pri[0] & core_clks_locked_cpa_pri[1]; + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + + if (PHY_PING_PONG_EN) begin : gen_sec_clk + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_clk_buf ( + .inclk (core_clks_from_cpa_sec[0]), + .outclk (core_clks_from_cpa_sec_buffered[0]), + .ena (1'b1), + .enaout () + ); + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_half_clk_buf ( + .inclk (core_clks_from_cpa_sec[1]), + .outclk (core_clks_from_cpa_sec_buffered[1]), + .ena (1'b1), + .enaout () + ); + + assign cpa_lock_sec = core_clks_locked_cpa_sec[0] & core_clks_locked_cpa_sec[1]; + assign core_clks_fb_to_cpa_sec = core_clks_from_cpa_sec_buffered; + + end else begin : non_pp + assign cpa_lock_sec = 1'b0; + assign core_clks_fb_to_cpa_sec = '0; + assign core_clks_from_cpa_sec_buffered = '0; + end + end + + assign emif_usr_clk = core_clks_from_cpa_pri_buffered[0]; + assign emif_usr_half_clk = core_clks_from_cpa_pri_buffered[1]; + assign emif_usr_clk_sec = core_clks_from_cpa_sec_buffered[0]; + assign emif_usr_half_clk_sec = core_clks_from_cpa_sec_buffered[1]; + + end else + begin : hr_qr + + // For half/quarter-rate, expose one core clock (i.e. emif_usr_clk) + // running at the user-requested rate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {emif_usr_half_clk_slave_in, emif_usr_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = {emif_usr_half_clk_sec_slave_in, emif_usr_clk_sec_slave_in}; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_clk_buf ( + .inclk (core_clks_from_cpa_pri[0]), + .outclk (core_clks_from_cpa_pri_buffered[0]), + .ena (1'b1), + .enaout () + ); + + if (DIAG_CPA_OUT_1_EN) + begin : force_cpa_out_1_en + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_extra_clk_buf ( + .inclk (core_clks_from_cpa_pri[1]), + .outclk (core_clks_from_cpa_pri_buffered[1]), + .ena (1'b1), + .enaout () + ); + assign cpa_lock_pri = core_clks_locked_cpa_pri[0] & core_clks_locked_cpa_pri[1]; + + end else begin : normal + assign core_clks_from_cpa_pri_buffered[1] = core_clks_from_cpa_pri_buffered[0]; + assign cpa_lock_pri = core_clks_locked_cpa_pri[0]; + end + + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + + if (PHY_PING_PONG_EN) begin : gen_sec_clk + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) emif_usr_clk_buf ( + .inclk (core_clks_from_cpa_sec[0]), + .outclk (core_clks_from_cpa_sec_buffered[0]), + .ena (1'b1), + .enaout () + ); + + assign cpa_lock_sec = core_clks_locked_cpa_sec[0]; + assign core_clks_fb_to_cpa_sec = core_clks_from_cpa_sec_buffered; + assign core_clks_from_cpa_sec_buffered[1] = core_clks_from_cpa_sec_buffered[0]; + + end else begin : non_pp + assign cpa_lock_sec = 1'b0; + assign core_clks_fb_to_cpa_sec = '0; + assign core_clks_from_cpa_sec_buffered = '0; + end + end + + assign emif_usr_clk = core_clks_from_cpa_pri_buffered[0]; + assign emif_usr_half_clk = core_clks_from_cpa_pri_buffered[1]; + assign emif_usr_clk_sec = core_clks_from_cpa_sec_buffered[0]; + assign emif_usr_half_clk_sec = core_clks_from_cpa_sec_buffered[1]; + + end + end else + begin : clk_gen_non_hmc + + // If HMC isn't used, there's no emif_usr_* clocks + assign emif_usr_clk = 1'b0; + assign emif_usr_half_clk = 1'b0; + assign emif_usr_clk_sec = 1'b0; + assign emif_usr_half_clk_sec = 1'b0; + + // Always expose both afi_clk and afi_half_clk + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : clk_gen_slave + assign core_clks_from_cpa_pri_buffered = {afi_clk_slave_in, afi_half_clk_slave_in}; + assign core_clks_from_cpa_sec_buffered = '0; + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = cpa_lock_pri_slave_in; + assign cpa_lock_sec = cpa_lock_sec_slave_in; + end else + begin : clk_gen_master + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) afi_half_clk_buf ( + .inclk (core_clks_from_cpa_pri[0]), + .outclk (core_clks_from_cpa_pri_buffered[0]), + .ena (1'b1), + .enaout () + ); + + twentynm_clkena # ( + .clock_type ("GLOBAL CLOCK") + ) afi_clk_buf ( + .inclk (core_clks_from_cpa_pri[1]), + .outclk (core_clks_from_cpa_pri_buffered[1]), + .ena (1'b1), + .enaout () + ); + + assign core_clks_fb_to_cpa_pri = core_clks_from_cpa_pri_buffered; + assign core_clks_fb_to_cpa_sec = '0; + assign cpa_lock_pri = core_clks_locked_cpa_pri[0] & core_clks_locked_cpa_pri[1]; + assign cpa_lock_sec = 1'b0; + end + + assign afi_half_clk = core_clks_from_cpa_pri_buffered[0]; + assign afi_clk = core_clks_from_cpa_pri_buffered[1]; + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate core reset signals for CPA-based core clocks + logic sync_clk_pri; + logic sync_clk_sec; + logic reset_sync_pri_pre_reg; + logic reset_sync_sec_pre_reg; + + // Every interface flops the synchronized reset signal locally, + // to avoid recovery/removal timing issue due to high fanout. + // The flop is marked to prevent from being optimized away. + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic reset_sync_pri_sdc_anchor /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin + if (~async_reset_n_pri) begin + reset_sync_pri_sdc_anchor <= '0; + end else begin + reset_sync_pri_sdc_anchor <= reset_sync_pri_pre_reg; + end + end + + logic reset_sync_sec_sdc_anchor_ext; + generate + if (PHY_PING_PONG_EN) begin : pp + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic reset_sync_sec_sdc_anchor /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + always_ff @(posedge sync_clk_sec or negedge async_reset_n_sec) begin + if (~async_reset_n_sec) begin + reset_sync_sec_sdc_anchor <= '0; + end else begin + reset_sync_sec_sdc_anchor <= reset_sync_sec_pre_reg; + end + end + assign reset_sync_sec_sdc_anchor_ext = reset_sync_sec_sdc_anchor; + end else begin : no_pp + assign reset_sync_sec_sdc_anchor_ext = 1'b0; + end + endgenerate + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") + begin : reset_gen_hmc + // Use the slower clock to synchronize the reset to ease + // recovery/removal in the slow clock domain. + assign sync_clk_pri = (USER_CLK_RATIO == 2 && C2P_P2C_CLK_RATIO == 4 ? emif_usr_half_clk : emif_usr_clk); + assign sync_clk_sec = (USER_CLK_RATIO == 2 && C2P_P2C_CLK_RATIO == 4 ? emif_usr_half_clk_sec : emif_usr_clk_sec); + assign emif_usr_reset_n_pri_pre_reg = reset_sync_pri_pre_reg; + assign emif_usr_reset_n_sec_pre_reg = reset_sync_sec_pre_reg; + assign emif_usr_reset_n = reset_sync_pri_sdc_anchor; + assign emif_usr_reset_n_sec = reset_sync_sec_sdc_anchor_ext; + assign afi_reset_n_pre_reg = 1'b0; + assign afi_reset_n = 1'b0; + end else + begin: reset_gen_non_hmc + // afi_half_clk is the slower clock compared to afi_clk. Use the + // slower clock to synchronize the reset to ease recovery/removal + // in the slow clock domain. + assign sync_clk_pri = afi_half_clk; + assign sync_clk_sec = 1'b0; + assign afi_reset_n_pre_reg = reset_sync_pri_pre_reg; + assign afi_reset_n = reset_sync_pri_sdc_anchor; + assign emif_usr_reset_n_pri_pre_reg = 1'b0; + assign emif_usr_reset_n = 1'b0; + assign emif_usr_reset_n_sec_pre_reg = 1'b0; + assign emif_usr_reset_n_sec = 1'b0; + end + + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : reset_gen_slave + // The master exposes a synchronized reset signal for the slaves + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") begin + assign reset_sync_pri_pre_reg = emif_usr_reset_n_pri_pre_reg_slave_in; + assign reset_sync_sec_pre_reg = emif_usr_reset_n_sec_pre_reg_slave_in; + end else begin + assign reset_sync_pri_pre_reg = afi_reset_n_pre_reg_slave_in; + assign reset_sync_sec_pre_reg = 1'b0; + end + end else + begin : reset_gen_master + + // Synchronize reset deassertion to core clock + logic [CPA_RESET_SYNC_LENGTH-1:0] reset_sync_pri; + always_ff @(posedge sync_clk_pri or negedge async_reset_n_pri) begin + if (~async_reset_n_pri) begin + reset_sync_pri <= '0; + end else begin + reset_sync_pri[0] <= 1'b1; + reset_sync_pri[CPA_RESET_SYNC_LENGTH-1:1] <= reset_sync_pri[CPA_RESET_SYNC_LENGTH-2:0]; + end + end + assign reset_sync_pri_pre_reg = reset_sync_pri[CPA_RESET_SYNC_LENGTH-1]; + + if (PHY_PING_PONG_EN) begin : gen_sec_rst_sync + logic [CPA_RESET_SYNC_LENGTH-1:0] reset_sync_sec; + always_ff @(posedge sync_clk_sec or negedge async_reset_n_sec) begin + if (~async_reset_n_sec) begin + reset_sync_sec <= '0; + end else begin + reset_sync_sec[0] <= 1'b1; + reset_sync_sec[CPA_RESET_SYNC_LENGTH-1:1] <= reset_sync_sec[CPA_RESET_SYNC_LENGTH-2:0]; + end + end + assign reset_sync_sec_pre_reg = reset_sync_sec[CPA_RESET_SYNC_LENGTH-1]; + end else begin : no_pp + assign reset_sync_sec_pre_reg = 1'b0; + end + end + endgenerate + + ///////////////////////////////////////////////////////////// + // Generate PLL-based core clock and reset signals + generate + if (PHY_CORE_CLKS_SHARING_ENUM == "CORE_CLKS_SHARING_SLAVE") + begin : pll_clk_gen_slave + assign cal_slave_clk = cal_slave_clk_slave_in; + assign cal_master_clk = cal_master_clk_slave_in; + assign cal_master_reset_n = cal_master_reset_n_slave_in; + end else + begin : pll_clk_gen_master + assign cal_slave_clk = pll_c_counters[3]; + assign cal_master_clk = pll_c_counters[4]; + + logic [PLL_RESET_SYNC_LENGTH-1:0] reset_sync; + + assign cal_master_reset_n = reset_sync[PLL_RESET_SYNC_LENGTH-1]; + + always_ff @(posedge cal_master_clk or negedge pll_locked) begin + if (~pll_locked) begin + reset_sync <= '0; + end else begin + reset_sync[0] <= 1'b1; + reset_sync[PLL_RESET_SYNC_LENGTH-1:1] <= reset_sync[PLL_RESET_SYNC_LENGTH-2:0]; + end + end + end + + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic [PLL_RESET_SYNC_LENGTH-1:0] per_if_cal_slave_reset_sync /* synthesis dont_merge */; + + assign cal_slave_reset_n = per_if_cal_slave_reset_sync[PLL_RESET_SYNC_LENGTH-1]; + + always_ff @(posedge cal_slave_clk or negedge pll_locked_int) begin + if (~pll_locked_int) begin + per_if_cal_slave_reset_sync <= '0; + end else begin + per_if_cal_slave_reset_sync[0] <= 1'b1; + per_if_cal_slave_reset_sync[PLL_RESET_SYNC_LENGTH-1:1] <= per_if_cal_slave_reset_sync[PLL_RESET_SYNC_LENGTH-2:0]; + end + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_amm_data_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_amm_data_if.sv new file mode 100644 index 000000000000..629ceab8d714 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_amm_data_if.sv @@ -0,0 +1,202 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the data interfaces through which +// soft logic interacts with the Avalon MM port of the HMC +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _core2l_data(_port_i, _phase_i) core2l_data\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 8) + _phase_i] + +`define _core2l_datamask(_port_i, _phase_i) core2l_data\ + [`_get_tile(WM_PINLOC, _port_i)]\ + [`_get_lane(WM_PINLOC, _port_i)]\ + [(`_get_pin(WM_PINLOC, _port_i) * 8) + _phase_i] + +`define _l2core_data(_port_i, _phase_i) l2core_data\ + [`_get_tile(RD_PINLOC, _port_i)]\ + [`_get_lane(RD_PINLOC, _port_i)]\ + [(`_get_pin(RD_PINLOC, _port_i) * 8) + _phase_i] + +`define _unused_core2l_data(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +module altera_emif_arch_nf_hmc_amm_data_if #( + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + + // Definition of port widths for "ctrl_amm" interface (auto-generated) + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + + // Pin indexes of data signals + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + + // Pin indexes of write data mask signals + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0 +) ( + // Signals between core and data lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + + // AMM data signals between core and data lanes when HMC is used + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0, + + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1 +); + timeunit 1ns; + timeprecision 1ps; + + localparam RD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_Q_PINLOC); + localparam WD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_D_PINLOC); + localparam WM_PINLOC = (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0 ? PORT_MEM_DM_PINLOC : (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0 ? PORT_MEM_DBI_N_PINLOC : PORT_MEM_BWS_N_PINLOC)); + + localparam NUM_RD_PINS = `_get_pin_count(RD_PINLOC); + localparam NUM_WD_PINS = `_get_pin_count(WD_PINLOC); + localparam NUM_WM_PINS = `_get_pin_count(WM_PINLOC); + + localparam NUM_RD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_RD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WM_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WM_PINS / NUM_OF_HMC_PORTS) : 0; + + localparam NUM_OF_RD_PHASES_PER_HMC_PORT = PORT_CTRL_AMM_RDATA_WIDTH / NUM_RD_PINS_PER_HMC_PORT; + localparam NUM_OF_WD_PHASES_PER_HMC_PORT = PORT_CTRL_AMM_WDATA_WIDTH / NUM_WD_PINS_PER_HMC_PORT; + localparam NUM_OF_WM_PHASES_PER_HMC_PORT = (NUM_WM_PINS == 0) ? 0 : (PORT_CTRL_AMM_BYTEEN_WIDTH / NUM_WM_PINS_PER_HMC_PORT); + + assign core2l_oe = '1; + + generate + genvar port_i; + genvar phase_i; + genvar pin_i; + + // Map Avalon-MM writedata signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port + for (phase_i = 0; phase_i < NUM_OF_WD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WD_PINS_PER_HMC_PORT) begin + assign `_core2l_data(port_i, phase_i) = amm_writedata_0[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_data(port_i, phase_i) = amm_writedata_1[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i - NUM_WD_PINS_PER_HMC_PORT]; + end + end + end + + // Map Avalon-MM byte-enable signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port + for (phase_i = 0; phase_i < NUM_OF_WM_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WM_PINS_PER_HMC_PORT) begin + assign `_core2l_datamask(port_i, phase_i) = amm_byteenable_0[phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_datamask(port_i, phase_i) = amm_byteenable_1[phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i - NUM_WM_PINS_PER_HMC_PORT]; + end + end + end + + // Map lanes' read data bus to Avalon-MM readdata signal + for (port_i = 0; port_i < NUM_RD_PINS; ++port_i) + begin : rd_port + for (phase_i = 0; phase_i < NUM_OF_RD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_RD_PINS_PER_HMC_PORT) begin + assign amm_readdata_0[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i] = `_l2core_data(port_i, phase_i); + end else begin + assign amm_readdata_1[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i - NUM_RD_PINS_PER_HMC_PORT] = `_l2core_data(port_i, phase_i); + end + end + end + + // Tie off unused phases for core2l_data for the write data pins + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port_unused + for (phase_i = NUM_OF_WD_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_data(port_i, phase_i) = 1'b0; + end + end + + // Tie off unused phases for core2l_data for the write data mask pins + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port_unused + for (phase_i = NUM_OF_WM_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_datamask(port_i, phase_i) = 1'b0; + end + end + + // Tie off core2l_data for unused connections + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) + assign `_unused_core2l_data(pin_i) = '0; + end + + // Tie off the read data ports if they're not used + if (NUM_OF_HMC_PORTS < 1) begin + assign amm_readdata_0 = '0; + end + + if (NUM_OF_HMC_PORTS < 2) begin + assign amm_readdata_1 = '0; + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_ast_data_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_ast_data_if.sv new file mode 100644 index 000000000000..983aeb46d93a --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_ast_data_if.sv @@ -0,0 +1,206 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the data interfaces through which +// soft logic interacts with the Avalon ST port of the HMC +// +/////////////////////////////////////////////////////////////////////////////// + +`define _get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _get_tile(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _get_lane(_loc, _port_i) ( (`_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _get_pin(_loc, _port_i) ( `_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _core2l_data(_port_i, _phase_i) core2l_data\ + [`_get_tile(WD_PINLOC, _port_i)]\ + [`_get_lane(WD_PINLOC, _port_i)]\ + [(`_get_pin(WD_PINLOC, _port_i) * 8) + _phase_i] + +`define _core2l_datamask(_port_i, _phase_i) core2l_data\ + [`_get_tile(WM_PINLOC, _port_i)]\ + [`_get_lane(WM_PINLOC, _port_i)]\ + [(`_get_pin(WM_PINLOC, _port_i) * 8) + _phase_i] + +`define _l2core_data(_port_i, _phase_i) l2core_data\ + [`_get_tile(RD_PINLOC, _port_i)]\ + [`_get_lane(RD_PINLOC, _port_i)]\ + [(`_get_pin(RD_PINLOC, _port_i) * 8) + _phase_i] + +`define _unused_core2l_data(_pin_i) core2l_data\ + [_pin_i / (PINS_PER_LANE * LANES_PER_TILE)]\ + [(_pin_i / PINS_PER_LANE) % LANES_PER_TILE]\ + [((_pin_i % PINS_PER_LANE) * 8) +: 8] + +module altera_emif_arch_nf_hmc_ast_data_if #( + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + + // Definition of port widths for "ctrl_ast_wr" interface (auto-generated) + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_rd" interface (auto-generated) + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + + // Pin indexes of data signals + parameter PORT_MEM_D_PINLOC = 10'b0000000000, + parameter PORT_MEM_DQ_PINLOC = 10'b0000000000, + parameter PORT_MEM_Q_PINLOC = 10'b0000000000, + + // Pin indexes of write data mask signals + parameter PORT_MEM_DM_PINLOC = 10'b0000000000, + parameter PORT_MEM_DBI_N_PINLOC = 10'b0000000000, + parameter PORT_MEM_BWS_N_PINLOC = 10'b0000000000, + + // Parameter indicating the core-2-lane connection of a pin is actually driven + parameter PINS_C2L_DRIVEN = 1'b0 +) ( + // Signals between core and data lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + + // AST data signals between core and data lanes when HMC is used + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_0, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_0, + + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_1, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_1 +); + timeunit 1ns; + timeprecision 1ps; + + localparam RD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_Q_PINLOC); + localparam WD_PINLOC = (`_get_pin_count(PORT_MEM_DQ_PINLOC) != 0 ? PORT_MEM_DQ_PINLOC : PORT_MEM_D_PINLOC); + localparam WM_PINLOC = (`_get_pin_count(PORT_MEM_DM_PINLOC) != 0 ? PORT_MEM_DM_PINLOC : (`_get_pin_count(PORT_MEM_DBI_N_PINLOC) != 0 ? PORT_MEM_DBI_N_PINLOC : PORT_MEM_BWS_N_PINLOC)); + + localparam NUM_RD_PINS = `_get_pin_count(RD_PINLOC); + localparam NUM_WD_PINS = `_get_pin_count(WD_PINLOC); + localparam NUM_WM_PINS = `_get_pin_count(WM_PINLOC); + + // The write data bus includes both data (LSBs) and data mask (MSBs). Here we calculate the width of both. + localparam NUM_OF_AST_REAL_WR_DATA_WIDTH = PORT_CTRL_AST_RD_DATA_WIDTH; + localparam NUM_OF_AST_BYTE_EN_WIDTH = PORT_CTRL_AST_WR_DATA_WIDTH - NUM_OF_AST_REAL_WR_DATA_WIDTH; + + localparam NUM_RD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_RD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WD_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WD_PINS / NUM_OF_HMC_PORTS) : 0; + localparam NUM_WM_PINS_PER_HMC_PORT = (NUM_OF_HMC_PORTS > 0) ? (NUM_WM_PINS / NUM_OF_HMC_PORTS) : 0; + + localparam NUM_OF_RD_PHASES_PER_HMC_PORT = PORT_CTRL_AST_RD_DATA_WIDTH / NUM_RD_PINS_PER_HMC_PORT; + localparam NUM_OF_WD_PHASES_PER_HMC_PORT = NUM_OF_AST_REAL_WR_DATA_WIDTH / NUM_WD_PINS_PER_HMC_PORT; + localparam NUM_OF_WM_PHASES_PER_HMC_PORT = (NUM_WM_PINS == 0) ? 0 : (NUM_OF_AST_BYTE_EN_WIDTH / NUM_WM_PINS_PER_HMC_PORT); + + assign core2l_oe = '1; + + generate + genvar port_i; + genvar phase_i; + genvar pin_i; + + // Map Avalon-ST writedata signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port + for (phase_i = 0; phase_i < NUM_OF_WD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WD_PINS_PER_HMC_PORT) begin + assign `_core2l_data(port_i, phase_i) = ast_wr_data_0[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i]; + end else begin + assign `_core2l_data(port_i, phase_i) = ast_wr_data_1[phase_i * NUM_WD_PINS_PER_HMC_PORT + port_i - NUM_WD_PINS_PER_HMC_PORT]; + end + end + end + + // Map Avalon-ST byte-enable signal to lanes' write data bus + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port + for (phase_i = 0; phase_i < NUM_OF_WM_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_WM_PINS_PER_HMC_PORT) begin + assign `_core2l_datamask(port_i, phase_i) = ast_wr_data_0[(NUM_OF_WD_PHASES_PER_HMC_PORT * NUM_WD_PINS_PER_HMC_PORT) + (phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i)]; + end else begin + assign `_core2l_datamask(port_i, phase_i) = ast_wr_data_1[(NUM_OF_WD_PHASES_PER_HMC_PORT * NUM_WD_PINS_PER_HMC_PORT) + (phase_i * NUM_WM_PINS_PER_HMC_PORT + port_i - NUM_WM_PINS_PER_HMC_PORT)]; + end + end + end + + // Map lanes' read data bus to Avalon-ST readdata signal + for (port_i = 0; port_i < NUM_RD_PINS; ++port_i) + begin : rd_port + for (phase_i = 0; phase_i < NUM_OF_RD_PHASES_PER_HMC_PORT; ++phase_i) + begin : phase + if (port_i < NUM_RD_PINS_PER_HMC_PORT) begin + assign ast_rd_data_0[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i] = `_l2core_data(port_i, phase_i); + end else begin + assign ast_rd_data_1[phase_i * NUM_RD_PINS_PER_HMC_PORT + port_i - NUM_RD_PINS_PER_HMC_PORT] = `_l2core_data(port_i, phase_i); + end + end + end + + // Tie off unused phases for core2l_data for the write data pins + for (port_i = 0; port_i < NUM_WD_PINS; ++port_i) + begin : wd_port_unused + for (phase_i = NUM_OF_WD_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_data(port_i, phase_i) = 1'b0; + end + end + + // Tie off unused phases for core2l_data for the write data mask pins + for (port_i = 0; port_i < NUM_WM_PINS; ++port_i) + begin : wm_port_unused + for (phase_i = NUM_OF_WM_PHASES_PER_HMC_PORT; phase_i < 8; ++phase_i) + begin : unused_phase + assign `_core2l_datamask(port_i, phase_i) = 1'b0; + end + end + + // Tie off core2l_data for unused connections + for (pin_i = 0; pin_i < (NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE); ++pin_i) + begin : non_c2l_pin + if (PINS_C2L_DRIVEN[pin_i] == 1'b0) + assign `_unused_core2l_data(pin_i) = '0; + end + + // Tie off the read data ports if they're not used + if (NUM_OF_HMC_PORTS < 1) begin + assign ast_rd_data_0 = '0; + end + + if (NUM_OF_HMC_PORTS < 2) begin + assign ast_rd_data_1 = '0; + end + endgenerate +endmodule + + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_avl_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_avl_if.sv new file mode 100644 index 000000000000..c7d073d8f0e6 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_avl_if.sv @@ -0,0 +1,257 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the Avalon interfaces through which +// soft logic interacts with the Hard Memory Controller inside the tile. +// The tile WYSIWYG blocks collapse the individual Avalon signals into big +// buses. This module re-wires the big buses into proper Avalon interfaces. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_hmc_avl_if #( + + // Parameters describing HMC front-end ports + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + + // Parameters describing lanes/tiles + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + + // Definition of port widths for "ctrl_ast_cmd" interface (auto-generated) + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_amm" interface (auto-generated) + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1 + +) ( + // Collapsed Avalon signals going into/out of tiles + output logic [59:0] core2ctl_avl_0, + output core2ctl_avl_rd_data_ready_0, + input logic ctl2core_avl_cmd_ready_0, + output logic core2l_wr_data_vld_ast_0, + output logic core2l_rd_data_rdy_ast_0, + + output logic [59:0] core2ctl_avl_1, + output core2ctl_avl_rd_data_ready_1, + input logic ctl2core_avl_cmd_ready_1, + output logic core2l_wr_data_vld_ast_1, + output logic core2l_rd_data_rdy_ast_1, + + // Avalon interfaces between core and lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast, + + // Ports for "ctrl_user_priority" interface + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + + // Controller auto-precharge request signals + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + + // Ports for "ctrl_ast_cmd" interfaces (auto-generated) + output logic ast_cmd_ready_0, + input logic ast_cmd_valid_0, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_0, + + output logic ast_cmd_ready_1, + input logic ast_cmd_valid_1, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_1, + + // Ports for "ctrl_ast_wr" interfaces (auto-generated) + output logic ast_wr_ready_0, + input logic ast_wr_valid_0, + + output logic ast_wr_ready_1, + input logic ast_wr_valid_1, + + // Ports for "ctrl_ast_rd" interfaces (auto-generated) + input logic ast_rd_ready_0, + output logic ast_rd_valid_0, + + input logic ast_rd_ready_1, + output logic ast_rd_valid_1, + + // Ports for "ctrl_amm" interfaces (auto-generated) + input logic amm_write_0, + input logic amm_read_0, + output logic amm_ready_0, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_0, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + + input logic amm_write_1, + input logic amm_read_1, + output logic amm_ready_1, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_1, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1 +); + timeunit 1ns; + timeprecision 1ps; + + + generate + + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM") begin : amm + + logic [31:0] amm_address_padded_0; + logic [31:0] amm_address_padded_1; + logic [7:0] amm_burstcount_padded_0; + logic [7:0] amm_burstcount_padded_1; + + if (PORT_CTRL_AMM_ADDRESS_WIDTH >= 32) begin + assign amm_address_padded_0 = amm_address_0; + assign amm_address_padded_1 = amm_address_1; + end else begin + assign amm_address_padded_0 = {'0, amm_address_0}; + assign amm_address_padded_1 = {'0, amm_address_1}; + end + + if (PORT_CTRL_AMM_BCOUNT_WIDTH >= 8) begin + assign amm_burstcount_padded_0 = amm_burstcount_0; + assign amm_burstcount_padded_1 = amm_burstcount_1; + end else begin + assign amm_burstcount_padded_0 = {'0, amm_burstcount_0}; + assign amm_burstcount_padded_1 = {'0, amm_burstcount_1}; + end + + // Port 0 + assign core2ctl_avl_0[0] = amm_read_0; + assign core2ctl_avl_0[1] = amm_write_0; + assign core2ctl_avl_0[33:2] = amm_address_padded_0; + assign core2ctl_avl_0[41:34] = amm_burstcount_padded_0; + assign core2ctl_avl_0[42] = ctrl_user_priority_hi_0; + assign core2ctl_avl_0[43] = ctrl_auto_precharge_req_0; + assign core2ctl_avl_0[44] = '0; + assign core2ctl_avl_0[57:45] = '0; + assign core2ctl_avl_0[58] = '0; + assign core2ctl_avl_0[59] = '0; + assign amm_ready_0 = ctl2core_avl_cmd_ready_0; + + assign amm_readdatavalid_0 = l2core_rd_data_vld_avl0[PRI_AC_TILE_INDEX][PRI_HMC_DBC_SHADOW_LANE_INDEX]; + + assign ast_cmd_ready_0 = '0; + assign ast_wr_ready_0 = '0; + assign ast_rd_valid_0 = '0; + assign core2ctl_avl_rd_data_ready_0 = '1; + assign core2l_wr_data_vld_ast_0 = '0; + assign core2l_rd_data_rdy_ast_0 = '1; + + // Port 1 + assign core2ctl_avl_1[0] = amm_read_1; + assign core2ctl_avl_1[1] = amm_write_1; + assign core2ctl_avl_1[33:2] = amm_address_padded_1; + assign core2ctl_avl_1[41:34] = amm_burstcount_padded_1; + assign core2ctl_avl_1[42] = ctrl_user_priority_hi_1; + assign core2ctl_avl_1[43] = ctrl_auto_precharge_req_1; + assign core2ctl_avl_1[44] = '0; + assign core2ctl_avl_1[57:45] = '0; + assign core2ctl_avl_1[58] = '0; + assign core2ctl_avl_1[59] = '0; + assign amm_ready_1 = ctl2core_avl_cmd_ready_1; + assign amm_readdatavalid_1 = l2core_rd_data_vld_avl0[SEC_RDATA_TILE_INDEX][SEC_RDATA_LANE_INDEX]; + assign ast_cmd_ready_1 = '0; + assign ast_wr_ready_1 = '0; + assign ast_rd_valid_1 = '0; + assign core2ctl_avl_rd_data_ready_1 = '1; + assign core2l_wr_data_vld_ast_1 = '0; + assign core2l_rd_data_rdy_ast_1 = '1; + + end else if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_ST") begin : ast + + // Port 0 + assign core2ctl_avl_0[57:0] = ast_cmd_data_0; + assign core2ctl_avl_0[58] = ast_cmd_valid_0; + assign core2ctl_avl_0[59] = ast_wr_valid_0; + assign ast_cmd_ready_0 = ctl2core_avl_cmd_ready_0; + + assign ast_wr_ready_0 = l2core_wr_data_rdy_ast[PRI_AC_TILE_INDEX][PRI_HMC_DBC_SHADOW_LANE_INDEX]; + assign ast_rd_valid_0 = l2core_rd_data_vld_avl0[PRI_AC_TILE_INDEX][PRI_HMC_DBC_SHADOW_LANE_INDEX]; + + assign core2ctl_avl_rd_data_ready_0 = ast_rd_ready_0; + assign amm_ready_0 = '0; + assign amm_readdatavalid_0 = '0; + assign core2l_wr_data_vld_ast_0 = ast_wr_valid_0; + assign core2l_rd_data_rdy_ast_0 = ast_rd_ready_0; + + // Port 1 + assign core2ctl_avl_1[57:0] = ast_cmd_data_1; + assign core2ctl_avl_1[58] = ast_cmd_valid_1; + assign core2ctl_avl_1[59] = ast_wr_valid_1; + assign ast_cmd_ready_1 = ctl2core_avl_cmd_ready_1; + assign ast_wr_ready_1 = l2core_wr_data_rdy_ast[SEC_WDATA_TILE_INDEX][SEC_WDATA_LANE_INDEX]; + assign ast_rd_valid_1 = l2core_rd_data_vld_avl0[SEC_RDATA_TILE_INDEX][SEC_RDATA_LANE_INDEX]; + assign core2ctl_avl_rd_data_ready_1 = ast_rd_ready_1; + assign amm_ready_1 = '0; + assign amm_readdatavalid_1 = '0; + assign core2l_wr_data_vld_ast_1 = ast_wr_valid_1; + assign core2l_rd_data_rdy_ast_1 = ast_rd_ready_1; + + end else begin : no_hmc + + // Port 0 + assign core2ctl_avl_0 = '0; + assign ast_cmd_ready_0 = '0; + assign ast_wr_ready_0 = '0; + assign ast_rd_valid_0 = '0; + assign core2ctl_avl_rd_data_ready_0 = '1; + assign amm_ready_0 = '0; + assign amm_readdatavalid_0 = '0; + assign core2l_wr_data_vld_ast_0 = '0; + assign core2l_rd_data_rdy_ast_0 = '1; + + // Port 1 + assign core2ctl_avl_1 = '0; + assign ast_cmd_ready_1 = '0; + assign ast_wr_ready_1 = '0; + assign ast_rd_valid_1 = '0; + assign core2ctl_avl_rd_data_ready_1 = '1; + assign amm_ready_1 = '0; + assign amm_readdatavalid_1 = '0; + assign core2l_wr_data_vld_ast_1 = '0; + assign core2l_rd_data_rdy_ast_1 = '1; + end + endgenerate +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_mmr_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_mmr_if.sv new file mode 100644 index 000000000000..d255c86b8eed --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_mmr_if.sv @@ -0,0 +1,99 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the MMR Avalon interfaces through which +// soft logic interacts with the Hard Memory Controller inside the tile. +// The tile WYSIWYG blocks collapse the individual Avalon signals into big +// buses. This module re-wires the big buses into proper Avalon interfaces. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_hmc_mmr_if #( + + // Definition of port widths for "ctrl_mmr" interface (auto-generated) + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1 +) ( + // MMR signals between core and HMC + input logic [33:0] ctl2core_mmr_0, + output logic [50:0] core2ctl_mmr_0, + input logic [33:0] ctl2core_mmr_1, + output logic [50:0] core2ctl_mmr_1, + + // Ports for "ctrl_mmr" interface (auto-generated) + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_0, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_0, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_0, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_1, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_1, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_1, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1 +); + timeunit 1ns; + timeprecision 1ps; + + assign core2ctl_mmr_0[9:0] = mmr_slave_address_0; + assign core2ctl_mmr_0[13:10] = 'b0; + assign core2ctl_mmr_0[45:14] = mmr_slave_writedata_0; + assign core2ctl_mmr_0[46] = mmr_slave_write_0; + assign core2ctl_mmr_0[47] = mmr_slave_read_0; + assign core2ctl_mmr_0[49:48] = mmr_slave_burstcount_0; + assign core2ctl_mmr_0[50] = mmr_slave_beginbursttransfer_0; + + assign mmr_slave_readdata_0 = ctl2core_mmr_0[31:0]; + assign mmr_slave_readdatavalid_0 = ctl2core_mmr_0[32]; + assign mmr_slave_waitrequest_0 = ctl2core_mmr_0[33]; + + assign core2ctl_mmr_1[9:0] = mmr_slave_address_1; + assign core2ctl_mmr_1[13:10] = 'b0; + assign core2ctl_mmr_1[45:14] = mmr_slave_writedata_1; + assign core2ctl_mmr_1[46] = mmr_slave_write_1; + assign core2ctl_mmr_1[47] = mmr_slave_read_1; + assign core2ctl_mmr_1[49:48] = mmr_slave_burstcount_1; + assign core2ctl_mmr_1[50] = mmr_slave_beginbursttransfer_1; + + assign mmr_slave_readdata_1 = ctl2core_mmr_1[31:0]; + assign mmr_slave_readdatavalid_1 = ctl2core_mmr_1[32]; + assign mmr_slave_waitrequest_1 = ctl2core_mmr_1[33]; + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_sideband_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_sideband_if.sv new file mode 100644 index 000000000000..14803b1bc768 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hmc_sideband_if.sv @@ -0,0 +1,169 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing the controller sideband interfaces +// through which soft logic interacts with the Hard Memory Controller. +// The tile WYSIWYG blocks collapse the individual sideband signals into big +// buses. This module re-logics the big buses into proper interfaces. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_hmc_sideband_if #( + + // Parameters describing lanes/tiles + parameter PHY_PING_PONG_EN = 0, + parameter LANES_PER_TILE = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter PRI_AC_TILE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + + // Definition of port widths for "ctrl_user_refresh" interface + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 1, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 1, + + // Definition of port widths for "ctrl_self_refresh" interface + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 1, + + // Definition describing ECC + parameter PRI_HMC_CFG_ENABLE_ECC = "disable", + parameter SEC_HMC_CFG_ENABLE_ECC = "disable", + + // Definition of port widths for "ctrl_ecc" interface + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1 + +) ( + // Collapsed sideband signals going into/out of tiles + output logic [41:0] core2ctl_sideband_0, + input logic [13:0] ctl2core_sideband_0, + output logic [41:0] core2ctl_sideband_1, + input logic [13:0] ctl2core_sideband_1, + + // Additional ECC signals going into/out of lanes + output logic [12:0] core2l_wr_ecc_info_0, + output logic [12:0] core2l_wr_ecc_info_1, + input logic [12:0] ctl2core_avl_rdata_id_0, + input logic [12:0] ctl2core_avl_rdata_id_1, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc, + + // Ports for "ctrl_user_refresh" interface + input logic [PORT_CTRL_USER_REFRESH_REQ_WIDTH-1:0] ctrl_user_refresh_req, + input logic [PORT_CTRL_USER_REFRESH_BANK_WIDTH-1:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + + // Ports for "ctrl_self_refresh" interface + input logic [PORT_CTRL_SELF_REFRESH_REQ_WIDTH-1:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + + // Ports for "ctrl_will_refresh" interface + output logic ctrl_will_refresh, + + // Ports for "ctrl_deep_power_down" interface + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + + // Ports for "ctrl_power_down" interface + output logic ctrl_power_down_ack, + + // Ports for "ctrl_zq_cal" interface + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_0, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_0, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_0, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_0, + + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_1, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_1, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_1, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_1 + +); + timeunit 1ns; + timeprecision 1ps; + + assign core2ctl_sideband_0[3:0] = ctrl_user_refresh_req; + assign core2ctl_sideband_0[19:4] = ctrl_user_refresh_bank; + assign core2ctl_sideband_0[20] = ctrl_deep_power_down_req; + assign core2ctl_sideband_0[24:21] = ctrl_self_refresh_req; + assign core2ctl_sideband_0[25] = ctrl_zq_cal_long_req; + assign core2ctl_sideband_0[26] = ctrl_zq_cal_short_req; + + assign ctrl_user_refresh_ack = ctl2core_sideband_0[6]; + assign ctrl_deep_power_down_ack = ctl2core_sideband_0[7]; + assign ctrl_power_down_ack = ctl2core_sideband_0[8]; + assign ctrl_self_refresh_ack = ctl2core_sideband_0[9]; + assign ctrl_zq_cal_ack = ctl2core_sideband_0[10]; + assign ctrl_will_refresh = ctl2core_sideband_0[13]; + + assign core2ctl_sideband_1[3:0] = '0; + assign core2ctl_sideband_1[19:4] = '0; + assign core2ctl_sideband_1[20] = '0; + assign core2ctl_sideband_1[24:21] = '0; + assign core2ctl_sideband_1[25] = '0; + assign core2ctl_sideband_1[26] = '0; + + + assign ctrl_ecc_read_info_0 = ctl2core_sideband_0[2:0]; + assign ctrl_ecc_cmd_info_0 = ctl2core_sideband_0[5:3]; + assign ctrl_ecc_idle_0 = ctl2core_sideband_0[12]; + assign ctrl_ecc_rdata_id_0 = ctl2core_avl_rdata_id_0; + + assign ctrl_ecc_wr_pointer_info_0 = l2core_wb_pointer_for_ecc[PRI_AC_TILE_INDEX][PRI_HMC_DBC_SHADOW_LANE_INDEX]; + + assign core2ctl_sideband_0[41:27] = ctrl_ecc_write_info_0; + assign core2l_wr_ecc_info_0 = ctrl_ecc_write_info_0[14:2]; + + assign ctrl_ecc_read_info_1 = ctl2core_sideband_1[2:0]; + assign ctrl_ecc_cmd_info_1 = ctl2core_sideband_1[5:3]; + assign ctrl_ecc_idle_1 = ctl2core_sideband_1[12]; + assign ctrl_ecc_rdata_id_1 = ctl2core_avl_rdata_id_1; + assign ctrl_ecc_wr_pointer_info_1 = l2core_wb_pointer_for_ecc[SEC_WDATA_TILE_INDEX][SEC_WDATA_LANE_INDEX]; + assign core2ctl_sideband_1[41:27] = ctrl_ecc_write_info_1; + assign core2l_wr_ecc_info_1 = ctrl_ecc_write_info_1[14:2]; +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hps_clks_rsts.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hps_clks_rsts.sv new file mode 100644 index 000000000000..2cc750cbddbe --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_hps_clks_rsts.sv @@ -0,0 +1,171 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation and wiring of the HPS clock/reset signals. +// +/////////////////////////////////////////////////////////////////////////////// + +// altera message_off 10036 + + module altera_emif_arch_nf_hps_clks_rsts #( + parameter IS_VID = 0, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 32, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 32, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 1, + parameter PHY_USERMODE_OCT = 0, + parameter PHY_HPS_ENABLE_EARLY_RELEASE = 0 +) ( + // For a master interface, the PLL ref clock and the global reset signal + // come from an external source from user logic, via the following ports. + // For slave interfaces, they come from the master via the sharing interface. + // The connectivity ensures that all interfaces in a master/slave + // configuration share the same ref clock and global reset, which is + // one of the requirements for core-clock sharing. + input logic pll_ref_clk, + input logic global_reset_n, + + // This signal is connected to the SmartVID controller, and signals EMIF to + // only calibrate after SmartVID is done voltage calibration. + input logic vid_cal_done_persist, + + // For a master interface, the core reset signal is generated by synchronizing + // the deassertion of the async reset coming from the hard PHY via the following + // port, to the core clock signal. + // For slave interfaces, the core reset signal comes from the master + // via the sharing interface. + input logic phy_reset_n, + + // Feedback signals to CPA via the core + output logic [1:0] core_clks_fb_to_cpa_pri, + output logic [1:0] core_clks_fb_to_cpa_sec, + + // The following is the master/slave sharing interfaces. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // The following are the actual pll ref clock and global reset signals that + // will be used internally by the rest of the IP. + output logic pll_ref_clk_int, + output logic global_reset_n_int, + + // The following are all the possible core clock/reset signals. + // afi_* only exists in PHY-only mode (or if soft controller is used). + // emif_usr_* only exists if hard memory controller is used. + output logic afi_clk, + output logic afi_half_clk, + output logic afi_reset_n, + + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n, + + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic emif_usr_reset_n_sec, + + // The calibration slave core clock domain is used by core logic that serves + // as Avalon slaves for the sequencer CPU. The clock comes directly from PLL C-counter + // instead of from the CPA. + output logic cal_slave_clk, + output logic cal_slave_reset_n, + + // The calibration master core clock domain is used by core logic that serves + // as Avalon masters for the sequencer calbus. The clock comes directly from PLL C-counter + // instead of from the CPA. + output logic cal_master_clk, + output logic cal_master_reset_n, + + // The following signal is driven by the HPS to hard reset the EMIF PHY + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + + // DFT + output logic [PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // HPS clocks are not modeled for simulation. + // Also in HPS mode we do not generate clocks that are visible to user logic. + assign pll_ref_clk_int = pll_ref_clk; + + generate + if (IS_VID) begin : use_vid_persist_reset + // Create register to capture path false path internal to EMIF block + reg vid_cal_done_persist_reg; + always_ff @(posedge pll_ref_clk) begin + vid_cal_done_persist_reg <= vid_cal_done_persist; + end + if (PHY_USERMODE_OCT == 1) begin : gen_hps_reset + assign global_reset_n_int = global_reset_n & hps_to_emif_gp[1] & vid_cal_done_persist_reg; + end else begin : gen_nohps_reset + assign global_reset_n_int = global_reset_n & vid_cal_done_persist_reg; + end + end else begin : default_reset + if (PHY_USERMODE_OCT == 1) begin : gen_hps_reset + assign global_reset_n_int = global_reset_n & hps_to_emif_gp[1]; + end else begin : gen_nohps_reset + if (PHY_HPS_ENABLE_EARLY_RELEASE == 1) begin : gen_nohps_early_reset + assign global_reset_n_int = 1'b1; + end else begin : gen_nohps_normal_reset + assign global_reset_n_int = global_reset_n; + end + end + end + endgenerate + + assign afi_clk = 1'b0; + assign afi_half_clk = 1'b0; + assign afi_reset_n = 1'b1; + + assign emif_usr_clk = 1'b0; + assign emif_usr_half_clk = 1'b0; + assign emif_usr_reset_n = 1'b1; + + assign emif_usr_clk_sec = 1'b0; + assign emif_usr_half_clk_sec = 1'b0; + assign emif_usr_reset_n_sec = 1'b1; + + assign core_clks_fb_to_cpa_pri = '0; + assign core_clks_fb_to_cpa_sec = '0; + assign clks_sharing_master_out = '0; + + assign cal_master_clk = 1'b0; + assign cal_master_reset_n = 1'b1; + + assign cal_slave_clk = 1'b0; + assign cal_slave_reset_n = 1'b1; + + assign dft_core_clk_locked = '0; + assign dft_core_clk_buf_out = '0; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles.sv new file mode 100644 index 000000000000..2ae38aedc107 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles.sv @@ -0,0 +1,1723 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// This module instantiates one or more x48 I/O tiles (along with +// the necessary x12 I/O lanes) that are required to build as single EMIF. +// +/////////////////////////////////////////////////////////////////////////////// + +// Simple max/min +`define _get_max(_i, _j) ( (_i) > (_j) ? (_i) : (_j) ) +`define _get_min(_i, _j) ( (_i) < (_j) ? (_i) : (_j) ) + +// Index to signal buses used to implement a daisy chain of +// (L0->L1->T0->L2->L3)->(L0->L1->T1->L2->L3)->... +`define _get_chain_index_for_tile(_tile_i) ( _tile_i * (LANES_PER_TILE + 1) + 2 ) + +`define _get_chain_index_for_lane(_tile_i, _lane_i) ( (_lane_i < 2) ? (_tile_i * (LANES_PER_TILE + 1) + _lane_i) : ( \ + (_tile_i * (LANES_PER_TILE + 1) + _lane_i + 1 )) ) + +// Index to signal buses used to implement a daisy chain of +// (L0->L1->L2->L3)->(L0->L1->L2->L3)->... +`define _get_broadcast_chain_index(_tile_i, _lane_i) ( _tile_i * LANES_PER_TILE + _lane_i ) + +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) + +`define _get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_OCT_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i)] ) + +`define _get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) ( PINS_RATE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) +`define _get_pin_ddr_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) == PIN_RATE_DDR ? "mode_ddr" : "mode_sdr" ) + +`define _get_pin_usage(_tile_i, _lane_i, _pin_i) ( PINS_USAGE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) + +`define _get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) ( PINS_WDB[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 3 +: 3] ) +`define _get_pin_wdb_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_AC_CORE ? "ac_core" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_AC_HMC ? "ac_hmc" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQS_WDB_MODE ? "dqs_wdb_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQS_MODE ? "dqs_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DM_WDB_MODE ? "dm_wdb_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DM_MODE ? "dm_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQ_WDB_MODE ? "dq_wdb_mode" : ( \ + "dq_mode" )))))))) + +`define _get_pin_db_in_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_IN_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_db_out_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_OUT_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_db_oe_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_OE_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_invert_wr(_tile_i, _lane_i, _pin_i) ( PINS_INVERT_WR[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_invert_oe(_tile_i, _lane_i, _pin_i) ( PINS_INVERT_OE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_ac_hmc_data_override_ena(_tile_i, _lane_i, _pin_i) ( PINS_AC_HMC_DATA_OVERRIDE_ENA[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_oct_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_STATIC_OFF ? "static_off" : ( \ + `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_DYNAMIC ? "dynamic" : ( \ + "dynamic" ))) + +`define _get_pin_gpio_or_ddr(_tile_i, _lane_i, _pin_i) ( PINS_GPIO_MODE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "gpio" : "ddr" ) + +`define _get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_DATA_IN_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 3 +: 3] ) + +`define _get_pin_data_in_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DISABLED ? "disabled" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_SSTL_IN ? "sstl_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_LOOPBACK_IN ? "loopback_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_XOR_LOOPBACK_IN ? "xor_loopback_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN ? "differential_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT ? "differential_in_avl_out" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_X12_OUT ? "differential_in_x12_out" : ( \ + "differential_in_avl_x12_out" )))))))) + +// Given the tile and lane index of a lane, returns the index of the AC tile controlling +// this lane. For non-ping-pong, return value is always PRI_AC_TILE_INDEX. +// For ping-pong, return SEC_AC_TILE_INDEX for all tiles below tile at SEC_AC_TILE_INDEX, +// and for lane 2 and 3 of tile SEC_AC_TILE_INDEX; return PRI_AC_TILE_INDEX otherwise. +// This assumption must be consistent with the logical pin placement strategy in hwtcl. +`define _get_ac_tile_index(_tile_i, _lane_i) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? SEC_AC_TILE_INDEX : PRI_AC_TILE_INDEX ) + +// _get_dbc_pipe_lat returns: current_distance_from_ac_tile +// which is the same as: abs(_tile_i - AC_TILE_INDEX) +`define _get_dbc_pipe_lat(_tile_i, _lane_i) ( (_tile_i > `_get_ac_tile_index(_tile_i, _lane_i)) ? (_tile_i - `_get_ac_tile_index(_tile_i, _lane_i)) : \ + (`_get_ac_tile_index(_tile_i, _lane_i) - _tile_i) ) + +// _get_db_ptr_pipe_depth returns: max_distance_from_ac_tile - current_distance_from_ac_tile +// which is the same as: max(NUM_OF_RTL_TILES - PRI_AC_TILE_INDEX - 1, PRI_AC_TILE_INDEX) - abs(_tile_i - PRI_AC_TILE_INDEX) +// In PingPong PHY case, the same calculation method applies but as if all data lanes are +// controlled by primary AC tile, except that the lanes actually controlled by secondary AC tile +// have the value added by 1. +`define _get_max_distance_from_ac_tile ( `_get_max( (NUM_OF_RTL_TILES - PRI_AC_TILE_INDEX - 1), PRI_AC_TILE_INDEX ) ) + +// Note that the maximum db_seq_rd_en_full_pipeline value supported by h/w is 4. In Ping-Pong PHY, +// applying the normal formulas can result in a value of 5 for the secondary lanes whenever the max +// distance from ac tile is 3. When this happens, we normalize by reducing both db_seq_rd_en_full_pipeline +// and pipeline_depth by 1. This is always safe to do because by construction, a ping-pong interface +// must have more tiles below the primary HMC tile than above, and so nominal pipeline_depth is always +// bigger than 1 (i.e. won't become negative after the subtraction). The simplest way to implement this +// is by capping max_distance_from_ac_tile to 2. +`define _get_max_distance_from_ac_tile_capped ( PHY_PING_PONG_EN ? `_get_min(2, `_get_max_distance_from_ac_tile) : `_get_max_distance_from_ac_tile ) + +`define _get_curr_distance_from_ac_tile(_tile_i) ( (_tile_i > PRI_AC_TILE_INDEX) ? (_tile_i - PRI_AC_TILE_INDEX) : (PRI_AC_TILE_INDEX - _tile_i) ) +`define _get_db_ptr_pipe_depth_pri(_tile_i) ( `_get_max_distance_from_ac_tile_capped - `_get_curr_distance_from_ac_tile(_tile_i) ) +`define _get_db_ptr_pipe_depth_sec(_tile_i) ( `_get_db_ptr_pipe_depth_pri(_tile_i) + 1) +`define _get_db_ptr_pipe_depth(_tile_i, _lane_i) ( `_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? `_get_db_ptr_pipe_depth_pri(_tile_i) : `_get_db_ptr_pipe_depth_sec(_tile_i)) + +// _get_db_seq_rd_en_full_pipeline: for HMC: max_distance_from_ac_tile + 1 +// for SMC: db_ptr_pipe_depth + 1 +// In PingPong PHY case, the same calculation method applies but as if all data lanes are +// controlled by primary AC tile, except that the lanes actually controlled by secondary AC tile +// have the value added by 1. +`define _get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) ( (NUM_OF_HMC_PORTS > 0) ? (`_get_max_distance_from_ac_tile_capped + 1) : (`_get_db_ptr_pipe_depth(_tile_i, _lane_i) + 1) ) +`define _get_db_seq_rd_en_full_pipeline_sec(_tile_i, _lane_i) ( `_get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) + 1 ) +`define _get_db_seq_rd_en_full_pipeline(_tile_i, _lane_i) ( `_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? `_get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) : `_get_db_seq_rd_en_full_pipeline_sec(_tile_i, _lane_i)) + +`define _get_db_data_alignment_mode ( (NUM_OF_HMC_PORTS > 0) ? "align_ena" : "align_disable" ) + +`define _get_lane_mode_rate_in ( PHY_HMC_CLK_RATIO == 4 ? "in_rate_1_4" : ( \ + PHY_HMC_CLK_RATIO == 2 ? "in_rate_1_2" : ( \ + "in_rate_full" ))) + +`define _get_lane_mode_rate_out ( PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 8 ? "out_rate_1_8" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 4 ? "out_rate_1_4" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 2 ? "out_rate_1_2" : ( \ + "out_rate_full" )))) + +`define _get_hmc_ctrl_mem_type ( PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "lpddr3" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "rldram_iii" : ( \ + "" )))))))) + +`define _get_hmc_or_core ( NUM_OF_HMC_PORTS == 0 ? "core" : "hmc" ) + +`define _get_hmc_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate" : "half_rate" ) +`define _get_dbc0_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc0" : "half_rate_dbc0" ) +`define _get_dbc1_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc1" : "half_rate_dbc1" ) +`define _get_dbc2_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc2" : "half_rate_dbc2" ) +`define _get_dbc3_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc3" : "half_rate_dbc3" ) + +`define _get_hmc_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_in" : "ast_in" ) +`define _get_dbc0_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc0" : "ast_dbc0" ) +`define _get_dbc1_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc1" : "ast_dbc1" ) +`define _get_dbc2_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc2" : "ast_dbc2" ) +`define _get_dbc3_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc3" : "ast_dbc3" ) + +`define _get_hmc_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_ctrl" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_ctrl" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_ctrl" : ( \ + "" )))) + +`define _get_dbc0_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc0" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc0" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc0" : ( \ + "" )))) + +`define _get_dbc1_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc1" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc1" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc1" : ( \ + "" )))) + +`define _get_dbc2_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc2" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc2" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc2" : ( \ + "" )))) + +`define _get_dbc3_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc3" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc3" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc3" : ( \ + "" )))) + +`define _get_dqs_lgc_burst_length ( PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "burst_length_2" : ( \ + MEM_BURST_LENGTH == 2 ? "burst_length_2" : ( \ + MEM_BURST_LENGTH == 4 ? "burst_length_4" : ( \ + MEM_BURST_LENGTH == 8 ? "burst_length_8" : ( \ + "" )))))))) + +`define _get_pa_exponent(_clk_ratio) ( (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 1 ? 3'b000 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 2 ? 3'b001 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 4 ? 3'b010 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 8 ? 3'b011 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 16 ? 3'b100 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 32 ? 3'b101 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 64 ? 3'b110 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 128 ? 3'b111 : ( \ + 3'b000 ))))))))) + +// CPA output 0 - in HMC mode, matches emif_usr_clk; in non-HMC mode, matches afi_half_clk +`define _get_cpa_0_clk_ratio ( NUM_OF_HMC_PORTS > 0 ? USER_CLK_RATIO : (USER_CLK_RATIO * 2) ) +`define _get_pa_exponent_0 ( (`_get_pa_exponent(`_get_cpa_0_clk_ratio)) ) + +// CPA output 1 - always matches the C2P/P2C rate +`define _get_cpa_1_clk_ratio ( C2P_P2C_CLK_RATIO ) +`define _get_pa_exponent_1 ( (`_get_pa_exponent(`_get_cpa_1_clk_ratio)) ) + +// CPA output 0 - clock divider on PHY clock feedback. +// Enable divide-by-2 whenever the core clock needs to run at half the speed of the feedback clock +`define _get_pa_feedback_divider_p0 ( (`_get_cpa_0_clk_ratio == C2P_P2C_CLK_RATIO * 2) ? "div_by_2_p0" : "div_by_1_p0" ) + +// CPA output 0 - clock divider on core clock feedback. +// Enable divide-by-2 whenever the core clock needs to run at 2x the speed of the feedback clock +`define _get_pa_feedback_divider_c0 ( (`_get_cpa_0_clk_ratio * 2 == C2P_P2C_CLK_RATIO) ? "div_by_2_c0" : "div_by_1_c0" ) + +`define _get_dqsin(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_RDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WRDATA) ? 2'b0 : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? t2l_dqsbus_x4[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? t2l_dqsbus_x8[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? t2l_dqsbus_x18[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? t2l_dqsbus_x36[_lane_i] : ( \ + 2'b0 )))))) + +`define _get_pin_dqs_x4_mode_0 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_1 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_2 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_3 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_4 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_5 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_6 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_7 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_8 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_9 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_10 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_11 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) + +// DBC Mux Scheme (non-ping-pong): +// +// Tiles above : switch0 = don't-care dbc*_sel = switch1 (lower mux) +// switch1 = from lower +// +// AC Tile : switch0 = local dbc*_sel = switch0 (upper mux) +// switch1 = local +// +// Tiles below : switch0 = from upper dbc*_sel = switch0 (upper mux) +// switch1 = don't-care +// +`define _get_ctrl2dbc_switch_0_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" ))) + +`define _get_ctrl2dbc_switch_1_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" ))) + +`define _get_ctrl2dbc_sel_0_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc0" : "lower_mux_dbc0" ) +`define _get_ctrl2dbc_sel_1_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc1" : "lower_mux_dbc1" ) +`define _get_ctrl2dbc_sel_2_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc2" : "lower_mux_dbc2" ) +`define _get_ctrl2dbc_sel_3_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc3" : "lower_mux_dbc3" ) + +// DBC Mux Scheme (ping-pong): +// +// Tiles above : switch0 = don't-care dbc*_sel = switch1 (lower mux) +// switch1 = from lower +// +// Primary AC Tile : switch0 = local dbc*_sel = switch1 (lower mux) +// switch1 = local +// +// Secondary AC Tile: switch0 = local dbc2_sel, dbc3_sel = switch0 (upper mux) +// switch1 = from upper dbc0_sel, dbc1_sel = switch1 (lower mux) +// +// Tiles below : switch0 = from upper dbc*_sel = switch0 (upper mux) +// switch1 = don't-care +// +`define _get_ctrl2dbc_switch_0_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i < SEC_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" )))) + +`define _get_ctrl2dbc_switch_1_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "upper_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" )))) + +`define _get_ctrl2dbc_sel_0_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc0" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc0" : (`_get_ac_tile_index(_tile_i, 0) == PRI_AC_TILE_INDEX ? "lower_mux_dbc0" : "upper_mux_dbc0")) ) +`define _get_ctrl2dbc_sel_1_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc1" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc1" : (`_get_ac_tile_index(_tile_i, 1) == PRI_AC_TILE_INDEX ? "lower_mux_dbc1" : "upper_mux_dbc1")) ) +`define _get_ctrl2dbc_sel_2_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc2" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc2" : (`_get_ac_tile_index(_tile_i, 2) == PRI_AC_TILE_INDEX ? "lower_mux_dbc2" : "upper_mux_dbc2")) ) +`define _get_ctrl2dbc_sel_3_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc3" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc3" : (`_get_ac_tile_index(_tile_i, 3) == PRI_AC_TILE_INDEX ? "lower_mux_dbc3" : "upper_mux_dbc3")) ) + +// DBC Mux Scheme (ping-pong and non-ping-pong) +`define _get_ctrl2dbc_switch_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_0_pp(_tile_i) : `_get_ctrl2dbc_switch_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_switch_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_1_pp(_tile_i) : `_get_ctrl2dbc_switch_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_0_pp(_tile_i) : `_get_ctrl2dbc_sel_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_1_pp(_tile_i) : `_get_ctrl2dbc_sel_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_2(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_2_pp(_tile_i) : `_get_ctrl2dbc_sel_2_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_3(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_3_pp(_tile_i) : `_get_ctrl2dbc_sel_3_non_pp(_tile_i) ) + +// Select which DBC to use as shadow. +// For the primary HMC tile or non-Ping-Pong HMC tile, pick "dbc1_to_local" as it's guaranteed to be used by the interface (as an A/C lane). +// The exception is for HPS mode - HPS is only connected to lane 3 of the HMC tile for the +// various Avalon control signals, therefore we must denote lane 3 as shadow. +// (note that HPS doesn't support Ping-Pong so we only need to handle non-Ping-Pong case) +// For the secondary HMC tile, which one we pick depends on which data lane in the tile belongs to the secondary interface. +`define _get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ( PRI_HMC_DBC_SHADOW_LANE_INDEX == 0 ? "dbc0_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 1 ? "dbc1_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 2 ? "dbc2_to_local" : ( \ + "dbc3_to_local" )))) + +`define _get_hmc_dbc2ctrl_sel_pp(_tile_i) ( (_tile_i != SEC_AC_TILE_INDEX) ? `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 0) == SEC_AC_TILE_INDEX) ? "dbc0_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 1) == SEC_AC_TILE_INDEX) ? "dbc1_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 2) == SEC_AC_TILE_INDEX) ? "dbc2_to_local" : ( \ + "dbc3_to_local" ))))) +`define _get_hmc_dbc2ctrl_sel(_tile_i) ( PHY_PING_PONG_EN ? `_get_hmc_dbc2ctrl_sel_pp(_tile_i) : `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ) + +// ac_hmc is hard connectivity between HMC and A/C lanes +// The Fitter uses ac_hmc as a special connection to locate the A/C tile and lanes, regardless of whether HMC is used. +// Normally, we only connect these to lanes that are used as A/C, regardless of HMC or SMC. +// For HPS non-ECC, we must ensure even the unused lane 3 is connected so that the lane isn't swept away by Fitter +`define _get_ac_hmc(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_HMC || \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_CORE || \ + (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_UNUSED && IS_HPS && _tile_i == PRI_AC_TILE_INDEX)) ? \ + t2l_ac_hmc[lane_i] : 96'b0 ) + +// core2dbc_wr_data_vld needs to fanout to every data lane and also the A/C lane denoted as shadow by _get_hmc_dbc2ctrl_sel +`define _get_core2dbc_wr_data_vld_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_wr_data_vld_ast_0 : core2l_wr_data_vld_ast_1 ) ) +`define _get_core2dbc_wr_data_vld(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_wr_data_vld_of_hmc(_tile_i, _lane_i) : 1'b0 ) + +// core2dbc_rd_data_rdy needs to fanout to every data lane and also the lane denoted as shadow by _get_hmc_dbc2ctrl_sel +`define _get_core2dbc_rd_data_rdy_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_rd_data_rdy_ast_0 : core2l_rd_data_rdy_ast_1 ) ) +`define _get_core2dbc_rd_data_rdy(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_rd_data_rdy_of_hmc(_tile_i, _lane_i) : 1'b1 ) + +// core2dbc_wr_ecc_info needs to fanout to every data lane and also the lane denoted as shadow by _get_hmc_dbc2ctrl_sel +`define _get_core2dbc_wr_ecc_info_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_wr_ecc_info_0 : core2l_wr_ecc_info_1 ) ) +`define _get_core2dbc_wr_ecc_info(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_wr_ecc_info_of_hmc(_tile_i, _lane_i) : 13'b0 ) + +`define _get_center_tid(_tile_i) ( CENTER_TIDS[_tile_i * 9 +: 9] ) +`define _get_hmc_tid(_tile_i) ( HMC_TIDS[_tile_i * 9 +: 9] ) +`define _get_lane_tid(_tile_i, _lane_i) ( LANE_TIDS[(_tile_i * LANES_PER_TILE + _lane_i) * 9 +: 9] ) + +`define _get_preamble_track_dqs_enable_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "preamble_track_toggler" : ( \ + "" )))))))) + +`define _get_pst_preamble_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "ddr3_preamble" : "ddr4_preamble") : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "ddr3_preamble" : ( \ + "" )))))))) + +`define _get_ddr4_search "ddr3_search" +/*`define _get_ddr4_search ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "ddr3_search" : ( \ + "" ))))))) +*/ + +// Enable DQSB bus for QDR-II and for x4 mode +`define _get_dqs_b_en ( (PROTOCOL_ENUM == "PROTOCOL_QDR2") || (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "true" : "false" ) + +`define _get_pst_en_shrink ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "shrink_1_1" : "shrink_1_0") : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "shrink_0_1" : ( \ + "" )))))))) + +`define _get_pa_track_speed ( 5'h0c ) + +// synthesis translate_off +`define _get_dll_ctlsel ( "ctl_dynamic" ) +`define _get_dll_ctl_static ( 10'd0 ) +// synthesis translate_on +// synthesis read_comments_as_HDL on +// `define _get_dll_ctlsel ( DIAG_SYNTH_FOR_SIM ? "ctl_dynamic" : DLL_MODE ) +// `define _get_dll_ctl_static ( DIAG_SYNTH_FOR_SIM ? 10'd0 : DLL_CODEWORD[9:0] ) +// synthesis read_comments_as_HDL off + +// Enable the per-lane hard DBI circuitry. Only intended to be used by DDR4 data lanes. +`define _get_dbi_wr_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_WR_ENABLE : "false") +`define _get_dbi_rd_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_RD_ENABLE : "false") + +// Enable the per-lane hard CRC circuitry. Only intended to be used by DDR4 data lanes. +`define _get_crc_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? CRC_EN : "crc_disable") + +// The hard CRC circuitry needs to know how many bits to use for CRC calculation. +`define _get_crc_x4_or_x8_or_x9 ( (PORT_MEM_DQ_WIDTH / PORT_MEM_DQS_WIDTH == 4) ? "x4_mode" : ( \ + (DBI_WR_ENABLE == "true" || MEM_DATA_MASK_EN) ? "x9_mode" : ( \ + "x8_mode" )) ) + +// Map CSR Bit Position tp each data pin +//In x4 mode only first 4 pins are required +`define _get_crc_pin_pos_0 1 +`define _get_crc_pin_pos_1 2 +`define _get_crc_pin_pos_2 3 +`define _get_crc_pin_pos_3 6 +`define _get_crc_pin_pos_4 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 7 : 4) +`define _get_crc_pin_pos_5 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 8 : 4) +`define _get_crc_pin_pos_6 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 9 : 4) +`define _get_crc_pin_pos_7 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 10 : 4) +`define _get_crc_pin_pos_8 ((`_get_crc_x4_or_x8_or_x9 == "x9_mode") ? 11 : 4) + +// Select primary or secondary HMC config +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select secondary +// For everything else, select primary +`define _sel_hmc_val(_tile_i, _pri, _sec) ( PHY_PING_PONG_EN ? (_tile_i <= SEC_AC_TILE_INDEX ? _sec : _pri) : _pri ) + +// Select primary/secondary/default HMC config +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select secondary +// For everything else, select default +`define _sel_hmc_def(_tile_i, _pri, _sec, _def) ( PHY_PING_PONG_EN ? ((_tile_i == SEC_AC_TILE_INDEX) ? _sec : (_tile_i == PRI_AC_TILE_INDEX) ? _pri : _def) : _pri ) + +// Select primary or secondary HMC config, with lane dependence +// For non-ping-pong and primary HMC of ping-pong, select primary +// For secondary HMC of ping-pong, select primary or secondary based on lane affiliation +`define _sel_hmc_lane(_tile_i, _lane_i, _pri, _sec) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? _sec : _pri ) + +module altera_emif_arch_nf_io_tiles #( + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_FAST_SIM = 0, + parameter IS_HPS = 0, + parameter SILICON_REV = "", + parameter PROTOCOL_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter LANES_USAGE = 1'b0, + parameter PINS_USAGE = 1'b0, + parameter PINS_RATE = 1'b0, + parameter PINS_WDB = 1'b0, + parameter PINS_DB_IN_BYPASS = 1'b0, + parameter PINS_DB_OUT_BYPASS = 1'b0, + parameter PINS_DB_OE_BYPASS = 1'b0, + parameter PINS_INVERT_WR = 1'b0, + parameter PINS_INVERT_OE = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA = 1'b0, + parameter PINS_DATA_IN_MODE = 1'b0, + parameter PINS_OCT_MODE = 1'b0, + parameter PINS_GPIO_MODE = 1'b0, + parameter CENTER_TIDS = 1'b0, + parameter HMC_TIDS = 1'b0, + parameter LANE_TIDS = 1'b0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = "", + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 1 +) ( + // Reset + input logic global_reset_n_int, //__ACDS_USER_COMMNET__ Async reset signal from user + output logic phy_reset_n_nonabphy, // Async reset signal from reset circuitry in the tile + + // Signals for various signals from PLL + input logic pll_locked, // Indicates PLL lock status + input logic pll_dll_clk, // PLL -> DLL output clock + input logic [7:0] phy_clk_phs, // FR PHY clock signals (8 phases, 45-deg apart) + input logic [1:0] phy_clk, // {phy_clk[1], phy_clk[0]} + input logic phy_fb_clk_to_tile, // PHY feedback clock (to tile) + output logic phy_fb_clk_to_pll_nonabphy, // PHY feedback clock (to PLL) + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + output logic [1:0] core_clks_from_cpa_pri_nonabphy, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri_nonabphy, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_fb_to_cpa_pri, // Core clock feedback signals to the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec_nonabphy, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec_nonabphy, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_fb_to_cpa_sec, // Core clock feedback signals to the CPA of secondary interface (ping-pong only) + + // Avalon interfaces between core and HMC + input logic [59:0] core2ctl_avl_0, + input logic [59:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + output logic ctl2core_avl_cmd_ready_0_nonabphy, + output logic ctl2core_avl_cmd_ready_1_nonabphy, + output logic [12:0] ctl2core_avl_rdata_id_0_nonabphy, + output logic [12:0] ctl2core_avl_rdata_id_1_nonabphy, + input logic core2l_wr_data_vld_ast_0, + input logic core2l_wr_data_vld_ast_1, + input logic core2l_rd_data_rdy_ast_0, + input logic core2l_rd_data_rdy_ast_1, + + // Avalon interfaces between core and lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_nonabphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_nonabphy, + + // ECC signals between core and lanes + input logic [12:0] core2l_wr_ecc_info_0, + input logic [12:0] core2l_wr_ecc_info_1, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_nonabphy, + + // Signals between core and data lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_nonabphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_nonabphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_nonabphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_nonabphy, + + // AFI signals between tile and core + input [16:0] c2t_afi, + output [25:0] t2c_afi_nonabphy, + + // Side-band signals between core and HMC + input logic [41:0] core2ctl_sideband_0, + output logic [13:0] ctl2core_sideband_0_nonabphy, + input logic [41:0] core2ctl_sideband_1, + output logic [13:0] ctl2core_sideband_1_nonabphy, + + // MMR signals between core and HMC + output logic [33:0] ctl2core_mmr_0_nonabphy, + input logic [50:0] core2ctl_mmr_0, + output logic [33:0] ctl2core_mmr_1_nonabphy, + input logic [50:0] core2ctl_mmr_1, + + // Signals between I/O buffers and lanes/tiles + output logic [PINS_IN_RTL_TILES-1:0] l2b_data_nonabphy, // lane-to-buffer data + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe_nonabphy, // lane-to-buffer output-enable + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_nonabphy, // lane-to-buffer dynamic-termination-control + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, // buffer-to-lane data + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, // buffer-to-tile DQS + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between io_aux and tiles + input logic cal_bus_clk, + input logic cal_bus_avl_read, + input logic cal_bus_avl_write, + input logic [19:0] cal_bus_avl_address, + output logic [31:0] cal_bus_avl_read_data, + input logic [31:0] cal_bus_avl_write_data, + + // Ports for internal test and debug + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select_nonabphy, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_nonabphy +); + timeunit 1ns; + timeprecision 1ps; + + // Enum that defines whether a lane is used or not, and in what mode. + // This enum type is used to encode the LANES_USAGE_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + // Enum that defines whether a pin is used by EMIF + // This enum type is used to encode the PINS_USAGE parameter + // passed into the io_tiles module. + typedef enum bit [0:0] { + PIN_USAGE_UNUSED = 1'b0, + PIN_USAGE_USED = 1'b1 + } PIN_USAGE; + + // Enum that defines whether an EMIF pin operates at SDR or DDR. + // This enum type is used to encode the PINS_RATE parameter + // passed into the io_tiles module. + typedef enum bit [0:0] { + PIN_RATE_DDR = 1'b0, + PIN_RATE_SDR = 1'b1 + } PIN_RATE; + + // Enum that defines the direction of an EMIF pin. + typedef enum bit [0:0] { + PIN_OCT_STATIC_OFF = 1'b0, + PIN_OCT_DYNAMIC = 1'b1 + } PIN_OCT_MODE; + + // Enum that defines the write data buffer mode of an EMIF pin. + // This enum type is used to encode the PINS_WDB parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + PIN_WDB_AC_CORE = 3'b000, + PIN_WDB_AC_HMC = 3'b001, + PIN_WDB_DQS_WDB_MODE = 3'b010, + PIN_WDB_DQS_MODE = 3'b011, + PIN_WDB_DM_WDB_MODE = 3'b100, + PIN_WDB_DM_MODE = 3'b101, + PIN_WDB_DQ_WDB_MODE = 3'b110, + PIN_WDB_DQ_MODE = 3'b111 + } PIN_WDB; + + // Enum that defines the pin data in mode of an EMIF pin. + // This enum type is used to encode the PINS_DATA_IN_MODE parameter + // passed into the io_tiles module. + typedef enum bit [2:0] { + PIN_DATA_IN_MODE_DISABLED = 3'b000, + PIN_DATA_IN_MODE_SSTL_IN = 3'b001, + PIN_DATA_IN_MODE_LOOPBACK_IN = 3'b010, + PIN_DATA_IN_MODE_XOR_LOOPBACK_IN = 3'b011, + PIN_DATA_IN_MODE_DIFF_IN = 3'b100, + PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT = 3'b101, + PIN_DATA_IN_MODE_DIFF_IN_X12_OUT = 3'b110, + PIN_DATA_IN_MODE_DIFF_IN_AVL_X12_OUT = 3'b111 + } PIN_DATA_IN_MODE; + + // Is HMC rate converter or dual-port feature turned on? + // This can be inferred from the clock rates at core/periphery boundary and in HMC. + localparam USE_HMC_RC_OR_DP = (C2P_P2C_CLK_RATIO == PHY_HMC_CLK_RATIO) ? 0 : 1; + + // The VCO frequency is used to derive filter code of interpolators + // This is capped at 650MHz intentionally for slower interfaces to ensure + // timing closure of a hard path. + localparam PLL_VCO_FREQ_MHZ_INT_CAPPED = PLL_VCO_FREQ_MHZ_INT < 650 ? 650 : PLL_VCO_FREQ_MHZ_INT; + + localparam USE_FAST_INTERPOLATOR_SIM = (PLL_VCO_FREQ_MHZ_INT < 600) ? 0 : DIAG_FAST_SIM; + + // Reset Signals + // Only element at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, is used + logic [NUM_OF_RTL_TILES-1:0] t2c_seq2core_reset_n; + assign phy_reset_n_nonabphy = t2c_seq2core_reset_n[PRI_AC_TILE_INDEX]; + + // The phase alignment blocks have synchronization signals between them + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_dn_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_dn_chain; + assign pa_sync_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_clk_dn_chain [NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_data_up_chain[0] = 1'b1; + assign pa_sync_clk_up_chain [0] = 1'b1; + + // The Avalon command bus signal daisy-chains one tile to another + // from bottom-to-top starting from the I/O aux. + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][54:0] cal_bus_avl_up_chain; + assign cal_bus_avl_up_chain[0][19:0] = cal_bus_avl_address; + assign cal_bus_avl_up_chain[0][51:20] = cal_bus_avl_write_data; + assign cal_bus_avl_up_chain[0][52] = cal_bus_avl_write; + assign cal_bus_avl_up_chain[0][53] = cal_bus_avl_read; + assign cal_bus_avl_up_chain[0][54] = cal_bus_clk; + + // The Avalon read data signal daisy-chains one tile to another + // from top-to-bottom ending at the I/O aux. + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][31:0] cal_bus_avl_read_data_dn_chain; + assign cal_bus_avl_read_data = cal_bus_avl_read_data_dn_chain[0]; + assign cal_bus_avl_read_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 32'b0; + + // Broadcast signals that daisy-chain all lanes in upward and downward directions. + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0] broadcast_up_chain; + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0] broadcast_dn_chain; + assign broadcast_dn_chain[NUM_OF_RTL_TILES * LANES_PER_TILE] = 1'b1; + assign broadcast_up_chain[0] = 1'b1; + + // HMC-to-DBC signals going from tiles to lanes and between tiles + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc0_dn_chain; + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc1_up_chain; + assign all_tiles_ctl2dbc0_dn_chain[NUM_OF_RTL_TILES] = {51{1'b1}}; + assign all_tiles_ctl2dbc1_up_chain[0] = {51{1'b1}}; + + // Ping-Pong signals going up the column + logic [NUM_OF_RTL_TILES:0][47:0] all_tiles_ping_pong_up_chain; + assign all_tiles_ping_pong_up_chain[0] = {48{1'b1}}; + + // PHY clock signals going from tiles to lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] all_tiles_t2l_phy_clk_phs; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][1:0] all_tiles_t2l_phy_clk; + + // DLL clock from tile_ctrl to lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] all_tiles_dll_clk_out; + + // Outputs from the CPA inside each tile + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + // In ping-pong configuration, the CPA inside the primary HMC tile is used, hence no need to account for secondary tile + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_out; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_fb_in; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_locked; + + assign core_clks_from_cpa_pri_nonabphy = all_tiles_core_clks_out[PRI_AC_TILE_INDEX]; + assign core_clks_locked_cpa_pri_nonabphy = all_tiles_core_clks_locked[PRI_AC_TILE_INDEX]; + assign all_tiles_core_clks_fb_in[PRI_AC_TILE_INDEX] = core_clks_fb_to_cpa_pri; + + assign core_clks_from_cpa_sec_nonabphy = PHY_PING_PONG_EN ? all_tiles_core_clks_out[SEC_AC_TILE_INDEX] : '0; + assign core_clks_locked_cpa_sec_nonabphy = PHY_PING_PONG_EN ? all_tiles_core_clks_locked[SEC_AC_TILE_INDEX] : '0; + generate + if (PHY_PING_PONG_EN) begin + assign all_tiles_core_clks_fb_in[SEC_AC_TILE_INDEX] = core_clks_fb_to_cpa_sec; + end + endgenerate + + // Outputs from PHY clock tree back to PLL + // Physically, this connection needs to happen in every tile but + // in RTL we only make this connection for the A/C tile (since we + // only have one logical PLL) + logic [NUM_OF_RTL_TILES-1:0] all_tiles_phy_fb_clk_to_pll; + assign phy_fb_clk_to_pll_nonabphy = all_tiles_phy_fb_clk_to_pll[PRI_AC_TILE_INDEX]; + + // Avalon signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0] all_tiles_ctl2core_avl_cmd_ready; + logic [NUM_OF_RTL_TILES-1:0][12:0] all_tiles_ctl2core_avl_rdata_id; + + assign ctl2core_avl_cmd_ready_0_nonabphy = all_tiles_ctl2core_avl_cmd_ready[PRI_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_0_nonabphy = all_tiles_ctl2core_avl_rdata_id[PRI_AC_TILE_INDEX]; + + assign ctl2core_avl_cmd_ready_1_nonabphy = all_tiles_ctl2core_avl_cmd_ready[SEC_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_1_nonabphy = all_tiles_ctl2core_avl_rdata_id[SEC_AC_TILE_INDEX]; + + // AFI signals between tile and core + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + // Ping-Pong PHY doesn't support AFI interface so there's no need to account for SEC_AC_TILE_INDEX + logic [NUM_OF_RTL_TILES-1:0][16:0] all_tiles_c2t_afi; + logic [NUM_OF_RTL_TILES-1:0][25:0] all_tiles_t2c_afi; + + assign all_tiles_c2t_afi[PRI_AC_TILE_INDEX] = c2t_afi; + assign t2c_afi_nonabphy = all_tiles_t2c_afi[PRI_AC_TILE_INDEX]; + + // Sideband signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0][13:0] all_tiles_ctl2core_sideband; + + assign ctl2core_sideband_0_nonabphy = all_tiles_ctl2core_sideband[PRI_AC_TILE_INDEX]; + assign ctl2core_sideband_1_nonabphy = all_tiles_ctl2core_sideband[SEC_AC_TILE_INDEX]; + + // MMR signals between HMC and core + // In the following arrays, only elements at tile index *_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0][33:0] all_tiles_ctl2core_mmr; + + assign ctl2core_mmr_0_nonabphy = all_tiles_ctl2core_mmr[PRI_AC_TILE_INDEX]; + assign ctl2core_mmr_1_nonabphy = all_tiles_ctl2core_mmr[SEC_AC_TILE_INDEX]; + + // CPA DPRIO signals (for internal debug) + // In the following arrays, only elements at tile index PRI_AC_TILE_INDEX, corresponding to the addr/cmd tile, are used + logic [NUM_OF_RTL_TILES-1:0] all_tiles_pa_dprio_block_select; + logic [NUM_OF_RTL_TILES-1:0][PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] all_tiles_pa_dprio_readdata; + + assign pa_dprio_readdata_nonabphy = all_tiles_pa_dprio_readdata[PRI_AC_TILE_INDEX]; + assign pa_dprio_block_select_nonabphy = all_tiles_pa_dprio_block_select[PRI_AC_TILE_INDEX]; + + // DLL reset signal + // Comes from the core solely when not using the HPS + logic [2:0] core2dll; + generate + if (IS_HPS) begin : core2dll_hps + assign core2dll = 3'b000; + end else begin : core2dll_non_hps + assign core2dll = {global_reset_n_int, 1'b0, 1'b0}; + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // Generate tiles and lanes. + //////////////////////////////////////////////////////////////////////////// + generate + genvar tile_i, lane_i; + for (tile_i = 0; tile_i < NUM_OF_RTL_TILES; ++tile_i) + begin: tile_gen + + // DQS bus from tile to lanes + logic [1:0] t2l_dqsbus_x4 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x8 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x18 [LANES_PER_TILE-1:0]; + logic [1:0] t2l_dqsbus_x36 [LANES_PER_TILE-1:0]; + + // HMC AFI signals going to lanes. + logic [3:0][95:0] t2l_ac_hmc; + + // HMC to Data buffer control blocks in the lanes + logic [16:0] t2l_cfg_dbc [LANES_PER_TILE-1:0]; + + // Data buffer control blocks in the lanes to HMC + logic [22:0] l2t_dbc2ctl [LANES_PER_TILE-1:0]; + + (* altera_attribute = "-name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 1" *) + twentynm_tile_ctrl # ( + .silicon_rev (SILICON_REV), + .hps_ctrl_en (IS_HPS ? "true" : "false"), + .pa_filter_code (PLL_VCO_FREQ_MHZ_INT_CAPPED), + .pa_phase_offset_0 (12'b0), // Output clock phase degree = phase_offset / 128 * 360 + .pa_phase_offset_1 (12'b0), // Output clock phase degree = phase_offset / 128 * 360 + .pa_exponent_0 (`_get_pa_exponent_0), // Output clock freq = VCO Freq / ( 1.mantissa * 2^exponent) + .pa_exponent_1 (`_get_pa_exponent_1), // Output clock freq = VCO Freq / ( 1.mantissa * 2^exponent) + .pa_mantissa_0 (5'b0), // Output clock freq = VCO Freq / ( 1.mantissa * 2^exponent) + .pa_mantissa_1 (5'b0), // Output clock freq = VCO Freq / ( 1.mantissa * 2^exponent) + .pa_feedback_divider_c0 (`_get_pa_feedback_divider_c0), // Core clock 0 divider (either 1 or 2) + .pa_feedback_divider_c1 ("div_by_1_c1"), // Core clock 1 divider (always 1) + .pa_feedback_divider_p0 (`_get_pa_feedback_divider_p0), // PHY clock 0 divider (either 1 or 2) + .pa_feedback_divider_p1 ("div_by_1_p1"), // PHY clock 1 divider (always 1) + .pa_feedback_mux_sel_0 ("fb2_p_clk_0"), // Use phy_clk[2] as feedback + .pa_feedback_mux_sel_1 (DIAG_CPA_OUT_1_EN ? "fb0_p_clk_1" : "fb2_p_clk_1"), // Use phy_clk[2] as feedback, unless in dual-CPA characterization mode + .pa_freq_track_speed (4'hd), + .pa_track_speed (`_get_pa_track_speed), + .pa_sync_control ("no_sync"), + .pa_sync_latency (4'b0000), + .hmc_ck_inv ("disable"), + .hmc_cfg_wdata_driver_sel ("core_w"), + .hmc_cfg_prbs_ctrl_sel ("hmc"), + .hmc_cfg_mmr_driver_sel ("core_m"), + .hmc_cfg_loopback_en ("disable"), + .hmc_cfg_cmd_driver_sel ("core_c"), + .hmc_cfg_dbg_mode ("function"), + .hmc_cfg_dbg_ctrl (32'b00000000000000000000000000000000), + .hmc_cfg_bist_cmd0_u (32'b00000000000000000000000000000000), + .hmc_cfg_bist_cmd0_l (32'b00000000000000000000000000000000), + .hmc_cfg_bist_cmd1_u (32'b00000000000000000000000000000000), + .hmc_cfg_bist_cmd1_l (32'b00000000000000000000000000000000), + .hmc_cfg_dbg_out_sel (16'b0000000000000000), + .hmc_ctrl_mem_type (`_get_hmc_ctrl_mem_type), + .hmc_ctrl_dimm_type (HMC_CTRL_DIMM_TYPE), + .hmc_ctrl_ac_pos (AC_PIN_MAP_SCHEME), + .hmc_ctrl_burst_length (`_get_hmc_burst_length), + .hmc_dbc0_burst_length (`_get_dbc0_burst_length), + .hmc_dbc1_burst_length (`_get_dbc1_burst_length), + .hmc_dbc2_burst_length (`_get_dbc2_burst_length), + .hmc_dbc3_burst_length (`_get_dbc3_burst_length), + .hmc_ctrl_enable_dm (MEM_DATA_MASK_EN ? "enable" : "disable"), + .hmc_dbc0_enable_dm (MEM_DATA_MASK_EN ? "enable" : "disable"), + .hmc_dbc1_enable_dm (MEM_DATA_MASK_EN ? "enable" : "disable"), + .hmc_dbc2_enable_dm (MEM_DATA_MASK_EN ? "enable" : "disable"), + .hmc_dbc3_enable_dm (MEM_DATA_MASK_EN ? "enable" : "disable"), + .hmc_clkgating_en ("disable"), // Gate the clock going into hard controller to save power, if hard controller isn't used + .hmc_ctrl_output_regd ("disable"), // Engineering option to turn on register stage to help internal timing. Currently not needed. + .hmc_dbc0_output_regd ("disable"), // Engineering option to turn on register stage to help internal timing. Currently not needed. + .hmc_dbc1_output_regd ("disable"), // Engineering option to turn on register stage to help internal timing. Currently not needed. + .hmc_dbc2_output_regd ("disable"), // Engineering option to turn on register stage to help internal timing. Currently not needed. + .hmc_dbc3_output_regd ("disable"), // Engineering option to turn on register stage to help internal timing. Currently not needed. + .hmc_ctrl2dbc_switch0 (`_get_ctrl2dbc_switch_0(tile_i)), + .hmc_ctrl2dbc_switch1 (`_get_ctrl2dbc_switch_1(tile_i)), + .hmc_dbc0_ctrl_sel (`_get_ctrl2dbc_sel_0(tile_i)), + .hmc_dbc1_ctrl_sel (`_get_ctrl2dbc_sel_1(tile_i)), + .hmc_dbc2_ctrl_sel (`_get_ctrl2dbc_sel_2(tile_i)), + .hmc_dbc3_ctrl_sel (`_get_ctrl2dbc_sel_3(tile_i)), + .hmc_dbc2ctrl_sel (`_get_hmc_dbc2ctrl_sel(tile_i)), + .hmc_dbc0_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 0))), + .hmc_dbc1_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 1))), + .hmc_dbc2_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 2))), + .hmc_dbc3_pipe_lat (3'(`_get_dbc_pipe_lat(tile_i, 3))), + .hmc_ctrl_cmd_rate (`_get_hmc_cmd_rate), + .hmc_dbc0_cmd_rate (`_get_dbc0_cmd_rate), + .hmc_dbc1_cmd_rate (`_get_dbc1_cmd_rate), + .hmc_dbc2_cmd_rate (`_get_dbc2_cmd_rate), + .hmc_dbc3_cmd_rate (`_get_dbc3_cmd_rate), + .hmc_ctrl_in_protocol (`_get_hmc_protocol), + .hmc_dbc0_in_protocol (`_get_dbc0_protocol), + .hmc_dbc1_in_protocol (`_get_dbc1_protocol), + .hmc_dbc2_in_protocol (`_get_dbc2_protocol), + .hmc_dbc3_in_protocol (`_get_dbc3_protocol), + .hmc_ctrl_dualport_en ("disable"), // No dual-port mode support + .hmc_dbc0_dualport_en ("disable"), // No dual-port mode support + .hmc_dbc1_dualport_en ("disable"), // No dual-port mode support + .hmc_dbc2_dualport_en ("disable"), // No dual-port mode support + .hmc_dbc3_dualport_en ("disable"), // No dual-port mode support + .hmc_tile_id (tile_i[4:0]), // HMC ID (0 for T0, 1 for T1, etc) - actual value set by Fitter based on placement + .physeq_tile_id (`_get_center_tid(tile_i)), // io_center tile ID - actual value is set by fitter based on placement + .physeq_bc_id_ena ("bc_enable"), // Enable broadcast mechanism + .physeq_avl_ena ("avl_enable"), // Enable Avalon interface + .physeq_hmc_or_core (`_get_hmc_or_core), // Is HMC used? + .physeq_trk_mgr_mrnk_mode ("one_rank"), + .physeq_trk_mgr_read_monitor_ena ("disable"), // Must be disabled to avoid an issue with tracking manager (ICD) + .physeq_hmc_id (`_get_hmc_tid(tile_i)), // HMC tile ID - actual value is set by fitter based on placement + .physeq_reset_auto_release ("avl"), // Reset sequencer controlled via Avalon by Nios + .physeq_rwlat_mode ("avl_vlu"), // wlat/rlat set dynamically via Avalon by Nios (instead of through CSR) + .physeq_afi_rlat_vlu (6'b000000), // Unused - wlat set dynamically via Avalon by Nios + .physeq_afi_wlat_vlu (6'b000000), // Unused - rlat set dynamically via Avalon by Nios + .hmc_second_clk_src (USE_HMC_RC_OR_DP ? "clk1" : "clk0"), // Use clk1 in rate-converter or dual-port mode, and clk0 otherwise + .physeq_seq_feature (21'b000000000000000000000), + .hmc_ctrl_enable_ecc (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_ECC , SEC_HMC_CFG_ENABLE_ECC )), // Enable ECC + .hmc_dbc0_enable_ecc (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_ECC , SEC_HMC_CFG_ENABLE_ECC )), // Enable ECC + .hmc_dbc1_enable_ecc (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_ECC , SEC_HMC_CFG_ENABLE_ECC )), // Enable ECC + .hmc_dbc2_enable_ecc (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_ECC , SEC_HMC_CFG_ENABLE_ECC )), // Enable ECC + .hmc_dbc3_enable_ecc (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_ECC , SEC_HMC_CFG_ENABLE_ECC )), // Enable ECC + .hmc_reorder_data (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_DATA , SEC_HMC_CFG_REORDER_DATA )), // Enable command reodering + .hmc_reorder_read (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_READ , SEC_HMC_CFG_REORDER_READ )), // Enable read command reordering if command reordering is enabled + .hmc_ctrl_reorder_rdata (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_RDATA , SEC_HMC_CFG_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .hmc_dbc0_reorder_rdata (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_RDATA , SEC_HMC_CFG_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .hmc_dbc1_reorder_rdata (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_RDATA , SEC_HMC_CFG_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .hmc_dbc2_reorder_rdata (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_RDATA , SEC_HMC_CFG_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .hmc_dbc3_reorder_rdata (`_sel_hmc_val(tile_i, PRI_HMC_CFG_REORDER_RDATA , SEC_HMC_CFG_REORDER_RDATA )), // Enable in-order read data return when read command reordering is enabled + .hmc_starve_limit (`_sel_hmc_val(tile_i, PRI_HMC_CFG_STARVE_LIMIT , SEC_HMC_CFG_STARVE_LIMIT )), // When command reordering is enabled, specifies the number of commands that can be served before a starved command is starved. + .hmc_enable_dqs_tracking (`_sel_hmc_val(tile_i, PRI_HMC_CFG_DQS_TRACKING_EN , SEC_HMC_CFG_DQS_TRACKING_EN )), // Enable DQS tracking + .hmc_arbiter_type (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ARBITER_TYPE , SEC_HMC_CFG_ARBITER_TYPE )), // Arbiter Type + .hmc_open_page_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_OPEN_PAGE_EN , SEC_HMC_CFG_OPEN_PAGE_EN )), // Unused + .hmc_geardn_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_GEAR_DOWN_EN , SEC_HMC_CFG_GEAR_DOWN_EN )), // Gear-down (DDR4) + .hmc_rld3_multibank_mode (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_MULTIBANK_MODE , SEC_HMC_CFG_RLD3_MULTIBANK_MODE )), // RLD3 multi-bank mode + .hmc_cfg_pinpong_mode (`_sel_hmc_def(tile_i, PRI_HMC_CFG_PING_PONG_MODE , SEC_HMC_CFG_PING_PONG_MODE ,"pingpong_off")), // Ping-Pong PHY mode + .hmc_ctrl_slot_rotate_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_ROTATE_EN , SEC_HMC_CFG_SLOT_ROTATE_EN )), // Command slot rotation + .hmc_dbc0_slot_rotate_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_ROTATE_EN , SEC_HMC_CFG_SLOT_ROTATE_EN )), // Command slot rotation + .hmc_dbc1_slot_rotate_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_ROTATE_EN , SEC_HMC_CFG_SLOT_ROTATE_EN )), // Command slot rotation + .hmc_dbc2_slot_rotate_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_ROTATE_EN , SEC_HMC_CFG_SLOT_ROTATE_EN )), // Command slot rotation + .hmc_dbc3_slot_rotate_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_ROTATE_EN , SEC_HMC_CFG_SLOT_ROTATE_EN )), // Command slot rotation + .hmc_ctrl_slot_offset (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SLOT_OFFSET , SEC_HMC_CFG_SLOT_OFFSET )), // Command slot offset + .hmc_dbc0_slot_offset (`_sel_hmc_lane(tile_i, 0, PRI_HMC_CFG_SLOT_OFFSET , SEC_HMC_CFG_SLOT_OFFSET )), // Command slot offset + .hmc_dbc1_slot_offset (`_sel_hmc_lane(tile_i, 1, PRI_HMC_CFG_SLOT_OFFSET , SEC_HMC_CFG_SLOT_OFFSET )), // Command slot offset + .hmc_dbc2_slot_offset (`_sel_hmc_lane(tile_i, 2, PRI_HMC_CFG_SLOT_OFFSET , SEC_HMC_CFG_SLOT_OFFSET )), // Command slot offset + .hmc_dbc3_slot_offset (`_sel_hmc_lane(tile_i, 3, PRI_HMC_CFG_SLOT_OFFSET , SEC_HMC_CFG_SLOT_OFFSET )), // Command slot offset + .hmc_col_cmd_slot (`_sel_hmc_val(tile_i, PRI_HMC_CFG_COL_CMD_SLOT , SEC_HMC_CFG_COL_CMD_SLOT )), // Command slot for column commands + .hmc_row_cmd_slot (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ROW_CMD_SLOT , SEC_HMC_CFG_ROW_CMD_SLOT )), // Command slot for row commands + .hmc_ctrl_rc_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_RC , SEC_HMC_CFG_ENABLE_RC )), // Enable rate-conversion feature + .hmc_dbc0_rc_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_RC , SEC_HMC_CFG_ENABLE_RC )), // Enable rate-conversion feature + .hmc_dbc1_rc_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_RC , SEC_HMC_CFG_ENABLE_RC )), // Enable rate-conversion feature + .hmc_dbc2_rc_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_RC , SEC_HMC_CFG_ENABLE_RC )), // Enable rate-conversion feature + .hmc_dbc3_rc_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ENABLE_RC , SEC_HMC_CFG_ENABLE_RC )), // Enable rate-conversion feature + .hmc_cs_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_CS_TO_CHIP_MAPPING , SEC_HMC_CFG_CS_TO_CHIP_MAPPING )), // Chip select mapping scheme + .hmc_rb_reserved_entry (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RB_RESERVED_ENTRY , SEC_HMC_CFG_RB_RESERVED_ENTRY )), // Number of entries reserved in read buffer before almost full is asserted. Should be set to 4 + 2 * user_pipe_stages + .hmc_wb_reserved_entry (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WB_RESERVED_ENTRY , SEC_HMC_CFG_WB_RESERVED_ENTRY )), // Number of entries reserved in write buffer before almost full is asserted. Should be set to 4 + 2 * user_pipe_stages + .hmc_tcl (`_sel_hmc_val(tile_i, PRI_HMC_CFG_TCL , SEC_HMC_CFG_TCL )), // Memory CAS latency + .hmc_power_saving_exit_cycles (`_sel_hmc_val(tile_i, PRI_HMC_CFG_POWER_SAVING_EXIT_CYC , SEC_HMC_CFG_POWER_SAVING_EXIT_CYC )), // The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR + .hmc_mem_clk_disable_entry_cycles (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC , SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC )), // Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed + .hmc_write_odt_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WRITE_ODT_CHIP , SEC_HMC_CFG_WRITE_ODT_CHIP )), // ODT scheme setting for write command + .hmc_read_odt_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_READ_ODT_CHIP , SEC_HMC_CFG_READ_ODT_CHIP )), // ODT scheme setting for read command + .hmc_wr_odt_on (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_ODT_ON , SEC_HMC_CFG_WR_ODT_ON )), // Indicates number of memory clock cycle gap between write command and ODT signal rising edge + .hmc_rd_odt_on (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_ODT_ON , SEC_HMC_CFG_RD_ODT_ON )), // Indicates number of memory clock cycle gap between read command and ODT signal rising edge + .hmc_wr_odt_period (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_ODT_PERIOD , SEC_HMC_CFG_WR_ODT_PERIOD )), // Indicates number of memory clock cycle write ODT signal should stay asserted after rising edge + .hmc_rd_odt_period (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_ODT_PERIOD , SEC_HMC_CFG_RD_ODT_PERIOD )), // Indicates number of memory clock cycle read ODT signal should stay asserted after rising edge + .hmc_rld3_refresh_seq0 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ0 , SEC_HMC_CFG_RLD3_REFRESH_SEQ0 )), // Banks to refresh for RLD3 in sequence 0. Must not be more than 4 banks + .hmc_rld3_refresh_seq1 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ1 , SEC_HMC_CFG_RLD3_REFRESH_SEQ1 )), // Banks to refresh for RLD3 in sequence 1. Must not be more than 4 banks + .hmc_rld3_refresh_seq2 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ2 , SEC_HMC_CFG_RLD3_REFRESH_SEQ2 )), // Banks to refresh for RLD3 in sequence 2. Must not be more than 4 banks + .hmc_rld3_refresh_seq3 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_REFRESH_SEQ3 , SEC_HMC_CFG_RLD3_REFRESH_SEQ3 )), // Banks to refresh for RLD3 in sequence 3. Must not be more than 4 banks + .hmc_srf_zqcal_disable (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SRF_ZQCAL_DISABLE , SEC_HMC_CFG_SRF_ZQCAL_DISABLE )), // Setting to disable ZQ Calibration after self refresh + .hmc_mps_zqcal_disable (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPS_ZQCAL_DISABLE , SEC_HMC_CFG_MPS_ZQCAL_DISABLE )), // Setting to disable ZQ Calibration after Maximum Power Saving exit + .hmc_short_dqstrk_ctrl_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN , SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN )), + .hmc_period_dqstrk_ctrl_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN , SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN )), + .hmc_period_dqstrk_interval (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL , SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL )), + .hmc_dqstrk_to_valid_last (`_sel_hmc_val(tile_i, PRI_HMC_CFG_DQSTRK_TO_VALID_LAST , SEC_HMC_CFG_DQSTRK_TO_VALID_LAST )), + .hmc_dqstrk_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_DQSTRK_TO_VALID , SEC_HMC_CFG_DQSTRK_TO_VALID )), + .hmc_rfsh_warn_threshold (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RFSH_WARN_THRESHOLD , SEC_HMC_CFG_RFSH_WARN_THRESHOLD )), + .hmc_mps_dqstrk_disable (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPS_DQSTRK_DISABLE , SEC_HMC_CFG_MPS_DQSTRK_DISABLE )), // Setting to disable DQS Tracking after Maximum Power Saving exit + .hmc_sb_cg_disable (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SB_CG_DISABLE , SEC_HMC_CFG_SB_CG_DISABLE )), // Setting to disable mem_ck gating during self refresh and deep power down + .hmc_user_rfsh_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_USER_RFSH_EN , SEC_HMC_CFG_USER_RFSH_EN )), // Setting to enable user refresh + .hmc_srf_autoexit_en (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SRF_AUTOEXIT_EN , SEC_HMC_CFG_SRF_AUTOEXIT_EN )), // Setting to enable controller to exit Self Refresh when new command is detected + .hmc_srf_entry_exit_block (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK , SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK )), // Blocking arbiter from issuing commands + .hmc_sb_ddr4_mr3 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SB_DDR4_MR3 , SEC_HMC_CFG_SB_DDR4_MR3 )), // DDR4 MR3 + .hmc_sb_ddr4_mr4 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SB_DDR4_MR4 , SEC_HMC_CFG_SB_DDR4_MR4 )), // DDR4 MR4 + .hmc_sb_ddr4_mr5 (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SB_DDR4_MR5 , SEC_HMC_CFG_SB_DDR4_MR5 )), // DDR4 MR5 + .hmc_ddr4_mps_addr_mirror (`_sel_hmc_val(tile_i, PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR , SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR )), // DDR4 MPS Address Mirror + .hmc_mem_if_coladdr_width (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH , SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH )), // Column address width + .hmc_mem_if_rowaddr_width (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH , SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH )), // Row address width + .hmc_mem_if_bankaddr_width (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH , SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH )), // Bank address width + .hmc_mem_if_bgaddr_width (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH , SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH )), // Bank group address width + .hmc_local_if_cs_width (`_sel_hmc_val(tile_i, PRI_HMC_CFG_LOCAL_IF_CS_WIDTH , SEC_HMC_CFG_LOCAL_IF_CS_WIDTH )), // Address width in bits required to access every CS in interface + .hmc_addr_order (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ADDR_ORDER , SEC_HMC_CFG_ADDR_ORDER )), // Mapping of Avalon address to physical address of the memory device + .hmc_act_to_rdwr (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ACT_TO_RDWR , SEC_HMC_CFG_ACT_TO_RDWR )), // Activate to Read/write command timing (e.g. tRCD) + .hmc_act_to_pch (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ACT_TO_PCH , SEC_HMC_CFG_ACT_TO_PCH )), // Active to precharge (e.g. tRAS) + .hmc_act_to_act (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ACT_TO_ACT , SEC_HMC_CFG_ACT_TO_ACT )), // Active to activate timing on same bank (e.g. tRC) + .hmc_act_to_act_diff_bank (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK , SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK )), // Active to activate timing on different banks, for DDR4 same bank group (e.g. tRRD) + .hmc_act_to_act_diff_bg (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG , SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG )), // Active to activate timing on different bank groups, DDR4 only + .hmc_rd_to_rd (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_RD , SEC_HMC_CFG_RD_TO_RD )), // Read to read command timing on same bank (e.g. tCCD) + .hmc_rd_to_rd_diff_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP , SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP )), // Read to read command timing on different chips + .hmc_rd_to_rd_diff_bg (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_RD_DIFF_BG , SEC_HMC_CFG_RD_TO_RD_DIFF_BG )), // Read to read command timing on different chips + .hmc_rd_to_wr (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_WR , SEC_HMC_CFG_RD_TO_WR )), // Read to write command timing on same bank + .hmc_rd_to_wr_diff_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP , SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP )), // Read to write command timing on different chips + .hmc_rd_to_wr_diff_bg (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_WR_DIFF_BG , SEC_HMC_CFG_RD_TO_WR_DIFF_BG )), // Read to write command timing on different bank groups + .hmc_rd_to_pch (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_TO_PCH , SEC_HMC_CFG_RD_TO_PCH )), // Read to precharge command timing (e.g. tRTP) + .hmc_rd_ap_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RD_AP_TO_VALID , SEC_HMC_CFG_RD_AP_TO_VALID )), // Read command with autoprecharge to data valid timing + .hmc_wr_to_wr (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_WR , SEC_HMC_CFG_WR_TO_WR )), // Write to write command timing on same bank. (e.g. tCCD) + .hmc_wr_to_wr_diff_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP , SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP )), // Write to write command timing on different chips. + .hmc_wr_to_wr_diff_bg (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_WR_DIFF_BG , SEC_HMC_CFG_WR_TO_WR_DIFF_BG )), // Write to write command timing on different bank groups. + .hmc_wr_to_rd (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_RD , SEC_HMC_CFG_WR_TO_RD )), // Write to read command timing. (e.g. tWTR) + .hmc_wr_to_rd_diff_chip (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP , SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP )), // Write to read command timing on different chips. + .hmc_wr_to_rd_diff_bg (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_RD_DIFF_BG , SEC_HMC_CFG_WR_TO_RD_DIFF_BG )), // Write to read command timing on different bank groups + .hmc_wr_to_pch (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_TO_PCH , SEC_HMC_CFG_WR_TO_PCH )), // Write to precharge command timing. (e.g. tWR) + .hmc_wr_ap_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_WR_AP_TO_VALID , SEC_HMC_CFG_WR_AP_TO_VALID )), // Write with autoprecharge to valid command timing. + .hmc_pch_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PCH_TO_VALID , SEC_HMC_CFG_PCH_TO_VALID )), // Precharge to valid command timing. (e.g. tRP) + .hmc_pch_all_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PCH_ALL_TO_VALID , SEC_HMC_CFG_PCH_ALL_TO_VALID )), // Precharge all to banks being ready for bank activation command. + .hmc_arf_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ARF_TO_VALID , SEC_HMC_CFG_ARF_TO_VALID )), // Auto Refresh to valid DRAM command window. + .hmc_pdn_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PDN_TO_VALID , SEC_HMC_CFG_PDN_TO_VALID )), // Power down to valid bank command window. + .hmc_srf_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SRF_TO_VALID , SEC_HMC_CFG_SRF_TO_VALID )), // Self-refresh to valid bank command window. (e.g. tRFC) + .hmc_srf_to_zq_cal (`_sel_hmc_val(tile_i, PRI_HMC_CFG_SRF_TO_ZQ_CAL , SEC_HMC_CFG_SRF_TO_ZQ_CAL )), // Self refresh to ZQ calibration window + .hmc_arf_period (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ARF_PERIOD , SEC_HMC_CFG_ARF_PERIOD )), // Auto-refresh period (e.g. tREFI) + .hmc_pdn_period (`_sel_hmc_val(tile_i, PRI_HMC_CFG_PDN_PERIOD , SEC_HMC_CFG_PDN_PERIOD )), // Number of controller cycles before automatic power down. + .hmc_zqcl_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ZQCL_TO_VALID , SEC_HMC_CFG_ZQCL_TO_VALID )), // Long ZQ calibration to valid + .hmc_zqcs_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_ZQCS_TO_VALID , SEC_HMC_CFG_ZQCS_TO_VALID )), // Short ZQ calibration to valid + .hmc_mrs_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MRS_TO_VALID , SEC_HMC_CFG_MRS_TO_VALID )), // Mode Register Setting to valid (e.g. tMRD) + .hmc_mps_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPS_TO_VALID , SEC_HMC_CFG_MPS_TO_VALID )), // Max Power Saving to Valid + .hmc_mrr_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MRR_TO_VALID , SEC_HMC_CFG_MRR_TO_VALID )), // Mode Register Read to Valid + .hmc_mpr_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPR_TO_VALID , SEC_HMC_CFG_MPR_TO_VALID )), // Multi Purpose Register Read to Valid + .hmc_mps_exit_cs_to_cke (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE , SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE )), // Max Power Saving CS to CKE + .hmc_mps_exit_cke_to_cs (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS , SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS )), // Max Power Saving CKE to CS + .hmc_rld3_multibank_ref_delay (`_sel_hmc_val(tile_i, PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY , SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY )), // RLD3 Multibank Refresh Delay + .hmc_mmr_cmd_to_valid (`_sel_hmc_val(tile_i, PRI_HMC_CFG_MMR_CMD_TO_VALID , SEC_HMC_CFG_MMR_CMD_TO_VALID )), // MMR cmd to valid delay + .hmc_4_act_to_act (`_sel_hmc_val(tile_i, PRI_HMC_CFG_4_ACT_TO_ACT , SEC_HMC_CFG_4_ACT_TO_ACT )), // The four-activate window timing parameter. (e.g. tFAW) + .hmc_16_act_to_act (`_sel_hmc_val(tile_i, PRI_HMC_CFG_16_ACT_TO_ACT , SEC_HMC_CFG_16_ACT_TO_ACT )), // The 16-activate window timing parameter (RLD3) (e.g. tSAW) + .mode ("tile_ddr") + + ) tile_ctrl_inst ( + + // Reset + .global_reset_n (global_reset_n_int), + + // PLL -> Tiles + .pll_locked_in (pll_locked), + .pll_vco_in (phy_clk_phs), // FR clocks routed on PHY clock tree + .phy_clk_in (phy_clk), // PHY clock tree inputs + + // Clock Phase Alignment + .pa_core_clk_in (all_tiles_core_clks_fb_in[tile_i]), // Input to CPA through feedback path + .pa_core_clk_out (all_tiles_core_clks_out[tile_i]), // Output from CPA to core clock networks + .pa_locked (all_tiles_core_clks_locked[tile_i]), // Lock signal from CPA to core + .pa_reset_n (IS_HPS ? 1'b1 : global_reset_n_int), // Connected to global reset from core in non-HPS mode + .pa_core_in (12'b000000000000), // Control code word + .pa_fbclk_in (phy_fb_clk_to_tile), // PLL signal going into PHY feedback clock + .pa_sync_data_bot_in (pa_sync_data_up_chain[`_get_chain_index_for_tile(tile_i)]), + .pa_sync_data_top_out (pa_sync_data_up_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_data_top_in (pa_sync_data_dn_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_data_bot_out (pa_sync_data_dn_chain[`_get_chain_index_for_tile(tile_i)]), + .pa_sync_clk_bot_in (pa_sync_clk_up_chain [`_get_chain_index_for_tile(tile_i)]), + .pa_sync_clk_top_out (pa_sync_clk_up_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_clk_top_in (pa_sync_clk_dn_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .pa_sync_clk_bot_out (pa_sync_clk_dn_chain [`_get_chain_index_for_tile(tile_i)]), + .pa_dprio_rst_n ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_rst_n : 1'b0)), + .pa_dprio_clk ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_clk : 1'b0)), + .pa_dprio_read ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_read : 1'b0)), + .pa_dprio_reg_addr ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_reg_addr : 9'b0)), + .pa_dprio_write ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_write : 1'b0)), + .pa_dprio_writedata ((tile_i == PRI_AC_TILE_INDEX ? pa_dprio_writedata : 8'b0)), + .pa_dprio_block_select (all_tiles_pa_dprio_block_select[tile_i]), + .pa_dprio_readdata (all_tiles_pa_dprio_readdata[tile_i]), + + // PHY clock signals going from tiles to lanes + .phy_clk_out0 ({all_tiles_t2l_phy_clk[tile_i][0], all_tiles_t2l_phy_clk_phs[tile_i][0]}), // PHY clocks to lane 0 + .phy_clk_out1 ({all_tiles_t2l_phy_clk[tile_i][1], all_tiles_t2l_phy_clk_phs[tile_i][1]}), // PHY clocks to lane 1 + .phy_clk_out2 ({all_tiles_t2l_phy_clk[tile_i][2], all_tiles_t2l_phy_clk_phs[tile_i][2]}), // PHY clocks to lane 2 + .phy_clk_out3 ({all_tiles_t2l_phy_clk[tile_i][3], all_tiles_t2l_phy_clk_phs[tile_i][3]}), // PHY clocks to lane 3 + .phy_fbclk_out (all_tiles_phy_fb_clk_to_pll[tile_i]), // PHY clock signal going into the M counter of PLL to complete the feedback loop + + // DLL Interface + .dll_clk_in (pll_dll_clk), // PLL clock feeding to DLL + .dll_clk_out0 (all_tiles_dll_clk_out[tile_i][0]), // DLL clock to lane 0 + .dll_clk_out1 (all_tiles_dll_clk_out[tile_i][1]), // DLL clock to lane 1 + .dll_clk_out2 (all_tiles_dll_clk_out[tile_i][2]), // DLL clock to lane 2 + .dll_clk_out3 (all_tiles_dll_clk_out[tile_i][3]), // DLL clock to lane 3 + + // Calibration bus between Nios and sequencer (a.k.a slow Avalon-MM bus) + .cal_avl_in (cal_bus_avl_up_chain [`_get_chain_index_for_tile(tile_i)]), + .cal_avl_out (cal_bus_avl_up_chain [`_get_chain_index_for_tile(tile_i) + 1]), + .cal_avl_rdata_in (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_tile(tile_i) + 1]), + .cal_avl_rdata_out (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_tile(tile_i)]), + + .core2ctl_avl0 (`_sel_hmc_def(tile_i, core2ctl_avl_0, core2ctl_avl_1, 60'b0)), + .core2ctl_avl1 (60'b0), + .core2ctl_avl_rd_data_ready (`_sel_hmc_def(tile_i, core2ctl_avl_rd_data_ready_0, core2ctl_avl_rd_data_ready_1, 1'b0)), + .ctl2core_avl_cmd_ready (all_tiles_ctl2core_avl_cmd_ready[tile_i]), + .ctl2core_avl_rdata_id (all_tiles_ctl2core_avl_rdata_id[tile_i]), + + .core2ctl_sideband (`_sel_hmc_def(tile_i, core2ctl_sideband_0, core2ctl_sideband_1, 42'b0)), + .ctl2core_sideband (all_tiles_ctl2core_sideband[tile_i]), + + // Interface between HMC and lanes + .afi_cmd_bus (t2l_ac_hmc), + + // DQS buses + // There are 8 x4 DQS buses per tile, with two pairs of input DQS per lane. + .dqs_in_x4_a_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 0] : 1'b0), + .dqs_in_x4_a_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 1] : 1'b0), + .dqs_in_x4_a_2 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 2] : 1'b0), + .dqs_in_x4_a_3 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqs[(tile_i * LANES_PER_TILE) + 3] : 1'b0), + .dqs_in_x4_b_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 0] : 1'b0), + .dqs_in_x4_b_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 1] : 1'b0), + .dqs_in_x4_b_2 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 2] : 1'b0), + .dqs_in_x4_b_3 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? b2t_dqsb[(tile_i * LANES_PER_TILE) + 3] : 1'b0), + .dqs_out_x4_a_lane0 (t2l_dqsbus_x4[0][0]), + .dqs_out_x4_b_lane0 (t2l_dqsbus_x4[0][1]), + .dqs_out_x4_a_lane1 (t2l_dqsbus_x4[1][0]), + .dqs_out_x4_b_lane1 (t2l_dqsbus_x4[1][1]), + .dqs_out_x4_a_lane2 (t2l_dqsbus_x4[2][0]), + .dqs_out_x4_b_lane2 (t2l_dqsbus_x4[2][1]), + .dqs_out_x4_a_lane3 (t2l_dqsbus_x4[3][0]), + .dqs_out_x4_b_lane3 (t2l_dqsbus_x4[3][1]), + + // There are 4 x8/x9 DQS buses per tile, with one pair of input DQS per lane. + .dqs_in_x8_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 0], b2t_dqs[(tile_i * LANES_PER_TILE) + 0]} : 2'b0), + .dqs_in_x8_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 1], b2t_dqs[(tile_i * LANES_PER_TILE) + 1]} : 2'b0), + .dqs_in_x8_2 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 2], b2t_dqs[(tile_i * LANES_PER_TILE) + 2]} : 2'b0), + .dqs_in_x8_3 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 3], b2t_dqs[(tile_i * LANES_PER_TILE) + 3]} : 2'b0), + .dqs_out_x8_lane0 (t2l_dqsbus_x8[0]), + .dqs_out_x8_lane1 (t2l_dqsbus_x8[1]), + .dqs_out_x8_lane2 (t2l_dqsbus_x8[2]), + .dqs_out_x8_lane3 (t2l_dqsbus_x8[3]), + + // There are 2 x16/x18 DQS buses per tile, and the input DQS must originate from lane 1 and 3 + .dqs_in_x18_0 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 1], b2t_dqs[(tile_i * LANES_PER_TILE) + 1]} : 2'b0), + .dqs_in_x18_1 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 3], b2t_dqs[(tile_i * LANES_PER_TILE) + 3]} : 2'b0), + .dqs_out_x18_lane0 (t2l_dqsbus_x18[0]), + .dqs_out_x18_lane1 (t2l_dqsbus_x18[1]), + .dqs_out_x18_lane2 (t2l_dqsbus_x18[2]), + .dqs_out_x18_lane3 (t2l_dqsbus_x18[3]), + + // There is 1 x32/x36 DQS bus per tile, and the input DQS must originate from lane 1 + .dqs_in_x36 (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? {b2t_dqsb[(tile_i * LANES_PER_TILE) + 1], b2t_dqs[(tile_i * LANES_PER_TILE) + 1]} : 2'b0), + .dqs_out_x36_lane0 (t2l_dqsbus_x36[0]), + .dqs_out_x36_lane1 (t2l_dqsbus_x36[1]), + .dqs_out_x36_lane2 (t2l_dqsbus_x36[2]), + .dqs_out_x36_lane3 (t2l_dqsbus_x36[3]), + + // Data buffer control signals + .ctl2dbc0 (all_tiles_ctl2dbc0_dn_chain[tile_i]), + .ctl2dbc1 (all_tiles_ctl2dbc1_up_chain[tile_i + 1]), + .ctl2dbc_in_up (all_tiles_ctl2dbc0_dn_chain[tile_i + 1]), + .ctl2dbc_in_down (all_tiles_ctl2dbc1_up_chain[tile_i]), + .dbc2ctl0 (l2t_dbc2ctl[0]), + .dbc2ctl1 (l2t_dbc2ctl[1]), + .dbc2ctl2 (l2t_dbc2ctl[2]), + .dbc2ctl3 (l2t_dbc2ctl[3]), + .cfg_dbc0 (t2l_cfg_dbc[0]), + .cfg_dbc1 (t2l_cfg_dbc[1]), + .cfg_dbc2 (t2l_cfg_dbc[2]), + .cfg_dbc3 (t2l_cfg_dbc[3]), + .dbc2core_wr_data_rdy0 (l2core_wr_data_rdy_ast_nonabphy[tile_i][0]), + .dbc2core_wr_data_rdy1 (l2core_wr_data_rdy_ast_nonabphy[tile_i][1]), + .dbc2core_wr_data_rdy2 (l2core_wr_data_rdy_ast_nonabphy[tile_i][2]), + .dbc2core_wr_data_rdy3 (l2core_wr_data_rdy_ast_nonabphy[tile_i][3]), + + // Ping-Pong PHY related signals + .ping_pong_in (all_tiles_ping_pong_up_chain[tile_i]), + .ping_pong_out (all_tiles_ping_pong_up_chain[tile_i + 1]), + + // MMR-related signals + .mmr_in (`_sel_hmc_def(tile_i, core2ctl_mmr_0, core2ctl_mmr_1, 51'b0)), + .mmr_out (all_tiles_ctl2core_mmr[tile_i]), + + // Miscellaneous signals + .afi_core2ctl (all_tiles_c2t_afi[tile_i]), + .afi_ctl2core (all_tiles_t2c_afi[tile_i]), + .seq2core_reset_n (t2c_seq2core_reset_n[tile_i]), + .ctl_mem_clk_disable (), + .afi_lane0_to_ctl (16'b0), + .afi_lane1_to_ctl (16'b0), + .afi_lane2_to_ctl (16'b0), + .afi_lane3_to_ctl (16'b0), + .rdata_en_full_core (4'b0), + .mrnk_read_core (16'b0), + .test_dbg_out () + ); + + for (lane_i = 0; lane_i < LANES_PER_TILE; ++lane_i) + begin: lane_gen + + (* altera_attribute = "-name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 2; -name MAX_WIRES_FOR_PERIPHERY_CORE_TRANSFER 1" *) + twentynm_io_12_lane #( + .silicon_rev (SILICON_REV), + .fast_interpolator_sim (USE_FAST_INTERPOLATOR_SIM), + .hps_ctrl_en (IS_HPS ? "true" : "false"), + .phy_clk_phs_freq (PLL_VCO_FREQ_MHZ_INT_CAPPED), + .mode_rate_in (`_get_lane_mode_rate_in), + .mode_rate_out (`_get_lane_mode_rate_out), + .pipe_latency (8'b00000000), // Don't-care - always set by calibration software + .dqs_enable_delay (6'b000000), // Don't-care - always set by calibration software + .rd_valid_delay (7'b0000000), // Don't-care - always set by calibration software + .phy_clk_sel (0), // Always use phy_clk[0] + .pin_0_initial_out ("initial_out_z"), + .pin_0_output_phase (13'b0000000000000), + .pin_0_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 0)), + .pin_0_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 0)), + .pin_0_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 0)), + .pin_0_dqs_x4_mode (`_get_pin_dqs_x4_mode_0), + .pin_0_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 0)), + .pin_1_initial_out ("initial_out_z"), + .pin_1_output_phase (13'b0000000000000), + .pin_1_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 1)), + .pin_1_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 1)), + .pin_1_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 1)), + .pin_1_dqs_x4_mode (`_get_pin_dqs_x4_mode_1), + .pin_1_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 1)), + .pin_2_initial_out ("initial_out_z"), + .pin_2_output_phase (13'b0000000000000), + .pin_2_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 2)), + .pin_2_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 2)), + .pin_2_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 2)), + .pin_2_dqs_x4_mode (`_get_pin_dqs_x4_mode_2), + .pin_2_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 2)), + .pin_3_initial_out ("initial_out_z"), + .pin_3_output_phase (13'b0000000000000), + .pin_3_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 3)), + .pin_3_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 3)), + .pin_3_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 3)), + .pin_3_dqs_x4_mode (`_get_pin_dqs_x4_mode_3), + .pin_3_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 3)), + .pin_4_initial_out ("initial_out_z"), + .pin_4_output_phase (13'b0000000000000), + .pin_4_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 4)), + .pin_4_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 4)), + .pin_4_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 4)), + .pin_4_dqs_x4_mode (`_get_pin_dqs_x4_mode_4), + .pin_4_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 4)), + .pin_5_initial_out ("initial_out_z"), + .pin_5_output_phase (13'b0000000000000), + .pin_5_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 5)), + .pin_5_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 5)), + .pin_5_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 5)), + .pin_5_dqs_x4_mode (`_get_pin_dqs_x4_mode_5), + .pin_5_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 5)), + .pin_6_initial_out ("initial_out_z"), + .pin_6_output_phase (13'b0000000000000), + .pin_6_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 6)), + .pin_6_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 6)), + .pin_6_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 6)), + .pin_6_dqs_x4_mode (`_get_pin_dqs_x4_mode_6), + .pin_6_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 6)), + .pin_7_initial_out ("initial_out_z"), + .pin_7_output_phase (13'b0000000000000), + .pin_7_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 7)), + .pin_7_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 7)), + .pin_7_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 7)), + .pin_7_dqs_x4_mode (`_get_pin_dqs_x4_mode_7), + .pin_7_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 7)), + .pin_8_initial_out ("initial_out_z"), + .pin_8_output_phase (13'b0000000000000), + .pin_8_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 8)), + .pin_8_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 8)), + .pin_8_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 8)), + .pin_8_dqs_x4_mode (`_get_pin_dqs_x4_mode_8), + .pin_8_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 8)), + .pin_9_initial_out ("initial_out_z"), + .pin_9_output_phase (13'b0000000000000), + .pin_9_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 9)), + .pin_9_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 9)), + .pin_9_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 9)), + .pin_9_dqs_x4_mode (`_get_pin_dqs_x4_mode_9), + .pin_9_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 9)), + .pin_10_initial_out ("initial_out_z"), + .pin_10_output_phase (13'b0000000000000), + .pin_10_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 10)), + .pin_10_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 10)), + .pin_10_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 10)), + .pin_10_dqs_x4_mode (`_get_pin_dqs_x4_mode_10), + .pin_10_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 10)), + .pin_11_initial_out ("initial_out_z"), + .pin_11_output_phase (13'b0000000000000), + .pin_11_mode_ddr (`_get_pin_ddr_str (tile_i, lane_i, 11)), + .pin_11_oct_mode (`_get_pin_oct_mode_str (tile_i, lane_i, 11)), + .pin_11_data_in_mode (`_get_pin_data_in_mode_str(tile_i, lane_i, 11)), + .pin_11_dqs_x4_mode (`_get_pin_dqs_x4_mode_11), + .pin_11_gpio_or_ddr (`_get_pin_gpio_or_ddr (tile_i, lane_i, 11)), + .avl_base_addr (`_get_lane_tid(tile_i, lane_i)), + .avl_ena ("true"), + .db_hmc_or_core (`_get_hmc_or_core), + .db_dbi_sel (11), + .db_dbi_wr_en (`_get_dbi_wr_en(tile_i, lane_i)), + .db_dbi_rd_en (`_get_dbi_rd_en(tile_i, lane_i)), + .db_crc_dq0 (`_get_crc_pin_pos_0), + .db_crc_dq1 (`_get_crc_pin_pos_1), + .db_crc_dq2 (`_get_crc_pin_pos_2), + .db_crc_dq3 (`_get_crc_pin_pos_3), + .db_crc_dq4 (`_get_crc_pin_pos_4), + .db_crc_dq5 (`_get_crc_pin_pos_5), + .db_crc_dq6 (`_get_crc_pin_pos_6), + .db_crc_dq7 (`_get_crc_pin_pos_7), + .db_crc_dq8 (`_get_crc_pin_pos_8), + .db_crc_x4_or_x8_or_x9 (`_get_crc_x4_or_x8_or_x9), + .db_crc_en (`_get_crc_en(tile_i, lane_i)), + .db_rwlat_mode ("avl_vlu"), // wlat/rlat set dynamically via Avalon by Nios (instead of through CSR) + .db_afi_wlat_vlu (6'b000000), // Unused - wlat set dynamically via Avalon by Nios + .db_afi_rlat_vlu (6'b000000), // Unused - rlat set dynamically via Avalon by Nios + .db_ptr_pipeline_depth (`_get_db_ptr_pipe_depth(tile_i, lane_i)), // Additional latency to compensate for distance from HMC + .db_seq_rd_en_full_pipeline (`_get_db_seq_rd_en_full_pipeline(tile_i, lane_i)), // Additional latency to compensate for distance from sequencer + .db_preamble_mode (PREAMBLE_MODE), + .db_reset_auto_release ("avl_release"), // Reset sequencer controlled via Avalon by Nios + .db_data_alignment_mode (`_get_db_data_alignment_mode), // Data alignment mode (enabled IFF HMC) + .db_db2core_registered ("true"), + .db_core_or_hmc2db_registered ("false"), + .dbc_core_clk_sel (USE_HMC_RC_OR_DP ? 1 : 0), // Use phy_clk1 if HMC dual-port or rate-converter is used, use phy_clk0 otherwise + .dbc_wb_reserved_entry (DBC_WB_RESERVED_ENTRY), + .db_pin_0_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 0)), + .db_pin_0_mode (`_get_pin_wdb_str (tile_i, lane_i, 0)), + .db_pin_0_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 0)), + .db_pin_0_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 0)), + .db_pin_0_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 0)), + .db_pin_0_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 0)), + .db_pin_0_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 0)), + .db_pin_1_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 1)), + .db_pin_1_mode (`_get_pin_wdb_str (tile_i, lane_i, 1)), + .db_pin_1_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 1)), + .db_pin_1_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 1)), + .db_pin_1_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 1)), + .db_pin_1_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 1)), + .db_pin_1_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 1)), + .db_pin_2_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 2)), + .db_pin_2_mode (`_get_pin_wdb_str (tile_i, lane_i, 2)), + .db_pin_2_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 2)), + .db_pin_2_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 2)), + .db_pin_2_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 2)), + .db_pin_2_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 2)), + .db_pin_2_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 2)), + .db_pin_3_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 3)), + .db_pin_3_mode (`_get_pin_wdb_str (tile_i, lane_i, 3)), + .db_pin_3_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 3)), + .db_pin_3_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 3)), + .db_pin_3_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 3)), + .db_pin_3_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 3)), + .db_pin_3_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 3)), + .db_pin_4_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 4)), + .db_pin_4_mode (`_get_pin_wdb_str (tile_i, lane_i, 4)), + .db_pin_4_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 4)), + .db_pin_4_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 4)), + .db_pin_4_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 4)), + .db_pin_4_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 4)), + .db_pin_4_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 4)), + .db_pin_5_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 5)), + .db_pin_5_mode (`_get_pin_wdb_str (tile_i, lane_i, 5)), + .db_pin_5_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 5)), + .db_pin_5_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 5)), + .db_pin_5_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 5)), + .db_pin_5_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 5)), + .db_pin_5_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 5)), + .db_pin_6_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 6)), + .db_pin_6_mode (`_get_pin_wdb_str (tile_i, lane_i, 6)), + .db_pin_6_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 6)), + .db_pin_6_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 6)), + .db_pin_6_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 6)), + .db_pin_6_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 6)), + .db_pin_6_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 6)), + .db_pin_7_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 7)), + .db_pin_7_mode (`_get_pin_wdb_str (tile_i, lane_i, 7)), + .db_pin_7_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 7)), + .db_pin_7_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 7)), + .db_pin_7_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 7)), + .db_pin_7_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 7)), + .db_pin_7_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 7)), + .db_pin_8_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 8)), + .db_pin_8_mode (`_get_pin_wdb_str (tile_i, lane_i, 8)), + .db_pin_8_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 8)), + .db_pin_8_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 8)), + .db_pin_8_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 8)), + .db_pin_8_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 8)), + .db_pin_8_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 8)), + .db_pin_9_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 9)), + .db_pin_9_mode (`_get_pin_wdb_str (tile_i, lane_i, 9)), + .db_pin_9_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 9)), + .db_pin_9_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 9)), + .db_pin_9_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 9)), + .db_pin_9_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 9)), + .db_pin_9_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 9)), + .db_pin_10_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 10)), + .db_pin_10_mode (`_get_pin_wdb_str (tile_i, lane_i, 10)), + .db_pin_10_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 10)), + .db_pin_10_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 10)), + .db_pin_10_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 10)), + .db_pin_10_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 10)), + .db_pin_10_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 10)), + .db_pin_11_ac_hmc_data_override_ena (`_get_pin_ac_hmc_data_override_ena (tile_i, lane_i, 11)), + .db_pin_11_mode (`_get_pin_wdb_str (tile_i, lane_i, 11)), + .db_pin_11_in_bypass (`_get_pin_db_in_bypass (tile_i, lane_i, 11)), + .db_pin_11_out_bypass (`_get_pin_db_out_bypass (tile_i, lane_i, 11)), + .db_pin_11_oe_bypass (`_get_pin_db_oe_bypass (tile_i, lane_i, 11)), + .db_pin_11_oe_invert (`_get_pin_invert_oe (tile_i, lane_i, 11)), + .db_pin_11_wr_invert (`_get_pin_invert_wr (tile_i, lane_i, 11)), + .dll_rst_en (IS_HPS ? "dll_rst_dis" : "dll_rst_en"), + .dll_en ("dll_en"), + .dll_core_updnen ("core_updn_dis"), + .dll_ctlsel (`_get_dll_ctlsel), + .dll_ctl_static (`_get_dll_ctl_static), + .dqs_lgc_dqs_b_en (`_get_dqs_b_en), // Must be enabled for complimentary (non differential) read clock + .dqs_lgc_dqs_a_interp_en ("false"), // This enables read capture using an internal clock - never used by EMIF + .dqs_lgc_dqs_b_interp_en ("false"), // This enables read capture using an internal clock - never used by EMIF + .dqs_lgc_swap_dqs_a_b (SWAP_DQS_A_B), // This is used by QDR2 which may have fractional (1.5 or 2.5 cyc) read latencies + .dqs_lgc_pvt_input_delay_a (10'b00000_00000), // Phase shift to center read clock/strobe signal in read window (DQS-A bus). Overriden by Nios during calibration. + .dqs_lgc_pvt_input_delay_b (10'b00000_00000), // Phase shift to center read clock/strobe signal in read window (DQS-B bus). Overriden by Nios during calibration. + .dqs_lgc_enable_toggler (`_get_preamble_track_dqs_enable_mode), // Tracking Mode + .dqs_lgc_phase_shift_b (13'b00000_0000_0000), // Delay to read clock/strobe gating signal. Overriden by Nios during calibration. + .dqs_lgc_phase_shift_a (13'b00000_0000_0000), // Delay to read clock/strobe gating signal. Overriden by Nios during calibration. + .dqs_lgc_pack_mode (DQS_PACK_MODE), + .oct_size (OCT_SIZE), + .dqs_lgc_pst_preamble_mode (`_get_pst_preamble_mode), + .dqs_lgc_pst_en_shrink (`_get_pst_en_shrink), + .dqs_lgc_broadcast_enable ("disable_broadcast"), + .dqs_lgc_burst_length (`_get_dqs_lgc_burst_length), + .dqs_lgc_ddr4_search (`_get_ddr4_search), + .dqs_lgc_count_threshold (7'b0011000), + .pingpong_primary (`_sel_hmc_lane(tile_i, lane_i, "true", "false")), + .pingpong_secondary (`_sel_hmc_lane(tile_i, lane_i, "false", "true")) + + ) lane_inst ( + + // PLL/DLL/PVT interface + .pll_locked (pll_locked), + .dll_ref_clk (all_tiles_dll_clk_out[tile_i][lane_i]), + .core_dll (core2dll), + .dll_core (), + .ioereg_locked (), + + // Clocks + .phy_clk (all_tiles_t2l_phy_clk[tile_i][lane_i]), + .phy_clk_phs (all_tiles_t2l_phy_clk_phs[tile_i][lane_i]), + + // Clock Phase Alignment + .sync_data_bot_in (pa_sync_data_up_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_data_top_out (pa_sync_data_up_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_data_top_in (pa_sync_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_data_bot_out (pa_sync_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_clk_bot_in (pa_sync_clk_up_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + .sync_clk_top_out (pa_sync_clk_up_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_clk_top_in (pa_sync_clk_dn_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .sync_clk_bot_out (pa_sync_clk_dn_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + + // DQS bus from tile. Connections are only made for the data lanes (as captured by the macro) + .dqs_in (`_get_dqsin(tile_i, lane_i)), + + // Interface to I/O buffers + .oct_enable (l2b_dtc_nonabphy [tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_oe (l2b_oe_nonabphy [tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_out (l2b_data_nonabphy[tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + .data_in (b2l_data[tile_i * PINS_PER_LANE * LANES_PER_TILE + lane_i * PINS_PER_LANE +: PINS_PER_LANE]), + + // Interface to core + .data_from_core (core2l_data[tile_i][lane_i]), + .data_to_core (l2core_data_nonabphy[tile_i][lane_i]), + // core2l_oe is inverted before feeding into the lane because + // oe_invert is always set to true as required by HMC and sequencer + .oe_from_core (~core2l_oe[tile_i][lane_i]), + .rdata_en_full_core ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_RDATA || `_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WRDATA) ? core2l_rdata_en_full[tile_i][lane_i] : 4'b0), + .mrnk_read_core ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_RDATA || `_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WRDATA) ? core2l_mrnk_read[tile_i][lane_i] : 16'b0), + .mrnk_write_core ((`_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WDATA || `_get_lane_usage(tile_i, lane_i) == LANE_USAGE_WRDATA) ? core2l_mrnk_write[tile_i][lane_i] : 16'b0), + .rdata_valid_core (l2core_rdata_valid_nonabphy[tile_i][lane_i]), + .afi_wlat_core (l2core_afi_wlat_nonabphy[tile_i][lane_i]), + .afi_rlat_core (l2core_afi_rlat_nonabphy[tile_i][lane_i]), + + // Data Buffer Interface to Core + .dbc2core_rd_data_vld0 (l2core_rd_data_vld_avl0_nonabphy[tile_i][lane_i]), + .dbc2core_rd_data_vld1 (), + .core2dbc_wr_data_vld0 (`_get_core2dbc_wr_data_vld(tile_i, lane_i)), + .core2dbc_wr_data_vld1 (1'b0), + .dbc2core_wr_data_rdy (l2core_wr_data_rdy_ast_nonabphy [tile_i][lane_i]), + .core2dbc_rd_data_rdy (`_get_core2dbc_rd_data_rdy(tile_i, lane_i)), + .dbc2core_wb_pointer (l2core_wb_pointer_for_ecc_nonabphy[tile_i][lane_i]), + .core2dbc_wr_ecc_info (`_get_core2dbc_wr_ecc_info(tile_i, lane_i)), + .dbc2core_rd_type (), + + // Calibration bus between Nios and sequencer (a.k.a slow Avalon-MM bus) + .reset_n (global_reset_n_int), + .cal_avl_in (cal_bus_avl_up_chain [`_get_chain_index_for_lane(tile_i, lane_i)]), + .cal_avl_out (cal_bus_avl_up_chain [`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .cal_avl_readdata_in (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i) + 1]), + .cal_avl_readdata_out (cal_bus_avl_read_data_dn_chain[`_get_chain_index_for_lane(tile_i, lane_i)]), + + // HMC interface + .ac_hmc (`_get_ac_hmc(tile_i, lane_i)), + .ctl2dbc0 (all_tiles_ctl2dbc0_dn_chain[tile_i]), + .ctl2dbc1 (all_tiles_ctl2dbc1_up_chain[tile_i + 1]), + .dbc2ctl (l2t_dbc2ctl[lane_i]), + .cfg_dbc (t2l_cfg_dbc[lane_i]), + + // Broadcast signals + .broadcast_in_bot (broadcast_up_chain[`_get_broadcast_chain_index(tile_i, lane_i)]), + .broadcast_out_top (broadcast_up_chain[`_get_broadcast_chain_index(tile_i, lane_i) + 1]), + .broadcast_in_top (broadcast_dn_chain[`_get_broadcast_chain_index(tile_i, lane_i) + 1]), + .broadcast_out_bot (broadcast_dn_chain[`_get_broadcast_chain_index(tile_i, lane_i)]), + + // Unused signals + .dft_phy_clk () + ); + end + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles_abphy.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles_abphy.sv new file mode 100644 index 000000000000..5082e1eba9dc --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_io_tiles_abphy.sv @@ -0,0 +1,1821 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + + + + +`define _get_max(_i, _j) ( (_i) > (_j) ? (_i) : (_j) ) +`define _get_min(_i, _j) ( (_i) < (_j) ? (_i) : (_j) ) + +`define _get_chain_index_for_tile(_tile_i) ( _tile_i * (LANES_PER_TILE + 1) + 2 ) + +`define _get_chain_index_for_lane(_tile_i, _lane_i) ( (_lane_i < 2) ? (_tile_i * (LANES_PER_TILE + 1) + _lane_i) : ( \ + (_tile_i * (LANES_PER_TILE + 1) + _lane_i + 1 )) ) + +`define _get_broadcast_chain_index(_tile_i, _lane_i) ( _tile_i * LANES_PER_TILE + _lane_i ) + +`define _get_lane_usage(_tile_i, _lane_i) ( LANES_USAGE[(_tile_i * LANES_PER_TILE + _lane_i) * 3 +: 3] ) + +`define _get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_OCT_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i)] ) + +`define _get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) ( PINS_RATE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) +`define _get_pin_ddr_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) == PIN_RATE_DDR ? "mode_ddr" : "mode_sdr" ) + +`define _get_pin_usage(_tile_i, _lane_i, _pin_i) ( PINS_USAGE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) + +`define _get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) ( PINS_WDB[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 3 +: 3] ) +`define _get_pin_wdb_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_AC_CORE ? "ac_core" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_AC_HMC ? "ac_hmc" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQS_WDB_MODE ? "dqs_wdb_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQS_MODE ? "dqs_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DM_WDB_MODE ? "dm_wdb_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DM_MODE ? "dm_mode" : ( \ + `_get_pin_wdb_raw(_tile_i, _lane_i, _pin_i) == PIN_WDB_DQ_WDB_MODE ? "dq_wdb_mode" : ( \ + "dq_mode" )))))))) + +`define _get_pin_db_in_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_IN_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_db_out_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_OUT_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_db_oe_bypass(_tile_i, _lane_i, _pin_i) ( PINS_DB_OE_BYPASS[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_invert_wr(_tile_i, _lane_i, _pin_i) ( PINS_INVERT_WR[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) +`define _get_pin_invert_oe(_tile_i, _lane_i, _pin_i) ( PINS_INVERT_OE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_ac_hmc_data_override_ena(_tile_i, _lane_i, _pin_i) ( PINS_AC_HMC_DATA_OVERRIDE_ENA[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "true" : "false" ) + +`define _get_pin_oct_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_STATIC_OFF ? "static_off" : ( \ + `_get_pin_oct_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_OCT_DYNAMIC ? "dynamic" : ( \ + "dynamic" ))) + +`define _get_pin_gpio_or_ddr(_tile_i, _lane_i, _pin_i) ( PINS_GPIO_MODE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ? "gpio" : "ddr" ) + +`define _get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) ( PINS_DATA_IN_MODE[(_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i) * 3 +: 3] ) + +`define _get_pin_data_in_mode_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DISABLED ? "disabled" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_SSTL_IN ? "sstl_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_LOOPBACK_IN ? "loopback_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_XOR_LOOPBACK_IN ? "xor_loopback_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN ? "differential_in" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT ? "differential_in_avl_out" : ( \ + `_get_pin_data_in_mode_raw(_tile_i, _lane_i, _pin_i) == PIN_DATA_IN_MODE_DIFF_IN_X12_OUT ? "differential_in_x12_out" : ( \ + "differential_in_avl_x12_out" )))))))) + +`define _get_ac_tile_index(_tile_i, _lane_i) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? SEC_AC_TILE_INDEX : PRI_AC_TILE_INDEX ) + +`define _get_dbc_pipe_lat(_tile_i, _lane_i) ( (_tile_i > `_get_ac_tile_index(_tile_i, _lane_i)) ? (_tile_i - `_get_ac_tile_index(_tile_i, _lane_i)) : \ + (`_get_ac_tile_index(_tile_i, _lane_i) - _tile_i) ) + +`define _get_max_distance_from_ac_tile ( `_get_max( (NUM_OF_RTL_TILES - PRI_AC_TILE_INDEX - 1), PRI_AC_TILE_INDEX ) ) + +`define _get_max_distance_from_ac_tile_capped ( PHY_PING_PONG_EN ? `_get_min(2, `_get_max_distance_from_ac_tile) : `_get_max_distance_from_ac_tile ) + +`define _get_curr_distance_from_ac_tile(_tile_i) ( (_tile_i > PRI_AC_TILE_INDEX) ? (_tile_i - PRI_AC_TILE_INDEX) : (PRI_AC_TILE_INDEX - _tile_i) ) +`define _get_db_ptr_pipe_depth_pri(_tile_i) ( `_get_max_distance_from_ac_tile_capped - `_get_curr_distance_from_ac_tile(_tile_i) ) +`define _get_db_ptr_pipe_depth_sec(_tile_i) ( `_get_db_ptr_pipe_depth_pri(_tile_i) + 1) +`define _get_db_ptr_pipe_depth(_tile_i, _lane_i) ( `_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? `_get_db_ptr_pipe_depth_pri(_tile_i) : `_get_db_ptr_pipe_depth_sec(_tile_i)) + +`define _get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) ( (NUM_OF_HMC_PORTS > 0) ? (`_get_max_distance_from_ac_tile_capped + 1) : (`_get_db_ptr_pipe_depth(_tile_i, _lane_i) + 1) ) +`define _get_db_seq_rd_en_full_pipeline_sec(_tile_i, _lane_i) ( `_get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) + 1 ) +`define _get_db_seq_rd_en_full_pipeline(_tile_i, _lane_i) ( `_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? `_get_db_seq_rd_en_full_pipeline_pri(_tile_i, _lane_i) : `_get_db_seq_rd_en_full_pipeline_sec(_tile_i, _lane_i)) + +`define _get_db_data_alignment_mode ( (NUM_OF_HMC_PORTS > 0) ? "align_ena" : "align_disable" ) + +`define _get_lane_mode_rate_in ( PHY_HMC_CLK_RATIO == 4 ? "in_rate_1_4" : ( \ + PHY_HMC_CLK_RATIO == 2 ? "in_rate_1_2" : ( \ + "in_rate_full" ))) + +`define _get_lane_mode_rate_out ( PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 8 ? "out_rate_1_8" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 4 ? "out_rate_1_4" : ( \ + PLL_VCO_TO_MEM_CLK_FREQ_RATIO == 2 ? "out_rate_1_2" : ( \ + "out_rate_full" )))) + +`define _get_hmc_ctrl_mem_type ( PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "lpddr3" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "rldram_iii" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "rldram_iii" : ( \ + "" )))))))) + +`define _get_hmc_or_core ( NUM_OF_HMC_PORTS == 0 ? "core" : "hmc" ) + +`define _get_hmc_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate" : "half_rate" ) +`define _get_dbc0_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc0" : "half_rate_dbc0" ) +`define _get_dbc1_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc1" : "half_rate_dbc1" ) +`define _get_dbc2_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc2" : "half_rate_dbc2" ) +`define _get_dbc3_cmd_rate ( PHY_HMC_CLK_RATIO == 4 ? "quarter_rate_dbc3" : "half_rate_dbc3" ) + +`define _get_hmc_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_in" : "ast_in" ) +`define _get_dbc0_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc0" : "ast_dbc0" ) +`define _get_dbc1_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc1" : "ast_dbc1" ) +`define _get_dbc2_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc2" : "ast_dbc2" ) +`define _get_dbc3_protocol ( HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM" ? "amm_dbc3" : "ast_dbc3" ) + +`define _get_hmc_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_ctrl" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_ctrl" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_ctrl" : ( \ + "" )))) + +`define _get_dbc0_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc0" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc0" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc0" : ( \ + "" )))) + +`define _get_dbc1_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc1" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc1" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc1" : ( \ + "" )))) + +`define _get_dbc2_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc2" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc2" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc2" : ( \ + "" )))) + +`define _get_dbc3_burst_length ( MEM_BURST_LENGTH == 2 ? "bl_2_dbc3" : ( \ + MEM_BURST_LENGTH == 4 ? "bl_4_dbc3" : ( \ + MEM_BURST_LENGTH == 8 ? "bl_8_dbc3" : ( \ + "" )))) + +`define _get_dqs_lgc_burst_length ( PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "burst_length_2" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "burst_length_2" : ( \ + MEM_BURST_LENGTH == 2 ? "burst_length_2" : ( \ + MEM_BURST_LENGTH == 4 ? "burst_length_4" : ( \ + MEM_BURST_LENGTH == 8 ? "burst_length_8" : ( \ + "" )))))))) + +`define _get_pa_exponent(_clk_ratio) ( (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 1 ? 3'b000 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 2 ? 3'b001 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 4 ? 3'b010 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 8 ? 3'b011 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 16 ? 3'b100 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 32 ? 3'b101 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 64 ? 3'b110 : ( \ + (_clk_ratio * PLL_VCO_TO_MEM_CLK_FREQ_RATIO) == 128 ? 3'b111 : ( \ + 3'b000 ))))))))) + +`define _get_cpa_0_clk_ratio ( NUM_OF_HMC_PORTS > 0 ? USER_CLK_RATIO : (USER_CLK_RATIO * 2) ) +`define _get_pa_exponent_0 ( (`_get_pa_exponent(`_get_cpa_0_clk_ratio)) ) + +`define _get_cpa_1_clk_ratio ( C2P_P2C_CLK_RATIO ) +`define _get_pa_exponent_1 ( (`_get_pa_exponent(`_get_cpa_1_clk_ratio)) ) + +`define _get_pa_feedback_divider_p0 ( (`_get_cpa_0_clk_ratio == C2P_P2C_CLK_RATIO * 2) ? "div_by_2_p0" : "div_by_1_p0" ) + +`define _get_pa_feedback_divider_c0 ( (`_get_cpa_0_clk_ratio * 2 == C2P_P2C_CLK_RATIO) ? "div_by_2_c0" : "div_by_1_c0" ) + +`define _get_dqsin(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_RDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WDATA && `_get_lane_usage(_tile_i, _lane_i) != LANE_USAGE_WRDATA) ? 2'b0 : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4" ? t2l_dqsbus_x4[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X8_X9" ? t2l_dqsbus_x8[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X16_X18" ? t2l_dqsbus_x18[_lane_i] : ( \ + DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X32_X36" ? t2l_dqsbus_x36[_lane_i] : ( \ + 2'b0 )))))) + +`define _get_pin_dqs_x4_mode_0 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_1 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_2 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_3 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_4 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_5 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_6 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_7 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_8 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_9 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_a" ) +`define _get_pin_dqs_x4_mode_10 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) +`define _get_pin_dqs_x4_mode_11 ( (DQS_BUS_MODE_ENUM != "DQS_BUS_MODE_X4") ? "dqs_x4_not_used" : "dqs_x4_b" ) + +`define _get_ctrl2dbc_switch_0_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" ))) + +`define _get_ctrl2dbc_switch_1_non_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" ))) + +`define _get_ctrl2dbc_sel_0_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc0" : "lower_mux_dbc0" ) +`define _get_ctrl2dbc_sel_1_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc1" : "lower_mux_dbc1" ) +`define _get_ctrl2dbc_sel_2_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc2" : "lower_mux_dbc2" ) +`define _get_ctrl2dbc_sel_3_non_pp(_tile_i) ( (_tile_i <= PRI_AC_TILE_INDEX) ? "upper_mux_dbc3" : "lower_mux_dbc3" ) + +`define _get_ctrl2dbc_switch_0_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "local_tile_dbc0" : ( \ + (_tile_i < SEC_AC_TILE_INDEX) ? "upper_tile_dbc0" : ( \ + "lower_tile_dbc0" )))) + +`define _get_ctrl2dbc_switch_1_pp(_tile_i) ( (_tile_i == PRI_AC_TILE_INDEX) ? "local_tile_dbc1" : ( \ + (_tile_i == SEC_AC_TILE_INDEX) ? "upper_tile_dbc1" : ( \ + (_tile_i > PRI_AC_TILE_INDEX) ? "lower_tile_dbc1" : ( \ + "upper_tile_dbc1" )))) + +`define _get_ctrl2dbc_sel_0_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc0" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc0" : (`_get_ac_tile_index(_tile_i, 0) == PRI_AC_TILE_INDEX ? "lower_mux_dbc0" : "upper_mux_dbc0")) ) +`define _get_ctrl2dbc_sel_1_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc1" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc1" : (`_get_ac_tile_index(_tile_i, 1) == PRI_AC_TILE_INDEX ? "lower_mux_dbc1" : "upper_mux_dbc1")) ) +`define _get_ctrl2dbc_sel_2_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc2" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc2" : (`_get_ac_tile_index(_tile_i, 2) == PRI_AC_TILE_INDEX ? "lower_mux_dbc2" : "upper_mux_dbc2")) ) +`define _get_ctrl2dbc_sel_3_pp(_tile_i) ( (_tile_i >= PRI_AC_TILE_INDEX) ? "lower_mux_dbc3" : ((_tile_i < SEC_AC_TILE_INDEX) ? "upper_mux_dbc3" : (`_get_ac_tile_index(_tile_i, 3) == PRI_AC_TILE_INDEX ? "lower_mux_dbc3" : "upper_mux_dbc3")) ) + +`define _get_ctrl2dbc_switch_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_0_pp(_tile_i) : `_get_ctrl2dbc_switch_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_switch_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_switch_1_pp(_tile_i) : `_get_ctrl2dbc_switch_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_0(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_0_pp(_tile_i) : `_get_ctrl2dbc_sel_0_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_1(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_1_pp(_tile_i) : `_get_ctrl2dbc_sel_1_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_2(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_2_pp(_tile_i) : `_get_ctrl2dbc_sel_2_non_pp(_tile_i) ) +`define _get_ctrl2dbc_sel_3(_tile_i) ( PHY_PING_PONG_EN ? `_get_ctrl2dbc_sel_3_pp(_tile_i) : `_get_ctrl2dbc_sel_3_non_pp(_tile_i) ) + +`define _get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ( PRI_HMC_DBC_SHADOW_LANE_INDEX == 0 ? "dbc0_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 1 ? "dbc1_to_local" : ( \ + PRI_HMC_DBC_SHADOW_LANE_INDEX == 2 ? "dbc2_to_local" : ( \ + "dbc3_to_local" )))) + +`define _get_hmc_dbc2ctrl_sel_pp(_tile_i) ( (_tile_i != SEC_AC_TILE_INDEX) ? `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 0) == SEC_AC_TILE_INDEX) ? "dbc0_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 1) == SEC_AC_TILE_INDEX) ? "dbc1_to_local" : ( \ + (`_get_ac_tile_index(SEC_AC_TILE_INDEX, 2) == SEC_AC_TILE_INDEX) ? "dbc2_to_local" : ( \ + "dbc3_to_local" ))))) +`define _get_hmc_dbc2ctrl_sel(_tile_i) ( PHY_PING_PONG_EN ? `_get_hmc_dbc2ctrl_sel_pp(_tile_i) : `_get_hmc_dbc2ctrl_sel_non_pp(_tile_i) ) + +`define _get_ac_hmc(_tile_i, _lane_i) ( (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_HMC || \ + `_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_AC_CORE || \ + (`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_UNUSED && IS_HPS && _tile_i == PRI_AC_TILE_INDEX)) ? \ + t2l_ac_hmc[lane_i] : 96'b0 ) + +`define _get_core2dbc_wr_data_vld_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_wr_data_vld_ast_0 : core2l_wr_data_vld_ast_1 ) ) +`define _get_core2dbc_wr_data_vld(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_wr_data_vld_of_hmc(_tile_i, _lane_i) : 1'b0 ) + +`define _get_core2dbc_rd_data_rdy_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_rd_data_rdy_ast_0 : core2l_rd_data_rdy_ast_1 ) ) +`define _get_core2dbc_rd_data_rdy(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_rd_data_rdy_of_hmc(_tile_i, _lane_i) : 1'b1 ) + +`define _get_core2dbc_wr_ecc_info_of_hmc(_tile_i, _lane_i) ( (`_get_ac_tile_index(_tile_i, _lane_i) == PRI_AC_TILE_INDEX ? core2l_wr_ecc_info_0 : core2l_wr_ecc_info_1 ) ) +`define _get_core2dbc_wr_ecc_info(_tile_i, _lane_i) ( ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) || \ + (_lane_i == 0 && `_get_lane_usage(_tile_i, 0) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc0_to_local") || \ + (_lane_i == 1 && `_get_lane_usage(_tile_i, 1) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc1_to_local") || \ + (_lane_i == 2 && `_get_lane_usage(_tile_i, 2) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc2_to_local") || \ + (_lane_i == 3 && `_get_lane_usage(_tile_i, 3) == LANE_USAGE_AC_HMC && `_get_hmc_dbc2ctrl_sel(_tile_i) == "dbc3_to_local")) ? \ + `_get_core2dbc_wr_ecc_info_of_hmc(_tile_i, _lane_i) : 13'b0 ) + +`define _get_center_tid(_tile_i) ( CENTER_TIDS[_tile_i * 9 +: 9] ) +`define _get_hmc_tid(_tile_i) ( HMC_TIDS[_tile_i * 9 +: 9] ) +`define _get_lane_tid(_tile_i, _lane_i) ( LANE_TIDS[(_tile_i * LANES_PER_TILE + _lane_i) * 9 +: 9] ) + +`define _get_preamble_track_dqs_enable_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "preamble_track_dqs_enable" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "preamble_track_toggler" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "preamble_track_toggler" : ( \ + "" )))))))) + +`define _get_pst_preamble_mode ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "ddr3_preamble" : "ddr4_preamble") : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "ddr3_preamble" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "ddr3_preamble" : ( \ + "" )))))))) + +`define _get_ddr4_search "ddr3_search" +/*`define _get_ddr4_search ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? "ddr4_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "ddr3_search" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "ddr3_search" : ( \ + "" ))))))) +*/ + +`define _get_dqs_b_en ( (PROTOCOL_ENUM == "PROTOCOL_QDR2") || (DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "true" : "false" ) + +`define _get_pst_en_shrink ( PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ((DQS_BUS_MODE_ENUM == "DQS_BUS_MODE_X4") ? "shrink_1_1" : "shrink_1_0") : ( \ + PROTOCOL_ENUM == "PROTOCOL_DDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? "shrink_1_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD3" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_RLD2" ? "shrink_0_1" : ( \ + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? "shrink_0_1" : ( \ + "" )))))))) + + +`define _get_dbi_wr_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_WR_ENABLE : "false") +`define _get_dbi_rd_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? DBI_RD_ENABLE : "false") + +`define _get_crc_en(_tile_i, _lane_i) ((`_get_lane_usage(_tile_i, _lane_i) == LANE_USAGE_WRDATA) ? CRC_EN : "crc_disable") + +`define _get_crc_x4_or_x8_or_x9 ( (PORT_MEM_DQ_WIDTH / PORT_MEM_DQS_WIDTH == 4) ? "x4_mode" : ( \ + (DBI_WR_ENABLE == "true" || MEM_DATA_MASK_EN) ? "x9_mode" : ( \ + "x8_mode" )) ) + +`define _get_crc_pin_pos_0 1 +`define _get_crc_pin_pos_1 2 +`define _get_crc_pin_pos_2 3 +`define _get_crc_pin_pos_3 6 +`define _get_crc_pin_pos_4 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 7 : 4) +`define _get_crc_pin_pos_5 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 8 : 4) +`define _get_crc_pin_pos_6 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 9 : 4) +`define _get_crc_pin_pos_7 ((`_get_crc_x4_or_x8_or_x9 != "x4_mode") ? 10 : 4) +`define _get_crc_pin_pos_8 ((`_get_crc_x4_or_x8_or_x9 == "x9_mode") ? 11 : 4) + +`define _sel_hmc_val(_tile_i, _pri, _sec) ( PHY_PING_PONG_EN ? (_tile_i <= SEC_AC_TILE_INDEX ? _sec : _pri) : _pri ) + +`define _sel_hmc_def(_tile_i, _pri, _sec, _def) ( PHY_PING_PONG_EN ? ((_tile_i == SEC_AC_TILE_INDEX) ? _sec : (_tile_i == PRI_AC_TILE_INDEX) ? _pri : _def) : _pri ) + +`define _sel_hmc_lane(_tile_i, _lane_i, _pri, _sec) ( (PHY_PING_PONG_EN && (_tile_i < SEC_AC_TILE_INDEX || (_tile_i == SEC_AC_TILE_INDEX && _lane_i < 2))) ? _sec : _pri ) + +module altera_emif_arch_nf_io_tiles_abphy #( + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_FAST_SIM = 0, + parameter IS_HPS = 0, + parameter SILICON_REV = "", + parameter PROTOCOL_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter PINS_PER_LANE = 1, + parameter LANES_PER_TILE = 1, + parameter PINS_IN_RTL_TILES = 1, + parameter LANES_IN_RTL_TILES = 1, + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter PRI_HMC_DBC_SHADOW_LANE_INDEX = -1, + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter LANES_USAGE = 1'b0, + parameter PINS_USAGE = 1'b0, + parameter PINS_RATE = 1'b0, + parameter PINS_WDB = 1'b0, + parameter PINS_DB_IN_BYPASS = 1'b0, + parameter PINS_DB_OUT_BYPASS = 1'b0, + parameter PINS_DB_OE_BYPASS = 1'b0, + parameter PINS_INVERT_WR = 1'b0, + parameter PINS_INVERT_OE = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA = 1'b0, + parameter PINS_DATA_IN_MODE = 1'b0, + parameter PINS_OCT_MODE = 1'b0, + parameter PINS_GPIO_MODE = 1'b0, + parameter CENTER_TIDS = 1'b0, + parameter HMC_TIDS = 1'b0, + parameter LANE_TIDS = 1'b0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = "", + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 1, + parameter PORT_MEM_A_PINLOC = 0, + parameter PORT_MEM_BA_PINLOC = 0, + parameter PORT_MEM_BG_PINLOC = 0, + parameter PORT_MEM_CS_N_PINLOC = 0, + parameter PORT_MEM_ACT_N_PINLOC = 0, + parameter PORT_MEM_DQ_PINLOC = 0, + parameter PORT_MEM_DM_PINLOC = 0, + parameter PORT_MEM_DBI_N_PINLOC = 0, + parameter PORT_MEM_RAS_N_PINLOC = 0, + parameter PORT_MEM_CAS_N_PINLOC = 0, + parameter PORT_MEM_WE_N_PINLOC = 0, + parameter PORT_MEM_REF_N_PINLOC = 0, + + parameter PORT_MEM_WPS_N_PINLOC = 0, + parameter PORT_MEM_RPS_N_PINLOC = 0, + parameter PORT_MEM_BWS_N_PINLOC = 0, + parameter PORT_MEM_DQA_PINLOC = 0, + parameter PORT_MEM_DQB_PINLOC = 0, + parameter PORT_MEM_Q_PINLOC = 0, + parameter PORT_MEM_D_PINLOC = 0, + parameter PORT_MEM_RWA_N_PINLOC = 0, + parameter PORT_MEM_RWB_N_PINLOC = 0, + parameter PORT_MEM_QKA_PINLOC = 0, + parameter PORT_MEM_QKB_PINLOC = 0, + parameter PORT_MEM_LDA_N_PINLOC = 0, + parameter PORT_MEM_LDB_N_PINLOC = 0, + parameter PORT_MEM_CK_PINLOC = 0, + parameter PORT_MEM_DINVA_PINLOC = 0, + parameter PORT_MEM_DINVB_PINLOC = 0, + parameter PORT_MEM_AINV_PINLOC = 0, + + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 0, + parameter DIAG_ABSTRACT_PHY_RLAT = 0, + parameter ABPHY_WRITE_PROTOCOL = 1 + ) ( + input logic global_reset_n_int, + output logic phy_reset_n_abphy, + + input logic pll_locked, + input logic pll_dll_clk, + input logic [7:0] phy_clk_phs, + input logic [1:0] phy_clk, + input logic phy_fb_clk_to_tile, + output logic phy_fb_clk_to_pll_abphy, + + output logic [1:0] core_clks_from_cpa_pri_abphy, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri_abphy, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_fb_to_cpa_pri, // Core clock feedback signals to the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec_abphy, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec_abphy, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_fb_to_cpa_sec, // Core clock feedback signals to the CPA of secondary interface (ping-pong only) + + input logic [59:0] core2ctl_avl_0, + input logic [59:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + output logic ctl2core_avl_cmd_ready_0_abphy, + output logic ctl2core_avl_cmd_ready_1_abphy, + output logic [12:0] ctl2core_avl_rdata_id_0_abphy, + output logic [12:0] ctl2core_avl_rdata_id_1_abphy, + input logic core2l_wr_data_vld_ast_0, + input logic core2l_wr_data_vld_ast_1, + input logic core2l_rd_data_rdy_ast_0, + input logic core2l_rd_data_rdy_ast_1, + + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_abphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_abphy, + + input logic [12:0] core2l_wr_ecc_info_0, + input logic [12:0] core2l_wr_ecc_info_1, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_abphy, + + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_abphy, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_abphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_abphy, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_abphy, + + input [16:0] c2t_afi, + output [25:0] t2c_afi_abphy, + + input logic [41:0] core2ctl_sideband_0, + output logic [13:0] ctl2core_sideband_0_abphy, + input logic [41:0] core2ctl_sideband_1, + output logic [13:0] ctl2core_sideband_1_abphy, + + output logic [33:0] ctl2core_mmr_0_abphy, + input logic [50:0] core2ctl_mmr_0, + output logic [33:0] ctl2core_mmr_1_abphy, + input logic [50:0] core2ctl_mmr_1, + + output logic [PINS_IN_RTL_TILES-1:0] l2b_data_abphy, + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe_abphy, + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_abphy, + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, + + // Avalon-MM bus for the calibration commands between io_aux and tiles + input logic cal_bus_clk, + input logic cal_bus_avl_write, + input logic [19:0] cal_bus_avl_address, + input logic [31:0] cal_bus_avl_write_data, + + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select_abphy, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_abphy, + + input logic afi_cal_success, + output logic runAbstractPhySim +); + timeunit 1ns; + timeprecision 1ps; + + typedef enum bit [2:0] { + LANE_USAGE_UNUSED = 3'b000, + LANE_USAGE_AC_HMC = 3'b001, + LANE_USAGE_AC_CORE = 3'b010, + LANE_USAGE_RDATA = 3'b011, + LANE_USAGE_WDATA = 3'b100, + LANE_USAGE_WRDATA = 3'b101 + } LANE_USAGE; + + typedef enum bit [0:0] { + PIN_USAGE_UNUSED = 1'b0, + PIN_USAGE_USED = 1'b1 + } PIN_USAGE; + + typedef enum bit [0:0] { + PIN_RATE_DDR = 1'b0, + PIN_RATE_SDR = 1'b1 + } PIN_RATE; + + typedef enum bit [0:0] { + PIN_OCT_STATIC_OFF = 1'b0, + PIN_OCT_DYNAMIC = 1'b1 + } PIN_OCT_MODE; + + typedef enum bit [2:0] { + PIN_WDB_AC_CORE = 3'b000, + PIN_WDB_AC_HMC = 3'b001, + PIN_WDB_DQS_WDB_MODE = 3'b010, + PIN_WDB_DQS_MODE = 3'b011, + PIN_WDB_DM_WDB_MODE = 3'b100, + PIN_WDB_DM_MODE = 3'b101, + PIN_WDB_DQ_WDB_MODE = 3'b110, + PIN_WDB_DQ_MODE = 3'b111 + } PIN_WDB; + + typedef enum bit [2:0] { + PIN_DATA_IN_MODE_DISABLED = 3'b000, + PIN_DATA_IN_MODE_SSTL_IN = 3'b001, + PIN_DATA_IN_MODE_LOOPBACK_IN = 3'b010, + PIN_DATA_IN_MODE_XOR_LOOPBACK_IN = 3'b011, + PIN_DATA_IN_MODE_DIFF_IN = 3'b100, + PIN_DATA_IN_MODE_DIFF_IN_AVL_OUT = 3'b101, + PIN_DATA_IN_MODE_DIFF_IN_X12_OUT = 3'b110, + PIN_DATA_IN_MODE_DIFF_IN_AVL_X12_OUT = 3'b111 + } PIN_DATA_IN_MODE; + + localparam USE_HMC_RC_OR_DP = (C2P_P2C_CLK_RATIO == PHY_HMC_CLK_RATIO) ? 0 : 1; + + logic [NUM_OF_RTL_TILES-1:0] t2c_seq2core_reset_n; + assign phy_reset_n_abphy = t2c_seq2core_reset_n[PRI_AC_TILE_INDEX]; + + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_data_dn_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_up_chain; + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0] pa_sync_clk_dn_chain; + assign pa_sync_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_clk_dn_chain [NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 1'b1; + assign pa_sync_data_up_chain[0] = 1'b1; + assign pa_sync_clk_up_chain [0] = 1'b1; + + wire cal_bus_clk_force; + wire cal_bus_avl_read; + wire [31:0] cal_bus_avl_read_data; + wire cal_bus_avl_write_force; + wire [19:0] cal_bus_avl_address_force; + wire [31:0] cal_bus_avl_write_data_force; + + assign cal_bus_avl_read = 'd0; + assign cal_bus_avl_read_data = 'd0; + + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][54:0] cal_bus_avl_up_chain; + assign cal_bus_avl_up_chain[0][19:0] = cal_bus_avl_address_force; + assign cal_bus_avl_up_chain[0][51:20] = cal_bus_avl_write_data_force; + assign cal_bus_avl_up_chain[0][52] = cal_bus_avl_write_force; + assign cal_bus_avl_up_chain[0][53] = cal_bus_avl_read; + assign cal_bus_avl_up_chain[0][54] = cal_bus_clk_force; + + logic [(NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)):0][31:0] cal_bus_avl_read_data_dn_chain; + assign cal_bus_avl_read_data_dn_chain[NUM_OF_RTL_TILES * (LANES_PER_TILE + 1)] = 32'b0; + + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0] broadcast_up_chain; + logic [(NUM_OF_RTL_TILES * LANES_PER_TILE):0] broadcast_dn_chain; + assign broadcast_dn_chain[NUM_OF_RTL_TILES * LANES_PER_TILE] = 1'b1; + assign broadcast_up_chain[0] = 1'b1; + + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc0_dn_chain; + logic [NUM_OF_RTL_TILES:0][50:0] all_tiles_ctl2dbc1_up_chain; + assign all_tiles_ctl2dbc0_dn_chain[NUM_OF_RTL_TILES] = {51{1'b1}}; + assign all_tiles_ctl2dbc1_up_chain[0] = {51{1'b1}}; + + logic [NUM_OF_RTL_TILES:0][47:0] all_tiles_ping_pong_up_chain; + assign all_tiles_ping_pong_up_chain[0] = {48{1'b1}}; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][7:0] all_tiles_t2l_phy_clk_phs; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][1:0] all_tiles_t2l_phy_clk; + + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] all_tiles_dll_clk_out; + + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_out; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_fb_in; + logic [NUM_OF_RTL_TILES-1:0][1:0] all_tiles_core_clks_locked; + + assign core_clks_from_cpa_pri_abphy = all_tiles_core_clks_out[PRI_AC_TILE_INDEX]; + assign core_clks_locked_cpa_pri_abphy = all_tiles_core_clks_locked[PRI_AC_TILE_INDEX]; + assign all_tiles_core_clks_fb_in[PRI_AC_TILE_INDEX] = core_clks_fb_to_cpa_pri; + + assign core_clks_from_cpa_sec_abphy = PHY_PING_PONG_EN ? all_tiles_core_clks_out[SEC_AC_TILE_INDEX] : '0; + assign core_clks_locked_cpa_sec_abphy = PHY_PING_PONG_EN ? all_tiles_core_clks_locked[SEC_AC_TILE_INDEX] : '0; + generate + if (PHY_PING_PONG_EN) begin + assign all_tiles_core_clks_fb_in[SEC_AC_TILE_INDEX] = core_clks_fb_to_cpa_sec; + end + endgenerate + + logic [NUM_OF_RTL_TILES-1:0] all_tiles_phy_fb_clk_to_pll; + assign phy_fb_clk_to_pll_abphy = all_tiles_phy_fb_clk_to_pll[PRI_AC_TILE_INDEX]; + + logic [NUM_OF_RTL_TILES-1:0] all_tiles_ctl2core_avl_cmd_ready; + logic [NUM_OF_RTL_TILES-1:0][12:0] all_tiles_ctl2core_avl_rdata_id; + + assign ctl2core_avl_cmd_ready_0_abphy = all_tiles_ctl2core_avl_cmd_ready[PRI_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_0_abphy = all_tiles_ctl2core_avl_rdata_id[PRI_AC_TILE_INDEX]; + + assign ctl2core_avl_cmd_ready_1_abphy = all_tiles_ctl2core_avl_cmd_ready[SEC_AC_TILE_INDEX]; + assign ctl2core_avl_rdata_id_1_abphy = all_tiles_ctl2core_avl_rdata_id[SEC_AC_TILE_INDEX]; + + logic [NUM_OF_RTL_TILES-1:0][16:0] all_tiles_c2t_afi; + logic [NUM_OF_RTL_TILES-1:0][25:0] all_tiles_t2c_afi; + + assign all_tiles_c2t_afi[PRI_AC_TILE_INDEX] = c2t_afi; + assign t2c_afi_abphy = all_tiles_t2c_afi[PRI_AC_TILE_INDEX]; + + logic [NUM_OF_RTL_TILES-1:0][13:0] all_tiles_ctl2core_sideband; + + assign ctl2core_sideband_0_abphy = all_tiles_ctl2core_sideband[PRI_AC_TILE_INDEX]; + assign ctl2core_sideband_1_abphy = all_tiles_ctl2core_sideband[SEC_AC_TILE_INDEX]; + + logic [NUM_OF_RTL_TILES-1:0][33:0] all_tiles_ctl2core_mmr; + + assign ctl2core_mmr_0_abphy = all_tiles_ctl2core_mmr[PRI_AC_TILE_INDEX]; + assign ctl2core_mmr_1_abphy = all_tiles_ctl2core_mmr[SEC_AC_TILE_INDEX]; + + logic [NUM_OF_RTL_TILES-1:0] all_tiles_pa_dprio_block_select; + logic [NUM_OF_RTL_TILES-1:0][PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] all_tiles_pa_dprio_readdata; + + assign pa_dprio_readdata_abphy = all_tiles_pa_dprio_readdata[PRI_AC_TILE_INDEX]; + assign pa_dprio_block_select_abphy = all_tiles_pa_dprio_block_select[PRI_AC_TILE_INDEX]; + + wire [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] ac_hmc_par; + wire [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_data_to_mem; + wire [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_data_from_mem; + wire [3:0] rdata_valid_local [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0]; + wire [48*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_oe; + + integer add_2 [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0]; + +`define _abphy_get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) +`define _abphy_get_tile(_loc, _port_i) ( `_abphy_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _abphy_get_lane(_loc, _port_i) ( (`_abphy_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) + + initial begin + runAbstractPhySim = 1; + end + + // synthesis translate_off + integer fileID,fileMentorID,r; + string sim_loc,force_file,force_file_mentor,line_in,sub_line_in; + reg afi_cal_success_delay; + initial begin + afi_cal_success_delay = 0; + @ ( posedge afi_cal_success ); + repeat (20) @ ( posedge cal_bus_clk ); + afi_cal_success_delay = 1; + end + + + integer min_wlat,wlat,wlat_offset,rlat; + initial begin + @ (posedge global_reset_n_int); + if ( global_reset_n_int !==1'b1 ) + @ (posedge global_reset_n_int); + min_wlat = 2; + + if ( NUM_OF_HMC_PORTS>0 ) begin + if ( SEC_AC_TILE_INDEX>-1 ) begin + if ( ((NUM_OF_RTL_TILES+1)-SEC_AC_TILE_INDEX)>min_wlat ) begin + min_wlat = (NUM_OF_RTL_TILES+1)-SEC_AC_TILE_INDEX; + end + if ( (SEC_AC_TILE_INDEX+1)>min_wlat ) begin + min_wlat = SEC_AC_TILE_INDEX+1; + end + end + if ( ((NUM_OF_RTL_TILES+1)-PRI_AC_TILE_INDEX)>min_wlat ) begin + min_wlat = (NUM_OF_RTL_TILES+1)-PRI_AC_TILE_INDEX; + end + if ( (PRI_AC_TILE_INDEX+1)>min_wlat ) begin + min_wlat = PRI_AC_TILE_INDEX+1; + end + end + if ( DIAG_VERBOSE_IOAUX!=0 ) $display("min wlat=%d",min_wlat); + if ( DIAG_ABSTRACT_PHY_WLAT DLL output clock + input logic [7:0] phy_clk_phs, // FR PHY clock signals (8 phases, 45-deg apart) + input logic [1:0] phy_clk, // {phy_clk[1], phy_clk[0]} + input logic phy_fb_clk_to_tile, // PHY feedback clock (to tile) + output logic phy_fb_clk_to_pll, // PHY feedback clock (to PLL) + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + output logic [1:0] core_clks_from_cpa_pri, // Core clock signals from the CPA of primary interface + output logic [1:0] core_clks_locked_cpa_pri, // Core clock locked signals from the CPA of primary interface + input logic [1:0] core_clks_fb_to_cpa_pri, // Core clock feedback signals to the CPA of primary interface + output logic [1:0] core_clks_from_cpa_sec, // Core clock signals from the CPA of secondary interface (ping-pong only) + output logic [1:0] core_clks_locked_cpa_sec, // Core clock locked signals from the CPA of secondary interface (ping-pong only) + input logic [1:0] core_clks_fb_to_cpa_sec, // Core clock feedback signals to the CPA of secondary interface (ping-pong only) + + // Avalon interfaces between core and HMC + input logic [59:0] core2ctl_avl_0, + input logic [59:0] core2ctl_avl_1, + input logic core2ctl_avl_rd_data_ready_0, + input logic core2ctl_avl_rd_data_ready_1, + output logic ctl2core_avl_cmd_ready_0, + output logic ctl2core_avl_cmd_ready_1, + output logic [12:0] ctl2core_avl_rdata_id_0, + output logic [12:0] ctl2core_avl_rdata_id_1, + input logic core2l_wr_data_vld_ast_0, + input logic core2l_wr_data_vld_ast_1, + input logic core2l_rd_data_rdy_ast_0, + input logic core2l_rd_data_rdy_ast_1, + + // Avalon interfaces between core and lanes + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast, + + // ECC signals between core and lanes + input logic [12:0] core2l_wr_ecc_info_0, + input logic [12:0] core2l_wr_ecc_info_1, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc, + + // Signals between core and data lanes + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read, + input logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat, + output logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat, + + // AFI signals between tile and core + input [16:0] c2t_afi, + output [25:0] t2c_afi, + + // Side-band signals between core and HMC + input logic [41:0] core2ctl_sideband_0, + output logic [13:0] ctl2core_sideband_0, + input logic [41:0] core2ctl_sideband_1, + output logic [13:0] ctl2core_sideband_1, + + // MMR signals between core and HMC + output logic [33:0] ctl2core_mmr_0, + input logic [50:0] core2ctl_mmr_0, + output logic [33:0] ctl2core_mmr_1, + input logic [50:0] core2ctl_mmr_1, + + // Signals between I/O buffers and lanes/tiles + output logic [PINS_IN_RTL_TILES-1:0] l2b_data, // lane-to-buffer data + output logic [PINS_IN_RTL_TILES-1:0] l2b_oe, // lane-to-buffer output-enable + output logic [PINS_IN_RTL_TILES-1:0] l2b_dtc, // lane-to-buffer dynamic-termination-control + input logic [PINS_IN_RTL_TILES-1:0] b2l_data, // buffer-to-lane data + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqs, // buffer-to-tile DQS + input logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb, // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between io_aux and tiles + input logic cal_bus_clk, + input logic cal_bus_avl_read, + input logic cal_bus_avl_write, + input logic [19:0] cal_bus_avl_address, + output logic [31:0] cal_bus_avl_read_data, + input logic [31:0] cal_bus_avl_write_data, + + // Ports for internal test and debug + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + output logic runAbstractPhySim, + input logic afi_cal_success +); + timeunit 1ns; + timeprecision 1ps; + + logic phy_reset_n_abphy; + logic phy_fb_clk_to_pll_abphy; + logic [1:0] core_clks_from_cpa_pri_abphy; + logic [1:0] core_clks_locked_cpa_pri_abphy; + logic [1:0] core_clks_from_cpa_sec_abphy; + logic [1:0] core_clks_locked_cpa_sec_abphy; + logic ctl2core_avl_cmd_ready_0_abphy; + logic ctl2core_avl_cmd_ready_1_abphy; + logic [12:0] ctl2core_avl_rdata_id_0_abphy; + logic [12:0] ctl2core_avl_rdata_id_1_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_abphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_abphy; + logic [25:0] t2c_afi_abphy; + logic [13:0] ctl2core_sideband_0_abphy; + logic [13:0] ctl2core_sideband_1_abphy; + logic [33:0] ctl2core_mmr_0_abphy; + logic [33:0] ctl2core_mmr_1_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_data_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_oe_abphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_abphy; + logic pa_dprio_block_select_abphy; + logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_abphy; + logic phy_reset_n_nonabphy; + logic phy_fb_clk_to_pll_nonabphy; + logic [1:0] core_clks_from_cpa_pri_nonabphy; + logic [1:0] core_clks_locked_cpa_pri_nonabphy; + logic [1:0] core_clks_from_cpa_sec_nonabphy; + logic [1:0] core_clks_locked_cpa_sec_nonabphy; + logic ctl2core_avl_cmd_ready_0_nonabphy; + logic ctl2core_avl_cmd_ready_1_nonabphy; + logic [12:0] ctl2core_avl_rdata_id_0_nonabphy; + logic [12:0] ctl2core_avl_rdata_id_1_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat_nonabphy; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat_nonabphy; + logic [25:0] t2c_afi_nonabphy; + logic [13:0] ctl2core_sideband_0_nonabphy; + logic [13:0] ctl2core_sideband_1_nonabphy; + logic [33:0] ctl2core_mmr_0_nonabphy; + logic [33:0] ctl2core_mmr_1_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_data_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_oe_nonabphy; + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc_nonabphy; + logic pa_dprio_block_select_nonabphy; + logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata_nonabphy; + + logic global_reset_n_int_iotile_in; + logic pll_locked_iotile_in; + logic pll_dll_clk_iotile_in; + logic [7:0] phy_clk_phs_iotile_in; + logic [1:0] phy_clk_iotile_in; + logic phy_fb_clk_to_tile_iotile_in; + logic [1:0] core_clks_fb_to_cpa_pri_iotile_in; + logic [1:0] core_clks_fb_to_cpa_sec_iotile_in; + logic [59:0] core2ctl_avl_0_iotile_in; + logic [59:0] core2ctl_avl_1_iotile_in; + logic core2ctl_avl_rd_data_ready_0_iotile_in; + logic core2ctl_avl_rd_data_ready_1_iotile_in; + logic core2l_wr_data_vld_ast_0_iotile_in; + logic core2l_wr_data_vld_ast_1_iotile_in; + logic core2l_rd_data_rdy_ast_0_iotile_in; + logic core2l_rd_data_rdy_ast_1_iotile_in; + logic [12:0] core2l_wr_ecc_info_0_iotile_in; + logic [12:0] core2l_wr_ecc_info_1_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read_iotile_in; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write_iotile_in; + logic [16:0] c2t_afi_iotile_in; + logic [41:0] core2ctl_sideband_0_iotile_in; + logic [41:0] core2ctl_sideband_1_iotile_in; + logic [50:0] core2ctl_mmr_0_iotile_in; + logic [50:0] core2ctl_mmr_1_iotile_in; + logic [PINS_IN_RTL_TILES-1:0] b2l_data_iotile_in; + logic [LANES_IN_RTL_TILES-1:0] b2t_dqs_iotile_in; + logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb_iotile_in; + logic cal_bus_clk_iotile_in; + logic cal_bus_avl_read_iotile_in; + logic cal_bus_avl_write_iotile_in; + logic [19:0] cal_bus_avl_address_iotile_in; + logic [31:0] cal_bus_avl_write_data_iotile_in; + logic pa_dprio_clk_iotile_in; + logic pa_dprio_read_iotile_in; + logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr_iotile_in; + logic pa_dprio_rst_n_iotile_in; + logic pa_dprio_write_iotile_in; + logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata_iotile_in; + + + //////////////////////////////////////////////////////////////////////////// + // Tiles and Lanes + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_io_tiles # ( + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .PINS_WDB (PINS_WDB), + .PINS_DB_IN_BYPASS (PINS_DB_IN_BYPASS), + .PINS_DB_OUT_BYPASS (PINS_DB_OUT_BYPASS), + .PINS_DB_OE_BYPASS (PINS_DB_OE_BYPASS), + .PINS_INVERT_WR (PINS_INVERT_WR), + .PINS_INVERT_OE (PINS_INVERT_OE), + .PINS_AC_HMC_DATA_OVERRIDE_ENA (PINS_AC_HMC_DATA_OVERRIDE_ENA), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_GPIO_MODE (PINS_GPIO_MODE), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH) + ) io_tiles_inst ( + .global_reset_n_int (global_reset_n_int_iotile_in), + .pll_locked (pll_locked_iotile_in), + .pll_dll_clk (pll_dll_clk_iotile_in), + .phy_clk_phs (phy_clk_phs_iotile_in), + .phy_clk (phy_clk_iotile_in), + .phy_fb_clk_to_tile (phy_fb_clk_to_tile_iotile_in), + .core_clks_fb_to_cpa_pri (core_clks_fb_to_cpa_pri_iotile_in), + .core_clks_fb_to_cpa_sec (core_clks_fb_to_cpa_sec_iotile_in), + .core2ctl_avl_0 (core2ctl_avl_0_iotile_in), + .core2ctl_avl_1 (core2ctl_avl_1_iotile_in), + .core2ctl_avl_rd_data_ready_0 (core2ctl_avl_rd_data_ready_0_iotile_in), + .core2ctl_avl_rd_data_ready_1 (core2ctl_avl_rd_data_ready_1_iotile_in), + .core2l_wr_data_vld_ast_0 (core2l_wr_data_vld_ast_0_iotile_in), + .core2l_wr_data_vld_ast_1 (core2l_wr_data_vld_ast_1_iotile_in), + .core2l_rd_data_rdy_ast_0 (core2l_rd_data_rdy_ast_0_iotile_in), + .core2l_rd_data_rdy_ast_1 (core2l_rd_data_rdy_ast_1_iotile_in), + .core2l_wr_ecc_info_0 (core2l_wr_ecc_info_0_iotile_in), + .core2l_wr_ecc_info_1 (core2l_wr_ecc_info_1_iotile_in), + .core2l_data (core2l_data_iotile_in), + .core2l_oe (core2l_oe_iotile_in), + .core2l_rdata_en_full (core2l_rdata_en_full_iotile_in), + .core2l_mrnk_read (core2l_mrnk_read_iotile_in), + .core2l_mrnk_write (core2l_mrnk_write_iotile_in), + .c2t_afi (c2t_afi_iotile_in), + .core2ctl_sideband_0 (core2ctl_sideband_0_iotile_in), + .core2ctl_sideband_1 (core2ctl_sideband_1_iotile_in), + .core2ctl_mmr_0 (core2ctl_mmr_0_iotile_in), + .core2ctl_mmr_1 (core2ctl_mmr_1_iotile_in), + .b2l_data (b2l_data_iotile_in), + .b2t_dqs (b2t_dqs_iotile_in), + .b2t_dqsb (b2t_dqsb_iotile_in), + .cal_bus_clk (cal_bus_clk_iotile_in), + .cal_bus_avl_read (cal_bus_avl_read_iotile_in), + .cal_bus_avl_write (cal_bus_avl_write_iotile_in), + .cal_bus_avl_address (cal_bus_avl_address_iotile_in), + .cal_bus_avl_write_data (cal_bus_avl_write_data_iotile_in), + .pa_dprio_clk (pa_dprio_clk_iotile_in), + .pa_dprio_read (pa_dprio_read_iotile_in), + .pa_dprio_reg_addr (pa_dprio_reg_addr_iotile_in), + .pa_dprio_rst_n (pa_dprio_rst_n_iotile_in), + .pa_dprio_write (pa_dprio_write_iotile_in), + .pa_dprio_writedata (pa_dprio_writedata_iotile_in), + .* + ); + + generate + if ( DIAG_USE_ABSTRACT_PHY==1 ) begin : abphy_tiles + altera_emif_arch_nf_io_tiles_abphy # ( + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .PINS_WDB (PINS_WDB), + .PINS_DB_IN_BYPASS (PINS_DB_IN_BYPASS), + .PINS_DB_OUT_BYPASS (PINS_DB_OUT_BYPASS), + .PINS_DB_OE_BYPASS (PINS_DB_OE_BYPASS), + .PINS_INVERT_WR (PINS_INVERT_WR), + .PINS_INVERT_OE (PINS_INVERT_OE), + .PINS_AC_HMC_DATA_OVERRIDE_ENA (PINS_AC_HMC_DATA_OVERRIDE_ENA), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_GPIO_MODE (PINS_GPIO_MODE), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL) + ) io_tiles_abphy_inst ( + .* + ); + end + else begin : nonabphy_setoutputs + assign phy_reset_n_abphy = 'd0; + assign phy_fb_clk_to_pll_abphy = 'd0; + assign core_clks_from_cpa_pri_abphy = 'd0; + assign core_clks_locked_cpa_pri_abphy = 'd0; + assign core_clks_from_cpa_sec_abphy = 'd0; + assign core_clks_locked_cpa_sec_abphy = 'd0; + assign ctl2core_avl_cmd_ready_0_abphy = 'd0; + assign ctl2core_avl_cmd_ready_1_abphy = 'd0; + assign ctl2core_avl_rdata_id_0_abphy = 'd0; + assign ctl2core_avl_rdata_id_1_abphy = 'd0; + assign l2core_rd_data_vld_avl0_abphy = 'd0; + assign l2core_wr_data_rdy_ast_abphy = 'd0; + assign l2core_wb_pointer_for_ecc_abphy = 'd0; + assign l2core_data_abphy = 'd0; + assign l2core_rdata_valid_abphy = 'd0; + assign l2core_afi_rlat_abphy = 'd0; + assign l2core_afi_wlat_abphy = 'd0; + assign t2c_afi_abphy = 'd0; + assign ctl2core_sideband_0_abphy = 'd0; + assign ctl2core_sideband_1_abphy = 'd0; + assign ctl2core_mmr_0_abphy = 'd0; + assign ctl2core_mmr_1_abphy = 'd0; + assign l2b_data_abphy = 'd0; + assign l2b_oe_abphy = 'd0; + assign l2b_dtc_abphy = 'd0; + assign pa_dprio_block_select_abphy = 'd0; + assign pa_dprio_readdata_abphy = 'd0; + assign runAbstractPhySim = 'd0; + end + endgenerate + + altera_emif_arch_nf_abphy_mux #( + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES) + ) altera_emif_arch_nf_abphy_mux_inst ( + .* + ); + + integer i, j; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_oct.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_oct.sv new file mode 100644 index 000000000000..d8ee6668d5df --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_oct.sv @@ -0,0 +1,433 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) + +module altera_emif_arch_nf_oct #( + parameter OCT_CONTROL_WIDTH = 1, + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_USERMODE_OCT = 1, + parameter PHY_PERIODIC_OCT_RECAL = 1, + parameter PHY_CONFIG_ENUM = "CONFIG_PHY_AND_HARD_CTRL", + parameter IS_HPS = 0 +) ( + input logic afi_clk, + input logic afi_reset_n, + input logic emif_usr_clk, + input logic emif_usr_reset_n, + input logic oct_cal_req, + output logic oct_cal_rdy, + output logic oct_recal_req, + input logic oct_s2pload_ena, + output logic oct_s2pload_rdy, + input logic pll_ref_clk_int, + input logic phy_reset_n, + + input logic oct_rzqin, + output logic [OCT_CONTROL_WIDTH-1:0] oct_stc, + output logic [OCT_CONTROL_WIDTH-1:0] oct_ptc +); + timeunit 1ns; + timeprecision 1ps; + + typedef enum + { + ST_OCTFSM_RESET, + ST_OCTFSM_WAIT_IDLE, + ST_OCTFSM_WAIT_REQ_HI, + ST_OCTFSM_WAIT_BUSY_HI, + ST_OCTFSM_WAIT_BUSY_LO, + ST_OCTFSM_WAIT_REQ_LO, + ST_OCTFSM_DONE + } ST_OCTFSM; + + localparam OCT_CAL_MODE = "A_OCT_CAL_MODE_AUTO"; + localparam OCT_USER_OCT = (PHY_USERMODE_OCT == 1) ? "A_OCT_USER_OCT_ON" : "A_OCT_USER_OCT_OFF"; + localparam OCT_CLK_DIV_CNT_SHIFT = 4; + localparam OCT_S2P_HANDSHAKE = (PHY_PERIODIC_OCT_RECAL == 1) ? "true" : "false"; + + localparam OCT_REFCLK_FREQ_MHZ = 1000000 / PLL_REF_CLK_FREQ_PS; + localparam OCT_RECAL_INTERVAL_MS = 500; + localparam OCT_RECAL_TIMER_PRESET = (OCT_RECAL_INTERVAL_MS * OCT_REFCLK_FREQ_MHZ * 1000 / (2 ** OCT_CLK_DIV_CNT_SHIFT)) - 1; + localparam OCT_RECAL_TIMER_WIDTH = 32; + + generate + if (PHY_CALIBRATED_OCT) begin : cal_oct + + if (PHY_USERMODE_OCT) begin : manual_oct_cal + wire w_clk; + wire w_oct_cal_request; + wire w_oct_clock; + wire w_oct_reset; + wire w_oct_cal_shift_busy; + wire w_oct_cal_busy; + wire w_oct_s2pload_ena; + wire w_oct_s2pload_rdy; + wire [15:0] w_oct_0_ser_term_ctrl; + wire [15:0] w_oct_0_par_term_ctrl; + wire [15:0] w_oct_1_ser_term_ctrl; + wire [15:0] w_oct_1_par_term_ctrl; + wire [15:0] w_oct_2_ser_term_ctrl; + wire [15:0] w_oct_2_par_term_ctrl; + wire [15:0] w_oct_3_ser_term_ctrl; + wire [15:0] w_oct_3_par_term_ctrl; + wire [15:0] w_oct_4_ser_term_ctrl; + wire [15:0] w_oct_4_par_term_ctrl; + wire [15:0] w_oct_5_ser_term_ctrl; + wire [15:0] w_oct_5_par_term_ctrl; + wire [15:0] w_oct_6_ser_term_ctrl; + wire [15:0] w_oct_6_par_term_ctrl; + wire [15:0] w_oct_7_ser_term_ctrl; + wire [15:0] w_oct_7_par_term_ctrl; + wire [15:0] w_oct_8_ser_term_ctrl; + wire [15:0] w_oct_8_par_term_ctrl; + wire [15:0] w_oct_9_ser_term_ctrl; + wire [15:0] w_oct_9_par_term_ctrl; + wire [15:0] w_oct_10_ser_term_ctrl; + wire [15:0] w_oct_10_par_term_ctrl; + wire [15:0] w_oct_11_ser_term_ctrl; + wire [15:0] w_oct_11_par_term_ctrl; + + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic [2:0] r_cal_req_metasync /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic [2:0] r_cal_rdy_metasync /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) logic [2:0] r_cal_rst_metasync /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + + logic r_cal_busy; + + ST_OCTFSM r_octfsm_cs; + ST_OCTFSM c_octfsm_ns; + logic r_octfsm_rdy; + logic c_octfsm_rdy; + logic r_octfsm_req; + logic c_octfsm_req; + + reg [7:0] r_clkdiv_ctr; + (* altera_attribute = {"-name GLOBAL_SIGNAL OFF"}*) reg r_clkdiv /* synthesis dont_merge syn_noprune syn_preserve = 1 */; + + altera_oct #( + .OCT_CAL_NUM(1), + .OCT_USER_MODE(OCT_USER_OCT), + .OCT_S2P_HANDSHAKE(OCT_S2P_HANDSHAKE), + .OCT_CAL_MODE_DER_0(OCT_CAL_MODE), + .OCT_CKBUF_MODE("true"), + .OCT_CAL_MODE_DER_1("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_2("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_3("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_4("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_5("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_6("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_7("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_8("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_9("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_10("A_OCT_CAL_MODE_SINGLE"), + .OCT_CAL_MODE_DER_11("A_OCT_CAL_MODE_SINGLE") + ) oct_inst ( + .rzqin(oct_rzqin), + .calibration_request(w_oct_cal_request), + .clock(w_oct_clock), + .reset(w_oct_reset), + .calibration_shift_busy(w_oct_cal_shift_busy), + .calibration_busy(w_oct_cal_busy), + .s2pload_ena(w_oct_s2pload_ena), + .s2pload_rdy(w_oct_s2pload_rdy), + .oct_0_series_termination_control(w_oct_0_ser_term_ctrl), + .oct_0_parallel_termination_control(w_oct_0_par_term_ctrl), + .oct_1_series_termination_control(w_oct_1_ser_term_ctrl), + .oct_1_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_2_series_termination_control(w_oct_2_ser_term_ctrl), + .oct_2_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_3_series_termination_control(w_oct_3_ser_term_ctrl), + .oct_3_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_4_series_termination_control(w_oct_4_ser_term_ctrl), + .oct_4_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_5_series_termination_control(w_oct_5_ser_term_ctrl), + .oct_5_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_6_series_termination_control(w_oct_6_ser_term_ctrl), + .oct_6_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_7_series_termination_control(w_oct_7_ser_term_ctrl), + .oct_7_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_8_series_termination_control(w_oct_8_ser_term_ctrl), + .oct_8_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_9_series_termination_control(w_oct_9_ser_term_ctrl), + .oct_9_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_10_series_termination_control(w_oct_10_ser_term_ctrl), + .oct_10_parallel_termination_control(w_oct_1_par_term_ctrl), + .oct_11_series_termination_control(w_oct_11_ser_term_ctrl), + .oct_11_parallel_termination_control(w_oct_1_par_term_ctrl) + ); + + initial + begin + r_clkdiv_ctr[7:0] <= 8'b0000_0000; + r_clkdiv <= 1'b0; + end + always @(posedge pll_ref_clk_int) + begin + if (r_clkdiv_ctr[7:0] == ((1< phy_clk_phs[7:0] FR clocks, 8 phases (45-deg apart) +// vcoph[0] -> DLL FR clock to DLL +// C-counter 0 lvds_clk[0] -> phy_clk[1] Secondary PHY clock tree (C2P/P2C rate) +// C-counter 1 loaden[0] -> phy_clk[0] Primary PHY clock tree (PHY/HMC rate) +// C-counter 2 phy_clk[2] Feedback PHY clock tree (slowest phy clock in system) +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_pll #( + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 1, + + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_OUT_EN_8 = "" +) ( + input logic global_reset_n_int, + input logic pll_ref_clk_int, + output logic pll_locked, + output logic pll_dll_clk, + output logic [7:0] phy_clk_phs, + output logic [1:0] phy_clk, + output logic phy_fb_clk_to_tile, + input logic phy_fb_clk_to_pll, + output logic [8:0] pll_c_counters, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_NF_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done +); + timeunit 1ns; + timeprecision 1ps; + + logic [7:0] pll_vcoph; + logic [1:0] pll_loaden; + logic [1:0] pll_lvds_clk; + + logic pll_dprio_clk; + logic pll_dprio_rst_n; + logic [8:0] pll_dprio_address; + logic pll_dprio_read; + logic [7:0] pll_dprio_readdata; + logic pll_dprio_write; + logic [7:0] pll_dprio_writedata; + logic pll_reset_n; + + assign phy_clk_phs = pll_vcoph; + + assign phy_clk[0] = pll_loaden[0]; // C-cnt 1 drives phy_clk 0 through a delay chain (swapping is intentional) + assign phy_clk[1] = pll_lvds_clk[0]; // C-cnt 0 drives phy_clk 1 through a delay chain (swapping is intentional) + +`ifdef ALTERA_A10_IOPLL_BOOTSTRAP + localparam PHY_IOPLL_WORKAROUND_LOCAL = 1; +`else + localparam PHY_IOPLL_WORKAROUND_LOCAL = 0; +`endif + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("PLLL"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) pll_lock_issp ( + .probe (pll_locked) + ); + +`endif + + twentynm_iopll # ( + + //////////////////////////////////// + // VCO and Ref clock + // fVCO = fRefClk * M * CCnt2 / N + //////////////////////////////////// + .reference_clock_frequency (PLL_REF_CLK_FREQ_PS_STR), + .vco_frequency (PLL_VCO_FREQ_PS_STR), + + .pll_vco_ph0_en ("true"), // vcoph[0] is required to drive phy_clk_phs[0] + .pll_vco_ph1_en ("true"), // vcoph[1] is required to drive phy_clk_phs[1] + .pll_vco_ph2_en ("true"), // vcoph[2] is required to drive phy_clk_phs[2] + .pll_vco_ph3_en ("true"), // vcoph[3] is required to drive phy_clk_phs[3] + .pll_vco_ph4_en ("true"), // vcoph[4] is required to drive phy_clk_phs[4] + .pll_vco_ph5_en ("true"), // vcoph[5] is required to drive phy_clk_phs[5] + .pll_vco_ph6_en ("true"), // vcoph[6] is required to drive phy_clk_phs[6] + .pll_vco_ph7_en ("true"), // vcoph[7] is required to drive phy_clk_phs[7] + + //////////////////////////////////// + // Special clock selects + //////////////////////////////////// + .pll_dll_src ("pll_dll_src_ph0"), // Use vcoph[0] as DLL input + .pll_phyfb_mux ("lvds_tx_fclk"), // PHY clock feedback path selector + + //////////////////////////////////// + // M Counter + //////////////////////////////////// + .pll_m_counter_bypass_en (PLL_M_CNT_BYPASS_EN), + .pll_m_counter_even_duty_en (PLL_M_CNT_EVEN_DUTY_EN), + .pll_m_counter_high (PLL_M_CNT_HIGH), + .pll_m_counter_low (PLL_M_CNT_LOW), + .pll_m_counter_ph_mux_prst (0), + .pll_m_counter_prst (1), + .pll_m_counter_coarse_dly ("0 ps"), + .pll_m_counter_fine_dly ("0 ps"), + .pll_m_counter_in_src (PLL_M_CNT_IN_SRC), // Take VCO clock as input to M Counter + + //////////////////////////////////// + // N Counter (bypassed) + //////////////////////////////////// + .pll_n_counter_bypass_en (PLL_N_CNT_BYPASS_EN), + .pll_n_counter_odd_div_duty_en (PLL_N_CNT_EVEN_DUTY_EN), + .pll_n_counter_high (PLL_N_CNT_HIGH), + .pll_n_counter_low (PLL_N_CNT_LOW), + .pll_n_counter_coarse_dly ("0 ps"), + .pll_n_counter_fine_dly ("0 ps"), + + //////////////////////////////////// + // C Counter 0 (phy_clk[1]) + //////////////////////////////////// + .pll_c0_out_en (PLL_C_CNT_OUT_EN_0), // C-counter driving phy_clk[1] + .output_clock_frequency_0 (PLL_C_CNT_FREQ_PS_STR_0), + .phase_shift_0 (PLL_C_CNT_PHASE_PS_STR_0), + .duty_cycle_0 (PLL_C_CNT_DUTY_CYCLE_0), + .pll_c0_extclk_dllout_en ("true"), + .pll_c_counter_0_bypass_en (PLL_C_CNT_BYPASS_EN_0), + .pll_c_counter_0_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_0), + .pll_c_counter_0_high (PLL_C_CNT_HIGH_0), + .pll_c_counter_0_low (PLL_C_CNT_LOW_0), + .pll_c_counter_0_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_0), + .pll_c_counter_0_prst (PLL_C_CNT_PRST_0), + .pll_c_counter_0_coarse_dly ("0 ps"), + .pll_c_counter_0_fine_dly ("0 ps"), + .pll_c_counter_0_in_src ("c_m_cnt_in_src_ph_mux_clk"), + + //////////////////////////////////// + // C Counter 1 (phy_clk[0]) + //////////////////////////////////// + .pll_c1_out_en (PLL_C_CNT_OUT_EN_1), // C-counter driving phy_clk[0] + .output_clock_frequency_1 (PLL_C_CNT_FREQ_PS_STR_1), + .phase_shift_1 (PLL_C_CNT_PHASE_PS_STR_1), + .duty_cycle_1 (PLL_C_CNT_DUTY_CYCLE_1), + .pll_c1_extclk_dllout_en ("true"), + .pll_c_counter_1_bypass_en (PLL_C_CNT_BYPASS_EN_1), + .pll_c_counter_1_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_1), + .pll_c_counter_1_high (PLL_C_CNT_HIGH_1), + .pll_c_counter_1_low (PLL_C_CNT_LOW_1), + .pll_c_counter_1_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_1), + .pll_c_counter_1_prst (PLL_C_CNT_PRST_1), + .pll_c_counter_1_coarse_dly ("0 ps"), + .pll_c_counter_1_fine_dly ("0 ps"), + .pll_c_counter_1_in_src ("c_m_cnt_in_src_ph_mux_clk"), + + //////////////////////////////////// + // C Counter 2 (phy_clk[2]) + //////////////////////////////////// + .pll_c2_out_en (PLL_C_CNT_OUT_EN_2), // C-counter driving phy_clk[2] + .output_clock_frequency_2 (PLL_C_CNT_FREQ_PS_STR_2), + .phase_shift_2 (PLL_C_CNT_PHASE_PS_STR_2), + .duty_cycle_2 (PLL_C_CNT_DUTY_CYCLE_2), + .pll_c2_extclk_dllout_en ("true"), + .pll_c_counter_2_bypass_en (PLL_C_CNT_BYPASS_EN_2), + .pll_c_counter_2_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_2), + .pll_c_counter_2_high (PLL_C_CNT_HIGH_2), + .pll_c_counter_2_low (PLL_C_CNT_LOW_2), + .pll_c_counter_2_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_2), + .pll_c_counter_2_prst (PLL_C_CNT_PRST_2), + .pll_c_counter_2_coarse_dly ("0 ps"), + .pll_c_counter_2_fine_dly ("0 ps"), + .pll_c_counter_2_in_src ("c_m_cnt_in_src_ph_mux_clk"), + + //////////////////////////////////// + // C Counter 3 (unused) + //////////////////////////////////// + .pll_c3_out_en (PLL_C_CNT_OUT_EN_3), // C-counter driving cal_slave_clk + .output_clock_frequency_3 (PLL_C_CNT_FREQ_PS_STR_3), + .phase_shift_3 (PLL_C_CNT_PHASE_PS_STR_3), + .duty_cycle_3 (PLL_C_CNT_DUTY_CYCLE_3), + .pll_c_counter_3_bypass_en (PLL_C_CNT_BYPASS_EN_3), + .pll_c_counter_3_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_3), + .pll_c_counter_3_high (PLL_C_CNT_HIGH_3), + .pll_c_counter_3_low (PLL_C_CNT_LOW_3), + .pll_c_counter_3_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_3), + .pll_c_counter_3_prst (PLL_C_CNT_PRST_3), + .pll_c_counter_3_coarse_dly ("0 ps"), + .pll_c_counter_3_fine_dly ("0 ps"), + .pll_c_counter_3_in_src ("c_m_cnt_in_src_ph_mux_clk"), + + //////////////////////////////////// + // C Counter 4 (unused) + //////////////////////////////////// + .pll_c4_out_en (PLL_C_CNT_OUT_EN_4), // C-counter driving cal_master_clk + .output_clock_frequency_4 (PLL_C_CNT_FREQ_PS_STR_4), + .phase_shift_4 (PLL_C_CNT_PHASE_PS_STR_4), + .duty_cycle_4 (PLL_C_CNT_DUTY_CYCLE_4), + .pll_c_counter_4_bypass_en (PLL_C_CNT_BYPASS_EN_4), + .pll_c_counter_4_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_4), + .pll_c_counter_4_high (PLL_C_CNT_HIGH_4), + .pll_c_counter_4_low (PLL_C_CNT_LOW_4), + .pll_c_counter_4_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_4), + .pll_c_counter_4_prst (PLL_C_CNT_PRST_4), + .pll_c_counter_4_coarse_dly ("0 ps"), + .pll_c_counter_4_fine_dly ("0 ps"), + .pll_c_counter_4_in_src ("c_m_cnt_in_src_ph_mux_clk"), + + //////////////////////////////////// + // C Counter 5 (unused) + //////////////////////////////////// + .pll_c5_out_en (PLL_C_CNT_OUT_EN_5), // Not used by EMIF + .output_clock_frequency_5 (PLL_C_CNT_FREQ_PS_STR_5), // Don't care (unused c-counter) + .phase_shift_5 (PLL_C_CNT_PHASE_PS_STR_5), // Don't care (unused c-counter) + .duty_cycle_5 (PLL_C_CNT_DUTY_CYCLE_5), // Don't care (unused c-counter) + .pll_c_counter_5_bypass_en (PLL_C_CNT_BYPASS_EN_5), // Don't care (unused c-counter) + .pll_c_counter_5_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_5), // Don't care (unused c-counter) + .pll_c_counter_5_high (PLL_C_CNT_HIGH_5), // Don't care (unused c-counter) + .pll_c_counter_5_low (PLL_C_CNT_LOW_5), // Don't care (unused c-counter) + .pll_c_counter_5_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_5), // Don't care (unused c-counter) + .pll_c_counter_5_prst (PLL_C_CNT_PRST_5), // Don't care (unused c-counter) + .pll_c_counter_5_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_5_fine_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_5_in_src ("c_m_cnt_in_src_ph_mux_clk"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 6 (unused) + //////////////////////////////////// + .pll_c6_out_en (PLL_C_CNT_OUT_EN_6), // Not used by EMIF + .output_clock_frequency_6 (PLL_C_CNT_FREQ_PS_STR_6), // Don't care (unused c-counter) + .phase_shift_6 (PLL_C_CNT_PHASE_PS_STR_6), // Don't care (unused c-counter) + .duty_cycle_6 (PLL_C_CNT_DUTY_CYCLE_6), // Don't care (unused c-counter) + .pll_c_counter_6_bypass_en (PLL_C_CNT_BYPASS_EN_6), // Don't care (unused c-counter) + .pll_c_counter_6_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_6), // Don't care (unused c-counter) + .pll_c_counter_6_high (PLL_C_CNT_HIGH_6), // Don't care (unused c-counter) + .pll_c_counter_6_low (PLL_C_CNT_LOW_6), // Don't care (unused c-counter) + .pll_c_counter_6_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_6), // Don't care (unused c-counter) + .pll_c_counter_6_prst (PLL_C_CNT_PRST_6), // Don't care (unused c-counter) + .pll_c_counter_6_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_6_fine_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_6_in_src ("c_m_cnt_in_src_ph_mux_clk"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 7 (unused) + //////////////////////////////////// + .pll_c7_out_en (PLL_C_CNT_OUT_EN_7), // Not used by EMIF + .output_clock_frequency_7 (PLL_C_CNT_FREQ_PS_STR_7), // Don't care (unused c-counter) + .phase_shift_7 (PLL_C_CNT_PHASE_PS_STR_7), // Don't care (unused c-counter) + .duty_cycle_7 (PLL_C_CNT_DUTY_CYCLE_7), // Don't care (unused c-counter) + .pll_c_counter_7_bypass_en (PLL_C_CNT_BYPASS_EN_7), // Don't care (unused c-counter) + .pll_c_counter_7_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_7), // Don't care (unused c-counter) + .pll_c_counter_7_high (PLL_C_CNT_HIGH_7), // Don't care (unused c-counter) + .pll_c_counter_7_low (PLL_C_CNT_LOW_7), // Don't care (unused c-counter) + .pll_c_counter_7_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_7), // Don't care (unused c-counter) + .pll_c_counter_7_prst (PLL_C_CNT_PRST_7), // Don't care (unused c-counter) + .pll_c_counter_7_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_7_fine_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_7_in_src ("c_m_cnt_in_src_ph_mux_clk"), // Don't care (unused c-counter) + + //////////////////////////////////// + // C Counter 8 (unused) + //////////////////////////////////// + .pll_c8_out_en (PLL_C_CNT_OUT_EN_8), // Not used by EMIF + .output_clock_frequency_8 (PLL_C_CNT_FREQ_PS_STR_8), // Don't care (unused c-counter) + .phase_shift_8 (PLL_C_CNT_PHASE_PS_STR_8), // Don't care (unused c-counter) + .duty_cycle_8 (PLL_C_CNT_DUTY_CYCLE_8), // Don't care (unused c-counter) + .pll_c_counter_8_bypass_en (PLL_C_CNT_BYPASS_EN_8), // Don't care (unused c-counter) + .pll_c_counter_8_even_duty_en (PLL_C_CNT_EVEN_DUTY_EN_8), // Don't care (unused c-counter) + .pll_c_counter_8_high (PLL_C_CNT_HIGH_8), // Don't care (unused c-counter) + .pll_c_counter_8_low (PLL_C_CNT_LOW_8), // Don't care (unused c-counter) + .pll_c_counter_8_ph_mux_prst (PLL_C_CNT_PH_MUX_PRST_8), // Don't care (unused c-counter) + .pll_c_counter_8_prst (PLL_C_CNT_PRST_8), // Don't care (unused c-counter) + .pll_c_counter_8_coarse_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_8_fine_dly ("0 ps"), // Don't care (unused c-counter) + .pll_c_counter_8_in_src ("c_m_cnt_in_src_ph_mux_clk"), // Don't care (unused c-counter) + + //////////////////////////////////// + // Misc Delay Chains + //////////////////////////////////// + .pll_ref_buf_dly ("0 ps"), + .pll_cmp_buf_dly ("0 ps"), + + .pll_dly_0_enable ("true"), // Controls whether delay chain on phyclk[0] is enabled, must be true for phyclk to toggle + .pll_dly_1_enable ("true"), // Controls whether delay chain on phyclk[1] is enabled, must be true for phyclk to toggle + .pll_dly_2_enable ("true"), // Controls whether delay chain on phyclk[2] is enabled + .pll_dly_3_enable ("true"), // Controls whether delay chain on phyclk[3] is enabled + + .pll_coarse_dly_0 ("0 ps"), // Fine delay chain to skew phyclk[0] + .pll_coarse_dly_1 ("0 ps"), // Fine delay chain to skew phyclk[1] + .pll_coarse_dly_2 ("0 ps"), // Fine delay chain to skew phyclk[2] + .pll_coarse_dly_3 ("0 ps"), // Fine delay chain to skew phyclk[3] + + .pll_fine_dly_0 ("0 ps"), // Fine delay chain to skew phyclk[0] + .pll_fine_dly_1 ("0 ps"), // Fine delay chain to skew phyclk[1] + .pll_fine_dly_2 ("0 ps"), // Fine delay chain to skew phyclk[2] + .pll_fine_dly_3 ("0 ps"), // Fine delay chain to skew phyclk[3] + + //////////////////////////////////// + // Misc PLL Modes and Features + //////////////////////////////////// + .pll_enable ("true"), // Enable PLL + .pll_powerdown_mode ("false"), // PLL power down mode + .is_cascaded_pll ("false"), // EMIF assumes non-cascaded PLL for optimal jitter + + .compensation_mode ("emif"), // EMIF doesn't need PLL compensation. Alignment of core clocks and PHY clocks is handled by CPA + .pll_fbclk_mux_1 (PLL_FBCLK_MUX_1), // Setting required by DIRECT compensation + .pll_fbclk_mux_2 (PLL_FBCLK_MUX_2), // Setting required by DIRECT compensation + + .pll_extclk_0_enable ("false"), // EMIF PLL does not need to drive output clock pin + .pll_extclk_1_enable ("false"), // EMIF PLL does not need to drive output clock pin + + .pll_clkin_0_src ("pll_clkin_0_src_refclkin"), // + .pll_clkin_1_src ("pll_clkin_1_src_refclkin"), // + .pll_sw_refclk_src ("pll_sw_refclk_src_clk_0"), // + .pll_auto_clk_sw_en ("false"), // EMIF PLL does not use the automatic clock switch-over feature + .pll_clk_loss_sw_en ("false"), // EMIF PLL does not use the automatic clock switch-over feature + .pll_manu_clk_sw_en ("false"), // EMIF PLL does not use the automatic clock switch-over feature + .pll_ctrl_override_setting ("true"), + .pll_cp_compensation ("false"), + + .bw_sel (PLL_BW_SEL), // Bandwidth select + .pll_bwctrl (PLL_BW_CTRL), // Bandwidth control + .pll_cp_current_setting (PLL_CP_SETTING), // Charge pump setting + .pll_unlock_fltr_cfg (2), + + .pll_dprio_broadcast_en ("false"), + .pll_dprio_cvp_inter_sel ("false"), + .pll_dprio_force_inter_sel ("false"), + .pll_dprio_power_iso_en ("false") + + ) pll_inst ( + + .refclk (4'b0000), + .rst_n (pll_reset_n), + .loaden (pll_loaden), + .lvds_clk (pll_lvds_clk), + .vcoph (pll_vcoph), + .fblvds_in (phy_fb_clk_to_pll), + .fblvds_out (phy_fb_clk_to_tile), + .dll_output (pll_dll_clk), + .lock (pll_locked), + .outclk (pll_c_counters), + .fbclk_in (1'b0), + .fbclk_out (), + .zdb_in (1'b0), + .phase_done (pll_phase_done), + .pll_cascade_in (pll_ref_clk_int), + .pll_cascade_out (), + .extclk_output (), + .core_refclk (1'b0), + .dps_rst_n (1'b1), + .mdio_dis (1'b0), + .pfden (1'b1), + .phase_en (pll_phase_en), + .pma_csr_test_dis (1'b1), + .up_dn (pll_up_dn), + .extswitch (1'b0), + .clken (2'b00), // Don't care (extclk) + .cnt_sel (pll_cnt_sel), + .num_phase_shifts (pll_num_phase_shifts), + .clk0_bad (), + .clk1_bad (), + .clksel (), + .csr_clk (1'b1), + .csr_en (1'b1), + .csr_in (1'b1), + .csr_out (), + .dprio_clk (pll_dprio_clk), + .dprio_rst_n (pll_dprio_rst_n), + .dprio_address (pll_dprio_address), + .scan_mode_n (1'b1), + .scan_shift_n (1'b1), + .write (pll_dprio_write), + .read (pll_dprio_read), + .readdata (pll_dprio_readdata), + .writedata (pll_dprio_writedata), + .extclk_dft (), + .block_select (), + .lf_reset (), + .pipeline_global_en_n (), + .pll_pd (), + .vcop_en (), + .user_mode (1'b1) + ); + + generate + if (PHY_IOPLL_WORKAROUND_LOCAL != 1) + begin : gen_pll_dprio_tieoff + assign pll_dprio_clk = 1'b0; + assign pll_dprio_rst_n = 1'b1; + assign pll_dprio_address[8:0] = 9'b0_0000_0000; + assign pll_dprio_read = 1'b0; + assign pll_dprio_write = 1'b0; + assign pll_dprio_writedata[7:0] = 8'b0000_0000; + assign pll_reset_n = global_reset_n_int; + end + else + begin : gen_pll_dprio + iopll_bootstrap + #( + .PLL_CTR_RESYNC(1), + .PLL_AUTO_RESET_ON_LOSS_OF_LOCK(0) + ) + inst_iopll_bootstrap + ( + .u_dprio_clk(1'b0), + .u_dprio_rst_n(1'b1), + .u_dprio_address({9{1'b0}}), + .u_dprio_read(1'b0), + .u_dprio_write(1'b0), + .u_dprio_writedata({8{1'b0}}), + .u_rst_n(global_reset_n_int), + .pll_locked(pll_locked), + .pll_dprio_readdata(pll_dprio_readdata), + + .pll_dprio_clk(pll_dprio_clk), + .pll_dprio_rst_n(pll_dprio_rst_n), + .pll_dprio_address(pll_dprio_address), + .pll_dprio_read(pll_dprio_read), + .pll_dprio_write(pll_dprio_write), + .pll_dprio_writedata(pll_dprio_writedata), + .pll_rst_n(pll_reset_n), + .u_locked() + ); + end + endgenerate + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_extra_clks.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_extra_clks.sv new file mode 100644 index 000000000000..1c601fd1a3e5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_extra_clks.sv @@ -0,0 +1,91 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Expose extra core clocks from IOPLL +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_pll_extra_clks #( + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter DIAG_SIM_REGTEST_MODE = 0 +) ( + input logic pll_locked, + input logic [8:0] pll_c_counters, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + output logic pll_extra_clk_diag_ok +); + timeunit 1ns; + timeprecision 1ps; + + logic [3:0] pll_extra_clks; + + // Extra core clocks to user logic. + // These clocks are unrelated to EMIF core clock domains. The feature is intended as a + // way to reuse EMIF PLL to generate core clocks for designs in which physical PLLs are scarce. + assign pll_extra_clks = pll_c_counters[8:5]; + assign pll_extra_clk_0 = pll_extra_clks[0]; + assign pll_extra_clk_1 = pll_extra_clks[1]; + assign pll_extra_clk_2 = pll_extra_clks[2]; + assign pll_extra_clk_3 = pll_extra_clks[3]; + + // In internal test mode, generate additional counters clocked by the extra clocks + generate + genvar i; + + if (DIAG_SIM_REGTEST_MODE && PLL_NUM_OF_EXTRA_CLKS > 0) begin: test_mode + logic [PLL_NUM_OF_EXTRA_CLKS-1:0] pll_extra_clk_diag_done; + + for (i = 0; i < PLL_NUM_OF_EXTRA_CLKS; ++i) + begin : extra_clk + logic [9:0] counter; + + always_ff @(posedge pll_extra_clks[i] or negedge pll_locked) begin + if (~pll_locked) begin + counter <= '0; + pll_extra_clk_diag_done[i] <= 1'b0; + end else begin + if (~counter[9]) begin + counter <= counter + 1'b1; + end + pll_extra_clk_diag_done[i] <= counter[9]; + end + end + end + + assign pll_extra_clk_diag_ok = &pll_extra_clk_diag_done; + + end else begin : normal_mode + assign pll_extra_clk_diag_ok = 1'b1; + end + endgenerate + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_fast_sim.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_fast_sim.sv new file mode 100644 index 000000000000..a189831aa37d --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_pll_fast_sim.sv @@ -0,0 +1,137 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +// EMIF IOPLL instantiation for 20nm families +// +// The following table describes the usage of IOPLL by EMIF. +// +// PLL Counter Fanouts Usage +// ===================================================================================== +// VCO Outputs vcoph[7:0] -> phy_clk_phs[7:0] FR clocks, 8 phases (45-deg apart) +// vcoph[0] -> DLL FR clock to DLL +// C-counter 0 lvds_clk[0] -> phy_clk[1] Secondary PHY clock tree (C2P/P2C rate) +// C-counter 1 loaden[0] -> phy_clk[0] Primary PHY clock tree (PHY/HMC rate) +// C-counter 2 phy_clk[2] Feedback PHY clock tree (slowest phy clock in system) +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////////// +module altera_emif_arch_nf_pll_fast_sim #( + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_SIM_CAL_SLAVE_CLK_FREQ_PS = 0, + parameter PLL_SIM_CAL_MASTER_CLK_FREQ_PS = 0, + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 1 + +) ( + input logic global_reset_n_int, + input logic pll_ref_clk_int, + output logic pll_locked, + output logic pll_dll_clk, + output logic [7:0] phy_clk_phs, + output logic [1:0] phy_clk, + output logic phy_fb_clk_to_tile, + input logic phy_fb_clk_to_pll, + output logic [8:0] pll_c_counters, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_NF_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done +); + timeunit 1ps; + timeprecision 1ps; + + localparam VCO_PHASES = 8; + + reg vco_out, phyclk0_out, phyclk1_out, fbclk_out, cal_slave_clk_out, cal_master_clk_out; + reg [4:0] pll_lock_count; + initial begin + vco_out <= 1'b1; + forever #(PLL_SIM_VCO_FREQ_PS/2) vco_out <= ~vco_out; + end + initial begin + phyclk0_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_0_FREQ_PS/2) phyclk0_out <= ~phyclk0_out; + end + initial begin + phyclk1_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_1_FREQ_PS/2) phyclk1_out <= ~phyclk1_out; + end + initial begin + fbclk_out <= 1'b1; + #(PLL_SIM_VCO_FREQ_PS*PLL_SIM_PHY_CLK_VCO_PHASE_PS/VCO_PHASES); + forever #(PLL_SIM_PHYCLK_FB_FREQ_PS/2) fbclk_out <= ~fbclk_out; + end + initial begin + cal_slave_clk_out <= 1'b1; + forever #(PLL_SIM_CAL_SLAVE_CLK_FREQ_PS/2) cal_slave_clk_out <= ~cal_slave_clk_out; + end + initial begin + cal_master_clk_out <= 1'b1; + forever #(PLL_SIM_CAL_MASTER_CLK_FREQ_PS/2) cal_master_clk_out <= ~cal_master_clk_out; + end + + always @ (posedge vco_out or negedge global_reset_n_int) begin + if (~global_reset_n_int) begin + pll_lock_count <= 5'b0; + end else if (pll_lock_count != 5'b11111) begin + pll_lock_count <= pll_lock_count + 1; + end + end + + assign pll_locked = (pll_lock_count == 5'b11111); + assign pll_dll_clk = pll_locked & vco_out; + assign phy_clk_phs[0] = pll_locked & vco_out; + always @ (*) begin + phy_clk_phs[1] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[0]; + phy_clk_phs[2] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[1]; + phy_clk_phs[3] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[2]; + phy_clk_phs[4] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[3]; + phy_clk_phs[5] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[4]; + phy_clk_phs[6] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[5]; + phy_clk_phs[7] <= #(PLL_SIM_VCO_FREQ_PS/VCO_PHASES) phy_clk_phs[6]; + end + assign phy_clk = {pll_locked & phyclk1_out, pll_locked & phyclk0_out}; + assign phy_fb_clk_to_tile = pll_locked & fbclk_out; + assign pll_c_counters[0] = pll_locked & phyclk1_out; + assign pll_c_counters[1] = pll_locked & phyclk0_out; + assign pll_c_counters[2] = pll_locked & fbclk_out; + assign pll_c_counters[3] = pll_locked & cal_slave_clk_out; + assign pll_c_counters[4] = pll_locked & cal_master_clk_out; + assign pll_c_counters[8:5] = 5'b0; + assign pll_phase_done = 1'b1; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_regs.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_regs.sv new file mode 100644 index 000000000000..de4c43719cc5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_regs.sv @@ -0,0 +1,69 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// This module handles the creation of a conditional register stage +// This module may be used to implement a synchronizer (with properly selected +// REGISTER value) +/////////////////////////////////////////////////////////////////////////////// + +// The following ensures that the register stage isn't synthesized into +// RAM-based shift-regs (especially if customer logic implements another follow-on +// pipeline stage). RAM-based shift-regs can degrade timing for C2P/P2C transfers. +(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) + + module altera_emif_arch_nf_regs #( + parameter REGISTER = 0, + parameter WIDTH = 0 +) ( + input logic clk, + input logic reset_n, + input logic [WIDTH-1:0] data_in, + output logic [WIDTH-1:0] data_out +) /* synthesis dont_merge */; + timeunit 1ns; + timeprecision 1ps; + + generate + if (REGISTER == 0) begin + assign data_out = data_in; + + end else begin + logic [WIDTH-1:0] sr_out; + always_ff @(posedge clk or negedge reset_n) begin + if (~reset_n) begin + sr_out <= '0; + end else begin + sr_out <= data_in; + end + end + assign data_out = sr_out; + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_seq_if.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_seq_if.sv new file mode 100644 index 000000000000..e920eadf3ae6 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_arch_nf_seq_if.sv @@ -0,0 +1,285 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// This module is responsible for exposing control signals from/to the +// sequencer. +// +/////////////////////////////////////////////////////////////////////////////// + +module altera_emif_arch_nf_seq_if #( + parameter PHY_CONFIG_ENUM = "", + parameter USER_CLK_RATIO = 1, + parameter REGISTER_AFI = 0, + parameter PORT_AFI_RLAT_WIDTH = 1, + parameter PORT_AFI_WLAT_WIDTH = 1, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 1, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 1, + parameter PHY_USERMODE_OCT = 0, + parameter PHY_PERIODIC_OCT_RECAL = 0, + parameter PHY_HAS_DCC = 0, + parameter IS_HPS = 0 +) ( + input logic afi_clk, + input logic afi_reset_n, + input logic emif_usr_clk, + input logic emif_usr_reset_n, + output logic afi_cal_success, + output logic afi_cal_fail, + output logic afi_cal_in_progress, + input logic afi_cal_req, + output logic [PORT_AFI_RLAT_WIDTH-1:0] afi_rlat, + output logic [PORT_AFI_WLAT_WIDTH-1:0] afi_wlat, + output logic [PORT_AFI_SEQ_BUSY_WIDTH-1:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + output logic [16:0] c2t_afi, + input logic [25:0] t2c_afi, + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + output logic [PORT_HPS_EMIF_E2H_GP_WIDTH-1:0] emif_to_hps_gp, + output logic oct_cal_req, + input logic oct_cal_rdy, + input logic oct_recal_req, + output logic oct_s2pload_ena, + input logic oct_s2pload_rdy, + output logic dcc_stable +); + timeunit 1ns; + timeprecision 1ps; + + logic clk; + logic reset_n; + + generate + if (PHY_CONFIG_ENUM == "CONFIG_PHY_AND_HARD_CTRL") begin : hmc + assign clk = emif_usr_clk; + assign reset_n = emif_usr_reset_n; + end else begin : non_hmc + assign clk = afi_clk; + assign reset_n = afi_reset_n; + end + endgenerate + + assign c2t_afi[4:0] = '0; + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) afi_cal_req_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (afi_cal_req), + .data_out (c2t_afi[8]) + ); + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (4) + ) afi_ctl_refresh_done_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in ({4{afi_ctl_refresh_done}}), + .data_out (c2t_afi[12:9]) + ); + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (4) + ) afi_ctl_long_idle_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in ({4{afi_ctl_long_idle}}), + .data_out (c2t_afi[16:13]) + ); + + generate + if (PHY_USERMODE_OCT == 1) begin : gen_oct_cal_rdy + if (IS_HPS == 0) begin : gen_oct_cal_rdy_no_hps + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) oct_cal_rdy_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (oct_cal_rdy), + .data_out (c2t_afi[7]) + ); + if (PHY_PERIODIC_OCT_RECAL == 1) begin : gen_oct_recal_rdy + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) oct_recal_req_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (oct_recal_req), + .data_out (c2t_afi[6]) + ); + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) oct_s2pload_ena_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (oct_s2pload_rdy), + .data_out (c2t_afi[5]) + ); + end else begin : gen_no_oct_recal_rdy + assign c2t_afi[6] = 1'b0; + assign c2t_afi[5] = 1'b1; + end + assign emif_to_hps_gp[0] = 1'b0; + end else begin : gen_oct_cal_rdy_hps + assign c2t_afi[7] = 1'b0; + assign c2t_afi[6] = 1'b0; + assign c2t_afi[5] = 1'b1; + assign emif_to_hps_gp[0] = oct_cal_rdy; + end + end else begin : gen_no_oct_cal_rdy + assign c2t_afi[7] = 1'b0; + assign c2t_afi[6] = 1'b0; + assign c2t_afi[5] = 1'b1; + assign emif_to_hps_gp[0] = 1'b0; + end + endgenerate + + + + logic [PORT_AFI_RLAT_WIDTH-1:0] pre_adjusted_afi_rlat; + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (6) + ) afi_rlat_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[5:0]), + .data_out (pre_adjusted_afi_rlat) + ); + + assign afi_rlat = (REGISTER_AFI ? (pre_adjusted_afi_rlat + 2'b10) : pre_adjusted_afi_rlat); + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (6) + ) afi_wlat_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[11:6]), + .data_out (afi_wlat) + ); + + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (4) + ) afi_seq_busy_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[23:20]), + .data_out (afi_seq_busy) + ); + + localparam SYNC_LENGTH = 3; + + altera_emif_arch_nf_regs # ( + .REGISTER (SYNC_LENGTH), + .WIDTH (1) + ) afi_cal_success_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[24]), + .data_out (afi_cal_success) + ); + + altera_emif_arch_nf_regs # ( + .REGISTER (SYNC_LENGTH), + .WIDTH (1) + ) afi_cal_fail_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[25]), + .data_out (afi_cal_fail) + ); + + altera_emif_arch_nf_regs # ( + .REGISTER (SYNC_LENGTH), + .WIDTH (1) + ) afi_cal_in_progress_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[16]), + .data_out (afi_cal_in_progress) + ); + + generate + if (PHY_USERMODE_OCT == 1) begin : gen_oct_cal_req + if (IS_HPS == 0) begin : gen_oct_cal_req_no_hps + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) oct_cal_req_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[19]), + .data_out (oct_cal_req) + ); + if (PHY_PERIODIC_OCT_RECAL == 1) begin : gen_oct_recal_ena + altera_emif_arch_nf_regs # ( + .REGISTER (REGISTER_AFI), + .WIDTH (1) + ) oct_s2pload_ena_regs ( + .clk (clk), + .reset_n (reset_n), + .data_in (t2c_afi[17]), + .data_out (oct_s2pload_ena) + ); + end else begin : gen_no_oct_recal_ena + assign oct_s2pload_ena = 1'b1; + end + end else begin : gen_oct_cal_req_hps + assign oct_cal_req = hps_to_emif_gp[0]; + assign oct_s2pload_ena = 1'b1; + end + end else begin : gen_no_oct_cal_req + assign oct_cal_req = 1'b0; + assign oct_s2pload_ena = 1'b1; + end + endgenerate + + generate + if (PHY_HAS_DCC == 1) begin : gen_has_dcc + if (IS_HPS == 0) begin : gen_has_dcc_no_hps + assign dcc_stable = t2c_afi[18]; + end else begin : gen_has_dcc_hps + assign dcc_stable = 1'b1; + end + end else begin : gen_no_dcc + assign dcc_stable = 1'b1; + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_db_chip.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_db_chip.sv new file mode 100644 index 000000000000..d1b893727a30 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_db_chip.sv @@ -0,0 +1,104 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// Basic simulation model of DDR4 Data Buffer used by LRDIMM +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_ddr4_model_db_chip ( + input BCK_t, + input BCK_c, + input BCKE, + input BODT, + input BVrefCA, + input [3:0] BCOM, + + inout [7:0] MDQ, + inout MDQS0_t, + inout MDQS0_c, + inout MDQS1_t, + inout MDQS1_c, + + inout [7:0] DQ, + inout DQS0_t, + inout DQS0_c, + inout DQS1_t, + inout DQS1_c, + + output ALERT_n, + + input VDD, + input VSS +); + + timeunit 1ps; + timeprecision 1ps; + + genvar i; + + generate + for (i = 0; i < 8; i = i + 1) begin : gen_dq_delay + altera_emif_ddrx_model_bidir_delay #( + .DELAY (1.0) + ) inst_dq_bidir_dly ( + .porta (MDQ[i]), + .portb (DQ[i]) + ); + end + endgenerate + + altera_emif_ddrx_model_bidir_delay #( + .DELAY (1.0) + ) dqs_p_0 ( + .porta (MDQS0_t), + .portb (DQS0_t) + ); + + altera_emif_ddrx_model_bidir_delay #( + .DELAY (1.0) + ) dqs_n_0 ( + .porta (MDQS0_c), + .portb (DQS0_c) + ); + + altera_emif_ddrx_model_bidir_delay #( + .DELAY (1.0) + ) dqs_p_1 ( + .porta (MDQS1_t), + .portb (DQS1_t) + ); + + altera_emif_ddrx_model_bidir_delay #( + .DELAY (1.0) + ) dqs_n_1 ( + .porta (MDQS1_c), + .portb (DQS1_c) + ); + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_rcd_chip.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_rcd_chip.sv new file mode 100644 index 000000000000..3304a29175c3 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddr4_model_rcd_chip.sv @@ -0,0 +1,1563 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// Basic simulation model of DDR4 Registering Clock Driver used by RDIMM and LRDIMM +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_ddr4_model_rcd_chip # ( + parameter ADDRESS_MIRRORING = 1, + parameter PORT_MEM_CS_N_WIDTH = 1 +) ( + input [1:0] DCKE, + input [1:0] DODT, + input [3:0] DCS_n, + input [2:0] DC, + + input [17:0] DA, + input [1:0] DBA, + input [1:0] DBG, + input DACT_n, + + input CK_t, + input CK_c, + + input DRST_n, + + input DPAR, + + input ERROR_IN_n, + + output BODT, + output BCKE, + output [3:0] BCOM, + output BCK_t, + output BCK_c, + output BVrefCA, + + output logic [1:0] QACKE, + output logic [1:0] QBCKE, + output logic [1:0] QAODT, + output logic [1:0] QBODT, + output logic [3:0] QACS_n, + output logic [3:0] QBCS_n, + output logic [1:0] QAC, + output logic [1:0] QBC, + + output logic [17:0] QAA, + output logic [17:0] QBA, + output logic [1:0] QABA, + output logic [1:0] QABG, + output logic [1:0] QBBA, + output logic [1:0] QBBG, + output logic QAACT_n, + output logic QBACT_n, + + output [3:0] Y_c, + output [3:0] Y_t, + + output logic QRST_n, + + output logic QAPAR, + output logic QBPAR, + + output logic ALERT_n, + + inout SDA, + input [2:0] SA, + input SCL, + input BFUNC, + input VDDSPD, + + input VDD, + input VSS, + input AVDD, + input PVDD, + input PVSS +); + + timeunit 1ps; + timeprecision 1ps; + + typedef enum + { + RC00, + RC01, + RC02, + RC03, + RC04, + RC05, + RC06, + RC07, + RC08, + RC09, + RC0A, + RC0B, + RC0C, + RC0D, + RC0E, + RC0F, + RC1X, + RC2X, + RC3X, + RC4X, + RC5X, + RC6X, + RC7X, + RC8X, + RC9X, + RCAX, + RCBX, + RC_NONE + } rcd_enum_t; + + typedef enum + { + OUTPUT_INVERSION_ENABLED, + OUTPUT_INVERSION_DISABLED + } rcd_oinv_t; + + typedef enum + { + WEAK_DRIVE_DISABLED, + WEAK_DRIVE_ENABLED + } rcd_wdrv_t; + + typedef enum + { + OUTPUT_ENABLED, + OUTPUT_DISABLED + } rcd_oe_t; + + typedef enum + { + ENABLED, + DISABLED + } rcd_en_t; + + typedef enum + { + FREQUENCY_BAND_OPERATION, + FREQUENCY_BAND_TEST_MODE + } rcd_freqband_t; + + typedef enum + { + DRIVE_LIGHT, + DRIVE_MODERATE, + DRIVE_STRONG, + DRIVE_VERYSTRONG + } rcd_drive_t; + + typedef enum + { + CMD_SOFT_RESET, + CMD_DB_RESET, + CMD_SET_DRAM_RESET, + CMD_CLR_DRAM_RESET, + CMD_CW_READ_OP, + CMD_CW_WRITE_OP, + CMD_CLR_PARITY_ERROR, + CMD_SOFT_RCD_RESET, + CMD_NOP + } rcd_cmd_cw_t; + + typedef enum + { + QXC_C_EN_111, + QXC_C_EN_011, + QXC_C_EN_001, + QXC_C_EN_000 + } rcd_qxc_t; + + typedef enum + { + CKE_POWERDOWN_IBT_ON, + CKE_POWERDOWN_IBT_OFF + } rcd_cke_pd_mode_t; + + typedef enum + { + RDIMM_SPEED_UP_TO_1600, + RDIMM_SPEED_1601_TO_1867, + RDIMM_SPEED_1868_TO_2134, + RDIMM_SPEED_2135_TO_2400, + RDIMM_SPEED_2401_TO_2667, + RDIMM_SPEED_2668_TO_3200, + RDIMM_SPEED_RESERVED, + RDIMM_SPEED_PLL_BYPASS + } rcd_rdimm_speed_t; + + typedef enum + { + RDIMM_SPEED_FINE_1241_TO_1260, + RDIMM_SPEED_FINE_1261_TO_1280, + RDIMM_SPEED_FINE_1281_TO_1300, + RDIMM_SPEED_FINE_1301_TO_1320, + RDIMM_SPEED_FINE_1321_TO_1340, + RDIMM_SPEED_FINE_1341_TO_1360, + RDIMM_SPEED_FINE_1361_TO_1380, + RDIMM_SPEED_FINE_1381_TO_1400, + RDIMM_SPEED_FINE_1401_TO_1420, + RDIMM_SPEED_FINE_1421_TO_1440, + RDIMM_SPEED_FINE_1441_TO_1460, + RDIMM_SPEED_FINE_1461_TO_1480, + RDIMM_SPEED_FINE_1481_TO_1500, + RDIMM_SPEED_FINE_1501_TO_1520, + RDIMM_SPEED_FINE_1521_TO_1540, + RDIMM_SPEED_FINE_1541_TO_1560, + RDIMM_SPEED_FINE_1561_TO_1580, + RDIMM_SPEED_FINE_1581_TO_1600, + RDIMM_SPEED_FINE_1601_TO_1620, + RDIMM_SPEED_FINE_1621_TO_1640, + RDIMM_SPEED_FINE_1641_TO_1660, + RDIMM_SPEED_FINE_1661_TO_1680, + RDIMM_SPEED_FINE_1681_TO_1700, + RDIMM_SPEED_FINE_1701_TO_1720, + RDIMM_SPEED_FINE_1721_TO_1740, + RDIMM_SPEED_FINE_1741_TO_1760, + RDIMM_SPEED_FINE_1761_TO_1780, + RDIMM_SPEED_FINE_1781_TO_1800, + RDIMM_SPEED_FINE_1801_TO_1820, + RDIMM_SPEED_FINE_1821_TO_1840, + RDIMM_SPEED_FINE_1841_TO_1860, + RDIMM_SPEED_FINE_1861_TO_1880, + RDIMM_SPEED_FINE_1881_TO_1900, + RDIMM_SPEED_FINE_1901_TO_1920, + RDIMM_SPEED_FINE_1921_TO_1940, + RDIMM_SPEED_FINE_1941_TO_1960, + RDIMM_SPEED_FINE_1961_TO_1980, + RDIMM_SPEED_FINE_1981_TO_2000, + RDIMM_SPEED_FINE_2001_TO_2020, + RDIMM_SPEED_FINE_2021_TO_2040, + RDIMM_SPEED_FINE_2041_TO_2060, + RDIMM_SPEED_FINE_2061_TO_2080, + RDIMM_SPEED_FINE_2081_TO_2100, + RDIMM_SPEED_FINE_2101_TO_2120, + RDIMM_SPEED_FINE_2121_TO_2140, + RDIMM_SPEED_FINE_2141_TO_2160, + RDIMM_SPEED_FINE_2161_TO_2180, + RDIMM_SPEED_FINE_2181_TO_2200, + RDIMM_SPEED_FINE_2201_TO_2220, + RDIMM_SPEED_FINE_2221_TO_2240, + RDIMM_SPEED_FINE_2241_TO_2260, + RDIMM_SPEED_FINE_2261_TO_2280, + RDIMM_SPEED_FINE_2281_TO_2300, + RDIMM_SPEED_FINE_2301_TO_2320, + RDIMM_SPEED_FINE_2321_TO_2340, + RDIMM_SPEED_FINE_2341_TO_2360, + RDIMM_SPEED_FINE_2361_TO_2380, + RDIMM_SPEED_FINE_2381_TO_2400, + RDIMM_SPEED_FINE_2401_TO_2420, + RDIMM_SPEED_FINE_2421_TO_2440, + RDIMM_SPEED_FINE_2441_TO_2460, + RDIMM_SPEED_FINE_2461_TO_2480, + RDIMM_SPEED_FINE_2481_TO_2500, + RDIMM_SPEED_FINE_2501_TO_2520, + RDIMM_SPEED_FINE_2521_TO_2540, + RDIMM_SPEED_FINE_2541_TO_2560, + RDIMM_SPEED_FINE_2561_TO_2580, + RDIMM_SPEED_FINE_2581_TO_2600, + RDIMM_SPEED_FINE_2601_TO_2620, + RDIMM_SPEED_FINE_2621_TO_2640, + RDIMM_SPEED_FINE_2641_TO_2660, + RDIMM_SPEED_FINE_2661_TO_2680, + RDIMM_SPEED_FINE_2681_TO_2700, + RDIMM_SPEED_FINE_2701_TO_2720, + RDIMM_SPEED_FINE_2721_TO_2740, + RDIMM_SPEED_FINE_2741_TO_2760, + RDIMM_SPEED_FINE_2761_TO_2780, + RDIMM_SPEED_FINE_2781_TO_2800, + RDIMM_SPEED_FINE_2801_TO_2820, + RDIMM_SPEED_FINE_2821_TO_2840, + RDIMM_SPEED_FINE_2841_TO_2860, + RDIMM_SPEED_FINE_2861_TO_2880, + RDIMM_SPEED_FINE_2881_TO_2900, + RDIMM_SPEED_FINE_2901_TO_2920, + RDIMM_SPEED_FINE_2921_TO_2940, + RDIMM_SPEED_FINE_2941_TO_2960, + RDIMM_SPEED_FINE_2961_TO_2980, + RDIMM_SPEED_FINE_2981_TO_3000, + RDIMM_SPEED_FINE_3001_TO_3020, + RDIMM_SPEED_FINE_3021_TO_3040, + RDIMM_SPEED_FINE_3041_TO_3060, + RDIMM_SPEED_FINE_3061_TO_3080, + RDIMM_SPEED_FINE_3081_TO_3100, + RDIMM_SPEED_FINE_3101_TO_3120, + RDIMM_SPEED_FINE_3121_TO_3140, + RDIMM_SPEED_FINE_3141_TO_3160, + RDIMM_SPEED_FINE_3161_TO_3180, + RDIMM_SPEED_FINE_3181_TO_3200 + } rcd_rdimm_fine_speed_t; + + typedef enum + { + CONTEXT_1, + CONTEXT_2 + } rcd_context_t; + + typedef enum + { + VDD_1P2V, + VDD_RESERVED_LOWER + } rcd_vdd_t; + + typedef enum + { + QVREFCA_VDD_HALF_BVREFCA_VDD_HALF, + QVREFCA_VREF_INT_BVREFCA_VDD_HALF, + QVREFCA_VDD_HALF_BVREFCA_VREF_INT, + QVREFCA_EXTERNAL_BVREFCA_EXTERNAL + } rcd_vrefca_src_t; + + typedef enum + { + RX_VREFIN_SRC_INTERNAL, + RX_VREFIN_SRC_EXTERNAL + } rcd_vrefin_src_t; + + typedef enum + { + NORMAL_MODE, + CLOCK_TO_CA_TRAINING_MODE, + DCS0N_LOOPBACK_MODE, + DCS1N_LOOPBACK_MODE, + DCKE0_LOOPBACK_MODE, + DCKE1_LOOPBACK_MODE, + DODT0_LOOPBACK_MODE, + DODT1_LOOPBACK_MODE + } rcd_training_mode; + + typedef enum + { + DIRECT_DUALCS_MODE, + DIRECT_QUADCS_MODE, + ENCODED_QUADCS_MODE + } rcd_cs_mode_t; + + typedef enum + { + LRDIMM, + RDIMM + } rcd_dimm_t; + + typedef enum + { + ALERT_N_STICKY, + ALERT_N_PULSE + } rcd_alert_assert_t; + + typedef enum + { + ALERT_N_REENABLE_OFF, + ALERT_N_REENABLE_ON + } rcd_alert_renable_t; + + typedef enum + { + LATENCY_1NCK, + LATENCY_2NCK, + LATENCY_3NCK, + LATENCY_4NCK, + LATENCY_0NCK + } rcd_latency_adder_t; + + typedef enum + { + VREFCA_INT_50P00, + VREFCA_INT_50P83, + VREFCA_INT_51P67, + VREFCA_INT_52P60, + VREFCA_INT_53P33, + VREFCA_INT_54P17, + VREFCA_INT_55P00, + VREFCA_INT_55P83, + VREFCA_INT_56P67, + VREFCA_INT_57P50, + VREFCA_INT_58P33, + VREFCA_INT_59P17, + VREFCA_INT_60P00, + VREFCA_INT_60P83, + VREFCA_INT_61P67, + VREFCA_INT_62P50, + VREFCA_INT_63P33, + VREFCA_INT_64P17, + VREFCA_INT_65P00, + VREFCA_INT_65P83, + VREFCA_INT_66P67, + VREFCA_INT_33P33, + VREFCA_INT_34P17, + VREFCA_INT_35P00, + VREFCA_INT_35P83, + VREFCA_INT_36P67, + VREFCA_INT_37P50, + VREFCA_INT_38P33, + VREFCA_INT_39P17, + VREFCA_INT_40P00, + VREFCA_INT_40P83, + VREFCA_INT_41P67, + VREFCA_INT_42P50, + VREFCA_INT_43P33, + VREFCA_INT_44P17, + VREFCA_INT_45P00, + VREFCA_INT_45P83, + VREFCA_INT_46P67, + VREFCA_INT_47P50, + VREFCA_INT_48P33, + VREFCA_INT_49P17 + } rcd_vrefca_int_t; + + typedef enum + { + ODT_ADDITION_OFF, + ODT_ADDITION_1CYC, + ODT_ADDITION_2CYC + } rcd_odt_addition_t; + + typedef enum + { + IBT_100OHM, + IBT_150OHM, + IBT_300OHM, + IBT_OFF + } rcd_ibt_t; + + typedef enum + { + ODT_WR_TIMING_0CYC, + ODT_WR_TIMING_1CYC + } rcd_odt_wr_timing_t; + + typedef enum + { + ODT_RD_TIMING_0CYC, + ODT_RD_TIMING_1CYC, + ODT_RD_TIMING_2CYC, + ODT_RD_TIMING_3CYC, + ODT_RD_TIMING_4CYC, + ODT_RD_TIMING_5CYC, + ODT_RD_TIMING_6CYC, + ODT_RD_TIMING_7CYC, + ODT_RD_TIMING_8CYC + } rcd_odt_rd_timing_t; + + typedef enum + { + QODT_CTRL_DODT01, + QODT_CTRL_DODT0, + QODT_CTRL_OFF, + QODT_CTRL_INTERNAL + } rcd_qodt_ctrl_t; + + typedef enum + { + QODT_ON, + QODT_OFF + } rcd_qodt_t; + + + typedef struct + { + rcd_enum_t current_rc; + + rcd_en_t rc00_output_inversion; + rcd_en_t rc00_weak_drive; + rcd_en_t rc00_a_outputs; + rcd_en_t rc00_b_outputs; + + rcd_en_t rc01_y0_clock; + rcd_en_t rc01_y1_clock; + rcd_en_t rc01_y2_clock; + rcd_en_t rc01_y3_clock; + + rcd_en_t rc02_da17_ibt; + rcd_en_t rc02_dpar_ibt; + rcd_en_t rc02_transparent_mode; + rcd_freqband_t rc02_freqband; + + rcd_drive_t rc03_qac_drive; + rcd_drive_t rc03_qcs_drive; + + rcd_drive_t rc04_qodt_drive; + rcd_drive_t rc04_qcke_drive; + + rcd_drive_t rc05_clka_drive; + rcd_drive_t rc05_clkb_drive; + + rcd_qxc_t rc08_qxc_outputs; + rcd_en_t rc08_qpar_outputs; + rcd_en_t rc08_a17; + + rcd_en_t rc09_dcs1_ibt; + rcd_en_t rc09_dcs1; + rcd_cke_pd_mode_t rc09_cke_pd_mode; + rcd_en_t rc09_cke_pd; + + rcd_rdimm_speed_t rc0a_rdimm_speed; + rcd_context_t rc0a_context; + + rcd_vdd_t rc0b_vdd; + rcd_vrefca_src_t rc0b_vrefca_src; + rcd_vrefin_src_t rc0b_vrefin_src; + + rcd_training_mode rc0c_training_mode; + + rcd_cs_mode_t rc0d_cs_mode; + rcd_dimm_t rc0d_dimm; + rcd_en_t rc0d_mrs_mirr; + + rcd_en_t rc0e_parity; + rcd_alert_assert_t rc0e_alert_assert; + rcd_alert_renable_t rc0e_alert_reenable; + + rcd_latency_adder_t rc0f_latency_adder; + + rcd_vrefca_int_t rc1x_vrefca_int; + + + rcd_rdimm_fine_speed_t rc3x_rdimm_fine_speed; + + + rcd_odt_addition_t rc5x_wr_odt_addition; + rcd_odt_addition_t rc5x_rd_odt_addition; + + rcd_ibt_t rc7x_ca_ibt; + rcd_ibt_t rc7x_dcs_ibt; + rcd_ibt_t rc7x_dcke_ibt; + rcd_ibt_t rc7x_dodt_ibt; + + rcd_odt_wr_timing_t rc8x_odt_wr_timing; + rcd_odt_rd_timing_t rc8x_odt_rd_timing; + rcd_en_t rc8x_bodt_outputs; + rcd_qodt_ctrl_t rc8x_qodt_ctrl; + + rcd_qodt_t rc9x_wr_qodt0_r0; + rcd_qodt_t rc9x_wr_qodt1_r0; + rcd_qodt_t rc9x_wr_qodt0_r1; + rcd_qodt_t rc9x_wr_qodt1_r1; + rcd_qodt_t rc9x_wr_qodt0_r2; + rcd_qodt_t rc9x_wr_qodt1_r2; + rcd_qodt_t rc9x_wr_qodt0_r3; + rcd_qodt_t rc9x_wr_qodt1_r3; + + rcd_qodt_t rcax_rd_qodt0_r0; + rcd_qodt_t rcax_rd_qodt1_r0; + rcd_qodt_t rcax_rd_qodt0_r1; + rcd_qodt_t rcax_rd_qodt1_r1; + rcd_qodt_t rcax_rd_qodt0_r2; + rcd_qodt_t rcax_rd_qodt1_r2; + rcd_qodt_t rcax_rd_qodt0_r3; + rcd_qodt_t rcax_rd_qodt1_r3; + + rcd_en_t rcbx_dc0_ibt; + rcd_en_t rcbx_dc1_ibt; + rcd_en_t rcbx_dc2_ibt; + rcd_en_t rcbx_ddr4db01_mrs_snoop; + rcd_en_t rcbx_ddr4rcd01_mrs_snoop; + rcd_en_t rcbx_dcke1_ibt; + rcd_en_t rcbx_dcke1; + + } rcd_t; + + + rcd_t rcd; + + logic mem_ck_diff; + + + assign Y_t = {4{CK_t}}; + assign Y_c = {4{CK_c}}; + + assign QRST_n = DRST_n; + + wire [3:0] active_ranks; + wire effective_DBG1; + assign active_ranks = {4'b0, ~DCS_n[PORT_MEM_CS_N_WIDTH-1:0]}; + assign effective_DBG1 = (ADDRESS_MIRRORING && (active_ranks & 4'b1010)) ? DBG[0] : DBG[1]; + + logic [3:0][17:0] QAA_pre_reg; + logic [3:0][17:0] QBA_pre_reg; + logic [3:0][1:0] QABA_pre_reg; + logic [3:0][1:0] QABG_pre_reg; + logic [3:0][1:0] QBBA_pre_reg; + logic [3:0][1:0] QBBG_pre_reg; + logic [3:0] QAACT_n_pre_reg; + logic [3:0] QBACT_n_pre_reg; + logic [3:0][3:0] QACS_n_pre_reg; + logic [3:0][3:0] QBCS_n_pre_reg; + logic [3:0][1:0] QAC_pre_reg; + logic [3:0][1:0] QBC_pre_reg; + logic [3:0][1:0] QAODT_pre_reg; + logic [3:0][1:0] QBODT_pre_reg; + logic [3:0][1:0] DCKE_reg; + logic [3:0] QAPAR_pre_reg; + logic [3:0] QBPAR_pre_reg; + + always_ff @(posedge CK_t) + begin + QAA_pre_reg[0] <= DA; + QBA_pre_reg[0] <= ((ADDRESS_MIRRORING) ? ({~DA[17], DA[16:14], ~DA[11], DA[12], ~DA[13], DA[10], ~DA[9], ~DA[7], ~DA[8], ~DA[5], ~DA[6], ~DA[3], ~DA[4], DA[2:0]}) : ({~DA[17], DA[16:14], ~DA[13], DA[12], ~DA[11], DA[10], ~DA[9:3], DA[2:0]})); + QABA_pre_reg[0] <= DBA; + QBBA_pre_reg[0] <= ((ADDRESS_MIRRORING) ? ({~DBA[0], ~DBA[1]}) : (~DBA)); + QABG_pre_reg[0] <= DBG; + QBBG_pre_reg[0] <= ((ADDRESS_MIRRORING) ? ({~DBG[0], ~DBG[1]}) : (~DBG)); + QAACT_n_pre_reg[0] <= DACT_n; + QBACT_n_pre_reg[0] <= DACT_n; + QACS_n_pre_reg[0] <= ((DACT_n == 1'b1) && (DA[16:14] == 3'b0) && (effective_DBG1 == 1'b1)) ? 4'b1111 : DCS_n; + QBCS_n_pre_reg[0] <= ((DACT_n == 1'b1) && (DA[16:14] == 3'b0) && (effective_DBG1 == 1'b0)) ? 4'b1111 : DCS_n; + QAC_pre_reg[0] <= DC; + QBC_pre_reg[0] <= DC; + QAODT_pre_reg[0] <= DODT; + QBODT_pre_reg[0] <= DODT; + DCKE_reg[0] <= DCKE; + QAPAR_pre_reg[0] <= DPAR; + QBPAR_pre_reg[0] <= ~DPAR; + + QAA_pre_reg[3:1] <= QAA_pre_reg[2:0]; + QBA_pre_reg[3:1] <= QBA_pre_reg[2:0]; + QABA_pre_reg[3:1] <= QABA_pre_reg[2:0]; + QBBA_pre_reg[3:1] <= QBBA_pre_reg[2:0]; + QABG_pre_reg[3:1] <= QABG_pre_reg[2:0]; + QBBG_pre_reg[3:1] <= QBBG_pre_reg[2:0]; + QAACT_n_pre_reg[3:1] <= QAACT_n_pre_reg[2:0]; + QBACT_n_pre_reg[3:1] <= QBACT_n_pre_reg[2:0]; + QACS_n_pre_reg[3:1] <= QACS_n_pre_reg[2:0]; + QBCS_n_pre_reg[3:1] <= QBCS_n_pre_reg[2:0]; + QAC_pre_reg[3:1] <= QAC_pre_reg[2:0]; + QBC_pre_reg[3:1] <= QBC_pre_reg[2:0]; + QAODT_pre_reg[3:1] <= QAODT_pre_reg[2:0]; + QBODT_pre_reg[3:1] <= QBODT_pre_reg[2:0]; + DCKE_reg[3:1] <= DCKE_reg[2:0]; + QAPAR_pre_reg[3:1] <= QAPAR_pre_reg[2:0]; + QBPAR_pre_reg[3:1] <= QBPAR_pre_reg[2:0]; + end + + always_comb + begin + if (rcd.rc0f_latency_adder == LATENCY_1NCK) begin + QAA = QAA_pre_reg[2]; + QBA = QBA_pre_reg[2]; + QABA = QABA_pre_reg[2]; + QBBA = QBBA_pre_reg[2]; + QABG = QABG_pre_reg[2]; + QBBG = QBBG_pre_reg[2]; + QAACT_n = QAACT_n_pre_reg[2]; + QBACT_n = QBACT_n_pre_reg[2]; + QACS_n = QACS_n_pre_reg[2]; + QBCS_n = QBCS_n_pre_reg[2]; + QAC = QAC_pre_reg[2]; + QBC = QBC_pre_reg[2]; + QAODT = QAODT_pre_reg[2]; + QBODT = QBODT_pre_reg[2]; + + QAPAR = QAPAR_pre_reg[1]; + QBPAR = QBPAR_pre_reg[1]; + + QACKE = DCKE_reg[0] || DCKE_reg[1] || DCKE_reg[2]; + QBCKE = DCKE_reg[0] || DCKE_reg[1] || DCKE_reg[2]; + + end else if (rcd.rc0f_latency_adder == LATENCY_2NCK) begin + QAA = QAA_pre_reg[3]; + QBA = QBA_pre_reg[3]; + QABA = QABA_pre_reg[3]; + QBBA = QBBA_pre_reg[3]; + QABG = QABG_pre_reg[3]; + QBBG = QBBG_pre_reg[3]; + QAACT_n = QAACT_n_pre_reg[3]; + QBACT_n = QBACT_n_pre_reg[3]; + QACS_n = QACS_n_pre_reg[3]; + QBCS_n = QBCS_n_pre_reg[3]; + QAC = QAC_pre_reg[3]; + QBC = QBC_pre_reg[3]; + QAODT = QAODT_pre_reg[3]; + QBODT = QBODT_pre_reg[3]; + + QAPAR = QAPAR_pre_reg[2]; + QBPAR = QBPAR_pre_reg[2]; + + QACKE = DCKE_reg[0] || DCKE_reg[1] || DCKE_reg[2] || DCKE_reg[3]; + QBCKE = DCKE_reg[0] || DCKE_reg[1] || DCKE_reg[2] || DCKE_reg[3]; + end else begin + $error("Model does not support RC0F Latency Adder Mode other than 1CK or 2CK"); + end + end + + localparam PARITY_TO_ALERT_N_LATENCY = 3; + localparam PARITY_PULSE_WIDTH = 48; + localparam ALERT_N_PIPELINE_SIZE = PARITY_PULSE_WIDTH + PARITY_TO_ALERT_N_LATENCY + 1; + + bit expected_parity; + bit parity_cmp_en; + bit [ALERT_N_PIPELINE_SIZE-1:0] parity_alert_n_pipeline; + + always @(posedge mem_ck_diff) + begin + if (rcd.rc0e_parity == ENABLED) + begin + if (DCS_n[PORT_MEM_CS_N_WIDTH-1:0] != {PORT_MEM_CS_N_WIDTH{1'b1}}) begin + expected_parity <= ^{DA, DBA, DBG, DACT_n, DC}; + parity_cmp_en <= 1'b1; + end else begin + expected_parity <= 1'b0; + parity_cmp_en <= 1'b0; + end + + if (parity_cmp_en) begin + if (DPAR != expected_parity) begin + parity_alert_n_pipeline[ALERT_N_PIPELINE_SIZE-1:PARITY_TO_ALERT_N_LATENCY] <= '0; + parity_alert_n_pipeline[PARITY_TO_ALERT_N_LATENCY-1:0] <= parity_alert_n_pipeline[PARITY_TO_ALERT_N_LATENCY:1]; + end else begin + parity_alert_n_pipeline <= {1'b1, parity_alert_n_pipeline[ALERT_N_PIPELINE_SIZE-1:1]}; + end + end else begin + parity_alert_n_pipeline <= {1'b1, parity_alert_n_pipeline[ALERT_N_PIPELINE_SIZE-1:1]}; + end + end + end + + assign ALERT_n = ERROR_IN_n && parity_alert_n_pipeline[0]; + + function string rc_string (rcd_enum_t rcd); + case (rcd) + RC00: rc_string = "Global Features Control Word"; + RC01: rc_string = "Clock Driver Enable Control Word"; + RC02: rc_string = "Timing and IBT Control Word"; + RC03: rc_string = "CA and CS Signals Driver Characteristics Control Word"; + RC04: rc_string = "ODT and CKE Signals Driver Characteristics Control Word"; + RC05: rc_string = "Clock Driver Characteristics Control Word"; + RC06: rc_string = "Command Space Control Word"; + RC07: rc_string = "RFU"; + RC08: rc_string = "Input/Output Configuration Control Word"; + RC09: rc_string = "Power Saving Settings Control Word"; + RC0A: rc_string = "RDIMM Operating Speed"; + RC0B: rc_string = "Operating Voltage VDD and VREF Source Control Word"; + RC0C: rc_string = "Training Control Word"; + RC0D: rc_string = "DIMM Configuration Control Word"; + RC0E: rc_string = "Parity Control Word"; + RC0F: rc_string = "Command Latency Adder Control Word"; + + RC1X: rc_string = "Internal Vref Control Word"; + RC2X: rc_string = "I2C Bus Control Word"; + RC3X: rc_string = "Fine Granularity RDIMM Operating Speed"; + RC4X: rc_string = "CW Source Selection Control Word"; + RC5X: rc_string = "CW Destination Selection & Write/Read Additional QxODT[1:0] Signal High Control word"; + RC6X: rc_string = "CW Data Control Word"; + RC7X: rc_string = "IBT Control Word"; + RC8X: rc_string = "ODT Control Word"; + RC9X: rc_string = "QxODT[1:0] Write Pattern Control Word"; + RCAX: rc_string = "QxODT[1:0] Read Pattern Control Word"; + RCBX: rc_string = "IBT and MRS Snoop Control Word"; + default: rc_string = "Error - Unknown RCD Value"; + + endcase + endfunction + + task rcd_reset(); + rcd.rc00_output_inversion = ENABLED; + rcd.rc00_weak_drive = DISABLED; + rcd.rc00_a_outputs = ENABLED; + rcd.rc00_b_outputs = ENABLED; + + rcd.rc01_y0_clock = ENABLED; + rcd.rc01_y1_clock = ENABLED; + rcd.rc01_y2_clock = ENABLED; + rcd.rc01_y3_clock = ENABLED; + + rcd.rc02_da17_ibt = ENABLED; + rcd.rc02_dpar_ibt = ENABLED; + rcd.rc02_transparent_mode = DISABLED; + rcd.rc02_freqband = FREQUENCY_BAND_OPERATION; + + rcd.rc03_qac_drive = DRIVE_LIGHT; + rcd.rc03_qcs_drive = DRIVE_LIGHT; + + rcd.rc04_qodt_drive = DRIVE_LIGHT; + rcd.rc04_qcke_drive = DRIVE_LIGHT; + + rcd.rc05_clka_drive = DRIVE_LIGHT; + rcd.rc05_clkb_drive = DRIVE_LIGHT; + + rcd.rc08_qxc_outputs = QXC_C_EN_111; + rcd.rc08_qpar_outputs = ENABLED; + rcd.rc08_a17 = ENABLED; + + rcd.rc09_dcs1_ibt = ENABLED; + rcd.rc09_dcs1 = ENABLED; + rcd.rc09_cke_pd_mode = CKE_POWERDOWN_IBT_ON; + rcd.rc09_cke_pd = DISABLED; + + rcd.rc0a_rdimm_speed = RDIMM_SPEED_UP_TO_1600; + rcd.rc0a_context = CONTEXT_1; + + rcd.rc0b_vdd = VDD_1P2V; + rcd.rc0b_vrefca_src = QVREFCA_VDD_HALF_BVREFCA_VDD_HALF; + rcd.rc0b_vrefin_src = RX_VREFIN_SRC_INTERNAL; + + rcd.rc0c_training_mode = NORMAL_MODE; + + rcd.rc0d_cs_mode = DIRECT_DUALCS_MODE; + rcd.rc0d_dimm = LRDIMM; + rcd.rc0d_mrs_mirr = DISABLED; + + rcd.rc0e_parity = DISABLED; + rcd.rc0e_alert_assert = ALERT_N_STICKY; + rcd.rc0e_alert_reenable = ALERT_N_REENABLE_OFF; + + rcd.rc0f_latency_adder = LATENCY_1NCK; + + rcd.rc1x_vrefca_int = VREFCA_INT_50P00; + + rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1241_TO_1260; + + rcd.rc5x_wr_odt_addition = ODT_ADDITION_OFF; + rcd.rc5x_rd_odt_addition = ODT_ADDITION_OFF; + + rcd.rc7x_ca_ibt = IBT_100OHM; + rcd.rc7x_dcs_ibt = IBT_100OHM; + rcd.rc7x_dcke_ibt = IBT_100OHM; + rcd.rc7x_dodt_ibt = IBT_100OHM; + + rcd.rc8x_odt_wr_timing = ODT_WR_TIMING_0CYC; + rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_0CYC; + rcd.rc8x_bodt_outputs = ENABLED; + rcd.rc8x_qodt_ctrl = QODT_CTRL_DODT01; + + rcd.rc9x_wr_qodt0_r0 = QODT_OFF; + rcd.rc9x_wr_qodt1_r0 = QODT_OFF; + rcd.rc9x_wr_qodt0_r1 = QODT_OFF; + rcd.rc9x_wr_qodt1_r1 = QODT_OFF; + rcd.rc9x_wr_qodt0_r2 = QODT_OFF; + rcd.rc9x_wr_qodt1_r2 = QODT_OFF; + rcd.rc9x_wr_qodt0_r3 = QODT_OFF; + rcd.rc9x_wr_qodt1_r3 = QODT_OFF; + + rcd.rcax_rd_qodt0_r0 = QODT_OFF; + rcd.rcax_rd_qodt1_r0 = QODT_OFF; + rcd.rcax_rd_qodt0_r1 = QODT_OFF; + rcd.rcax_rd_qodt1_r1 = QODT_OFF; + rcd.rcax_rd_qodt0_r2 = QODT_OFF; + rcd.rcax_rd_qodt1_r2 = QODT_OFF; + rcd.rcax_rd_qodt0_r3 = QODT_OFF; + rcd.rcax_rd_qodt1_r3 = QODT_OFF; + + rcd.rcbx_dc0_ibt = ENABLED; + rcd.rcbx_dc1_ibt = ENABLED; + rcd.rcbx_dc2_ibt = ENABLED; + rcd.rcbx_ddr4db01_mrs_snoop = ENABLED; + rcd.rcbx_ddr4rcd01_mrs_snoop = ENABLED; + rcd.rcbx_dcke1_ibt = ENABLED; + rcd.rcbx_dcke1 = ENABLED; + + + endtask + + + always @(CK_t or CK_c) + begin + case ({CK_t, CK_c}) + 2'b00: mem_ck_diff = mem_ck_diff; + 2'b01: mem_ck_diff = 1'b0; + 2'b10: mem_ck_diff = 1'b1; + 2'b11: mem_ck_diff = mem_ck_diff; + default: mem_ck_diff = 1'bx; + endcase + end + + + always @(posedge mem_ck_diff) + begin + if ( ({DBG[0], DBA[1:0]} == 3'b111) && ({DCS_n[0], DACT_n, DA[16:14]} == {1'b0, 1'b1, 3'b000}) ) + begin + if ( ((rcd.rc0d_cs_mode == ENCODED_QUADCS_MODE) && (DC[0] == 1'b0)) + || (rcd.rc0d_cs_mode != ENCODED_QUADCS_MODE) ) + begin + $display(" DA[12]=%x DA[11: 8]=%x%x%x%x DA[ 7: 4]=%x%x%x%x DA[ 3: 0]=%x%x%x%x", + DA[12], DA[11], DA[10], DA[9], DA[8], DA[7], + DA[6], DA[5], DA[4], DA[3], DA[2], DA[1], DA[0]); + casex (DA[12:4]) + 9'b0_0000_0000: begin rcd.current_rc <= RC00; update_rc(RC00, DA[7:0]); end + 9'b0_0000_0001: begin rcd.current_rc <= RC01; update_rc(RC01, DA[7:0]); end + 9'b0_0000_0010: begin rcd.current_rc <= RC02; update_rc(RC02, DA[7:0]); end + 9'b0_0000_0011: begin rcd.current_rc <= RC03; update_rc(RC03, DA[7:0]); end + 9'b0_0000_0100: begin rcd.current_rc <= RC04; update_rc(RC04, DA[7:0]); end + 9'b0_0000_0101: begin rcd.current_rc <= RC05; update_rc(RC05, DA[7:0]); end + 9'b0_0000_0110: begin rcd.current_rc <= RC06; update_rc(RC06, DA[7:0]); end + 9'b0_0000_0111: begin rcd.current_rc <= RC07; update_rc(RC07, DA[7:0]); end + 9'b0_0000_1000: begin rcd.current_rc <= RC08; update_rc(RC08, DA[7:0]); end + 9'b0_0000_1001: begin rcd.current_rc <= RC09; update_rc(RC09, DA[7:0]); end + 9'b0_0000_1010: begin rcd.current_rc <= RC0A; update_rc(RC0A, DA[7:0]); end + 9'b0_0000_1011: begin rcd.current_rc <= RC0B; update_rc(RC0B, DA[7:0]); end + 9'b0_0000_1100: begin rcd.current_rc <= RC0C; update_rc(RC0C, DA[7:0]); end + 9'b0_0000_1101: begin rcd.current_rc <= RC0D; update_rc(RC0D, DA[7:0]); end + 9'b0_0000_1110: begin rcd.current_rc <= RC0E; update_rc(RC0E, DA[7:0]); end + 9'b0_0000_1111: begin rcd.current_rc <= RC0F; update_rc(RC0F, DA[7:0]); end + 9'b0_0001_xxxx: begin rcd.current_rc <= RC1X; update_rc(RC1X, DA[7:0]); end + 9'b0_0010_xxxx: begin rcd.current_rc <= RC2X; update_rc(RC2X, DA[7:0]); end + 9'b0_0011_xxxx: begin rcd.current_rc <= RC3X; update_rc(RC3X, DA[7:0]); end + 9'b0_0100_xxxx: begin rcd.current_rc <= RC4X; update_rc(RC4X, DA[7:0]); end + 9'b0_0101_xxxx: begin rcd.current_rc <= RC5X; update_rc(RC5X, DA[7:0]); end + 9'b0_0110_xxxx: begin rcd.current_rc <= RC6X; update_rc(RC6X, DA[7:0]); end + 9'b0_0111_xxxx: begin rcd.current_rc <= RC7X; update_rc(RC7X, DA[7:0]); end + 9'b0_1000_xxxx: begin rcd.current_rc <= RC8X; update_rc(RC8X, DA[7:0]); end + 9'b0_1001_xxxx: begin rcd.current_rc <= RC9X; update_rc(RC9X, DA[7:0]); end + 9'b0_1010_xxxx: begin rcd.current_rc <= RCAX; update_rc(RCAX, DA[7:0]); end + 9'b0_1011_xxxx: begin rcd.current_rc <= RCBX; update_rc(RCBX, DA[7:0]); end + endcase + end + end + end + + + task print_rc(input rcd_enum_t rc); + $display(" RCD Write to %s: %s", rc.name(), rc_string(rc)); + case (rc) + RC00: + begin + $display(" Output Inversion: %s", rcd.rc00_output_inversion.name()); + $display(" Weak Drive: %s", rcd.rc00_weak_drive.name()); + $display(" A-Side Outputs: %s", rcd.rc00_a_outputs.name()); + $display(" B-Side Outputs: %s", rcd.rc00_b_outputs.name()); + end + + RC01: + begin + $display(" Y0_t/Y0_c Clocks: %s", rcd.rc01_y0_clock.name()); + $display(" Y1_t/Y1_c Clocks: %s", rcd.rc01_y1_clock.name()); + $display(" Y2_t/Y2_c Clocks: %s", rcd.rc01_y2_clock.name()); + $display(" Y3_t/Y3_c Clocks: %s", rcd.rc01_y3_clock.name()); + end + + RC02: + begin + $display(" DA17 Input Bus Termination: %s", rcd.rc02_da17_ibt.name()); + $display(" DPAR Input Bus Termination: %s", rcd.rc02_dpar_ibt.name()); + $display(" Transparent Mode: %s", rcd.rc02_transparent_mode.name()); + $display(" Frequency Band Select: %s", rcd.rc02_freqband.name()); + end + + RC03: + begin + $display(" A/C Output Drive: %s", rcd.rc03_qac_drive.name()); + $display(" CSn Output Drive: %s", rcd.rc03_qcs_drive.name()); + end + + RC04: + begin + $display(" ODT Output Drive: %s", rcd.rc04_qodt_drive.name()); + $display(" CKE Output Drive: %s", rcd.rc04_qcke_drive.name()); + end + + RC05: + begin + $display(" CLKA Output Drive: %s", rcd.rc05_clka_drive.name()); + $display(" CLKB Output Drive: %s", rcd.rc05_clkb_drive.name()); + end + + RC06: + begin + end + + RC07: + begin + end + + RC08: + begin + $display(" QxC[2:0] Output Enable: %s", rcd.rc08_qxc_outputs.name()); + $display(" QPAR Output Enable: %s", rcd.rc08_qpar_outputs.name()); + $display(" DA17/QxA17 I/O Enable: %s", rcd.rc08_a17.name()); + end + + RC09: + begin + $display(" DCS1 Input Bus Termination: %s", rcd.rc09_dcs1_ibt.name()); + $display(" DCS1/QxCS1 I/O Enable: %s", rcd.rc09_dcs1.name()); + $display(" CKE Power-Down Mode: %s", rcd.rc09_cke_pd_mode.name()); + $display(" CKE Power-Down Mode Enable: %s", rcd.rc09_cke_pd.name()); + end + + RC0A: + begin + $display(" RDIMM Operating Speed: %s", rcd.rc0a_rdimm_speed.name()); + $display(" Context for operation: %s", rcd.rc0a_context.name()); + end + + RC0B: + begin + $display(" Register VDD Operating Voltage: %s", rcd.rc0b_vdd.name()); + $display(" QVrefCA and BVrefCA Sources: %s", rcd.rc0b_vrefca_src.name()); + $display(" Input Receiver Vref Source: %s", rcd.rc0b_vrefin_src.name()); + end + + RC0C: + begin + $display(" Training Mode Selection: %s", rcd.rc0c_training_mode.name()); + end + + RC0D: + begin + $display(" Chip Select Mode: %s", rcd.rc0d_cs_mode.name()); + $display(" DIMM Type: %s", rcd.rc0d_dimm.name()); + $display(" Address Mirroring for MRS: %s", rcd.rc0d_mrs_mirr.name()); + end + + RC0E: + begin + $display(" Parity Checking: %s", rcd.rc0e_parity.name()); + $display(" ALERT_n Assertion: %s", rcd.rc0e_alert_assert.name()); + $display(" ALERT_n Re-Enable: %s", rcd.rc0e_alert_reenable.name()); + end + + RC0F: + begin + $display(" DRAM Command Latency Addition: %s", rcd.rc0f_latency_adder.name()); + end + + RC1X: + begin + $display(" Internal VrefCA Control Word: %s", rcd.rc1x_vrefca_int.name()); + end + + RC2X: + begin + $display(" Fine Granularity RDIMM Speed: %s", rcd.rc3x_rdimm_fine_speed.name()); + end + + RC3X: + begin + end + + RC4X: + begin + end + + RC5X: + begin + end + + RC6X: + begin + end + + RC7X: + begin + $display(" CA Input Bus Termination: %s", rcd.rc7x_ca_ibt.name()); + $display(" DCSn Input Bus Termination: %s", rcd.rc7x_dcs_ibt.name()); + $display(" DCKE Input Bus Termination: %s", rcd.rc7x_dcke_ibt.name()); + $display(" DODT Input Bus Termination: %s", rcd.rc7x_dodt_ibt.name()); + end + + RC8X: + begin + $display(" QxODT[1:0] Write Timing: %s", rcd.rc8x_odt_wr_timing.name()); + $display(" QxODT[1:0] Read Timing: %s", rcd.rc8x_odt_rd_timing.name()); + $display(" BODT Output Driver: %s", rcd.rc8x_bodt_outputs.name()); + $display(" ODT In/Out/IBT Control: %s", rcd.rc8x_qodt_ctrl.name()); + end + + RC9X: + begin + $display(" QxODT[0] for Rank 0 Write: %s", rcd.rc9x_wr_qodt0_r0.name()); + $display(" QxODT[1] for Rank 0 Write: %s", rcd.rc9x_wr_qodt1_r0.name()); + $display(" QxODT[0] for Rank 1 Write: %s", rcd.rc9x_wr_qodt0_r1.name()); + $display(" QxODT[1] for Rank 1 Write: %s", rcd.rc9x_wr_qodt1_r1.name()); + $display(" QxODT[0] for Rank 2 Write: %s", rcd.rc9x_wr_qodt0_r2.name()); + $display(" QxODT[1] for Rank 2 Write: %s", rcd.rc9x_wr_qodt1_r2.name()); + $display(" QxODT[0] for Rank 3 Write: %s", rcd.rc9x_wr_qodt0_r3.name()); + $display(" QxODT[1] for Rank 3 Write: %s", rcd.rc9x_wr_qodt1_r3.name()); + end + + RCAX: + begin + $display(" QxODT[0] for Rank 0 Read: %s", rcd.rcax_rd_qodt0_r0.name()); + $display(" QxODT[1] for Rank 0 Read: %s", rcd.rcax_rd_qodt1_r0.name()); + $display(" QxODT[0] for Rank 1 Read: %s", rcd.rcax_rd_qodt0_r1.name()); + $display(" QxODT[1] for Rank 1 Read: %s", rcd.rcax_rd_qodt1_r1.name()); + $display(" QxODT[0] for Rank 2 Read: %s", rcd.rcax_rd_qodt0_r2.name()); + $display(" QxODT[1] for Rank 2 Read: %s", rcd.rcax_rd_qodt1_r2.name()); + $display(" QxODT[0] for Rank 3 Read: %s", rcd.rcax_rd_qodt0_r3.name()); + $display(" QxODT[1] for Rank 3 Read: %s", rcd.rcax_rd_qodt1_r3.name()); + end + + RCBX: + begin + $display(" DC0 Input Bus Termination: %s", rcd.rcbx_dc0_ibt.name()); + $display(" DC1 Input Bus Termination: %s", rcd.rcbx_dc1_ibt.name()); + $display(" DC2 Input Bus Termination: %s", rcd.rcbx_dc2_ibt.name()); + $display(" DDR4 DB01 MRS Snooping: %s", rcd.rcbx_ddr4db01_mrs_snoop.name()); + $display(" DDR4 RCD01 MRS Snooping: %s", rcd.rcbx_ddr4rcd01_mrs_snoop.name()); + $display(" DCKE1 Input Bus Termination: %s", rcd.rcbx_dcke1_ibt.name()); + $display(" DKCE1/QxCKE1 Input/Output: %s", rcd.rcbx_dcke1.name()); + end + + default: + begin + $display(" RC Command is unrecognized or not implemented"); + end + endcase + endtask + + task update_rc(input rcd_enum_t rc, input [7:0] da); + case (rc) + RC00: + begin + rcd.rc00_output_inversion = (da[0] == 1'b0) ? ENABLED : DISABLED; + rcd.rc00_weak_drive = (da[1] == 1'b0) ? DISABLED : ENABLED; + rcd.rc00_a_outputs = (da[2] == 1'b0) ? ENABLED : DISABLED; + rcd.rc00_b_outputs = (da[3] == 1'b0) ? ENABLED : DISABLED; + end + + RC01: + begin + rcd.rc01_y0_clock = (da[0] == 1'b0) ? ENABLED : DISABLED; + rcd.rc01_y1_clock = (da[1] == 1'b0) ? ENABLED : DISABLED; + rcd.rc01_y2_clock = (da[2] == 1'b0) ? ENABLED : DISABLED; + rcd.rc01_y3_clock = (da[3] == 1'b0) ? ENABLED : DISABLED; + end + + RC02: + begin + rcd.rc02_da17_ibt = (da[0] == 1'b0) ? ENABLED : DISABLED; + rcd.rc02_dpar_ibt = (da[1] == 1'b0) ? ENABLED : DISABLED; + rcd.rc02_transparent_mode = (da[2] == 1'b0) ? DISABLED : ENABLED; + rcd.rc02_freqband = (da[3] == 1'b0) ? FREQUENCY_BAND_OPERATION : FREQUENCY_BAND_TEST_MODE; + end + + RC03: + begin + case (da[1:0]) + 2'b00: rcd.rc03_qac_drive = DRIVE_LIGHT; + 2'b01: rcd.rc03_qac_drive = DRIVE_MODERATE; + 2'b10: rcd.rc03_qac_drive = DRIVE_STRONG; + 2'b11: rcd.rc03_qac_drive = DRIVE_VERYSTRONG; + endcase + case (da[3:2]) + 2'b00: rcd.rc03_qcs_drive = DRIVE_LIGHT; + 2'b01: rcd.rc03_qcs_drive = DRIVE_MODERATE; + 2'b10: rcd.rc03_qcs_drive = DRIVE_STRONG; + 2'b11: rcd.rc03_qcs_drive = DRIVE_VERYSTRONG; + endcase + end + + RC04: + begin + case (da[1:0]) + 2'b00: rcd.rc04_qodt_drive = DRIVE_LIGHT; + 2'b01: rcd.rc04_qodt_drive = DRIVE_MODERATE; + 2'b10: rcd.rc04_qodt_drive = DRIVE_STRONG; + 2'b11: rcd.rc04_qodt_drive = DRIVE_VERYSTRONG; + endcase + case (da[3:2]) + 2'b00: rcd.rc04_qcke_drive = DRIVE_LIGHT; + 2'b01: rcd.rc04_qcke_drive = DRIVE_MODERATE; + 2'b10: rcd.rc04_qcke_drive = DRIVE_STRONG; + 2'b11: rcd.rc04_qcke_drive = DRIVE_VERYSTRONG; + endcase + end + + RC05: + begin + case (da[1:0]) + 2'b00: rcd.rc05_clka_drive = DRIVE_LIGHT; + 2'b01: rcd.rc05_clka_drive = DRIVE_MODERATE; + 2'b10: rcd.rc05_clka_drive = DRIVE_STRONG; + 2'b11: rcd.rc05_clka_drive = DRIVE_VERYSTRONG; + endcase + case (da[3:2]) + 2'b00: rcd.rc05_clkb_drive = DRIVE_LIGHT; + 2'b01: rcd.rc05_clkb_drive = DRIVE_MODERATE; + 2'b10: rcd.rc05_clkb_drive = DRIVE_STRONG; + 2'b11: rcd.rc05_clkb_drive = DRIVE_VERYSTRONG; + endcase + end + + RC08: + begin + case (da[1:0]) + 2'b00: rcd.rc08_qxc_outputs = QXC_C_EN_111; + 2'b01: rcd.rc08_qxc_outputs = QXC_C_EN_011; + 2'b10: rcd.rc08_qxc_outputs = QXC_C_EN_001; + 2'b11: rcd.rc08_qxc_outputs = QXC_C_EN_000; + endcase + + rcd.rc08_qpar_outputs = (da[2] == 1'b0) ? ENABLED : DISABLED; + rcd.rc08_a17 = (da[3] == 1'b0) ? ENABLED : DISABLED; + end + + RC09: + begin + rcd.rc09_dcs1_ibt = (da[0] == 1'b0) ? ENABLED : DISABLED; + rcd.rc09_dcs1 = (da[1] == 1'b0) ? ENABLED : DISABLED; + rcd.rc09_cke_pd_mode = (da[2] == 1'b0) ? CKE_POWERDOWN_IBT_ON : CKE_POWERDOWN_IBT_OFF; + rcd.rc09_cke_pd = (da[3] == 1'b0) ? DISABLED : ENABLED; + end + + RC0A: + begin + case (da[2:0]) + 3'b000: rcd.rc0a_rdimm_speed = RDIMM_SPEED_UP_TO_1600; + 3'b001: rcd.rc0a_rdimm_speed = RDIMM_SPEED_1601_TO_1867; + 3'b010: rcd.rc0a_rdimm_speed = RDIMM_SPEED_1868_TO_2134; + 3'b011: rcd.rc0a_rdimm_speed = RDIMM_SPEED_2135_TO_2400; + 3'b100: rcd.rc0a_rdimm_speed = RDIMM_SPEED_2401_TO_2667; + 3'b101: rcd.rc0a_rdimm_speed = RDIMM_SPEED_2668_TO_3200; + 3'b110: rcd.rc0a_rdimm_speed = RDIMM_SPEED_RESERVED; + 3'b111: rcd.rc0a_rdimm_speed = RDIMM_SPEED_PLL_BYPASS; + endcase + rcd.rc0a_context = (da[3] == 1'b0) ? CONTEXT_1 : CONTEXT_2; + end + + RC0B: + begin + rcd.rc0b_vdd = (da[0] == 1'b0) ? VDD_1P2V : VDD_RESERVED_LOWER; + case (da[2:1]) + 2'b00: rcd.rc0b_vrefca_src = QVREFCA_VDD_HALF_BVREFCA_VDD_HALF; + 2'b01: rcd.rc0b_vrefca_src = QVREFCA_VREF_INT_BVREFCA_VDD_HALF; + 2'b10: rcd.rc0b_vrefca_src = QVREFCA_VDD_HALF_BVREFCA_VREF_INT; + 2'b11: rcd.rc0b_vrefca_src = QVREFCA_EXTERNAL_BVREFCA_EXTERNAL; + endcase + rcd.rc0b_vrefin_src = (da[3] == 1'b0) ? RX_VREFIN_SRC_INTERNAL : RX_VREFIN_SRC_EXTERNAL; + end + + RC0C: + begin + case (da[2:0]) + 3'b000: rcd.rc0c_training_mode = NORMAL_MODE; + 3'b001: rcd.rc0c_training_mode = CLOCK_TO_CA_TRAINING_MODE; + 3'b010: rcd.rc0c_training_mode = DCS0N_LOOPBACK_MODE; + 3'b011: rcd.rc0c_training_mode = DCS1N_LOOPBACK_MODE; + 3'b100: rcd.rc0c_training_mode = DCKE0_LOOPBACK_MODE; + 3'b101: rcd.rc0c_training_mode = DCKE1_LOOPBACK_MODE; + 3'b110: rcd.rc0c_training_mode = DODT0_LOOPBACK_MODE; + 3'b111: rcd.rc0c_training_mode = DODT1_LOOPBACK_MODE; + endcase + end + + RC0D: + begin + case (da[1:0]) + 2'b00: rcd.rc0d_cs_mode = DIRECT_DUALCS_MODE; + 2'b01: rcd.rc0d_cs_mode = DIRECT_QUADCS_MODE; + 2'b11: rcd.rc0d_cs_mode = ENCODED_QUADCS_MODE; + default: $error("Invalid setting for RC0D CS Mode"); + endcase + rcd.rc0d_dimm = (da[2] == 1'b0) ? LRDIMM : RDIMM; + rcd.rc0d_mrs_mirr = (da[3] == 1'b0) ? DISABLED : ENABLED; + end + + RC0E: + begin + rcd.rc0e_parity = (da[0] == 1'b0) ? DISABLED : ENABLED; + rcd.rc0e_alert_assert = (da[2] == 1'b0) ? ALERT_N_STICKY : ALERT_N_PULSE; + rcd.rc0e_alert_reenable = (da[3] == 1'b0) ? ALERT_N_REENABLE_OFF : ALERT_N_REENABLE_ON; + end + + RC0F: + begin + case (da[2:0]) + 3'b000: rcd.rc0f_latency_adder = LATENCY_1NCK; + 3'b001: rcd.rc0f_latency_adder = LATENCY_2NCK; + 3'b010: rcd.rc0f_latency_adder = LATENCY_3NCK; + 3'b011: rcd.rc0f_latency_adder = LATENCY_4NCK; + 3'b100: rcd.rc0f_latency_adder = LATENCY_0NCK; + default: $error("Reserved setting for RC0F Latency Adder Mode"); + endcase + end + + RC1X: + begin + case (da[7:0]) + 8'b0000_0000: rcd.rc1x_vrefca_int = VREFCA_INT_50P00; + 8'b0000_0001: rcd.rc1x_vrefca_int = VREFCA_INT_50P83; + 8'b0000_0010: rcd.rc1x_vrefca_int = VREFCA_INT_51P67; + 8'b0000_0011: rcd.rc1x_vrefca_int = VREFCA_INT_52P60; + 8'b0000_0100: rcd.rc1x_vrefca_int = VREFCA_INT_53P33; + 8'b0000_0101: rcd.rc1x_vrefca_int = VREFCA_INT_54P17; + 8'b0000_0110: rcd.rc1x_vrefca_int = VREFCA_INT_55P00; + 8'b0000_0111: rcd.rc1x_vrefca_int = VREFCA_INT_55P83; + 8'b0000_1000: rcd.rc1x_vrefca_int = VREFCA_INT_56P67; + 8'b0000_1001: rcd.rc1x_vrefca_int = VREFCA_INT_57P50; + 8'b0000_1010: rcd.rc1x_vrefca_int = VREFCA_INT_58P33; + 8'b0000_1011: rcd.rc1x_vrefca_int = VREFCA_INT_59P17; + 8'b0000_1100: rcd.rc1x_vrefca_int = VREFCA_INT_60P00; + 8'b0000_1101: rcd.rc1x_vrefca_int = VREFCA_INT_60P83; + 8'b0000_1110: rcd.rc1x_vrefca_int = VREFCA_INT_61P67; + 8'b0000_1111: rcd.rc1x_vrefca_int = VREFCA_INT_62P50; + 8'b0001_0000: rcd.rc1x_vrefca_int = VREFCA_INT_63P33; + 8'b0001_0001: rcd.rc1x_vrefca_int = VREFCA_INT_64P17; + 8'b0001_0010: rcd.rc1x_vrefca_int = VREFCA_INT_65P00; + 8'b0001_0011: rcd.rc1x_vrefca_int = VREFCA_INT_65P83; + 8'b0001_0100: rcd.rc1x_vrefca_int = VREFCA_INT_66P67; + + 8'b0010_1100: rcd.rc1x_vrefca_int = VREFCA_INT_33P33; + 8'b0010_1101: rcd.rc1x_vrefca_int = VREFCA_INT_34P17; + 8'b0010_1110: rcd.rc1x_vrefca_int = VREFCA_INT_35P00; + 8'b0010_1111: rcd.rc1x_vrefca_int = VREFCA_INT_35P83; + 8'b0011_0000: rcd.rc1x_vrefca_int = VREFCA_INT_36P67; + 8'b0011_0001: rcd.rc1x_vrefca_int = VREFCA_INT_37P50; + 8'b0011_0010: rcd.rc1x_vrefca_int = VREFCA_INT_38P33; + 8'b0011_0011: rcd.rc1x_vrefca_int = VREFCA_INT_39P17; + 8'b0011_0100: rcd.rc1x_vrefca_int = VREFCA_INT_40P00; + 8'b0011_0101: rcd.rc1x_vrefca_int = VREFCA_INT_40P83; + 8'b0011_0110: rcd.rc1x_vrefca_int = VREFCA_INT_41P67; + 8'b0011_0111: rcd.rc1x_vrefca_int = VREFCA_INT_42P50; + 8'b0011_1000: rcd.rc1x_vrefca_int = VREFCA_INT_43P33; + 8'b0011_1001: rcd.rc1x_vrefca_int = VREFCA_INT_44P17; + 8'b0011_1010: rcd.rc1x_vrefca_int = VREFCA_INT_45P00; + 8'b0011_1011: rcd.rc1x_vrefca_int = VREFCA_INT_45P83; + 8'b0011_1100: rcd.rc1x_vrefca_int = VREFCA_INT_46P67; + 8'b0011_1101: rcd.rc1x_vrefca_int = VREFCA_INT_47P50; + 8'b0011_1110: rcd.rc1x_vrefca_int = VREFCA_INT_48P33; + 8'b0011_1111: rcd.rc1x_vrefca_int = VREFCA_INT_49P17; + + default: $error("Reserved setting for RC1X Internal VrefCA"); + + endcase + end + + RC3X: + begin + case (da[6:0]) + 7'b000_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1241_TO_1260; + 7'b000_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1261_TO_1280; + 7'b000_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1281_TO_1300; + 7'b000_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1301_TO_1320; + 7'b000_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1321_TO_1340; + 7'b000_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1341_TO_1360; + 7'b000_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1361_TO_1380; + 7'b000_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1381_TO_1400; + 7'b000_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1401_TO_1420; + 7'b000_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1421_TO_1440; + 7'b000_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1441_TO_1460; + 7'b000_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1461_TO_1480; + 7'b000_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1481_TO_1500; + 7'b000_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1501_TO_1520; + 7'b000_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1521_TO_1540; + 7'b000_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1541_TO_1560; + 7'b001_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1561_TO_1580; + 7'b001_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1581_TO_1600; + 7'b001_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1601_TO_1620; + 7'b001_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1621_TO_1640; + 7'b001_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1641_TO_1660; + 7'b001_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1661_TO_1680; + 7'b001_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1681_TO_1700; + 7'b001_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1701_TO_1720; + 7'b001_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1721_TO_1740; + 7'b001_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1741_TO_1760; + 7'b001_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1761_TO_1780; + 7'b001_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1781_TO_1800; + 7'b001_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1801_TO_1820; + 7'b001_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1821_TO_1840; + 7'b001_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1841_TO_1860; + 7'b001_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1861_TO_1880; + 7'b010_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1881_TO_1900; + 7'b010_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1901_TO_1920; + 7'b010_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1921_TO_1940; + 7'b010_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1941_TO_1960; + 7'b010_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1961_TO_1980; + 7'b010_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_1981_TO_2000; + 7'b010_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2001_TO_2020; + 7'b010_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2021_TO_2040; + 7'b010_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2041_TO_2060; + 7'b010_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2061_TO_2080; + 7'b010_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2081_TO_2100; + 7'b010_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2101_TO_2120; + 7'b010_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2121_TO_2140; + 7'b010_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2141_TO_2160; + 7'b010_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2161_TO_2180; + 7'b010_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2181_TO_2200; + 7'b011_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2201_TO_2220; + 7'b011_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2221_TO_2240; + 7'b011_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2241_TO_2260; + 7'b011_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2261_TO_2280; + 7'b011_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2281_TO_2300; + 7'b011_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2301_TO_2320; + 7'b011_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2321_TO_2340; + 7'b011_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2341_TO_2360; + 7'b011_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2361_TO_2380; + 7'b011_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2381_TO_2400; + 7'b011_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2401_TO_2420; + 7'b011_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2421_TO_2440; + 7'b011_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2441_TO_2460; + 7'b011_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2461_TO_2480; + 7'b011_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2481_TO_2500; + 7'b011_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2501_TO_2520; + 7'b100_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2521_TO_2540; + 7'b100_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2541_TO_2560; + 7'b100_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2561_TO_2580; + 7'b100_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2581_TO_2600; + 7'b100_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2601_TO_2620; + 7'b100_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2621_TO_2640; + 7'b100_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2641_TO_2660; + 7'b100_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2661_TO_2680; + 7'b100_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2681_TO_2700; + 7'b100_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2701_TO_2720; + 7'b100_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2721_TO_2740; + 7'b100_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2741_TO_2760; + 7'b100_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2761_TO_2780; + 7'b100_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2781_TO_2800; + 7'b100_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2801_TO_2820; + 7'b100_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2821_TO_2840; + 7'b101_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2841_TO_2860; + 7'b101_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2861_TO_2880; + 7'b101_0010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2881_TO_2900; + 7'b101_0011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2901_TO_2920; + 7'b101_0100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2921_TO_2940; + 7'b101_0101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2941_TO_2960; + 7'b101_0110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2961_TO_2980; + 7'b101_0111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_2981_TO_3000; + 7'b101_1000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3001_TO_3020; + 7'b101_1001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3021_TO_3040; + 7'b101_1010: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3041_TO_3060; + 7'b101_1011: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3061_TO_3080; + 7'b101_1100: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3081_TO_3100; + 7'b101_1101: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3101_TO_3120; + 7'b101_1110: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3121_TO_3140; + 7'b101_1111: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3141_TO_3160; + 7'b110_0000: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3161_TO_3180; + 7'b110_0001: rcd.rc3x_rdimm_fine_speed = RDIMM_SPEED_FINE_3181_TO_3200; + default: $error("Reserved setting for RC3X RDIMM Fine Speed"); + endcase + end + + RC5X: + begin + case (da[1:0]) + 2'b00: rcd.rc5x_wr_odt_addition = ODT_ADDITION_OFF; + 2'b01: rcd.rc5x_wr_odt_addition = ODT_ADDITION_1CYC; + 2'b10: rcd.rc5x_wr_odt_addition = ODT_ADDITION_2CYC; + default: $error("Reserved setting for RC5X Write ODT Addition"); + endcase + case (da[3:2]) + 2'b00: rcd.rc5x_rd_odt_addition = ODT_ADDITION_OFF; + 2'b01: rcd.rc5x_rd_odt_addition = ODT_ADDITION_1CYC; + 2'b10: rcd.rc5x_rd_odt_addition = ODT_ADDITION_2CYC; + default: $error("Reserved setting for RC5X Read ODT Addition"); + endcase + end + + RC7X: + begin + case (da[1:0]) + 2'b00: rcd.rc7x_ca_ibt = IBT_100OHM; + 2'b01: rcd.rc7x_ca_ibt = IBT_150OHM; + 2'b10: rcd.rc7x_ca_ibt = IBT_300OHM; + 2'b11: rcd.rc7x_ca_ibt = IBT_OFF; + endcase + case (da[3:2]) + 2'b00: rcd.rc7x_dcs_ibt = IBT_100OHM; + 2'b01: rcd.rc7x_dcs_ibt = IBT_150OHM; + 2'b10: rcd.rc7x_dcs_ibt = IBT_300OHM; + 2'b11: rcd.rc7x_dcs_ibt = IBT_OFF; + endcase + case (da[5:4]) + 2'b00: rcd.rc7x_dcke_ibt = IBT_100OHM; + 2'b01: rcd.rc7x_dcke_ibt = IBT_150OHM; + 2'b10: rcd.rc7x_dcke_ibt = IBT_300OHM; + 2'b11: rcd.rc7x_dcke_ibt = IBT_OFF; + endcase + case (da[7:6]) + 2'b00: rcd.rc7x_dodt_ibt = IBT_100OHM; + 2'b01: rcd.rc7x_dodt_ibt = IBT_150OHM; + 2'b10: rcd.rc7x_dodt_ibt = IBT_300OHM; + 2'b11: rcd.rc7x_dodt_ibt = IBT_OFF; + endcase + end + + RC8X: + begin + rcd.rc8x_odt_wr_timing = (da[0] == 1'b0) ? ODT_WR_TIMING_0CYC : ODT_WR_TIMING_1CYC; + case (da[4:1]) + 4'b0000: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_0CYC; + 4'b0001: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_1CYC; + 4'b0010: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_2CYC; + 4'b0011: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_3CYC; + 4'b0100: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_4CYC; + 4'b0101: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_5CYC; + 4'b0110: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_6CYC; + 4'b0111: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_7CYC; + 4'b1000: rcd.rc8x_odt_rd_timing = ODT_RD_TIMING_8CYC; + default: $error("Reserved setting for RC8X QODT Read Timing"); + endcase + rcd.rc8x_bodt_outputs = (da[5] == 1'b0) ? ENABLED : DISABLED; + case (da[7:6]) + 2'b00: rcd.rc8x_qodt_ctrl = QODT_CTRL_DODT01; + 2'b01: rcd.rc8x_qodt_ctrl = QODT_CTRL_DODT0; + 2'b10: rcd.rc8x_qodt_ctrl = QODT_CTRL_OFF; + 2'b11: rcd.rc8x_qodt_ctrl = QODT_CTRL_INTERNAL; + endcase + end + + RC9X: + begin + rcd.rc9x_wr_qodt0_r0 = (da[0] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt1_r0 = (da[1] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt0_r1 = (da[2] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt1_r1 = (da[3] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt0_r2 = (da[4] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt1_r2 = (da[5] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt0_r3 = (da[6] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rc9x_wr_qodt1_r3 = (da[7] == 1'b0) ? QODT_OFF : QODT_ON; + end + + RCAX: + begin + rcd.rcax_rd_qodt0_r0 = (da[0] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt1_r0 = (da[1] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt0_r1 = (da[2] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt1_r1 = (da[3] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt0_r2 = (da[4] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt1_r2 = (da[5] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt0_r3 = (da[6] == 1'b0) ? QODT_OFF : QODT_ON; + rcd.rcax_rd_qodt1_r3 = (da[7] == 1'b0) ? QODT_OFF : QODT_ON; + end + + RCBX: + begin + rcd.rcbx_dc0_ibt = (da[0] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_dc1_ibt = (da[1] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_dc2_ibt = (da[2] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_ddr4db01_mrs_snoop = (da[3] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_ddr4rcd01_mrs_snoop = (da[4] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_dcke1_ibt = (da[5] == 1'b0) ? ENABLED : DISABLED; + rcd.rcbx_dcke1 = (da[6] == 1'b0) ? ENABLED : DISABLED; + end + + endcase + + print_rc(rc); + endtask + + initial begin + parity_alert_n_pipeline = '1; + expected_parity = 1'b0; + parity_cmp_en = 1'b0; + end + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model.sv new file mode 100644 index 000000000000..f25b661abd80 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model.sv @@ -0,0 +1,290 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// Top-level wrapper of memory model +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_ddrx_model # ( + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter MEM_RANKS_PER_DIMM = 0, + parameter MEM_NUM_OF_DIMMS = 0, + parameter MEM_DM_EN = 0, + parameter MEM_AC_PAR_EN = 0, + + parameter MEM_DISCRETE_CS_WIDTH = 1, + parameter MEM_CHIP_ID_WIDTH = 0, + parameter MEM_ROW_ADDR_WIDTH = 1, + parameter MEM_COL_ADDR_WIDTH = 1, + + parameter MEM_TRTP = 0, + parameter MEM_TRCD = 0, + parameter MEM_DISCRETE_MIRROR_ADDRESSING_EN = 0, + parameter MEM_MIRROR_ADDRESSING_EN = 0, + parameter MEM_INIT_MRS0 = 0, + parameter MEM_INIT_MRS1 = 0, + parameter MEM_INIT_MRS2 = 0, + parameter MEM_INIT_MRS3 = 0, + parameter MEM_CFG_GEN_SBE = 0, + parameter MEM_CFG_GEN_DBE = 0, + parameter MEM_CLK_FREQUENCY = 0, + + parameter MEM_MICRON_AUTOMATA = 0, + + // Definition of port widths for "mem" interface + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1 +) ( + // Ports for "mem" interface + input logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + input logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + input logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + input logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + input logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + input logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + input logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + input logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + input logic [PORT_MEM_K_WIDTH-1:0] mem_k, + input logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + input logic [PORT_MEM_A_WIDTH-1:0] mem_a, + input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + input logic [PORT_MEM_C_WIDTH-1:0] mem_c, + input logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + input logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + input logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + input logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + input logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + input logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + input logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + input logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + input logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + input logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + input logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + input logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + input logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + input logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + input logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + input logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + input logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + input logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + input logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + input logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + input logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + input logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + input logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + input logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + input logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + input logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + output logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + output logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + output logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + output logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + output logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + output logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + output logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + output logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + output logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n +); + timeunit 1ps; + timeprecision 1ps; + + // The first level of the memory model (i.e. this module) acts as a bus + // "splitter" for ping-pong PHY configuration. In ping-pong mode, the + // memory bus consists of signals for two logically-independent + // interfaces. The two interfaces however share the same physical + // address/command bus through time-multiplexing. Certain signals, including + // CS#/ODT/CKE/CK/CK# and the data signals, are not shared by the two + // interfaces. This module is responsible for instantiating two underlying + // memory models corresponding to the two logically-independent memory + // interfaces, feeding shared signals to both models, and splitting the + // non-shared signals before feeding them to each model. + // + // In non-ping-pong configuration, only one underlying model is + // instantiated and this module is a pass-through. + //(JCHOI) + localparam NUM_OF_IFS = (PHY_PING_PONG_EN ? 2 : 1); + + // Calculate width of non-shared signals after splitting + localparam PORT_MEM_CKE_WIDTH_PER_IF = PORT_MEM_CKE_WIDTH / NUM_OF_IFS; + localparam PORT_MEM_CS_N_WIDTH_PER_IF = PORT_MEM_CS_N_WIDTH / NUM_OF_IFS; + localparam PORT_MEM_ODT_WIDTH_PER_IF = PORT_MEM_ODT_WIDTH / NUM_OF_IFS; + localparam PORT_MEM_CK_WIDTH_PER_IF = PORT_MEM_CK_WIDTH; + localparam PORT_MEM_CK_N_WIDTH_PER_IF = PORT_MEM_CK_N_WIDTH; + localparam PORT_MEM_DQ_WIDTH_PER_IF = PORT_MEM_DQ_WIDTH / NUM_OF_IFS; + localparam PORT_MEM_DQS_WIDTH_PER_IF = PORT_MEM_DQS_WIDTH / NUM_OF_IFS; + localparam PORT_MEM_DQS_N_WIDTH_PER_IF = PORT_MEM_DQS_N_WIDTH / NUM_OF_IFS; + + // DBI#/DM are optional pins. If they're unused, we still generate a fake signal of width 1 to avoid + // index range issue when declaring/selecting signals. Note that mem_dm is a DDR3-only issue and + // mem_dbi_n is a DDR4-only signal. + localparam PORT_MEM_DM_WIDTH_PER_IF = (PORT_MEM_DM_WIDTH == 1 && NUM_OF_IFS == 2) ? 1 : (PORT_MEM_DM_WIDTH / NUM_OF_IFS); + localparam PORT_MEM_DBI_N_WIDTH_PER_IF = (PORT_MEM_DBI_N_WIDTH == 1 && NUM_OF_IFS == 2) ? 1 : (PORT_MEM_DBI_N_WIDTH / NUM_OF_IFS); + + // Multiple alert# pins are meant to be daisy-chained on the board + // to obtain a single logically-AND'ed version of alert# before + // passing upward. + logic [NUM_OF_IFS-1:0] alert_n; + assign mem_alert_n = &alert_n; + + generate + genvar inst_i; + + for (inst_i = 0; inst_i < NUM_OF_IFS; ++inst_i) + begin : pp_gen + altera_emif_ddrx_model_per_ping_pong # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .MEM_DISCRETE_CS_WIDTH (MEM_DISCRETE_CS_WIDTH), + .MEM_CHIP_ID_WIDTH (MEM_CHIP_ID_WIDTH), + .MEM_RANKS_PER_DIMM (MEM_RANKS_PER_DIMM), + .MEM_NUM_OF_DIMMS (MEM_NUM_OF_DIMMS), + .MEM_AC_PAR_EN (MEM_AC_PAR_EN), + .MEM_DM_EN (MEM_DM_EN), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH_PER_IF), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH_PER_IF), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH_PER_IF), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH_PER_IF), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH_PER_IF), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH_PER_IF), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH_PER_IF), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH_PER_IF), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH_PER_IF), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH / NUM_OF_IFS), + .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH), + .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH), + .MEM_TRTP (MEM_TRTP), + .MEM_TRCD (MEM_TRCD), + .MEM_INIT_MRS0 (MEM_INIT_MRS0), + .MEM_INIT_MRS1 (MEM_INIT_MRS1), + .MEM_INIT_MRS2 (MEM_INIT_MRS2), + .MEM_INIT_MRS3 (MEM_INIT_MRS3), + .MEM_MIRROR_ADDRESSING_EN (MEM_FORMAT_ENUM == "MEM_FORMAT_DISCRETE" ? MEM_DISCRETE_MIRROR_ADDRESSING_EN : MEM_MIRROR_ADDRESSING_EN), + .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE), + .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE), + .MEM_CLK_FREQUENCY (MEM_CLK_FREQUENCY), + .MEM_MICRON_AUTOMATA (MEM_MICRON_AUTOMATA) + ) inst ( + .mem_cs_n (mem_cs_n [ (PORT_MEM_CS_N_WIDTH_PER_IF * inst_i) +: PORT_MEM_CS_N_WIDTH_PER_IF]), + .mem_cke (mem_cke [ (PORT_MEM_CKE_WIDTH_PER_IF * inst_i) +: PORT_MEM_CKE_WIDTH_PER_IF]), + .mem_odt (mem_odt [ (PORT_MEM_ODT_WIDTH_PER_IF * inst_i) +: PORT_MEM_ODT_WIDTH_PER_IF]), + .mem_dq (mem_dq [ (PORT_MEM_DQ_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQ_WIDTH_PER_IF]), + .mem_dqs (mem_dqs [ (PORT_MEM_DQS_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQS_WIDTH_PER_IF]), + .mem_dqs_n (mem_dqs_n[ (PORT_MEM_DQS_N_WIDTH_PER_IF * inst_i) +: PORT_MEM_DQS_N_WIDTH_PER_IF]), + .mem_dm (mem_dm [ (PORT_MEM_DM_WIDTH_PER_IF * ((PORT_MEM_DM_WIDTH == 1 && NUM_OF_IFS == 2) ? 0 : inst_i)) +: PORT_MEM_DM_WIDTH_PER_IF]), + .mem_dbi_n (mem_dbi_n[ (PORT_MEM_DBI_N_WIDTH_PER_IF * ((PORT_MEM_DBI_N_WIDTH == 1 && NUM_OF_IFS == 2) ? 0 : inst_i)) +: PORT_MEM_DBI_N_WIDTH_PER_IF]), + .mem_alert_n (alert_n [inst_i]), + .mem_rm (mem_rm), + .* + ); + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_bidir_delay.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_bidir_delay.sv new file mode 100644 index 000000000000..227a63ee819b --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_bidir_delay.sv @@ -0,0 +1,61 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_ddrx_model_bidir_delay +#( + parameter DELAY = 2.0 +) ( + inout porta, + inout portb +); + timeunit 1ps; + timeprecision 1ps; + + reg porta_dly; + reg portb_dly; + + initial begin + porta_dly = 1'bz; + portb_dly = 1'bz; + end + + always @(porta) begin + if (portb_dly === 1'bz || porta === 1'bz) begin + porta_dly <= #DELAY porta; + end + end + + always @(portb) begin + if (porta_dly === 1'bz || portb === 1'bz) begin + portb_dly <= #DELAY portb; + end + end + + assign porta = portb_dly; + assign portb = porta_dly; +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_device.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_device.sv new file mode 100644 index 000000000000..ad4dff657d31 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_device.sv @@ -0,0 +1,541 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// memory model per device in a given depth expansion +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_ddrx_model_per_device + # ( + + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter MEM_RANKS_PER_DIMM = 0, + parameter MEM_NUM_OF_DIMMS = 0, + parameter MEM_AC_PAR_EN = 0, + parameter MEM_DM_EN = 0, + + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + + parameter MEM_CHIP_ID_WIDTH = 0, + parameter MEM_ROW_ADDR_WIDTH = 1, + parameter MEM_COL_ADDR_WIDTH = 1, + parameter MEM_TRTP = 0, + parameter MEM_TRCD = 0, + parameter MEM_INIT_MRS0 = 0, + parameter MEM_INIT_MRS1 = 0, + parameter MEM_INIT_MRS2 = 0, + parameter MEM_INIT_MRS3 = 0, + parameter MEM_MIRROR_ADDRESSING_EN = 0, + parameter MEM_DEPTH_IDX = -1, + parameter MEM_CFG_GEN_SBE = 0, + parameter MEM_CFG_GEN_DBE = 0, + parameter MEM_CLK_FREQUENCY = 0, + parameter MEM_MICRON_AUTOMATA = 0 + ) ( + + input logic [PORT_MEM_A_WIDTH-1:0] mem_a, + input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + input logic [PORT_MEM_C_WIDTH-1:0] mem_c, + input logic mem_ck, + input logic mem_ck_n, + input logic [PORT_MEM_CKE_WIDTH - 1:0] mem_cke, + input logic [PORT_MEM_CS_N_WIDTH - 1:0] mem_cs_n, + input logic [PORT_MEM_RAS_N_WIDTH - 1:0] mem_ras_n, + input logic [PORT_MEM_CAS_N_WIDTH - 1:0] mem_cas_n, + input logic [PORT_MEM_WE_N_WIDTH - 1:0] mem_we_n, + input logic [PORT_MEM_ACT_N_WIDTH - 1:0] mem_act_n, + input logic [PORT_MEM_RESET_N_WIDTH - 1:0] mem_reset_n, + input logic [PORT_MEM_DM_WIDTH - 1:0] mem_dm, + inout tri [PORT_MEM_DBI_N_WIDTH - 1:0] mem_dbi_n, + inout tri [PORT_MEM_DQ_WIDTH - 1:0] mem_dq, + inout tri [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH - 1:0] mem_dqs_n, + output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + input logic mem_odt, + input logic [PORT_MEM_RM_WIDTH-1:0] mem_rm + + ); + timeunit 1ps; + timeprecision 1ps; + + localparam MEM_NUMBER_OF_RANKS = (MEM_FORMAT_ENUM == "MEM_FORMAT_DISCRETE" ? PORT_MEM_CS_N_WIDTH : MEM_RANKS_PER_DIMM); + + reg [PORT_MEM_A_WIDTH-1:0] a; + reg [PORT_MEM_BA_WIDTH-1:0] ba; + reg [PORT_MEM_BG_WIDTH-1:0] bg; + reg [PORT_MEM_C_WIDTH-1:0] c; + reg ck; + reg ck_n; + reg cke; + reg [MEM_NUMBER_OF_RANKS-1:0] cs_n; + reg ras_n; + reg cas_n; + reg we_n; + reg act_n; + reg [PORT_MEM_RESET_N_WIDTH-1:0] reset_n; + reg odt; + reg [MEM_NUMBER_OF_RANKS-1:0] alert_n; + reg [PORT_MEM_PAR_WIDTH-1:0] par; + reg single_bit_alert_n; + reg [PORT_MEM_DM_WIDTH-1:0] dm; + + wire [PORT_MEM_DQ_WIDTH-1:0] dq; + wire [PORT_MEM_DQS_WIDTH-1:0] dqs; + wire [PORT_MEM_DQS_N_WIDTH-1:0] dqs_n; + + reg [7:0] ddr3_lrdimm_qcs_n; + + reg bcom_ck; + reg bcom_ck_n; + reg [3:0] bcom_bus; + reg bcom_odt; + reg bcom_cke; + wire bcom_vref; + + generate + always @(*) begin + if (MEM_DM_EN != 0) begin + if ((PROTOCOL_ENUM != "PROTOCOL_DDR4") && (PORT_MEM_DM_WIDTH != PORT_MEM_DQS_WIDTH) || + (PROTOCOL_ENUM == "PROTOCOL_DDR4") && (PORT_MEM_DBI_N_WIDTH != PORT_MEM_DQS_WIDTH)) begin + $display("Memory model DM width must equal DQS width."); + $finish; + end + end + else begin + dm <= #10 {PORT_MEM_DM_WIDTH{1'b0}}; + end + end + endgenerate + + + generate + reg my_parity; + reg [4:0] err_out_shiftreg = 5'b11111; + if (MEM_AC_PAR_EN) begin + always @(posedge mem_ck) begin + if (mem_cke) begin + my_parity <= ^{mem_a, mem_ba, mem_ras_n, mem_cas_n, mem_we_n}; + err_out_shiftreg[4:1] <= err_out_shiftreg[3:0]; + if (cs_n != {PORT_MEM_CS_N_WIDTH{1'b1}}) begin + err_out_shiftreg[1:0] <= {2{my_parity == mem_par}}; + end else begin + err_out_shiftreg[0] <= 1'b1; + end + end + end + end + assign single_bit_alert_n = (PROTOCOL_ENUM == "PROTOCOL_DDR4" ? &alert_n : err_out_shiftreg[4]); + endgenerate + + + generate + if ((MEM_FORMAT_ENUM == "MEM_FORMAT_UDIMM") || (MEM_FORMAT_ENUM == "MEM_FORMAT_DISCRETE") || (MEM_FORMAT_ENUM == "MEM_FORMAT_SODIMM")) begin + always @(*) begin + a <= mem_a; + ba <= mem_ba; + bg <= mem_bg; + c <= mem_c; + ck <= mem_ck; + ck_n <= mem_ck_n; + cke <= mem_cke; + cs_n <= mem_cs_n; + ras_n <= mem_ras_n; + cas_n <= mem_cas_n; + we_n <= mem_we_n; + act_n <= mem_act_n; + reset_n <= mem_reset_n; + odt <= mem_odt; + par <= mem_par; + mem_alert_n <= single_bit_alert_n; + end + end + endgenerate + + + generate + genvar i; + + if ((PROTOCOL_ENUM == "PROTOCOL_DDR4") && (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM")) begin : gen_ddr4_rcd_chip + + always @(*) begin + ras_n <= a[16]; + cas_n <= a[15]; + we_n <= a[14]; + end + + altera_emif_ddr4_model_rcd_chip #( + .ADDRESS_MIRRORING (MEM_MIRROR_ADDRESSING_EN), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH) + ) ddr4_rcd_chip ( + .DCKE (mem_cke), + .DODT (mem_odt), + .DCS_n (mem_cs_n), + .DC (mem_c), + + .DA (mem_a), + .DBA (mem_ba), + .DBG (mem_bg), + .DACT_n (mem_act_n), + + .CK_t (mem_ck), + .CK_c (mem_ck_n), + + .DRST_n (mem_reset_n), + + .DPAR (mem_par), + + .ERROR_IN_n (single_bit_alert_n), + + .BODT (bcom_odt), + .BCKE (bcom_cke), + .BCOM (bcom_bus), + .BCK_t (bcom_ck), + .BCK_c (bcom_ck_n), + .BVrefCA (bcom_vref), + + .QACKE (cke), + .QBCKE (), + .QAODT (odt), + .QBODT (), + .QACS_n (cs_n), + .QBCS_n (), + .QAC (c), + .QBC (), + + .QAA (a), + .QBA (), + .QABA (ba), + .QABG (bg), + .QBBA (), + .QBBG (), + .QAACT_n (act_n), + .QBACT_n (), + + .Y_t (ck), + .Y_c (ck_n), + + .QRST_n (reset_n), + + .QAPAR (par), + .QBPAR (), + + .ALERT_n (mem_alert_n), + + .SDA (), + .SA (), + .SCL (), + .BFUNC (), + .VDDSPD (), + + .VDD (1'b1), + .VSS (1'b0), + .AVDD (1'b1), + .PVDD (1'b1), + .PVSS (1'b0) + ); + end + + if ((PROTOCOL_ENUM == "PROTOCOL_DDR3") && (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM")) begin : gen_ddr3_rdimm_chip + always @(*) begin + reset_n <= mem_reset_n; + end + + altera_emif_ddr3_model_rdimm_chip #( + .MEM_DEPTH_IDX (MEM_DEPTH_IDX), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH) + ) rdimm_chip_i ( + .DCKE (mem_cke), + .DODT (mem_odt), + .DCS_n (mem_cs_n), + + .DA (mem_a), + .DBA (mem_ba), + .DRAS_n (mem_ras_n), + .DCAS_n (mem_cas_n), + .DWE_n (mem_we_n), + + .CK (mem_ck), + .CK_n (mem_ck_n), + + .DRESET_n (mem_reset_n), + + .PAR_IN (mem_par), + + .QCKE (cke), + .QODT (odt), + .QCS_n (cs_n), + + .QA (a), + .QBA (ba), + .QRAS_n (ras_n), + .QCAS_n (cas_n), + .QWE_n (we_n), + + .Y (ck), + .Y_n (ck_n), + + .ERROUT_n (mem_alert_n) + ); + end + + if ((PROTOCOL_ENUM == "PROTOCOL_DDR4") && (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM")) begin : gen_ddr4_lrdimm_buffer + for (i = 0; i < PORT_MEM_DQS_WIDTH/2; i = i + 1) begin : gen_ddr4_db_chip + altera_emif_ddr4_model_db_chip ddr4_db_chip ( + .BCK_t (bcom_ck), + .BCK_c (bcom_ck_n), + .BCKE (bcom_cke), + .BODT (bcom_odt), + .BVrefCA (bcom_vref), + .BCOM (bcom_bus), + + .MDQ ( dq[i*8+7:i*8]), + .MDQS0_t ( dqs[i*2]), + .MDQS0_c ( dqs_n[i*2]), + .MDQS1_t ( dqs[i*2+1]), + .MDQS1_c ( dqs_n[i*2+1]), + + .DQ ( mem_dq[i*8+7:i*8]), + .DQS0_t ( mem_dqs[i*2]), + .DQS0_c (mem_dqs_n[i*2]), + .DQS1_t ( mem_dqs[i*2+1]), + .DQS1_c (mem_dqs_n[i*2+1]), + + .ALERT_n (), + + .VDD (1'b1), + .VSS (1'b0) + ); + end + end + + if ((PROTOCOL_ENUM == "PROTOCOL_DDR3") && (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM")) begin : gen_ddr3_lrdimm_chip + always @(*) begin + cs_n <= ddr3_lrdimm_qcs_n; + end + + altera_emif_ddr3_model_lrdimm_chip #( + .MEM_DEPTH_IDX (MEM_DEPTH_IDX), + .MEM_WIDTH_IDX (0), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .MEM_CLK_FREQUENCY (MEM_CLK_FREQUENCY) + ) lrdimm_chip_i ( + .DQ (mem_dq), + .DQS_p (mem_dqs), + .DQS_n (mem_dqs_n), + .DA (mem_a), + .DBA (mem_ba), + .DRAS_n (mem_ras_n), + .DCAS_n (mem_cas_n), + .DWE_n (mem_we_n), + .DCS_n ({{(8-PORT_MEM_CS_N_WIDTH-PORT_MEM_RM_WIDTH){1'b1}}, mem_rm, mem_cs_n}), + .DCKE (mem_cke), + .DODT (mem_odt), + .CLK_p (mem_ck), + .CLK_n (mem_ck_n), + .PAR_IN (mem_par), + .ERR_n (mem_alert_n), + + .MDQ (dq), + .MDQS_p (dqs), + .MDQS_n (dqs_n), + .Y_p (ck), + .Y_n (ck_n), + + .QAA (a), + .QABA (ba), + .QARAS_n (ras_n), + .QACAS_n (cas_n), + .QAWE_n (we_n), + .QACS_n (ddr3_lrdimm_qcs_n[3:0]), + .QACKE (cke), + .QAODT (odt), + + .QBA (), + .QBBA (), + .QBRAS_n (), + .QBCAS_n (), + .QBWE_n (), + .QBCS_n (ddr3_lrdimm_qcs_n[7:4]), + .QBCKE (), + .QBODT (), + + .RESET_n (mem_reset_n), + .QRST_n (reset_n) + ); + end + endgenerate + + + generate + if (MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM") begin : gen_lrdimm_rank + genvar rank; + for (rank = 0; rank < MEM_NUMBER_OF_RANKS; rank = rank + 1) begin : rank_gen_lrdimm + altera_emif_ddrx_model_rank #( + + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .MEM_CHIP_ID_WIDTH (MEM_CHIP_ID_WIDTH), + .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH), + .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + + .MEM_DM_EN (MEM_DM_EN), + .MEM_TRTP (MEM_TRTP), + .MEM_TRCD (MEM_TRCD), + .MEM_INIT_MRS0 (MEM_INIT_MRS0), + .MEM_INIT_MRS1 (MEM_INIT_MRS1), + .MEM_INIT_MRS2 (MEM_INIT_MRS2), + .MEM_INIT_MRS3 (MEM_INIT_MRS3), + .MEM_MIRROR_ADDRESSING (MEM_MIRROR_ADDRESSING_EN & (rank & 1'b1)), + .MEM_DEPTH_IDX (MEM_DEPTH_IDX), + .MEM_RANK_IDX (rank), + .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE), + .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE), + .MEM_MICRON_AUTOMATA (MEM_MICRON_AUTOMATA) + + ) rank_inst ( + + .mem_a (a), + .mem_ba (ba), + .mem_bg (bg), + .mem_c (c), + .mem_ck (ck), + .mem_ck_n (ck_n), + .mem_cke (cke), + .mem_ras_n (ras_n), + .mem_cas_n (cas_n), + .mem_we_n (we_n), + .mem_act_n (act_n), + .mem_reset_n (reset_n), + .mem_dm (mem_dm), + .mem_dbi_n (mem_dbi_n), + .mem_dq (dq), + .mem_dqs (dqs), + .mem_dqs_n (dqs_n), + .mem_odt (odt), + .mem_cs_n (cs_n[rank]), + .mem_alert_n (alert_n[rank]), + .mem_par (par) + + ); + end + end + else begin : gen_mem_rank + genvar rank; + for (rank = 0; rank < MEM_NUMBER_OF_RANKS; rank = rank + 1) begin : rank_gen + altera_emif_ddrx_model_rank #( + + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .MEM_CHIP_ID_WIDTH (MEM_CHIP_ID_WIDTH), + .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH), + .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + + .MEM_DM_EN (MEM_DM_EN), + .MEM_TRTP (MEM_TRTP), + .MEM_TRCD (MEM_TRCD), + .MEM_INIT_MRS0 (MEM_INIT_MRS0), + .MEM_INIT_MRS1 (MEM_INIT_MRS1), + .MEM_INIT_MRS2 (MEM_INIT_MRS2), + .MEM_INIT_MRS3 (MEM_INIT_MRS3), + .MEM_MIRROR_ADDRESSING (MEM_MIRROR_ADDRESSING_EN & (rank & 1'b1)), + .MEM_DEPTH_IDX (MEM_DEPTH_IDX), + .MEM_RANK_IDX (rank), + .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE), + .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE), + .MEM_MICRON_AUTOMATA (MEM_MICRON_AUTOMATA) + + ) rank_inst ( + + .mem_a (a), + .mem_ba (ba), + .mem_bg (bg), + .mem_c (c), + .mem_ck (ck), + .mem_ck_n (ck_n), + .mem_cke (cke), + .mem_ras_n (ras_n), + .mem_cas_n (cas_n), + .mem_we_n (we_n), + .mem_act_n (act_n), + .mem_reset_n (reset_n), + .mem_dm (mem_dm), + .mem_dbi_n (mem_dbi_n), + .mem_dq (mem_dq), + .mem_dqs (mem_dqs), + .mem_dqs_n (mem_dqs_n), + .mem_odt (odt), + .mem_cs_n (cs_n[rank]), + .mem_alert_n (alert_n[rank]), + .mem_par (par) + + ); + end + end + endgenerate + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_ping_pong.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_ping_pong.sv new file mode 100644 index 000000000000..d7e78854df19 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_per_ping_pong.sv @@ -0,0 +1,211 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +/////////////////////////////////////////////////////////////////////////////// +// Memory model representing either the "ping" or the "pong" side of +// the memory device for ping-pong topology. For non-ping-pong topology +// this is simply the top-level wrapper of the memory model. +// +/////////////////////////////////////////////////////////////////////////////// +module altera_emif_ddrx_model_per_ping_pong # +( + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter MEM_DISCRETE_CS_WIDTH = 1, + parameter MEM_CHIP_ID_WIDTH = 0, + parameter MEM_RANKS_PER_DIMM = 0, + parameter MEM_NUM_OF_DIMMS = 0, + parameter MEM_AC_PAR_EN = 0, + parameter MEM_DM_EN = 0, + + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + + parameter MEM_ROW_ADDR_WIDTH = 1, + parameter MEM_COL_ADDR_WIDTH = 1, + parameter MEM_TRTP = 0, + parameter MEM_TRCD = 0, + parameter MEM_INIT_MRS0 = 0, + parameter MEM_INIT_MRS1 = 0, + parameter MEM_INIT_MRS2 = 0, + parameter MEM_INIT_MRS3 = 0, + parameter MEM_MIRROR_ADDRESSING_EN = 0, + parameter MEM_CFG_GEN_SBE = 0, + parameter MEM_CFG_GEN_DBE = 0, + parameter MEM_CLK_FREQUENCY = 0, + parameter MEM_MICRON_AUTOMATA = 0 +) ( + input logic [PORT_MEM_A_WIDTH-1:0] mem_a, + input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + input logic [PORT_MEM_C_WIDTH-1:0] mem_c, + input logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + input logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + input logic [PORT_MEM_CKE_WIDTH - 1:0] mem_cke, + input logic [PORT_MEM_CS_N_WIDTH - 1:0] mem_cs_n, + input logic [PORT_MEM_RAS_N_WIDTH - 1:0] mem_ras_n, + input logic [PORT_MEM_CAS_N_WIDTH - 1:0] mem_cas_n, + input logic [PORT_MEM_WE_N_WIDTH - 1:0] mem_we_n, + input logic [PORT_MEM_ACT_N_WIDTH - 1:0] mem_act_n, + input logic [PORT_MEM_RESET_N_WIDTH - 1:0] mem_reset_n, + input logic [PORT_MEM_DM_WIDTH - 1:0] mem_dm, + inout tri [PORT_MEM_DBI_N_WIDTH - 1:0] mem_dbi_n, + inout tri [PORT_MEM_DQ_WIDTH - 1:0] mem_dq, + inout tri [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH - 1:0] mem_dqs_n, + output logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + input logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + input logic [PORT_MEM_RM_WIDTH-1:0] mem_rm +); + timeunit 1ps; + timeprecision 1ps; + + localparam MEM_MODEL_DEVICE_DEPTH = (MEM_FORMAT_ENUM == "MEM_FORMAT_RDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_LRDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_UDIMM" || MEM_FORMAT_ENUM == "MEM_FORMAT_SODIMM" ) ? MEM_NUM_OF_DIMMS : 1 ; + + wire logic [MEM_MODEL_DEVICE_DEPTH - 1:0] alert_n; + assign mem_alert_n = &alert_n; + + /* DDR4 Shared Address/Command Bus: {RAS_n, CAS_n, WE_n} = A[16:14] + Interpret as RAS/CAS/WE when ACT_n = 1 + Interpret as A[16:14] when ACT_n = 0 + If DDR4, there should be no RAS/CAS/WE coming in. We copy A[16:14] to those signals here. */ + logic [PORT_MEM_RAS_N_WIDTH-1:0] int_mem_ras_n; + logic [PORT_MEM_CAS_N_WIDTH-1:0] int_mem_cas_n; + logic [PORT_MEM_WE_N_WIDTH-1:0] int_mem_we_n; + initial begin + assert(!(PROTOCOL_ENUM == "PROTOCOL_DDR4" && PORT_MEM_A_WIDTH < 17)) else $error("mem_a width must be at least 17 for DDR4"); + end + + generate + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + always_comb begin + int_mem_ras_n <= {PORT_MEM_RAS_N_WIDTH{mem_a[16]}}; + int_mem_cas_n <= {PORT_MEM_CAS_N_WIDTH{mem_a[15]}}; + int_mem_we_n <= {PORT_MEM_WE_N_WIDTH{mem_a[14]}}; + end + end else begin + always_comb begin + int_mem_ras_n <= mem_ras_n; + int_mem_cas_n <= mem_cas_n; + int_mem_we_n <= mem_we_n; + end + end + endgenerate + + generate + genvar depth; + for (depth = 0; depth < MEM_MODEL_DEVICE_DEPTH; ++depth) begin : depth_gen + + altera_emif_ddrx_model_per_device #( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH / MEM_MODEL_DEVICE_DEPTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .MEM_CHIP_ID_WIDTH (MEM_CHIP_ID_WIDTH), + .MEM_ROW_ADDR_WIDTH (MEM_ROW_ADDR_WIDTH), + .MEM_COL_ADDR_WIDTH (MEM_COL_ADDR_WIDTH), + .MEM_TRTP (MEM_TRTP), + .MEM_TRCD (MEM_TRCD), + .MEM_INIT_MRS0 (MEM_INIT_MRS0), + .MEM_INIT_MRS1 (MEM_INIT_MRS1), + .MEM_INIT_MRS2 (MEM_INIT_MRS2), + .MEM_INIT_MRS3 (MEM_INIT_MRS3), + .MEM_DEPTH_IDX (depth), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .MEM_RANKS_PER_DIMM (MEM_RANKS_PER_DIMM), + .MEM_DM_EN (MEM_DM_EN), + .MEM_MIRROR_ADDRESSING_EN (MEM_MIRROR_ADDRESSING_EN), + .MEM_AC_PAR_EN (MEM_AC_PAR_EN), + .MEM_CFG_GEN_SBE (MEM_CFG_GEN_SBE), + .MEM_CFG_GEN_DBE (MEM_CFG_GEN_DBE), + .MEM_CLK_FREQUENCY (MEM_CLK_FREQUENCY), + .MEM_MICRON_AUTOMATA (MEM_MICRON_AUTOMATA) + ) mem_inst ( + .mem_a (mem_a), + .mem_ba (mem_ba), + .mem_bg (mem_bg), + .mem_c (mem_c), + .mem_ck (mem_ck[0]), + .mem_ck_n (mem_ck_n[0]), + .mem_cke (mem_cke), + .mem_cs_n (mem_cs_n[PORT_MEM_CS_N_WIDTH/MEM_MODEL_DEVICE_DEPTH*(depth+1)-1:PORT_MEM_CS_N_WIDTH/MEM_MODEL_DEVICE_DEPTH*depth]), + .mem_ras_n (int_mem_ras_n), + .mem_cas_n (int_mem_cas_n), + .mem_we_n (int_mem_we_n), + .mem_act_n (mem_act_n), + .mem_reset_n (mem_reset_n), + .mem_dm (mem_dm), + .mem_dbi_n (mem_dbi_n), + .mem_dq (mem_dq), + .mem_dqs (mem_dqs), + .mem_dqs_n (mem_dqs_n), + .mem_par (mem_par), + .mem_alert_n (alert_n[depth]), + .mem_odt (mem_odt[0]), + .mem_rm (mem_rm) + ); + end + endgenerate +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_rank.sv b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_rank.sv new file mode 100644 index 000000000000..3ab14a48949f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_emif_ddrx_model_rank.sv @@ -0,0 +1,2073 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module altera_emif_ddrx_model_rank + # ( + parameter PROTOCOL_ENUM = "", + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter MEM_CHIP_ID_WIDTH = 0, + parameter MEM_ROW_ADDR_WIDTH = 1, + parameter MEM_COL_ADDR_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter MEM_DM_EN = 0, + parameter MEM_PAR_ALERT_PW = 48, + parameter MEM_TRTP = 0, + parameter MEM_TRCD = 0, + parameter MEM_DQS_TO_CLK_CAPTURE_DELAY = 100, + parameter MEM_CLK_TO_DQS_CAPTURE_DELAY = 100000, + parameter MEM_MIRROR_ADDRESSING = 0, + parameter MEM_DEPTH_IDX = -1, + parameter MEM_WIDTH_IDX = 0, + parameter MEM_RANK_IDX = -1, + parameter MEM_VERBOSE = 1, + parameter MEM_GUARANTEED_WRITE_INIT = 0, + parameter REFRESH_BURST_VALIDATION = 0, + parameter MEM_INIT_MRS0 = 0, + parameter MEM_INIT_MRS1 = 0, + parameter MEM_INIT_MRS2 = 0, + parameter MEM_INIT_MRS3 = 0, + parameter MEM_CFG_GEN_SBE = 0, + parameter MEM_CFG_GEN_DBE = 0, + parameter MEM_MICRON_AUTOMATA = 0 + ) ( + + input logic [PORT_MEM_A_WIDTH-1:0] mem_a, + input logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + input logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + input logic [PORT_MEM_C_WIDTH-1:0] mem_c, + input logic mem_ck, + input logic mem_ck_n, + input logic mem_cke, + input logic mem_ras_n, + input logic mem_cas_n, + input logic mem_we_n, + input logic mem_act_n, + input logic mem_reset_n, + input logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs_n, + input logic mem_odt, + input logic mem_cs_n, + output logic mem_alert_n, + input logic mem_par + ); + timeunit 1ps; + timeprecision 1ps; + + + localparam MEM_DQS_GROUP_SIZE = PORT_MEM_DQ_WIDTH / PORT_MEM_DQS_WIDTH; + localparam ALERT_N_PIPELINE_SIZE = 2 * (MEM_PAR_ALERT_PW+16) + 1; + localparam DISABLE_NOP_DISPLAY = 1; + localparam CHECK_VIOLATIONS = 1; + localparam REFRESH_INTERVAL_PS = 36000000; + localparam FULL_BURST_REFRESH_COUNT = 8192; + localparam STD_REFRESH_INTERVAL_PS = 7800000; + localparam MAX_LATENCY = 64; + localparam MAX_BURST = 8; + localparam OPCODE_WIDTH = 5; + + localparam INT_MEM_A_WIDTH = ((PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + ? (2 * PORT_MEM_A_WIDTH) : PORT_MEM_A_WIDTH); + localparam INT_MEM_BA_WIDTH = ((PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + ? 3 : PORT_MEM_BA_WIDTH); + + localparam NUM_STACK_LEVELS = ((PROTOCOL_ENUM == "PROTOCOL_DDR4") ? (2**MEM_CHIP_ID_WIDTH) : 1); + + localparam NUM_BANKS_PER_GROUP = 2**INT_MEM_BA_WIDTH; + localparam NUM_BANK_GROUPS = 2**PORT_MEM_BG_WIDTH; + localparam NUM_BANKS = NUM_BANKS_PER_GROUP * NUM_BANK_GROUPS; + + wire [INT_MEM_A_WIDTH - 1:0] mem_a_wire; + wire [INT_MEM_BA_WIDTH - 1:0] mem_ba_wire; + wire [PORT_MEM_BG_WIDTH - 1:0] mem_bg_wire; + + reg [PORT_MEM_A_WIDTH - 1:0] mem_a_posedge; + reg [PORT_MEM_A_WIDTH - 1:0] mem_a_negedge; + + wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_shifted; + wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted; + + wire [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted_2; + reg [PORT_MEM_DQS_WIDTH - 1:0] mem_dqs_n_shifted_2_prev = 'z; + + + typedef enum logic[OPCODE_WIDTH-1:0] { + OPCODE_PRECHARGE = 'b01010, + OPCODE_ACTIVATE = 'b01011, + OPCODE_DDR4_ACTIVATE = 'b00xxx, + OPCODE_WRITE = 'b01100, + OPCODE_READ = 'b01101, + OPCODE_MRS = 'b01000, + OPCODE_REFRESH = 'b01001, + OPCODE_DES = 'b1xxxx, + OPCODE_ZQC = 'b01110, + OPCODE_NOP = 'b01111 + } OPCODE_TYPE; + + typedef enum logic[OPCODE_WIDTH-1:0] { + LPDDR3_OPCODE_PRECHARGE = 'b0_1101, + LPDDR3_OPCODE_ACTIVATE = 'b0_01xx, + LPDDR3_OPCODE_WRITE = 'b0_100x, + LPDDR3_OPCODE_READ = 'b0_101x, + LPDDR3_OPCODE_MRW = 'b0_0000, + LPDDR3_OPCODE_MRR = 'b0_0001, + LPDDR3_OPCODE_REFRESH = 'b0_001x, + LPDDR3_OPCODE_DES = 'b1_xxxx, + LPDDR3_OPCODE_NOP = 'b0_111x + } LPDDR3_OPCODE_TYPE; + + typedef enum { + CA_TRAINING_OFF, + CA_TRAINING_MR41, + CA_TRAINING_MR48 + } CA_TRAINING_MODE; + + typedef enum { + + DDR_BURST_TYPE_BL16, + DDR_BURST_TYPE_BL8, + DDR_BURST_TYPE_OTF, + DDR_BURST_TYPE_BL4 + + } DDR_BURST_TYPE; + + typedef enum { + + DDR_AL_TYPE_ZERO, + DDR_AL_TYPE_CL_MINUS_1, + DDR_AL_TYPE_CL_MINUS_2, + DDR_AL_TYPE_CL_MINUS_3 + + } DDR_AL_TYPE; + + DDR_BURST_TYPE burst_type; + int cas_latency; + int cas_write_latency; + DDR_AL_TYPE al_type; + int parity_latency; + bit wlevel_en; + bit [1:0] lpasr; + bit mpr_mode; + bit [1:0] mpr_page; + bit [1:0] mpr_read_format; + bit read_preamble_training_mode; + bit read_preamble_2ck_mode; + bit geardown_mode; + bit [2:0] fine_granularity_refresh_mode; + bit max_power_saving_en; + bit temp_controlled_refresh_range; + bit temp_controlled_refresh_en; + + int tRTP_cycles = MEM_TRTP; + int tRCD_cycles = MEM_TRCD; + + int clock_cycle; + + reg clock_stable; + + time last_refresh_time; + bit refresh_burst_active; + int refresh_executed_count; + int refresh_debt; + time refresh_required_time; + + CA_TRAINING_MODE lpddr3_ca_training = CA_TRAINING_OFF; + + typedef struct { + + bit [MEM_ROW_ADDR_WIDTH - 1:0] opened_row; + time last_ref_time; + int last_ref_cycle; + int last_activate_cycle; + int last_precharge_cycle; + int last_write_cmd_cycle; + int last_write_access_cycle; + int last_read_cmd_cycle; + int last_read_access_cycle; + + } bank_struct; + + typedef struct { + bank_struct bank[NUM_BANKS_PER_GROUP-1:0]; + } bg_struct; + + typedef struct { + bg_struct bg[NUM_BANK_GROUPS - 1:0]; + } stack_level_struct; + + stack_level_struct device [NUM_STACK_LEVELS - 1:0]; + + bit [PORT_MEM_DQ_WIDTH - 1:0] mem_data[*]; + bit [3:0][7:0] mpr_p0_data; + + typedef enum { + + DDR_CMD_TYPE_PRECHARGE, + DDR_CMD_TYPE_ACTIVATE, + DDR_CMD_TYPE_WRITE, + DDR_CMD_TYPE_READ, + DDR_CMD_TYPE_REFRESH, + DDR_CMD_TYPE_NOP, + DDR_CMD_TYPE_MRS, + DDR_CMD_TYPE_MRW, + DDR_CMD_TYPE_MRR, + DDR_CMD_TYPE_DES, + DDR_CMD_TYPE_ZQC, + DDR_CMD_TYPE_ERROR + + } DDR_CMD_TYPE; + + typedef struct { + DDR_CMD_TYPE cmd_type; + int word_count; + int burst_length; + bit [INT_MEM_BA_WIDTH - 1:0] bank; + bit [PORT_MEM_BG_WIDTH - 1:0] bank_group; + bit [PORT_MEM_C_WIDTH - 1:0] chip_id; + bit [INT_MEM_A_WIDTH - 1:0] address; + bit [OPCODE_WIDTH-1:0] opcode; + } command_struct; + + typedef enum { + RTT_DISABLED, + RTT_RZQ_2, + RTT_RZQ_3, + RTT_RZQ_4, + RTT_RZQ_5, + RTT_RZQ_6, + RTT_RZQ_7, + RTT_RZQ_8, + RTT_RZQ_9, + RTT_RZQ_10, + RTT_RZQ_11, + RTT_RZQ_12, + RTT_RESERVED, + RTT_UNKNOWN + } RTT_TERM_TYPE; + + typedef struct { + RTT_TERM_TYPE rtt_nom; + RTT_TERM_TYPE rtt_drv; + RTT_TERM_TYPE rtt_wr; + } rtt_struct; + + + DDR_CMD_TYPE write_command_queue[$]; + int write_word_count_queue[$]; + int write_burst_length_queue[$]; + bit [INT_MEM_A_WIDTH - 1:0] write_address_queue[$]; + bit [INT_MEM_BA_WIDTH - 1:0] write_bank_queue[$]; + bit [PORT_MEM_BG_WIDTH - 1:0] write_bank_group_queue[$]; + bit [PORT_MEM_C_WIDTH-1:0] write_chip_id_queue[$]; + + DDR_CMD_TYPE read_command_queue[$]; + int read_word_count_queue[$]; + int read_burst_length_queue[$]; + bit [INT_MEM_A_WIDTH - 1:0] read_address_queue[$]; + bit [INT_MEM_BA_WIDTH - 1:0] read_bank_queue[$]; + bit [PORT_MEM_BG_WIDTH - 1:0] read_bank_group_queue[$]; + bit [PORT_MEM_C_WIDTH-1:0] read_chip_id_queue[$]; + + DDR_CMD_TYPE precharge_command_queue[$]; + bit [INT_MEM_BA_WIDTH - 1:0] precharge_bank_queue[$]; + bit [PORT_MEM_BG_WIDTH - 1:0] precharge_bank_group_queue[$]; + bit [PORT_MEM_C_WIDTH-1:0] precharge_chip_id_queue[$]; + + DDR_CMD_TYPE activate_command_queue[$]; + bit [INT_MEM_A_WIDTH-1:0] activate_row_queue[$]; + bit [INT_MEM_BA_WIDTH-1:0] activate_bank_queue[$]; + bit [PORT_MEM_BG_WIDTH-1:0] activate_bank_group_queue[$]; + bit [PORT_MEM_C_WIDTH-1:0] activate_chip_id_queue[$]; + + command_struct parity_latency_queue[$]; + bit [2 * MAX_LATENCY + 1:0] parity_latency_pipeline; + bit [ALERT_N_PIPELINE_SIZE:0] parity_alert_n_pipeline; + + command_struct active_command; + command_struct new_command; + command_struct precharge_command; + command_struct activate_command; + rtt_struct rtt_values; + + bit [2 * MAX_LATENCY + 1:0] read_command_pipeline; + bit [2 * MAX_LATENCY + 1:0] write_command_pipeline; + bit [2 * MAX_LATENCY + 1:0] precharge_command_pipeline; + bit [2 * MAX_LATENCY + 1:0] activate_command_pipeline; + + reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_from_mem; + reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_int; + reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_ca_map; + reg [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_captured; + reg [PORT_MEM_DQ_WIDTH - 1:0] mem_ck_sampled_by_dqs; + reg [PORT_MEM_DQS_WIDTH - 1:0] mem_dm_captured; + bit mem_dq_en; + bit mem_dqs_en; + bit mem_dqs_preamble_no_toggle; + bit mem_dqs_preamble_toggle; + bit mem_dqs_pod_pullup; + wire [PORT_MEM_DQ_WIDTH - 1:0] full_mask; + logic [PORT_MEM_DQ_WIDTH - 1:0] full_dbi_n; + wire [PORT_MEM_DQ_WIDTH - 1:0] full_dbi_n_in; + reg [PORT_MEM_DQS_WIDTH - 1:0] dbi_n; + + time mem_dqs_time[PORT_MEM_DQS_WIDTH]; + time mem_ck_time; + + bit wdbi_en; + bit rdbi_en; + bit dm_n_en; + + + function automatic string bank_str (input [PORT_MEM_C_WIDTH-1:0] chip_id, input [PORT_MEM_BG_WIDTH-1:0] bank_group, input [INT_MEM_BA_WIDTH-1:0] bank); + string result; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + $sformat(result, "C [ %0h ] - BG [ %0h ] - BANK [ %0h ]", chip_id, bank_group, bank); + end else begin + $sformat(result, "BANK [ %0h ]", bank); + end + return result; + endfunction + + task init_guaranteed_write (input integer option); + + static int burst_length = 8; + static int other_bank = 3; + bit [32-1:0] five_s; + bit [32-1:0] a_s; + + int i; + command_struct cmd; + + $display("Pre-initializing memory for guaranteed write"); + + if (option == -1) begin + $display("option=%0d: distorting guaranteed write data", option); + five_s = 32'h55554; + a_s = 32'hAAAAB; + end else begin + five_s = 32'h55555; + a_s = 32'hAAAAA; + end + + cmd.word_count = 0; + cmd.burst_length = burst_length; + cmd.address = 0; + cmd.bank = 0; + cmd.bank_group = 0; + cmd.chip_id = 0; + + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + cmd.opcode = LPDDR3_OPCODE_WRITE; + else + cmd.opcode = OPCODE_WRITE; + + cmd.address = burst_length; + cmd.bank = 0; + for (i = 0; i < burst_length; i++) begin + cmd.word_count = i; + write_memory(cmd, five_s, '0, '0); + end + + cmd.address = 0; + cmd.bank = other_bank; + for (i = 0; i < burst_length; i++) begin + cmd.word_count = i; + write_memory(cmd, five_s, '0, '0); + end + + cmd.address = burst_length; + cmd.bank = other_bank; + for (i = 0; i < burst_length; i++) begin + cmd.word_count = i; + write_memory(cmd, a_s, '0, '0); + end + + cmd.address = 0; + cmd.bank = 0; + for (i = 0; i < burst_length; i++) begin + cmd.word_count = i; + write_memory(cmd, a_s, '0, '0); + end + + endtask + + function automatic int min; + input int a; + input int b; + int result = (a < b) ? a : b; + return result; + endfunction + + task automatic initialize_db; + while (write_command_queue.size() > 0) + write_command_queue.delete(0); + while (write_word_count_queue.size() > 0) + write_word_count_queue.delete(0); + while (write_burst_length_queue.size() > 0) + write_burst_length_queue.delete(0); + while (write_address_queue.size() > 0) + write_address_queue.delete(0); + while (write_bank_queue.size() > 0) + write_bank_queue.delete(0); + + while (read_command_queue.size() > 0) + read_command_queue.delete(0); + while (read_word_count_queue.size() > 0) + read_word_count_queue.delete(0); + while (read_burst_length_queue.size() > 0) + read_burst_length_queue.delete(0); + while (read_address_queue.size() > 0) + read_address_queue.delete(0); + while (read_bank_queue.size() > 0) + read_bank_queue.delete(0); + + while (precharge_command_queue.size() > 0) + precharge_command_queue.delete(0); + while (precharge_bank_queue.size() > 0) + precharge_bank_queue.delete(0); + + while (activate_command_queue.size() > 0) + activate_command_queue.delete(0); + while (activate_bank_queue.size() > 0) + activate_bank_queue.delete(0); + while (activate_row_queue.size() > 0) + activate_row_queue.delete(0); + + mem_data.delete(); + endtask + + task automatic set_cas_latency (input bit [3:0] code); + if(PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + case(code) + 4'b0000 : cas_latency = 9; + 4'b0001 : cas_latency = 10; + 4'b0010 : cas_latency = 11; + 4'b0011 : cas_latency = 12; + 4'b0100 : cas_latency = 13; + 4'b0101 : cas_latency = 14; + 4'b0110 : cas_latency = 15; + 4'b0111 : cas_latency = 16; + 4'b1101 : cas_latency = 17; + 4'b1000 : cas_latency = 18; + 4'b1110 : cas_latency = 19; + 4'b1001 : cas_latency = 20; + 4'b1111 : cas_latency = 21; + 4'b1010 : cas_latency = 22; + 4'b1011 : cas_latency = 24; + default: begin + $display("Error: Use of reserved DDR4 CAS latency code : %b", code); + $stop(1); + end + endcase + end else if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") begin + case(code) + 4'b0001 : cas_latency = 3; + 4'b0100 : cas_latency = 6; + 4'b0110 : cas_latency = 8; + 4'b0111 : cas_latency = 9; + 4'b1000 : cas_latency = 10; + 4'b1001 : cas_latency = 11; + 4'b1010 : cas_latency = 12; + 4'b1100 : cas_latency = 14; + 4'b1110 : cas_latency = 16; + default : begin + $display("Error: Use of a reserved LPDDR3 READ latency code : %b", code); + $stop(1); + end + endcase + end else begin + case(code) + 4'b0001 : cas_latency = 5; + 4'b0010 : cas_latency = 6; + 4'b0011 : cas_latency = 7; + 4'b0100 : cas_latency = 8; + 4'b0101 : cas_latency = 9; + 4'b0110 : cas_latency = 10; + 4'b0111 : cas_latency = 11; + 4'b1000 : cas_latency = 12; + 4'b1001 : cas_latency = 13; + 4'b1010 : cas_latency = 14; + default: begin + end + endcase + end + + if (MEM_VERBOSE) begin + $display(" CAS LATENCY set to : %0d", cas_latency); + end + + endtask + + task automatic set_additive_latency (input bit [1:0] code); + case(code) + 3'b00 : begin + if (MEM_VERBOSE) + $display(" Setting Additive CAS LATENCY to 0"); + al_type = DDR_AL_TYPE_ZERO; + end + 3'b01 : begin + if (MEM_VERBOSE) + $display(" Setting Additive CAS LATENCY to CL - 1"); + al_type = DDR_AL_TYPE_CL_MINUS_1; + end + 3'b10 : begin + if (MEM_VERBOSE) + $display(" Setting Additive CAS LATENCY to CL - 2"); + al_type = DDR_AL_TYPE_CL_MINUS_2; + end + 3'b11 : begin + if (MEM_VERBOSE) + $display(" Setting Additive CAS LATENCY to CL - 3"); + al_type = DDR_AL_TYPE_CL_MINUS_3; + end + endcase + endtask + + task automatic set_write_leveling_mode (input bit code); + wlevel_en = code; + if (MEM_VERBOSE) + $display(" Setting write_leveling mode to %d", wlevel_en); + endtask + + function automatic int get_additive_latency; + int additive_latency = 0; + case(al_type) + DDR_AL_TYPE_ZERO : begin + end + DDR_AL_TYPE_CL_MINUS_1 : begin + additive_latency = cas_latency - 1; + end + DDR_AL_TYPE_CL_MINUS_2 : begin + additive_latency = cas_latency - 2; + end + DDR_AL_TYPE_CL_MINUS_3 : begin + additive_latency = cas_latency - 3; + end + default : begin + $display("Error: Unknown additive latency type: %0d", al_type); + end + endcase + return additive_latency; + endfunction + + task automatic set_parity_latency (input bit [2:0] code); + + int i; + + case(code) + 3'b000 : begin + if (MEM_VERBOSE) + $display(" Setting A/C parity to DISABLED"); + parity_latency = 0; + end + 3'b001 : begin + if (MEM_VERBOSE) + $display(" Setting A/C parity to 4CK"); + parity_latency = 4; + end + 3'b010 : begin + if (MEM_VERBOSE) + $display(" Setting A/C parity to 5CK"); + parity_latency = 5; + end + 3'b011 : begin + if (MEM_VERBOSE) + $display(" Setting A/C parity to 6CK"); + parity_latency = 6; + end + 3'b100 : begin + if (MEM_VERBOSE) + $display(" Setting A/C parity to 8CK"); + parity_latency = 8; + end + default : begin + $display("Error: Use of reserved A/C parity latency code : %b", code); + $stop(1); + end + endcase + + while (parity_latency_queue.size() > 0) + parity_latency_queue.delete(0); + + for (i = 0; i < 2 * MAX_LATENCY; i++) begin + parity_latency_pipeline[i] = 0; + end + + endtask + + function automatic int get_read_latency; + int read_latency = cas_latency + get_additive_latency(); + return read_latency; + endfunction + + function automatic int get_write_latency; + int write_latency = cas_write_latency + get_additive_latency(); + return write_latency; + endfunction + + function automatic int get_precharge_latency; + return tRTP_cycles + get_additive_latency(); + endfunction + + task automatic set_cas_write_latency (input bit [4:0] code); + if(PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + case(code[2:0]) + 3'b000 : cas_write_latency = 9; + 3'b001 : cas_write_latency = 10; + 3'b010 : cas_write_latency = 11; + 3'b011 : cas_write_latency = 12; + 3'b100 : cas_write_latency = 14; + 3'b101 : cas_write_latency = 16; + 3'b110 : cas_write_latency = 18; + default : begin + $display("Error: Use of reserved DDR4 CAS WRITE latency code : %b", code); + $stop(1); + end + endcase + end else if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") begin + casex(code[4:0]) + 5'bx_0001 : cas_write_latency = 1; + 5'bx_0100 : cas_write_latency = 3; + 5'bx_0110 : cas_write_latency = 4; + 5'bx_0111 : cas_write_latency = 5; + 5'b0_1000 : cas_write_latency = 6; + 5'b0_1001 : cas_write_latency = 6; + 5'b0_1010 : cas_write_latency = 6; + 5'b0_1100 : cas_write_latency = 8; + 5'b0_1110 : cas_write_latency = 8; + 5'b1_1000 : cas_write_latency = 8; + 5'b1_1001 : cas_write_latency = 9; + 5'b1_1010 : cas_write_latency = 9; + 5'b1_1100 : cas_write_latency = 11; + 5'b1_1110 : cas_write_latency = 13; + default : begin + $display("Error: Use of reserved LPDDR3 WRITE latency code : %b", code); + $stop(1); + end + endcase + end else begin + case(code[2:0]) + 3'b000 : cas_write_latency = 5; + 3'b001 : cas_write_latency = 6; + 3'b010 : cas_write_latency = 7; + 3'b011 : cas_write_latency = 8; + 3'b100 : cas_write_latency = 9; + 3'b101 : cas_write_latency = 10; + default : begin + $display("Error: Use of reserved CAS WRITE latency code : %b", code); + $stop(1); + end + endcase + end + if (MEM_VERBOSE) + $display(" CAS WRITE LATENCY set to : %0d", cas_write_latency); + endtask + + task automatic set_rtt_nom (input bit [2:0] code); + case (code) + 3'b000: rtt_values.rtt_nom = RTT_DISABLED; + 3'b001: rtt_values.rtt_nom = RTT_RZQ_4; + 3'b010: rtt_values.rtt_nom = RTT_RZQ_2; + 3'b011: rtt_values.rtt_nom = RTT_RZQ_6; + 3'b100: rtt_values.rtt_nom = RTT_RZQ_12; + 3'b101: rtt_values.rtt_nom = RTT_RZQ_8; + default:rtt_values.rtt_nom = RTT_RESERVED; + endcase + if (MEM_VERBOSE) $display(" RTT_NOM set to : %s (%m)", rtt_values.rtt_nom.name()); + endtask + + task automatic set_rtt_drv (input bit [1:0] code); + case (code) + 2'b00: rtt_values.rtt_drv = RTT_RZQ_6; + 2'b01: rtt_values.rtt_drv = RTT_RZQ_7; + default: rtt_values.rtt_drv = RTT_RESERVED; + endcase + if (MEM_VERBOSE) $display(" RTT_DRV set to : %s (%m)", rtt_values.rtt_drv.name()); + endtask + + task automatic set_rtt_wr (input bit [1:0] code); + case (code) + 2'b00: rtt_values.rtt_wr = RTT_DISABLED; + 2'b01: rtt_values.rtt_wr = RTT_RZQ_4; + 2'b10: rtt_values.rtt_wr = RTT_RZQ_2; + 2'b11: rtt_values.rtt_wr = RTT_RESERVED; + endcase + if (MEM_VERBOSE) $display(" RTT_WR set to : %s (%m)", rtt_values.rtt_wr.name()); + endtask + + task automatic reset_dll (input bit code); + if(code == 1'b1) begin + if (MEM_VERBOSE) + $display(" Resetting DLL"); + end + endtask + + task automatic set_burst_type (input bit [1:0] burst_mode); + case (burst_mode) + 2'b00 : begin + if (MEM_VERBOSE) + $display(" Setting burst length Fixed BL8"); + burst_type = DDR_BURST_TYPE_BL8; + end + 2'b01 : begin + if (MEM_VERBOSE) + $display(" Setting burst length on-the-fly"); + burst_type = DDR_BURST_TYPE_OTF; + end + 2'b10 : begin + if (MEM_VERBOSE) + $display(" Setting burst length Fixed BL4"); + burst_type = DDR_BURST_TYPE_BL4; + end + default : begin + $display("ERROR: Invalid burst type mode %0d specified!", burst_mode); + $finish(1); + end + endcase + endtask + + task automatic set_lpasr (input bit [1:0] code); + if (code ^ lpasr) begin + case (code) + 2'b00 : begin + if (MEM_VERBOSE) + $display(" Setting low power array self refresh mode: Manual, Normal temperature range"); + end + 2'b01 : begin + if (MEM_VERBOSE) + $display(" Setting low power array self refresh mode: Manual, Reduced temperature range"); + end + 2'b10 : begin + if (MEM_VERBOSE) + $display(" Setting low power array self refresh mode: Manual, Extended temperature range"); + end + 2'b11 : begin + if (MEM_VERBOSE) + $display(" Setting low power array self refresh mode: Auto self-refresh"); + end + default : begin + $display("ERROR: Invalid low power array self refresh mode %0d specified!", code); + $finish(1); + end + endcase + lpasr = code; + $display(" Low power array self refresh mode behavior is not implemented in this memory model."); + end + endtask + + task automatic set_mpr_mode (input bit [4:0] code); + + mpr_mode = code[0]; + mpr_page = code[2:1]; + mpr_read_format = code[4:3]; + + if (code[0]) begin + if (code[2:1] != 2'b00) begin + $display("ERROR: MPR page %0d is unsupported!", code); + $finish(1); + end + if (code[4:3] != 2'b00) begin + $display("ERROR: MPR read format %0d is unsupported!", code); + $finish(1); + end + $display(" MPR access is on."); + + end else begin + $display(" MPR access is off."); + end + endtask + + task automatic set_geardown_mode (input bit code); + if (code ^ geardown_mode) begin + $display(" Setting geardown mode: %d", code); + if (code) + $display(" Geardown mode behavior is not implemented in this memory model."); + geardown_mode = code; + end + endtask + + task automatic set_fine_granularity_refresh_mode (input bit [2:0] code); + if (code ^ fine_granularity_refresh_mode) begin + case (code) + 3'b000 : begin + if (MEM_VERBOSE) + $display(" Setting fine granularity refresh mode: Fixed 1x"); + end + 3'b001 : begin + if (MEM_VERBOSE) + $display(" Setting fine granularity refresh mode: Fixed 2x"); + end + 3'b010 : begin + if (MEM_VERBOSE) + $display(" Setting fine granularity refresh mode: Fixed 4x"); + end + 3'b101 : begin + if (MEM_VERBOSE) + $display(" Setting fine granularity refresh mode: On-the-fly 2x"); + end + 3'b110 : begin + if (MEM_VERBOSE) + $display(" Setting fine granularity refresh mode: On-the-fly 4x"); + end + default : begin + $display("ERROR: Invalid fine granularity refresh mode %0d specified!", code); + $finish(1); + end + endcase + fine_granularity_refresh_mode = code; + $display(" Fine granularity refresh mode behavior is not implemented in this memory model."); + end + endtask + + task automatic set_max_power_saving (input bit code); + if (code ^ max_power_saving_en) begin + $display(" Setting maximum power saving mode: %d", code); + if (code) + $display(" Maximum power saving mode behavior is not implemented in this memory model."); + max_power_saving_en = code; + end + endtask + task automatic set_temp_controlled_refresh_range(input bit code); + if (code ^ temp_controlled_refresh_range) begin + $display(" Setting temperature controlled refresh range: %d", code); + temp_controlled_refresh_range = code; + end + endtask + task automatic set_temp_controlled_refresh_enable(input bit code); + if (code ^ temp_controlled_refresh_en) begin + $display(" Setting temperature controlled refresh enable: %d", code); + if (code) + $display(" Temperature controlled refresh behavior is not implemented in this memory model."); + temp_controlled_refresh_en = code; + end + endtask + task automatic set_read_preamble_training_mode(input bit code); + if (code ^ read_preamble_training_mode) begin + $display(" Setting read preamble training mode: %d", code); + if (code) + $display(" Read preamble training mode behavior is not fully implemented in this memory model."); + read_preamble_training_mode = code; + end + endtask + task automatic set_read_preamble_2ck_mode(input bit code); + if (code ^ read_preamble_2ck_mode) begin + $display(" Setting read preamble 2ck mode: %d", code); + read_preamble_2ck_mode = code; + end + endtask + + task automatic cmd_nop; + if (MEM_VERBOSE && !DISABLE_NOP_DISPLAY) + $display("[%0t] [DWR=%0d%0d%0d]: NOP Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + endtask + + task automatic cmd_des; + if (MEM_VERBOSE && !DISABLE_NOP_DISPLAY) + $display("[%0t] [DWR=%0d%0d%0d]: DES Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + endtask + + task automatic cmd_zqc; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + if (new_command.chip_id !== 0) begin + $display("Error: ZQC commands sent with chip_id != 0"); + $stop(1); + end + end + + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: ZQC Command", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + endtask + + + task automatic cmd_unknown; + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: WARNING: Unknown Command (OPCODE %b). Command ignored.", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.opcode); + endtask + + task automatic cmd_set_activate; + int activate_latency = min(get_read_latency(), get_write_latency()) + 1; + + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: ACTIVATE (queue) - %s - ROW [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), new_command.address); + activate_command_queue.push_back(DDR_CMD_TYPE_ACTIVATE); + activate_row_queue.push_back(new_command.address); + activate_bank_queue.push_back(new_command.bank); + activate_bank_group_queue.push_back(new_command.bank_group); + activate_chip_id_queue.push_back(new_command.chip_id); + activate_command_pipeline[ 2 * activate_latency ] = 1; + device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle = clock_cycle; + endtask + + task automatic cmd_activate(bit [PORT_MEM_C_WIDTH-1:0] chip_id, bit [PORT_MEM_BG_WIDTH-1:0] bank_group, bit [INT_MEM_BA_WIDTH-1:0] bank, bit [INT_MEM_A_WIDTH-1:0] address); + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: ACTIVATE (execute) - %s - ROW [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(chip_id, bank_group, bank), address); + device[chip_id].bg[bank_group].bank[bank].opened_row = address; + endtask + + task automatic cmd_precharge(bit [PORT_MEM_C_WIDTH-1:0] chip_id, bit [PORT_MEM_BG_WIDTH-1:0] bank_group, bit [INT_MEM_BA_WIDTH-1:0] bank, bit all_banks); + if (MEM_VERBOSE) + if(all_banks) + $display("[%0t] [DWR=%0d%0d%0d]: PRECHARGE - C [ %0h ] - ALL BANKS", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, chip_id); + else + $display("[%0t] [DWR=%0d%0d%0d]: PRECHARGE - %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(chip_id, bank_group, bank)); + device[chip_id].bg[bank_group].bank[bank].last_precharge_cycle = clock_cycle; + endtask + + task automatic cmd_mrs; + int mrs_idx; + + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + mrs_idx = {new_command.bank_group[0], new_command.bank[1:0]}; + + if (PORT_MEM_BG_WIDTH > 1) begin + if (new_command.bank_group[1] !== 1'b0) begin + $display("Error: BG1 must be programmed to 0 during MRS"); + $stop(1); + end + end + if (INT_MEM_A_WIDTH >= 18) begin + if (new_command.address[17] !== 1'b0) begin + $display("Error: A17 must be programmed to 0 during MRS"); + $stop(1); + end + end + if (new_command.address[13] !== 1'b0) begin + $display("Error: A13 must be programmed to 0 during MRS"); + $stop(1); + end + + if (new_command.chip_id !== 0) begin + $display("Error: MRS commands must be issued with chip_id 0"); + $stop(1); + end + end else begin + mrs_idx = new_command.bank; + end + + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: MRS Command - MRS [ %0d ] -> %0h", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, mrs_idx, new_command.address); + + case(mrs_idx) + 3'b000 : begin + if (MEM_VERBOSE) + $display(" MRS - 0"); + set_burst_type(new_command.address[1:0]); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_cas_latency({new_command.address[6:4], new_command.address[2:2] }); + end else begin + set_cas_latency({new_command.address[2:2], new_command.address[6:4]}); + end + reset_dll(new_command.address[8]); + end + + 3'b001 : begin + if (MEM_VERBOSE) + $display(" MRS - 1"); + set_additive_latency(new_command.address[4:3]); + set_write_leveling_mode(new_command.address[7]); + if (PROTOCOL_ENUM == "PROTOCOL_DDR3") begin + set_rtt_nom({new_command.address[9],new_command.address[6],new_command.address[2]}); + set_rtt_drv({new_command.address[5],new_command.address[1]}); + end + end + + 3'b010 : begin + if (MEM_VERBOSE) + $display(" MRS - 2"); + set_cas_write_latency({2'b0, new_command.address[5:3]}); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_lpasr(new_command.address[7:6]); + end + else if (PROTOCOL_ENUM == "PROTOCOL_DDR3") begin + set_rtt_wr(new_command.address[10:9]); + end + end + + 3'b011 : begin + if (MEM_VERBOSE) + $display(" MRS - 3"); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_mpr_mode({new_command.address[12:11], new_command.address[1:0], new_command.address[2]}); + set_geardown_mode(new_command.address[3]); + set_fine_granularity_refresh_mode(new_command.address[8:6]); + end + end + + 3'b100 : begin + if (MEM_VERBOSE) + $display(" MRS - 4"); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_max_power_saving(new_command.address[1]); + set_temp_controlled_refresh_range(new_command.address[2]); + set_temp_controlled_refresh_enable(new_command.address[3]); + set_read_preamble_training_mode(new_command.address[10]); + set_read_preamble_2ck_mode(new_command.address[11]); + end + end + + 3'b101 : begin + if (MEM_VERBOSE) + $display(" MRS - 5"); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_parity_latency(new_command.address[2:0]); + dm_n_en = new_command.address[10]; + wdbi_en = new_command.address[11]; + rdbi_en = new_command.address[12]; + end + end + + 3'b110 : begin + if (MEM_VERBOSE) + $display(" MRS - 6: not supported"); + end + + 3'b111 : begin + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + if (MEM_VERBOSE) begin + $display(" Detected RCD/DB Control Word"); + end + end else begin + $display("Error: MRS Invalid Bank Address: %0d", mrs_idx); + $stop(1); + end + end + endcase + endtask + + task automatic cmd_mrr; + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: MRR Command - MRR [ %0d ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.address[11:4]); + + $display("Warning: MRR not implemented"); + endtask + + task automatic cmd_mrw; + if (lpddr3_ca_training == CA_TRAINING_OFF || new_command.address[11:4] == 41 || new_command.address[11:4] == 42 || new_command.address[11:4] == 48) begin + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: MRW Command - MRW [ %0d ] -> %0h", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.address[11:4], new_command.address[19:12]); + + case (new_command.address[11:4]) + 1 : begin + end + 2 : begin + set_cas_write_latency({new_command.address[18], new_command.address[15:12]}); + set_cas_latency(new_command.address[15:12]); + end + 3 : begin + end + 9 : begin + $display(" Warning: MRW 9 not implemented in model"); + end + 10 : begin + $display(" Warning: MRW 10 not implemented in model"); + end + 11 : begin + $display(" Warning: MRW 11 not implemented in model"); + end + 16 : begin + $display(" Warning: setting PASR bank mask not implemented in model"); + end + 17 : begin + $display(" Warning: setting PASR segment mask not implemented in model"); + end + 41 : begin + lpddr3_ca_training = CA_TRAINING_MR41; + $display(" CA Training Phase 1"); + end + 42 : begin + lpddr3_ca_training = CA_TRAINING_OFF; + $display(" CA Training End"); + end + 48 : begin + lpddr3_ca_training = CA_TRAINING_MR48; + $display(" CA Training Phase 2"); + end + 63 : begin + $display(" MRW Reset Issued"); + end + default : begin + $display("Warning: Attempted Write to Read-Only Mode Register: %0d", new_command.address[11:4]); + end + endcase + end + endtask + + task automatic cmd_refresh(input int chip_id_num); + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: REFRESH Command C [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, chip_id_num); + + for (int g = 0; g < NUM_BANK_GROUPS; g++) begin + for (int b = 0; b < NUM_BANKS_PER_GROUP; b++) begin + refresh_bank(chip_id_num, g, b); + end + end + endtask + + task automatic cmd_read; + int read_latency = get_read_latency(); + int precharge_latency = get_precharge_latency(); + + int auto_precharge; + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + auto_precharge = mem_a[0]; + else + auto_precharge = mem_a_wire[10]; + + if (MEM_VERBOSE) begin + if (mpr_mode) begin + $display("[%0t] [DWR=%0d%0d%0d]: MPR READ - PAGE [ %0d ] - LOC[ %0d ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, mpr_page, new_command.bank); + end else if(auto_precharge) begin + $display("[%0t] [DWR=%0d%0d%0d]: READ with AP (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), new_command.address); + end else begin + $display("[%0t] [DWR=%0d%0d%0d]: READ (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), new_command.address); + end + end + + new_command.word_count = 0; + read_command_queue.push_back(new_command.cmd_type); + read_word_count_queue.push_back(new_command.word_count); + read_burst_length_queue.push_back(new_command.burst_length); + read_address_queue.push_back(new_command.address); + read_bank_queue.push_back(new_command.bank); + read_bank_group_queue.push_back(new_command.bank_group); + read_chip_id_queue.push_back(new_command.chip_id); + + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + read_command_pipeline[(2 * read_latency) + 1] = 1; + else + read_command_pipeline[2 * read_latency] = 1; + + device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle = clock_cycle; + + if (!mpr_mode) begin + refresh_bank(new_command.chip_id, new_command.bank_group, new_command.bank); + end + + if(auto_precharge) begin + precharge_command_queue.push_back(DDR_CMD_TYPE_PRECHARGE); + precharge_bank_queue.push_back(new_command.bank); + precharge_bank_group_queue.push_back(new_command.bank_group); + precharge_chip_id_queue.push_back(new_command.chip_id); + precharge_command_pipeline[ 2 * precharge_latency ] = 1; + end + endtask + + task automatic cmd_write; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4" && mpr_mode) begin + mpr_p0_data[new_command.bank] = new_command.address[7:0]; + $display("[%0t] [DWR=%0d%0d%0d]: MPR WRITE - PAGE [ %d ] - LOC[ %0d ] - DATA = %0h", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, mpr_page, new_command.bank, new_command.address[7:0]); + + end else begin + int write_latency = get_write_latency(); + + int auto_precharge; + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + auto_precharge = mem_a[0]; + else + auto_precharge = mem_a_wire[10]; + + if (MEM_VERBOSE) begin + if(auto_precharge) + $display("[%0t] [DWR=%0d%0d%0d]: WRITE with AP (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), new_command.address); + else + $display("[%0t] [DWR=%0d%0d%0d]: WRITE (BL%0d) - %s - COL [ %0h ]", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, new_command.burst_length, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), new_command.address); + end + + new_command.word_count = 0; + write_command_queue.push_back(new_command.cmd_type); + write_word_count_queue.push_back(new_command.word_count); + write_burst_length_queue.push_back(new_command.burst_length); + write_address_queue.push_back(new_command.address); + write_bank_queue.push_back(new_command.bank); + write_bank_group_queue.push_back(new_command.bank_group); + write_chip_id_queue.push_back(new_command.chip_id); + + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") + write_command_pipeline[(2 * write_latency) + 1] = 1'b1; + else + write_command_pipeline[2 * write_latency] = 1'b1; + + device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle = clock_cycle; + end + endtask + + task automatic refresh_bank(input int chip_id_num, input int bank_group_num, input int bank_num); + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: Refreshing - %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(chip_id_num, bank_group_num, bank_num)); + device[chip_id_num].bg[bank_group_num].bank[bank_num].last_ref_time = $time; + device[chip_id_num].bg[bank_group_num].bank[bank_num].last_ref_cycle = clock_cycle; + endtask + + task automatic init_banks; + int c, b,g; + for (c = 0; c < NUM_STACK_LEVELS; c++) begin + for (g = 0; g < NUM_BANK_GROUPS; g++) begin + for (b = 0; b < NUM_BANKS_PER_GROUP; b++) begin + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: Initializing - %s", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(c, g, b)); + device[c].bg[g].bank[b].opened_row = '0; + device[c].bg[g].bank[b].last_ref_time = 0; + device[c].bg[g].bank[b].last_ref_cycle = 0; + device[c].bg[g].bank[b].last_activate_cycle = 0; + device[c].bg[g].bank[b].last_precharge_cycle = 0; + device[c].bg[g].bank[b].last_read_cmd_cycle = 0; + device[c].bg[g].bank[b].last_read_access_cycle = 0; + device[c].bg[g].bank[b].last_write_cmd_cycle = 0; + device[c].bg[g].bank[b].last_write_access_cycle = 0; + end + end + end + endtask + + task automatic check_violations; + + /* **** * + * tRCD * + * **** */ + + if(new_command.cmd_type == DDR_CMD_TYPE_READ) begin + if(!mpr_mode && device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle > device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle + get_additive_latency() - tRCD_cycles) begin + $display("[%0t] [DWR=%0d%0d%0d]: ERROR: tRCD violation (READ) on %s @ cycle %0d", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), clock_cycle); + $display(" tRCD = %0d", tRCD_cycles); + $display(" Last ACTIVATE @ %0d", device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle); + $display(" Last READ CMD @ %0d", device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_read_cmd_cycle); + $finish(1); + end + end + if(new_command.cmd_type == DDR_CMD_TYPE_WRITE) begin + if(!mpr_mode && device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle > device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle + get_additive_latency() - tRCD_cycles) begin + $display("[%0t] [DWR=%0d%0d%0d]: ERROR: tRCD violation (WRITE) on %s @ cycle %0d", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, bank_str(new_command.chip_id, new_command.bank_group, new_command.bank), clock_cycle); + $display(" tRCD = %0d", tRCD_cycles); + $display(" Last ACTIVATE @ %0d", device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_activate_cycle); + $display(" Last WRITE CMD @ %0d", device[new_command.chip_id].bg[new_command.bank_group].bank[new_command.bank].last_write_cmd_cycle); + $finish(1); + end + end + endtask + + task write_memory( + input command_struct write_command, + input [PORT_MEM_DQ_WIDTH - 1:0] write_data, + input [PORT_MEM_DQ_WIDTH - 1:0] data_mask, + input [PORT_MEM_DQ_WIDTH - 1:0] dbi_n); + + bit [PORT_MEM_C_WIDTH - 1:0] chip_id; + bit [PORT_MEM_BG_WIDTH - 1:0] bank_group; + bit [INT_MEM_BA_WIDTH - 1:0] bank_address; + bit [MEM_ROW_ADDR_WIDTH - 1:0] row_address; + bit [MEM_COL_ADDR_WIDTH - 1:0] col_address; + bit [PORT_MEM_BG_WIDTH + INT_MEM_BA_WIDTH + MEM_ROW_ADDR_WIDTH + MEM_COL_ADDR_WIDTH - 1 : 0] address; + bit [PORT_MEM_DQ_WIDTH - 1:0] masked_data; + + integer i; + + chip_id = write_command.chip_id; + bank_group = write_command.bank_group; + bank_address = write_command.bank; + row_address = device[chip_id].bg[bank_group].bank[bank_address].opened_row; + col_address = write_command.address; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + address = {chip_id, bank_group, bank_address, row_address, col_address} + write_command.word_count; + end else begin + address = {bank_address, row_address, col_address} + write_command.word_count; + end + + for(i = 0; i < PORT_MEM_DQ_WIDTH; i = i + 1) begin + if (data_mask[i] !== 0 && data_mask[i] !== 1) + masked_data[i] = 'x; + else if (wdbi_en) begin + masked_data[i] = dbi_n[i] ? write_data[i] : ~write_data[i]; + end else if (PROTOCOL_ENUM == "PROTOCOL_DDR4" ? ~data_mask[i] : data_mask[i]) + begin + if (mem_data.exists(address)) + masked_data[i] = mem_data[address][i]; + else + masked_data[i] = 'x; + end + else + masked_data[i] = write_data[i]; + end + + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: Writing data %h (%h/%h) @ %0h (CGBRC=%0h/%0h/%0h/%0h/%0h ) burst %0d", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, masked_data, write_data, PROTOCOL_ENUM == "PROTOCOL_DDR4" ? data_mask : ~data_mask, address, chip_id, bank_group, bank_address, row_address, col_address, write_command.word_count); + + mem_data[address] = masked_data; + device[chip_id].bg[bank_group].bank[bank_address].last_write_access_cycle = clock_cycle; + endtask + + task read_memory( + input command_struct read_command, + output [PORT_MEM_DQ_WIDTH - 1:0] read_data, + output [PORT_MEM_DQS_WIDTH - 1:0] dbi_n); + + bit [PORT_MEM_C_WIDTH - 1:0] chip_id; + bit [PORT_MEM_BG_WIDTH - 1:0] bank_group; + bit [INT_MEM_BA_WIDTH - 1:0] bank_address; + bit [MEM_ROW_ADDR_WIDTH - 1:0] row_address; + bit [MEM_COL_ADDR_WIDTH - 1:0] col_address; + bit [PORT_MEM_BG_WIDTH + INT_MEM_BA_WIDTH + MEM_ROW_ADDR_WIDTH + MEM_COL_ADDR_WIDTH - 1 : 0] address; + reg [1:0] int_error_inject; + integer bit_index; + + chip_id = read_command.chip_id; + bank_group = read_command.bank_group; + bank_address = read_command.bank; + row_address = device[chip_id].bg[bank_group].bank[bank_address].opened_row; + col_address = read_command.address; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + address = {chip_id, bank_group, bank_address, row_address, col_address} + read_command.word_count; + end else begin + address = {bank_address, row_address, col_address} + read_command.word_count; + end + + if (mpr_mode) begin + read_data = {PORT_MEM_DQ_WIDTH{mpr_p0_data[read_command.bank][7 - read_command.word_count]}}; + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: Reading MPR data %h @ %0d %0d burst %0d", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, read_data, mpr_page, read_command.bank, read_command.word_count); + + end else if (mem_data.exists(address)) begin + integer i, j; + if (rdbi_en) begin + for (i = 0; i < PORT_MEM_DQS_WIDTH; i = i + 1) begin + integer sum; + sum = 0; + for (j = 0; j < (MEM_DQS_GROUP_SIZE); j = j + 1) begin + sum = sum + mem_data[address][i*(MEM_DQS_GROUP_SIZE) + j]; + end + dbi_n[i] = sum >= 4; + end + read_data = mem_data[address]; + end else begin + dbi_n = 'z; + if (MEM_MICRON_AUTOMATA && address [2:0] >= 3'b100) + read_data = {PORT_MEM_DQ_WIDTH{1'b0}}; + else + read_data = mem_data[address]; + end + for (i = 0; i < PORT_MEM_DQ_WIDTH; i = i + 1) begin: dbi_n_in_mapping + full_dbi_n [i] = dbi_n[i / MEM_DQS_GROUP_SIZE]; + end + + if (MEM_CFG_GEN_SBE == 1) begin + int_error_inject = 2'b01; + end + else if (MEM_CFG_GEN_DBE == 1) begin + int_error_inject = 2'b11; + end + else begin + int_error_inject = 2'b00; + end + bit_index = {$random} % PORT_MEM_DQ_WIDTH; + read_data[bit_index] = read_data[bit_index] ^ int_error_inject[0]; + if (bit_index < PORT_MEM_DQ_WIDTH-1) begin + read_data[bit_index+1] = read_data[bit_index+1] ^ int_error_inject[1]; + end + + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: Reading data %h @ %0h (CGBRC=%0h/%0h/%0h/%0h/%0h ) burst %0d", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, read_data, address, chip_id, bank_group, bank_address, row_address, col_address, read_command.word_count); + end + else begin + if (MEM_VERBOSE) + $display("[%0t] [DWR=%0d%0d%0d]: WARNING: Attempting to read from uninitialized location @ %0h (CGBRC=%0h/%0h/%0h/%0h/%0h) burst %0d", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, address, chip_id, bank_group, bank_address, row_address, col_address, read_command.word_count); + + if (rdbi_en) begin + read_data = '1; + dbi_n = '1; + full_dbi_n = '1; + end else begin + read_data = '0; + dbi_n = 'z; + full_dbi_n = 'z; + end + end + + device[chip_id].bg[bank_group].bank[bank_address].last_read_access_cycle = clock_cycle; + endtask + + if(MEM_MIRROR_ADDRESSING) begin + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + if (PORT_MEM_A_WIDTH > 14) begin + assign mem_a_wire = {mem_a[PORT_MEM_A_WIDTH - 1:14], mem_a[11], mem_a[12], mem_a[13], mem_a[10:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]}; + end else begin + assign mem_a_wire = {mem_a[11], mem_a[12], mem_a[13], mem_a[10:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]}; + end + + if(PORT_MEM_BA_WIDTH > 2) begin + assign mem_ba_wire = {mem_ba[PORT_MEM_BA_WIDTH - 1:2], mem_ba[0], mem_ba[1]}; + end else if(PORT_MEM_BA_WIDTH > 1) begin + assign mem_ba_wire = {mem_ba[0], mem_ba[1]}; + end else begin + assign mem_ba_wire = mem_ba; + end + + if(PORT_MEM_BG_WIDTH > 2) begin + assign mem_bg_wire = {mem_bg[PORT_MEM_BG_WIDTH - 1:2], mem_bg[0], mem_bg[1]}; + end else if(PORT_MEM_BG_WIDTH > 1) begin + assign mem_bg_wire = {mem_bg[0], mem_bg[1]}; + end else begin + assign mem_bg_wire = mem_bg; + end + + end else begin + assign mem_a_wire = {mem_a[PORT_MEM_A_WIDTH - 1:9], mem_a[7], mem_a[8], mem_a[5], mem_a[6], mem_a[3], mem_a[4], mem_a[2:0]}; + + if(PORT_MEM_BA_WIDTH > 2) begin + assign mem_ba_wire = {mem_ba[PORT_MEM_BA_WIDTH - 1:2], mem_ba[0], mem_ba[1]}; + end else begin + assign mem_ba_wire = {mem_ba[0], mem_ba[1]}; + end + + assign mem_bg_wire = mem_bg; + end + end else begin + assign mem_a_wire = mem_a; + assign mem_ba_wire = mem_ba; + assign mem_bg_wire = mem_bg; + end + + logic mem_ck_diff; + logic mem_ck_ca; + always @(posedge mem_ck) begin + if (mem_cke == 1'b1) begin + #8 mem_ck_diff <= mem_ck; + end + + if (lpddr3_ca_training != CA_TRAINING_OFF) begin + #8 mem_ck_ca <= mem_ck; + end + end + + always @(posedge mem_ck_n) begin + if (mem_cke == 1'b1) begin + #8 mem_ck_diff <= ~mem_ck_n; + end + + if (lpddr3_ca_training != CA_TRAINING_OFF) begin + #8 mem_ck_ca <= mem_ck; + end + end + + initial begin + int i; + + $display("Intel FPGA Generic DDRx Memory Model"); + if (MEM_VERBOSE) begin + $display("[%0t] [DWR=%0d%0d%0d]: Max refresh interval of %0d ps", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, REFRESH_INTERVAL_PS); + end + + clock_cycle = 0; + clock_stable = 1'b0; + initialize_db; + set_burst_type(2'b0); + init_banks(); + + mem_data.delete(); + + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") begin + set_burst_type(2'b0); + set_cas_latency(MEM_INIT_MRS2[3:0]); + set_cas_write_latency({MEM_INIT_MRS2[7], MEM_INIT_MRS2[3:0]}); + set_additive_latency(2'b0); + lpddr3_ca_training = CA_TRAINING_OFF; + mem_dq_ca_map = 16'b0; + end else begin + if (MEM_VERBOSE) begin + $display(" MRS - 0"); + end + + set_burst_type(MEM_INIT_MRS0[1:0]); + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + set_cas_latency({MEM_INIT_MRS0[6:4], MEM_INIT_MRS0[2]}); + end else begin + set_cas_latency({MEM_INIT_MRS0[2], MEM_INIT_MRS0[6:4]}); + end + + if (MEM_VERBOSE) begin + $display(" MRS - 1"); + end + + set_additive_latency(MEM_INIT_MRS1[4:3]); + + if (MEM_VERBOSE) begin + $display(" MRS - 2"); + end + + set_cas_write_latency({2'b0, MEM_INIT_MRS2[5:3]}); + + if (MEM_VERBOSE) begin + $display(" MRS - 3: not supported"); + end + end + + parity_latency = 0; + wdbi_en = 0; + rdbi_en = 0; + mpr_mode = 0; + read_preamble_training_mode = 0; + read_preamble_2ck_mode = 0; + max_power_saving_en = 0; + temp_controlled_refresh_range = 0; + temp_controlled_refresh_en = 0; + + if (MEM_GUARANTEED_WRITE_INIT != 0) begin + init_guaranteed_write(MEM_GUARANTEED_WRITE_INIT); + end + + active_command.cmd_type <= DDR_CMD_TYPE_NOP; + + for (i = 0; i < 2 * MAX_LATENCY; i++) begin + read_command_pipeline[i] = 0; + write_command_pipeline[i] = 0; + parity_latency_pipeline[i] = 0; + end + + for (i = 0; i <= ALERT_N_PIPELINE_SIZE; i++) begin + parity_alert_n_pipeline[i] = 1'b1; + end + + last_refresh_time = 0; + refresh_burst_active = 0; + refresh_executed_count = 0; + refresh_required_time = 0; + refresh_debt = 0; + mem_ck_sampled_by_dqs = '0; + end + + always @ (posedge mem_ck) begin + clock_cycle <= clock_cycle + 1; + if (clock_cycle == 4) clock_stable <= 1'b1; + end + + wire [MEM_COL_ADDR_WIDTH-1:0] col_addr; + generate + if(MEM_COL_ADDR_WIDTH <= 10) begin : col_addr_gen1 + assign col_addr = mem_a_wire[9:0]; + end + else if(MEM_COL_ADDR_WIDTH == 11) begin : col_addr_gen2 + assign col_addr = {mem_a_wire[11],mem_a_wire[9:0]}; + end + else begin : col_addr_gen3 + assign col_addr = {mem_a_wire[MEM_COL_ADDR_WIDTH+1:13],mem_a_wire[11],mem_a_wire[9:0]}; + end + endgenerate + + always @ (posedge mem_ck_diff or negedge mem_ck_diff) begin + int i; + + mem_ck_time = $time; + read_command_pipeline = read_command_pipeline >> 1; + write_command_pipeline = write_command_pipeline >> 1; + activate_command_pipeline = activate_command_pipeline >> 1; + parity_latency_pipeline = parity_latency_pipeline >> 1; + parity_alert_n_pipeline = parity_alert_n_pipeline >> 1; + + parity_alert_n_pipeline[ALERT_N_PIPELINE_SIZE] = 1'b1; + + if(mem_ck_diff && clock_stable && (PROTOCOL_ENUM != "PROTOCOL_LPDDR3")) begin + new_command.bank = mem_ba_wire; + new_command.bank_group = mem_bg_wire; + new_command.chip_id = mem_c; + new_command.word_count = 0; + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + new_command.opcode = {mem_cs_n, mem_act_n, mem_ras_n, mem_cas_n, mem_we_n}; + end else begin + new_command.opcode = {mem_cs_n, 1'b1, mem_ras_n, mem_cas_n, mem_we_n}; + end + + case (burst_type) + DDR_BURST_TYPE_BL8 : new_command.burst_length = 8; + DDR_BURST_TYPE_BL4 : new_command.burst_length = 4; + DDR_BURST_TYPE_OTF : new_command.burst_length = (mem_a_wire[12]) ? 8 : 4; + endcase + + casex (new_command.opcode) + OPCODE_PRECHARGE : new_command.cmd_type = DDR_CMD_TYPE_PRECHARGE; + OPCODE_ACTIVATE : new_command.cmd_type = DDR_CMD_TYPE_ACTIVATE; + OPCODE_DDR4_ACTIVATE : new_command.cmd_type = DDR_CMD_TYPE_ACTIVATE; + OPCODE_WRITE : new_command.cmd_type = DDR_CMD_TYPE_WRITE; + OPCODE_READ : new_command.cmd_type = DDR_CMD_TYPE_READ; + OPCODE_MRS : new_command.cmd_type = DDR_CMD_TYPE_MRS; + OPCODE_REFRESH : new_command.cmd_type = DDR_CMD_TYPE_REFRESH; + OPCODE_NOP : new_command.cmd_type = DDR_CMD_TYPE_NOP; + OPCODE_DES : new_command.cmd_type = DDR_CMD_TYPE_DES; + OPCODE_ZQC : new_command.cmd_type = DDR_CMD_TYPE_ZQC; + default : new_command.cmd_type = DDR_CMD_TYPE_ERROR; + endcase + + new_command.address = mem_a_wire; + if(new_command.cmd_type == DDR_CMD_TYPE_READ || new_command.cmd_type == DDR_CMD_TYPE_WRITE) begin + new_command.address = {'0,col_addr}; + end + + if (REFRESH_BURST_VALIDATION) begin + if (new_command.cmd_type == DDR_CMD_TYPE_REFRESH) begin + if (!refresh_burst_active) begin + refresh_burst_active = 1; + refresh_executed_count = 1; + refresh_required_time = mem_ck_time - last_refresh_time; + $display("[%0t] [DWR=%0d%0d%0d]: Time since last refresh %0t ps", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_required_time); + last_refresh_time = mem_ck_time; + end else begin + refresh_executed_count = refresh_executed_count + 1; + end + end else if (new_command.cmd_type == DDR_CMD_TYPE_NOP || new_command.cmd_type == DDR_CMD_TYPE_DES) begin + end else begin + if (refresh_burst_active) begin + refresh_burst_active = 0; + if (refresh_executed_count >= FULL_BURST_REFRESH_COUNT) + refresh_debt = -(STD_REFRESH_INTERVAL_PS * 9); + else + refresh_debt = refresh_debt + (refresh_required_time - (STD_REFRESH_INTERVAL_PS * refresh_executed_count)); + + if (refresh_debt > STD_REFRESH_INTERVAL_PS * 9) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: REFRESH interval has exceeded allowable buffer! %0d refreshes executed. Debt: %0t ps", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt); + $finish(1); + end else begin + $display("[%0t] [DWR=%0d%0d%0d]: REFRESH burst complete! %0d refreshes executed. Buffer: %0d ps", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt); + end + end + end + end + + if (parity_latency > 0) begin + + reg my_parity; + my_parity = ^{mem_a, mem_ba, mem_bg, mem_act_n, mem_c}; + if (mem_cs_n == 1'b0) begin + if (my_parity != mem_par) begin + for (i = 0; i < 2*parity_latency + 2*(parity_latency + MEM_PAR_ALERT_PW); i = i + 1) begin + if (i >= 2*parity_latency) begin + parity_alert_n_pipeline[i] = 1'b0; + end + end + end else begin + parity_latency_queue.push_back(new_command); + parity_latency_pipeline[2*parity_latency] = 1'b1; + end + end + + if (parity_latency_pipeline[0]) begin + if (parity_latency_queue.size() == 0) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Parity latency command queue empty but commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end else begin + new_command = parity_latency_queue.pop_front(); + end + end else begin + new_command.cmd_type = DDR_CMD_TYPE_DES; + end + + if (parity_alert_n_pipeline[0] == 1'b0) begin + new_command.cmd_type = DDR_CMD_TYPE_ERROR; + end + end + + case (new_command.cmd_type) + DDR_CMD_TYPE_NOP : cmd_nop(); + DDR_CMD_TYPE_DES : cmd_des(); + DDR_CMD_TYPE_ZQC : cmd_zqc(); + DDR_CMD_TYPE_ERROR : cmd_unknown(); + DDR_CMD_TYPE_ACTIVATE : cmd_set_activate(); + DDR_CMD_TYPE_PRECHARGE : cmd_precharge(new_command.chip_id, new_command.bank_group, new_command.bank, mem_a_wire[10]); + DDR_CMD_TYPE_WRITE : cmd_write(); + DDR_CMD_TYPE_READ : cmd_read(); + DDR_CMD_TYPE_MRS : cmd_mrs(); + DDR_CMD_TYPE_REFRESH : cmd_refresh(new_command.chip_id); + endcase + + if(CHECK_VIOLATIONS) + check_violations(); + + end else if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3") begin + if (mem_ck_diff && clock_stable) begin + new_command.bank = mem_a[9:7]; + new_command.bank_group = 0; + new_command.chip_id = 0; + new_command.word_count = 0; + new_command.burst_length = 8; + + mem_a_posedge = mem_a; + + new_command.opcode = {mem_cs_n, mem_a[0], mem_a[1], mem_a[2], mem_a[3]}; + + casex (new_command.opcode) + LPDDR3_OPCODE_PRECHARGE : new_command.cmd_type = DDR_CMD_TYPE_PRECHARGE; + LPDDR3_OPCODE_ACTIVATE : new_command.cmd_type = DDR_CMD_TYPE_ACTIVATE; + LPDDR3_OPCODE_WRITE : new_command.cmd_type = DDR_CMD_TYPE_WRITE; + LPDDR3_OPCODE_READ : new_command.cmd_type = DDR_CMD_TYPE_READ; + LPDDR3_OPCODE_MRW: new_command.cmd_type = DDR_CMD_TYPE_MRW; + LPDDR3_OPCODE_MRR: new_command.cmd_type = DDR_CMD_TYPE_MRR; + LPDDR3_OPCODE_REFRESH : new_command.cmd_type = DDR_CMD_TYPE_REFRESH; + LPDDR3_OPCODE_NOP : new_command.cmd_type = DDR_CMD_TYPE_NOP; + LPDDR3_OPCODE_DES : new_command.cmd_type = DDR_CMD_TYPE_DES; + default : new_command.cmd_type = DDR_CMD_TYPE_ERROR; + endcase + + if (REFRESH_BURST_VALIDATION) begin + if (new_command.cmd_type == DDR_CMD_TYPE_REFRESH) begin + if (!refresh_burst_active) begin + refresh_burst_active = 1; + refresh_executed_count = 1; + refresh_required_time = mem_ck_time - last_refresh_time; + $display("[%0t] [DWR=%0d%0d%0d]: Time since last refresh %0t ps", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_required_time); + last_refresh_time = mem_ck_time; + end else begin + refresh_executed_count = refresh_executed_count + 1; + end + end else if (new_command.cmd_type == DDR_CMD_TYPE_NOP || new_command.cmd_type == DDR_CMD_TYPE_DES) begin + end else begin + if (refresh_burst_active) begin + refresh_burst_active = 0; + if (refresh_executed_count >= FULL_BURST_REFRESH_COUNT) + refresh_debt = -(STD_REFRESH_INTERVAL_PS * 9); + else + refresh_debt = refresh_debt + (refresh_required_time - (STD_REFRESH_INTERVAL_PS * refresh_executed_count)); + + if (refresh_debt > STD_REFRESH_INTERVAL_PS * 9) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: REFRESH interval has exceeded allowable buffer! %0d refreshes executed. Debt: %0t ps", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt); + $finish(1); + end else begin + $display("[%0t] [DWR=%0d%0d%0d]: REFRESH burst complete! %0d refreshes executed. Buffer: %0d ps", + $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX, refresh_executed_count, refresh_debt); + end + end + end + end + end else if (!mem_ck_diff && clock_stable) begin + mem_a_negedge = mem_a; + + if ((new_command.cmd_type == DDR_CMD_TYPE_READ) || (new_command.cmd_type == DDR_CMD_TYPE_WRITE)) begin + new_command.address = {8'b0, mem_a_negedge[9:1], mem_a_posedge[6:5], 1'b0}; + end else if (new_command.cmd_type == DDR_CMD_TYPE_ACTIVATE) begin + new_command.address = {5'b0, mem_a_negedge[9:8], mem_a_posedge[6:2], mem_a_negedge[7:0]}; + end else begin + new_command.address = {mem_a_negedge, mem_a_posedge}; + end + + case (new_command.cmd_type) + DDR_CMD_TYPE_NOP : cmd_nop(); + DDR_CMD_TYPE_DES : cmd_des(); + DDR_CMD_TYPE_ERROR : cmd_unknown(); + DDR_CMD_TYPE_ACTIVATE : cmd_set_activate(); + DDR_CMD_TYPE_PRECHARGE : cmd_precharge(new_command.chip_id, new_command.bank_group, new_command.bank, mem_a_negedge[4]); + DDR_CMD_TYPE_WRITE : cmd_write(); + DDR_CMD_TYPE_READ : cmd_read(); + DDR_CMD_TYPE_MRW : cmd_mrw(); + DDR_CMD_TYPE_MRR : cmd_mrr(); + DDR_CMD_TYPE_REFRESH : cmd_refresh(new_command.chip_id); + endcase + + if (CHECK_VIOLATIONS) + check_violations(); + end + end + + + if (read_command_pipeline[0]) begin + if (read_command_queue.size() == 0) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: READ command queue empty but READ commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end + end + + if (write_command_pipeline[0]) begin + if (write_command_queue.size() == 0) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: WRITE command queue empty but WRITE commands expected!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end + end + + if (active_command.cmd_type != DDR_CMD_TYPE_NOP) begin + if (active_command.word_count == active_command.burst_length) begin + active_command.cmd_type = DDR_CMD_TYPE_NOP; + end + end + + + if (active_command.cmd_type == DDR_CMD_TYPE_NOP) begin + + if (read_command_pipeline[0]) begin + active_command.cmd_type = read_command_queue.pop_front(); + active_command.word_count = read_word_count_queue.pop_front(); + active_command.burst_length = read_burst_length_queue.pop_front(); + active_command.address = read_address_queue.pop_front(); + active_command.bank = read_bank_queue.pop_front(); + active_command.bank_group = read_bank_group_queue.pop_front(); + active_command.chip_id = read_chip_id_queue.pop_front(); + + if (active_command.cmd_type != DDR_CMD_TYPE_READ) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Expected READ command not in queue!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end + + end + else if (write_command_pipeline[0]) begin + active_command.cmd_type = write_command_queue.pop_front(); + active_command.word_count = write_word_count_queue.pop_front(); + active_command.burst_length = write_burst_length_queue.pop_front(); + active_command.address = write_address_queue.pop_front(); + active_command.bank = write_bank_queue.pop_front(); + active_command.bank_group = write_bank_group_queue.pop_front(); + active_command.chip_id = write_chip_id_queue.pop_front(); + + if (active_command.cmd_type != DDR_CMD_TYPE_WRITE) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Expected WRITE command not in queue!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end + end + else begin + if (read_command_pipeline[0] || write_command_pipeline[0]) begin + $display("[%0t] [DWR=%0d%0d%0d]: Internal Error: Active command but read/write pipeline also active!", $time, MEM_DEPTH_IDX, MEM_WIDTH_IDX, MEM_RANK_IDX); + $stop(1); + end + end + end + + if (precharge_command_pipeline[0]) begin + precharge_command.cmd_type = precharge_command_queue.pop_front(); + precharge_command.bank = precharge_bank_queue.pop_front(); + precharge_command.bank_group = precharge_bank_group_queue.pop_front(); + precharge_command.chip_id = precharge_chip_id_queue.pop_front(); + cmd_precharge(precharge_command.chip_id, precharge_command.bank_group, precharge_command.bank, 1'b0); + end + + if (activate_command_pipeline[0]) begin + activate_command.cmd_type = activate_command_queue.pop_front(); + activate_command.address = activate_row_queue.pop_front(); + activate_command.bank = activate_bank_queue.pop_front(); + activate_command.bank_group = activate_bank_group_queue.pop_front(); + activate_command.chip_id = activate_chip_id_queue.pop_front(); + cmd_activate(activate_command.chip_id, activate_command.bank_group, activate_command.bank, activate_command.address); + end + + mem_dq_en = 1'b0; + mem_dqs_en = 1'b0; + mem_dqs_preamble_no_toggle = 1'b0; + mem_dqs_preamble_toggle = 1'b0; + mem_dqs_pod_pullup = 1'b0; + if (active_command.cmd_type == DDR_CMD_TYPE_WRITE) begin + integer mem_ck_dqs_diff; + integer dqs; + logic [PORT_MEM_DQ_WIDTH - 1:0] mem_dq_write; + #(MEM_DQS_TO_CLK_CAPTURE_DELAY); + mem_dq_write = '0; + for (dqs = 0; dqs < PORT_MEM_DQS_WIDTH; dqs = dqs + 1) begin + + if (mem_ck_time > mem_dqs_time[dqs]) begin + mem_ck_dqs_diff = -(mem_ck_time - mem_dqs_time[dqs]); + end + else begin + mem_ck_dqs_diff = mem_dqs_time[dqs] - mem_ck_time; + end + + if (mem_ck_dqs_diff >= -(MEM_CLK_TO_DQS_CAPTURE_DELAY)) begin + mem_dq_write = mem_dq_write | (mem_dq_captured & ({MEM_DQS_GROUP_SIZE{1'b1}} << (dqs*MEM_DQS_GROUP_SIZE))); + end + else begin + $display("[%0t] %s Write: mem_ck=%0t mem_dqs=%0t delta=%0d min=%0d", + $time, mem_ck_dqs_diff >= -(MEM_CLK_TO_DQS_CAPTURE_DELAY) ? "GOOD" : "BAD", + mem_ck_time, mem_dqs_time[dqs], mem_ck_dqs_diff, -(MEM_CLK_TO_DQS_CAPTURE_DELAY)); + mem_dq_write = mem_dq_write | ({MEM_DQS_GROUP_SIZE{1'bx}} << (dqs*MEM_DQS_GROUP_SIZE)); + end + + end + + write_memory(active_command, mem_dq_write, full_mask, full_dbi_n_in); + active_command.word_count = active_command.word_count+1; + end + else if (active_command.cmd_type == DDR_CMD_TYPE_READ) begin + if (rdbi_en) begin + read_memory(active_command, mem_dq_from_mem, dbi_n); + mem_dq_int = mem_dq_from_mem ^ ~full_dbi_n; + end else + read_memory(active_command, mem_dq_int, dbi_n); + mem_dq_en = 1'b1; + mem_dqs_en = 1'b1; + active_command.word_count = active_command.word_count+1; + end + + if (PROTOCOL_ENUM == "PROTOCOL_DDR4" && !read_preamble_training_mode) begin + if (!mem_dqs_en) begin + if ((read_preamble_2ck_mode && read_command_pipeline[5]) || (!read_preamble_2ck_mode && read_command_pipeline[3])) begin + mem_dqs_en = 1'b1; + mem_dqs_pod_pullup = 1'b1; + mem_dqs_preamble_no_toggle = 1'b0; + mem_dqs_preamble_toggle = 1'b0; + end else if (read_preamble_2ck_mode && (read_command_pipeline[4] || read_command_pipeline[3])) begin + mem_dqs_en = 1'b1; + mem_dqs_pod_pullup = 1'b0; + mem_dqs_preamble_no_toggle = 1'b1; + mem_dqs_preamble_toggle = 1'b0; + end else if (read_command_pipeline[2] || read_command_pipeline[1]) begin + mem_dqs_en = 1'b1; + mem_dqs_pod_pullup = 1'b0; + mem_dqs_preamble_no_toggle = 1'b0; + mem_dqs_preamble_toggle = 1'b1; + end + end + end else begin + if (!mem_dqs_en && (read_command_pipeline[2] | read_command_pipeline[1])) begin + mem_dqs_en = 1'b1; + mem_dqs_pod_pullup = 1'b0; + mem_dqs_preamble_no_toggle = 1'b1; + mem_dqs_preamble_toggle = 1'b0; + end + end + end + + int capture_ca_negedge = 0; + always @(posedge mem_ck_ca) begin + if (PROTOCOL_ENUM == "PROTOCOL_LPDDR3" && lpddr3_ca_training != CA_TRAINING_OFF && mem_cs_n == 1'b0) begin + if (lpddr3_ca_training == CA_TRAINING_MR41) begin + mem_dq_ca_map[0] <= mem_a[0]; + mem_dq_ca_map[2] <= mem_a[1]; + mem_dq_ca_map[4] <= mem_a[2]; + mem_dq_ca_map[6] <= mem_a[3]; + mem_dq_ca_map[8] <= mem_a[5]; + mem_dq_ca_map[10] <= mem_a[6]; + mem_dq_ca_map[12] <= mem_a[7]; + mem_dq_ca_map[14] <= mem_a[8]; + end else if (lpddr3_ca_training == CA_TRAINING_MR48) begin + mem_dq_ca_map[0] <= mem_a[4]; + mem_dq_ca_map[8] <= mem_a[9]; + end + + capture_ca_negedge = 1; + end + end + + always @(negedge mem_ck_ca) begin + if (capture_ca_negedge) begin + if (lpddr3_ca_training == CA_TRAINING_MR41) begin + mem_dq_ca_map[1] <= mem_a[0]; + mem_dq_ca_map[3] <= mem_a[1]; + mem_dq_ca_map[5] <= mem_a[2]; + mem_dq_ca_map[7] <= mem_a[3]; + mem_dq_ca_map[9] <= mem_a[5]; + mem_dq_ca_map[11] <= mem_a[6]; + mem_dq_ca_map[13] <= mem_a[7]; + mem_dq_ca_map[15] <= mem_a[8]; + end else if (lpddr3_ca_training == CA_TRAINING_MR48) begin + mem_dq_ca_map[1] <= mem_a[4]; + mem_dq_ca_map[9] <= mem_a[9]; + end + + capture_ca_negedge = 0; + end + end + + generate + genvar dm_count; + for (dm_count = 0; dm_count < PORT_MEM_DQS_WIDTH; dm_count = dm_count + 1) begin: dm_mapping + assign full_mask [(dm_count + 1) * MEM_DQS_GROUP_SIZE - 1 : dm_count * MEM_DQS_GROUP_SIZE] = {MEM_DQS_GROUP_SIZE{mem_dm_captured[dm_count]}}; + end + genvar dbi_n_count_in; + for (dbi_n_count_in = 0; dbi_n_count_in < PORT_MEM_DQS_WIDTH; dbi_n_count_in = dbi_n_count_in + 1) begin: dbi_n_mapping + assign full_dbi_n_in [(dbi_n_count_in + 1) * MEM_DQS_GROUP_SIZE - 1 : dbi_n_count_in * MEM_DQS_GROUP_SIZE] = {MEM_DQS_GROUP_SIZE{mem_dbi_n[dbi_n_count_in]}}; + end + endgenerate + + assign #1 mem_dqs_shifted = mem_dqs; + assign #1 mem_dqs_n_shifted = mem_dqs_n; + assign #2 mem_dqs_n_shifted_2 = mem_dqs_n; + + generate + genvar dqs; + for (dqs = 0; dqs < PORT_MEM_DQS_WIDTH; dqs = dqs + 1) begin + always @(posedge mem_dqs_shifted[dqs] or posedge mem_dqs_n_shifted[dqs]) begin + if (mem_dqs_shifted[dqs] === 1'b1 || mem_dqs_n_shifted[dqs] === 1'b1) begin + mem_dqs_time[dqs] <= $time; + mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= mem_dq[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE]; + + if (PROTOCOL_ENUM == "PROTOCOL_DDR4") begin + if (wdbi_en || dm_n_en) begin + mem_dm_captured[dqs] <= mem_dbi_n[dqs]; + end else begin + mem_dm_captured[dqs] <= 1'b1; + end + end else begin + if (PORT_MEM_DM_WIDTH == PORT_MEM_DQS_WIDTH) begin + mem_dm_captured[dqs] <= mem_dm[dqs]; + end else begin + mem_dm_captured[dqs] <= 1'b0; + end + end + + if (mem_dqs_n_shifted_2[dqs] === 'z || mem_dqs_n_shifted_2_prev[dqs] === 'z) begin + mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= 'z; + mem_dm_captured[dqs] <= 'z; + end + mem_dqs_n_shifted_2_prev[dqs] <= mem_dqs_n_shifted_2[dqs]; + end else begin + mem_dq_captured[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= 'x; + mem_dm_captured[dqs] <= 'x; + end + end + always @(posedge mem_dqs_shifted[dqs]) begin + mem_ck_sampled_by_dqs[((dqs+1)*MEM_DQS_GROUP_SIZE)-1:dqs*MEM_DQS_GROUP_SIZE] <= {MEM_DQS_GROUP_SIZE{mem_ck_diff}}; + end + end + endgenerate + + assign mem_dq = (lpddr3_ca_training == CA_TRAINING_OFF) ? (wlevel_en ? mem_ck_sampled_by_dqs : (mem_dq_en ? mem_dq_int : 'z)) : mem_dq_ca_map; + assign mem_dbi_n = rdbi_en ? (mem_dq_en ? dbi_n : 'z) : 'z; + assign mem_dqs = (!mem_dqs_en) ? 'z : + (mem_dqs_pod_pullup) ? '1 : + (mem_dqs_preamble_toggle) ? {PORT_MEM_DQS_WIDTH{mem_ck_diff}} : + (mem_dqs_preamble_no_toggle && read_preamble_training_mode) ? '0 : + (mem_dqs_preamble_no_toggle && PROTOCOL_ENUM == "PROTOCOL_DDR4") ? '1 : + (mem_dqs_preamble_no_toggle && PROTOCOL_ENUM != "PROTOCOL_DDR4") ? '0 : + {PORT_MEM_DQS_WIDTH{mem_ck_diff}}; + assign mem_dqs_n = (!mem_dqs_en) ? 'z : + (mem_dqs_pod_pullup) ? '1 : + (mem_dqs_preamble_toggle) ? {PORT_MEM_DQS_WIDTH{~mem_ck_diff}} : + (mem_dqs_preamble_no_toggle && read_preamble_training_mode) ? '1 : + (mem_dqs_preamble_no_toggle && PROTOCOL_ENUM == "PROTOCOL_DDR4") ? '0 : + (mem_dqs_preamble_no_toggle && PROTOCOL_ENUM != "PROTOCOL_DDR4") ? '1 : + {PORT_MEM_DQS_WIDTH{~mem_ck_diff}}; + + assign mem_alert_n = parity_alert_n_pipeline[0]; + +// synthesis translate_on + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_merlin_master_translator.sv b/ase/rtl/device_models/dcp_emif_model/altera_merlin_master_translator.sv new file mode 100644 index 000000000000..6348e0846cc0 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_merlin_master_translator.sv @@ -0,0 +1,571 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/rel/17.0/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts an Avalon-MM master interface into an +// Avalon-MM "universal" master interface. +// +// The universal interface is defined as the superset of ports +// and parameters that can represent any legal Avalon +// interface. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_translator #( + parameter + // widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + + // optional ports + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + USE_WRITERESPONSE = 0, + USE_READRESPONSE = 0, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + // must be enabled for a bursting master + AV_CONSTANT_BURST_BEHAVIOR = 1, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0 +)( + input wire clk, + input wire reset, + + // Universal Avalon Master + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + input wire [1 : 0] uav_response, + input wire uav_writeresponsevalid, + + // Avalon-MM Anti-master (slave) + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest, + output reg [1 : 0] av_response, + output reg av_writeresponsevalid +); + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD); + localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD)); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0; + localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1; + localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1; + + localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW); + localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW); + + function integer flog2; + input [31:0] depth; + integer i; + begin + i = depth; + if ( i <= 0 ) flog2 = 0; + else begin + for (flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + endfunction // flog2 + + // ------------------------------------------------------------ + // Calculates the ceil(log2()) of the input val. + // + // Limited to a positive 32-bit input value. + // ------------------------------------------------------------ + function integer clog2; + input[31:0] val; + reg[31:0] i; + + begin + i = 1; + clog2 = 0; + + while (i < val) begin + clog2 = clog2 + 1; + i = i[30:0] << 1; + end + end + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2 = 1; + pow2 = pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // + // The symbols per word calculation here rounds non-power of two + // symbols to the next highest power of two, which is what we want + // when calculating the decrementing byte count. + // ------------------------------------------------- + wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0])); + wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0]; + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W -1 : 0] uav_address_pre; + reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount_pre; + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + // ------------------------------------------------- + // Pass through signals that we don't touch + // ------------------------------------------------- + assign uav_writedata = av_writedata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + assign av_readdata = uav_readdata; + assign av_readdatavalid = uav_readdatavalid; + + // ------------------------------------------------- + // Response signals + // ------------------------------------------------- + always_comb begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) + av_response = '0; + else + av_response = uav_response; + + if (USE_WRITERESPONSE) begin + av_writeresponsevalid = uav_writeresponsevalid; + end else begin + av_writeresponsevalid = '0; + end + end + + // ------------------------------------------------- + // Convert byte and word addresses into byte addresses + // ------------------------------------------------- + always_comb begin + uav_address_pre = {UAV_ADDRESS_W{1'b0}}; + + if (AV_ADDRESS_SYMBOLS) + uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0]; + else begin + uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0]; + end + end + + // ------------------------------------------------- + // Convert burstcount into symbol units + // ------------------------------------------------- + always_comb begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if (USE_BURSTCOUNT) begin + uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}}; + if (AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0]; + else begin + uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0]; + end + end + end + + // ------------------------------------------------- + // This is where we perform the per-transfer address and burstcount + // calculations that are required by downstream modules. + // ------------------------------------------------- + reg [UAV_ADDRESS_W -1 : 0] address_register; + wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register; + reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint; + + assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0]; + + always_comb begin + uav_address = uav_address_pre; + uav_burstcount = uav_burstcount_pre; + + if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address = address_register; + uav_burstcount = burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg; + + generate + if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin + if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0]; + assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0]; + end + endgenerate + + always @(posedge clk, posedge reset) begin + if (reset) begin + address_register <= '0; + burstcount_register_lint <= '0; + end else begin + address_register <= address_register; + burstcount_register_lint <= burstcount_register_lint; + + if (internal_beginbursttransfer || first_burst_stalled) begin + if (av_waitrequest) begin + address_register <= uav_address_pre; + burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre; + end else begin + address_register <= combi_burst_addr_reg; + burstcount_register_lint <= uav_burstcount_pre - symbols_per_word; + end + end else if (internal_begintransfer || burst_stalled) begin + if (~av_waitrequest) begin + address_register <= combi_addr_reg; + burstcount_register_lint <= burstcount_register - symbols_per_word; + end + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end else begin + if (internal_beginbursttransfer || first_burst_stalled) begin + if (av_waitrequest) begin + first_burst_stalled <= 1'b1; + end else begin + first_burst_stalled <= 1'b0; + end + end else if (internal_begintransfer || burst_stalled) begin + if (~av_waitrequest) begin + burst_stalled <= 1'b0; + end else begin + burst_stalled <= 1'b1; + end + end + end + end + + // ------------------------------------------------- + // Waitrequest translation + // ------------------------------------------------- + always @(posedge clk, posedge reset) begin + if (reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + if (read_accepted == 0) + read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + else if (read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always @(posedge clk, posedge reset) begin + if (reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always_comb begin + av_waitrequest = uav_waitrequest; + + if (USE_READDATAVALID == 0) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if (USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + // ------------------------------------------------- + // Determine the output read and write signals from + // the read/write/chipselect input signals. + // ------------------------------------------------- + always_comb begin + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if (!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre = av_read; + end + + if (USE_WRITE) begin + uav_write_pre = av_write; + end + end else begin + if (!USE_WRITE && USE_READ) begin + uav_write_pre = av_chipselect & ~av_read; + uav_read_pre = av_read; + end else if (!USE_READ && USE_WRITE) begin + uav_write_pre = av_write; + uav_read_pre = av_chipselect & ~av_write; + end else if (USE_READ && USE_WRITE) begin + uav_write_pre = av_write; + uav_read_pre = av_read; + end + end + + if (USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if (AV_REGISTERINCOMINGSIGNALS == 0) + uav_write = uav_write_pre; + else + uav_write = uav_write_pre & ~write_accepted; + end + + // ------------------------------------------------- + // Begintransfer assignment + // ------------------------------------------------- + reg end_begintransfer; + + always_comb begin + if (USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + end_begintransfer <= 1'b0; + end else begin + if (internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if (uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + end + end + + // ------------------------------------------------- + // Beginbursttransfer assignment + // ------------------------------------------------- + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always_comb begin + if (USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + end_beginbursttransfer <= 1'b0; + end else begin + end_beginbursttransfer <= end_beginbursttransfer; + if (last_burst_transfer && internal_begintransfer || uav_read) begin + end_beginbursttransfer <= 1'b0; + end + else if (uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + end + + // synthesis translate_off + + // ------------------------------------------------ + // check_1 : for waitrequest signal violation + // Ensure that when waitreqeust is asserted, the master is not allowed to change its controls + // Exception : begintransfer / beginbursttransfer + // : previously not in any transaction (idle) + // Note : Not checking clken which is not exactly part of Avalon controls/inputs + // : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE + // ------------------------------------------------ + + reg av_waitrequest_r; + reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r; + reg [AV_ADDRESS_W-1:0] av_address_r; + reg [AV_BYTEENABLE_W-1:0] av_byteenable_r; + reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r; + reg [AV_DATA_W-1:0] av_writedata_r; + + always @(posedge clk or posedge reset) begin + if (reset) begin + av_waitrequest_r <= '0; + av_write_r <= '0; + av_read_r <= '0; + av_lock_r <= '0; + av_chipselect_r <= '0; + av_debugaccess_r <= '0; + av_address_r <= '0; + av_byteenable_r <= '0; + av_burstcount_r <= '0; + av_writedata_r <= '0; + end else begin + av_waitrequest_r <= av_waitrequest; + av_write_r <= av_write; + av_read_r <= av_read; + av_lock_r <= av_lock; + av_chipselect_r <= av_chipselect; + av_debugaccess_r <= av_debugaccess; + av_address_r <= av_address; + av_byteenable_r <= av_byteenable; + av_burstcount_r <= av_burstcount; + av_writedata_r <= av_writedata; + + if ( + av_waitrequest_r && // When waitrequest is asserted + ( + (av_write != av_write_r) || // Checks that : Input controls/data does not change + (av_read != av_read_r) || + (av_lock != av_lock_r) || + (av_debugaccess != av_debugaccess_r) || + (av_address != av_address_r) || + (av_byteenable != av_byteenable_r) || + (av_burstcount != av_burstcount_r) + ) && + (av_write_r | av_read_r) && // Check only when : previously initiated a write/read + (!USE_CHIPSELECT | av_chipselect_r) // and chipselect was asserted (or unused) + ) begin + $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time()); + $display("av_address %x --> %x", av_address_r , av_address ); + $display("av_byteenable %x --> %x", av_byteenable_r , av_byteenable ); + $display("av_burstcount %x --> %x", av_burstcount_r , av_burstcount ); + $display("av_writedata %x --> %x", av_writedata_r , av_writedata ); + $display("av_write %x --> %x", av_write_r , av_write ); + $display("av_read %x --> %x", av_read_r , av_read ); + $display("av_lock %x --> %x", av_lock_r , av_lock ); + $display("av_chipselect %x --> %x", av_chipselect_r , av_chipselect ); + $display("av_debugaccess %x --> %x", av_debugaccess_r , av_debugaccess ); + end + end + + // end check_1 + + end + + // synthesis translate_on + + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_merlin_slave_translator.sv b/ase/rtl/device_models/dcp_emif_model/altera_merlin_slave_translator.sv new file mode 100644 index 000000000000..c694c402d310 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_merlin_slave_translator.sv @@ -0,0 +1,497 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +// $Id: //acds/rel/17.0/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + USE_READRESPONSE = 0, + USE_WRITERESPONSE = 0, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 +) ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic [UAV_DATA_W - 1 : 0] uav_readdata, + output logic [1:0] uav_response, + // input wire uav_writeresponserequest, + output logic uav_writeresponsevalid, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest, + + input logic [1:0] av_response, + // output logic av_writeresponserequest, + input wire av_writeresponsevalid + +); + + function integer clog2_plusone; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1) + i = i >> 1; + end + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + + reg [1 : 0] av_response_delayed; + + always @(posedge clk, posedge reset) begin + if (reset) begin + av_response_delayed <= 2'b0; + end else begin + av_response_delayed <= av_response; + end + end + + always_comb + begin + if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin + uav_response = '0; + end else begin + if (AV_READLATENCY != 0 || USE_READDATAVALID) begin + uav_response = av_response; + end else begin + uav_response = av_response_delayed; + end + end + end + // assign av_writeresponserequest = uav_writeresponserequest; + assign uav_writeresponsevalid = av_writeresponsevalid; + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + end + end + end + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end else begin + waitrequest_reset_override <= 1'h0; + wait_latency_counter <= '0; + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + else if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + end + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = {UAV_DATA_W{1'b0}}; + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata[AV_DATA_W-1:0] = av_readdata; + end else begin + uav_readdata[AV_DATA_W-1:0] = av_readdata_pre; + end + end + + // ------------------- + // Readdatavalid Assigment + // ------------------- + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + always@* begin + uav_readdatavalid=top_read_latency_shift_reg; + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + end + + always@* begin + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + end + + always@(posedge reset, posedge clk) begin + if (reset) begin + read_latency_shift_reg <= '0; + end else if (av_clken) begin + read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + end + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end else begin + av_chipselect_pre <= 1'b0; + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_begintransfer <= 1'b0; + end else begin + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + end + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + reg end_beginbursttransfer; + reg in_transfer; + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end else begin + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + end + end + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_oct.sv b/ase/rtl/device_models/dcp_emif_model/altera_oct.sv new file mode 100644 index 000000000000..6430dd704a6a --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_oct.sv @@ -0,0 +1,238 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +`timescale 1 ps / 1 ps + +module altera_oct( + rzqin, + calibration_request, + clock, + reset, + calibration_shift_busy, + calibration_busy, + s2pload_ena, + s2pload_rdy, + oct_0_series_termination_control, + oct_0_parallel_termination_control, + oct_1_series_termination_control, + oct_1_parallel_termination_control, + oct_2_series_termination_control, + oct_2_parallel_termination_control, + oct_3_series_termination_control, + oct_3_parallel_termination_control, + oct_4_series_termination_control, + oct_4_parallel_termination_control, + oct_5_series_termination_control, + oct_5_parallel_termination_control, + oct_6_series_termination_control, + oct_6_parallel_termination_control, + oct_7_series_termination_control, + oct_7_parallel_termination_control, + oct_8_series_termination_control, + oct_8_parallel_termination_control, + oct_9_series_termination_control, + oct_9_parallel_termination_control, + oct_10_series_termination_control, + oct_10_parallel_termination_control, + oct_11_series_termination_control, + oct_11_parallel_termination_control +); + +parameter OCT_CAL_NUM = 1; +parameter OCT_USER_MODE = "A_OCT_USER_OCT_OFF"; +parameter OCT_CKBUF_MODE = "false"; +parameter OCT_S2P_HANDSHAKE = "false"; + +parameter OCT_CAL_MODE_DER_0 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_1 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_2 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_3 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_4 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_5 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_6 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_7 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_8 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_9 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_10 = "A_OCT_CAL_MODE_SINGLE"; +parameter OCT_CAL_MODE_DER_11 = "A_OCT_CAL_MODE_SINGLE"; + +localparam string OCT_CAL_MODE_S[0:11] ='{ OCT_CAL_MODE_DER_0, + OCT_CAL_MODE_DER_1 , + OCT_CAL_MODE_DER_2 , + OCT_CAL_MODE_DER_3 , + OCT_CAL_MODE_DER_4 , + OCT_CAL_MODE_DER_5 , + OCT_CAL_MODE_DER_6 , + OCT_CAL_MODE_DER_7 , + OCT_CAL_MODE_DER_8 , + OCT_CAL_MODE_DER_9 , + OCT_CAL_MODE_DER_10 , + OCT_CAL_MODE_DER_11 }; + +input [OCT_CAL_NUM-1:0] rzqin; +input [OCT_CAL_NUM-1:0] calibration_request; +input clock; +input reset; +input s2pload_ena; + +output [OCT_CAL_NUM-1:0] calibration_shift_busy; +output [OCT_CAL_NUM-1:0] calibration_busy; + +output [15:0] oct_0_series_termination_control; +output [15:0] oct_0_parallel_termination_control; +output [15:0] oct_1_series_termination_control; +output [15:0] oct_1_parallel_termination_control; +output [15:0] oct_2_series_termination_control; +output [15:0] oct_2_parallel_termination_control; +output [15:0] oct_3_series_termination_control; +output [15:0] oct_3_parallel_termination_control; +output [15:0] oct_4_series_termination_control; +output [15:0] oct_4_parallel_termination_control; +output [15:0] oct_5_series_termination_control; +output [15:0] oct_5_parallel_termination_control; +output [15:0] oct_6_series_termination_control; +output [15:0] oct_6_parallel_termination_control; +output [15:0] oct_7_series_termination_control; +output [15:0] oct_7_parallel_termination_control; +output [15:0] oct_8_series_termination_control; +output [15:0] oct_8_parallel_termination_control; +output [15:0] oct_9_series_termination_control; +output [15:0] oct_9_parallel_termination_control; +output [15:0] oct_10_series_termination_control; +output [15:0] oct_10_parallel_termination_control; +output [15:0] oct_11_series_termination_control; +output [15:0] oct_11_parallel_termination_control; +output s2pload_rdy; + +wire [191 : 0] series_termination_control; +wire [191 : 0] parallel_termination_control; + +wire [OCT_CAL_NUM-1:0] enserusr; +wire nclrusr; +wire clkenusr; +wire clkusr; +wire [OCT_CAL_NUM-1:0] ser_data; +wire [OCT_CAL_NUM-1:0] s2pload_w; + +assign oct_0_series_termination_control = series_termination_control[15:0]; +assign oct_0_parallel_termination_control = parallel_termination_control[15:0]; +assign oct_1_series_termination_control = series_termination_control[31:16]; +assign oct_1_parallel_termination_control = parallel_termination_control[31:16]; +assign oct_2_series_termination_control = series_termination_control[47:32]; +assign oct_2_parallel_termination_control = parallel_termination_control[47:32]; +assign oct_3_series_termination_control = series_termination_control[63:48]; +assign oct_3_parallel_termination_control = parallel_termination_control[63:48]; +assign oct_4_series_termination_control = series_termination_control[79:64]; +assign oct_4_parallel_termination_control = parallel_termination_control[79:64]; +assign oct_5_series_termination_control = series_termination_control[95:80]; +assign oct_5_parallel_termination_control = parallel_termination_control[95:80]; +assign oct_6_series_termination_control = series_termination_control[111:96]; +assign oct_6_parallel_termination_control = parallel_termination_control[111:96]; +assign oct_7_series_termination_control = series_termination_control[127:112]; +assign oct_7_parallel_termination_control = parallel_termination_control[127:112]; +assign oct_8_series_termination_control = series_termination_control[143:128]; +assign oct_8_parallel_termination_control = parallel_termination_control[143:128]; +assign oct_9_series_termination_control = series_termination_control[159:144]; +assign oct_9_parallel_termination_control = parallel_termination_control[159:144]; +assign oct_10_series_termination_control = series_termination_control[175:160]; +assign oct_10_parallel_termination_control = parallel_termination_control[175:160]; +assign oct_11_series_termination_control = series_termination_control[191:176]; +assign oct_11_parallel_termination_control = parallel_termination_control[191:176]; + + +genvar i; +generate +begin : gpio_one_bit + for(i = 0 ; i < OCT_CAL_NUM ; i = i + 1) begin : oct_i_loop + + localparam OCT_CAL_MODE = (OCT_CAL_MODE_S[i] == "A_OCT_CAL_MODE_SINGLE") ? "A_OCT_CAL_MODE_SINGLE" : + (OCT_CAL_MODE_S[i] == "A_OCT_CAL_MODE_DOUBLE") ? "A_OCT_CAL_MODE_DOUBLE" : + (OCT_CAL_MODE_S[i] == "A_OCT_CAL_MODE_AUTO") ? "A_OCT_CAL_MODE_AUTO" : + "A_OCT_CAL_MODE_POD"; + + twentynm_termination #( + .a_oct_cal_mode(OCT_CAL_MODE), + .a_oct_user_oct(OCT_USER_MODE) + ) sd1a_i ( + .rzqin(rzqin[i]), + .enserusr(enserusr[i]), + .nclrusr(nclrusr), + .clkenusr(clkenusr), + .clkusr(clkusr), + .serdataout(ser_data[i]) + ); + + twentynm_termination_logic sd2a_i + ( + .parallelterminationcontrol(parallel_termination_control[15+16*i:i*16]), + .s2pload(s2pload_w[i]), + .serdata(ser_data[i]), + .seriesterminationcontrol(series_termination_control[15+16*i:i*16]) + ); + + end + + if (OCT_CAL_NUM < 12) + begin : gen_term_ctrl_tieoff + assign series_termination_control[191:(OCT_CAL_NUM*16)] = '0; + assign parallel_termination_control[191:(OCT_CAL_NUM*16)] = '0; + end +end +endgenerate + +generate +if (OCT_USER_MODE == "A_OCT_USER_OCT_ON") begin + altera_oct_um_fsm #( + .OCT_CKBUF_MODE(OCT_CKBUF_MODE), + .OCT_CAL_NUM(OCT_CAL_NUM), + .OCT_S2P_HANDSHAKE(OCT_S2P_HANDSHAKE) + ) altera_oct_um_fsm_i ( + .calibration_request(calibration_request), + .clock(clock), + .reset(reset), + .calibration_shift_busy(calibration_shift_busy), + .calibration_busy(calibration_busy), + .s2pload_rdy(s2pload_rdy), + .s2pload_ena(s2pload_ena), + .enserusr(enserusr), + .nclrusr(nclrusr), + .clkenusr(clkenusr), + .clkusr(clkusr), + .s2pload(s2pload_w) +); + +end else begin + assign calibration_shift_busy = {OCT_CAL_NUM{1'b0}}; + assign calibration_busy = {OCT_CAL_NUM{1'b0}}; + assign s2pload_rdy = 1'b1; +end +endgenerate + + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_oct_um_fsm.sv b/ase/rtl/device_models/dcp_emif_model/altera_oct_um_fsm.sv new file mode 100644 index 000000000000..9a438daafe62 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_oct_um_fsm.sv @@ -0,0 +1,311 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +`timescale 1 ps / 1 ps + +module altera_oct_um_fsm( + calibration_request, + clock, + reset, + calibration_shift_busy, + calibration_busy, + enserusr, + nclrusr, + clkenusr, + clkusr, + s2pload, + s2pload_ena, + s2pload_rdy +); + +parameter OCT_CAL_NUM = 1; +parameter OCT_CKBUF_MODE = "false"; +parameter OCT_S2P_HANDSHAKE = "false"; + +input [OCT_CAL_NUM-1:0] calibration_request; +input clock; +input reset; +input s2pload_ena; + +output reg [OCT_CAL_NUM-1:0] calibration_shift_busy; +output reg [OCT_CAL_NUM-1:0] calibration_busy; + +output reg [OCT_CAL_NUM-1:0] enserusr; +output reg nclrusr; +output reg clkenusr; +output clkusr; +output reg [OCT_CAL_NUM-1:0] s2pload; +output reg s2pload_rdy; + +typedef enum { + OCT_IDLE, + OCT_RESET, + OCT_CALIBRATION, + OCT_CALIBRATION_DONE, + OCT_READY_FOR_SERIAL_SHIFT, + OCT_SERIAL_SHIFT_SETUP, + OCT_SERIAL_SHIFT, + OCT_S2P_ASSERT, + OCT_SERIAL_SHIFT_DONE, + OCT_SERIAL_SHIFT_HOLD +} FSM_STATES; + +FSM_STATES state; + +reg [OCT_CAL_NUM-1:0] calibration_request_snapshot; +reg [11:0] calibration_counter; +reg [6:0] serial_shift_counter; +reg [3:0] oct_block_shifting; +reg [OCT_CAL_NUM-1:0] oct_block_shifting_decode; +reg [4:0] serial_shift_setup_counter; +reg [4:0] serial_shift_hold_counter; + +localparam SERIAL_SHIFT_SETUP_CYCLES = 4'h4; +localparam SERIAL_SHIFT_HOLD_CYCLES = 4'h4; +localparam CALIBRATION_CYCLES = 12'h7D0; +localparam SERIAL_SHIFT_CYCLES = 6'h20; + +wire calibration_done = (calibration_counter == CALIBRATION_CYCLES); +wire shifting_done = (serial_shift_counter == SERIAL_SHIFT_CYCLES); +wire oct_block_shifting_done = (oct_block_shifting == OCT_CAL_NUM); +wire serial_shift_setup_done = (serial_shift_setup_counter == SERIAL_SHIFT_SETUP_CYCLES); +wire serial_shift_hold_done_int = (serial_shift_hold_counter == SERIAL_SHIFT_HOLD_CYCLES); +wire serial_shift_hold_done = ((OCT_S2P_HANDSHAKE == "true") ? (serial_shift_hold_done_int & s2pload_ena) : serial_shift_hold_done_int); +wire clk; + +wire [OCT_CAL_NUM-1:0] calibration_shift_busy_w; +wire [OCT_CAL_NUM-1:0] calibration_busy_w; +wire [OCT_CAL_NUM-1:0] enserusr_w; +wire nclrusr_w; +wire clkenusr_w; +wire [OCT_CAL_NUM-1:0] s2pload_w; + + +assign nclrusr_w = ~(state == OCT_RESET); +assign clkenusr_w = ( + (state == OCT_RESET) | + (state == OCT_CALIBRATION) | + (state == OCT_CALIBRATION_DONE) +); +assign calibration_busy_w = (state == OCT_CALIBRATION) ? calibration_request_snapshot : {OCT_CAL_NUM{1'b0}}; +assign calibration_shift_busy_w = ( + state == OCT_CALIBRATION || + state == OCT_CALIBRATION_DONE || + state == OCT_READY_FOR_SERIAL_SHIFT || + state == OCT_SERIAL_SHIFT_SETUP || + state == OCT_SERIAL_SHIFT || + state == OCT_S2P_ASSERT || + state == OCT_SERIAL_SHIFT_DONE || + state == OCT_SERIAL_SHIFT_HOLD) ? calibration_request_snapshot : {OCT_CAL_NUM{1'b0}}; +assign s2pload_w = (state == OCT_S2P_ASSERT) ? (calibration_request_snapshot & oct_block_shifting_decode) : {OCT_CAL_NUM{1'b0}}; + +integer i; +always @(*) begin + oct_block_shifting_decode <= {OCT_CAL_NUM{1'b0}}; + + for (i = 0; i < OCT_CAL_NUM; i = i + 1) begin + oct_block_shifting_decode[i] <= ((oct_block_shifting == i) ? 1'b1 : 1'b0); + end +end + +always @(posedge clk or posedge reset) begin + if(reset) begin + state <= OCT_IDLE; + calibration_request_snapshot <= {OCT_CAL_NUM{1'b0}}; + calibration_counter <= 12'h000; + oct_block_shifting <= 4'h0; + serial_shift_counter <= 6'h00; + serial_shift_setup_counter <= 4'h0; + serial_shift_hold_counter <= 4'h0; + end + else begin + case(state) + OCT_IDLE: begin + if(|calibration_request) begin + state <= OCT_RESET; + calibration_request_snapshot <= calibration_request; + end + end + OCT_RESET: begin + state <= OCT_CALIBRATION; + calibration_counter <= 12'h000; + oct_block_shifting <= 4'h0; + serial_shift_counter <= 6'h00; + end + OCT_CALIBRATION: begin + if(calibration_done) begin + state <= OCT_CALIBRATION_DONE; + end + else begin + calibration_counter <= calibration_counter + 1'b1; + end + end + OCT_CALIBRATION_DONE: begin + state <= OCT_READY_FOR_SERIAL_SHIFT; + oct_block_shifting <= 4'h0; + end + OCT_READY_FOR_SERIAL_SHIFT: begin + state <= OCT_SERIAL_SHIFT_SETUP; + serial_shift_counter <= 6'h00; + serial_shift_setup_counter <= 4'h0; + end + OCT_SERIAL_SHIFT_SETUP:begin + if(serial_shift_setup_done) begin + state <= OCT_SERIAL_SHIFT; + end + else begin + serial_shift_setup_counter <= serial_shift_setup_counter + 1'b1; + end + end + OCT_SERIAL_SHIFT: begin + if(shifting_done) begin + state <= OCT_SERIAL_SHIFT_HOLD; + serial_shift_hold_counter <= 4'h0; + end + else begin + serial_shift_counter <= serial_shift_counter + 1'b1; + end + end + OCT_SERIAL_SHIFT_HOLD: begin + if(serial_shift_hold_done) begin + state <= OCT_S2P_ASSERT; + end + else if (serial_shift_hold_done_int == 1'b0) begin + serial_shift_hold_counter <= serial_shift_hold_counter + 1'b1; + end + end + OCT_S2P_ASSERT: begin + state <= OCT_SERIAL_SHIFT_DONE; + oct_block_shifting <= oct_block_shifting + 1'b1; + end + OCT_SERIAL_SHIFT_DONE: begin + if(oct_block_shifting_done) begin + state <= OCT_IDLE; + end + else begin + state <= OCT_SERIAL_SHIFT_SETUP; + serial_shift_counter <= 6'h00; + serial_shift_setup_counter <= 4'h0; + end + end + endcase; + end +end + +always @(posedge clk) begin + s2pload_rdy <= ((state == OCT_SERIAL_SHIFT_HOLD) ? 1'b1 : 1'b0); +end + +assign enserusr_w = + (state == OCT_CALIBRATION) ? calibration_request_snapshot : + (state == OCT_SERIAL_SHIFT_SETUP || + state == OCT_SERIAL_SHIFT || + state == OCT_SERIAL_SHIFT_HOLD || + state == OCT_S2P_ASSERT || + state == OCT_SERIAL_SHIFT_DONE) ? (calibration_request_snapshot & oct_block_shifting_decode) : + {OCT_CAL_NUM{1'b0}}; + +wire clock_enable = + state == OCT_IDLE || + state == OCT_RESET || + state == OCT_CALIBRATION || + state == OCT_CALIBRATION_DONE || + state == OCT_SERIAL_SHIFT; + +generate + +if (OCT_CKBUF_MODE == "true") begin + reg cken_w; + always @(negedge clock) begin + cken_w <= clock_enable; + end + twentynm_clkena #( + .clock_type("GLOBAL CLOCK"), + .ena_register_mode("falling edge") + ) clkena ( + .inclk(clock), + .ena(cken_w), + .outclk(clkusr) + ); + + assign clk = clock; + + reg ff /* synthesis noprune */; + always @(posedge clkusr) ff <= ~ff; + + always @(posedge clk) + begin + calibration_shift_busy <= calibration_shift_busy_w; + calibration_busy <= calibration_busy_w; + enserusr <= enserusr_w; + nclrusr <= nclrusr_w; + clkenusr <= clkenusr_w; + s2pload <= s2pload_w; + end + +end else begin + + reg clkusr_out; + reg div_clk; + + always @(posedge clock or posedge reset) begin : CLKUSR_GEN + if(reset) begin + clkusr_out <= 1'b0; + end + else if(clock_enable) begin + clkusr_out <= ~clkusr_out; + end + end + + always @(negedge clock or posedge reset) begin : FSM_CLK_GEN + if(reset) begin + div_clk <= 1'b0; + end + else begin + div_clk <= ~div_clk; + end + end + + assign clk = div_clk; + assign clkusr = clkusr_out; + + always @(*) + begin + calibration_shift_busy <= calibration_shift_busy_w; + calibration_busy <= calibration_busy_w; + enserusr <= enserusr_w; + nclrusr <= nclrusr_w; + clkenusr <= clkenusr_w; + s2pload <= s2pload_w; + end + +end +endgenerate + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_reset_controller.v b/ase/rtl/device_models/dcp_emif_model/altera_reset_controller.v new file mode 100644 index 000000000000..5361dee467f0 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_reset_controller.v @@ -0,0 +1,321 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/rel/17.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter USE_RESET_REQUEST_IN0 = 0, + parameter USE_RESET_REQUEST_IN1 = 0, + parameter USE_RESET_REQUEST_IN2 = 0, + parameter USE_RESET_REQUEST_IN3 = 0, + parameter USE_RESET_REQUEST_IN4 = 0, + parameter USE_RESET_REQUEST_IN5 = 0, + parameter USE_RESET_REQUEST_IN6 = 0, + parameter USE_RESET_REQUEST_IN7 = 0, + parameter USE_RESET_REQUEST_IN8 = 0, + parameter USE_RESET_REQUEST_IN9 = 0, + parameter USE_RESET_REQUEST_IN10 = 0, + parameter USE_RESET_REQUEST_IN11 = 0, + parameter USE_RESET_REQUEST_IN12 = 0, + parameter USE_RESET_REQUEST_IN13 = 0, + parameter USE_RESET_REQUEST_IN14 = 0, + parameter USE_RESET_REQUEST_IN15 = 0, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0, + parameter RESET_REQ_WAIT_TIME = 3, + parameter MIN_RST_ASSERTION_TIME = 11, + parameter RESET_REQ_EARLY_DSRT_TIME = 4, + parameter ADAPT_RESET_REQUEST = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + input reset_req_in0, + input reset_req_in1, + input reset_req_in2, + input reset_req_in3, + input reset_req_in4, + input reset_req_in5, + input reset_req_in6, + input reset_req_in7, + input reset_req_in8, + input reset_req_in9, + input reset_req_in10, + input reset_req_in11, + input reset_req_in12, + input reset_req_in13, + input reset_req_in14, + input reset_req_in15, + + + input clk, + output reg reset_out, + output reg reset_req +); + + // Always use async reset synchronizer if reset_req is used + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + // -------------------------------------- + // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 + // -------------------------------------- + localparam MIN_METASTABLE = 3; + localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; + + localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; + + localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? + MIN_RST_ASSERTION_TIME + 1 : + ( + (MIN_RST_ASSERTION_TIME > LARGER)? + MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : + MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 + ); + + localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; + // -------------------------------------- + + wire merged_reset; + wire merged_reset_req_in; + wire reset_out_pre; + wire reset_req_pre; + + // Registers and Interconnect + (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; + reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + assign merged_reset_req_in = ( + ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | + ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | + ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | + ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | + ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | + ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | + ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | + ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | + ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | + ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | + ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | + ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | + ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | + ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | + ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | + ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) + ); + + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin + + assign reset_out_pre = merged_reset; + assign reset_req_pre = merged_reset_req_in; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(0) + ) + alt_rst_req_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset_req_in), + .reset_out (reset_req_pre) + ); + + end + endgenerate + + generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| + ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin + always @* begin + reset_out = reset_out_pre; + reset_req = reset_req_pre; + end + end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin + + wire reset_out_pre2; + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH+1), + .ASYNC_RESET(0) + ) + alt_rst_sync_uq2 + ( + .clk (clk), + .reset_in (reset_out_pre), + .reset_out (reset_out_pre2) + ); + + always @* begin + reset_out = reset_out_pre2; + reset_req = reset_req_pre; + end + + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= + {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; + end + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + + always @(posedge clk) + begin + case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/altera_reset_synchronizer.v b/ase/rtl/device_models/dcp_emif_model/altera_reset_synchronizer.v new file mode 100644 index 000000000000..8915cf658516 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_reset_synchronizer.v @@ -0,0 +1,102 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/rel/17.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/altera_std_synchronizer_nocut.v b/ase/rtl/device_models/dcp_emif_model/altera_std_synchronizer_nocut.v new file mode 100644 index 000000000000..34e78fc4a060 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/altera_std_synchronizer_nocut.v @@ -0,0 +1,210 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $ +// $Revision: #8 $ +// $Date: 2009/02/18 $ +// $Author: pscheidt $ +//----------------------------------------------------------------------------- +// +// File: altera_std_synchronizer_nocut.v +// +// Abstract: Single bit clock domain crossing synchronizer. Exactly the same +// as altera_std_synchronizer.v, except that the embedded false +// path constraint is removed in this module. If you use this +// module, you will have to apply the appropriate timing +// constraints. +// +// We expect to make this a standard Quartus atom eventually. +// +// Composed of two or more flip flops connected in series. +// Random metastable condition is simulated when the +// __ALTERA_STD__METASTABLE_SIM macro is defined. +// Use +define+__ALTERA_STD__METASTABLE_SIM argument +// on the Verilog simulator compiler command line to +// enable this mode. In addition, define the macro +// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output +// with every metastable event generated in the synchronizer. +// +// Copyright (C) Altera Corporation 2009, All Rights Reserved +//----------------------------------------------------------------------------- + +`timescale 1ns / 1ns + +module altera_std_synchronizer_nocut ( + clk, + reset_n, + din, + dout + ); + + parameter depth = 3; // This value must be >= 2 ! + parameter rst_value = 0; + + input clk; + input reset_n; + input din; + output dout; + + // QuartusII synthesis directives: + // 1. Preserve all registers ie. do not touch them. + // 2. Do not merge other flip-flops with synchronizer flip-flops. + // QuartusII TimeQuest directives: + // 1. Identify all flip-flops in this module as members of the synchronizer + // to enable automatic metastability MTBF analysis. + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1; + + (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg; + + //synthesis translate_off + initial begin + if (depth <2) begin + $display("%m: Error: synchronizer length: %0d less than 2.", depth); + end + end + + // the first synchronizer register is either a simple D flop for synthesis + // and non-metastable simulation or a D flop with a method to inject random + // metastable events resulting in random delay of [0,1] cycles + +`ifdef __ALTERA_STD__METASTABLE_SIM + + reg[31:0] RANDOM_SEED = 123456; + wire next_din_s1; + wire dout; + reg din_last; + reg random; + event metastable_event; // hook for debug monitoring + + initial begin + $display("%m: Info: Metastable event injection simulation mode enabled"); + end + + always @(posedge clk) begin + if (reset_n == 0) + random <= $random(RANDOM_SEED); + else + random <= $random; + end + + assign next_din_s1 = (din_last ^ din) ? random : din; + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_last <= (rst_value == 0)? 1'b0 : 1'b1; + else + din_last <= din; + end + + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= (rst_value == 0)? 1'b0 : 1'b1; + else + din_s1 <= next_din_s1; + end + +`else + + //synthesis translate_on + generate if (rst_value == 0) + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b0; + else + din_s1 <= din; + end + endgenerate + + generate if (rst_value == 1) + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + din_s1 <= 1'b1; + else + din_s1 <= din; + end + endgenerate + //synthesis translate_off + +`endif + +`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE + always @(*) begin + if (reset_n && (din_last != din) && (random != din)) begin + $display("%m: Verbose Info: metastable event @ time %t", $time); + ->metastable_event; + end + end +`endif + + //synthesis translate_on + + // the remaining synchronizer registers form a simple shift register + // of length depth-1 + generate if (rst_value == 0) + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b0}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + endgenerate + + generate if (rst_value == 1) + if (depth < 3) begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b1}}; + else + dreg <= din_s1; + end + end else begin + always @(posedge clk or negedge reset_n) begin + if (reset_n == 0) + dreg <= {depth-1{1'b1}}; + else + dreg <= {dreg[depth-3:0], din_s1}; + end + end + endgenerate + + assign dout = dreg[depth-2]; + +endmodule + + + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim.v b/ase/rtl/device_models/dcp_emif_model/ed_sim.v new file mode 100644 index 000000000000..f350b99dcd2e --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim.v @@ -0,0 +1,187 @@ +// ed_sim.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim ( + output wire ddr4a_waitrequest_n, // ddr4a.waitrequest_n + input wire ddr4a_read, // .read + input wire ddr4a_write, // .write + input wire [25:0] ddr4a_address, // .address + output wire [511:0] ddr4a_readdata, // .readdata + input wire [511:0] ddr4a_writedata, // .writedata + input wire [6:0] ddr4a_burstcount, // .burstcount + input wire [63:0] ddr4a_byteenable, // .byteenable + output wire ddr4a_readdatavalid, // .readdatavalid + output wire ddr4a_userclk_clk, // ddr4a_userclk.clk + output wire ddr4b_waitrequest_n, // ddr4b.waitrequest_n + input wire ddr4b_read, // .read + input wire ddr4b_write, // .write + input wire [25:0] ddr4b_address, // .address + output wire [511:0] ddr4b_readdata, // .readdata + input wire [511:0] ddr4b_writedata, // .writedata + input wire [6:0] ddr4b_burstcount, // .burstcount + input wire [63:0] ddr4b_byteenable, // .byteenable + output wire ddr4b_readdatavalid // .readdatavalid + ); + + wire ed_sim_clock_source_0_clk_clk; // ed_sim_clock_source_0:clk -> [ddr4a:pll_ref_clk, ed_sim_reset_source_0:clk] + wire [31:0] ddr4a_clks_sharing_master_out_clks_sharing; // ddr4a:clks_sharing_master_out -> clks_sharing_splitter:sig_input + wire [0:0] ddr4a_mem_mem_reset_n; // ddr4a:mem_reset_n -> mem_a:mem_reset_n + wire [1:0] ddr4a_mem_mem_ba; // ddr4a:mem_ba -> mem_a:mem_ba + wire [1:0] ddr4a_mem_mem_bg; // ddr4a:mem_bg -> mem_a:mem_bg + wire [0:0] ddr4a_mem_mem_ck; // ddr4a:mem_ck -> mem_a:mem_ck + wire [7:0] ddr4a_mem_mem_dqs; // [] -> [ddr4a:mem_dqs, mem_a:mem_dqs] + wire [0:0] ddr4a_mem_mem_act_n; // ddr4a:mem_act_n -> mem_a:mem_act_n + wire [63:0] ddr4a_mem_mem_dq; // [] -> [ddr4a:mem_dq, mem_a:mem_dq] + wire [0:0] ddr4a_mem_mem_cs_n; // ddr4a:mem_cs_n -> mem_a:mem_cs_n + wire [16:0] ddr4a_mem_mem_a; // ddr4a:mem_a -> mem_a:mem_a + wire [0:0] ddr4a_mem_mem_odt; // ddr4a:mem_odt -> mem_a:mem_odt + wire [0:0] mem_a_mem_mem_alert_n; // mem_a:mem_alert_n -> ddr4a:mem_alert_n + wire [7:0] ddr4a_mem_mem_dqs_n; // [] -> [ddr4a:mem_dqs_n, mem_a:mem_dqs_n] + wire [0:0] ddr4a_mem_mem_par; // ddr4a:mem_par -> mem_a:mem_par + wire [7:0] ddr4a_mem_mem_dbi_n; // [] -> [ddr4a:mem_dbi_n, mem_a:mem_dbi_n] + wire [0:0] ddr4a_mem_mem_ck_n; // ddr4a:mem_ck_n -> mem_a:mem_ck_n + wire [0:0] ddr4a_mem_mem_cke; // ddr4a:mem_cke -> mem_a:mem_cke + wire [0:0] ddr4b_mem_mem_reset_n; // ddr4b:mem_reset_n -> mem_b:mem_reset_n + wire [1:0] ddr4b_mem_mem_ba; // ddr4b:mem_ba -> mem_b:mem_ba + wire [1:0] ddr4b_mem_mem_bg; // ddr4b:mem_bg -> mem_b:mem_bg + wire [0:0] ddr4b_mem_mem_ck; // ddr4b:mem_ck -> mem_b:mem_ck + wire [7:0] ddr4b_mem_mem_dqs; // [] -> [ddr4b:mem_dqs, mem_b:mem_dqs] + wire [0:0] ddr4b_mem_mem_act_n; // ddr4b:mem_act_n -> mem_b:mem_act_n + wire [63:0] ddr4b_mem_mem_dq; // [] -> [ddr4b:mem_dq, mem_b:mem_dq] + wire [0:0] ddr4b_mem_mem_cs_n; // ddr4b:mem_cs_n -> mem_b:mem_cs_n + wire [16:0] ddr4b_mem_mem_a; // ddr4b:mem_a -> mem_b:mem_a + wire [0:0] ddr4b_mem_mem_odt; // ddr4b:mem_odt -> mem_b:mem_odt + wire [0:0] mem_b_mem_mem_alert_n; // mem_b:mem_alert_n -> ddr4b:mem_alert_n + wire [7:0] ddr4b_mem_mem_dqs_n; // [] -> [ddr4b:mem_dqs_n, mem_b:mem_dqs_n] + wire [0:0] ddr4b_mem_mem_par; // ddr4b:mem_par -> mem_b:mem_par + wire [7:0] ddr4b_mem_mem_dbi_n; // [] -> [ddr4b:mem_dbi_n, mem_b:mem_dbi_n] + wire [0:0] ddr4b_mem_mem_ck_n; // ddr4b:mem_ck_n -> mem_b:mem_ck_n + wire [0:0] ddr4b_mem_mem_cke; // ddr4b:mem_cke -> mem_b:mem_cke + wire [31:0] clks_sharing_splitter_sig_output_if_0_clks_sharing; // clks_sharing_splitter:sig_output_0 -> ddr4b:clks_sharing_slave_in + wire ed_sim_reset_source_0_reset_reset; // ed_sim_reset_source_0:reset -> ddr4a:global_reset_n + + ed_sim_clks_sharing_splitter clks_sharing_splitter ( + .sig_input (ddr4a_clks_sharing_master_out_clks_sharing), // sig_input_if.clks_sharing + .sig_output_0 (clks_sharing_splitter_sig_output_if_0_clks_sharing) // sig_output_if_0.clks_sharing + ); + + ed_sim_ddr4a ddr4a ( + .clks_sharing_master_out (ddr4a_clks_sharing_master_out_clks_sharing), // clks_sharing_master_out.clks_sharing + .amm_ready_0 (ddr4a_waitrequest_n), // ctrl_amm_0.waitrequest_n + .amm_read_0 (ddr4a_read), // .read + .amm_write_0 (ddr4a_write), // .write + .amm_address_0 (ddr4a_address), // .address + .amm_readdata_0 (ddr4a_readdata), // .readdata + .amm_writedata_0 (ddr4a_writedata), // .writedata + .amm_burstcount_0 (ddr4a_burstcount), // .burstcount + .amm_byteenable_0 (ddr4a_byteenable), // .byteenable + .amm_readdatavalid_0 (ddr4a_readdatavalid), // .readdatavalid + .emif_usr_clk (ddr4a_userclk_clk), // emif_usr_clk.clk + .emif_usr_reset_n (), // emif_usr_reset_n.reset_n + .global_reset_n (ed_sim_reset_source_0_reset_reset), // global_reset_n.reset_n + .mem_ck (ddr4a_mem_mem_ck), // mem.mem_ck + .mem_ck_n (ddr4a_mem_mem_ck_n), // .mem_ck_n + .mem_a (ddr4a_mem_mem_a), // .mem_a + .mem_act_n (ddr4a_mem_mem_act_n), // .mem_act_n + .mem_ba (ddr4a_mem_mem_ba), // .mem_ba + .mem_bg (ddr4a_mem_mem_bg), // .mem_bg + .mem_cke (ddr4a_mem_mem_cke), // .mem_cke + .mem_cs_n (ddr4a_mem_mem_cs_n), // .mem_cs_n + .mem_odt (ddr4a_mem_mem_odt), // .mem_odt + .mem_reset_n (ddr4a_mem_mem_reset_n), // .mem_reset_n + .mem_par (ddr4a_mem_mem_par), // .mem_par + .mem_alert_n (mem_a_mem_mem_alert_n), // .mem_alert_n + .mem_dqs (ddr4a_mem_mem_dqs), // .mem_dqs + .mem_dqs_n (ddr4a_mem_mem_dqs_n), // .mem_dqs_n + .mem_dq (ddr4a_mem_mem_dq), // .mem_dq + .mem_dbi_n (ddr4a_mem_mem_dbi_n), // .mem_dbi_n + .oct_rzqin (), // oct.oct_rzqin + .pll_ref_clk (ed_sim_clock_source_0_clk_clk), // pll_ref_clk.clk + .local_cal_success (), // status.local_cal_success + .local_cal_fail () // .local_cal_fail + ); + + ed_sim_emif_slave_1 ddr4b ( + .clks_sharing_slave_in (clks_sharing_splitter_sig_output_if_0_clks_sharing), // clks_sharing_slave_in.clks_sharing + .amm_ready_0 (ddr4b_waitrequest_n), // ctrl_amm_0.waitrequest_n + .amm_read_0 (ddr4b_read), // .read + .amm_write_0 (ddr4b_write), // .write + .amm_address_0 (ddr4b_address), // .address + .amm_readdata_0 (ddr4b_readdata), // .readdata + .amm_writedata_0 (ddr4b_writedata), // .writedata + .amm_burstcount_0 (ddr4b_burstcount), // .burstcount + .amm_byteenable_0 (ddr4b_byteenable), // .byteenable + .amm_readdatavalid_0 (ddr4b_readdatavalid), // .readdatavalid + .emif_usr_clk (), // emif_usr_clk.clk + .emif_usr_reset_n (), // emif_usr_reset_n.reset_n + .mem_ck (ddr4b_mem_mem_ck), // mem.mem_ck + .mem_ck_n (ddr4b_mem_mem_ck_n), // .mem_ck_n + .mem_a (ddr4b_mem_mem_a), // .mem_a + .mem_act_n (ddr4b_mem_mem_act_n), // .mem_act_n + .mem_ba (ddr4b_mem_mem_ba), // .mem_ba + .mem_bg (ddr4b_mem_mem_bg), // .mem_bg + .mem_cke (ddr4b_mem_mem_cke), // .mem_cke + .mem_cs_n (ddr4b_mem_mem_cs_n), // .mem_cs_n + .mem_odt (ddr4b_mem_mem_odt), // .mem_odt + .mem_reset_n (ddr4b_mem_mem_reset_n), // .mem_reset_n + .mem_par (ddr4b_mem_mem_par), // .mem_par + .mem_alert_n (mem_b_mem_mem_alert_n), // .mem_alert_n + .mem_dqs (ddr4b_mem_mem_dqs), // .mem_dqs + .mem_dqs_n (ddr4b_mem_mem_dqs_n), // .mem_dqs_n + .mem_dq (ddr4b_mem_mem_dq), // .mem_dq + .mem_dbi_n (ddr4b_mem_mem_dbi_n), // .mem_dbi_n + .oct_rzqin (), // oct.oct_rzqin + .local_cal_success (), // status.local_cal_success + .local_cal_fail () // .local_cal_fail + ); + + ed_sim_pll_ref_clk_source ed_sim_clock_source_0 ( + .clk (ed_sim_clock_source_0_clk_clk) // clk.clk + ); + + ed_sim_global_reset_n_source ed_sim_reset_source_0 ( + .clk (ed_sim_clock_source_0_clk_clk), // clk.clk + .reset (ed_sim_reset_source_0_reset_reset) // reset.reset_n + ); + + ed_sim_mem_0 mem_a ( + .mem_ck (ddr4a_mem_mem_ck), // mem.mem_ck + .mem_ck_n (ddr4a_mem_mem_ck_n), // .mem_ck_n + .mem_a (ddr4a_mem_mem_a), // .mem_a + .mem_act_n (ddr4a_mem_mem_act_n), // .mem_act_n + .mem_ba (ddr4a_mem_mem_ba), // .mem_ba + .mem_bg (ddr4a_mem_mem_bg), // .mem_bg + .mem_cke (ddr4a_mem_mem_cke), // .mem_cke + .mem_cs_n (ddr4a_mem_mem_cs_n), // .mem_cs_n + .mem_odt (ddr4a_mem_mem_odt), // .mem_odt + .mem_reset_n (ddr4a_mem_mem_reset_n), // .mem_reset_n + .mem_par (ddr4a_mem_mem_par), // .mem_par + .mem_alert_n (mem_a_mem_mem_alert_n), // .mem_alert_n + .mem_dqs (ddr4a_mem_mem_dqs), // .mem_dqs + .mem_dqs_n (ddr4a_mem_mem_dqs_n), // .mem_dqs_n + .mem_dq (ddr4a_mem_mem_dq), // .mem_dq + .mem_dbi_n (ddr4a_mem_mem_dbi_n) // .mem_dbi_n + ); + + ed_sim_mem_1 mem_b ( + .mem_ck (ddr4b_mem_mem_ck), // mem.mem_ck + .mem_ck_n (ddr4b_mem_mem_ck_n), // .mem_ck_n + .mem_a (ddr4b_mem_mem_a), // .mem_a + .mem_act_n (ddr4b_mem_mem_act_n), // .mem_act_n + .mem_ba (ddr4b_mem_mem_ba), // .mem_ba + .mem_bg (ddr4b_mem_mem_bg), // .mem_bg + .mem_cke (ddr4b_mem_mem_cke), // .mem_cke + .mem_cs_n (ddr4b_mem_mem_cs_n), // .mem_cs_n + .mem_odt (ddr4b_mem_mem_odt), // .mem_odt + .mem_reset_n (ddr4b_mem_mem_reset_n), // .mem_reset_n + .mem_par (ddr4b_mem_mem_par), // .mem_par + .mem_alert_n (mem_b_mem_mem_alert_n), // .mem_alert_n + .mem_dqs (ddr4b_mem_mem_dqs), // .mem_dqs + .mem_dqs_n (ddr4b_mem_mem_dqs_n), // .mem_dqs_n + .mem_dq (ddr4b_mem_mem_dq), // .mem_dq + .mem_dbi_n (ddr4b_mem_mem_dbi_n) // .mem_dbi_n + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_clks_sharing_splitter.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_clks_sharing_splitter.v new file mode 100644 index 000000000000..9496e03857d7 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_clks_sharing_splitter.v @@ -0,0 +1,13 @@ +// ed_sim_clks_sharing_splitter.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_clks_sharing_splitter ( + input wire [31:0] sig_input, // sig_input_if.clks_sharing + output wire [31:0] sig_output_0 // sig_output_if_0.clks_sharing + ); + + assign sig_output_0 = sig_input; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a.v new file mode 100644 index 000000000000..919b03fbb31a --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a.v @@ -0,0 +1,78 @@ +// ed_sim_ddr4a.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_ddr4a ( + output wire [31:0] clks_sharing_master_out, // clks_sharing_master_out.clks_sharing + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n + input wire amm_read_0, // .read + input wire amm_write_0, // .write + input wire [25:0] amm_address_0, // .address + output wire [511:0] amm_readdata_0, // .readdata + input wire [511:0] amm_writedata_0, // .writedata + input wire [6:0] amm_burstcount_0, // .burstcount + input wire [63:0] amm_byteenable_0, // .byteenable + output wire amm_readdatavalid_0, // .readdatavalid + output wire emif_usr_clk, // emif_usr_clk.clk + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n + input wire global_reset_n, // global_reset_n.reset_n + output wire [0:0] mem_ck, // mem.mem_ck + output wire [0:0] mem_ck_n, // .mem_ck_n + output wire [16:0] mem_a, // .mem_a + output wire [0:0] mem_act_n, // .mem_act_n + output wire [1:0] mem_ba, // .mem_ba + output wire [1:0] mem_bg, // .mem_bg + output wire [0:0] mem_cke, // .mem_cke + output wire [0:0] mem_cs_n, // .mem_cs_n + output wire [0:0] mem_odt, // .mem_odt + output wire [0:0] mem_reset_n, // .mem_reset_n + output wire [0:0] mem_par, // .mem_par + input wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n, // .mem_dbi_n + input wire oct_rzqin, // oct.oct_rzqin + input wire pll_ref_clk, // pll_ref_clk.clk + output wire local_cal_success, // status.local_cal_success + output wire local_cal_fail // .local_cal_fail + ); + + ed_sim_ddr4a_altera_emif_170_svsenxa ddr4a ( + .clks_sharing_master_out (clks_sharing_master_out), // clks_sharing_master_out.clks_sharing + .amm_ready_0 (amm_ready_0), // ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // .read + .amm_write_0 (amm_write_0), // .write + .amm_address_0 (amm_address_0), // .address + .amm_readdata_0 (amm_readdata_0), // .readdata + .amm_writedata_0 (amm_writedata_0), // .writedata + .amm_burstcount_0 (amm_burstcount_0), // .burstcount + .amm_byteenable_0 (amm_byteenable_0), // .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0), // .readdatavalid + .emif_usr_clk (emif_usr_clk), // emif_usr_clk.clk + .emif_usr_reset_n (emif_usr_reset_n), // emif_usr_reset_n.reset_n + .global_reset_n (global_reset_n), // global_reset_n.reset_n + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .oct_rzqin (oct_rzqin), // oct.oct_rzqin + .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk + .local_cal_success (local_cal_success), // status.local_cal_success + .local_cal_fail (local_cal_fail) // .local_cal_fail + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_avalon_onchip_memory2_170_yroldmy.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_avalon_onchip_memory2_170_yroldmy.v new file mode 100644 index 000000000000..9ac8199b33c8 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_avalon_onchip_memory2_170_yroldmy.v @@ -0,0 +1,105 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module ed_sim_ddr4a_altera_avalon_onchip_memory2_170_yroldmy ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + debugaccess, + freeze, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "seq_cal_soft_m20k.hex"; + + + output [ 31: 0] readdata; + input [ 11: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input debugaccess; + input freeze; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + +wire clocken0; +wire [ 31: 0] readdata; +wire wren; + assign wren = chipselect & write & debugaccess; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 4096, + the_altsyncram.numwords_a = 4096, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 12; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_170_svsenxa.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_170_svsenxa.v new file mode 100644 index 000000000000..0beb7d2cb6ef --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_170_svsenxa.v @@ -0,0 +1,1857 @@ +// ed_sim_ddr4a_altera_emif_170_svsenxa.v + +// This file was auto-generated from altera_emif_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_ddr4a_altera_emif_170_svsenxa ( + output wire [31:0] clks_sharing_master_out, // clks_sharing_master_out.clks_sharing + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n + input wire amm_read_0, // .read + input wire amm_write_0, // .write + input wire [25:0] amm_address_0, // .address + output wire [511:0] amm_readdata_0, // .readdata + input wire [511:0] amm_writedata_0, // .writedata + input wire [6:0] amm_burstcount_0, // .burstcount + input wire [63:0] amm_byteenable_0, // .byteenable + output wire amm_readdatavalid_0, // .readdatavalid + output wire emif_usr_clk, // emif_usr_clk.clk + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n + input wire global_reset_n, // global_reset_n.reset_n + output wire [0:0] mem_ck, // mem.mem_ck + output wire [0:0] mem_ck_n, // .mem_ck_n + output wire [16:0] mem_a, // .mem_a + output wire [0:0] mem_act_n, // .mem_act_n + output wire [1:0] mem_ba, // .mem_ba + output wire [1:0] mem_bg, // .mem_bg + output wire [0:0] mem_cke, // .mem_cke + output wire [0:0] mem_cs_n, // .mem_cs_n + output wire [0:0] mem_odt, // .mem_odt + output wire [0:0] mem_reset_n, // .mem_reset_n + output wire [0:0] mem_par, // .mem_par + input wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n, // .mem_dbi_n + input wire oct_rzqin, // oct.oct_rzqin + input wire pll_ref_clk, // pll_ref_clk.clk + output wire local_cal_success, // status.local_cal_success + output wire local_cal_fail // .local_cal_fail + ); + + wire arch_cal_slave_clk_clk; // arch:cal_slave_clk -> [arch:cal_slave_clk_in, cal_slave_component:clk_clk] + wire arch_cal_slave_reset_n_reset; // arch:cal_slave_reset_n -> [arch:cal_slave_reset_n_in, cal_slave_component:rst_reset] + wire arch_cal_master_waitrequest; // cal_slave_component:avl_waitrequest -> arch:cal_master_waitrequest + wire [31:0] arch_cal_master_readdata; // cal_slave_component:avl_readdata -> arch:cal_master_read_data + wire arch_cal_master_debugaccess; // arch:cal_master_debugaccess -> cal_slave_component:avl_debugaccess + wire arch_cal_master_read; // arch:cal_master_read -> cal_slave_component:avl_read + wire [15:0] arch_cal_master_address; // arch:cal_master_addr -> cal_slave_component:avl_address + wire [3:0] arch_cal_master_byteenable; // arch:cal_master_byteenable -> cal_slave_component:avl_byteenable + wire arch_cal_master_readdatavalid; // cal_slave_component:avl_readdatavalid -> arch:cal_master_read_data_valid + wire arch_cal_master_write; // arch:cal_master_write -> cal_slave_component:avl_write + wire [31:0] arch_cal_master_writedata; // arch:cal_master_write_data -> cal_slave_component:avl_writedata + wire arch_cal_master_burstcount; // arch:cal_master_burstcount -> cal_slave_component:avl_burstcount + + ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy #( + .PROTOCOL_ENUM ("PROTOCOL_DDR4"), + .PHY_TARGET_IS_ES (0), + .PHY_TARGET_IS_ES2 (0), + .PHY_TARGET_IS_PRODUCTION (1), + .PHY_CONFIG_ENUM ("CONFIG_PHY_AND_HARD_CTRL"), + .PHY_PING_PONG_EN (0), + .PHY_CORE_CLKS_SHARING_ENUM ("CORE_CLKS_SHARING_MASTER"), + .PHY_CALIBRATED_OCT (1), + .PHY_AC_CALIBRATED_OCT (0), + .PHY_CK_CALIBRATED_OCT (1), + .PHY_DATA_CALIBRATED_OCT (1), + .PHY_HPS_ENABLE_EARLY_RELEASE (0), + .PLL_NUM_OF_EXTRA_CLKS (0), + .MEM_FORMAT_ENUM ("MEM_FORMAT_DISCRETE"), + .MEM_BURST_LENGTH (8), + .MEM_DATA_MASK_EN (1), + .MEM_TTL_DATA_WIDTH (64), + .MEM_TTL_NUM_OF_READ_GROUPS (8), + .MEM_TTL_NUM_OF_WRITE_GROUPS (8), + .DIAG_SIM_REGTEST_MODE (0), + .DIAG_SYNTH_FOR_SIM (0), + .DIAG_VERBOSE_IOAUX (0), + .DIAG_ECLIPSE_DEBUG (0), + .DIAG_EXPORT_VJI (0), + .DIAG_INTERFACE_ID (0), + .DIAG_FAST_SIM (1), + .DIAG_USE_ABSTRACT_PHY (1), + .SILICON_REV ("20nm5"), + .IS_HPS (0), + .IS_VID (0), + .USER_CLK_RATIO (4), + .C2P_P2C_CLK_RATIO (4), + .PHY_HMC_CLK_RATIO (2), + .DIAG_ABSTRACT_PHY_WLAT (5), + .DIAG_ABSTRACT_PHY_RLAT (18), + .DIAG_CPA_OUT_1_EN (0), + .DIAG_USE_CPA_LOCK (0), + .DQS_BUS_MODE_ENUM ("DQS_BUS_MODE_X8_X9"), + .AC_PIN_MAP_SCHEME ("use_0_1_2_lane"), + .NUM_OF_HMC_PORTS (1), + .HMC_AVL_PROTOCOL_ENUM ("CTRL_AVL_PROTOCOL_MM"), + .HMC_CTRL_DIMM_TYPE ("component"), + .REGISTER_AFI (1), + .SEQ_SYNTH_CPU_CLK_DIVIDE (2), + .SEQ_SYNTH_CAL_CLK_DIVIDE (8), + .SEQ_SIM_CPU_CLK_DIVIDE (1), + .SEQ_SIM_CAL_CLK_DIVIDE (32), + .SEQ_SYNTH_OSC_FREQ_MHZ (450), + .SEQ_SIM_OSC_FREQ_MHZ (2123), + .NUM_OF_RTL_TILES (3), + .PRI_RDATA_TILE_INDEX (1), + .PRI_RDATA_LANE_INDEX (3), + .PRI_WDATA_TILE_INDEX (1), + .PRI_WDATA_LANE_INDEX (3), + .PRI_AC_TILE_INDEX (1), + .SEC_RDATA_TILE_INDEX (1), + .SEC_RDATA_LANE_INDEX (3), + .SEC_WDATA_TILE_INDEX (1), + .SEC_WDATA_LANE_INDEX (3), + .SEC_AC_TILE_INDEX (1), + .LANES_USAGE_0 (765762413), + .LANES_USAGE_1 (5), + .LANES_USAGE_2 (0), + .LANES_USAGE_3 (0), + .LANES_USAGE_AUTOGEN_WCNT (4), + .PINS_USAGE_0 (1056960511), + .PINS_USAGE_1 (763363263), + .PINS_USAGE_2 (1055887359), + .PINS_USAGE_3 (1073479615), + .PINS_USAGE_4 (4094), + .PINS_USAGE_5 (0), + .PINS_USAGE_6 (0), + .PINS_USAGE_7 (0), + .PINS_USAGE_8 (0), + .PINS_USAGE_9 (0), + .PINS_USAGE_10 (0), + .PINS_USAGE_11 (0), + .PINS_USAGE_12 (0), + .PINS_USAGE_AUTOGEN_WCNT (13), + .PINS_RATE_0 (1), + .PINS_RATE_1 (561774592), + .PINS_RATE_2 (15699967), + .PINS_RATE_3 (0), + .PINS_RATE_4 (0), + .PINS_RATE_5 (0), + .PINS_RATE_6 (0), + .PINS_RATE_7 (0), + .PINS_RATE_8 (0), + .PINS_RATE_9 (0), + .PINS_RATE_10 (0), + .PINS_RATE_11 (0), + .PINS_RATE_12 (0), + .PINS_RATE_AUTOGEN_WCNT (13), + .PINS_WDB_0 (920202678), + .PINS_WDB_1 (910912566), + .PINS_WDB_2 (316345782), + .PINS_WDB_3 (918777270), + .PINS_WDB_4 (165375378), + .PINS_WDB_5 (136581193), + .PINS_WDB_6 (153391689), + .PINS_WDB_7 (153387017), + .PINS_WDB_8 (316342856), + .PINS_WDB_9 (918777270), + .PINS_WDB_10 (819686802), + .PINS_WDB_11 (920347830), + .PINS_WDB_12 (920202672), + .PINS_WDB_13 (54), + .PINS_WDB_14 (0), + .PINS_WDB_15 (0), + .PINS_WDB_16 (0), + .PINS_WDB_17 (0), + .PINS_WDB_18 (0), + .PINS_WDB_19 (0), + .PINS_WDB_20 (0), + .PINS_WDB_21 (0), + .PINS_WDB_22 (0), + .PINS_WDB_23 (0), + .PINS_WDB_24 (0), + .PINS_WDB_25 (0), + .PINS_WDB_26 (0), + .PINS_WDB_27 (0), + .PINS_WDB_28 (0), + .PINS_WDB_29 (0), + .PINS_WDB_30 (0), + .PINS_WDB_31 (0), + .PINS_WDB_32 (0), + .PINS_WDB_33 (0), + .PINS_WDB_34 (0), + .PINS_WDB_35 (0), + .PINS_WDB_36 (0), + .PINS_WDB_37 (0), + .PINS_WDB_38 (0), + .PINS_WDB_AUTOGEN_WCNT (39), + .PINS_DATA_IN_MODE_0 (153612873), + .PINS_DATA_IN_MODE_1 (167547401), + .PINS_DATA_IN_MODE_2 (1059357257), + .PINS_DATA_IN_MODE_3 (153129545), + .PINS_DATA_IN_MODE_4 (153391743), + .PINS_DATA_IN_MODE_5 (150736969), + .PINS_DATA_IN_MODE_6 (153391689), + .PINS_DATA_IN_MODE_7 (153387017), + .PINS_DATA_IN_MODE_8 (1059357256), + .PINS_DATA_IN_MODE_9 (153129545), + .PINS_DATA_IN_MODE_10 (136614527), + .PINS_DATA_IN_MODE_11 (153395145), + .PINS_DATA_IN_MODE_12 (153612872), + .PINS_DATA_IN_MODE_13 (9), + .PINS_DATA_IN_MODE_14 (0), + .PINS_DATA_IN_MODE_15 (0), + .PINS_DATA_IN_MODE_16 (0), + .PINS_DATA_IN_MODE_17 (0), + .PINS_DATA_IN_MODE_18 (0), + .PINS_DATA_IN_MODE_19 (0), + .PINS_DATA_IN_MODE_20 (0), + .PINS_DATA_IN_MODE_21 (0), + .PINS_DATA_IN_MODE_22 (0), + .PINS_DATA_IN_MODE_23 (0), + .PINS_DATA_IN_MODE_24 (0), + .PINS_DATA_IN_MODE_25 (0), + .PINS_DATA_IN_MODE_26 (0), + .PINS_DATA_IN_MODE_27 (0), + .PINS_DATA_IN_MODE_28 (0), + .PINS_DATA_IN_MODE_29 (0), + .PINS_DATA_IN_MODE_30 (0), + .PINS_DATA_IN_MODE_31 (0), + .PINS_DATA_IN_MODE_32 (0), + .PINS_DATA_IN_MODE_33 (0), + .PINS_DATA_IN_MODE_34 (0), + .PINS_DATA_IN_MODE_35 (0), + .PINS_DATA_IN_MODE_36 (0), + .PINS_DATA_IN_MODE_37 (0), + .PINS_DATA_IN_MODE_38 (0), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (39), + .PINS_C2L_DRIVEN_0 (251457486), + .PINS_C2L_DRIVEN_1 (259007), + .PINS_C2L_DRIVEN_2 (234881024), + .PINS_C2L_DRIVEN_3 (1060893631), + .PINS_C2L_DRIVEN_4 (4046), + .PINS_C2L_DRIVEN_5 (0), + .PINS_C2L_DRIVEN_6 (0), + .PINS_C2L_DRIVEN_7 (0), + .PINS_C2L_DRIVEN_8 (0), + .PINS_C2L_DRIVEN_9 (0), + .PINS_C2L_DRIVEN_10 (0), + .PINS_C2L_DRIVEN_11 (0), + .PINS_C2L_DRIVEN_12 (0), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (13), + .PINS_DB_IN_BYPASS_0 (1), + .PINS_DB_IN_BYPASS_1 (763101184), + .PINS_DB_IN_BYPASS_2 (15699967), + .PINS_DB_IN_BYPASS_3 (0), + .PINS_DB_IN_BYPASS_4 (0), + .PINS_DB_IN_BYPASS_5 (0), + .PINS_DB_IN_BYPASS_6 (0), + .PINS_DB_IN_BYPASS_7 (0), + .PINS_DB_IN_BYPASS_8 (0), + .PINS_DB_IN_BYPASS_9 (0), + .PINS_DB_IN_BYPASS_10 (0), + .PINS_DB_IN_BYPASS_11 (0), + .PINS_DB_IN_BYPASS_12 (0), + .PINS_DB_IN_BYPASS_AUTOGEN_WCNT (13), + .PINS_DB_OUT_BYPASS_0 (1), + .PINS_DB_OUT_BYPASS_1 (763101184), + .PINS_DB_OUT_BYPASS_2 (15699967), + .PINS_DB_OUT_BYPASS_3 (0), + .PINS_DB_OUT_BYPASS_4 (0), + .PINS_DB_OUT_BYPASS_5 (0), + .PINS_DB_OUT_BYPASS_6 (0), + .PINS_DB_OUT_BYPASS_7 (0), + .PINS_DB_OUT_BYPASS_8 (0), + .PINS_DB_OUT_BYPASS_9 (0), + .PINS_DB_OUT_BYPASS_10 (0), + .PINS_DB_OUT_BYPASS_11 (0), + .PINS_DB_OUT_BYPASS_12 (0), + .PINS_DB_OUT_BYPASS_AUTOGEN_WCNT (13), + .PINS_DB_OE_BYPASS_0 (1), + .PINS_DB_OE_BYPASS_1 (763101184), + .PINS_DB_OE_BYPASS_2 (15699967), + .PINS_DB_OE_BYPASS_3 (0), + .PINS_DB_OE_BYPASS_4 (0), + .PINS_DB_OE_BYPASS_5 (0), + .PINS_DB_OE_BYPASS_6 (0), + .PINS_DB_OE_BYPASS_7 (0), + .PINS_DB_OE_BYPASS_8 (0), + .PINS_DB_OE_BYPASS_9 (0), + .PINS_DB_OE_BYPASS_10 (0), + .PINS_DB_OE_BYPASS_11 (0), + .PINS_DB_OE_BYPASS_12 (0), + .PINS_DB_OE_BYPASS_AUTOGEN_WCNT (13), + .PINS_INVERT_WR_0 (537002016), + .PINS_INVERT_WR_1 (2048), + .PINS_INVERT_WR_2 (536870912), + .PINS_INVERT_WR_3 (8390656), + .PINS_INVERT_WR_4 (32), + .PINS_INVERT_WR_5 (0), + .PINS_INVERT_WR_6 (0), + .PINS_INVERT_WR_7 (0), + .PINS_INVERT_WR_8 (0), + .PINS_INVERT_WR_9 (0), + .PINS_INVERT_WR_10 (0), + .PINS_INVERT_WR_11 (0), + .PINS_INVERT_WR_12 (0), + .PINS_INVERT_WR_AUTOGEN_WCNT (13), + .PINS_INVERT_OE_0 (1056960510), + .PINS_INVERT_OE_1 (763363263), + .PINS_INVERT_OE_2 (1055887359), + .PINS_INVERT_OE_3 (1073479615), + .PINS_INVERT_OE_4 (4094), + .PINS_INVERT_OE_5 (0), + .PINS_INVERT_OE_6 (0), + .PINS_INVERT_OE_7 (0), + .PINS_INVERT_OE_8 (0), + .PINS_INVERT_OE_9 (0), + .PINS_INVERT_OE_10 (0), + .PINS_INVERT_OE_11 (0), + .PINS_INVERT_OE_12 (0), + .PINS_INVERT_OE_AUTOGEN_WCNT (13), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_0 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_1 (201326592), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_2 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_3 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_4 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_5 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_6 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_7 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_8 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_9 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_10 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_11 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_12 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT (13), + .PINS_OCT_MODE_0 (1056960510), + .PINS_OCT_MODE_1 (262079), + .PINS_OCT_MODE_2 (1040187392), + .PINS_OCT_MODE_3 (1073479615), + .PINS_OCT_MODE_4 (4094), + .PINS_OCT_MODE_5 (0), + .PINS_OCT_MODE_6 (0), + .PINS_OCT_MODE_7 (0), + .PINS_OCT_MODE_8 (0), + .PINS_OCT_MODE_9 (0), + .PINS_OCT_MODE_10 (0), + .PINS_OCT_MODE_11 (0), + .PINS_OCT_MODE_12 (0), + .PINS_OCT_MODE_AUTOGEN_WCNT (13), + .PINS_GPIO_MODE_0 (1), + .PINS_GPIO_MODE_1 (0), + .PINS_GPIO_MODE_2 (0), + .PINS_GPIO_MODE_3 (0), + .PINS_GPIO_MODE_4 (0), + .PINS_GPIO_MODE_5 (0), + .PINS_GPIO_MODE_6 (0), + .PINS_GPIO_MODE_7 (0), + .PINS_GPIO_MODE_8 (0), + .PINS_GPIO_MODE_9 (0), + .PINS_GPIO_MODE_10 (0), + .PINS_GPIO_MODE_11 (0), + .PINS_GPIO_MODE_12 (0), + .PINS_GPIO_MODE_AUTOGEN_WCNT (13), + .UNUSED_MEM_PINS_PINLOC_0 (149044250), + .UNUSED_MEM_PINS_PINLOC_1 (145895565), + .UNUSED_MEM_PINS_PINLOC_2 (142746762), + .UNUSED_MEM_PINS_PINLOC_3 (139597959), + .UNUSED_MEM_PINS_PINLOC_4 (113369220), + .UNUSED_MEM_PINS_PINLOC_5 (83972192), + .UNUSED_MEM_PINS_PINLOC_6 (75572298), + .UNUSED_MEM_PINS_PINLOC_7 (55630906), + .UNUSED_MEM_PINS_PINLOC_8 (12607524), + .UNUSED_MEM_PINS_PINLOC_9 (0), + .UNUSED_MEM_PINS_PINLOC_10 (0), + .UNUSED_MEM_PINS_PINLOC_11 (0), + .UNUSED_MEM_PINS_PINLOC_12 (0), + .UNUSED_MEM_PINS_PINLOC_13 (0), + .UNUSED_MEM_PINS_PINLOC_14 (0), + .UNUSED_MEM_PINS_PINLOC_15 (0), + .UNUSED_MEM_PINS_PINLOC_16 (0), + .UNUSED_MEM_PINS_PINLOC_17 (0), + .UNUSED_MEM_PINS_PINLOC_18 (0), + .UNUSED_MEM_PINS_PINLOC_19 (0), + .UNUSED_MEM_PINS_PINLOC_20 (0), + .UNUSED_MEM_PINS_PINLOC_21 (0), + .UNUSED_MEM_PINS_PINLOC_22 (0), + .UNUSED_MEM_PINS_PINLOC_23 (0), + .UNUSED_MEM_PINS_PINLOC_24 (0), + .UNUSED_MEM_PINS_PINLOC_25 (0), + .UNUSED_MEM_PINS_PINLOC_26 (0), + .UNUSED_MEM_PINS_PINLOC_27 (0), + .UNUSED_MEM_PINS_PINLOC_28 (0), + .UNUSED_MEM_PINS_PINLOC_29 (0), + .UNUSED_MEM_PINS_PINLOC_30 (0), + .UNUSED_MEM_PINS_PINLOC_31 (0), + .UNUSED_MEM_PINS_PINLOC_32 (0), + .UNUSED_MEM_PINS_PINLOC_33 (0), + .UNUSED_MEM_PINS_PINLOC_34 (0), + .UNUSED_MEM_PINS_PINLOC_35 (0), + .UNUSED_MEM_PINS_PINLOC_36 (0), + .UNUSED_MEM_PINS_PINLOC_37 (0), + .UNUSED_MEM_PINS_PINLOC_38 (0), + .UNUSED_MEM_PINS_PINLOC_39 (0), + .UNUSED_MEM_PINS_PINLOC_40 (0), + .UNUSED_MEM_PINS_PINLOC_41 (0), + .UNUSED_MEM_PINS_PINLOC_42 (0), + .UNUSED_MEM_PINS_PINLOC_43 (0), + .UNUSED_MEM_PINS_PINLOC_44 (0), + .UNUSED_MEM_PINS_PINLOC_45 (0), + .UNUSED_MEM_PINS_PINLOC_46 (0), + .UNUSED_MEM_PINS_PINLOC_47 (0), + .UNUSED_MEM_PINS_PINLOC_48 (0), + .UNUSED_MEM_PINS_PINLOC_49 (0), + .UNUSED_MEM_PINS_PINLOC_50 (0), + .UNUSED_MEM_PINS_PINLOC_51 (0), + .UNUSED_MEM_PINS_PINLOC_52 (0), + .UNUSED_MEM_PINS_PINLOC_53 (0), + .UNUSED_MEM_PINS_PINLOC_54 (0), + .UNUSED_MEM_PINS_PINLOC_55 (0), + .UNUSED_MEM_PINS_PINLOC_56 (0), + .UNUSED_MEM_PINS_PINLOC_57 (0), + .UNUSED_MEM_PINS_PINLOC_58 (0), + .UNUSED_MEM_PINS_PINLOC_59 (0), + .UNUSED_MEM_PINS_PINLOC_60 (0), + .UNUSED_MEM_PINS_PINLOC_61 (0), + .UNUSED_MEM_PINS_PINLOC_62 (0), + .UNUSED_MEM_PINS_PINLOC_63 (0), + .UNUSED_MEM_PINS_PINLOC_64 (0), + .UNUSED_MEM_PINS_PINLOC_65 (0), + .UNUSED_MEM_PINS_PINLOC_66 (0), + .UNUSED_MEM_PINS_PINLOC_67 (0), + .UNUSED_MEM_PINS_PINLOC_68 (0), + .UNUSED_MEM_PINS_PINLOC_69 (0), + .UNUSED_MEM_PINS_PINLOC_70 (0), + .UNUSED_MEM_PINS_PINLOC_71 (0), + .UNUSED_MEM_PINS_PINLOC_72 (0), + .UNUSED_MEM_PINS_PINLOC_73 (0), + .UNUSED_MEM_PINS_PINLOC_74 (0), + .UNUSED_MEM_PINS_PINLOC_75 (0), + .UNUSED_MEM_PINS_PINLOC_76 (0), + .UNUSED_MEM_PINS_PINLOC_77 (0), + .UNUSED_MEM_PINS_PINLOC_78 (0), + .UNUSED_MEM_PINS_PINLOC_79 (0), + .UNUSED_MEM_PINS_PINLOC_80 (0), + .UNUSED_MEM_PINS_PINLOC_81 (0), + .UNUSED_MEM_PINS_PINLOC_82 (0), + .UNUSED_MEM_PINS_PINLOC_83 (0), + .UNUSED_MEM_PINS_PINLOC_84 (0), + .UNUSED_MEM_PINS_PINLOC_85 (0), + .UNUSED_MEM_PINS_PINLOC_86 (0), + .UNUSED_MEM_PINS_PINLOC_87 (0), + .UNUSED_MEM_PINS_PINLOC_88 (0), + .UNUSED_MEM_PINS_PINLOC_89 (0), + .UNUSED_MEM_PINS_PINLOC_90 (0), + .UNUSED_MEM_PINS_PINLOC_91 (0), + .UNUSED_MEM_PINS_PINLOC_92 (0), + .UNUSED_MEM_PINS_PINLOC_93 (0), + .UNUSED_MEM_PINS_PINLOC_94 (0), + .UNUSED_MEM_PINS_PINLOC_95 (0), + .UNUSED_MEM_PINS_PINLOC_96 (0), + .UNUSED_MEM_PINS_PINLOC_97 (0), + .UNUSED_MEM_PINS_PINLOC_98 (0), + .UNUSED_MEM_PINS_PINLOC_99 (0), + .UNUSED_MEM_PINS_PINLOC_100 (0), + .UNUSED_MEM_PINS_PINLOC_101 (0), + .UNUSED_MEM_PINS_PINLOC_102 (0), + .UNUSED_MEM_PINS_PINLOC_103 (0), + .UNUSED_MEM_PINS_PINLOC_104 (0), + .UNUSED_MEM_PINS_PINLOC_105 (0), + .UNUSED_MEM_PINS_PINLOC_106 (0), + .UNUSED_MEM_PINS_PINLOC_107 (0), + .UNUSED_MEM_PINS_PINLOC_108 (0), + .UNUSED_MEM_PINS_PINLOC_109 (0), + .UNUSED_MEM_PINS_PINLOC_110 (0), + .UNUSED_MEM_PINS_PINLOC_111 (0), + .UNUSED_MEM_PINS_PINLOC_112 (0), + .UNUSED_MEM_PINS_PINLOC_113 (0), + .UNUSED_MEM_PINS_PINLOC_114 (0), + .UNUSED_MEM_PINS_PINLOC_115 (0), + .UNUSED_MEM_PINS_PINLOC_116 (0), + .UNUSED_MEM_PINS_PINLOC_117 (0), + .UNUSED_MEM_PINS_PINLOC_118 (0), + .UNUSED_MEM_PINS_PINLOC_119 (0), + .UNUSED_MEM_PINS_PINLOC_120 (0), + .UNUSED_MEM_PINS_PINLOC_121 (0), + .UNUSED_MEM_PINS_PINLOC_122 (0), + .UNUSED_MEM_PINS_PINLOC_123 (0), + .UNUSED_MEM_PINS_PINLOC_124 (0), + .UNUSED_MEM_PINS_PINLOC_125 (0), + .UNUSED_MEM_PINS_PINLOC_126 (0), + .UNUSED_MEM_PINS_PINLOC_127 (0), + .UNUSED_MEM_PINS_PINLOC_128 (0), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (129), + .UNUSED_DQS_BUSES_LANELOC_0 (6302724), + .UNUSED_DQS_BUSES_LANELOC_1 (4101), + .UNUSED_DQS_BUSES_LANELOC_2 (0), + .UNUSED_DQS_BUSES_LANELOC_3 (0), + .UNUSED_DQS_BUSES_LANELOC_4 (0), + .UNUSED_DQS_BUSES_LANELOC_5 (0), + .UNUSED_DQS_BUSES_LANELOC_6 (0), + .UNUSED_DQS_BUSES_LANELOC_7 (0), + .UNUSED_DQS_BUSES_LANELOC_8 (0), + .UNUSED_DQS_BUSES_LANELOC_9 (0), + .UNUSED_DQS_BUSES_LANELOC_10 (0), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (11), + .CENTER_TIDS_0 (5249028), + .CENTER_TIDS_1 (0), + .CENTER_TIDS_2 (0), + .CENTER_TIDS_AUTOGEN_WCNT (3), + .HMC_TIDS_0 (5511685), + .HMC_TIDS_1 (0), + .HMC_TIDS_2 (0), + .HMC_TIDS_AUTOGEN_WCNT (3), + .LANE_TIDS_0 (403177984), + .LANE_TIDS_1 (168067584), + .LANE_TIDS_2 (35717208), + .LANE_TIDS_3 (9746), + .LANE_TIDS_4 (0), + .LANE_TIDS_5 (0), + .LANE_TIDS_6 (0), + .LANE_TIDS_7 (0), + .LANE_TIDS_8 (0), + .LANE_TIDS_9 (0), + .LANE_TIDS_AUTOGEN_WCNT (10), + .PREAMBLE_MODE ("preamble_one_cycle"), + .DBI_WR_ENABLE ("false"), + .DBI_RD_ENABLE ("true"), + .CRC_EN ("crc_disable"), + .SWAP_DQS_A_B ("false"), + .DQS_PACK_MODE ("packed"), + .OCT_SIZE (2), + .DBC_WB_RESERVED_ENTRY (8), + .DLL_MODE ("ctl_dynamic"), + .DLL_CODEWORD (0), + .ABPHY_WRITE_PROTOCOL (0), + .PHY_USERMODE_OCT (0), + .PHY_PERIODIC_OCT_RECAL (0), + .PHY_HAS_DCC (1), + .PRI_HMC_CFG_ENABLE_ECC ("disable"), + .PRI_HMC_CFG_REORDER_DATA ("enable"), + .PRI_HMC_CFG_REORDER_READ ("enable"), + .PRI_HMC_CFG_REORDER_RDATA ("enable"), + .PRI_HMC_CFG_STARVE_LIMIT (10), + .PRI_HMC_CFG_DQS_TRACKING_EN ("disable"), + .PRI_HMC_CFG_ARBITER_TYPE ("twot"), + .PRI_HMC_CFG_OPEN_PAGE_EN ("enable"), + .PRI_HMC_CFG_GEAR_DOWN_EN ("disable"), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE ("singlebank"), + .PRI_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .PRI_HMC_CFG_SLOT_ROTATE_EN (0), + .PRI_HMC_CFG_SLOT_OFFSET (2), + .PRI_HMC_CFG_COL_CMD_SLOT (2), + .PRI_HMC_CFG_ROW_CMD_SLOT (1), + .PRI_HMC_CFG_ENABLE_RC ("enable"), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (8), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (8), + .PRI_HMC_CFG_TCL (18), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (14), + .PRI_HMC_CFG_WRITE_ODT_CHIP (1), + .PRI_HMC_CFG_READ_ODT_CHIP (0), + .PRI_HMC_CFG_WR_ODT_ON (0), + .PRI_HMC_CFG_RD_ODT_ON (6), + .PRI_HMC_CFG_WR_ODT_PERIOD (6), + .PRI_HMC_CFG_RD_ODT_PERIOD (7), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (15), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (240), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (3840), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (61440), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (512), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (24), + .PRI_HMC_CFG_DQSTRK_TO_VALID (4), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (4), + .PRI_HMC_CFG_SB_CG_DISABLE ("disable"), + .PRI_HMC_CFG_USER_RFSH_EN ("disable"), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ("presrfexit"), + .PRI_HMC_CFG_SB_DDR4_MR3 (197120), + .PRI_HMC_CFG_SB_DDR4_MR4 (264192), + .PRI_HMC_CFG_SB_DDR4_MR5 (5152), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (0), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ("col_width_10"), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ("row_width_15"), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ("bank_width_2"), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ("bg_width_2"), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ("cs_width_0"), + .PRI_HMC_CFG_ADDR_ORDER ("chip_row_bank_col"), + .PRI_HMC_CFG_ACT_TO_RDWR (7), + .PRI_HMC_CFG_ACT_TO_PCH (18), + .PRI_HMC_CFG_ACT_TO_ACT (25), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .PRI_HMC_CFG_RD_TO_RD (3), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .PRI_HMC_CFG_RD_TO_WR (9), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (9), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (9), + .PRI_HMC_CFG_RD_TO_PCH (5), + .PRI_HMC_CFG_RD_AP_TO_VALID (13), + .PRI_HMC_CFG_WR_TO_WR (3), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .PRI_HMC_CFG_WR_TO_RD (14), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (5), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (12), + .PRI_HMC_CFG_WR_TO_PCH (17), + .PRI_HMC_CFG_WR_AP_TO_VALID (25), + .PRI_HMC_CFG_PCH_TO_VALID (8), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (8), + .PRI_HMC_CFG_ARF_TO_VALID (140), + .PRI_HMC_CFG_PDN_TO_VALID (4), + .PRI_HMC_CFG_SRF_TO_VALID (513), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (449), + .PRI_HMC_CFG_ARF_PERIOD (4161), + .PRI_HMC_CFG_PDN_PERIOD (0), + .PRI_HMC_CFG_ZQCL_TO_VALID (257), + .PRI_HMC_CFG_ZQCS_TO_VALID (65), + .PRI_HMC_CFG_MRS_TO_VALID (7), + .PRI_HMC_CFG_MPS_TO_VALID (768), + .PRI_HMC_CFG_MRR_TO_VALID (0), + .PRI_HMC_CFG_MPR_TO_VALID (16), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (16), + .PRI_HMC_CFG_4_ACT_TO_ACT (11), + .PRI_HMC_CFG_16_ACT_TO_ACT (0), + .SEC_HMC_CFG_ENABLE_ECC ("disable"), + .SEC_HMC_CFG_REORDER_DATA ("enable"), + .SEC_HMC_CFG_REORDER_READ ("enable"), + .SEC_HMC_CFG_REORDER_RDATA ("enable"), + .SEC_HMC_CFG_STARVE_LIMIT (10), + .SEC_HMC_CFG_DQS_TRACKING_EN ("disable"), + .SEC_HMC_CFG_ARBITER_TYPE ("twot"), + .SEC_HMC_CFG_OPEN_PAGE_EN ("enable"), + .SEC_HMC_CFG_GEAR_DOWN_EN ("disable"), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE ("singlebank"), + .SEC_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .SEC_HMC_CFG_SLOT_ROTATE_EN (0), + .SEC_HMC_CFG_SLOT_OFFSET (2), + .SEC_HMC_CFG_COL_CMD_SLOT (2), + .SEC_HMC_CFG_ROW_CMD_SLOT (1), + .SEC_HMC_CFG_ENABLE_RC ("enable"), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (8), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (8), + .SEC_HMC_CFG_TCL (18), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (14), + .SEC_HMC_CFG_WRITE_ODT_CHIP (1), + .SEC_HMC_CFG_READ_ODT_CHIP (0), + .SEC_HMC_CFG_WR_ODT_ON (0), + .SEC_HMC_CFG_RD_ODT_ON (6), + .SEC_HMC_CFG_WR_ODT_PERIOD (6), + .SEC_HMC_CFG_RD_ODT_PERIOD (7), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (15), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (240), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (3840), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (61440), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (512), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (24), + .SEC_HMC_CFG_DQSTRK_TO_VALID (4), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (4), + .SEC_HMC_CFG_SB_CG_DISABLE ("disable"), + .SEC_HMC_CFG_USER_RFSH_EN ("disable"), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ("presrfexit"), + .SEC_HMC_CFG_SB_DDR4_MR3 (197120), + .SEC_HMC_CFG_SB_DDR4_MR4 (264192), + .SEC_HMC_CFG_SB_DDR4_MR5 (5152), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (0), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ("col_width_10"), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ("row_width_15"), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ("bank_width_2"), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ("bg_width_2"), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ("cs_width_0"), + .SEC_HMC_CFG_ADDR_ORDER ("chip_row_bank_col"), + .SEC_HMC_CFG_ACT_TO_RDWR (7), + .SEC_HMC_CFG_ACT_TO_PCH (18), + .SEC_HMC_CFG_ACT_TO_ACT (25), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .SEC_HMC_CFG_RD_TO_RD (3), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .SEC_HMC_CFG_RD_TO_WR (9), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (9), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (9), + .SEC_HMC_CFG_RD_TO_PCH (5), + .SEC_HMC_CFG_RD_AP_TO_VALID (13), + .SEC_HMC_CFG_WR_TO_WR (3), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .SEC_HMC_CFG_WR_TO_RD (14), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (5), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (12), + .SEC_HMC_CFG_WR_TO_PCH (17), + .SEC_HMC_CFG_WR_AP_TO_VALID (25), + .SEC_HMC_CFG_PCH_TO_VALID (8), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (8), + .SEC_HMC_CFG_ARF_TO_VALID (140), + .SEC_HMC_CFG_PDN_TO_VALID (4), + .SEC_HMC_CFG_SRF_TO_VALID (513), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (449), + .SEC_HMC_CFG_ARF_PERIOD (4161), + .SEC_HMC_CFG_PDN_PERIOD (0), + .SEC_HMC_CFG_ZQCL_TO_VALID (257), + .SEC_HMC_CFG_ZQCS_TO_VALID (65), + .SEC_HMC_CFG_MRS_TO_VALID (7), + .SEC_HMC_CFG_MPS_TO_VALID (768), + .SEC_HMC_CFG_MRR_TO_VALID (0), + .SEC_HMC_CFG_MPR_TO_VALID (16), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (16), + .SEC_HMC_CFG_4_ACT_TO_ACT (11), + .SEC_HMC_CFG_16_ACT_TO_ACT (0), + .PINS_PER_LANE (12), + .LANES_PER_TILE (4), + .OCT_CONTROL_WIDTH (16), + .PORT_MEM_CK_WIDTH (1), + .PORT_MEM_CK_PINLOC_0 (57345), + .PORT_MEM_CK_PINLOC_1 (0), + .PORT_MEM_CK_PINLOC_2 (0), + .PORT_MEM_CK_PINLOC_3 (0), + .PORT_MEM_CK_PINLOC_4 (0), + .PORT_MEM_CK_PINLOC_5 (0), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CK_N_WIDTH (1), + .PORT_MEM_CK_N_PINLOC_0 (58369), + .PORT_MEM_CK_N_PINLOC_1 (0), + .PORT_MEM_CK_N_PINLOC_2 (0), + .PORT_MEM_CK_N_PINLOC_3 (0), + .PORT_MEM_CK_N_PINLOC_4 (0), + .PORT_MEM_CK_N_PINLOC_5 (0), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_WIDTH (1), + .PORT_MEM_DK_PINLOC_0 (0), + .PORT_MEM_DK_PINLOC_1 (0), + .PORT_MEM_DK_PINLOC_2 (0), + .PORT_MEM_DK_PINLOC_3 (0), + .PORT_MEM_DK_PINLOC_4 (0), + .PORT_MEM_DK_PINLOC_5 (0), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_N_WIDTH (1), + .PORT_MEM_DK_N_PINLOC_0 (0), + .PORT_MEM_DK_N_PINLOC_1 (0), + .PORT_MEM_DK_N_PINLOC_2 (0), + .PORT_MEM_DK_N_PINLOC_3 (0), + .PORT_MEM_DK_N_PINLOC_4 (0), + .PORT_MEM_DK_N_PINLOC_5 (0), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_WIDTH (1), + .PORT_MEM_DKA_PINLOC_0 (0), + .PORT_MEM_DKA_PINLOC_1 (0), + .PORT_MEM_DKA_PINLOC_2 (0), + .PORT_MEM_DKA_PINLOC_3 (0), + .PORT_MEM_DKA_PINLOC_4 (0), + .PORT_MEM_DKA_PINLOC_5 (0), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_N_WIDTH (1), + .PORT_MEM_DKA_N_PINLOC_0 (0), + .PORT_MEM_DKA_N_PINLOC_1 (0), + .PORT_MEM_DKA_N_PINLOC_2 (0), + .PORT_MEM_DKA_N_PINLOC_3 (0), + .PORT_MEM_DKA_N_PINLOC_4 (0), + .PORT_MEM_DKA_N_PINLOC_5 (0), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_WIDTH (1), + .PORT_MEM_DKB_PINLOC_0 (0), + .PORT_MEM_DKB_PINLOC_1 (0), + .PORT_MEM_DKB_PINLOC_2 (0), + .PORT_MEM_DKB_PINLOC_3 (0), + .PORT_MEM_DKB_PINLOC_4 (0), + .PORT_MEM_DKB_PINLOC_5 (0), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_N_WIDTH (1), + .PORT_MEM_DKB_N_PINLOC_0 (0), + .PORT_MEM_DKB_N_PINLOC_1 (0), + .PORT_MEM_DKB_N_PINLOC_2 (0), + .PORT_MEM_DKB_N_PINLOC_3 (0), + .PORT_MEM_DKB_N_PINLOC_4 (0), + .PORT_MEM_DKB_N_PINLOC_5 (0), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_WIDTH (1), + .PORT_MEM_K_PINLOC_0 (0), + .PORT_MEM_K_PINLOC_1 (0), + .PORT_MEM_K_PINLOC_2 (0), + .PORT_MEM_K_PINLOC_3 (0), + .PORT_MEM_K_PINLOC_4 (0), + .PORT_MEM_K_PINLOC_5 (0), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_N_WIDTH (1), + .PORT_MEM_K_N_PINLOC_0 (0), + .PORT_MEM_K_N_PINLOC_1 (0), + .PORT_MEM_K_N_PINLOC_2 (0), + .PORT_MEM_K_N_PINLOC_3 (0), + .PORT_MEM_K_N_PINLOC_4 (0), + .PORT_MEM_K_N_PINLOC_5 (0), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_A_WIDTH (17), + .PORT_MEM_A_PINLOC_0 (64024593), + .PORT_MEM_A_PINLOC_1 (67173438), + .PORT_MEM_A_PINLOC_2 (70322241), + .PORT_MEM_A_PINLOC_3 (73471044), + .PORT_MEM_A_PINLOC_4 (79768647), + .PORT_MEM_A_PINLOC_5 (82917453), + .PORT_MEM_A_PINLOC_6 (0), + .PORT_MEM_A_PINLOC_7 (0), + .PORT_MEM_A_PINLOC_8 (0), + .PORT_MEM_A_PINLOC_9 (0), + .PORT_MEM_A_PINLOC_10 (0), + .PORT_MEM_A_PINLOC_11 (0), + .PORT_MEM_A_PINLOC_12 (0), + .PORT_MEM_A_PINLOC_13 (0), + .PORT_MEM_A_PINLOC_14 (0), + .PORT_MEM_A_PINLOC_15 (0), + .PORT_MEM_A_PINLOC_16 (0), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_BA_WIDTH (2), + .PORT_MEM_BA_PINLOC_0 (86066178), + .PORT_MEM_BA_PINLOC_1 (0), + .PORT_MEM_BA_PINLOC_2 (0), + .PORT_MEM_BA_PINLOC_3 (0), + .PORT_MEM_BA_PINLOC_4 (0), + .PORT_MEM_BA_PINLOC_5 (0), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_BG_WIDTH (2), + .PORT_MEM_BG_PINLOC_0 (50416642), + .PORT_MEM_BG_PINLOC_1 (0), + .PORT_MEM_BG_PINLOC_2 (0), + .PORT_MEM_BG_PINLOC_3 (0), + .PORT_MEM_BG_PINLOC_4 (0), + .PORT_MEM_BG_PINLOC_5 (0), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_C_WIDTH (1), + .PORT_MEM_C_PINLOC_0 (0), + .PORT_MEM_C_PINLOC_1 (0), + .PORT_MEM_C_PINLOC_2 (0), + .PORT_MEM_C_PINLOC_3 (0), + .PORT_MEM_C_PINLOC_4 (0), + .PORT_MEM_C_PINLOC_5 (0), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CKE_WIDTH (1), + .PORT_MEM_CKE_PINLOC_0 (55297), + .PORT_MEM_CKE_PINLOC_1 (0), + .PORT_MEM_CKE_PINLOC_2 (0), + .PORT_MEM_CKE_PINLOC_3 (0), + .PORT_MEM_CKE_PINLOC_4 (0), + .PORT_MEM_CKE_PINLOC_5 (0), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CS_N_WIDTH (1), + .PORT_MEM_CS_N_PINLOC_0 (51201), + .PORT_MEM_CS_N_PINLOC_1 (0), + .PORT_MEM_CS_N_PINLOC_2 (0), + .PORT_MEM_CS_N_PINLOC_3 (0), + .PORT_MEM_CS_N_PINLOC_4 (0), + .PORT_MEM_CS_N_PINLOC_5 (0), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RM_WIDTH (1), + .PORT_MEM_RM_PINLOC_0 (0), + .PORT_MEM_RM_PINLOC_1 (0), + .PORT_MEM_RM_PINLOC_2 (0), + .PORT_MEM_RM_PINLOC_3 (0), + .PORT_MEM_RM_PINLOC_4 (0), + .PORT_MEM_RM_PINLOC_5 (0), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_ODT_WIDTH (1), + .PORT_MEM_ODT_PINLOC_0 (53249), + .PORT_MEM_ODT_PINLOC_1 (0), + .PORT_MEM_ODT_PINLOC_2 (0), + .PORT_MEM_ODT_PINLOC_3 (0), + .PORT_MEM_ODT_PINLOC_4 (0), + .PORT_MEM_ODT_PINLOC_5 (0), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RAS_N_WIDTH (1), + .PORT_MEM_RAS_N_PINLOC_0 (0), + .PORT_MEM_RAS_N_PINLOC_1 (0), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CAS_N_WIDTH (1), + .PORT_MEM_CAS_N_PINLOC_0 (0), + .PORT_MEM_CAS_N_PINLOC_1 (0), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_WE_N_WIDTH (1), + .PORT_MEM_WE_N_PINLOC_0 (0), + .PORT_MEM_WE_N_PINLOC_1 (0), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_RESET_N_WIDTH (1), + .PORT_MEM_RESET_N_PINLOC_0 (50177), + .PORT_MEM_RESET_N_PINLOC_1 (0), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ACT_N_WIDTH (1), + .PORT_MEM_ACT_N_PINLOC_0 (52225), + .PORT_MEM_ACT_N_PINLOC_1 (0), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PAR_WIDTH (1), + .PORT_MEM_PAR_PINLOC_0 (60417), + .PORT_MEM_PAR_PINLOC_1 (0), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CA_WIDTH (1), + .PORT_MEM_CA_PINLOC_0 (0), + .PORT_MEM_CA_PINLOC_1 (0), + .PORT_MEM_CA_PINLOC_2 (0), + .PORT_MEM_CA_PINLOC_3 (0), + .PORT_MEM_CA_PINLOC_4 (0), + .PORT_MEM_CA_PINLOC_5 (0), + .PORT_MEM_CA_PINLOC_6 (0), + .PORT_MEM_CA_PINLOC_7 (0), + .PORT_MEM_CA_PINLOC_8 (0), + .PORT_MEM_CA_PINLOC_9 (0), + .PORT_MEM_CA_PINLOC_10 (0), + .PORT_MEM_CA_PINLOC_11 (0), + .PORT_MEM_CA_PINLOC_12 (0), + .PORT_MEM_CA_PINLOC_13 (0), + .PORT_MEM_CA_PINLOC_14 (0), + .PORT_MEM_CA_PINLOC_15 (0), + .PORT_MEM_CA_PINLOC_16 (0), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_REF_N_WIDTH (1), + .PORT_MEM_REF_N_PINLOC_0 (0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_WPS_N_WIDTH (1), + .PORT_MEM_WPS_N_PINLOC_0 (0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RPS_N_WIDTH (1), + .PORT_MEM_RPS_N_PINLOC_0 (0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DOFF_N_WIDTH (1), + .PORT_MEM_DOFF_N_PINLOC_0 (0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDA_N_WIDTH (1), + .PORT_MEM_LDA_N_PINLOC_0 (0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDB_N_WIDTH (1), + .PORT_MEM_LDB_N_PINLOC_0 (0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWA_N_WIDTH (1), + .PORT_MEM_RWA_N_PINLOC_0 (0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWB_N_WIDTH (1), + .PORT_MEM_RWB_N_PINLOC_0 (0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK0_N_WIDTH (1), + .PORT_MEM_LBK0_N_PINLOC_0 (0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK1_N_WIDTH (1), + .PORT_MEM_LBK1_N_PINLOC_0 (0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_CFG_N_WIDTH (1), + .PORT_MEM_CFG_N_PINLOC_0 (0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AP_WIDTH (1), + .PORT_MEM_AP_PINLOC_0 (0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AINV_WIDTH (1), + .PORT_MEM_AINV_PINLOC_0 (0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DM_WIDTH (1), + .PORT_MEM_DM_PINLOC_0 (0), + .PORT_MEM_DM_PINLOC_1 (0), + .PORT_MEM_DM_PINLOC_2 (0), + .PORT_MEM_DM_PINLOC_3 (0), + .PORT_MEM_DM_PINLOC_4 (0), + .PORT_MEM_DM_PINLOC_5 (0), + .PORT_MEM_DM_PINLOC_6 (0), + .PORT_MEM_DM_PINLOC_7 (0), + .PORT_MEM_DM_PINLOC_8 (0), + .PORT_MEM_DM_PINLOC_9 (0), + .PORT_MEM_DM_PINLOC_10 (0), + .PORT_MEM_DM_PINLOC_11 (0), + .PORT_MEM_DM_PINLOC_12 (0), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_BWS_N_WIDTH (1), + .PORT_MEM_BWS_N_PINLOC_0 (0), + .PORT_MEM_BWS_N_PINLOC_1 (0), + .PORT_MEM_BWS_N_PINLOC_2 (0), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_D_WIDTH (1), + .PORT_MEM_D_PINLOC_0 (0), + .PORT_MEM_D_PINLOC_1 (0), + .PORT_MEM_D_PINLOC_2 (0), + .PORT_MEM_D_PINLOC_3 (0), + .PORT_MEM_D_PINLOC_4 (0), + .PORT_MEM_D_PINLOC_5 (0), + .PORT_MEM_D_PINLOC_6 (0), + .PORT_MEM_D_PINLOC_7 (0), + .PORT_MEM_D_PINLOC_8 (0), + .PORT_MEM_D_PINLOC_9 (0), + .PORT_MEM_D_PINLOC_10 (0), + .PORT_MEM_D_PINLOC_11 (0), + .PORT_MEM_D_PINLOC_12 (0), + .PORT_MEM_D_PINLOC_13 (0), + .PORT_MEM_D_PINLOC_14 (0), + .PORT_MEM_D_PINLOC_15 (0), + .PORT_MEM_D_PINLOC_16 (0), + .PORT_MEM_D_PINLOC_17 (0), + .PORT_MEM_D_PINLOC_18 (0), + .PORT_MEM_D_PINLOC_19 (0), + .PORT_MEM_D_PINLOC_20 (0), + .PORT_MEM_D_PINLOC_21 (0), + .PORT_MEM_D_PINLOC_22 (0), + .PORT_MEM_D_PINLOC_23 (0), + .PORT_MEM_D_PINLOC_24 (0), + .PORT_MEM_D_PINLOC_25 (0), + .PORT_MEM_D_PINLOC_26 (0), + .PORT_MEM_D_PINLOC_27 (0), + .PORT_MEM_D_PINLOC_28 (0), + .PORT_MEM_D_PINLOC_29 (0), + .PORT_MEM_D_PINLOC_30 (0), + .PORT_MEM_D_PINLOC_31 (0), + .PORT_MEM_D_PINLOC_32 (0), + .PORT_MEM_D_PINLOC_33 (0), + .PORT_MEM_D_PINLOC_34 (0), + .PORT_MEM_D_PINLOC_35 (0), + .PORT_MEM_D_PINLOC_36 (0), + .PORT_MEM_D_PINLOC_37 (0), + .PORT_MEM_D_PINLOC_38 (0), + .PORT_MEM_D_PINLOC_39 (0), + .PORT_MEM_D_PINLOC_40 (0), + .PORT_MEM_D_PINLOC_41 (0), + .PORT_MEM_D_PINLOC_42 (0), + .PORT_MEM_D_PINLOC_43 (0), + .PORT_MEM_D_PINLOC_44 (0), + .PORT_MEM_D_PINLOC_45 (0), + .PORT_MEM_D_PINLOC_46 (0), + .PORT_MEM_D_PINLOC_47 (0), + .PORT_MEM_D_PINLOC_48 (0), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQ_WIDTH (64), + .PORT_MEM_DQ_PINLOC_0 (2098240), + .PORT_MEM_DQ_PINLOC_1 (7346179), + .PORT_MEM_DQ_PINLOC_2 (10494984), + .PORT_MEM_DQ_PINLOC_3 (15742989), + .PORT_MEM_DQ_PINLOC_4 (20990994), + .PORT_MEM_DQ_PINLOC_5 (26236949), + .PORT_MEM_DQ_PINLOC_6 (31484954), + .PORT_MEM_DQ_PINLOC_7 (34635807), + .PORT_MEM_DQ_PINLOC_8 (39883810), + .PORT_MEM_DQ_PINLOC_9 (45131815), + .PORT_MEM_DQ_PINLOC_10 (48280620), + .PORT_MEM_DQ_PINLOC_11 (91314261), + .PORT_MEM_DQ_PINLOC_12 (96562266), + .PORT_MEM_DQ_PINLOC_13 (101808221), + .PORT_MEM_DQ_PINLOC_14 (107056226), + .PORT_MEM_DQ_PINLOC_15 (110207079), + .PORT_MEM_DQ_PINLOC_16 (115455082), + .PORT_MEM_DQ_PINLOC_17 (120703087), + .PORT_MEM_DQ_PINLOC_18 (123851892), + .PORT_MEM_DQ_PINLOC_19 (129099897), + .PORT_MEM_DQ_PINLOC_20 (134347902), + .PORT_MEM_DQ_PINLOC_21 (133249), + .PORT_MEM_DQ_PINLOC_22 (0), + .PORT_MEM_DQ_PINLOC_23 (0), + .PORT_MEM_DQ_PINLOC_24 (0), + .PORT_MEM_DQ_PINLOC_25 (0), + .PORT_MEM_DQ_PINLOC_26 (0), + .PORT_MEM_DQ_PINLOC_27 (0), + .PORT_MEM_DQ_PINLOC_28 (0), + .PORT_MEM_DQ_PINLOC_29 (0), + .PORT_MEM_DQ_PINLOC_30 (0), + .PORT_MEM_DQ_PINLOC_31 (0), + .PORT_MEM_DQ_PINLOC_32 (0), + .PORT_MEM_DQ_PINLOC_33 (0), + .PORT_MEM_DQ_PINLOC_34 (0), + .PORT_MEM_DQ_PINLOC_35 (0), + .PORT_MEM_DQ_PINLOC_36 (0), + .PORT_MEM_DQ_PINLOC_37 (0), + .PORT_MEM_DQ_PINLOC_38 (0), + .PORT_MEM_DQ_PINLOC_39 (0), + .PORT_MEM_DQ_PINLOC_40 (0), + .PORT_MEM_DQ_PINLOC_41 (0), + .PORT_MEM_DQ_PINLOC_42 (0), + .PORT_MEM_DQ_PINLOC_43 (0), + .PORT_MEM_DQ_PINLOC_44 (0), + .PORT_MEM_DQ_PINLOC_45 (0), + .PORT_MEM_DQ_PINLOC_46 (0), + .PORT_MEM_DQ_PINLOC_47 (0), + .PORT_MEM_DQ_PINLOC_48 (0), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DBI_N_WIDTH (8), + .PORT_MEM_DBI_N_PINLOC_0 (24128520), + .PORT_MEM_DBI_N_PINLOC_1 (99662883), + .PORT_MEM_DBI_N_PINLOC_2 (137485419), + .PORT_MEM_DBI_N_PINLOC_3 (0), + .PORT_MEM_DBI_N_PINLOC_4 (0), + .PORT_MEM_DBI_N_PINLOC_5 (0), + .PORT_MEM_DBI_N_PINLOC_6 (0), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (7), + .PORT_MEM_DQA_WIDTH (1), + .PORT_MEM_DQA_PINLOC_0 (0), + .PORT_MEM_DQA_PINLOC_1 (0), + .PORT_MEM_DQA_PINLOC_2 (0), + .PORT_MEM_DQA_PINLOC_3 (0), + .PORT_MEM_DQA_PINLOC_4 (0), + .PORT_MEM_DQA_PINLOC_5 (0), + .PORT_MEM_DQA_PINLOC_6 (0), + .PORT_MEM_DQA_PINLOC_7 (0), + .PORT_MEM_DQA_PINLOC_8 (0), + .PORT_MEM_DQA_PINLOC_9 (0), + .PORT_MEM_DQA_PINLOC_10 (0), + .PORT_MEM_DQA_PINLOC_11 (0), + .PORT_MEM_DQA_PINLOC_12 (0), + .PORT_MEM_DQA_PINLOC_13 (0), + .PORT_MEM_DQA_PINLOC_14 (0), + .PORT_MEM_DQA_PINLOC_15 (0), + .PORT_MEM_DQA_PINLOC_16 (0), + .PORT_MEM_DQA_PINLOC_17 (0), + .PORT_MEM_DQA_PINLOC_18 (0), + .PORT_MEM_DQA_PINLOC_19 (0), + .PORT_MEM_DQA_PINLOC_20 (0), + .PORT_MEM_DQA_PINLOC_21 (0), + .PORT_MEM_DQA_PINLOC_22 (0), + .PORT_MEM_DQA_PINLOC_23 (0), + .PORT_MEM_DQA_PINLOC_24 (0), + .PORT_MEM_DQA_PINLOC_25 (0), + .PORT_MEM_DQA_PINLOC_26 (0), + .PORT_MEM_DQA_PINLOC_27 (0), + .PORT_MEM_DQA_PINLOC_28 (0), + .PORT_MEM_DQA_PINLOC_29 (0), + .PORT_MEM_DQA_PINLOC_30 (0), + .PORT_MEM_DQA_PINLOC_31 (0), + .PORT_MEM_DQA_PINLOC_32 (0), + .PORT_MEM_DQA_PINLOC_33 (0), + .PORT_MEM_DQA_PINLOC_34 (0), + .PORT_MEM_DQA_PINLOC_35 (0), + .PORT_MEM_DQA_PINLOC_36 (0), + .PORT_MEM_DQA_PINLOC_37 (0), + .PORT_MEM_DQA_PINLOC_38 (0), + .PORT_MEM_DQA_PINLOC_39 (0), + .PORT_MEM_DQA_PINLOC_40 (0), + .PORT_MEM_DQA_PINLOC_41 (0), + .PORT_MEM_DQA_PINLOC_42 (0), + .PORT_MEM_DQA_PINLOC_43 (0), + .PORT_MEM_DQA_PINLOC_44 (0), + .PORT_MEM_DQA_PINLOC_45 (0), + .PORT_MEM_DQA_PINLOC_46 (0), + .PORT_MEM_DQA_PINLOC_47 (0), + .PORT_MEM_DQA_PINLOC_48 (0), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQB_WIDTH (1), + .PORT_MEM_DQB_PINLOC_0 (0), + .PORT_MEM_DQB_PINLOC_1 (0), + .PORT_MEM_DQB_PINLOC_2 (0), + .PORT_MEM_DQB_PINLOC_3 (0), + .PORT_MEM_DQB_PINLOC_4 (0), + .PORT_MEM_DQB_PINLOC_5 (0), + .PORT_MEM_DQB_PINLOC_6 (0), + .PORT_MEM_DQB_PINLOC_7 (0), + .PORT_MEM_DQB_PINLOC_8 (0), + .PORT_MEM_DQB_PINLOC_9 (0), + .PORT_MEM_DQB_PINLOC_10 (0), + .PORT_MEM_DQB_PINLOC_11 (0), + .PORT_MEM_DQB_PINLOC_12 (0), + .PORT_MEM_DQB_PINLOC_13 (0), + .PORT_MEM_DQB_PINLOC_14 (0), + .PORT_MEM_DQB_PINLOC_15 (0), + .PORT_MEM_DQB_PINLOC_16 (0), + .PORT_MEM_DQB_PINLOC_17 (0), + .PORT_MEM_DQB_PINLOC_18 (0), + .PORT_MEM_DQB_PINLOC_19 (0), + .PORT_MEM_DQB_PINLOC_20 (0), + .PORT_MEM_DQB_PINLOC_21 (0), + .PORT_MEM_DQB_PINLOC_22 (0), + .PORT_MEM_DQB_PINLOC_23 (0), + .PORT_MEM_DQB_PINLOC_24 (0), + .PORT_MEM_DQB_PINLOC_25 (0), + .PORT_MEM_DQB_PINLOC_26 (0), + .PORT_MEM_DQB_PINLOC_27 (0), + .PORT_MEM_DQB_PINLOC_28 (0), + .PORT_MEM_DQB_PINLOC_29 (0), + .PORT_MEM_DQB_PINLOC_30 (0), + .PORT_MEM_DQB_PINLOC_31 (0), + .PORT_MEM_DQB_PINLOC_32 (0), + .PORT_MEM_DQB_PINLOC_33 (0), + .PORT_MEM_DQB_PINLOC_34 (0), + .PORT_MEM_DQB_PINLOC_35 (0), + .PORT_MEM_DQB_PINLOC_36 (0), + .PORT_MEM_DQB_PINLOC_37 (0), + .PORT_MEM_DQB_PINLOC_38 (0), + .PORT_MEM_DQB_PINLOC_39 (0), + .PORT_MEM_DQB_PINLOC_40 (0), + .PORT_MEM_DQB_PINLOC_41 (0), + .PORT_MEM_DQB_PINLOC_42 (0), + .PORT_MEM_DQB_PINLOC_43 (0), + .PORT_MEM_DQB_PINLOC_44 (0), + .PORT_MEM_DQB_PINLOC_45 (0), + .PORT_MEM_DQB_PINLOC_46 (0), + .PORT_MEM_DQB_PINLOC_47 (0), + .PORT_MEM_DQB_PINLOC_48 (0), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DINVA_WIDTH (1), + .PORT_MEM_DINVA_PINLOC_0 (0), + .PORT_MEM_DINVA_PINLOC_1 (0), + .PORT_MEM_DINVA_PINLOC_2 (0), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_DINVB_WIDTH (1), + .PORT_MEM_DINVB_PINLOC_0 (0), + .PORT_MEM_DINVB_PINLOC_1 (0), + .PORT_MEM_DINVB_PINLOC_2 (0), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_Q_WIDTH (1), + .PORT_MEM_Q_PINLOC_0 (0), + .PORT_MEM_Q_PINLOC_1 (0), + .PORT_MEM_Q_PINLOC_2 (0), + .PORT_MEM_Q_PINLOC_3 (0), + .PORT_MEM_Q_PINLOC_4 (0), + .PORT_MEM_Q_PINLOC_5 (0), + .PORT_MEM_Q_PINLOC_6 (0), + .PORT_MEM_Q_PINLOC_7 (0), + .PORT_MEM_Q_PINLOC_8 (0), + .PORT_MEM_Q_PINLOC_9 (0), + .PORT_MEM_Q_PINLOC_10 (0), + .PORT_MEM_Q_PINLOC_11 (0), + .PORT_MEM_Q_PINLOC_12 (0), + .PORT_MEM_Q_PINLOC_13 (0), + .PORT_MEM_Q_PINLOC_14 (0), + .PORT_MEM_Q_PINLOC_15 (0), + .PORT_MEM_Q_PINLOC_16 (0), + .PORT_MEM_Q_PINLOC_17 (0), + .PORT_MEM_Q_PINLOC_18 (0), + .PORT_MEM_Q_PINLOC_19 (0), + .PORT_MEM_Q_PINLOC_20 (0), + .PORT_MEM_Q_PINLOC_21 (0), + .PORT_MEM_Q_PINLOC_22 (0), + .PORT_MEM_Q_PINLOC_23 (0), + .PORT_MEM_Q_PINLOC_24 (0), + .PORT_MEM_Q_PINLOC_25 (0), + .PORT_MEM_Q_PINLOC_26 (0), + .PORT_MEM_Q_PINLOC_27 (0), + .PORT_MEM_Q_PINLOC_28 (0), + .PORT_MEM_Q_PINLOC_29 (0), + .PORT_MEM_Q_PINLOC_30 (0), + .PORT_MEM_Q_PINLOC_31 (0), + .PORT_MEM_Q_PINLOC_32 (0), + .PORT_MEM_Q_PINLOC_33 (0), + .PORT_MEM_Q_PINLOC_34 (0), + .PORT_MEM_Q_PINLOC_35 (0), + .PORT_MEM_Q_PINLOC_36 (0), + .PORT_MEM_Q_PINLOC_37 (0), + .PORT_MEM_Q_PINLOC_38 (0), + .PORT_MEM_Q_PINLOC_39 (0), + .PORT_MEM_Q_PINLOC_40 (0), + .PORT_MEM_Q_PINLOC_41 (0), + .PORT_MEM_Q_PINLOC_42 (0), + .PORT_MEM_Q_PINLOC_43 (0), + .PORT_MEM_Q_PINLOC_44 (0), + .PORT_MEM_Q_PINLOC_45 (0), + .PORT_MEM_Q_PINLOC_46 (0), + .PORT_MEM_Q_PINLOC_47 (0), + .PORT_MEM_Q_PINLOC_48 (0), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQS_WIDTH (8), + .PORT_MEM_DQS_PINLOC_0 (16781320), + .PORT_MEM_DQS_PINLOC_1 (92315676), + .PORT_MEM_DQS_PINLOC_2 (130138212), + .PORT_MEM_DQS_PINLOC_3 (0), + .PORT_MEM_DQS_PINLOC_4 (0), + .PORT_MEM_DQS_PINLOC_5 (0), + .PORT_MEM_DQS_PINLOC_6 (0), + .PORT_MEM_DQS_PINLOC_7 (0), + .PORT_MEM_DQS_PINLOC_8 (0), + .PORT_MEM_DQS_PINLOC_9 (0), + .PORT_MEM_DQS_PINLOC_10 (0), + .PORT_MEM_DQS_PINLOC_11 (0), + .PORT_MEM_DQS_PINLOC_12 (0), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_DQS_N_WIDTH (8), + .PORT_MEM_DQS_N_PINLOC_0 (17830920), + .PORT_MEM_DQS_N_PINLOC_1 (93365277), + .PORT_MEM_DQS_N_PINLOC_2 (131187813), + .PORT_MEM_DQS_N_PINLOC_3 (0), + .PORT_MEM_DQS_N_PINLOC_4 (0), + .PORT_MEM_DQS_N_PINLOC_5 (0), + .PORT_MEM_DQS_N_PINLOC_6 (0), + .PORT_MEM_DQS_N_PINLOC_7 (0), + .PORT_MEM_DQS_N_PINLOC_8 (0), + .PORT_MEM_DQS_N_PINLOC_9 (0), + .PORT_MEM_DQS_N_PINLOC_10 (0), + .PORT_MEM_DQS_N_PINLOC_11 (0), + .PORT_MEM_DQS_N_PINLOC_12 (0), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_QK_WIDTH (1), + .PORT_MEM_QK_PINLOC_0 (0), + .PORT_MEM_QK_PINLOC_1 (0), + .PORT_MEM_QK_PINLOC_2 (0), + .PORT_MEM_QK_PINLOC_3 (0), + .PORT_MEM_QK_PINLOC_4 (0), + .PORT_MEM_QK_PINLOC_5 (0), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QK_N_WIDTH (1), + .PORT_MEM_QK_N_PINLOC_0 (0), + .PORT_MEM_QK_N_PINLOC_1 (0), + .PORT_MEM_QK_N_PINLOC_2 (0), + .PORT_MEM_QK_N_PINLOC_3 (0), + .PORT_MEM_QK_N_PINLOC_4 (0), + .PORT_MEM_QK_N_PINLOC_5 (0), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_WIDTH (1), + .PORT_MEM_QKA_PINLOC_0 (0), + .PORT_MEM_QKA_PINLOC_1 (0), + .PORT_MEM_QKA_PINLOC_2 (0), + .PORT_MEM_QKA_PINLOC_3 (0), + .PORT_MEM_QKA_PINLOC_4 (0), + .PORT_MEM_QKA_PINLOC_5 (0), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_N_WIDTH (1), + .PORT_MEM_QKA_N_PINLOC_0 (0), + .PORT_MEM_QKA_N_PINLOC_1 (0), + .PORT_MEM_QKA_N_PINLOC_2 (0), + .PORT_MEM_QKA_N_PINLOC_3 (0), + .PORT_MEM_QKA_N_PINLOC_4 (0), + .PORT_MEM_QKA_N_PINLOC_5 (0), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_WIDTH (1), + .PORT_MEM_QKB_PINLOC_0 (0), + .PORT_MEM_QKB_PINLOC_1 (0), + .PORT_MEM_QKB_PINLOC_2 (0), + .PORT_MEM_QKB_PINLOC_3 (0), + .PORT_MEM_QKB_PINLOC_4 (0), + .PORT_MEM_QKB_PINLOC_5 (0), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_N_WIDTH (1), + .PORT_MEM_QKB_N_PINLOC_0 (0), + .PORT_MEM_QKB_N_PINLOC_1 (0), + .PORT_MEM_QKB_N_PINLOC_2 (0), + .PORT_MEM_QKB_N_PINLOC_3 (0), + .PORT_MEM_QKB_N_PINLOC_4 (0), + .PORT_MEM_QKB_N_PINLOC_5 (0), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CQ_WIDTH (1), + .PORT_MEM_CQ_PINLOC_0 (0), + .PORT_MEM_CQ_PINLOC_1 (0), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CQ_N_WIDTH (1), + .PORT_MEM_CQ_N_PINLOC_0 (0), + .PORT_MEM_CQ_N_PINLOC_1 (0), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_ALERT_N_PINLOC_0 (1), + .PORT_MEM_ALERT_N_PINLOC_1 (0), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PE_N_WIDTH (1), + .PORT_MEM_PE_N_PINLOC_0 (0), + .PORT_MEM_PE_N_PINLOC_1 (0), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (32), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (32), + .PORT_AFI_RLAT_WIDTH (6), + .PORT_AFI_WLAT_WIDTH (6), + .PORT_AFI_SEQ_BUSY_WIDTH (4), + .PORT_AFI_ADDR_WIDTH (1), + .PORT_AFI_BA_WIDTH (1), + .PORT_AFI_BG_WIDTH (1), + .PORT_AFI_C_WIDTH (1), + .PORT_AFI_CKE_WIDTH (1), + .PORT_AFI_CS_N_WIDTH (1), + .PORT_AFI_RM_WIDTH (1), + .PORT_AFI_ODT_WIDTH (1), + .PORT_AFI_RAS_N_WIDTH (1), + .PORT_AFI_CAS_N_WIDTH (1), + .PORT_AFI_WE_N_WIDTH (1), + .PORT_AFI_RST_N_WIDTH (1), + .PORT_AFI_ACT_N_WIDTH (1), + .PORT_AFI_PAR_WIDTH (1), + .PORT_AFI_CA_WIDTH (1), + .PORT_AFI_REF_N_WIDTH (1), + .PORT_AFI_WPS_N_WIDTH (1), + .PORT_AFI_RPS_N_WIDTH (1), + .PORT_AFI_DOFF_N_WIDTH (1), + .PORT_AFI_LD_N_WIDTH (1), + .PORT_AFI_RW_N_WIDTH (1), + .PORT_AFI_LBK0_N_WIDTH (1), + .PORT_AFI_LBK1_N_WIDTH (1), + .PORT_AFI_CFG_N_WIDTH (1), + .PORT_AFI_AP_WIDTH (1), + .PORT_AFI_AINV_WIDTH (1), + .PORT_AFI_DM_WIDTH (1), + .PORT_AFI_DM_N_WIDTH (1), + .PORT_AFI_BWS_N_WIDTH (1), + .PORT_AFI_RDATA_DBI_N_WIDTH (1), + .PORT_AFI_WDATA_DBI_N_WIDTH (1), + .PORT_AFI_RDATA_DINV_WIDTH (1), + .PORT_AFI_WDATA_DINV_WIDTH (1), + .PORT_AFI_DQS_BURST_WIDTH (1), + .PORT_AFI_WDATA_VALID_WIDTH (1), + .PORT_AFI_WDATA_WIDTH (1), + .PORT_AFI_RDATA_EN_FULL_WIDTH (1), + .PORT_AFI_RDATA_WIDTH (1), + .PORT_AFI_RDATA_VALID_WIDTH (1), + .PORT_AFI_RRANK_WIDTH (1), + .PORT_AFI_WRANK_WIDTH (1), + .PORT_AFI_ALERT_N_WIDTH (1), + .PORT_AFI_PE_N_WIDTH (1), + .PORT_CTRL_AST_CMD_DATA_WIDTH (1), + .PORT_CTRL_AST_WR_DATA_WIDTH (1), + .PORT_CTRL_AST_RD_DATA_WIDTH (1), + .PORT_CTRL_AMM_ADDRESS_WIDTH (26), + .PORT_CTRL_AMM_RDATA_WIDTH (512), + .PORT_CTRL_AMM_WDATA_WIDTH (512), + .PORT_CTRL_AMM_BCOUNT_WIDTH (7), + .PORT_CTRL_AMM_BYTEEN_WIDTH (64), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (16), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (15), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (13), + .PORT_CTRL_ECC_READ_INFO_WIDTH (3), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (3), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (12), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (10), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (2), + .PORT_HPS_EMIF_H2E_WIDTH (4096), + .PORT_HPS_EMIF_E2H_WIDTH (4096), + .PORT_HPS_EMIF_H2E_GP_WIDTH (2), + .PORT_HPS_EMIF_E2H_GP_WIDTH (1), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (24), + .PORT_CAL_DEBUG_RDATA_WIDTH (32), + .PORT_CAL_DEBUG_WDATA_WIDTH (32), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (4), + .PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH (24), + .PORT_CAL_DEBUG_OUT_RDATA_WIDTH (32), + .PORT_CAL_DEBUG_OUT_WDATA_WIDTH (32), + .PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH (4), + .PORT_CAL_MASTER_ADDRESS_WIDTH (16), + .PORT_CAL_MASTER_RDATA_WIDTH (32), + .PORT_CAL_MASTER_WDATA_WIDTH (32), + .PORT_CAL_MASTER_BYTEEN_WIDTH (4), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (8), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (8), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (9), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (8), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (8), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (4), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (3), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (2), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (2), + .PLL_VCO_FREQ_MHZ_INT (1067), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (1), + .PLL_PHY_CLK_VCO_PHASE (1), + .PLL_VCO_FREQ_PS_STR ("938 ps"), + .PLL_REF_CLK_FREQ_PS_STR ("3752 ps"), + .PLL_REF_CLK_FREQ_PS (3752), + .PLL_SIM_VCO_FREQ_PS (944), + .PLL_SIM_PHYCLK_0_FREQ_PS (1888), + .PLL_SIM_PHYCLK_1_FREQ_PS (3776), + .PLL_SIM_PHYCLK_FB_FREQ_PS (3776), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (118), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (6608), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (6608), + .PLL_M_CNT_HIGH (2), + .PLL_M_CNT_LOW (2), + .PLL_N_CNT_HIGH (256), + .PLL_N_CNT_LOW (256), + .PLL_M_CNT_BYPASS_EN ("false"), + .PLL_N_CNT_BYPASS_EN ("true"), + .PLL_M_CNT_EVEN_DUTY_EN ("false"), + .PLL_N_CNT_EVEN_DUTY_EN ("false"), + .PLL_FBCLK_MUX_1 ("pll_fbclk_mux_1_glb"), + .PLL_FBCLK_MUX_2 ("pll_fbclk_mux_2_m_cnt"), + .PLL_M_CNT_IN_SRC ("c_m_cnt_in_src_ph_mux_clk"), + .PLL_CP_SETTING ("pll_cp_setting15"), + .PLL_BW_CTRL ("pll_bw_res_setting2"), + .PLL_BW_SEL ("high"), + .PLL_C_CNT_HIGH_0 (2), + .PLL_C_CNT_LOW_0 (2), + .PLL_C_CNT_PRST_0 (1), + .PLL_C_CNT_PH_MUX_PRST_0 (1), + .PLL_C_CNT_BYPASS_EN_0 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_0 ("false"), + .PLL_C_CNT_FREQ_PS_STR_0 ("3752 ps"), + .PLL_C_CNT_PHASE_PS_STR_0 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_0 (50), + .PLL_C_CNT_OUT_EN_0 ("true"), + .PLL_C_CNT_HIGH_1 (1), + .PLL_C_CNT_LOW_1 (1), + .PLL_C_CNT_PRST_1 (1), + .PLL_C_CNT_PH_MUX_PRST_1 (1), + .PLL_C_CNT_BYPASS_EN_1 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_1 ("false"), + .PLL_C_CNT_FREQ_PS_STR_1 ("1876 ps"), + .PLL_C_CNT_PHASE_PS_STR_1 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_1 (50), + .PLL_C_CNT_OUT_EN_1 ("true"), + .PLL_C_CNT_HIGH_2 (2), + .PLL_C_CNT_LOW_2 (2), + .PLL_C_CNT_PRST_2 (1), + .PLL_C_CNT_PH_MUX_PRST_2 (1), + .PLL_C_CNT_BYPASS_EN_2 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_2 ("false"), + .PLL_C_CNT_FREQ_PS_STR_2 ("3752 ps"), + .PLL_C_CNT_PHASE_PS_STR_2 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_2 (50), + .PLL_C_CNT_OUT_EN_2 ("true"), + .PLL_C_CNT_HIGH_3 (4), + .PLL_C_CNT_LOW_3 (3), + .PLL_C_CNT_PRST_3 (1), + .PLL_C_CNT_PH_MUX_PRST_3 (0), + .PLL_C_CNT_BYPASS_EN_3 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_3 ("true"), + .PLL_C_CNT_FREQ_PS_STR_3 ("6566 ps"), + .PLL_C_CNT_PHASE_PS_STR_3 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_3 (50), + .PLL_C_CNT_OUT_EN_3 ("true"), + .PLL_C_CNT_HIGH_4 (4), + .PLL_C_CNT_LOW_4 (3), + .PLL_C_CNT_PRST_4 (1), + .PLL_C_CNT_PH_MUX_PRST_4 (0), + .PLL_C_CNT_BYPASS_EN_4 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_4 ("true"), + .PLL_C_CNT_FREQ_PS_STR_4 ("6566 ps"), + .PLL_C_CNT_PHASE_PS_STR_4 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_4 (50), + .PLL_C_CNT_OUT_EN_4 ("true"), + .PLL_C_CNT_HIGH_5 (256), + .PLL_C_CNT_LOW_5 (256), + .PLL_C_CNT_PRST_5 (1), + .PLL_C_CNT_PH_MUX_PRST_5 (0), + .PLL_C_CNT_BYPASS_EN_5 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_5 ("false"), + .PLL_C_CNT_FREQ_PS_STR_5 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_5 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_5 (50), + .PLL_C_CNT_OUT_EN_5 ("false"), + .PLL_C_CNT_HIGH_6 (256), + .PLL_C_CNT_LOW_6 (256), + .PLL_C_CNT_PRST_6 (1), + .PLL_C_CNT_PH_MUX_PRST_6 (0), + .PLL_C_CNT_BYPASS_EN_6 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_6 ("false"), + .PLL_C_CNT_FREQ_PS_STR_6 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_6 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_6 (50), + .PLL_C_CNT_OUT_EN_6 ("false"), + .PLL_C_CNT_HIGH_7 (256), + .PLL_C_CNT_LOW_7 (256), + .PLL_C_CNT_PRST_7 (1), + .PLL_C_CNT_PH_MUX_PRST_7 (0), + .PLL_C_CNT_BYPASS_EN_7 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_7 ("false"), + .PLL_C_CNT_FREQ_PS_STR_7 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_7 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_7 (50), + .PLL_C_CNT_OUT_EN_7 ("false"), + .PLL_C_CNT_HIGH_8 (256), + .PLL_C_CNT_LOW_8 (256), + .PLL_C_CNT_PRST_8 (1), + .PLL_C_CNT_PH_MUX_PRST_8 (0), + .PLL_C_CNT_BYPASS_EN_8 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_8 ("false"), + .PLL_C_CNT_FREQ_PS_STR_8 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_8 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_8 (50), + .PLL_C_CNT_OUT_EN_8 ("false") + ) arch ( + .global_reset_n (global_reset_n), // global_reset_n.reset_n + .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk + .oct_rzqin (oct_rzqin), // oct.oct_rzqin + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .local_cal_success (local_cal_success), // status.local_cal_success + .local_cal_fail (local_cal_fail), // .local_cal_fail + .emif_usr_reset_n (emif_usr_reset_n), // emif_usr_reset_n.reset_n + .emif_usr_clk (emif_usr_clk), // emif_usr_clk.clk + .cal_slave_reset_n (arch_cal_slave_reset_n_reset), // cal_slave_reset_n.reset_n + .cal_slave_clk (arch_cal_slave_clk_clk), // cal_slave_clk.clk + .cal_slave_reset_n_in (arch_cal_slave_reset_n_reset), // cal_slave_reset_n_in.reset_n + .cal_slave_clk_in (arch_cal_slave_clk_clk), // cal_slave_clk_in.clk + .clks_sharing_master_out (clks_sharing_master_out), // clks_sharing_master_out.clks_sharing + .amm_ready_0 (amm_ready_0), // ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // .read + .amm_write_0 (amm_write_0), // .write + .amm_address_0 (amm_address_0), // .address + .amm_readdata_0 (amm_readdata_0), // .readdata + .amm_writedata_0 (amm_writedata_0), // .writedata + .amm_burstcount_0 (amm_burstcount_0), // .burstcount + .amm_byteenable_0 (amm_byteenable_0), // .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0), // .readdatavalid + .cal_master_waitrequest (arch_cal_master_waitrequest), // cal_master.waitrequest + .cal_master_read (arch_cal_master_read), // .read + .cal_master_write (arch_cal_master_write), // .write + .cal_master_addr (arch_cal_master_address), // .address + .cal_master_read_data (arch_cal_master_readdata), // .readdata + .cal_master_write_data (arch_cal_master_writedata), // .writedata + .cal_master_byteenable (arch_cal_master_byteenable), // .byteenable + .cal_master_read_data_valid (arch_cal_master_readdatavalid), // .readdatavalid + .cal_master_burstcount (arch_cal_master_burstcount), // .burstcount + .cal_master_debugaccess (arch_cal_master_debugaccess), // .debugaccess + .pll_locked (), // (terminated) + .pll_extra_clk_0 (), // (terminated) + .pll_extra_clk_1 (), // (terminated) + .pll_extra_clk_2 (), // (terminated) + .pll_extra_clk_3 (), // (terminated) + .mem_c (), // (terminated) + .mem_rm (), // (terminated) + .mem_dk (), // (terminated) + .mem_dk_n (), // (terminated) + .mem_dka (), // (terminated) + .mem_dka_n (), // (terminated) + .mem_dkb (), // (terminated) + .mem_dkb_n (), // (terminated) + .mem_k (), // (terminated) + .mem_k_n (), // (terminated) + .mem_ras_n (), // (terminated) + .mem_cas_n (), // (terminated) + .mem_we_n (), // (terminated) + .mem_ca (), // (terminated) + .mem_ref_n (), // (terminated) + .mem_wps_n (), // (terminated) + .mem_rps_n (), // (terminated) + .mem_doff_n (), // (terminated) + .mem_lda_n (), // (terminated) + .mem_ldb_n (), // (terminated) + .mem_rwa_n (), // (terminated) + .mem_rwb_n (), // (terminated) + .mem_lbk0_n (), // (terminated) + .mem_lbk1_n (), // (terminated) + .mem_cfg_n (), // (terminated) + .mem_ap (), // (terminated) + .mem_ainv (), // (terminated) + .mem_dm (), // (terminated) + .mem_bws_n (), // (terminated) + .mem_d (), // (terminated) + .mem_dqa (), // (terminated) + .mem_dqb (), // (terminated) + .mem_dinva (), // (terminated) + .mem_dinvb (), // (terminated) + .mem_q (1'b0), // (terminated) + .mem_qk (1'b0), // (terminated) + .mem_qk_n (1'b0), // (terminated) + .mem_qka (1'b0), // (terminated) + .mem_qka_n (1'b0), // (terminated) + .mem_qkb (1'b0), // (terminated) + .mem_qkb_n (1'b0), // (terminated) + .mem_cq (1'b0), // (terminated) + .mem_cq_n (1'b0), // (terminated) + .mem_pe_n (1'b0), // (terminated) + .vid_cal_done_persist (1'b0), // (terminated) + .afi_reset_n (), // (terminated) + .afi_clk (), // (terminated) + .afi_half_clk (), // (terminated) + .emif_usr_half_clk (), // (terminated) + .emif_usr_reset_n_sec (), // (terminated) + .emif_usr_clk_sec (), // (terminated) + .emif_usr_half_clk_sec (), // (terminated) + .cal_master_reset_n (), // (terminated) + .cal_master_clk (), // (terminated) + .cal_debug_reset_n (1'b0), // (terminated) + .cal_debug_clk (1'b0), // (terminated) + .cal_debug_out_reset_n (), // (terminated) + .cal_debug_out_clk (), // (terminated) + .clks_sharing_slave_in (32'b00000000000000000000000000000000), // (terminated) + .afi_cal_success (), // (terminated) + .afi_cal_fail (), // (terminated) + .afi_cal_req (1'b0), // (terminated) + .afi_rlat (), // (terminated) + .afi_wlat (), // (terminated) + .afi_seq_busy (), // (terminated) + .afi_ctl_refresh_done (1'b0), // (terminated) + .afi_ctl_long_idle (1'b0), // (terminated) + .afi_mps_req (1'b0), // (terminated) + .afi_mps_ack (), // (terminated) + .afi_addr (1'b0), // (terminated) + .afi_ba (1'b0), // (terminated) + .afi_bg (1'b0), // (terminated) + .afi_c (1'b0), // (terminated) + .afi_cke (1'b0), // (terminated) + .afi_cs_n (1'b0), // (terminated) + .afi_rm (1'b0), // (terminated) + .afi_odt (1'b0), // (terminated) + .afi_ras_n (1'b0), // (terminated) + .afi_cas_n (1'b0), // (terminated) + .afi_we_n (1'b0), // (terminated) + .afi_rst_n (1'b0), // (terminated) + .afi_act_n (1'b0), // (terminated) + .afi_par (1'b0), // (terminated) + .afi_ca (1'b0), // (terminated) + .afi_ref_n (1'b0), // (terminated) + .afi_wps_n (1'b0), // (terminated) + .afi_rps_n (1'b0), // (terminated) + .afi_doff_n (1'b0), // (terminated) + .afi_ld_n (1'b0), // (terminated) + .afi_rw_n (1'b0), // (terminated) + .afi_lbk0_n (1'b0), // (terminated) + .afi_lbk1_n (1'b0), // (terminated) + .afi_cfg_n (1'b0), // (terminated) + .afi_ap (1'b0), // (terminated) + .afi_ainv (1'b0), // (terminated) + .afi_dm (1'b0), // (terminated) + .afi_dm_n (1'b0), // (terminated) + .afi_bws_n (1'b0), // (terminated) + .afi_rdata_dbi_n (), // (terminated) + .afi_wdata_dbi_n (1'b0), // (terminated) + .afi_rdata_dinv (), // (terminated) + .afi_wdata_dinv (1'b0), // (terminated) + .afi_dqs_burst (1'b0), // (terminated) + .afi_wdata_valid (1'b0), // (terminated) + .afi_wdata (1'b0), // (terminated) + .afi_rdata_en_full (1'b0), // (terminated) + .afi_rdata (), // (terminated) + .afi_rdata_valid (), // (terminated) + .afi_rrank (1'b0), // (terminated) + .afi_wrank (1'b0), // (terminated) + .afi_alert_n (), // (terminated) + .afi_pe_n (), // (terminated) + .ast_cmd_data_0 (1'b0), // (terminated) + .ast_cmd_valid_0 (1'b0), // (terminated) + .ast_cmd_ready_0 (), // (terminated) + .ast_cmd_data_1 (1'b0), // (terminated) + .ast_cmd_valid_1 (1'b0), // (terminated) + .ast_cmd_ready_1 (), // (terminated) + .ast_wr_data_0 (1'b0), // (terminated) + .ast_wr_valid_0 (1'b0), // (terminated) + .ast_wr_ready_0 (), // (terminated) + .ast_wr_data_1 (1'b0), // (terminated) + .ast_wr_valid_1 (1'b0), // (terminated) + .ast_wr_ready_1 (), // (terminated) + .ast_rd_data_0 (), // (terminated) + .ast_rd_valid_0 (), // (terminated) + .ast_rd_ready_0 (1'b0), // (terminated) + .ast_rd_data_1 (), // (terminated) + .ast_rd_valid_1 (), // (terminated) + .ast_rd_ready_1 (1'b0), // (terminated) + .amm_beginbursttransfer_0 (1'b0), // (terminated) + .amm_beginbursttransfer_1 (1'b0), // (terminated) + .ctrl_user_priority_hi_0 (1'b0), // (terminated) + .ctrl_user_priority_hi_1 (1'b0), // (terminated) + .ctrl_auto_precharge_req_0 (1'b0), // (terminated) + .ctrl_auto_precharge_req_1 (1'b0), // (terminated) + .ctrl_user_refresh_req (4'b0000), // (terminated) + .ctrl_user_refresh_bank (16'b0000000000000000), // (terminated) + .ctrl_user_refresh_ack (), // (terminated) + .ctrl_self_refresh_req (4'b0000), // (terminated) + .ctrl_self_refresh_ack (), // (terminated) + .ctrl_will_refresh (), // (terminated) + .ctrl_deep_power_down_req (1'b0), // (terminated) + .ctrl_deep_power_down_ack (), // (terminated) + .ctrl_power_down_ack (), // (terminated) + .ctrl_zq_cal_long_req (1'b0), // (terminated) + .ctrl_zq_cal_short_req (1'b0), // (terminated) + .ctrl_zq_cal_ack (), // (terminated) + .ctrl_ecc_write_info_0 (15'b000000000000000), // (terminated) + .ctrl_ecc_rdata_id_0 (), // (terminated) + .ctrl_ecc_read_info_0 (), // (terminated) + .ctrl_ecc_cmd_info_0 (), // (terminated) + .ctrl_ecc_idle_0 (), // (terminated) + .ctrl_ecc_wr_pointer_info_0 (), // (terminated) + .ctrl_ecc_write_info_1 (15'b000000000000000), // (terminated) + .ctrl_ecc_rdata_id_1 (), // (terminated) + .ctrl_ecc_read_info_1 (), // (terminated) + .ctrl_ecc_cmd_info_1 (), // (terminated) + .ctrl_ecc_idle_1 (), // (terminated) + .ctrl_ecc_wr_pointer_info_1 (), // (terminated) + .mmr_slave_waitrequest_0 (), // (terminated) + .mmr_slave_read_0 (1'b0), // (terminated) + .mmr_slave_write_0 (1'b0), // (terminated) + .mmr_slave_address_0 (10'b0000000000), // (terminated) + .mmr_slave_readdata_0 (), // (terminated) + .mmr_slave_writedata_0 (32'b00000000000000000000000000000000), // (terminated) + .mmr_slave_burstcount_0 (2'b00), // (terminated) + .mmr_slave_beginbursttransfer_0 (1'b0), // (terminated) + .mmr_slave_readdatavalid_0 (), // (terminated) + .mmr_slave_waitrequest_1 (), // (terminated) + .mmr_slave_read_1 (1'b0), // (terminated) + .mmr_slave_write_1 (1'b0), // (terminated) + .mmr_slave_address_1 (10'b0000000000), // (terminated) + .mmr_slave_readdata_1 (), // (terminated) + .mmr_slave_writedata_1 (32'b00000000000000000000000000000000), // (terminated) + .mmr_slave_burstcount_1 (2'b00), // (terminated) + .mmr_slave_beginbursttransfer_1 (1'b0), // (terminated) + .mmr_slave_readdatavalid_1 (), // (terminated) + .hps_to_emif (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .emif_to_hps (), // (terminated) + .hps_to_emif_gp (2'b00), // (terminated) + .emif_to_hps_gp (), // (terminated) + .cal_debug_waitrequest (), // (terminated) + .cal_debug_read (1'b0), // (terminated) + .cal_debug_write (1'b0), // (terminated) + .cal_debug_addr (24'b000000000000000000000000), // (terminated) + .cal_debug_read_data (), // (terminated) + .cal_debug_write_data (32'b00000000000000000000000000000000), // (terminated) + .cal_debug_byteenable (4'b0000), // (terminated) + .cal_debug_read_data_valid (), // (terminated) + .cal_debug_out_waitrequest (1'b0), // (terminated) + .cal_debug_out_read (), // (terminated) + .cal_debug_out_write (), // (terminated) + .cal_debug_out_addr (), // (terminated) + .cal_debug_out_read_data (32'b00000000000000000000000000000000), // (terminated) + .cal_debug_out_write_data (), // (terminated) + .cal_debug_out_byteenable (), // (terminated) + .cal_debug_out_read_data_valid (1'b0), // (terminated) + .ioaux_pio_in (8'b00000000), // (terminated) + .ioaux_pio_out (), // (terminated) + .pa_dprio_clk (1'b0), // (terminated) + .pa_dprio_read (1'b0), // (terminated) + .pa_dprio_reg_addr (9'b000000000), // (terminated) + .pa_dprio_rst_n (1'b0), // (terminated) + .pa_dprio_write (1'b0), // (terminated) + .pa_dprio_writedata (8'b00000000), // (terminated) + .pa_dprio_block_select (), // (terminated) + .pa_dprio_readdata (), // (terminated) + .pll_phase_en (1'b0), // (terminated) + .pll_up_dn (1'b0), // (terminated) + .pll_cnt_sel (4'b0000), // (terminated) + .pll_num_phase_shifts (3'b000), // (terminated) + .pll_phase_done (), // (terminated) + .dft_core_clk_buf_out (), // (terminated) + .dft_core_clk_locked (), // (terminated) + .amm_ready_1 (), // (terminated) + .amm_read_1 (1'b0), // (terminated) + .amm_write_1 (1'b0), // (terminated) + .amm_address_1 (26'b00000000000000000000000000), // (terminated) + .amm_readdata_1 (), // (terminated) + .amm_writedata_1 (512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .amm_burstcount_1 (7'b0000000), // (terminated) + .amm_byteenable_1 (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .amm_readdatavalid_1 () // (terminated) + ); + + ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy cal_slave_component ( + .avl_waitrequest (arch_cal_master_waitrequest), // avl.waitrequest + .avl_readdata (arch_cal_master_readdata), // .readdata + .avl_readdatavalid (arch_cal_master_readdatavalid), // .readdatavalid + .avl_burstcount (arch_cal_master_burstcount), // .burstcount + .avl_writedata (arch_cal_master_writedata), // .writedata + .avl_address (arch_cal_master_address), // .address + .avl_write (arch_cal_master_write), // .write + .avl_read (arch_cal_master_read), // .read + .avl_byteenable (arch_cal_master_byteenable), // .byteenable + .avl_debugaccess (arch_cal_master_debugaccess), // .debugaccess + .clk_clk (arch_cal_slave_clk_clk), // clk.clk + .rst_reset (~arch_cal_slave_reset_n_reset) // rst.reset + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy.sv new file mode 100644 index 000000000000..db7172e7ec15 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy.sv @@ -0,0 +1,3573 @@ +module ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy #( + parameter PROTOCOL_ENUM = "", + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 0, + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_CALIBRATED_OCT = 0, + parameter PHY_AC_CALIBRATED_OCT = 0, + parameter PHY_CK_CALIBRATED_OCT = 0, + parameter PHY_DATA_CALIBRATED_OCT = 0, + parameter PHY_HPS_ENABLE_EARLY_RELEASE = 0, + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter MEM_FORMAT_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 0, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter SILICON_REV = "", + parameter IS_HPS = 0, + parameter IS_VID = 0, + parameter USER_CLK_RATIO = 0, + parameter C2P_P2C_CLK_RATIO = 0, + parameter PHY_HMC_CLK_RATIO = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 0, + parameter DIAG_ABSTRACT_PHY_RLAT = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter AC_PIN_MAP_SCHEME = "", + parameter NUM_OF_HMC_PORTS = 0, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter REGISTER_AFI = 0, + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 0, + parameter SEQ_SIM_OSC_FREQ_MHZ = 0, + parameter NUM_OF_RTL_TILES = 0, + parameter PRI_RDATA_TILE_INDEX = 0, + parameter PRI_RDATA_LANE_INDEX = 0, + parameter PRI_WDATA_TILE_INDEX = 0, + parameter PRI_WDATA_LANE_INDEX = 0, + parameter PRI_AC_TILE_INDEX = 0, + parameter SEC_RDATA_TILE_INDEX = 0, + parameter SEC_RDATA_LANE_INDEX = 0, + parameter SEC_WDATA_TILE_INDEX = 0, + parameter SEC_WDATA_LANE_INDEX = 0, + parameter SEC_AC_TILE_INDEX = 0, + parameter LANES_USAGE_0 = 0, + parameter LANES_USAGE_1 = 0, + parameter LANES_USAGE_2 = 0, + parameter LANES_USAGE_3 = 0, + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_0 = 0, + parameter PINS_USAGE_1 = 0, + parameter PINS_USAGE_2 = 0, + parameter PINS_USAGE_3 = 0, + parameter PINS_USAGE_4 = 0, + parameter PINS_USAGE_5 = 0, + parameter PINS_USAGE_6 = 0, + parameter PINS_USAGE_7 = 0, + parameter PINS_USAGE_8 = 0, + parameter PINS_USAGE_9 = 0, + parameter PINS_USAGE_10 = 0, + parameter PINS_USAGE_11 = 0, + parameter PINS_USAGE_12 = 0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_0 = 0, + parameter PINS_RATE_1 = 0, + parameter PINS_RATE_2 = 0, + parameter PINS_RATE_3 = 0, + parameter PINS_RATE_4 = 0, + parameter PINS_RATE_5 = 0, + parameter PINS_RATE_6 = 0, + parameter PINS_RATE_7 = 0, + parameter PINS_RATE_8 = 0, + parameter PINS_RATE_9 = 0, + parameter PINS_RATE_10 = 0, + parameter PINS_RATE_11 = 0, + parameter PINS_RATE_12 = 0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter PINS_WDB_0 = 0, + parameter PINS_WDB_1 = 0, + parameter PINS_WDB_2 = 0, + parameter PINS_WDB_3 = 0, + parameter PINS_WDB_4 = 0, + parameter PINS_WDB_5 = 0, + parameter PINS_WDB_6 = 0, + parameter PINS_WDB_7 = 0, + parameter PINS_WDB_8 = 0, + parameter PINS_WDB_9 = 0, + parameter PINS_WDB_10 = 0, + parameter PINS_WDB_11 = 0, + parameter PINS_WDB_12 = 0, + parameter PINS_WDB_13 = 0, + parameter PINS_WDB_14 = 0, + parameter PINS_WDB_15 = 0, + parameter PINS_WDB_16 = 0, + parameter PINS_WDB_17 = 0, + parameter PINS_WDB_18 = 0, + parameter PINS_WDB_19 = 0, + parameter PINS_WDB_20 = 0, + parameter PINS_WDB_21 = 0, + parameter PINS_WDB_22 = 0, + parameter PINS_WDB_23 = 0, + parameter PINS_WDB_24 = 0, + parameter PINS_WDB_25 = 0, + parameter PINS_WDB_26 = 0, + parameter PINS_WDB_27 = 0, + parameter PINS_WDB_28 = 0, + parameter PINS_WDB_29 = 0, + parameter PINS_WDB_30 = 0, + parameter PINS_WDB_31 = 0, + parameter PINS_WDB_32 = 0, + parameter PINS_WDB_33 = 0, + parameter PINS_WDB_34 = 0, + parameter PINS_WDB_35 = 0, + parameter PINS_WDB_36 = 0, + parameter PINS_WDB_37 = 0, + parameter PINS_WDB_38 = 0, + parameter PINS_WDB_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_0 = 0, + parameter PINS_DATA_IN_MODE_1 = 0, + parameter PINS_DATA_IN_MODE_2 = 0, + parameter PINS_DATA_IN_MODE_3 = 0, + parameter PINS_DATA_IN_MODE_4 = 0, + parameter PINS_DATA_IN_MODE_5 = 0, + parameter PINS_DATA_IN_MODE_6 = 0, + parameter PINS_DATA_IN_MODE_7 = 0, + parameter PINS_DATA_IN_MODE_8 = 0, + parameter PINS_DATA_IN_MODE_9 = 0, + parameter PINS_DATA_IN_MODE_10 = 0, + parameter PINS_DATA_IN_MODE_11 = 0, + parameter PINS_DATA_IN_MODE_12 = 0, + parameter PINS_DATA_IN_MODE_13 = 0, + parameter PINS_DATA_IN_MODE_14 = 0, + parameter PINS_DATA_IN_MODE_15 = 0, + parameter PINS_DATA_IN_MODE_16 = 0, + parameter PINS_DATA_IN_MODE_17 = 0, + parameter PINS_DATA_IN_MODE_18 = 0, + parameter PINS_DATA_IN_MODE_19 = 0, + parameter PINS_DATA_IN_MODE_20 = 0, + parameter PINS_DATA_IN_MODE_21 = 0, + parameter PINS_DATA_IN_MODE_22 = 0, + parameter PINS_DATA_IN_MODE_23 = 0, + parameter PINS_DATA_IN_MODE_24 = 0, + parameter PINS_DATA_IN_MODE_25 = 0, + parameter PINS_DATA_IN_MODE_26 = 0, + parameter PINS_DATA_IN_MODE_27 = 0, + parameter PINS_DATA_IN_MODE_28 = 0, + parameter PINS_DATA_IN_MODE_29 = 0, + parameter PINS_DATA_IN_MODE_30 = 0, + parameter PINS_DATA_IN_MODE_31 = 0, + parameter PINS_DATA_IN_MODE_32 = 0, + parameter PINS_DATA_IN_MODE_33 = 0, + parameter PINS_DATA_IN_MODE_34 = 0, + parameter PINS_DATA_IN_MODE_35 = 0, + parameter PINS_DATA_IN_MODE_36 = 0, + parameter PINS_DATA_IN_MODE_37 = 0, + parameter PINS_DATA_IN_MODE_38 = 0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_0 = 0, + parameter PINS_C2L_DRIVEN_1 = 0, + parameter PINS_C2L_DRIVEN_2 = 0, + parameter PINS_C2L_DRIVEN_3 = 0, + parameter PINS_C2L_DRIVEN_4 = 0, + parameter PINS_C2L_DRIVEN_5 = 0, + parameter PINS_C2L_DRIVEN_6 = 0, + parameter PINS_C2L_DRIVEN_7 = 0, + parameter PINS_C2L_DRIVEN_8 = 0, + parameter PINS_C2L_DRIVEN_9 = 0, + parameter PINS_C2L_DRIVEN_10 = 0, + parameter PINS_C2L_DRIVEN_11 = 0, + parameter PINS_C2L_DRIVEN_12 = 0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_DB_IN_BYPASS_0 = 0, + parameter PINS_DB_IN_BYPASS_1 = 0, + parameter PINS_DB_IN_BYPASS_2 = 0, + parameter PINS_DB_IN_BYPASS_3 = 0, + parameter PINS_DB_IN_BYPASS_4 = 0, + parameter PINS_DB_IN_BYPASS_5 = 0, + parameter PINS_DB_IN_BYPASS_6 = 0, + parameter PINS_DB_IN_BYPASS_7 = 0, + parameter PINS_DB_IN_BYPASS_8 = 0, + parameter PINS_DB_IN_BYPASS_9 = 0, + parameter PINS_DB_IN_BYPASS_10 = 0, + parameter PINS_DB_IN_BYPASS_11 = 0, + parameter PINS_DB_IN_BYPASS_12 = 0, + parameter PINS_DB_IN_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OUT_BYPASS_0 = 0, + parameter PINS_DB_OUT_BYPASS_1 = 0, + parameter PINS_DB_OUT_BYPASS_2 = 0, + parameter PINS_DB_OUT_BYPASS_3 = 0, + parameter PINS_DB_OUT_BYPASS_4 = 0, + parameter PINS_DB_OUT_BYPASS_5 = 0, + parameter PINS_DB_OUT_BYPASS_6 = 0, + parameter PINS_DB_OUT_BYPASS_7 = 0, + parameter PINS_DB_OUT_BYPASS_8 = 0, + parameter PINS_DB_OUT_BYPASS_9 = 0, + parameter PINS_DB_OUT_BYPASS_10 = 0, + parameter PINS_DB_OUT_BYPASS_11 = 0, + parameter PINS_DB_OUT_BYPASS_12 = 0, + parameter PINS_DB_OUT_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OE_BYPASS_0 = 0, + parameter PINS_DB_OE_BYPASS_1 = 0, + parameter PINS_DB_OE_BYPASS_2 = 0, + parameter PINS_DB_OE_BYPASS_3 = 0, + parameter PINS_DB_OE_BYPASS_4 = 0, + parameter PINS_DB_OE_BYPASS_5 = 0, + parameter PINS_DB_OE_BYPASS_6 = 0, + parameter PINS_DB_OE_BYPASS_7 = 0, + parameter PINS_DB_OE_BYPASS_8 = 0, + parameter PINS_DB_OE_BYPASS_9 = 0, + parameter PINS_DB_OE_BYPASS_10 = 0, + parameter PINS_DB_OE_BYPASS_11 = 0, + parameter PINS_DB_OE_BYPASS_12 = 0, + parameter PINS_DB_OE_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_WR_0 = 0, + parameter PINS_INVERT_WR_1 = 0, + parameter PINS_INVERT_WR_2 = 0, + parameter PINS_INVERT_WR_3 = 0, + parameter PINS_INVERT_WR_4 = 0, + parameter PINS_INVERT_WR_5 = 0, + parameter PINS_INVERT_WR_6 = 0, + parameter PINS_INVERT_WR_7 = 0, + parameter PINS_INVERT_WR_8 = 0, + parameter PINS_INVERT_WR_9 = 0, + parameter PINS_INVERT_WR_10 = 0, + parameter PINS_INVERT_WR_11 = 0, + parameter PINS_INVERT_WR_12 = 0, + parameter PINS_INVERT_WR_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_OE_0 = 0, + parameter PINS_INVERT_OE_1 = 0, + parameter PINS_INVERT_OE_2 = 0, + parameter PINS_INVERT_OE_3 = 0, + parameter PINS_INVERT_OE_4 = 0, + parameter PINS_INVERT_OE_5 = 0, + parameter PINS_INVERT_OE_6 = 0, + parameter PINS_INVERT_OE_7 = 0, + parameter PINS_INVERT_OE_8 = 0, + parameter PINS_INVERT_OE_9 = 0, + parameter PINS_INVERT_OE_10 = 0, + parameter PINS_INVERT_OE_11 = 0, + parameter PINS_INVERT_OE_12 = 0, + parameter PINS_INVERT_OE_AUTOGEN_WCNT = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_0 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_1 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_2 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_3 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_4 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_5 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_6 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_7 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_8 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_9 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_10 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_11 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_12 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_0 = 0, + parameter PINS_OCT_MODE_1 = 0, + parameter PINS_OCT_MODE_2 = 0, + parameter PINS_OCT_MODE_3 = 0, + parameter PINS_OCT_MODE_4 = 0, + parameter PINS_OCT_MODE_5 = 0, + parameter PINS_OCT_MODE_6 = 0, + parameter PINS_OCT_MODE_7 = 0, + parameter PINS_OCT_MODE_8 = 0, + parameter PINS_OCT_MODE_9 = 0, + parameter PINS_OCT_MODE_10 = 0, + parameter PINS_OCT_MODE_11 = 0, + parameter PINS_OCT_MODE_12 = 0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_GPIO_MODE_0 = 0, + parameter PINS_GPIO_MODE_1 = 0, + parameter PINS_GPIO_MODE_2 = 0, + parameter PINS_GPIO_MODE_3 = 0, + parameter PINS_GPIO_MODE_4 = 0, + parameter PINS_GPIO_MODE_5 = 0, + parameter PINS_GPIO_MODE_6 = 0, + parameter PINS_GPIO_MODE_7 = 0, + parameter PINS_GPIO_MODE_8 = 0, + parameter PINS_GPIO_MODE_9 = 0, + parameter PINS_GPIO_MODE_10 = 0, + parameter PINS_GPIO_MODE_11 = 0, + parameter PINS_GPIO_MODE_12 = 0, + parameter PINS_GPIO_MODE_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_0 = 0, + parameter CENTER_TIDS_1 = 0, + parameter CENTER_TIDS_2 = 0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_0 = 0, + parameter HMC_TIDS_1 = 0, + parameter HMC_TIDS_2 = 0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_0 = 0, + parameter LANE_TIDS_1 = 0, + parameter LANE_TIDS_2 = 0, + parameter LANE_TIDS_3 = 0, + parameter LANE_TIDS_4 = 0, + parameter LANE_TIDS_5 = 0, + parameter LANE_TIDS_6 = 0, + parameter LANE_TIDS_7 = 0, + parameter LANE_TIDS_8 = 0, + parameter LANE_TIDS_9 = 0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 0, + parameter DBC_WB_RESERVED_ENTRY = 0, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + parameter ABPHY_WRITE_PROTOCOL = 0, + parameter PHY_USERMODE_OCT = 0, + parameter PHY_PERIODIC_OCT_RECAL = 0, + parameter PHY_HAS_DCC = 0, + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_TCL = 0, + parameter PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter PRI_HMC_CFG_WR_ODT_ON = 0, + parameter PRI_HMC_CFG_RD_ODT_ON = 0, + parameter PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_RD = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_WR = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_PCH = 0, + parameter PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_WR_TO_WR = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_RD = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_PCH = 0, + parameter PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_ARF_PERIOD = 0, + parameter PRI_HMC_CFG_PDN_PERIOD = 0, + parameter PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_TCL = 0, + parameter SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter SEC_HMC_CFG_WR_ODT_ON = 0, + parameter SEC_HMC_CFG_RD_ODT_ON = 0, + parameter SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_RD = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_WR = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_PCH = 0, + parameter SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_WR_TO_WR = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_RD = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_PCH = 0, + parameter SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_ARF_PERIOD = 0, + parameter SEC_HMC_CFG_PDN_PERIOD = 0, + parameter SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter PINS_PER_LANE = 0, + parameter LANES_PER_TILE = 0, + parameter OCT_CONTROL_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_CK_PINLOC_0 = 0, + parameter PORT_MEM_CK_PINLOC_1 = 0, + parameter PORT_MEM_CK_PINLOC_2 = 0, + parameter PORT_MEM_CK_PINLOC_3 = 0, + parameter PORT_MEM_CK_PINLOC_4 = 0, + parameter PORT_MEM_CK_PINLOC_5 = 0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_WIDTH = 0, + parameter PORT_MEM_CK_N_PINLOC_0 = 0, + parameter PORT_MEM_CK_N_PINLOC_1 = 0, + parameter PORT_MEM_CK_N_PINLOC_2 = 0, + parameter PORT_MEM_CK_N_PINLOC_3 = 0, + parameter PORT_MEM_CK_N_PINLOC_4 = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_WIDTH = 0, + parameter PORT_MEM_DK_PINLOC_0 = 0, + parameter PORT_MEM_DK_PINLOC_1 = 0, + parameter PORT_MEM_DK_PINLOC_2 = 0, + parameter PORT_MEM_DK_PINLOC_3 = 0, + parameter PORT_MEM_DK_PINLOC_4 = 0, + parameter PORT_MEM_DK_PINLOC_5 = 0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_WIDTH = 0, + parameter PORT_MEM_DK_N_PINLOC_0 = 0, + parameter PORT_MEM_DK_N_PINLOC_1 = 0, + parameter PORT_MEM_DK_N_PINLOC_2 = 0, + parameter PORT_MEM_DK_N_PINLOC_3 = 0, + parameter PORT_MEM_DK_N_PINLOC_4 = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_WIDTH = 0, + parameter PORT_MEM_DKA_PINLOC_0 = 0, + parameter PORT_MEM_DKA_PINLOC_1 = 0, + parameter PORT_MEM_DKA_PINLOC_2 = 0, + parameter PORT_MEM_DKA_PINLOC_3 = 0, + parameter PORT_MEM_DKA_PINLOC_4 = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_WIDTH = 0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_WIDTH = 0, + parameter PORT_MEM_DKB_PINLOC_0 = 0, + parameter PORT_MEM_DKB_PINLOC_1 = 0, + parameter PORT_MEM_DKB_PINLOC_2 = 0, + parameter PORT_MEM_DKB_PINLOC_3 = 0, + parameter PORT_MEM_DKB_PINLOC_4 = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_WIDTH = 0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_WIDTH = 0, + parameter PORT_MEM_K_PINLOC_0 = 0, + parameter PORT_MEM_K_PINLOC_1 = 0, + parameter PORT_MEM_K_PINLOC_2 = 0, + parameter PORT_MEM_K_PINLOC_3 = 0, + parameter PORT_MEM_K_PINLOC_4 = 0, + parameter PORT_MEM_K_PINLOC_5 = 0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_WIDTH = 0, + parameter PORT_MEM_K_N_PINLOC_0 = 0, + parameter PORT_MEM_K_N_PINLOC_1 = 0, + parameter PORT_MEM_K_N_PINLOC_2 = 0, + parameter PORT_MEM_K_N_PINLOC_3 = 0, + parameter PORT_MEM_K_N_PINLOC_4 = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_A_PINLOC_0 = 0, + parameter PORT_MEM_A_PINLOC_1 = 0, + parameter PORT_MEM_A_PINLOC_2 = 0, + parameter PORT_MEM_A_PINLOC_3 = 0, + parameter PORT_MEM_A_PINLOC_4 = 0, + parameter PORT_MEM_A_PINLOC_5 = 0, + parameter PORT_MEM_A_PINLOC_6 = 0, + parameter PORT_MEM_A_PINLOC_7 = 0, + parameter PORT_MEM_A_PINLOC_8 = 0, + parameter PORT_MEM_A_PINLOC_9 = 0, + parameter PORT_MEM_A_PINLOC_10 = 0, + parameter PORT_MEM_A_PINLOC_11 = 0, + parameter PORT_MEM_A_PINLOC_12 = 0, + parameter PORT_MEM_A_PINLOC_13 = 0, + parameter PORT_MEM_A_PINLOC_14 = 0, + parameter PORT_MEM_A_PINLOC_15 = 0, + parameter PORT_MEM_A_PINLOC_16 = 0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BA_PINLOC_0 = 0, + parameter PORT_MEM_BA_PINLOC_1 = 0, + parameter PORT_MEM_BA_PINLOC_2 = 0, + parameter PORT_MEM_BA_PINLOC_3 = 0, + parameter PORT_MEM_BA_PINLOC_4 = 0, + parameter PORT_MEM_BA_PINLOC_5 = 0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_BG_PINLOC_0 = 0, + parameter PORT_MEM_BG_PINLOC_1 = 0, + parameter PORT_MEM_BG_PINLOC_2 = 0, + parameter PORT_MEM_BG_PINLOC_3 = 0, + parameter PORT_MEM_BG_PINLOC_4 = 0, + parameter PORT_MEM_BG_PINLOC_5 = 0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_WIDTH = 0, + parameter PORT_MEM_C_PINLOC_0 = 0, + parameter PORT_MEM_C_PINLOC_1 = 0, + parameter PORT_MEM_C_PINLOC_2 = 0, + parameter PORT_MEM_C_PINLOC_3 = 0, + parameter PORT_MEM_C_PINLOC_4 = 0, + parameter PORT_MEM_C_PINLOC_5 = 0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_WIDTH = 0, + parameter PORT_MEM_CKE_PINLOC_0 = 0, + parameter PORT_MEM_CKE_PINLOC_1 = 0, + parameter PORT_MEM_CKE_PINLOC_2 = 0, + parameter PORT_MEM_CKE_PINLOC_3 = 0, + parameter PORT_MEM_CKE_PINLOC_4 = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_CS_N_PINLOC_0 = 0, + parameter PORT_MEM_CS_N_PINLOC_1 = 0, + parameter PORT_MEM_CS_N_PINLOC_2 = 0, + parameter PORT_MEM_CS_N_PINLOC_3 = 0, + parameter PORT_MEM_CS_N_PINLOC_4 = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_WIDTH = 0, + parameter PORT_MEM_RM_PINLOC_0 = 0, + parameter PORT_MEM_RM_PINLOC_1 = 0, + parameter PORT_MEM_RM_PINLOC_2 = 0, + parameter PORT_MEM_RM_PINLOC_3 = 0, + parameter PORT_MEM_RM_PINLOC_4 = 0, + parameter PORT_MEM_RM_PINLOC_5 = 0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_WIDTH = 0, + parameter PORT_MEM_ODT_PINLOC_0 = 0, + parameter PORT_MEM_ODT_PINLOC_1 = 0, + parameter PORT_MEM_ODT_PINLOC_2 = 0, + parameter PORT_MEM_ODT_PINLOC_3 = 0, + parameter PORT_MEM_ODT_PINLOC_4 = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_WE_N_PINLOC_0 = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_WIDTH = 0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_WIDTH = 0, + parameter PORT_MEM_PAR_PINLOC_0 = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_WIDTH = 0, + parameter PORT_MEM_CA_PINLOC_0 = 0, + parameter PORT_MEM_CA_PINLOC_1 = 0, + parameter PORT_MEM_CA_PINLOC_2 = 0, + parameter PORT_MEM_CA_PINLOC_3 = 0, + parameter PORT_MEM_CA_PINLOC_4 = 0, + parameter PORT_MEM_CA_PINLOC_5 = 0, + parameter PORT_MEM_CA_PINLOC_6 = 0, + parameter PORT_MEM_CA_PINLOC_7 = 0, + parameter PORT_MEM_CA_PINLOC_8 = 0, + parameter PORT_MEM_CA_PINLOC_9 = 0, + parameter PORT_MEM_CA_PINLOC_10 = 0, + parameter PORT_MEM_CA_PINLOC_11 = 0, + parameter PORT_MEM_CA_PINLOC_12 = 0, + parameter PORT_MEM_CA_PINLOC_13 = 0, + parameter PORT_MEM_CA_PINLOC_14 = 0, + parameter PORT_MEM_CA_PINLOC_15 = 0, + parameter PORT_MEM_CA_PINLOC_16 = 0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_WIDTH = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_WIDTH = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_WIDTH = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_WIDTH = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_WIDTH = 0, + parameter PORT_MEM_AP_PINLOC_0 = 0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_DM_PINLOC_0 = 0, + parameter PORT_MEM_DM_PINLOC_1 = 0, + parameter PORT_MEM_DM_PINLOC_2 = 0, + parameter PORT_MEM_DM_PINLOC_3 = 0, + parameter PORT_MEM_DM_PINLOC_4 = 0, + parameter PORT_MEM_DM_PINLOC_5 = 0, + parameter PORT_MEM_DM_PINLOC_6 = 0, + parameter PORT_MEM_DM_PINLOC_7 = 0, + parameter PORT_MEM_DM_PINLOC_8 = 0, + parameter PORT_MEM_DM_PINLOC_9 = 0, + parameter PORT_MEM_DM_PINLOC_10 = 0, + parameter PORT_MEM_DM_PINLOC_11 = 0, + parameter PORT_MEM_DM_PINLOC_12 = 0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_D_PINLOC_0 = 0, + parameter PORT_MEM_D_PINLOC_1 = 0, + parameter PORT_MEM_D_PINLOC_2 = 0, + parameter PORT_MEM_D_PINLOC_3 = 0, + parameter PORT_MEM_D_PINLOC_4 = 0, + parameter PORT_MEM_D_PINLOC_5 = 0, + parameter PORT_MEM_D_PINLOC_6 = 0, + parameter PORT_MEM_D_PINLOC_7 = 0, + parameter PORT_MEM_D_PINLOC_8 = 0, + parameter PORT_MEM_D_PINLOC_9 = 0, + parameter PORT_MEM_D_PINLOC_10 = 0, + parameter PORT_MEM_D_PINLOC_11 = 0, + parameter PORT_MEM_D_PINLOC_12 = 0, + parameter PORT_MEM_D_PINLOC_13 = 0, + parameter PORT_MEM_D_PINLOC_14 = 0, + parameter PORT_MEM_D_PINLOC_15 = 0, + parameter PORT_MEM_D_PINLOC_16 = 0, + parameter PORT_MEM_D_PINLOC_17 = 0, + parameter PORT_MEM_D_PINLOC_18 = 0, + parameter PORT_MEM_D_PINLOC_19 = 0, + parameter PORT_MEM_D_PINLOC_20 = 0, + parameter PORT_MEM_D_PINLOC_21 = 0, + parameter PORT_MEM_D_PINLOC_22 = 0, + parameter PORT_MEM_D_PINLOC_23 = 0, + parameter PORT_MEM_D_PINLOC_24 = 0, + parameter PORT_MEM_D_PINLOC_25 = 0, + parameter PORT_MEM_D_PINLOC_26 = 0, + parameter PORT_MEM_D_PINLOC_27 = 0, + parameter PORT_MEM_D_PINLOC_28 = 0, + parameter PORT_MEM_D_PINLOC_29 = 0, + parameter PORT_MEM_D_PINLOC_30 = 0, + parameter PORT_MEM_D_PINLOC_31 = 0, + parameter PORT_MEM_D_PINLOC_32 = 0, + parameter PORT_MEM_D_PINLOC_33 = 0, + parameter PORT_MEM_D_PINLOC_34 = 0, + parameter PORT_MEM_D_PINLOC_35 = 0, + parameter PORT_MEM_D_PINLOC_36 = 0, + parameter PORT_MEM_D_PINLOC_37 = 0, + parameter PORT_MEM_D_PINLOC_38 = 0, + parameter PORT_MEM_D_PINLOC_39 = 0, + parameter PORT_MEM_D_PINLOC_40 = 0, + parameter PORT_MEM_D_PINLOC_41 = 0, + parameter PORT_MEM_D_PINLOC_42 = 0, + parameter PORT_MEM_D_PINLOC_43 = 0, + parameter PORT_MEM_D_PINLOC_44 = 0, + parameter PORT_MEM_D_PINLOC_45 = 0, + parameter PORT_MEM_D_PINLOC_46 = 0, + parameter PORT_MEM_D_PINLOC_47 = 0, + parameter PORT_MEM_D_PINLOC_48 = 0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_WIDTH = 0, + parameter PORT_MEM_DQ_PINLOC_0 = 0, + parameter PORT_MEM_DQ_PINLOC_1 = 0, + parameter PORT_MEM_DQ_PINLOC_2 = 0, + parameter PORT_MEM_DQ_PINLOC_3 = 0, + parameter PORT_MEM_DQ_PINLOC_4 = 0, + parameter PORT_MEM_DQ_PINLOC_5 = 0, + parameter PORT_MEM_DQ_PINLOC_6 = 0, + parameter PORT_MEM_DQ_PINLOC_7 = 0, + parameter PORT_MEM_DQ_PINLOC_8 = 0, + parameter PORT_MEM_DQ_PINLOC_9 = 0, + parameter PORT_MEM_DQ_PINLOC_10 = 0, + parameter PORT_MEM_DQ_PINLOC_11 = 0, + parameter PORT_MEM_DQ_PINLOC_12 = 0, + parameter PORT_MEM_DQ_PINLOC_13 = 0, + parameter PORT_MEM_DQ_PINLOC_14 = 0, + parameter PORT_MEM_DQ_PINLOC_15 = 0, + parameter PORT_MEM_DQ_PINLOC_16 = 0, + parameter PORT_MEM_DQ_PINLOC_17 = 0, + parameter PORT_MEM_DQ_PINLOC_18 = 0, + parameter PORT_MEM_DQ_PINLOC_19 = 0, + parameter PORT_MEM_DQ_PINLOC_20 = 0, + parameter PORT_MEM_DQ_PINLOC_21 = 0, + parameter PORT_MEM_DQ_PINLOC_22 = 0, + parameter PORT_MEM_DQ_PINLOC_23 = 0, + parameter PORT_MEM_DQ_PINLOC_24 = 0, + parameter PORT_MEM_DQ_PINLOC_25 = 0, + parameter PORT_MEM_DQ_PINLOC_26 = 0, + parameter PORT_MEM_DQ_PINLOC_27 = 0, + parameter PORT_MEM_DQ_PINLOC_28 = 0, + parameter PORT_MEM_DQ_PINLOC_29 = 0, + parameter PORT_MEM_DQ_PINLOC_30 = 0, + parameter PORT_MEM_DQ_PINLOC_31 = 0, + parameter PORT_MEM_DQ_PINLOC_32 = 0, + parameter PORT_MEM_DQ_PINLOC_33 = 0, + parameter PORT_MEM_DQ_PINLOC_34 = 0, + parameter PORT_MEM_DQ_PINLOC_35 = 0, + parameter PORT_MEM_DQ_PINLOC_36 = 0, + parameter PORT_MEM_DQ_PINLOC_37 = 0, + parameter PORT_MEM_DQ_PINLOC_38 = 0, + parameter PORT_MEM_DQ_PINLOC_39 = 0, + parameter PORT_MEM_DQ_PINLOC_40 = 0, + parameter PORT_MEM_DQ_PINLOC_41 = 0, + parameter PORT_MEM_DQ_PINLOC_42 = 0, + parameter PORT_MEM_DQ_PINLOC_43 = 0, + parameter PORT_MEM_DQ_PINLOC_44 = 0, + parameter PORT_MEM_DQ_PINLOC_45 = 0, + parameter PORT_MEM_DQ_PINLOC_46 = 0, + parameter PORT_MEM_DQ_PINLOC_47 = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQA_PINLOC_0 = 0, + parameter PORT_MEM_DQA_PINLOC_1 = 0, + parameter PORT_MEM_DQA_PINLOC_2 = 0, + parameter PORT_MEM_DQA_PINLOC_3 = 0, + parameter PORT_MEM_DQA_PINLOC_4 = 0, + parameter PORT_MEM_DQA_PINLOC_5 = 0, + parameter PORT_MEM_DQA_PINLOC_6 = 0, + parameter PORT_MEM_DQA_PINLOC_7 = 0, + parameter PORT_MEM_DQA_PINLOC_8 = 0, + parameter PORT_MEM_DQA_PINLOC_9 = 0, + parameter PORT_MEM_DQA_PINLOC_10 = 0, + parameter PORT_MEM_DQA_PINLOC_11 = 0, + parameter PORT_MEM_DQA_PINLOC_12 = 0, + parameter PORT_MEM_DQA_PINLOC_13 = 0, + parameter PORT_MEM_DQA_PINLOC_14 = 0, + parameter PORT_MEM_DQA_PINLOC_15 = 0, + parameter PORT_MEM_DQA_PINLOC_16 = 0, + parameter PORT_MEM_DQA_PINLOC_17 = 0, + parameter PORT_MEM_DQA_PINLOC_18 = 0, + parameter PORT_MEM_DQA_PINLOC_19 = 0, + parameter PORT_MEM_DQA_PINLOC_20 = 0, + parameter PORT_MEM_DQA_PINLOC_21 = 0, + parameter PORT_MEM_DQA_PINLOC_22 = 0, + parameter PORT_MEM_DQA_PINLOC_23 = 0, + parameter PORT_MEM_DQA_PINLOC_24 = 0, + parameter PORT_MEM_DQA_PINLOC_25 = 0, + parameter PORT_MEM_DQA_PINLOC_26 = 0, + parameter PORT_MEM_DQA_PINLOC_27 = 0, + parameter PORT_MEM_DQA_PINLOC_28 = 0, + parameter PORT_MEM_DQA_PINLOC_29 = 0, + parameter PORT_MEM_DQA_PINLOC_30 = 0, + parameter PORT_MEM_DQA_PINLOC_31 = 0, + parameter PORT_MEM_DQA_PINLOC_32 = 0, + parameter PORT_MEM_DQA_PINLOC_33 = 0, + parameter PORT_MEM_DQA_PINLOC_34 = 0, + parameter PORT_MEM_DQA_PINLOC_35 = 0, + parameter PORT_MEM_DQA_PINLOC_36 = 0, + parameter PORT_MEM_DQA_PINLOC_37 = 0, + parameter PORT_MEM_DQA_PINLOC_38 = 0, + parameter PORT_MEM_DQA_PINLOC_39 = 0, + parameter PORT_MEM_DQA_PINLOC_40 = 0, + parameter PORT_MEM_DQA_PINLOC_41 = 0, + parameter PORT_MEM_DQA_PINLOC_42 = 0, + parameter PORT_MEM_DQA_PINLOC_43 = 0, + parameter PORT_MEM_DQA_PINLOC_44 = 0, + parameter PORT_MEM_DQA_PINLOC_45 = 0, + parameter PORT_MEM_DQA_PINLOC_46 = 0, + parameter PORT_MEM_DQA_PINLOC_47 = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_DQB_PINLOC_0 = 0, + parameter PORT_MEM_DQB_PINLOC_1 = 0, + parameter PORT_MEM_DQB_PINLOC_2 = 0, + parameter PORT_MEM_DQB_PINLOC_3 = 0, + parameter PORT_MEM_DQB_PINLOC_4 = 0, + parameter PORT_MEM_DQB_PINLOC_5 = 0, + parameter PORT_MEM_DQB_PINLOC_6 = 0, + parameter PORT_MEM_DQB_PINLOC_7 = 0, + parameter PORT_MEM_DQB_PINLOC_8 = 0, + parameter PORT_MEM_DQB_PINLOC_9 = 0, + parameter PORT_MEM_DQB_PINLOC_10 = 0, + parameter PORT_MEM_DQB_PINLOC_11 = 0, + parameter PORT_MEM_DQB_PINLOC_12 = 0, + parameter PORT_MEM_DQB_PINLOC_13 = 0, + parameter PORT_MEM_DQB_PINLOC_14 = 0, + parameter PORT_MEM_DQB_PINLOC_15 = 0, + parameter PORT_MEM_DQB_PINLOC_16 = 0, + parameter PORT_MEM_DQB_PINLOC_17 = 0, + parameter PORT_MEM_DQB_PINLOC_18 = 0, + parameter PORT_MEM_DQB_PINLOC_19 = 0, + parameter PORT_MEM_DQB_PINLOC_20 = 0, + parameter PORT_MEM_DQB_PINLOC_21 = 0, + parameter PORT_MEM_DQB_PINLOC_22 = 0, + parameter PORT_MEM_DQB_PINLOC_23 = 0, + parameter PORT_MEM_DQB_PINLOC_24 = 0, + parameter PORT_MEM_DQB_PINLOC_25 = 0, + parameter PORT_MEM_DQB_PINLOC_26 = 0, + parameter PORT_MEM_DQB_PINLOC_27 = 0, + parameter PORT_MEM_DQB_PINLOC_28 = 0, + parameter PORT_MEM_DQB_PINLOC_29 = 0, + parameter PORT_MEM_DQB_PINLOC_30 = 0, + parameter PORT_MEM_DQB_PINLOC_31 = 0, + parameter PORT_MEM_DQB_PINLOC_32 = 0, + parameter PORT_MEM_DQB_PINLOC_33 = 0, + parameter PORT_MEM_DQB_PINLOC_34 = 0, + parameter PORT_MEM_DQB_PINLOC_35 = 0, + parameter PORT_MEM_DQB_PINLOC_36 = 0, + parameter PORT_MEM_DQB_PINLOC_37 = 0, + parameter PORT_MEM_DQB_PINLOC_38 = 0, + parameter PORT_MEM_DQB_PINLOC_39 = 0, + parameter PORT_MEM_DQB_PINLOC_40 = 0, + parameter PORT_MEM_DQB_PINLOC_41 = 0, + parameter PORT_MEM_DQB_PINLOC_42 = 0, + parameter PORT_MEM_DQB_PINLOC_43 = 0, + parameter PORT_MEM_DQB_PINLOC_44 = 0, + parameter PORT_MEM_DQB_PINLOC_45 = 0, + parameter PORT_MEM_DQB_PINLOC_46 = 0, + parameter PORT_MEM_DQB_PINLOC_47 = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVA_PINLOC_0 = 0, + parameter PORT_MEM_DINVA_PINLOC_1 = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_DINVB_PINLOC_0 = 0, + parameter PORT_MEM_DINVB_PINLOC_1 = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_Q_PINLOC_0 = 0, + parameter PORT_MEM_Q_PINLOC_1 = 0, + parameter PORT_MEM_Q_PINLOC_2 = 0, + parameter PORT_MEM_Q_PINLOC_3 = 0, + parameter PORT_MEM_Q_PINLOC_4 = 0, + parameter PORT_MEM_Q_PINLOC_5 = 0, + parameter PORT_MEM_Q_PINLOC_6 = 0, + parameter PORT_MEM_Q_PINLOC_7 = 0, + parameter PORT_MEM_Q_PINLOC_8 = 0, + parameter PORT_MEM_Q_PINLOC_9 = 0, + parameter PORT_MEM_Q_PINLOC_10 = 0, + parameter PORT_MEM_Q_PINLOC_11 = 0, + parameter PORT_MEM_Q_PINLOC_12 = 0, + parameter PORT_MEM_Q_PINLOC_13 = 0, + parameter PORT_MEM_Q_PINLOC_14 = 0, + parameter PORT_MEM_Q_PINLOC_15 = 0, + parameter PORT_MEM_Q_PINLOC_16 = 0, + parameter PORT_MEM_Q_PINLOC_17 = 0, + parameter PORT_MEM_Q_PINLOC_18 = 0, + parameter PORT_MEM_Q_PINLOC_19 = 0, + parameter PORT_MEM_Q_PINLOC_20 = 0, + parameter PORT_MEM_Q_PINLOC_21 = 0, + parameter PORT_MEM_Q_PINLOC_22 = 0, + parameter PORT_MEM_Q_PINLOC_23 = 0, + parameter PORT_MEM_Q_PINLOC_24 = 0, + parameter PORT_MEM_Q_PINLOC_25 = 0, + parameter PORT_MEM_Q_PINLOC_26 = 0, + parameter PORT_MEM_Q_PINLOC_27 = 0, + parameter PORT_MEM_Q_PINLOC_28 = 0, + parameter PORT_MEM_Q_PINLOC_29 = 0, + parameter PORT_MEM_Q_PINLOC_30 = 0, + parameter PORT_MEM_Q_PINLOC_31 = 0, + parameter PORT_MEM_Q_PINLOC_32 = 0, + parameter PORT_MEM_Q_PINLOC_33 = 0, + parameter PORT_MEM_Q_PINLOC_34 = 0, + parameter PORT_MEM_Q_PINLOC_35 = 0, + parameter PORT_MEM_Q_PINLOC_36 = 0, + parameter PORT_MEM_Q_PINLOC_37 = 0, + parameter PORT_MEM_Q_PINLOC_38 = 0, + parameter PORT_MEM_Q_PINLOC_39 = 0, + parameter PORT_MEM_Q_PINLOC_40 = 0, + parameter PORT_MEM_Q_PINLOC_41 = 0, + parameter PORT_MEM_Q_PINLOC_42 = 0, + parameter PORT_MEM_Q_PINLOC_43 = 0, + parameter PORT_MEM_Q_PINLOC_44 = 0, + parameter PORT_MEM_Q_PINLOC_45 = 0, + parameter PORT_MEM_Q_PINLOC_46 = 0, + parameter PORT_MEM_Q_PINLOC_47 = 0, + parameter PORT_MEM_Q_PINLOC_48 = 0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_WIDTH = 0, + parameter PORT_MEM_DQS_PINLOC_0 = 0, + parameter PORT_MEM_DQS_PINLOC_1 = 0, + parameter PORT_MEM_DQS_PINLOC_2 = 0, + parameter PORT_MEM_DQS_PINLOC_3 = 0, + parameter PORT_MEM_DQS_PINLOC_4 = 0, + parameter PORT_MEM_DQS_PINLOC_5 = 0, + parameter PORT_MEM_DQS_PINLOC_6 = 0, + parameter PORT_MEM_DQS_PINLOC_7 = 0, + parameter PORT_MEM_DQS_PINLOC_8 = 0, + parameter PORT_MEM_DQS_PINLOC_9 = 0, + parameter PORT_MEM_DQS_PINLOC_10 = 0, + parameter PORT_MEM_DQS_PINLOC_11 = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_WIDTH = 0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_WIDTH = 0, + parameter PORT_MEM_QK_PINLOC_0 = 0, + parameter PORT_MEM_QK_PINLOC_1 = 0, + parameter PORT_MEM_QK_PINLOC_2 = 0, + parameter PORT_MEM_QK_PINLOC_3 = 0, + parameter PORT_MEM_QK_PINLOC_4 = 0, + parameter PORT_MEM_QK_PINLOC_5 = 0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_WIDTH = 0, + parameter PORT_MEM_QK_N_PINLOC_0 = 0, + parameter PORT_MEM_QK_N_PINLOC_1 = 0, + parameter PORT_MEM_QK_N_PINLOC_2 = 0, + parameter PORT_MEM_QK_N_PINLOC_3 = 0, + parameter PORT_MEM_QK_N_PINLOC_4 = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKA_PINLOC_0 = 0, + parameter PORT_MEM_QKA_PINLOC_1 = 0, + parameter PORT_MEM_QKA_PINLOC_2 = 0, + parameter PORT_MEM_QKA_PINLOC_3 = 0, + parameter PORT_MEM_QKA_PINLOC_4 = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_WIDTH = 0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_QKB_PINLOC_0 = 0, + parameter PORT_MEM_QKB_PINLOC_1 = 0, + parameter PORT_MEM_QKB_PINLOC_2 = 0, + parameter PORT_MEM_QKB_PINLOC_3 = 0, + parameter PORT_MEM_QKB_PINLOC_4 = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_WIDTH = 0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_WIDTH = 0, + parameter PORT_MEM_CQ_PINLOC_0 = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_WIDTH = 0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_WIDTH = 0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_WIDTH = 0, + parameter PORT_MEM_PE_N_PINLOC_0 = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 0, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 0, + parameter PORT_AFI_RLAT_WIDTH = 0, + parameter PORT_AFI_WLAT_WIDTH = 0, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 0, + parameter PORT_AFI_ADDR_WIDTH = 0, + parameter PORT_AFI_BA_WIDTH = 0, + parameter PORT_AFI_BG_WIDTH = 0, + parameter PORT_AFI_C_WIDTH = 0, + parameter PORT_AFI_CKE_WIDTH = 0, + parameter PORT_AFI_CS_N_WIDTH = 0, + parameter PORT_AFI_RM_WIDTH = 0, + parameter PORT_AFI_ODT_WIDTH = 0, + parameter PORT_AFI_RAS_N_WIDTH = 0, + parameter PORT_AFI_CAS_N_WIDTH = 0, + parameter PORT_AFI_WE_N_WIDTH = 0, + parameter PORT_AFI_RST_N_WIDTH = 0, + parameter PORT_AFI_ACT_N_WIDTH = 0, + parameter PORT_AFI_PAR_WIDTH = 0, + parameter PORT_AFI_CA_WIDTH = 0, + parameter PORT_AFI_REF_N_WIDTH = 0, + parameter PORT_AFI_WPS_N_WIDTH = 0, + parameter PORT_AFI_RPS_N_WIDTH = 0, + parameter PORT_AFI_DOFF_N_WIDTH = 0, + parameter PORT_AFI_LD_N_WIDTH = 0, + parameter PORT_AFI_RW_N_WIDTH = 0, + parameter PORT_AFI_LBK0_N_WIDTH = 0, + parameter PORT_AFI_LBK1_N_WIDTH = 0, + parameter PORT_AFI_CFG_N_WIDTH = 0, + parameter PORT_AFI_AP_WIDTH = 0, + parameter PORT_AFI_AINV_WIDTH = 0, + parameter PORT_AFI_DM_WIDTH = 0, + parameter PORT_AFI_DM_N_WIDTH = 0, + parameter PORT_AFI_BWS_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DINV_WIDTH = 0, + parameter PORT_AFI_WDATA_DINV_WIDTH = 0, + parameter PORT_AFI_DQS_BURST_WIDTH = 0, + parameter PORT_AFI_WDATA_VALID_WIDTH = 0, + parameter PORT_AFI_WDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 0, + parameter PORT_AFI_RDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_VALID_WIDTH = 0, + parameter PORT_AFI_RRANK_WIDTH = 0, + parameter PORT_AFI_WRANK_WIDTH = 0, + parameter PORT_AFI_ALERT_N_WIDTH = 0, + parameter PORT_AFI_PE_N_WIDTH = 0, + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 0, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_AMM_RDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 0, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 0, + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 0, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 0, + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 0, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_RDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_WDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH = 0, + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 0, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 0, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 0, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 0, + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 0, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 0, + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 0, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 0, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 0, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 0, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 0, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_SIM_CAL_SLAVE_CLK_FREQ_PS = 0, + parameter PLL_SIM_CAL_MASTER_CLK_FREQ_PS = 0, + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_8 = "" +) ( + input logic global_reset_n, + input logic pll_ref_clk, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + input logic oct_rzqin, + output logic [0:0] mem_ck, + output logic [0:0] mem_ck_n, + output logic [16:0] mem_a, + output logic [0:0] mem_act_n, + output logic [1:0] mem_ba, + output logic [1:0] mem_bg, + output logic [0:0] mem_c, + output logic [0:0] mem_cke, + output logic [0:0] mem_cs_n, + output logic [0:0] mem_rm, + output logic [0:0] mem_odt, + output logic [0:0] mem_reset_n, + output logic [0:0] mem_par, + input logic [0:0] mem_alert_n, + inout tri [7:0] mem_dqs, + inout tri [7:0] mem_dqs_n, + inout tri [63:0] mem_dq, + inout tri [7:0] mem_dbi_n, + output logic [0:0] mem_dk, + output logic [0:0] mem_dk_n, + output logic [0:0] mem_dka, + output logic [0:0] mem_dka_n, + output logic [0:0] mem_dkb, + output logic [0:0] mem_dkb_n, + output logic [0:0] mem_k, + output logic [0:0] mem_k_n, + output logic [0:0] mem_ras_n, + output logic [0:0] mem_cas_n, + output logic [0:0] mem_we_n, + output logic [0:0] mem_ca, + output logic [0:0] mem_ref_n, + output logic [0:0] mem_wps_n, + output logic [0:0] mem_rps_n, + output logic [0:0] mem_doff_n, + output logic [0:0] mem_lda_n, + output logic [0:0] mem_ldb_n, + output logic [0:0] mem_rwa_n, + output logic [0:0] mem_rwb_n, + output logic [0:0] mem_lbk0_n, + output logic [0:0] mem_lbk1_n, + output logic [0:0] mem_cfg_n, + output logic [0:0] mem_ap, + output logic [0:0] mem_ainv, + output logic [0:0] mem_dm, + output logic [0:0] mem_bws_n, + output logic [0:0] mem_d, + inout tri [0:0] mem_dqa, + inout tri [0:0] mem_dqb, + inout tri [0:0] mem_dinva, + inout tri [0:0] mem_dinvb, + input logic [0:0] mem_q, + input logic [0:0] mem_qk, + input logic [0:0] mem_qk_n, + input logic [0:0] mem_qka, + input logic [0:0] mem_qka_n, + input logic [0:0] mem_qkb, + input logic [0:0] mem_qkb_n, + input logic [0:0] mem_cq, + input logic [0:0] mem_cq_n, + input logic [0:0] mem_pe_n, + output logic local_cal_success, + output logic local_cal_fail, + input logic vid_cal_done_persist, + output logic afi_reset_n, + output logic afi_clk, + output logic afi_half_clk, + output logic emif_usr_reset_n, + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n_sec, + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic cal_master_reset_n, + output logic cal_master_clk, + output logic cal_slave_reset_n, + output logic cal_slave_clk, + input logic cal_slave_reset_n_in, + input logic cal_slave_clk_in, + input logic cal_debug_reset_n, + input logic cal_debug_clk, + output logic cal_debug_out_reset_n, + output logic cal_debug_out_clk, + output logic [31:0] clks_sharing_master_out, + input logic [31:0] clks_sharing_slave_in, + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [5:0] afi_rlat, + output logic [5:0] afi_wlat, + output logic [3:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [0:0] afi_addr, + input logic [0:0] afi_ba, + input logic [0:0] afi_bg, + input logic [0:0] afi_c, + input logic [0:0] afi_cke, + input logic [0:0] afi_cs_n, + input logic [0:0] afi_rm, + input logic [0:0] afi_odt, + input logic [0:0] afi_ras_n, + input logic [0:0] afi_cas_n, + input logic [0:0] afi_we_n, + input logic [0:0] afi_rst_n, + input logic [0:0] afi_act_n, + input logic [0:0] afi_par, + input logic [0:0] afi_ca, + input logic [0:0] afi_ref_n, + input logic [0:0] afi_wps_n, + input logic [0:0] afi_rps_n, + input logic [0:0] afi_doff_n, + input logic [0:0] afi_ld_n, + input logic [0:0] afi_rw_n, + input logic [0:0] afi_lbk0_n, + input logic [0:0] afi_lbk1_n, + input logic [0:0] afi_cfg_n, + input logic [0:0] afi_ap, + input logic [0:0] afi_ainv, + input logic [0:0] afi_dm, + input logic [0:0] afi_dm_n, + input logic [0:0] afi_bws_n, + output logic [0:0] afi_rdata_dbi_n, + input logic [0:0] afi_wdata_dbi_n, + output logic [0:0] afi_rdata_dinv, + input logic [0:0] afi_wdata_dinv, + input logic [0:0] afi_dqs_burst, + input logic [0:0] afi_wdata_valid, + input logic [0:0] afi_wdata, + input logic [0:0] afi_rdata_en_full, + output logic [0:0] afi_rdata, + output logic [0:0] afi_rdata_valid, + input logic [0:0] afi_rrank, + input logic [0:0] afi_wrank, + output logic [0:0] afi_alert_n, + output logic [0:0] afi_pe_n, + input logic [0:0] ast_cmd_data_0, + input logic ast_cmd_valid_0, + output logic ast_cmd_ready_0, + input logic [0:0] ast_cmd_data_1, + input logic ast_cmd_valid_1, + output logic ast_cmd_ready_1, + input logic [0:0] ast_wr_data_0, + input logic ast_wr_valid_0, + output logic ast_wr_ready_0, + input logic [0:0] ast_wr_data_1, + input logic ast_wr_valid_1, + output logic ast_wr_ready_1, + output logic [0:0] ast_rd_data_0, + output logic ast_rd_valid_0, + input logic ast_rd_ready_0, + output logic [0:0] ast_rd_data_1, + output logic ast_rd_valid_1, + input logic ast_rd_ready_1, + output logic amm_ready_0, + input logic amm_read_0, + input logic amm_write_0, + input logic [25:0] amm_address_0, + output logic [511:0] amm_readdata_0, + input logic [511:0] amm_writedata_0, + input logic [6:0] amm_burstcount_0, + input logic [63:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + output logic amm_ready_1, + input logic amm_read_1, + input logic amm_write_1, + input logic [25:0] amm_address_1, + output logic [511:0] amm_readdata_1, + input logic [511:0] amm_writedata_1, + input logic [6:0] amm_burstcount_1, + input logic [63:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + input logic [3:0] ctrl_user_refresh_req, + input logic [15:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + input logic [3:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + output logic ctrl_will_refresh, + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + output logic ctrl_power_down_ack, + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + input logic [14:0] ctrl_ecc_write_info_0, + output logic [12:0] ctrl_ecc_rdata_id_0, + output logic [2:0] ctrl_ecc_read_info_0, + output logic [2:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + output logic [11:0] ctrl_ecc_wr_pointer_info_0, + input logic [14:0] ctrl_ecc_write_info_1, + output logic [12:0] ctrl_ecc_rdata_id_1, + output logic [2:0] ctrl_ecc_read_info_1, + output logic [2:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + output logic [11:0] ctrl_ecc_wr_pointer_info_1, + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [9:0] mmr_slave_address_0, + output logic [31:0] mmr_slave_readdata_0, + input logic [31:0] mmr_slave_writedata_0, + input logic [1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [9:0] mmr_slave_address_1, + output logic [31:0] mmr_slave_readdata_1, + input logic [31:0] mmr_slave_writedata_1, + input logic [1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + input logic [4095:0] hps_to_emif, + output logic [4095:0] emif_to_hps, + input logic [1:0] hps_to_emif_gp, + output logic [0:0] emif_to_hps_gp, + output logic cal_debug_waitrequest, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [23:0] cal_debug_addr, + output logic [31:0] cal_debug_read_data, + input logic [31:0] cal_debug_write_data, + input logic [3:0] cal_debug_byteenable, + output logic cal_debug_read_data_valid, + input logic cal_debug_out_waitrequest, + output logic cal_debug_out_read, + output logic cal_debug_out_write, + output logic [23:0] cal_debug_out_addr, + input logic [31:0] cal_debug_out_read_data, + output logic [31:0] cal_debug_out_write_data, + output logic [3:0] cal_debug_out_byteenable, + input logic cal_debug_out_read_data_valid, + input logic cal_master_waitrequest, + output logic cal_master_read, + output logic cal_master_write, + output logic [15:0] cal_master_addr, + input logic [31:0] cal_master_read_data, + output logic [31:0] cal_master_write_data, + output logic [3:0] cal_master_byteenable, + input logic cal_master_read_data_valid, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + input logic [7:0] ioaux_pio_in, + output logic [7:0] ioaux_pio_out, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [8:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [7:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [7:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [3:0] pll_cnt_sel, + input logic [2:0] pll_num_phase_shifts, + output logic pll_phase_done, + output logic [1:0] dft_core_clk_buf_out, + output logic [1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_top # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_TARGET_IS_ES (PHY_TARGET_IS_ES), + .PHY_TARGET_IS_ES2 (PHY_TARGET_IS_ES2), + .PHY_TARGET_IS_PRODUCTION (PHY_TARGET_IS_PRODUCTION), + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT), + .PHY_HPS_ENABLE_EARLY_RELEASE (PHY_HPS_ENABLE_EARLY_RELEASE), + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_ECLIPSE_DEBUG (DIAG_ECLIPSE_DEBUG), + .DIAG_EXPORT_VJI (DIAG_EXPORT_VJI), + .DIAG_INTERFACE_ID (DIAG_INTERFACE_ID), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .SILICON_REV (SILICON_REV), + .IS_HPS (IS_HPS), + .IS_VID (IS_VID), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .REGISTER_AFI (REGISTER_AFI), + .SEQ_SYNTH_CPU_CLK_DIVIDE (SEQ_SYNTH_CPU_CLK_DIVIDE), + .SEQ_SYNTH_CAL_CLK_DIVIDE (SEQ_SYNTH_CAL_CLK_DIVIDE), + .SEQ_SIM_CPU_CLK_DIVIDE (SEQ_SIM_CPU_CLK_DIVIDE), + .SEQ_SIM_CAL_CLK_DIVIDE (SEQ_SIM_CAL_CLK_DIVIDE), + .SEQ_SYNTH_OSC_FREQ_MHZ (SEQ_SYNTH_OSC_FREQ_MHZ), + .SEQ_SIM_OSC_FREQ_MHZ (SEQ_SIM_OSC_FREQ_MHZ), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .LANES_USAGE_0 (LANES_USAGE_0), + .LANES_USAGE_1 (LANES_USAGE_1), + .LANES_USAGE_2 (LANES_USAGE_2), + .LANES_USAGE_3 (LANES_USAGE_3), + .LANES_USAGE_AUTOGEN_WCNT (LANES_USAGE_AUTOGEN_WCNT), + .PINS_USAGE_0 (PINS_USAGE_0), + .PINS_USAGE_1 (PINS_USAGE_1), + .PINS_USAGE_2 (PINS_USAGE_2), + .PINS_USAGE_3 (PINS_USAGE_3), + .PINS_USAGE_4 (PINS_USAGE_4), + .PINS_USAGE_5 (PINS_USAGE_5), + .PINS_USAGE_6 (PINS_USAGE_6), + .PINS_USAGE_7 (PINS_USAGE_7), + .PINS_USAGE_8 (PINS_USAGE_8), + .PINS_USAGE_9 (PINS_USAGE_9), + .PINS_USAGE_10 (PINS_USAGE_10), + .PINS_USAGE_11 (PINS_USAGE_11), + .PINS_USAGE_12 (PINS_USAGE_12), + .PINS_USAGE_AUTOGEN_WCNT (PINS_USAGE_AUTOGEN_WCNT), + .PINS_RATE_0 (PINS_RATE_0), + .PINS_RATE_1 (PINS_RATE_1), + .PINS_RATE_2 (PINS_RATE_2), + .PINS_RATE_3 (PINS_RATE_3), + .PINS_RATE_4 (PINS_RATE_4), + .PINS_RATE_5 (PINS_RATE_5), + .PINS_RATE_6 (PINS_RATE_6), + .PINS_RATE_7 (PINS_RATE_7), + .PINS_RATE_8 (PINS_RATE_8), + .PINS_RATE_9 (PINS_RATE_9), + .PINS_RATE_10 (PINS_RATE_10), + .PINS_RATE_11 (PINS_RATE_11), + .PINS_RATE_12 (PINS_RATE_12), + .PINS_RATE_AUTOGEN_WCNT (PINS_RATE_AUTOGEN_WCNT), + .PINS_WDB_0 (PINS_WDB_0), + .PINS_WDB_1 (PINS_WDB_1), + .PINS_WDB_2 (PINS_WDB_2), + .PINS_WDB_3 (PINS_WDB_3), + .PINS_WDB_4 (PINS_WDB_4), + .PINS_WDB_5 (PINS_WDB_5), + .PINS_WDB_6 (PINS_WDB_6), + .PINS_WDB_7 (PINS_WDB_7), + .PINS_WDB_8 (PINS_WDB_8), + .PINS_WDB_9 (PINS_WDB_9), + .PINS_WDB_10 (PINS_WDB_10), + .PINS_WDB_11 (PINS_WDB_11), + .PINS_WDB_12 (PINS_WDB_12), + .PINS_WDB_13 (PINS_WDB_13), + .PINS_WDB_14 (PINS_WDB_14), + .PINS_WDB_15 (PINS_WDB_15), + .PINS_WDB_16 (PINS_WDB_16), + .PINS_WDB_17 (PINS_WDB_17), + .PINS_WDB_18 (PINS_WDB_18), + .PINS_WDB_19 (PINS_WDB_19), + .PINS_WDB_20 (PINS_WDB_20), + .PINS_WDB_21 (PINS_WDB_21), + .PINS_WDB_22 (PINS_WDB_22), + .PINS_WDB_23 (PINS_WDB_23), + .PINS_WDB_24 (PINS_WDB_24), + .PINS_WDB_25 (PINS_WDB_25), + .PINS_WDB_26 (PINS_WDB_26), + .PINS_WDB_27 (PINS_WDB_27), + .PINS_WDB_28 (PINS_WDB_28), + .PINS_WDB_29 (PINS_WDB_29), + .PINS_WDB_30 (PINS_WDB_30), + .PINS_WDB_31 (PINS_WDB_31), + .PINS_WDB_32 (PINS_WDB_32), + .PINS_WDB_33 (PINS_WDB_33), + .PINS_WDB_34 (PINS_WDB_34), + .PINS_WDB_35 (PINS_WDB_35), + .PINS_WDB_36 (PINS_WDB_36), + .PINS_WDB_37 (PINS_WDB_37), + .PINS_WDB_38 (PINS_WDB_38), + .PINS_WDB_AUTOGEN_WCNT (PINS_WDB_AUTOGEN_WCNT), + .PINS_DATA_IN_MODE_0 (PINS_DATA_IN_MODE_0), + .PINS_DATA_IN_MODE_1 (PINS_DATA_IN_MODE_1), + .PINS_DATA_IN_MODE_2 (PINS_DATA_IN_MODE_2), + .PINS_DATA_IN_MODE_3 (PINS_DATA_IN_MODE_3), + .PINS_DATA_IN_MODE_4 (PINS_DATA_IN_MODE_4), + .PINS_DATA_IN_MODE_5 (PINS_DATA_IN_MODE_5), + .PINS_DATA_IN_MODE_6 (PINS_DATA_IN_MODE_6), + .PINS_DATA_IN_MODE_7 (PINS_DATA_IN_MODE_7), + .PINS_DATA_IN_MODE_8 (PINS_DATA_IN_MODE_8), + .PINS_DATA_IN_MODE_9 (PINS_DATA_IN_MODE_9), + .PINS_DATA_IN_MODE_10 (PINS_DATA_IN_MODE_10), + .PINS_DATA_IN_MODE_11 (PINS_DATA_IN_MODE_11), + .PINS_DATA_IN_MODE_12 (PINS_DATA_IN_MODE_12), + .PINS_DATA_IN_MODE_13 (PINS_DATA_IN_MODE_13), + .PINS_DATA_IN_MODE_14 (PINS_DATA_IN_MODE_14), + .PINS_DATA_IN_MODE_15 (PINS_DATA_IN_MODE_15), + .PINS_DATA_IN_MODE_16 (PINS_DATA_IN_MODE_16), + .PINS_DATA_IN_MODE_17 (PINS_DATA_IN_MODE_17), + .PINS_DATA_IN_MODE_18 (PINS_DATA_IN_MODE_18), + .PINS_DATA_IN_MODE_19 (PINS_DATA_IN_MODE_19), + .PINS_DATA_IN_MODE_20 (PINS_DATA_IN_MODE_20), + .PINS_DATA_IN_MODE_21 (PINS_DATA_IN_MODE_21), + .PINS_DATA_IN_MODE_22 (PINS_DATA_IN_MODE_22), + .PINS_DATA_IN_MODE_23 (PINS_DATA_IN_MODE_23), + .PINS_DATA_IN_MODE_24 (PINS_DATA_IN_MODE_24), + .PINS_DATA_IN_MODE_25 (PINS_DATA_IN_MODE_25), + .PINS_DATA_IN_MODE_26 (PINS_DATA_IN_MODE_26), + .PINS_DATA_IN_MODE_27 (PINS_DATA_IN_MODE_27), + .PINS_DATA_IN_MODE_28 (PINS_DATA_IN_MODE_28), + .PINS_DATA_IN_MODE_29 (PINS_DATA_IN_MODE_29), + .PINS_DATA_IN_MODE_30 (PINS_DATA_IN_MODE_30), + .PINS_DATA_IN_MODE_31 (PINS_DATA_IN_MODE_31), + .PINS_DATA_IN_MODE_32 (PINS_DATA_IN_MODE_32), + .PINS_DATA_IN_MODE_33 (PINS_DATA_IN_MODE_33), + .PINS_DATA_IN_MODE_34 (PINS_DATA_IN_MODE_34), + .PINS_DATA_IN_MODE_35 (PINS_DATA_IN_MODE_35), + .PINS_DATA_IN_MODE_36 (PINS_DATA_IN_MODE_36), + .PINS_DATA_IN_MODE_37 (PINS_DATA_IN_MODE_37), + .PINS_DATA_IN_MODE_38 (PINS_DATA_IN_MODE_38), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (PINS_DATA_IN_MODE_AUTOGEN_WCNT), + .PINS_C2L_DRIVEN_0 (PINS_C2L_DRIVEN_0), + .PINS_C2L_DRIVEN_1 (PINS_C2L_DRIVEN_1), + .PINS_C2L_DRIVEN_2 (PINS_C2L_DRIVEN_2), + .PINS_C2L_DRIVEN_3 (PINS_C2L_DRIVEN_3), + .PINS_C2L_DRIVEN_4 (PINS_C2L_DRIVEN_4), + .PINS_C2L_DRIVEN_5 (PINS_C2L_DRIVEN_5), + .PINS_C2L_DRIVEN_6 (PINS_C2L_DRIVEN_6), + .PINS_C2L_DRIVEN_7 (PINS_C2L_DRIVEN_7), + .PINS_C2L_DRIVEN_8 (PINS_C2L_DRIVEN_8), + .PINS_C2L_DRIVEN_9 (PINS_C2L_DRIVEN_9), + .PINS_C2L_DRIVEN_10 (PINS_C2L_DRIVEN_10), + .PINS_C2L_DRIVEN_11 (PINS_C2L_DRIVEN_11), + .PINS_C2L_DRIVEN_12 (PINS_C2L_DRIVEN_12), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (PINS_C2L_DRIVEN_AUTOGEN_WCNT), + .PINS_DB_IN_BYPASS_0 (PINS_DB_IN_BYPASS_0), + .PINS_DB_IN_BYPASS_1 (PINS_DB_IN_BYPASS_1), + .PINS_DB_IN_BYPASS_2 (PINS_DB_IN_BYPASS_2), + .PINS_DB_IN_BYPASS_3 (PINS_DB_IN_BYPASS_3), + .PINS_DB_IN_BYPASS_4 (PINS_DB_IN_BYPASS_4), + .PINS_DB_IN_BYPASS_5 (PINS_DB_IN_BYPASS_5), + .PINS_DB_IN_BYPASS_6 (PINS_DB_IN_BYPASS_6), + .PINS_DB_IN_BYPASS_7 (PINS_DB_IN_BYPASS_7), + .PINS_DB_IN_BYPASS_8 (PINS_DB_IN_BYPASS_8), + .PINS_DB_IN_BYPASS_9 (PINS_DB_IN_BYPASS_9), + .PINS_DB_IN_BYPASS_10 (PINS_DB_IN_BYPASS_10), + .PINS_DB_IN_BYPASS_11 (PINS_DB_IN_BYPASS_11), + .PINS_DB_IN_BYPASS_12 (PINS_DB_IN_BYPASS_12), + .PINS_DB_IN_BYPASS_AUTOGEN_WCNT (PINS_DB_IN_BYPASS_AUTOGEN_WCNT), + .PINS_DB_OUT_BYPASS_0 (PINS_DB_OUT_BYPASS_0), + .PINS_DB_OUT_BYPASS_1 (PINS_DB_OUT_BYPASS_1), + .PINS_DB_OUT_BYPASS_2 (PINS_DB_OUT_BYPASS_2), + .PINS_DB_OUT_BYPASS_3 (PINS_DB_OUT_BYPASS_3), + .PINS_DB_OUT_BYPASS_4 (PINS_DB_OUT_BYPASS_4), + .PINS_DB_OUT_BYPASS_5 (PINS_DB_OUT_BYPASS_5), + .PINS_DB_OUT_BYPASS_6 (PINS_DB_OUT_BYPASS_6), + .PINS_DB_OUT_BYPASS_7 (PINS_DB_OUT_BYPASS_7), + .PINS_DB_OUT_BYPASS_8 (PINS_DB_OUT_BYPASS_8), + .PINS_DB_OUT_BYPASS_9 (PINS_DB_OUT_BYPASS_9), + .PINS_DB_OUT_BYPASS_10 (PINS_DB_OUT_BYPASS_10), + .PINS_DB_OUT_BYPASS_11 (PINS_DB_OUT_BYPASS_11), + .PINS_DB_OUT_BYPASS_12 (PINS_DB_OUT_BYPASS_12), + .PINS_DB_OUT_BYPASS_AUTOGEN_WCNT (PINS_DB_OUT_BYPASS_AUTOGEN_WCNT), + .PINS_DB_OE_BYPASS_0 (PINS_DB_OE_BYPASS_0), + .PINS_DB_OE_BYPASS_1 (PINS_DB_OE_BYPASS_1), + .PINS_DB_OE_BYPASS_2 (PINS_DB_OE_BYPASS_2), + .PINS_DB_OE_BYPASS_3 (PINS_DB_OE_BYPASS_3), + .PINS_DB_OE_BYPASS_4 (PINS_DB_OE_BYPASS_4), + .PINS_DB_OE_BYPASS_5 (PINS_DB_OE_BYPASS_5), + .PINS_DB_OE_BYPASS_6 (PINS_DB_OE_BYPASS_6), + .PINS_DB_OE_BYPASS_7 (PINS_DB_OE_BYPASS_7), + .PINS_DB_OE_BYPASS_8 (PINS_DB_OE_BYPASS_8), + .PINS_DB_OE_BYPASS_9 (PINS_DB_OE_BYPASS_9), + .PINS_DB_OE_BYPASS_10 (PINS_DB_OE_BYPASS_10), + .PINS_DB_OE_BYPASS_11 (PINS_DB_OE_BYPASS_11), + .PINS_DB_OE_BYPASS_12 (PINS_DB_OE_BYPASS_12), + .PINS_DB_OE_BYPASS_AUTOGEN_WCNT (PINS_DB_OE_BYPASS_AUTOGEN_WCNT), + .PINS_INVERT_WR_0 (PINS_INVERT_WR_0), + .PINS_INVERT_WR_1 (PINS_INVERT_WR_1), + .PINS_INVERT_WR_2 (PINS_INVERT_WR_2), + .PINS_INVERT_WR_3 (PINS_INVERT_WR_3), + .PINS_INVERT_WR_4 (PINS_INVERT_WR_4), + .PINS_INVERT_WR_5 (PINS_INVERT_WR_5), + .PINS_INVERT_WR_6 (PINS_INVERT_WR_6), + .PINS_INVERT_WR_7 (PINS_INVERT_WR_7), + .PINS_INVERT_WR_8 (PINS_INVERT_WR_8), + .PINS_INVERT_WR_9 (PINS_INVERT_WR_9), + .PINS_INVERT_WR_10 (PINS_INVERT_WR_10), + .PINS_INVERT_WR_11 (PINS_INVERT_WR_11), + .PINS_INVERT_WR_12 (PINS_INVERT_WR_12), + .PINS_INVERT_WR_AUTOGEN_WCNT (PINS_INVERT_WR_AUTOGEN_WCNT), + .PINS_INVERT_OE_0 (PINS_INVERT_OE_0), + .PINS_INVERT_OE_1 (PINS_INVERT_OE_1), + .PINS_INVERT_OE_2 (PINS_INVERT_OE_2), + .PINS_INVERT_OE_3 (PINS_INVERT_OE_3), + .PINS_INVERT_OE_4 (PINS_INVERT_OE_4), + .PINS_INVERT_OE_5 (PINS_INVERT_OE_5), + .PINS_INVERT_OE_6 (PINS_INVERT_OE_6), + .PINS_INVERT_OE_7 (PINS_INVERT_OE_7), + .PINS_INVERT_OE_8 (PINS_INVERT_OE_8), + .PINS_INVERT_OE_9 (PINS_INVERT_OE_9), + .PINS_INVERT_OE_10 (PINS_INVERT_OE_10), + .PINS_INVERT_OE_11 (PINS_INVERT_OE_11), + .PINS_INVERT_OE_12 (PINS_INVERT_OE_12), + .PINS_INVERT_OE_AUTOGEN_WCNT (PINS_INVERT_OE_AUTOGEN_WCNT), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_0 (PINS_AC_HMC_DATA_OVERRIDE_ENA_0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_1 (PINS_AC_HMC_DATA_OVERRIDE_ENA_1), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_2 (PINS_AC_HMC_DATA_OVERRIDE_ENA_2), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_3 (PINS_AC_HMC_DATA_OVERRIDE_ENA_3), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_4 (PINS_AC_HMC_DATA_OVERRIDE_ENA_4), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_5 (PINS_AC_HMC_DATA_OVERRIDE_ENA_5), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_6 (PINS_AC_HMC_DATA_OVERRIDE_ENA_6), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_7 (PINS_AC_HMC_DATA_OVERRIDE_ENA_7), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_8 (PINS_AC_HMC_DATA_OVERRIDE_ENA_8), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_9 (PINS_AC_HMC_DATA_OVERRIDE_ENA_9), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_10 (PINS_AC_HMC_DATA_OVERRIDE_ENA_10), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_11 (PINS_AC_HMC_DATA_OVERRIDE_ENA_11), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_12 (PINS_AC_HMC_DATA_OVERRIDE_ENA_12), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT (PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT), + .PINS_OCT_MODE_0 (PINS_OCT_MODE_0), + .PINS_OCT_MODE_1 (PINS_OCT_MODE_1), + .PINS_OCT_MODE_2 (PINS_OCT_MODE_2), + .PINS_OCT_MODE_3 (PINS_OCT_MODE_3), + .PINS_OCT_MODE_4 (PINS_OCT_MODE_4), + .PINS_OCT_MODE_5 (PINS_OCT_MODE_5), + .PINS_OCT_MODE_6 (PINS_OCT_MODE_6), + .PINS_OCT_MODE_7 (PINS_OCT_MODE_7), + .PINS_OCT_MODE_8 (PINS_OCT_MODE_8), + .PINS_OCT_MODE_9 (PINS_OCT_MODE_9), + .PINS_OCT_MODE_10 (PINS_OCT_MODE_10), + .PINS_OCT_MODE_11 (PINS_OCT_MODE_11), + .PINS_OCT_MODE_12 (PINS_OCT_MODE_12), + .PINS_OCT_MODE_AUTOGEN_WCNT (PINS_OCT_MODE_AUTOGEN_WCNT), + .PINS_GPIO_MODE_0 (PINS_GPIO_MODE_0), + .PINS_GPIO_MODE_1 (PINS_GPIO_MODE_1), + .PINS_GPIO_MODE_2 (PINS_GPIO_MODE_2), + .PINS_GPIO_MODE_3 (PINS_GPIO_MODE_3), + .PINS_GPIO_MODE_4 (PINS_GPIO_MODE_4), + .PINS_GPIO_MODE_5 (PINS_GPIO_MODE_5), + .PINS_GPIO_MODE_6 (PINS_GPIO_MODE_6), + .PINS_GPIO_MODE_7 (PINS_GPIO_MODE_7), + .PINS_GPIO_MODE_8 (PINS_GPIO_MODE_8), + .PINS_GPIO_MODE_9 (PINS_GPIO_MODE_9), + .PINS_GPIO_MODE_10 (PINS_GPIO_MODE_10), + .PINS_GPIO_MODE_11 (PINS_GPIO_MODE_11), + .PINS_GPIO_MODE_12 (PINS_GPIO_MODE_12), + .PINS_GPIO_MODE_AUTOGEN_WCNT (PINS_GPIO_MODE_AUTOGEN_WCNT), + .UNUSED_MEM_PINS_PINLOC_0 (UNUSED_MEM_PINS_PINLOC_0), + .UNUSED_MEM_PINS_PINLOC_1 (UNUSED_MEM_PINS_PINLOC_1), + .UNUSED_MEM_PINS_PINLOC_2 (UNUSED_MEM_PINS_PINLOC_2), + .UNUSED_MEM_PINS_PINLOC_3 (UNUSED_MEM_PINS_PINLOC_3), + .UNUSED_MEM_PINS_PINLOC_4 (UNUSED_MEM_PINS_PINLOC_4), + .UNUSED_MEM_PINS_PINLOC_5 (UNUSED_MEM_PINS_PINLOC_5), + .UNUSED_MEM_PINS_PINLOC_6 (UNUSED_MEM_PINS_PINLOC_6), + .UNUSED_MEM_PINS_PINLOC_7 (UNUSED_MEM_PINS_PINLOC_7), + .UNUSED_MEM_PINS_PINLOC_8 (UNUSED_MEM_PINS_PINLOC_8), + .UNUSED_MEM_PINS_PINLOC_9 (UNUSED_MEM_PINS_PINLOC_9), + .UNUSED_MEM_PINS_PINLOC_10 (UNUSED_MEM_PINS_PINLOC_10), + .UNUSED_MEM_PINS_PINLOC_11 (UNUSED_MEM_PINS_PINLOC_11), + .UNUSED_MEM_PINS_PINLOC_12 (UNUSED_MEM_PINS_PINLOC_12), + .UNUSED_MEM_PINS_PINLOC_13 (UNUSED_MEM_PINS_PINLOC_13), + .UNUSED_MEM_PINS_PINLOC_14 (UNUSED_MEM_PINS_PINLOC_14), + .UNUSED_MEM_PINS_PINLOC_15 (UNUSED_MEM_PINS_PINLOC_15), + .UNUSED_MEM_PINS_PINLOC_16 (UNUSED_MEM_PINS_PINLOC_16), + .UNUSED_MEM_PINS_PINLOC_17 (UNUSED_MEM_PINS_PINLOC_17), + .UNUSED_MEM_PINS_PINLOC_18 (UNUSED_MEM_PINS_PINLOC_18), + .UNUSED_MEM_PINS_PINLOC_19 (UNUSED_MEM_PINS_PINLOC_19), + .UNUSED_MEM_PINS_PINLOC_20 (UNUSED_MEM_PINS_PINLOC_20), + .UNUSED_MEM_PINS_PINLOC_21 (UNUSED_MEM_PINS_PINLOC_21), + .UNUSED_MEM_PINS_PINLOC_22 (UNUSED_MEM_PINS_PINLOC_22), + .UNUSED_MEM_PINS_PINLOC_23 (UNUSED_MEM_PINS_PINLOC_23), + .UNUSED_MEM_PINS_PINLOC_24 (UNUSED_MEM_PINS_PINLOC_24), + .UNUSED_MEM_PINS_PINLOC_25 (UNUSED_MEM_PINS_PINLOC_25), + .UNUSED_MEM_PINS_PINLOC_26 (UNUSED_MEM_PINS_PINLOC_26), + .UNUSED_MEM_PINS_PINLOC_27 (UNUSED_MEM_PINS_PINLOC_27), + .UNUSED_MEM_PINS_PINLOC_28 (UNUSED_MEM_PINS_PINLOC_28), + .UNUSED_MEM_PINS_PINLOC_29 (UNUSED_MEM_PINS_PINLOC_29), + .UNUSED_MEM_PINS_PINLOC_30 (UNUSED_MEM_PINS_PINLOC_30), + .UNUSED_MEM_PINS_PINLOC_31 (UNUSED_MEM_PINS_PINLOC_31), + .UNUSED_MEM_PINS_PINLOC_32 (UNUSED_MEM_PINS_PINLOC_32), + .UNUSED_MEM_PINS_PINLOC_33 (UNUSED_MEM_PINS_PINLOC_33), + .UNUSED_MEM_PINS_PINLOC_34 (UNUSED_MEM_PINS_PINLOC_34), + .UNUSED_MEM_PINS_PINLOC_35 (UNUSED_MEM_PINS_PINLOC_35), + .UNUSED_MEM_PINS_PINLOC_36 (UNUSED_MEM_PINS_PINLOC_36), + .UNUSED_MEM_PINS_PINLOC_37 (UNUSED_MEM_PINS_PINLOC_37), + .UNUSED_MEM_PINS_PINLOC_38 (UNUSED_MEM_PINS_PINLOC_38), + .UNUSED_MEM_PINS_PINLOC_39 (UNUSED_MEM_PINS_PINLOC_39), + .UNUSED_MEM_PINS_PINLOC_40 (UNUSED_MEM_PINS_PINLOC_40), + .UNUSED_MEM_PINS_PINLOC_41 (UNUSED_MEM_PINS_PINLOC_41), + .UNUSED_MEM_PINS_PINLOC_42 (UNUSED_MEM_PINS_PINLOC_42), + .UNUSED_MEM_PINS_PINLOC_43 (UNUSED_MEM_PINS_PINLOC_43), + .UNUSED_MEM_PINS_PINLOC_44 (UNUSED_MEM_PINS_PINLOC_44), + .UNUSED_MEM_PINS_PINLOC_45 (UNUSED_MEM_PINS_PINLOC_45), + .UNUSED_MEM_PINS_PINLOC_46 (UNUSED_MEM_PINS_PINLOC_46), + .UNUSED_MEM_PINS_PINLOC_47 (UNUSED_MEM_PINS_PINLOC_47), + .UNUSED_MEM_PINS_PINLOC_48 (UNUSED_MEM_PINS_PINLOC_48), + .UNUSED_MEM_PINS_PINLOC_49 (UNUSED_MEM_PINS_PINLOC_49), + .UNUSED_MEM_PINS_PINLOC_50 (UNUSED_MEM_PINS_PINLOC_50), + .UNUSED_MEM_PINS_PINLOC_51 (UNUSED_MEM_PINS_PINLOC_51), + .UNUSED_MEM_PINS_PINLOC_52 (UNUSED_MEM_PINS_PINLOC_52), + .UNUSED_MEM_PINS_PINLOC_53 (UNUSED_MEM_PINS_PINLOC_53), + .UNUSED_MEM_PINS_PINLOC_54 (UNUSED_MEM_PINS_PINLOC_54), + .UNUSED_MEM_PINS_PINLOC_55 (UNUSED_MEM_PINS_PINLOC_55), + .UNUSED_MEM_PINS_PINLOC_56 (UNUSED_MEM_PINS_PINLOC_56), + .UNUSED_MEM_PINS_PINLOC_57 (UNUSED_MEM_PINS_PINLOC_57), + .UNUSED_MEM_PINS_PINLOC_58 (UNUSED_MEM_PINS_PINLOC_58), + .UNUSED_MEM_PINS_PINLOC_59 (UNUSED_MEM_PINS_PINLOC_59), + .UNUSED_MEM_PINS_PINLOC_60 (UNUSED_MEM_PINS_PINLOC_60), + .UNUSED_MEM_PINS_PINLOC_61 (UNUSED_MEM_PINS_PINLOC_61), + .UNUSED_MEM_PINS_PINLOC_62 (UNUSED_MEM_PINS_PINLOC_62), + .UNUSED_MEM_PINS_PINLOC_63 (UNUSED_MEM_PINS_PINLOC_63), + .UNUSED_MEM_PINS_PINLOC_64 (UNUSED_MEM_PINS_PINLOC_64), + .UNUSED_MEM_PINS_PINLOC_65 (UNUSED_MEM_PINS_PINLOC_65), + .UNUSED_MEM_PINS_PINLOC_66 (UNUSED_MEM_PINS_PINLOC_66), + .UNUSED_MEM_PINS_PINLOC_67 (UNUSED_MEM_PINS_PINLOC_67), + .UNUSED_MEM_PINS_PINLOC_68 (UNUSED_MEM_PINS_PINLOC_68), + .UNUSED_MEM_PINS_PINLOC_69 (UNUSED_MEM_PINS_PINLOC_69), + .UNUSED_MEM_PINS_PINLOC_70 (UNUSED_MEM_PINS_PINLOC_70), + .UNUSED_MEM_PINS_PINLOC_71 (UNUSED_MEM_PINS_PINLOC_71), + .UNUSED_MEM_PINS_PINLOC_72 (UNUSED_MEM_PINS_PINLOC_72), + .UNUSED_MEM_PINS_PINLOC_73 (UNUSED_MEM_PINS_PINLOC_73), + .UNUSED_MEM_PINS_PINLOC_74 (UNUSED_MEM_PINS_PINLOC_74), + .UNUSED_MEM_PINS_PINLOC_75 (UNUSED_MEM_PINS_PINLOC_75), + .UNUSED_MEM_PINS_PINLOC_76 (UNUSED_MEM_PINS_PINLOC_76), + .UNUSED_MEM_PINS_PINLOC_77 (UNUSED_MEM_PINS_PINLOC_77), + .UNUSED_MEM_PINS_PINLOC_78 (UNUSED_MEM_PINS_PINLOC_78), + .UNUSED_MEM_PINS_PINLOC_79 (UNUSED_MEM_PINS_PINLOC_79), + .UNUSED_MEM_PINS_PINLOC_80 (UNUSED_MEM_PINS_PINLOC_80), + .UNUSED_MEM_PINS_PINLOC_81 (UNUSED_MEM_PINS_PINLOC_81), + .UNUSED_MEM_PINS_PINLOC_82 (UNUSED_MEM_PINS_PINLOC_82), + .UNUSED_MEM_PINS_PINLOC_83 (UNUSED_MEM_PINS_PINLOC_83), + .UNUSED_MEM_PINS_PINLOC_84 (UNUSED_MEM_PINS_PINLOC_84), + .UNUSED_MEM_PINS_PINLOC_85 (UNUSED_MEM_PINS_PINLOC_85), + .UNUSED_MEM_PINS_PINLOC_86 (UNUSED_MEM_PINS_PINLOC_86), + .UNUSED_MEM_PINS_PINLOC_87 (UNUSED_MEM_PINS_PINLOC_87), + .UNUSED_MEM_PINS_PINLOC_88 (UNUSED_MEM_PINS_PINLOC_88), + .UNUSED_MEM_PINS_PINLOC_89 (UNUSED_MEM_PINS_PINLOC_89), + .UNUSED_MEM_PINS_PINLOC_90 (UNUSED_MEM_PINS_PINLOC_90), + .UNUSED_MEM_PINS_PINLOC_91 (UNUSED_MEM_PINS_PINLOC_91), + .UNUSED_MEM_PINS_PINLOC_92 (UNUSED_MEM_PINS_PINLOC_92), + .UNUSED_MEM_PINS_PINLOC_93 (UNUSED_MEM_PINS_PINLOC_93), + .UNUSED_MEM_PINS_PINLOC_94 (UNUSED_MEM_PINS_PINLOC_94), + .UNUSED_MEM_PINS_PINLOC_95 (UNUSED_MEM_PINS_PINLOC_95), + .UNUSED_MEM_PINS_PINLOC_96 (UNUSED_MEM_PINS_PINLOC_96), + .UNUSED_MEM_PINS_PINLOC_97 (UNUSED_MEM_PINS_PINLOC_97), + .UNUSED_MEM_PINS_PINLOC_98 (UNUSED_MEM_PINS_PINLOC_98), + .UNUSED_MEM_PINS_PINLOC_99 (UNUSED_MEM_PINS_PINLOC_99), + .UNUSED_MEM_PINS_PINLOC_100 (UNUSED_MEM_PINS_PINLOC_100), + .UNUSED_MEM_PINS_PINLOC_101 (UNUSED_MEM_PINS_PINLOC_101), + .UNUSED_MEM_PINS_PINLOC_102 (UNUSED_MEM_PINS_PINLOC_102), + .UNUSED_MEM_PINS_PINLOC_103 (UNUSED_MEM_PINS_PINLOC_103), + .UNUSED_MEM_PINS_PINLOC_104 (UNUSED_MEM_PINS_PINLOC_104), + .UNUSED_MEM_PINS_PINLOC_105 (UNUSED_MEM_PINS_PINLOC_105), + .UNUSED_MEM_PINS_PINLOC_106 (UNUSED_MEM_PINS_PINLOC_106), + .UNUSED_MEM_PINS_PINLOC_107 (UNUSED_MEM_PINS_PINLOC_107), + .UNUSED_MEM_PINS_PINLOC_108 (UNUSED_MEM_PINS_PINLOC_108), + .UNUSED_MEM_PINS_PINLOC_109 (UNUSED_MEM_PINS_PINLOC_109), + .UNUSED_MEM_PINS_PINLOC_110 (UNUSED_MEM_PINS_PINLOC_110), + .UNUSED_MEM_PINS_PINLOC_111 (UNUSED_MEM_PINS_PINLOC_111), + .UNUSED_MEM_PINS_PINLOC_112 (UNUSED_MEM_PINS_PINLOC_112), + .UNUSED_MEM_PINS_PINLOC_113 (UNUSED_MEM_PINS_PINLOC_113), + .UNUSED_MEM_PINS_PINLOC_114 (UNUSED_MEM_PINS_PINLOC_114), + .UNUSED_MEM_PINS_PINLOC_115 (UNUSED_MEM_PINS_PINLOC_115), + .UNUSED_MEM_PINS_PINLOC_116 (UNUSED_MEM_PINS_PINLOC_116), + .UNUSED_MEM_PINS_PINLOC_117 (UNUSED_MEM_PINS_PINLOC_117), + .UNUSED_MEM_PINS_PINLOC_118 (UNUSED_MEM_PINS_PINLOC_118), + .UNUSED_MEM_PINS_PINLOC_119 (UNUSED_MEM_PINS_PINLOC_119), + .UNUSED_MEM_PINS_PINLOC_120 (UNUSED_MEM_PINS_PINLOC_120), + .UNUSED_MEM_PINS_PINLOC_121 (UNUSED_MEM_PINS_PINLOC_121), + .UNUSED_MEM_PINS_PINLOC_122 (UNUSED_MEM_PINS_PINLOC_122), + .UNUSED_MEM_PINS_PINLOC_123 (UNUSED_MEM_PINS_PINLOC_123), + .UNUSED_MEM_PINS_PINLOC_124 (UNUSED_MEM_PINS_PINLOC_124), + .UNUSED_MEM_PINS_PINLOC_125 (UNUSED_MEM_PINS_PINLOC_125), + .UNUSED_MEM_PINS_PINLOC_126 (UNUSED_MEM_PINS_PINLOC_126), + .UNUSED_MEM_PINS_PINLOC_127 (UNUSED_MEM_PINS_PINLOC_127), + .UNUSED_MEM_PINS_PINLOC_128 (UNUSED_MEM_PINS_PINLOC_128), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT), + .UNUSED_DQS_BUSES_LANELOC_0 (UNUSED_DQS_BUSES_LANELOC_0), + .UNUSED_DQS_BUSES_LANELOC_1 (UNUSED_DQS_BUSES_LANELOC_1), + .UNUSED_DQS_BUSES_LANELOC_2 (UNUSED_DQS_BUSES_LANELOC_2), + .UNUSED_DQS_BUSES_LANELOC_3 (UNUSED_DQS_BUSES_LANELOC_3), + .UNUSED_DQS_BUSES_LANELOC_4 (UNUSED_DQS_BUSES_LANELOC_4), + .UNUSED_DQS_BUSES_LANELOC_5 (UNUSED_DQS_BUSES_LANELOC_5), + .UNUSED_DQS_BUSES_LANELOC_6 (UNUSED_DQS_BUSES_LANELOC_6), + .UNUSED_DQS_BUSES_LANELOC_7 (UNUSED_DQS_BUSES_LANELOC_7), + .UNUSED_DQS_BUSES_LANELOC_8 (UNUSED_DQS_BUSES_LANELOC_8), + .UNUSED_DQS_BUSES_LANELOC_9 (UNUSED_DQS_BUSES_LANELOC_9), + .UNUSED_DQS_BUSES_LANELOC_10 (UNUSED_DQS_BUSES_LANELOC_10), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT), + .CENTER_TIDS_0 (CENTER_TIDS_0), + .CENTER_TIDS_1 (CENTER_TIDS_1), + .CENTER_TIDS_2 (CENTER_TIDS_2), + .CENTER_TIDS_AUTOGEN_WCNT (CENTER_TIDS_AUTOGEN_WCNT), + .HMC_TIDS_0 (HMC_TIDS_0), + .HMC_TIDS_1 (HMC_TIDS_1), + .HMC_TIDS_2 (HMC_TIDS_2), + .HMC_TIDS_AUTOGEN_WCNT (HMC_TIDS_AUTOGEN_WCNT), + .LANE_TIDS_0 (LANE_TIDS_0), + .LANE_TIDS_1 (LANE_TIDS_1), + .LANE_TIDS_2 (LANE_TIDS_2), + .LANE_TIDS_3 (LANE_TIDS_3), + .LANE_TIDS_4 (LANE_TIDS_4), + .LANE_TIDS_5 (LANE_TIDS_5), + .LANE_TIDS_6 (LANE_TIDS_6), + .LANE_TIDS_7 (LANE_TIDS_7), + .LANE_TIDS_8 (LANE_TIDS_8), + .LANE_TIDS_9 (LANE_TIDS_9), + .LANE_TIDS_AUTOGEN_WCNT (LANE_TIDS_AUTOGEN_WCNT), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_HAS_DCC (PHY_HAS_DCC), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_PINLOC_0 (PORT_MEM_CK_PINLOC_0), + .PORT_MEM_CK_PINLOC_1 (PORT_MEM_CK_PINLOC_1), + .PORT_MEM_CK_PINLOC_2 (PORT_MEM_CK_PINLOC_2), + .PORT_MEM_CK_PINLOC_3 (PORT_MEM_CK_PINLOC_3), + .PORT_MEM_CK_PINLOC_4 (PORT_MEM_CK_PINLOC_4), + .PORT_MEM_CK_PINLOC_5 (PORT_MEM_CK_PINLOC_5), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_CK_N_PINLOC_0 (PORT_MEM_CK_N_PINLOC_0), + .PORT_MEM_CK_N_PINLOC_1 (PORT_MEM_CK_N_PINLOC_1), + .PORT_MEM_CK_N_PINLOC_2 (PORT_MEM_CK_N_PINLOC_2), + .PORT_MEM_CK_N_PINLOC_3 (PORT_MEM_CK_N_PINLOC_3), + .PORT_MEM_CK_N_PINLOC_4 (PORT_MEM_CK_N_PINLOC_4), + .PORT_MEM_CK_N_PINLOC_5 (PORT_MEM_CK_N_PINLOC_5), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_PINLOC_0 (PORT_MEM_DK_PINLOC_0), + .PORT_MEM_DK_PINLOC_1 (PORT_MEM_DK_PINLOC_1), + .PORT_MEM_DK_PINLOC_2 (PORT_MEM_DK_PINLOC_2), + .PORT_MEM_DK_PINLOC_3 (PORT_MEM_DK_PINLOC_3), + .PORT_MEM_DK_PINLOC_4 (PORT_MEM_DK_PINLOC_4), + .PORT_MEM_DK_PINLOC_5 (PORT_MEM_DK_PINLOC_5), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DK_N_PINLOC_0 (PORT_MEM_DK_N_PINLOC_0), + .PORT_MEM_DK_N_PINLOC_1 (PORT_MEM_DK_N_PINLOC_1), + .PORT_MEM_DK_N_PINLOC_2 (PORT_MEM_DK_N_PINLOC_2), + .PORT_MEM_DK_N_PINLOC_3 (PORT_MEM_DK_N_PINLOC_3), + .PORT_MEM_DK_N_PINLOC_4 (PORT_MEM_DK_N_PINLOC_4), + .PORT_MEM_DK_N_PINLOC_5 (PORT_MEM_DK_N_PINLOC_5), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_PINLOC_0 (PORT_MEM_DKA_PINLOC_0), + .PORT_MEM_DKA_PINLOC_1 (PORT_MEM_DKA_PINLOC_1), + .PORT_MEM_DKA_PINLOC_2 (PORT_MEM_DKA_PINLOC_2), + .PORT_MEM_DKA_PINLOC_3 (PORT_MEM_DKA_PINLOC_3), + .PORT_MEM_DKA_PINLOC_4 (PORT_MEM_DKA_PINLOC_4), + .PORT_MEM_DKA_PINLOC_5 (PORT_MEM_DKA_PINLOC_5), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKA_N_PINLOC_0 (PORT_MEM_DKA_N_PINLOC_0), + .PORT_MEM_DKA_N_PINLOC_1 (PORT_MEM_DKA_N_PINLOC_1), + .PORT_MEM_DKA_N_PINLOC_2 (PORT_MEM_DKA_N_PINLOC_2), + .PORT_MEM_DKA_N_PINLOC_3 (PORT_MEM_DKA_N_PINLOC_3), + .PORT_MEM_DKA_N_PINLOC_4 (PORT_MEM_DKA_N_PINLOC_4), + .PORT_MEM_DKA_N_PINLOC_5 (PORT_MEM_DKA_N_PINLOC_5), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_PINLOC_0 (PORT_MEM_DKB_PINLOC_0), + .PORT_MEM_DKB_PINLOC_1 (PORT_MEM_DKB_PINLOC_1), + .PORT_MEM_DKB_PINLOC_2 (PORT_MEM_DKB_PINLOC_2), + .PORT_MEM_DKB_PINLOC_3 (PORT_MEM_DKB_PINLOC_3), + .PORT_MEM_DKB_PINLOC_4 (PORT_MEM_DKB_PINLOC_4), + .PORT_MEM_DKB_PINLOC_5 (PORT_MEM_DKB_PINLOC_5), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_DKB_N_PINLOC_0 (PORT_MEM_DKB_N_PINLOC_0), + .PORT_MEM_DKB_N_PINLOC_1 (PORT_MEM_DKB_N_PINLOC_1), + .PORT_MEM_DKB_N_PINLOC_2 (PORT_MEM_DKB_N_PINLOC_2), + .PORT_MEM_DKB_N_PINLOC_3 (PORT_MEM_DKB_N_PINLOC_3), + .PORT_MEM_DKB_N_PINLOC_4 (PORT_MEM_DKB_N_PINLOC_4), + .PORT_MEM_DKB_N_PINLOC_5 (PORT_MEM_DKB_N_PINLOC_5), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_PINLOC_0 (PORT_MEM_K_PINLOC_0), + .PORT_MEM_K_PINLOC_1 (PORT_MEM_K_PINLOC_1), + .PORT_MEM_K_PINLOC_2 (PORT_MEM_K_PINLOC_2), + .PORT_MEM_K_PINLOC_3 (PORT_MEM_K_PINLOC_3), + .PORT_MEM_K_PINLOC_4 (PORT_MEM_K_PINLOC_4), + .PORT_MEM_K_PINLOC_5 (PORT_MEM_K_PINLOC_5), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_K_N_PINLOC_0 (PORT_MEM_K_N_PINLOC_0), + .PORT_MEM_K_N_PINLOC_1 (PORT_MEM_K_N_PINLOC_1), + .PORT_MEM_K_N_PINLOC_2 (PORT_MEM_K_N_PINLOC_2), + .PORT_MEM_K_N_PINLOC_3 (PORT_MEM_K_N_PINLOC_3), + .PORT_MEM_K_N_PINLOC_4 (PORT_MEM_K_N_PINLOC_4), + .PORT_MEM_K_N_PINLOC_5 (PORT_MEM_K_N_PINLOC_5), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_A_PINLOC_0 (PORT_MEM_A_PINLOC_0), + .PORT_MEM_A_PINLOC_1 (PORT_MEM_A_PINLOC_1), + .PORT_MEM_A_PINLOC_2 (PORT_MEM_A_PINLOC_2), + .PORT_MEM_A_PINLOC_3 (PORT_MEM_A_PINLOC_3), + .PORT_MEM_A_PINLOC_4 (PORT_MEM_A_PINLOC_4), + .PORT_MEM_A_PINLOC_5 (PORT_MEM_A_PINLOC_5), + .PORT_MEM_A_PINLOC_6 (PORT_MEM_A_PINLOC_6), + .PORT_MEM_A_PINLOC_7 (PORT_MEM_A_PINLOC_7), + .PORT_MEM_A_PINLOC_8 (PORT_MEM_A_PINLOC_8), + .PORT_MEM_A_PINLOC_9 (PORT_MEM_A_PINLOC_9), + .PORT_MEM_A_PINLOC_10 (PORT_MEM_A_PINLOC_10), + .PORT_MEM_A_PINLOC_11 (PORT_MEM_A_PINLOC_11), + .PORT_MEM_A_PINLOC_12 (PORT_MEM_A_PINLOC_12), + .PORT_MEM_A_PINLOC_13 (PORT_MEM_A_PINLOC_13), + .PORT_MEM_A_PINLOC_14 (PORT_MEM_A_PINLOC_14), + .PORT_MEM_A_PINLOC_15 (PORT_MEM_A_PINLOC_15), + .PORT_MEM_A_PINLOC_16 (PORT_MEM_A_PINLOC_16), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (PORT_MEM_A_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BA_PINLOC_0 (PORT_MEM_BA_PINLOC_0), + .PORT_MEM_BA_PINLOC_1 (PORT_MEM_BA_PINLOC_1), + .PORT_MEM_BA_PINLOC_2 (PORT_MEM_BA_PINLOC_2), + .PORT_MEM_BA_PINLOC_3 (PORT_MEM_BA_PINLOC_3), + .PORT_MEM_BA_PINLOC_4 (PORT_MEM_BA_PINLOC_4), + .PORT_MEM_BA_PINLOC_5 (PORT_MEM_BA_PINLOC_5), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (PORT_MEM_BA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_BG_PINLOC_0 (PORT_MEM_BG_PINLOC_0), + .PORT_MEM_BG_PINLOC_1 (PORT_MEM_BG_PINLOC_1), + .PORT_MEM_BG_PINLOC_2 (PORT_MEM_BG_PINLOC_2), + .PORT_MEM_BG_PINLOC_3 (PORT_MEM_BG_PINLOC_3), + .PORT_MEM_BG_PINLOC_4 (PORT_MEM_BG_PINLOC_4), + .PORT_MEM_BG_PINLOC_5 (PORT_MEM_BG_PINLOC_5), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (PORT_MEM_BG_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_C_PINLOC_0 (PORT_MEM_C_PINLOC_0), + .PORT_MEM_C_PINLOC_1 (PORT_MEM_C_PINLOC_1), + .PORT_MEM_C_PINLOC_2 (PORT_MEM_C_PINLOC_2), + .PORT_MEM_C_PINLOC_3 (PORT_MEM_C_PINLOC_3), + .PORT_MEM_C_PINLOC_4 (PORT_MEM_C_PINLOC_4), + .PORT_MEM_C_PINLOC_5 (PORT_MEM_C_PINLOC_5), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (PORT_MEM_C_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CKE_PINLOC_0 (PORT_MEM_CKE_PINLOC_0), + .PORT_MEM_CKE_PINLOC_1 (PORT_MEM_CKE_PINLOC_1), + .PORT_MEM_CKE_PINLOC_2 (PORT_MEM_CKE_PINLOC_2), + .PORT_MEM_CKE_PINLOC_3 (PORT_MEM_CKE_PINLOC_3), + .PORT_MEM_CKE_PINLOC_4 (PORT_MEM_CKE_PINLOC_4), + .PORT_MEM_CKE_PINLOC_5 (PORT_MEM_CKE_PINLOC_5), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_CS_N_PINLOC_0 (PORT_MEM_CS_N_PINLOC_0), + .PORT_MEM_CS_N_PINLOC_1 (PORT_MEM_CS_N_PINLOC_1), + .PORT_MEM_CS_N_PINLOC_2 (PORT_MEM_CS_N_PINLOC_2), + .PORT_MEM_CS_N_PINLOC_3 (PORT_MEM_CS_N_PINLOC_3), + .PORT_MEM_CS_N_PINLOC_4 (PORT_MEM_CS_N_PINLOC_4), + .PORT_MEM_CS_N_PINLOC_5 (PORT_MEM_CS_N_PINLOC_5), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_RM_PINLOC_0 (PORT_MEM_RM_PINLOC_0), + .PORT_MEM_RM_PINLOC_1 (PORT_MEM_RM_PINLOC_1), + .PORT_MEM_RM_PINLOC_2 (PORT_MEM_RM_PINLOC_2), + .PORT_MEM_RM_PINLOC_3 (PORT_MEM_RM_PINLOC_3), + .PORT_MEM_RM_PINLOC_4 (PORT_MEM_RM_PINLOC_4), + .PORT_MEM_RM_PINLOC_5 (PORT_MEM_RM_PINLOC_5), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (PORT_MEM_RM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_ODT_PINLOC_0 (PORT_MEM_ODT_PINLOC_0), + .PORT_MEM_ODT_PINLOC_1 (PORT_MEM_ODT_PINLOC_1), + .PORT_MEM_ODT_PINLOC_2 (PORT_MEM_ODT_PINLOC_2), + .PORT_MEM_ODT_PINLOC_3 (PORT_MEM_ODT_PINLOC_3), + .PORT_MEM_ODT_PINLOC_4 (PORT_MEM_ODT_PINLOC_4), + .PORT_MEM_ODT_PINLOC_5 (PORT_MEM_ODT_PINLOC_5), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_RAS_N_PINLOC_0 (PORT_MEM_RAS_N_PINLOC_0), + .PORT_MEM_RAS_N_PINLOC_1 (PORT_MEM_RAS_N_PINLOC_1), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_CAS_N_PINLOC_0 (PORT_MEM_CAS_N_PINLOC_0), + .PORT_MEM_CAS_N_PINLOC_1 (PORT_MEM_CAS_N_PINLOC_1), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_WE_N_PINLOC_0 (PORT_MEM_WE_N_PINLOC_0), + .PORT_MEM_WE_N_PINLOC_1 (PORT_MEM_WE_N_PINLOC_1), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_RESET_N_PINLOC_0 (PORT_MEM_RESET_N_PINLOC_0), + .PORT_MEM_RESET_N_PINLOC_1 (PORT_MEM_RESET_N_PINLOC_1), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_ACT_N_PINLOC_0 (PORT_MEM_ACT_N_PINLOC_0), + .PORT_MEM_ACT_N_PINLOC_1 (PORT_MEM_ACT_N_PINLOC_1), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_PAR_PINLOC_0 (PORT_MEM_PAR_PINLOC_0), + .PORT_MEM_PAR_PINLOC_1 (PORT_MEM_PAR_PINLOC_1), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_CA_PINLOC_0 (PORT_MEM_CA_PINLOC_0), + .PORT_MEM_CA_PINLOC_1 (PORT_MEM_CA_PINLOC_1), + .PORT_MEM_CA_PINLOC_2 (PORT_MEM_CA_PINLOC_2), + .PORT_MEM_CA_PINLOC_3 (PORT_MEM_CA_PINLOC_3), + .PORT_MEM_CA_PINLOC_4 (PORT_MEM_CA_PINLOC_4), + .PORT_MEM_CA_PINLOC_5 (PORT_MEM_CA_PINLOC_5), + .PORT_MEM_CA_PINLOC_6 (PORT_MEM_CA_PINLOC_6), + .PORT_MEM_CA_PINLOC_7 (PORT_MEM_CA_PINLOC_7), + .PORT_MEM_CA_PINLOC_8 (PORT_MEM_CA_PINLOC_8), + .PORT_MEM_CA_PINLOC_9 (PORT_MEM_CA_PINLOC_9), + .PORT_MEM_CA_PINLOC_10 (PORT_MEM_CA_PINLOC_10), + .PORT_MEM_CA_PINLOC_11 (PORT_MEM_CA_PINLOC_11), + .PORT_MEM_CA_PINLOC_12 (PORT_MEM_CA_PINLOC_12), + .PORT_MEM_CA_PINLOC_13 (PORT_MEM_CA_PINLOC_13), + .PORT_MEM_CA_PINLOC_14 (PORT_MEM_CA_PINLOC_14), + .PORT_MEM_CA_PINLOC_15 (PORT_MEM_CA_PINLOC_15), + .PORT_MEM_CA_PINLOC_16 (PORT_MEM_CA_PINLOC_16), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (PORT_MEM_CA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_REF_N_PINLOC_0 (PORT_MEM_REF_N_PINLOC_0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_WPS_N_PINLOC_0 (PORT_MEM_WPS_N_PINLOC_0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_RPS_N_PINLOC_0 (PORT_MEM_RPS_N_PINLOC_0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_DOFF_N_PINLOC_0 (PORT_MEM_DOFF_N_PINLOC_0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDA_N_PINLOC_0 (PORT_MEM_LDA_N_PINLOC_0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_LDB_N_PINLOC_0 (PORT_MEM_LDB_N_PINLOC_0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWA_N_PINLOC_0 (PORT_MEM_RWA_N_PINLOC_0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_RWB_N_PINLOC_0 (PORT_MEM_RWB_N_PINLOC_0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK0_N_PINLOC_0 (PORT_MEM_LBK0_N_PINLOC_0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_LBK1_N_PINLOC_0 (PORT_MEM_LBK1_N_PINLOC_0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_CFG_N_PINLOC_0 (PORT_MEM_CFG_N_PINLOC_0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AP_PINLOC_0 (PORT_MEM_AP_PINLOC_0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (PORT_MEM_AP_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_AINV_PINLOC_0 (PORT_MEM_AINV_PINLOC_0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DM_PINLOC_0 (PORT_MEM_DM_PINLOC_0), + .PORT_MEM_DM_PINLOC_1 (PORT_MEM_DM_PINLOC_1), + .PORT_MEM_DM_PINLOC_2 (PORT_MEM_DM_PINLOC_2), + .PORT_MEM_DM_PINLOC_3 (PORT_MEM_DM_PINLOC_3), + .PORT_MEM_DM_PINLOC_4 (PORT_MEM_DM_PINLOC_4), + .PORT_MEM_DM_PINLOC_5 (PORT_MEM_DM_PINLOC_5), + .PORT_MEM_DM_PINLOC_6 (PORT_MEM_DM_PINLOC_6), + .PORT_MEM_DM_PINLOC_7 (PORT_MEM_DM_PINLOC_7), + .PORT_MEM_DM_PINLOC_8 (PORT_MEM_DM_PINLOC_8), + .PORT_MEM_DM_PINLOC_9 (PORT_MEM_DM_PINLOC_9), + .PORT_MEM_DM_PINLOC_10 (PORT_MEM_DM_PINLOC_10), + .PORT_MEM_DM_PINLOC_11 (PORT_MEM_DM_PINLOC_11), + .PORT_MEM_DM_PINLOC_12 (PORT_MEM_DM_PINLOC_12), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (PORT_MEM_DM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_BWS_N_PINLOC_0 (PORT_MEM_BWS_N_PINLOC_0), + .PORT_MEM_BWS_N_PINLOC_1 (PORT_MEM_BWS_N_PINLOC_1), + .PORT_MEM_BWS_N_PINLOC_2 (PORT_MEM_BWS_N_PINLOC_2), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_D_PINLOC_0 (PORT_MEM_D_PINLOC_0), + .PORT_MEM_D_PINLOC_1 (PORT_MEM_D_PINLOC_1), + .PORT_MEM_D_PINLOC_2 (PORT_MEM_D_PINLOC_2), + .PORT_MEM_D_PINLOC_3 (PORT_MEM_D_PINLOC_3), + .PORT_MEM_D_PINLOC_4 (PORT_MEM_D_PINLOC_4), + .PORT_MEM_D_PINLOC_5 (PORT_MEM_D_PINLOC_5), + .PORT_MEM_D_PINLOC_6 (PORT_MEM_D_PINLOC_6), + .PORT_MEM_D_PINLOC_7 (PORT_MEM_D_PINLOC_7), + .PORT_MEM_D_PINLOC_8 (PORT_MEM_D_PINLOC_8), + .PORT_MEM_D_PINLOC_9 (PORT_MEM_D_PINLOC_9), + .PORT_MEM_D_PINLOC_10 (PORT_MEM_D_PINLOC_10), + .PORT_MEM_D_PINLOC_11 (PORT_MEM_D_PINLOC_11), + .PORT_MEM_D_PINLOC_12 (PORT_MEM_D_PINLOC_12), + .PORT_MEM_D_PINLOC_13 (PORT_MEM_D_PINLOC_13), + .PORT_MEM_D_PINLOC_14 (PORT_MEM_D_PINLOC_14), + .PORT_MEM_D_PINLOC_15 (PORT_MEM_D_PINLOC_15), + .PORT_MEM_D_PINLOC_16 (PORT_MEM_D_PINLOC_16), + .PORT_MEM_D_PINLOC_17 (PORT_MEM_D_PINLOC_17), + .PORT_MEM_D_PINLOC_18 (PORT_MEM_D_PINLOC_18), + .PORT_MEM_D_PINLOC_19 (PORT_MEM_D_PINLOC_19), + .PORT_MEM_D_PINLOC_20 (PORT_MEM_D_PINLOC_20), + .PORT_MEM_D_PINLOC_21 (PORT_MEM_D_PINLOC_21), + .PORT_MEM_D_PINLOC_22 (PORT_MEM_D_PINLOC_22), + .PORT_MEM_D_PINLOC_23 (PORT_MEM_D_PINLOC_23), + .PORT_MEM_D_PINLOC_24 (PORT_MEM_D_PINLOC_24), + .PORT_MEM_D_PINLOC_25 (PORT_MEM_D_PINLOC_25), + .PORT_MEM_D_PINLOC_26 (PORT_MEM_D_PINLOC_26), + .PORT_MEM_D_PINLOC_27 (PORT_MEM_D_PINLOC_27), + .PORT_MEM_D_PINLOC_28 (PORT_MEM_D_PINLOC_28), + .PORT_MEM_D_PINLOC_29 (PORT_MEM_D_PINLOC_29), + .PORT_MEM_D_PINLOC_30 (PORT_MEM_D_PINLOC_30), + .PORT_MEM_D_PINLOC_31 (PORT_MEM_D_PINLOC_31), + .PORT_MEM_D_PINLOC_32 (PORT_MEM_D_PINLOC_32), + .PORT_MEM_D_PINLOC_33 (PORT_MEM_D_PINLOC_33), + .PORT_MEM_D_PINLOC_34 (PORT_MEM_D_PINLOC_34), + .PORT_MEM_D_PINLOC_35 (PORT_MEM_D_PINLOC_35), + .PORT_MEM_D_PINLOC_36 (PORT_MEM_D_PINLOC_36), + .PORT_MEM_D_PINLOC_37 (PORT_MEM_D_PINLOC_37), + .PORT_MEM_D_PINLOC_38 (PORT_MEM_D_PINLOC_38), + .PORT_MEM_D_PINLOC_39 (PORT_MEM_D_PINLOC_39), + .PORT_MEM_D_PINLOC_40 (PORT_MEM_D_PINLOC_40), + .PORT_MEM_D_PINLOC_41 (PORT_MEM_D_PINLOC_41), + .PORT_MEM_D_PINLOC_42 (PORT_MEM_D_PINLOC_42), + .PORT_MEM_D_PINLOC_43 (PORT_MEM_D_PINLOC_43), + .PORT_MEM_D_PINLOC_44 (PORT_MEM_D_PINLOC_44), + .PORT_MEM_D_PINLOC_45 (PORT_MEM_D_PINLOC_45), + .PORT_MEM_D_PINLOC_46 (PORT_MEM_D_PINLOC_46), + .PORT_MEM_D_PINLOC_47 (PORT_MEM_D_PINLOC_47), + .PORT_MEM_D_PINLOC_48 (PORT_MEM_D_PINLOC_48), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (PORT_MEM_D_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DQ_PINLOC_0 (PORT_MEM_DQ_PINLOC_0), + .PORT_MEM_DQ_PINLOC_1 (PORT_MEM_DQ_PINLOC_1), + .PORT_MEM_DQ_PINLOC_2 (PORT_MEM_DQ_PINLOC_2), + .PORT_MEM_DQ_PINLOC_3 (PORT_MEM_DQ_PINLOC_3), + .PORT_MEM_DQ_PINLOC_4 (PORT_MEM_DQ_PINLOC_4), + .PORT_MEM_DQ_PINLOC_5 (PORT_MEM_DQ_PINLOC_5), + .PORT_MEM_DQ_PINLOC_6 (PORT_MEM_DQ_PINLOC_6), + .PORT_MEM_DQ_PINLOC_7 (PORT_MEM_DQ_PINLOC_7), + .PORT_MEM_DQ_PINLOC_8 (PORT_MEM_DQ_PINLOC_8), + .PORT_MEM_DQ_PINLOC_9 (PORT_MEM_DQ_PINLOC_9), + .PORT_MEM_DQ_PINLOC_10 (PORT_MEM_DQ_PINLOC_10), + .PORT_MEM_DQ_PINLOC_11 (PORT_MEM_DQ_PINLOC_11), + .PORT_MEM_DQ_PINLOC_12 (PORT_MEM_DQ_PINLOC_12), + .PORT_MEM_DQ_PINLOC_13 (PORT_MEM_DQ_PINLOC_13), + .PORT_MEM_DQ_PINLOC_14 (PORT_MEM_DQ_PINLOC_14), + .PORT_MEM_DQ_PINLOC_15 (PORT_MEM_DQ_PINLOC_15), + .PORT_MEM_DQ_PINLOC_16 (PORT_MEM_DQ_PINLOC_16), + .PORT_MEM_DQ_PINLOC_17 (PORT_MEM_DQ_PINLOC_17), + .PORT_MEM_DQ_PINLOC_18 (PORT_MEM_DQ_PINLOC_18), + .PORT_MEM_DQ_PINLOC_19 (PORT_MEM_DQ_PINLOC_19), + .PORT_MEM_DQ_PINLOC_20 (PORT_MEM_DQ_PINLOC_20), + .PORT_MEM_DQ_PINLOC_21 (PORT_MEM_DQ_PINLOC_21), + .PORT_MEM_DQ_PINLOC_22 (PORT_MEM_DQ_PINLOC_22), + .PORT_MEM_DQ_PINLOC_23 (PORT_MEM_DQ_PINLOC_23), + .PORT_MEM_DQ_PINLOC_24 (PORT_MEM_DQ_PINLOC_24), + .PORT_MEM_DQ_PINLOC_25 (PORT_MEM_DQ_PINLOC_25), + .PORT_MEM_DQ_PINLOC_26 (PORT_MEM_DQ_PINLOC_26), + .PORT_MEM_DQ_PINLOC_27 (PORT_MEM_DQ_PINLOC_27), + .PORT_MEM_DQ_PINLOC_28 (PORT_MEM_DQ_PINLOC_28), + .PORT_MEM_DQ_PINLOC_29 (PORT_MEM_DQ_PINLOC_29), + .PORT_MEM_DQ_PINLOC_30 (PORT_MEM_DQ_PINLOC_30), + .PORT_MEM_DQ_PINLOC_31 (PORT_MEM_DQ_PINLOC_31), + .PORT_MEM_DQ_PINLOC_32 (PORT_MEM_DQ_PINLOC_32), + .PORT_MEM_DQ_PINLOC_33 (PORT_MEM_DQ_PINLOC_33), + .PORT_MEM_DQ_PINLOC_34 (PORT_MEM_DQ_PINLOC_34), + .PORT_MEM_DQ_PINLOC_35 (PORT_MEM_DQ_PINLOC_35), + .PORT_MEM_DQ_PINLOC_36 (PORT_MEM_DQ_PINLOC_36), + .PORT_MEM_DQ_PINLOC_37 (PORT_MEM_DQ_PINLOC_37), + .PORT_MEM_DQ_PINLOC_38 (PORT_MEM_DQ_PINLOC_38), + .PORT_MEM_DQ_PINLOC_39 (PORT_MEM_DQ_PINLOC_39), + .PORT_MEM_DQ_PINLOC_40 (PORT_MEM_DQ_PINLOC_40), + .PORT_MEM_DQ_PINLOC_41 (PORT_MEM_DQ_PINLOC_41), + .PORT_MEM_DQ_PINLOC_42 (PORT_MEM_DQ_PINLOC_42), + .PORT_MEM_DQ_PINLOC_43 (PORT_MEM_DQ_PINLOC_43), + .PORT_MEM_DQ_PINLOC_44 (PORT_MEM_DQ_PINLOC_44), + .PORT_MEM_DQ_PINLOC_45 (PORT_MEM_DQ_PINLOC_45), + .PORT_MEM_DQ_PINLOC_46 (PORT_MEM_DQ_PINLOC_46), + .PORT_MEM_DQ_PINLOC_47 (PORT_MEM_DQ_PINLOC_47), + .PORT_MEM_DQ_PINLOC_48 (PORT_MEM_DQ_PINLOC_48), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DBI_N_PINLOC_0 (PORT_MEM_DBI_N_PINLOC_0), + .PORT_MEM_DBI_N_PINLOC_1 (PORT_MEM_DBI_N_PINLOC_1), + .PORT_MEM_DBI_N_PINLOC_2 (PORT_MEM_DBI_N_PINLOC_2), + .PORT_MEM_DBI_N_PINLOC_3 (PORT_MEM_DBI_N_PINLOC_3), + .PORT_MEM_DBI_N_PINLOC_4 (PORT_MEM_DBI_N_PINLOC_4), + .PORT_MEM_DBI_N_PINLOC_5 (PORT_MEM_DBI_N_PINLOC_5), + .PORT_MEM_DBI_N_PINLOC_6 (PORT_MEM_DBI_N_PINLOC_6), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQA_PINLOC_0 (PORT_MEM_DQA_PINLOC_0), + .PORT_MEM_DQA_PINLOC_1 (PORT_MEM_DQA_PINLOC_1), + .PORT_MEM_DQA_PINLOC_2 (PORT_MEM_DQA_PINLOC_2), + .PORT_MEM_DQA_PINLOC_3 (PORT_MEM_DQA_PINLOC_3), + .PORT_MEM_DQA_PINLOC_4 (PORT_MEM_DQA_PINLOC_4), + .PORT_MEM_DQA_PINLOC_5 (PORT_MEM_DQA_PINLOC_5), + .PORT_MEM_DQA_PINLOC_6 (PORT_MEM_DQA_PINLOC_6), + .PORT_MEM_DQA_PINLOC_7 (PORT_MEM_DQA_PINLOC_7), + .PORT_MEM_DQA_PINLOC_8 (PORT_MEM_DQA_PINLOC_8), + .PORT_MEM_DQA_PINLOC_9 (PORT_MEM_DQA_PINLOC_9), + .PORT_MEM_DQA_PINLOC_10 (PORT_MEM_DQA_PINLOC_10), + .PORT_MEM_DQA_PINLOC_11 (PORT_MEM_DQA_PINLOC_11), + .PORT_MEM_DQA_PINLOC_12 (PORT_MEM_DQA_PINLOC_12), + .PORT_MEM_DQA_PINLOC_13 (PORT_MEM_DQA_PINLOC_13), + .PORT_MEM_DQA_PINLOC_14 (PORT_MEM_DQA_PINLOC_14), + .PORT_MEM_DQA_PINLOC_15 (PORT_MEM_DQA_PINLOC_15), + .PORT_MEM_DQA_PINLOC_16 (PORT_MEM_DQA_PINLOC_16), + .PORT_MEM_DQA_PINLOC_17 (PORT_MEM_DQA_PINLOC_17), + .PORT_MEM_DQA_PINLOC_18 (PORT_MEM_DQA_PINLOC_18), + .PORT_MEM_DQA_PINLOC_19 (PORT_MEM_DQA_PINLOC_19), + .PORT_MEM_DQA_PINLOC_20 (PORT_MEM_DQA_PINLOC_20), + .PORT_MEM_DQA_PINLOC_21 (PORT_MEM_DQA_PINLOC_21), + .PORT_MEM_DQA_PINLOC_22 (PORT_MEM_DQA_PINLOC_22), + .PORT_MEM_DQA_PINLOC_23 (PORT_MEM_DQA_PINLOC_23), + .PORT_MEM_DQA_PINLOC_24 (PORT_MEM_DQA_PINLOC_24), + .PORT_MEM_DQA_PINLOC_25 (PORT_MEM_DQA_PINLOC_25), + .PORT_MEM_DQA_PINLOC_26 (PORT_MEM_DQA_PINLOC_26), + .PORT_MEM_DQA_PINLOC_27 (PORT_MEM_DQA_PINLOC_27), + .PORT_MEM_DQA_PINLOC_28 (PORT_MEM_DQA_PINLOC_28), + .PORT_MEM_DQA_PINLOC_29 (PORT_MEM_DQA_PINLOC_29), + .PORT_MEM_DQA_PINLOC_30 (PORT_MEM_DQA_PINLOC_30), + .PORT_MEM_DQA_PINLOC_31 (PORT_MEM_DQA_PINLOC_31), + .PORT_MEM_DQA_PINLOC_32 (PORT_MEM_DQA_PINLOC_32), + .PORT_MEM_DQA_PINLOC_33 (PORT_MEM_DQA_PINLOC_33), + .PORT_MEM_DQA_PINLOC_34 (PORT_MEM_DQA_PINLOC_34), + .PORT_MEM_DQA_PINLOC_35 (PORT_MEM_DQA_PINLOC_35), + .PORT_MEM_DQA_PINLOC_36 (PORT_MEM_DQA_PINLOC_36), + .PORT_MEM_DQA_PINLOC_37 (PORT_MEM_DQA_PINLOC_37), + .PORT_MEM_DQA_PINLOC_38 (PORT_MEM_DQA_PINLOC_38), + .PORT_MEM_DQA_PINLOC_39 (PORT_MEM_DQA_PINLOC_39), + .PORT_MEM_DQA_PINLOC_40 (PORT_MEM_DQA_PINLOC_40), + .PORT_MEM_DQA_PINLOC_41 (PORT_MEM_DQA_PINLOC_41), + .PORT_MEM_DQA_PINLOC_42 (PORT_MEM_DQA_PINLOC_42), + .PORT_MEM_DQA_PINLOC_43 (PORT_MEM_DQA_PINLOC_43), + .PORT_MEM_DQA_PINLOC_44 (PORT_MEM_DQA_PINLOC_44), + .PORT_MEM_DQA_PINLOC_45 (PORT_MEM_DQA_PINLOC_45), + .PORT_MEM_DQA_PINLOC_46 (PORT_MEM_DQA_PINLOC_46), + .PORT_MEM_DQA_PINLOC_47 (PORT_MEM_DQA_PINLOC_47), + .PORT_MEM_DQA_PINLOC_48 (PORT_MEM_DQA_PINLOC_48), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DQB_PINLOC_0 (PORT_MEM_DQB_PINLOC_0), + .PORT_MEM_DQB_PINLOC_1 (PORT_MEM_DQB_PINLOC_1), + .PORT_MEM_DQB_PINLOC_2 (PORT_MEM_DQB_PINLOC_2), + .PORT_MEM_DQB_PINLOC_3 (PORT_MEM_DQB_PINLOC_3), + .PORT_MEM_DQB_PINLOC_4 (PORT_MEM_DQB_PINLOC_4), + .PORT_MEM_DQB_PINLOC_5 (PORT_MEM_DQB_PINLOC_5), + .PORT_MEM_DQB_PINLOC_6 (PORT_MEM_DQB_PINLOC_6), + .PORT_MEM_DQB_PINLOC_7 (PORT_MEM_DQB_PINLOC_7), + .PORT_MEM_DQB_PINLOC_8 (PORT_MEM_DQB_PINLOC_8), + .PORT_MEM_DQB_PINLOC_9 (PORT_MEM_DQB_PINLOC_9), + .PORT_MEM_DQB_PINLOC_10 (PORT_MEM_DQB_PINLOC_10), + .PORT_MEM_DQB_PINLOC_11 (PORT_MEM_DQB_PINLOC_11), + .PORT_MEM_DQB_PINLOC_12 (PORT_MEM_DQB_PINLOC_12), + .PORT_MEM_DQB_PINLOC_13 (PORT_MEM_DQB_PINLOC_13), + .PORT_MEM_DQB_PINLOC_14 (PORT_MEM_DQB_PINLOC_14), + .PORT_MEM_DQB_PINLOC_15 (PORT_MEM_DQB_PINLOC_15), + .PORT_MEM_DQB_PINLOC_16 (PORT_MEM_DQB_PINLOC_16), + .PORT_MEM_DQB_PINLOC_17 (PORT_MEM_DQB_PINLOC_17), + .PORT_MEM_DQB_PINLOC_18 (PORT_MEM_DQB_PINLOC_18), + .PORT_MEM_DQB_PINLOC_19 (PORT_MEM_DQB_PINLOC_19), + .PORT_MEM_DQB_PINLOC_20 (PORT_MEM_DQB_PINLOC_20), + .PORT_MEM_DQB_PINLOC_21 (PORT_MEM_DQB_PINLOC_21), + .PORT_MEM_DQB_PINLOC_22 (PORT_MEM_DQB_PINLOC_22), + .PORT_MEM_DQB_PINLOC_23 (PORT_MEM_DQB_PINLOC_23), + .PORT_MEM_DQB_PINLOC_24 (PORT_MEM_DQB_PINLOC_24), + .PORT_MEM_DQB_PINLOC_25 (PORT_MEM_DQB_PINLOC_25), + .PORT_MEM_DQB_PINLOC_26 (PORT_MEM_DQB_PINLOC_26), + .PORT_MEM_DQB_PINLOC_27 (PORT_MEM_DQB_PINLOC_27), + .PORT_MEM_DQB_PINLOC_28 (PORT_MEM_DQB_PINLOC_28), + .PORT_MEM_DQB_PINLOC_29 (PORT_MEM_DQB_PINLOC_29), + .PORT_MEM_DQB_PINLOC_30 (PORT_MEM_DQB_PINLOC_30), + .PORT_MEM_DQB_PINLOC_31 (PORT_MEM_DQB_PINLOC_31), + .PORT_MEM_DQB_PINLOC_32 (PORT_MEM_DQB_PINLOC_32), + .PORT_MEM_DQB_PINLOC_33 (PORT_MEM_DQB_PINLOC_33), + .PORT_MEM_DQB_PINLOC_34 (PORT_MEM_DQB_PINLOC_34), + .PORT_MEM_DQB_PINLOC_35 (PORT_MEM_DQB_PINLOC_35), + .PORT_MEM_DQB_PINLOC_36 (PORT_MEM_DQB_PINLOC_36), + .PORT_MEM_DQB_PINLOC_37 (PORT_MEM_DQB_PINLOC_37), + .PORT_MEM_DQB_PINLOC_38 (PORT_MEM_DQB_PINLOC_38), + .PORT_MEM_DQB_PINLOC_39 (PORT_MEM_DQB_PINLOC_39), + .PORT_MEM_DQB_PINLOC_40 (PORT_MEM_DQB_PINLOC_40), + .PORT_MEM_DQB_PINLOC_41 (PORT_MEM_DQB_PINLOC_41), + .PORT_MEM_DQB_PINLOC_42 (PORT_MEM_DQB_PINLOC_42), + .PORT_MEM_DQB_PINLOC_43 (PORT_MEM_DQB_PINLOC_43), + .PORT_MEM_DQB_PINLOC_44 (PORT_MEM_DQB_PINLOC_44), + .PORT_MEM_DQB_PINLOC_45 (PORT_MEM_DQB_PINLOC_45), + .PORT_MEM_DQB_PINLOC_46 (PORT_MEM_DQB_PINLOC_46), + .PORT_MEM_DQB_PINLOC_47 (PORT_MEM_DQB_PINLOC_47), + .PORT_MEM_DQB_PINLOC_48 (PORT_MEM_DQB_PINLOC_48), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVA_PINLOC_0 (PORT_MEM_DINVA_PINLOC_0), + .PORT_MEM_DINVA_PINLOC_1 (PORT_MEM_DINVA_PINLOC_1), + .PORT_MEM_DINVA_PINLOC_2 (PORT_MEM_DINVA_PINLOC_2), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_DINVB_PINLOC_0 (PORT_MEM_DINVB_PINLOC_0), + .PORT_MEM_DINVB_PINLOC_1 (PORT_MEM_DINVB_PINLOC_1), + .PORT_MEM_DINVB_PINLOC_2 (PORT_MEM_DINVB_PINLOC_2), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_Q_PINLOC_0 (PORT_MEM_Q_PINLOC_0), + .PORT_MEM_Q_PINLOC_1 (PORT_MEM_Q_PINLOC_1), + .PORT_MEM_Q_PINLOC_2 (PORT_MEM_Q_PINLOC_2), + .PORT_MEM_Q_PINLOC_3 (PORT_MEM_Q_PINLOC_3), + .PORT_MEM_Q_PINLOC_4 (PORT_MEM_Q_PINLOC_4), + .PORT_MEM_Q_PINLOC_5 (PORT_MEM_Q_PINLOC_5), + .PORT_MEM_Q_PINLOC_6 (PORT_MEM_Q_PINLOC_6), + .PORT_MEM_Q_PINLOC_7 (PORT_MEM_Q_PINLOC_7), + .PORT_MEM_Q_PINLOC_8 (PORT_MEM_Q_PINLOC_8), + .PORT_MEM_Q_PINLOC_9 (PORT_MEM_Q_PINLOC_9), + .PORT_MEM_Q_PINLOC_10 (PORT_MEM_Q_PINLOC_10), + .PORT_MEM_Q_PINLOC_11 (PORT_MEM_Q_PINLOC_11), + .PORT_MEM_Q_PINLOC_12 (PORT_MEM_Q_PINLOC_12), + .PORT_MEM_Q_PINLOC_13 (PORT_MEM_Q_PINLOC_13), + .PORT_MEM_Q_PINLOC_14 (PORT_MEM_Q_PINLOC_14), + .PORT_MEM_Q_PINLOC_15 (PORT_MEM_Q_PINLOC_15), + .PORT_MEM_Q_PINLOC_16 (PORT_MEM_Q_PINLOC_16), + .PORT_MEM_Q_PINLOC_17 (PORT_MEM_Q_PINLOC_17), + .PORT_MEM_Q_PINLOC_18 (PORT_MEM_Q_PINLOC_18), + .PORT_MEM_Q_PINLOC_19 (PORT_MEM_Q_PINLOC_19), + .PORT_MEM_Q_PINLOC_20 (PORT_MEM_Q_PINLOC_20), + .PORT_MEM_Q_PINLOC_21 (PORT_MEM_Q_PINLOC_21), + .PORT_MEM_Q_PINLOC_22 (PORT_MEM_Q_PINLOC_22), + .PORT_MEM_Q_PINLOC_23 (PORT_MEM_Q_PINLOC_23), + .PORT_MEM_Q_PINLOC_24 (PORT_MEM_Q_PINLOC_24), + .PORT_MEM_Q_PINLOC_25 (PORT_MEM_Q_PINLOC_25), + .PORT_MEM_Q_PINLOC_26 (PORT_MEM_Q_PINLOC_26), + .PORT_MEM_Q_PINLOC_27 (PORT_MEM_Q_PINLOC_27), + .PORT_MEM_Q_PINLOC_28 (PORT_MEM_Q_PINLOC_28), + .PORT_MEM_Q_PINLOC_29 (PORT_MEM_Q_PINLOC_29), + .PORT_MEM_Q_PINLOC_30 (PORT_MEM_Q_PINLOC_30), + .PORT_MEM_Q_PINLOC_31 (PORT_MEM_Q_PINLOC_31), + .PORT_MEM_Q_PINLOC_32 (PORT_MEM_Q_PINLOC_32), + .PORT_MEM_Q_PINLOC_33 (PORT_MEM_Q_PINLOC_33), + .PORT_MEM_Q_PINLOC_34 (PORT_MEM_Q_PINLOC_34), + .PORT_MEM_Q_PINLOC_35 (PORT_MEM_Q_PINLOC_35), + .PORT_MEM_Q_PINLOC_36 (PORT_MEM_Q_PINLOC_36), + .PORT_MEM_Q_PINLOC_37 (PORT_MEM_Q_PINLOC_37), + .PORT_MEM_Q_PINLOC_38 (PORT_MEM_Q_PINLOC_38), + .PORT_MEM_Q_PINLOC_39 (PORT_MEM_Q_PINLOC_39), + .PORT_MEM_Q_PINLOC_40 (PORT_MEM_Q_PINLOC_40), + .PORT_MEM_Q_PINLOC_41 (PORT_MEM_Q_PINLOC_41), + .PORT_MEM_Q_PINLOC_42 (PORT_MEM_Q_PINLOC_42), + .PORT_MEM_Q_PINLOC_43 (PORT_MEM_Q_PINLOC_43), + .PORT_MEM_Q_PINLOC_44 (PORT_MEM_Q_PINLOC_44), + .PORT_MEM_Q_PINLOC_45 (PORT_MEM_Q_PINLOC_45), + .PORT_MEM_Q_PINLOC_46 (PORT_MEM_Q_PINLOC_46), + .PORT_MEM_Q_PINLOC_47 (PORT_MEM_Q_PINLOC_47), + .PORT_MEM_Q_PINLOC_48 (PORT_MEM_Q_PINLOC_48), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (PORT_MEM_Q_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_PINLOC_0 (PORT_MEM_DQS_PINLOC_0), + .PORT_MEM_DQS_PINLOC_1 (PORT_MEM_DQS_PINLOC_1), + .PORT_MEM_DQS_PINLOC_2 (PORT_MEM_DQS_PINLOC_2), + .PORT_MEM_DQS_PINLOC_3 (PORT_MEM_DQS_PINLOC_3), + .PORT_MEM_DQS_PINLOC_4 (PORT_MEM_DQS_PINLOC_4), + .PORT_MEM_DQS_PINLOC_5 (PORT_MEM_DQS_PINLOC_5), + .PORT_MEM_DQS_PINLOC_6 (PORT_MEM_DQS_PINLOC_6), + .PORT_MEM_DQS_PINLOC_7 (PORT_MEM_DQS_PINLOC_7), + .PORT_MEM_DQS_PINLOC_8 (PORT_MEM_DQS_PINLOC_8), + .PORT_MEM_DQS_PINLOC_9 (PORT_MEM_DQS_PINLOC_9), + .PORT_MEM_DQS_PINLOC_10 (PORT_MEM_DQS_PINLOC_10), + .PORT_MEM_DQS_PINLOC_11 (PORT_MEM_DQS_PINLOC_11), + .PORT_MEM_DQS_PINLOC_12 (PORT_MEM_DQS_PINLOC_12), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_DQS_N_PINLOC_0 (PORT_MEM_DQS_N_PINLOC_0), + .PORT_MEM_DQS_N_PINLOC_1 (PORT_MEM_DQS_N_PINLOC_1), + .PORT_MEM_DQS_N_PINLOC_2 (PORT_MEM_DQS_N_PINLOC_2), + .PORT_MEM_DQS_N_PINLOC_3 (PORT_MEM_DQS_N_PINLOC_3), + .PORT_MEM_DQS_N_PINLOC_4 (PORT_MEM_DQS_N_PINLOC_4), + .PORT_MEM_DQS_N_PINLOC_5 (PORT_MEM_DQS_N_PINLOC_5), + .PORT_MEM_DQS_N_PINLOC_6 (PORT_MEM_DQS_N_PINLOC_6), + .PORT_MEM_DQS_N_PINLOC_7 (PORT_MEM_DQS_N_PINLOC_7), + .PORT_MEM_DQS_N_PINLOC_8 (PORT_MEM_DQS_N_PINLOC_8), + .PORT_MEM_DQS_N_PINLOC_9 (PORT_MEM_DQS_N_PINLOC_9), + .PORT_MEM_DQS_N_PINLOC_10 (PORT_MEM_DQS_N_PINLOC_10), + .PORT_MEM_DQS_N_PINLOC_11 (PORT_MEM_DQS_N_PINLOC_11), + .PORT_MEM_DQS_N_PINLOC_12 (PORT_MEM_DQS_N_PINLOC_12), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_PINLOC_0 (PORT_MEM_QK_PINLOC_0), + .PORT_MEM_QK_PINLOC_1 (PORT_MEM_QK_PINLOC_1), + .PORT_MEM_QK_PINLOC_2 (PORT_MEM_QK_PINLOC_2), + .PORT_MEM_QK_PINLOC_3 (PORT_MEM_QK_PINLOC_3), + .PORT_MEM_QK_PINLOC_4 (PORT_MEM_QK_PINLOC_4), + .PORT_MEM_QK_PINLOC_5 (PORT_MEM_QK_PINLOC_5), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QK_N_PINLOC_0 (PORT_MEM_QK_N_PINLOC_0), + .PORT_MEM_QK_N_PINLOC_1 (PORT_MEM_QK_N_PINLOC_1), + .PORT_MEM_QK_N_PINLOC_2 (PORT_MEM_QK_N_PINLOC_2), + .PORT_MEM_QK_N_PINLOC_3 (PORT_MEM_QK_N_PINLOC_3), + .PORT_MEM_QK_N_PINLOC_4 (PORT_MEM_QK_N_PINLOC_4), + .PORT_MEM_QK_N_PINLOC_5 (PORT_MEM_QK_N_PINLOC_5), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_PINLOC_0 (PORT_MEM_QKA_PINLOC_0), + .PORT_MEM_QKA_PINLOC_1 (PORT_MEM_QKA_PINLOC_1), + .PORT_MEM_QKA_PINLOC_2 (PORT_MEM_QKA_PINLOC_2), + .PORT_MEM_QKA_PINLOC_3 (PORT_MEM_QKA_PINLOC_3), + .PORT_MEM_QKA_PINLOC_4 (PORT_MEM_QKA_PINLOC_4), + .PORT_MEM_QKA_PINLOC_5 (PORT_MEM_QKA_PINLOC_5), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKA_N_PINLOC_0 (PORT_MEM_QKA_N_PINLOC_0), + .PORT_MEM_QKA_N_PINLOC_1 (PORT_MEM_QKA_N_PINLOC_1), + .PORT_MEM_QKA_N_PINLOC_2 (PORT_MEM_QKA_N_PINLOC_2), + .PORT_MEM_QKA_N_PINLOC_3 (PORT_MEM_QKA_N_PINLOC_3), + .PORT_MEM_QKA_N_PINLOC_4 (PORT_MEM_QKA_N_PINLOC_4), + .PORT_MEM_QKA_N_PINLOC_5 (PORT_MEM_QKA_N_PINLOC_5), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_PINLOC_0 (PORT_MEM_QKB_PINLOC_0), + .PORT_MEM_QKB_PINLOC_1 (PORT_MEM_QKB_PINLOC_1), + .PORT_MEM_QKB_PINLOC_2 (PORT_MEM_QKB_PINLOC_2), + .PORT_MEM_QKB_PINLOC_3 (PORT_MEM_QKB_PINLOC_3), + .PORT_MEM_QKB_PINLOC_4 (PORT_MEM_QKB_PINLOC_4), + .PORT_MEM_QKB_PINLOC_5 (PORT_MEM_QKB_PINLOC_5), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_QKB_N_PINLOC_0 (PORT_MEM_QKB_N_PINLOC_0), + .PORT_MEM_QKB_N_PINLOC_1 (PORT_MEM_QKB_N_PINLOC_1), + .PORT_MEM_QKB_N_PINLOC_2 (PORT_MEM_QKB_N_PINLOC_2), + .PORT_MEM_QKB_N_PINLOC_3 (PORT_MEM_QKB_N_PINLOC_3), + .PORT_MEM_QKB_N_PINLOC_4 (PORT_MEM_QKB_N_PINLOC_4), + .PORT_MEM_QKB_N_PINLOC_5 (PORT_MEM_QKB_N_PINLOC_5), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_PINLOC_0 (PORT_MEM_CQ_PINLOC_0), + .PORT_MEM_CQ_PINLOC_1 (PORT_MEM_CQ_PINLOC_1), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_CQ_N_PINLOC_0 (PORT_MEM_CQ_N_PINLOC_0), + .PORT_MEM_CQ_N_PINLOC_1 (PORT_MEM_CQ_N_PINLOC_1), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_ALERT_N_PINLOC_0 (PORT_MEM_ALERT_N_PINLOC_0), + .PORT_MEM_ALERT_N_PINLOC_1 (PORT_MEM_ALERT_N_PINLOC_1), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_PE_N_PINLOC_0 (PORT_MEM_PE_N_PINLOC_0), + .PORT_MEM_PE_N_PINLOC_1 (PORT_MEM_PE_N_PINLOC_1), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH), + .PORT_HPS_EMIF_H2E_WIDTH (PORT_HPS_EMIF_H2E_WIDTH), + .PORT_HPS_EMIF_E2H_WIDTH (PORT_HPS_EMIF_E2H_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH (PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_OUT_RDATA_WIDTH (PORT_CAL_DEBUG_OUT_RDATA_WIDTH), + .PORT_CAL_DEBUG_OUT_WDATA_WIDTH (PORT_CAL_DEBUG_OUT_WDATA_WIDTH), + .PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH (PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH), + .PORT_CAL_MASTER_ADDRESS_WIDTH (PORT_CAL_MASTER_ADDRESS_WIDTH), + .PORT_CAL_MASTER_RDATA_WIDTH (PORT_CAL_MASTER_RDATA_WIDTH), + .PORT_CAL_MASTER_WDATA_WIDTH (PORT_CAL_MASTER_WDATA_WIDTH), + .PORT_CAL_MASTER_BYTEEN_WIDTH (PORT_CAL_MASTER_BYTEEN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (PORT_DFT_NF_IOAUX_PIO_IN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .PLL_PHY_CLK_VCO_PHASE (PLL_PHY_CLK_VCO_PHASE), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_PS (PLL_REF_CLK_FREQ_PS), + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (PLL_SIM_CAL_SLAVE_CLK_FREQ_PS), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (PLL_SIM_CAL_MASTER_CLK_FREQ_PS), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_BW_SEL (PLL_BW_SEL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .SEQ_SYNTH_PARAMS_HEX_FILENAME ("ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_params_synth.hex"), + .SEQ_SIM_PARAMS_HEX_FILENAME ("ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_params_sim.hex"), + .SEQ_CODE_HEX_FILENAME ("ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_cal.hex") + ) arch_inst ( + .global_reset_n (global_reset_n), + .pll_ref_clk (pll_ref_clk), + .pll_locked (pll_locked), + .pll_extra_clk_0 (pll_extra_clk_0), + .pll_extra_clk_1 (pll_extra_clk_1), + .pll_extra_clk_2 (pll_extra_clk_2), + .pll_extra_clk_3 (pll_extra_clk_3), + .oct_rzqin (oct_rzqin), + .mem_ck (mem_ck), + .mem_ck_n (mem_ck_n), + .mem_a (mem_a), + .mem_act_n (mem_act_n), + .mem_ba (mem_ba), + .mem_bg (mem_bg), + .mem_c (mem_c), + .mem_cke (mem_cke), + .mem_cs_n (mem_cs_n), + .mem_rm (mem_rm), + .mem_odt (mem_odt), + .mem_reset_n (mem_reset_n), + .mem_par (mem_par), + .mem_alert_n (mem_alert_n), + .mem_dqs (mem_dqs), + .mem_dqs_n (mem_dqs_n), + .mem_dq (mem_dq), + .mem_dbi_n (mem_dbi_n), + .mem_dk (mem_dk), + .mem_dk_n (mem_dk_n), + .mem_dka (mem_dka), + .mem_dka_n (mem_dka_n), + .mem_dkb (mem_dkb), + .mem_dkb_n (mem_dkb_n), + .mem_k (mem_k), + .mem_k_n (mem_k_n), + .mem_ras_n (mem_ras_n), + .mem_cas_n (mem_cas_n), + .mem_we_n (mem_we_n), + .mem_ca (mem_ca), + .mem_ref_n (mem_ref_n), + .mem_wps_n (mem_wps_n), + .mem_rps_n (mem_rps_n), + .mem_doff_n (mem_doff_n), + .mem_lda_n (mem_lda_n), + .mem_ldb_n (mem_ldb_n), + .mem_rwa_n (mem_rwa_n), + .mem_rwb_n (mem_rwb_n), + .mem_lbk0_n (mem_lbk0_n), + .mem_lbk1_n (mem_lbk1_n), + .mem_cfg_n (mem_cfg_n), + .mem_ap (mem_ap), + .mem_ainv (mem_ainv), + .mem_dm (mem_dm), + .mem_bws_n (mem_bws_n), + .mem_d (mem_d), + .mem_dqa (mem_dqa), + .mem_dqb (mem_dqb), + .mem_dinva (mem_dinva), + .mem_dinvb (mem_dinvb), + .mem_q (mem_q), + .mem_qk (mem_qk), + .mem_qk_n (mem_qk_n), + .mem_qka (mem_qka), + .mem_qka_n (mem_qka_n), + .mem_qkb (mem_qkb), + .mem_qkb_n (mem_qkb_n), + .mem_cq (mem_cq), + .mem_cq_n (mem_cq_n), + .mem_pe_n (mem_pe_n), + .local_cal_success (local_cal_success), + .local_cal_fail (local_cal_fail), + .vid_cal_done_persist (vid_cal_done_persist), + .afi_reset_n (afi_reset_n), + .afi_clk (afi_clk), + .afi_half_clk (afi_half_clk), + .emif_usr_reset_n (emif_usr_reset_n), + .emif_usr_clk (emif_usr_clk), + .emif_usr_half_clk (emif_usr_half_clk), + .emif_usr_reset_n_sec (emif_usr_reset_n_sec), + .emif_usr_clk_sec (emif_usr_clk_sec), + .emif_usr_half_clk_sec (emif_usr_half_clk_sec), + .cal_master_reset_n (cal_master_reset_n), + .cal_master_clk (cal_master_clk), + .cal_slave_reset_n (cal_slave_reset_n), + .cal_slave_clk (cal_slave_clk), + .cal_slave_reset_n_in (cal_slave_reset_n_in), + .cal_slave_clk_in (cal_slave_clk_in), + .cal_debug_reset_n (cal_debug_reset_n), + .cal_debug_clk (cal_debug_clk), + .cal_debug_out_reset_n (cal_debug_out_reset_n), + .cal_debug_out_clk (cal_debug_out_clk), + .clks_sharing_master_out (clks_sharing_master_out), + .clks_sharing_slave_in (clks_sharing_slave_in), + .afi_cal_success (afi_cal_success), + .afi_cal_fail (afi_cal_fail), + .afi_cal_req (afi_cal_req), + .afi_rlat (afi_rlat), + .afi_wlat (afi_wlat), + .afi_seq_busy (afi_seq_busy), + .afi_ctl_refresh_done (afi_ctl_refresh_done), + .afi_ctl_long_idle (afi_ctl_long_idle), + .afi_mps_req (afi_mps_req), + .afi_mps_ack (afi_mps_ack), + .afi_addr (afi_addr), + .afi_ba (afi_ba), + .afi_bg (afi_bg), + .afi_c (afi_c), + .afi_cke (afi_cke), + .afi_cs_n (afi_cs_n), + .afi_rm (afi_rm), + .afi_odt (afi_odt), + .afi_ras_n (afi_ras_n), + .afi_cas_n (afi_cas_n), + .afi_we_n (afi_we_n), + .afi_rst_n (afi_rst_n), + .afi_act_n (afi_act_n), + .afi_par (afi_par), + .afi_ca (afi_ca), + .afi_ref_n (afi_ref_n), + .afi_wps_n (afi_wps_n), + .afi_rps_n (afi_rps_n), + .afi_doff_n (afi_doff_n), + .afi_ld_n (afi_ld_n), + .afi_rw_n (afi_rw_n), + .afi_lbk0_n (afi_lbk0_n), + .afi_lbk1_n (afi_lbk1_n), + .afi_cfg_n (afi_cfg_n), + .afi_ap (afi_ap), + .afi_ainv (afi_ainv), + .afi_dm (afi_dm), + .afi_dm_n (afi_dm_n), + .afi_bws_n (afi_bws_n), + .afi_rdata_dbi_n (afi_rdata_dbi_n), + .afi_wdata_dbi_n (afi_wdata_dbi_n), + .afi_rdata_dinv (afi_rdata_dinv), + .afi_wdata_dinv (afi_wdata_dinv), + .afi_dqs_burst (afi_dqs_burst), + .afi_wdata_valid (afi_wdata_valid), + .afi_wdata (afi_wdata), + .afi_rdata_en_full (afi_rdata_en_full), + .afi_rdata (afi_rdata), + .afi_rdata_valid (afi_rdata_valid), + .afi_rrank (afi_rrank), + .afi_wrank (afi_wrank), + .afi_alert_n (afi_alert_n), + .afi_pe_n (afi_pe_n), + .ast_cmd_data_0 (ast_cmd_data_0), + .ast_cmd_valid_0 (ast_cmd_valid_0), + .ast_cmd_ready_0 (ast_cmd_ready_0), + .ast_cmd_data_1 (ast_cmd_data_1), + .ast_cmd_valid_1 (ast_cmd_valid_1), + .ast_cmd_ready_1 (ast_cmd_ready_1), + .ast_wr_data_0 (ast_wr_data_0), + .ast_wr_valid_0 (ast_wr_valid_0), + .ast_wr_ready_0 (ast_wr_ready_0), + .ast_wr_data_1 (ast_wr_data_1), + .ast_wr_valid_1 (ast_wr_valid_1), + .ast_wr_ready_1 (ast_wr_ready_1), + .ast_rd_data_0 (ast_rd_data_0), + .ast_rd_valid_0 (ast_rd_valid_0), + .ast_rd_ready_0 (ast_rd_ready_0), + .ast_rd_data_1 (ast_rd_data_1), + .ast_rd_valid_1 (ast_rd_valid_1), + .ast_rd_ready_1 (ast_rd_ready_1), + .amm_ready_0 (amm_ready_0), + .amm_read_0 (amm_read_0), + .amm_write_0 (amm_write_0), + .amm_address_0 (amm_address_0), + .amm_readdata_0 (amm_readdata_0), + .amm_writedata_0 (amm_writedata_0), + .amm_burstcount_0 (amm_burstcount_0), + .amm_byteenable_0 (amm_byteenable_0), + .amm_beginbursttransfer_0 (amm_beginbursttransfer_0), + .amm_readdatavalid_0 (amm_readdatavalid_0), + .amm_ready_1 (amm_ready_1), + .amm_read_1 (amm_read_1), + .amm_write_1 (amm_write_1), + .amm_address_1 (amm_address_1), + .amm_readdata_1 (amm_readdata_1), + .amm_writedata_1 (amm_writedata_1), + .amm_burstcount_1 (amm_burstcount_1), + .amm_byteenable_1 (amm_byteenable_1), + .amm_beginbursttransfer_1 (amm_beginbursttransfer_1), + .amm_readdatavalid_1 (amm_readdatavalid_1), + .ctrl_user_priority_hi_0 (ctrl_user_priority_hi_0), + .ctrl_user_priority_hi_1 (ctrl_user_priority_hi_1), + .ctrl_auto_precharge_req_0 (ctrl_auto_precharge_req_0), + .ctrl_auto_precharge_req_1 (ctrl_auto_precharge_req_1), + .ctrl_user_refresh_req (ctrl_user_refresh_req), + .ctrl_user_refresh_bank (ctrl_user_refresh_bank), + .ctrl_user_refresh_ack (ctrl_user_refresh_ack), + .ctrl_self_refresh_req (ctrl_self_refresh_req), + .ctrl_self_refresh_ack (ctrl_self_refresh_ack), + .ctrl_will_refresh (ctrl_will_refresh), + .ctrl_deep_power_down_req (ctrl_deep_power_down_req), + .ctrl_deep_power_down_ack (ctrl_deep_power_down_ack), + .ctrl_power_down_ack (ctrl_power_down_ack), + .ctrl_zq_cal_long_req (ctrl_zq_cal_long_req), + .ctrl_zq_cal_short_req (ctrl_zq_cal_short_req), + .ctrl_zq_cal_ack (ctrl_zq_cal_ack), + .ctrl_ecc_write_info_0 (ctrl_ecc_write_info_0), + .ctrl_ecc_rdata_id_0 (ctrl_ecc_rdata_id_0), + .ctrl_ecc_read_info_0 (ctrl_ecc_read_info_0), + .ctrl_ecc_cmd_info_0 (ctrl_ecc_cmd_info_0), + .ctrl_ecc_idle_0 (ctrl_ecc_idle_0), + .ctrl_ecc_wr_pointer_info_0 (ctrl_ecc_wr_pointer_info_0), + .ctrl_ecc_write_info_1 (ctrl_ecc_write_info_1), + .ctrl_ecc_rdata_id_1 (ctrl_ecc_rdata_id_1), + .ctrl_ecc_read_info_1 (ctrl_ecc_read_info_1), + .ctrl_ecc_cmd_info_1 (ctrl_ecc_cmd_info_1), + .ctrl_ecc_idle_1 (ctrl_ecc_idle_1), + .ctrl_ecc_wr_pointer_info_1 (ctrl_ecc_wr_pointer_info_1), + .mmr_slave_waitrequest_0 (mmr_slave_waitrequest_0), + .mmr_slave_read_0 (mmr_slave_read_0), + .mmr_slave_write_0 (mmr_slave_write_0), + .mmr_slave_address_0 (mmr_slave_address_0), + .mmr_slave_readdata_0 (mmr_slave_readdata_0), + .mmr_slave_writedata_0 (mmr_slave_writedata_0), + .mmr_slave_burstcount_0 (mmr_slave_burstcount_0), + .mmr_slave_beginbursttransfer_0 (mmr_slave_beginbursttransfer_0), + .mmr_slave_readdatavalid_0 (mmr_slave_readdatavalid_0), + .mmr_slave_waitrequest_1 (mmr_slave_waitrequest_1), + .mmr_slave_read_1 (mmr_slave_read_1), + .mmr_slave_write_1 (mmr_slave_write_1), + .mmr_slave_address_1 (mmr_slave_address_1), + .mmr_slave_readdata_1 (mmr_slave_readdata_1), + .mmr_slave_writedata_1 (mmr_slave_writedata_1), + .mmr_slave_burstcount_1 (mmr_slave_burstcount_1), + .mmr_slave_beginbursttransfer_1 (mmr_slave_beginbursttransfer_1), + .mmr_slave_readdatavalid_1 (mmr_slave_readdatavalid_1), + .hps_to_emif (hps_to_emif), + .emif_to_hps (emif_to_hps), + .hps_to_emif_gp (hps_to_emif_gp), + .emif_to_hps_gp (emif_to_hps_gp), + .cal_debug_waitrequest (cal_debug_waitrequest), + .cal_debug_read (cal_debug_read), + .cal_debug_write (cal_debug_write), + .cal_debug_addr (cal_debug_addr), + .cal_debug_read_data (cal_debug_read_data), + .cal_debug_write_data (cal_debug_write_data), + .cal_debug_byteenable (cal_debug_byteenable), + .cal_debug_read_data_valid (cal_debug_read_data_valid), + .cal_debug_out_waitrequest (cal_debug_out_waitrequest), + .cal_debug_out_read (cal_debug_out_read), + .cal_debug_out_write (cal_debug_out_write), + .cal_debug_out_addr (cal_debug_out_addr), + .cal_debug_out_read_data (cal_debug_out_read_data), + .cal_debug_out_write_data (cal_debug_out_write_data), + .cal_debug_out_byteenable (cal_debug_out_byteenable), + .cal_debug_out_read_data_valid (cal_debug_out_read_data_valid), + .cal_master_waitrequest (cal_master_waitrequest), + .cal_master_read (cal_master_read), + .cal_master_write (cal_master_write), + .cal_master_addr (cal_master_addr), + .cal_master_read_data (cal_master_read_data), + .cal_master_write_data (cal_master_write_data), + .cal_master_byteenable (cal_master_byteenable), + .cal_master_read_data_valid (cal_master_read_data_valid), + .cal_master_burstcount (cal_master_burstcount), + .cal_master_debugaccess (cal_master_debugaccess), + .ioaux_pio_in (ioaux_pio_in), + .ioaux_pio_out (ioaux_pio_out), + .pa_dprio_clk (pa_dprio_clk), + .pa_dprio_read (pa_dprio_read), + .pa_dprio_reg_addr (pa_dprio_reg_addr), + .pa_dprio_rst_n (pa_dprio_rst_n), + .pa_dprio_write (pa_dprio_write), + .pa_dprio_writedata (pa_dprio_writedata), + .pa_dprio_block_select (pa_dprio_block_select), + .pa_dprio_readdata (pa_dprio_readdata), + .pll_phase_en (pll_phase_en), + .pll_up_dn (pll_up_dn), + .pll_cnt_sel (pll_cnt_sel), + .pll_num_phase_shifts (pll_num_phase_shifts), + .pll_phase_done (pll_phase_done), + .dft_core_clk_buf_out (dft_core_clk_buf_out), + .dft_core_clk_locked (dft_core_clk_locked) + ); +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_io_aux.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_io_aux.sv new file mode 100644 index 000000000000..cacb91c80e2f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_io_aux.sv @@ -0,0 +1,276 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +module ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_io_aux #( + // Device parameters + parameter SILICON_REV = "", + parameter IS_HPS = 0, + parameter SEQ_CODE_HEX_FILENAME = "", + + // Synthesis Parameters + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 800, + parameter SEQ_SYNTH_PARAMS_HEX_FILENAME = "", + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + + // Simulation Parameters + parameter SEQ_SIM_OSC_FREQ_MHZ = 800, + parameter SEQ_SIM_PARAMS_HEX_FILENAME = "", + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + + // Debug Parameters + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + + // Port widths for core debug access + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 1, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 1, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 1 +) ( + input logic global_reset_n_int, + output logic cal_bus_clk, + output logic cal_bus_avl_read, + output logic cal_bus_avl_write, + output logic [19:0] cal_bus_avl_address, + input logic [31:0] cal_bus_avl_read_data, + output logic [31:0] cal_bus_avl_write_data, + + // Toolkit/On-Chip Debug Access + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_clk, + input logic cal_debug_read, + input logic cal_debug_reset_n, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + input logic cal_slave_clk_in, + input logic cal_slave_reset_n_in, + + + // Avalon Master to core + output logic [PORT_CAL_MASTER_ADDRESS_WIDTH-1:0] cal_master_addr, + output logic [PORT_CAL_MASTER_BYTEEN_WIDTH-1:0] cal_master_byteenable, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + output logic cal_master_read, + output logic cal_master_write, + output logic [PORT_CAL_MASTER_WDATA_WIDTH-1:0] cal_master_write_data, + input logic [PORT_CAL_MASTER_RDATA_WIDTH-1:0] cal_master_read_data, + input logic cal_master_read_data_valid, + input logic cal_master_waitrequest, + + // Toolkit/On-Chip Debug connection to next interface in column + output logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_out_addr, + output logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_out_byteenable, + output logic cal_debug_out_clk, + output logic cal_debug_out_read, + output logic cal_debug_out_reset_n, + output logic cal_debug_out_write, + output logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_out_write_data, + input logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_out_read_data, + input logic cal_debug_out_read_data_valid, + input logic cal_debug_out_waitrequest, + + // Internal test and debug + input logic [PORT_DFT_NF_IOAUX_PIO_IN_WIDTH-1:0] ioaux_pio_in, + output logic [PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH-1:0] ioaux_pio_out +); + timeunit 1ns; + timeprecision 1ps; + + // Derive localparam values + // The following is evaluated for simulation + // synthesis translate_off + localparam SEQ_PARAMS_HEX_FILENAME = SEQ_SIM_PARAMS_HEX_FILENAME; + localparam SEQ_CPU_CLK_DIVIDE = SEQ_SIM_CPU_CLK_DIVIDE; + localparam SEQ_CAL_CLK_DIVIDE = SEQ_SIM_CAL_CLK_DIVIDE; + localparam SEQ_OSC_FREQ_MHZ = SEQ_SIM_OSC_FREQ_MHZ; + // synthesis translate_on + + // The following is evaluated for synthesis. + // Typically we synthesize full-calibration behavior for hardware, + // except when DIAG_SYNTH_FOR_SIM is set, which allows flows such + // as post-fit simulation to adopt RTL simulation behavior. + // synthesis read_comments_as_HDL on + // localparam SEQ_PARAMS_HEX_FILENAME = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_PARAMS_HEX_FILENAME : SEQ_SYNTH_PARAMS_HEX_FILENAME; + // localparam SEQ_CPU_CLK_DIVIDE = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_CPU_CLK_DIVIDE : SEQ_SYNTH_CPU_CLK_DIVIDE; + // localparam SEQ_CAL_CLK_DIVIDE = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_CAL_CLK_DIVIDE : SEQ_SYNTH_CAL_CLK_DIVIDE; + // localparam SEQ_OSC_FREQ_MHZ = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_OSC_FREQ_MHZ : SEQ_SYNTH_OSC_FREQ_MHZ; + // synthesis read_comments_as_HDL off + + wire w_core_clk; + wire w_debug_clk; + wire [ 3: 0] w_debug_select; + wire w_mcu_en; + wire w_mode; + wire [31: 0] w_uc_read_data; + wire w_usrmode; + wire [21: 0] w_debug_out; + wire [ 8: 0] w_soft_nios_ctl_sig_bidir_out; + wire [19: 0] w_uc_address; + wire w_uc_av_bus_clk; + wire w_uc_read; + wire w_uc_write; + wire [31: 0] w_uc_write_data; + + assign cal_bus_clk = w_uc_av_bus_clk; + assign cal_bus_avl_read = w_uc_read; + assign cal_bus_avl_write = w_uc_write; + assign cal_bus_avl_write_data[31: 0] = w_uc_write_data[31: 0]; + assign cal_bus_avl_address[19: 0] = w_uc_address[19: 0]; + assign w_uc_read_data[31: 0] = cal_bus_avl_read_data[31: 0]; + assign w_core_clk = 1'b0; + + assign cal_master_debugaccess = 1'b0; + twentynm_io_aux # ( + .silicon_rev(SILICON_REV), + .sys_clk_source("int_osc_clk"), + .config_hps(IS_HPS ? "true" : "false"), + .config_io_aux_bypass("false"), + .config_power_down("false"), + .config_ram(38'h306420c0), + .config_spare(8'h00), + .nios_break_vector_word_addr(16'h8200), + .nios_exception_vector_word_addr(16'h0008), + .nios_reset_vector_word_addr(16'h0000), + .simulation_osc_freq_mhz(SEQ_OSC_FREQ_MHZ), + .sys_clk_div(SEQ_CPU_CLK_DIVIDE), + .cal_clk_div(SEQ_CAL_CLK_DIVIDE), + .nios_code_hex_file(SEQ_CODE_HEX_FILENAME), + .parameter_table_hex_file (SEQ_PARAMS_HEX_FILENAME), + .interface_id(DIAG_INTERFACE_ID), + .verbose_ioaux(DIAG_VERBOSE_IOAUX ? "true" : "false") + ) io_aux ( + .core_clk(w_core_clk), + .core_usr_reset_n(global_reset_n_int), + .debug_clk(w_debug_clk), + .debug_select(w_debug_select), + .mcu_en(w_mcu_en), + .mode(w_mode), + .soft_nios_addr(cal_debug_addr), + // synthesis translate_off + //This is needed to allow simulation of core logic driving the cal bus. + .soft_nios_burstcount(1'b1), + // synthesis translate_on + .soft_nios_byteenable(cal_debug_byteenable), + .soft_nios_clk(cal_debug_clk), + .soft_nios_read(cal_debug_read), + .soft_nios_reset_n(cal_debug_reset_n), + .soft_nios_write(cal_debug_write), + .soft_nios_write_data(cal_debug_write_data), + .soft_ram_clk(cal_slave_clk_in), + .soft_ram_reset_n(cal_slave_reset_n_in), + .soft_ram_read_data(cal_master_read_data), + .soft_ram_rdata_valid(cal_master_read_data_valid), + .soft_ram_waitrequest(cal_master_waitrequest), + .uc_read_data(w_uc_read_data), + .usrmode(w_usrmode), + .vji_cdr_to_the_hard_nios(), + .vji_ir_in_to_the_hard_nios(), + .vji_rti_to_the_hard_nios(), + .vji_sdr_to_the_hard_nios(), + .vji_tck_to_the_hard_nios(), + .vji_tdi_to_the_hard_nios(), + .vji_udr_to_the_hard_nios(), + .vji_uir_to_the_hard_nios(), + .debug_out(w_debug_out), + .soft_nios_read_data(cal_debug_read_data), + .soft_nios_read_data_valid(cal_debug_read_data_valid), + .soft_nios_waitrequest(cal_debug_waitrequest), + .soft_ram_addr(cal_master_addr), + .soft_ram_burstcount(cal_master_burstcount), + .soft_ram_byteenable(cal_master_byteenable), + .soft_ram_debugaccess(), + .soft_ram_read(cal_master_read), + .soft_ram_rst_n(), + .soft_ram_write(cal_master_write), + .soft_ram_write_data(cal_master_write_data), + .uc_address(w_uc_address), + .uc_av_bus_clk(w_uc_av_bus_clk), + .uc_read(w_uc_read), + .uc_write(w_uc_write), + .uc_write_data(w_uc_write_data), + .vji_ir_out_from_the_hard_nios(), + .vji_tdo_from_the_hard_nios(), + .soft_nios_out_addr(cal_debug_out_addr), + .soft_nios_out_burstcount(), + .soft_nios_out_byteenable(cal_debug_out_byteenable), + .soft_nios_out_clk(cal_debug_out_clk), + .soft_nios_out_read(cal_debug_out_read), + .soft_nios_out_reset_n(cal_debug_out_reset_n), + .soft_nios_out_write(cal_debug_out_write), + .soft_nios_out_write_data(cal_debug_out_write_data), + .soft_nios_out_read_data(cal_debug_out_read_data), + .soft_nios_out_read_data_valid(cal_debug_out_read_data_valid), + .soft_nios_out_waitrequest(cal_debug_out_waitrequest), + .pio_in(ioaux_pio_in), + .pio_out(ioaux_pio_out) + ); + + // Debug print + // synthesis translate_off + string debug_str = ""; + logic [31:0] chars; + always @ (posedge w_uc_av_bus_clk) begin + if (w_uc_address == 20'h1_0000 && w_uc_write) begin + chars = w_uc_write_data; + + while (chars[7:0] != 8'b0) begin + debug_str = {debug_str, string'(chars[7:0])}; + chars = chars >> 8; + end + + if ((w_uc_write_data & 32'hff) == 32'b0 || + (w_uc_write_data & 32'hff00) == 32'b0 || + (w_uc_write_data & 32'hff0000) == 32'b0 || + (w_uc_write_data & 32'hff000000) == 32'b0 ) begin + $display("%s", debug_str); + debug_str = ""; + end + end + end + // synthesis translate_on + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_cal.hex b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_cal.hex new file mode 100644 index 000000000000..916f51ac6b0f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_seq_cal.hex @@ -0,0 +1,15362 @@ +:020000020000FC +:040000000081001467 +:040001001001483A68 +:0400020010BFF8042F +:0400030000BFFD1627 +:040004000040003484 +:040005000840081493 +:040006000800683A4C +:0400070000000000F5 +:0400080006C00034FA +:04000900DEF8001409 +:04000A0006800074F8 +:04000B00D690011476 +:04000C00008000343C +:04000D0010B00F140C +:04000E0000C00034FA +:04000F0018F31114BD +:0400100010C00326F3 +:0400110010000015C6 +:040012001080010455 +:0400130010FFFD36A7 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diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_top.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_top.sv new file mode 100644 index 000000000000..b0dbeca9c54c --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_top.sv @@ -0,0 +1,3382 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// Top-level wrapper of 20nm hardened EMIF component. +// +/////////////////////////////////////////////////////////////////////////////// +module ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_top #( + + // Interface properties + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_HPS_ENABLE_EARLY_RELEASE = 0, + parameter IS_HPS = 0, + parameter IS_VID = 0, + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 1, + parameter SILICON_REV = "", + parameter PHY_HAS_DCC = 0, + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter DQS_BUS_MODE_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + + // Core logic related properties + parameter REGISTER_AFI = 0, + + // OCT-related properties + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_AC_CALIBRATED_OCT = 1, + parameter PHY_CK_CALIBRATED_OCT = 1, + parameter PHY_DATA_CALIBRATED_OCT = 1, + parameter PHY_USERMODE_OCT = 1, + parameter PHY_PERIODIC_OCT_RECAL = 1, + + // Debug parameters + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 1, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 3, + parameter DIAG_ABSTRACT_PHY_RLAT = 8, + parameter ABPHY_WRITE_PROTOCOL = 1, + + // Calibration algorithm and parameter table + parameter SEQ_CODE_HEX_FILENAME = "", + + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 0, + parameter SEQ_SYNTH_PARAMS_HEX_FILENAME = "", + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + + parameter SEQ_SIM_OSC_FREQ_MHZ = 0, + parameter SEQ_SIM_PARAMS_HEX_FILENAME = "", + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + + // Family traits + parameter LANES_PER_TILE = 1, + parameter PINS_PER_LANE = 1, + parameter OCT_CONTROL_WIDTH = 1, + + // PLL parameters + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_SIM_CAL_SLAVE_CLK_FREQ_PS = 0, + parameter PLL_SIM_CAL_MASTER_CLK_FREQ_PS = 0, + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_OUT_EN_8 = "", + + // Parameters describing HMC configuration + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 1, + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + + // Parameters describing logical tile/lane/pin allocation in the RTL + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + + // Definition of port widhts for "clks_sharing_master_out" interface + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 1, + + // Definition of port widhts for "clks_sharing_slave_in" interface + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 1, + + // Definition of port widths for "mem" interface + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + // Definition of port widths for "afi" interface + //AUTOGEN_BEGIN: Definition of afi port widths + parameter PORT_AFI_RLAT_WIDTH = 1, + parameter PORT_AFI_WLAT_WIDTH = 1, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 1, + parameter PORT_AFI_ADDR_WIDTH = 1, + parameter PORT_AFI_BA_WIDTH = 1, + parameter PORT_AFI_BG_WIDTH = 1, + parameter PORT_AFI_C_WIDTH = 1, + parameter PORT_AFI_CKE_WIDTH = 1, + parameter PORT_AFI_CS_N_WIDTH = 1, + parameter PORT_AFI_RM_WIDTH = 1, + parameter PORT_AFI_ODT_WIDTH = 1, + parameter PORT_AFI_RAS_N_WIDTH = 1, + parameter PORT_AFI_CAS_N_WIDTH = 1, + parameter PORT_AFI_WE_N_WIDTH = 1, + parameter PORT_AFI_RST_N_WIDTH = 1, + parameter PORT_AFI_ACT_N_WIDTH = 1, + parameter PORT_AFI_PAR_WIDTH = 1, + parameter PORT_AFI_CA_WIDTH = 1, + parameter PORT_AFI_REF_N_WIDTH = 1, + parameter PORT_AFI_WPS_N_WIDTH = 1, + parameter PORT_AFI_RPS_N_WIDTH = 1, + parameter PORT_AFI_DOFF_N_WIDTH = 1, + parameter PORT_AFI_LD_N_WIDTH = 1, + parameter PORT_AFI_RW_N_WIDTH = 1, + parameter PORT_AFI_LBK0_N_WIDTH = 1, + parameter PORT_AFI_LBK1_N_WIDTH = 1, + parameter PORT_AFI_CFG_N_WIDTH = 1, + parameter PORT_AFI_AP_WIDTH = 1, + parameter PORT_AFI_AINV_WIDTH = 1, + parameter PORT_AFI_DM_WIDTH = 1, + parameter PORT_AFI_DM_N_WIDTH = 1, + parameter PORT_AFI_BWS_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DINV_WIDTH = 1, + parameter PORT_AFI_WDATA_DINV_WIDTH = 1, + parameter PORT_AFI_DQS_BURST_WIDTH = 1, + parameter PORT_AFI_WDATA_VALID_WIDTH = 1, + parameter PORT_AFI_WDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 1, + parameter PORT_AFI_RDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_VALID_WIDTH = 1, + parameter PORT_AFI_RRANK_WIDTH = 1, + parameter PORT_AFI_WRANK_WIDTH = 1, + parameter PORT_AFI_ALERT_N_WIDTH = 1, + parameter PORT_AFI_PE_N_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_cmd" interface + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_wr" interface + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_rd" interface + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_amm" interface + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + + // Definition of port widths for "ctrl_user_refresh" interface + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 1, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 1, + + // Definition of port widths for "ctrl_self_refresh" interface + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 1, + + // Definition of port widths for "ctrl_ecc" interface + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1, + + // Definition of port widths for "ctrl_mmr" interface + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1, + + // Definition of port widths for "hps_emif" interface + parameter PORT_HPS_EMIF_H2E_WIDTH = 1, + parameter PORT_HPS_EMIF_E2H_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 2, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 1, + + // Definition of port widths for "cal_debug" interface + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + + // Definition of port widths for "cal_debug_out" interface + parameter PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_WDATA_WIDTH = 1, + + // Definition of port widths for "cal_master" interface + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 1, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 1, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 1, + + // Definition of port widths for "dft_nf" interface + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 1, + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 1, + + // Definition of port widths for "vji" interface + parameter PORT_VJI_IR_IN_WIDTH = 1, + parameter PORT_VJI_IR_OUT_WIDTH = 1, + + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter LANES_USAGE_3 = 1'b0, + parameter LANES_USAGE_2 = 1'b0, + parameter LANES_USAGE_1 = 1'b0, + parameter LANES_USAGE_0 = 1'b0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_12 = 1'b0, + parameter PINS_USAGE_11 = 1'b0, + parameter PINS_USAGE_10 = 1'b0, + parameter PINS_USAGE_9 = 1'b0, + parameter PINS_USAGE_8 = 1'b0, + parameter PINS_USAGE_7 = 1'b0, + parameter PINS_USAGE_6 = 1'b0, + parameter PINS_USAGE_5 = 1'b0, + parameter PINS_USAGE_4 = 1'b0, + parameter PINS_USAGE_3 = 1'b0, + parameter PINS_USAGE_2 = 1'b0, + parameter PINS_USAGE_1 = 1'b0, + parameter PINS_USAGE_0 = 1'b0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_12 = 1'b0, + parameter PINS_RATE_11 = 1'b0, + parameter PINS_RATE_10 = 1'b0, + parameter PINS_RATE_9 = 1'b0, + parameter PINS_RATE_8 = 1'b0, + parameter PINS_RATE_7 = 1'b0, + parameter PINS_RATE_6 = 1'b0, + parameter PINS_RATE_5 = 1'b0, + parameter PINS_RATE_4 = 1'b0, + parameter PINS_RATE_3 = 1'b0, + parameter PINS_RATE_2 = 1'b0, + parameter PINS_RATE_1 = 1'b0, + parameter PINS_RATE_0 = 1'b0, + parameter PINS_WDB_AUTOGEN_WCNT = 0, + parameter PINS_WDB_38 = 1'b0, + parameter PINS_WDB_37 = 1'b0, + parameter PINS_WDB_36 = 1'b0, + parameter PINS_WDB_35 = 1'b0, + parameter PINS_WDB_34 = 1'b0, + parameter PINS_WDB_33 = 1'b0, + parameter PINS_WDB_32 = 1'b0, + parameter PINS_WDB_31 = 1'b0, + parameter PINS_WDB_30 = 1'b0, + parameter PINS_WDB_29 = 1'b0, + parameter PINS_WDB_28 = 1'b0, + parameter PINS_WDB_27 = 1'b0, + parameter PINS_WDB_26 = 1'b0, + parameter PINS_WDB_25 = 1'b0, + parameter PINS_WDB_24 = 1'b0, + parameter PINS_WDB_23 = 1'b0, + parameter PINS_WDB_22 = 1'b0, + parameter PINS_WDB_21 = 1'b0, + parameter PINS_WDB_20 = 1'b0, + parameter PINS_WDB_19 = 1'b0, + parameter PINS_WDB_18 = 1'b0, + parameter PINS_WDB_17 = 1'b0, + parameter PINS_WDB_16 = 1'b0, + parameter PINS_WDB_15 = 1'b0, + parameter PINS_WDB_14 = 1'b0, + parameter PINS_WDB_13 = 1'b0, + parameter PINS_WDB_12 = 1'b0, + parameter PINS_WDB_11 = 1'b0, + parameter PINS_WDB_10 = 1'b0, + parameter PINS_WDB_9 = 1'b0, + parameter PINS_WDB_8 = 1'b0, + parameter PINS_WDB_7 = 1'b0, + parameter PINS_WDB_6 = 1'b0, + parameter PINS_WDB_5 = 1'b0, + parameter PINS_WDB_4 = 1'b0, + parameter PINS_WDB_3 = 1'b0, + parameter PINS_WDB_2 = 1'b0, + parameter PINS_WDB_1 = 1'b0, + parameter PINS_WDB_0 = 1'b0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_38 = 1'b0, + parameter PINS_DATA_IN_MODE_37 = 1'b0, + parameter PINS_DATA_IN_MODE_36 = 1'b0, + parameter PINS_DATA_IN_MODE_35 = 1'b0, + parameter PINS_DATA_IN_MODE_34 = 1'b0, + parameter PINS_DATA_IN_MODE_33 = 1'b0, + parameter PINS_DATA_IN_MODE_32 = 1'b0, + parameter PINS_DATA_IN_MODE_31 = 1'b0, + parameter PINS_DATA_IN_MODE_30 = 1'b0, + parameter PINS_DATA_IN_MODE_29 = 1'b0, + parameter PINS_DATA_IN_MODE_28 = 1'b0, + parameter PINS_DATA_IN_MODE_27 = 1'b0, + parameter PINS_DATA_IN_MODE_26 = 1'b0, + parameter PINS_DATA_IN_MODE_25 = 1'b0, + parameter PINS_DATA_IN_MODE_24 = 1'b0, + parameter PINS_DATA_IN_MODE_23 = 1'b0, + parameter PINS_DATA_IN_MODE_22 = 1'b0, + parameter PINS_DATA_IN_MODE_21 = 1'b0, + parameter PINS_DATA_IN_MODE_20 = 1'b0, + parameter PINS_DATA_IN_MODE_19 = 1'b0, + parameter PINS_DATA_IN_MODE_18 = 1'b0, + parameter PINS_DATA_IN_MODE_17 = 1'b0, + parameter PINS_DATA_IN_MODE_16 = 1'b0, + parameter PINS_DATA_IN_MODE_15 = 1'b0, + parameter PINS_DATA_IN_MODE_14 = 1'b0, + parameter PINS_DATA_IN_MODE_13 = 1'b0, + parameter PINS_DATA_IN_MODE_12 = 1'b0, + parameter PINS_DATA_IN_MODE_11 = 1'b0, + parameter PINS_DATA_IN_MODE_10 = 1'b0, + parameter PINS_DATA_IN_MODE_9 = 1'b0, + parameter PINS_DATA_IN_MODE_8 = 1'b0, + parameter PINS_DATA_IN_MODE_7 = 1'b0, + parameter PINS_DATA_IN_MODE_6 = 1'b0, + parameter PINS_DATA_IN_MODE_5 = 1'b0, + parameter PINS_DATA_IN_MODE_4 = 1'b0, + parameter PINS_DATA_IN_MODE_3 = 1'b0, + parameter PINS_DATA_IN_MODE_2 = 1'b0, + parameter PINS_DATA_IN_MODE_1 = 1'b0, + parameter PINS_DATA_IN_MODE_0 = 1'b0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_12 = 1'b0, + parameter PINS_C2L_DRIVEN_11 = 1'b0, + parameter PINS_C2L_DRIVEN_10 = 1'b0, + parameter PINS_C2L_DRIVEN_9 = 1'b0, + parameter PINS_C2L_DRIVEN_8 = 1'b0, + parameter PINS_C2L_DRIVEN_7 = 1'b0, + parameter PINS_C2L_DRIVEN_6 = 1'b0, + parameter PINS_C2L_DRIVEN_5 = 1'b0, + parameter PINS_C2L_DRIVEN_4 = 1'b0, + parameter PINS_C2L_DRIVEN_3 = 1'b0, + parameter PINS_C2L_DRIVEN_2 = 1'b0, + parameter PINS_C2L_DRIVEN_1 = 1'b0, + parameter PINS_C2L_DRIVEN_0 = 1'b0, + parameter PINS_DB_IN_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_IN_BYPASS_12 = 1'b0, + parameter PINS_DB_IN_BYPASS_11 = 1'b0, + parameter PINS_DB_IN_BYPASS_10 = 1'b0, + parameter PINS_DB_IN_BYPASS_9 = 1'b0, + parameter PINS_DB_IN_BYPASS_8 = 1'b0, + parameter PINS_DB_IN_BYPASS_7 = 1'b0, + parameter PINS_DB_IN_BYPASS_6 = 1'b0, + parameter PINS_DB_IN_BYPASS_5 = 1'b0, + parameter PINS_DB_IN_BYPASS_4 = 1'b0, + parameter PINS_DB_IN_BYPASS_3 = 1'b0, + parameter PINS_DB_IN_BYPASS_2 = 1'b0, + parameter PINS_DB_IN_BYPASS_1 = 1'b0, + parameter PINS_DB_IN_BYPASS_0 = 1'b0, + parameter PINS_DB_OUT_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OUT_BYPASS_12 = 1'b0, + parameter PINS_DB_OUT_BYPASS_11 = 1'b0, + parameter PINS_DB_OUT_BYPASS_10 = 1'b0, + parameter PINS_DB_OUT_BYPASS_9 = 1'b0, + parameter PINS_DB_OUT_BYPASS_8 = 1'b0, + parameter PINS_DB_OUT_BYPASS_7 = 1'b0, + parameter PINS_DB_OUT_BYPASS_6 = 1'b0, + parameter PINS_DB_OUT_BYPASS_5 = 1'b0, + parameter PINS_DB_OUT_BYPASS_4 = 1'b0, + parameter PINS_DB_OUT_BYPASS_3 = 1'b0, + parameter PINS_DB_OUT_BYPASS_2 = 1'b0, + parameter PINS_DB_OUT_BYPASS_1 = 1'b0, + parameter PINS_DB_OUT_BYPASS_0 = 1'b0, + parameter PINS_DB_OE_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OE_BYPASS_12 = 1'b0, + parameter PINS_DB_OE_BYPASS_11 = 1'b0, + parameter PINS_DB_OE_BYPASS_10 = 1'b0, + parameter PINS_DB_OE_BYPASS_9 = 1'b0, + parameter PINS_DB_OE_BYPASS_8 = 1'b0, + parameter PINS_DB_OE_BYPASS_7 = 1'b0, + parameter PINS_DB_OE_BYPASS_6 = 1'b0, + parameter PINS_DB_OE_BYPASS_5 = 1'b0, + parameter PINS_DB_OE_BYPASS_4 = 1'b0, + parameter PINS_DB_OE_BYPASS_3 = 1'b0, + parameter PINS_DB_OE_BYPASS_2 = 1'b0, + parameter PINS_DB_OE_BYPASS_1 = 1'b0, + parameter PINS_DB_OE_BYPASS_0 = 1'b0, + parameter PINS_INVERT_WR_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_WR_12 = 1'b0, + parameter PINS_INVERT_WR_11 = 1'b0, + parameter PINS_INVERT_WR_10 = 1'b0, + parameter PINS_INVERT_WR_9 = 1'b0, + parameter PINS_INVERT_WR_8 = 1'b0, + parameter PINS_INVERT_WR_7 = 1'b0, + parameter PINS_INVERT_WR_6 = 1'b0, + parameter PINS_INVERT_WR_5 = 1'b0, + parameter PINS_INVERT_WR_4 = 1'b0, + parameter PINS_INVERT_WR_3 = 1'b0, + parameter PINS_INVERT_WR_2 = 1'b0, + parameter PINS_INVERT_WR_1 = 1'b0, + parameter PINS_INVERT_WR_0 = 1'b0, + parameter PINS_INVERT_OE_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_OE_12 = 1'b0, + parameter PINS_INVERT_OE_11 = 1'b0, + parameter PINS_INVERT_OE_10 = 1'b0, + parameter PINS_INVERT_OE_9 = 1'b0, + parameter PINS_INVERT_OE_8 = 1'b0, + parameter PINS_INVERT_OE_7 = 1'b0, + parameter PINS_INVERT_OE_6 = 1'b0, + parameter PINS_INVERT_OE_5 = 1'b0, + parameter PINS_INVERT_OE_4 = 1'b0, + parameter PINS_INVERT_OE_3 = 1'b0, + parameter PINS_INVERT_OE_2 = 1'b0, + parameter PINS_INVERT_OE_1 = 1'b0, + parameter PINS_INVERT_OE_0 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT= 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_12 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_11 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_10 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_9 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_8 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_7 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_6 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_5 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_4 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_3 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_2 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_1 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_0 = 1'b0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_12 = 1'b0, + parameter PINS_OCT_MODE_11 = 1'b0, + parameter PINS_OCT_MODE_10 = 1'b0, + parameter PINS_OCT_MODE_9 = 1'b0, + parameter PINS_OCT_MODE_8 = 1'b0, + parameter PINS_OCT_MODE_7 = 1'b0, + parameter PINS_OCT_MODE_6 = 1'b0, + parameter PINS_OCT_MODE_5 = 1'b0, + parameter PINS_OCT_MODE_4 = 1'b0, + parameter PINS_OCT_MODE_3 = 1'b0, + parameter PINS_OCT_MODE_2 = 1'b0, + parameter PINS_OCT_MODE_1 = 1'b0, + parameter PINS_OCT_MODE_0 = 1'b0, + parameter PINS_GPIO_MODE_AUTOGEN_WCNT = 0, + parameter PINS_GPIO_MODE_12 = 1'b0, + parameter PINS_GPIO_MODE_11 = 1'b0, + parameter PINS_GPIO_MODE_10 = 1'b0, + parameter PINS_GPIO_MODE_9 = 1'b0, + parameter PINS_GPIO_MODE_8 = 1'b0, + parameter PINS_GPIO_MODE_7 = 1'b0, + parameter PINS_GPIO_MODE_6 = 1'b0, + parameter PINS_GPIO_MODE_5 = 1'b0, + parameter PINS_GPIO_MODE_4 = 1'b0, + parameter PINS_GPIO_MODE_3 = 1'b0, + parameter PINS_GPIO_MODE_2 = 1'b0, + parameter PINS_GPIO_MODE_1 = 1'b0, + parameter PINS_GPIO_MODE_0 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 1'b0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_2 = 1'b0, + parameter CENTER_TIDS_1 = 1'b0, + parameter CENTER_TIDS_0 = 1'b0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_2 = 1'b0, + parameter HMC_TIDS_1 = 1'b0, + parameter HMC_TIDS_0 = 1'b0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_9 = 1'b0, + parameter LANE_TIDS_8 = 1'b0, + parameter LANE_TIDS_7 = 1'b0, + parameter LANE_TIDS_6 = 1'b0, + parameter LANE_TIDS_5 = 1'b0, + parameter LANE_TIDS_4 = 1'b0, + parameter LANE_TIDS_3 = 1'b0, + parameter LANE_TIDS_2 = 1'b0, + parameter LANE_TIDS_1 = 1'b0, + parameter LANE_TIDS_0 = 1'b0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_PINLOC_0 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_PINLOC_16 = 1'b0, + parameter PORT_MEM_A_PINLOC_15 = 1'b0, + parameter PORT_MEM_A_PINLOC_14 = 1'b0, + parameter PORT_MEM_A_PINLOC_13 = 1'b0, + parameter PORT_MEM_A_PINLOC_12 = 1'b0, + parameter PORT_MEM_A_PINLOC_11 = 1'b0, + parameter PORT_MEM_A_PINLOC_10 = 1'b0, + parameter PORT_MEM_A_PINLOC_9 = 1'b0, + parameter PORT_MEM_A_PINLOC_8 = 1'b0, + parameter PORT_MEM_A_PINLOC_7 = 1'b0, + parameter PORT_MEM_A_PINLOC_6 = 1'b0, + parameter PORT_MEM_A_PINLOC_5 = 1'b0, + parameter PORT_MEM_A_PINLOC_4 = 1'b0, + parameter PORT_MEM_A_PINLOC_3 = 1'b0, + parameter PORT_MEM_A_PINLOC_2 = 1'b0, + parameter PORT_MEM_A_PINLOC_1 = 1'b0, + parameter PORT_MEM_A_PINLOC_0 = 1'b0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_PINLOC_5 = 1'b0, + parameter PORT_MEM_BA_PINLOC_4 = 1'b0, + parameter PORT_MEM_BA_PINLOC_3 = 1'b0, + parameter PORT_MEM_BA_PINLOC_2 = 1'b0, + parameter PORT_MEM_BA_PINLOC_1 = 1'b0, + parameter PORT_MEM_BA_PINLOC_0 = 1'b0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_PINLOC_5 = 1'b0, + parameter PORT_MEM_BG_PINLOC_4 = 1'b0, + parameter PORT_MEM_BG_PINLOC_3 = 1'b0, + parameter PORT_MEM_BG_PINLOC_2 = 1'b0, + parameter PORT_MEM_BG_PINLOC_1 = 1'b0, + parameter PORT_MEM_BG_PINLOC_0 = 1'b0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_PINLOC_5 = 1'b0, + parameter PORT_MEM_C_PINLOC_4 = 1'b0, + parameter PORT_MEM_C_PINLOC_3 = 1'b0, + parameter PORT_MEM_C_PINLOC_2 = 1'b0, + parameter PORT_MEM_C_PINLOC_1 = 1'b0, + parameter PORT_MEM_C_PINLOC_0 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_4 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_3 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_2 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_1 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_0 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_PINLOC_5 = 1'b0, + parameter PORT_MEM_RM_PINLOC_4 = 1'b0, + parameter PORT_MEM_RM_PINLOC_3 = 1'b0, + parameter PORT_MEM_RM_PINLOC_2 = 1'b0, + parameter PORT_MEM_RM_PINLOC_1 = 1'b0, + parameter PORT_MEM_RM_PINLOC_0 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_4 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_3 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_2 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_1 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_0 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_0 = 1'b0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_PINLOC_16 = 1'b0, + parameter PORT_MEM_CA_PINLOC_15 = 1'b0, + parameter PORT_MEM_CA_PINLOC_14 = 1'b0, + parameter PORT_MEM_CA_PINLOC_13 = 1'b0, + parameter PORT_MEM_CA_PINLOC_12 = 1'b0, + parameter PORT_MEM_CA_PINLOC_11 = 1'b0, + parameter PORT_MEM_CA_PINLOC_10 = 1'b0, + parameter PORT_MEM_CA_PINLOC_9 = 1'b0, + parameter PORT_MEM_CA_PINLOC_8 = 1'b0, + parameter PORT_MEM_CA_PINLOC_7 = 1'b0, + parameter PORT_MEM_CA_PINLOC_6 = 1'b0, + parameter PORT_MEM_CA_PINLOC_5 = 1'b0, + parameter PORT_MEM_CA_PINLOC_4 = 1'b0, + parameter PORT_MEM_CA_PINLOC_3 = 1'b0, + parameter PORT_MEM_CA_PINLOC_2 = 1'b0, + parameter PORT_MEM_CA_PINLOC_1 = 1'b0, + parameter PORT_MEM_CA_PINLOC_0 = 1'b0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_PINLOC_0 = 1'b0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 1'b0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_PINLOC_12 = 1'b0, + parameter PORT_MEM_DM_PINLOC_11 = 1'b0, + parameter PORT_MEM_DM_PINLOC_10 = 1'b0, + parameter PORT_MEM_DM_PINLOC_9 = 1'b0, + parameter PORT_MEM_DM_PINLOC_8 = 1'b0, + parameter PORT_MEM_DM_PINLOC_7 = 1'b0, + parameter PORT_MEM_DM_PINLOC_6 = 1'b0, + parameter PORT_MEM_DM_PINLOC_5 = 1'b0, + parameter PORT_MEM_DM_PINLOC_4 = 1'b0, + parameter PORT_MEM_DM_PINLOC_3 = 1'b0, + parameter PORT_MEM_DM_PINLOC_2 = 1'b0, + parameter PORT_MEM_DM_PINLOC_1 = 1'b0, + parameter PORT_MEM_DM_PINLOC_0 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_PINLOC_48 = 1'b0, + parameter PORT_MEM_D_PINLOC_47 = 1'b0, + parameter PORT_MEM_D_PINLOC_46 = 1'b0, + parameter PORT_MEM_D_PINLOC_45 = 1'b0, + parameter PORT_MEM_D_PINLOC_44 = 1'b0, + parameter PORT_MEM_D_PINLOC_43 = 1'b0, + parameter PORT_MEM_D_PINLOC_42 = 1'b0, + parameter PORT_MEM_D_PINLOC_41 = 1'b0, + parameter PORT_MEM_D_PINLOC_40 = 1'b0, + parameter PORT_MEM_D_PINLOC_39 = 1'b0, + parameter PORT_MEM_D_PINLOC_38 = 1'b0, + parameter PORT_MEM_D_PINLOC_37 = 1'b0, + parameter PORT_MEM_D_PINLOC_36 = 1'b0, + parameter PORT_MEM_D_PINLOC_35 = 1'b0, + parameter PORT_MEM_D_PINLOC_34 = 1'b0, + parameter PORT_MEM_D_PINLOC_33 = 1'b0, + parameter PORT_MEM_D_PINLOC_32 = 1'b0, + parameter PORT_MEM_D_PINLOC_31 = 1'b0, + parameter PORT_MEM_D_PINLOC_30 = 1'b0, + parameter PORT_MEM_D_PINLOC_29 = 1'b0, + parameter PORT_MEM_D_PINLOC_28 = 1'b0, + parameter PORT_MEM_D_PINLOC_27 = 1'b0, + parameter PORT_MEM_D_PINLOC_26 = 1'b0, + parameter PORT_MEM_D_PINLOC_25 = 1'b0, + parameter PORT_MEM_D_PINLOC_24 = 1'b0, + parameter PORT_MEM_D_PINLOC_23 = 1'b0, + parameter PORT_MEM_D_PINLOC_22 = 1'b0, + parameter PORT_MEM_D_PINLOC_21 = 1'b0, + parameter PORT_MEM_D_PINLOC_20 = 1'b0, + parameter PORT_MEM_D_PINLOC_19 = 1'b0, + parameter PORT_MEM_D_PINLOC_18 = 1'b0, + parameter PORT_MEM_D_PINLOC_17 = 1'b0, + parameter PORT_MEM_D_PINLOC_16 = 1'b0, + parameter PORT_MEM_D_PINLOC_15 = 1'b0, + parameter PORT_MEM_D_PINLOC_14 = 1'b0, + parameter PORT_MEM_D_PINLOC_13 = 1'b0, + parameter PORT_MEM_D_PINLOC_12 = 1'b0, + parameter PORT_MEM_D_PINLOC_11 = 1'b0, + parameter PORT_MEM_D_PINLOC_10 = 1'b0, + parameter PORT_MEM_D_PINLOC_9 = 1'b0, + parameter PORT_MEM_D_PINLOC_8 = 1'b0, + parameter PORT_MEM_D_PINLOC_7 = 1'b0, + parameter PORT_MEM_D_PINLOC_6 = 1'b0, + parameter PORT_MEM_D_PINLOC_5 = 1'b0, + parameter PORT_MEM_D_PINLOC_4 = 1'b0, + parameter PORT_MEM_D_PINLOC_3 = 1'b0, + parameter PORT_MEM_D_PINLOC_2 = 1'b0, + parameter PORT_MEM_D_PINLOC_1 = 1'b0, + parameter PORT_MEM_D_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_0 = 1'b0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_PINLOC_48 = 1'b0, + parameter PORT_MEM_Q_PINLOC_47 = 1'b0, + parameter PORT_MEM_Q_PINLOC_46 = 1'b0, + parameter PORT_MEM_Q_PINLOC_45 = 1'b0, + parameter PORT_MEM_Q_PINLOC_44 = 1'b0, + parameter PORT_MEM_Q_PINLOC_43 = 1'b0, + parameter PORT_MEM_Q_PINLOC_42 = 1'b0, + parameter PORT_MEM_Q_PINLOC_41 = 1'b0, + parameter PORT_MEM_Q_PINLOC_40 = 1'b0, + parameter PORT_MEM_Q_PINLOC_39 = 1'b0, + parameter PORT_MEM_Q_PINLOC_38 = 1'b0, + parameter PORT_MEM_Q_PINLOC_37 = 1'b0, + parameter PORT_MEM_Q_PINLOC_36 = 1'b0, + parameter PORT_MEM_Q_PINLOC_35 = 1'b0, + parameter PORT_MEM_Q_PINLOC_34 = 1'b0, + parameter PORT_MEM_Q_PINLOC_33 = 1'b0, + parameter PORT_MEM_Q_PINLOC_32 = 1'b0, + parameter PORT_MEM_Q_PINLOC_31 = 1'b0, + parameter PORT_MEM_Q_PINLOC_30 = 1'b0, + parameter PORT_MEM_Q_PINLOC_29 = 1'b0, + parameter PORT_MEM_Q_PINLOC_28 = 1'b0, + parameter PORT_MEM_Q_PINLOC_27 = 1'b0, + parameter PORT_MEM_Q_PINLOC_26 = 1'b0, + parameter PORT_MEM_Q_PINLOC_25 = 1'b0, + parameter PORT_MEM_Q_PINLOC_24 = 1'b0, + parameter PORT_MEM_Q_PINLOC_23 = 1'b0, + parameter PORT_MEM_Q_PINLOC_22 = 1'b0, + parameter PORT_MEM_Q_PINLOC_21 = 1'b0, + parameter PORT_MEM_Q_PINLOC_20 = 1'b0, + parameter PORT_MEM_Q_PINLOC_19 = 1'b0, + parameter PORT_MEM_Q_PINLOC_18 = 1'b0, + parameter PORT_MEM_Q_PINLOC_17 = 1'b0, + parameter PORT_MEM_Q_PINLOC_16 = 1'b0, + parameter PORT_MEM_Q_PINLOC_15 = 1'b0, + parameter PORT_MEM_Q_PINLOC_14 = 1'b0, + parameter PORT_MEM_Q_PINLOC_13 = 1'b0, + parameter PORT_MEM_Q_PINLOC_12 = 1'b0, + parameter PORT_MEM_Q_PINLOC_11 = 1'b0, + parameter PORT_MEM_Q_PINLOC_10 = 1'b0, + parameter PORT_MEM_Q_PINLOC_9 = 1'b0, + parameter PORT_MEM_Q_PINLOC_8 = 1'b0, + parameter PORT_MEM_Q_PINLOC_7 = 1'b0, + parameter PORT_MEM_Q_PINLOC_6 = 1'b0, + parameter PORT_MEM_Q_PINLOC_5 = 1'b0, + parameter PORT_MEM_Q_PINLOC_4 = 1'b0, + parameter PORT_MEM_Q_PINLOC_3 = 1'b0, + parameter PORT_MEM_Q_PINLOC_2 = 1'b0, + parameter PORT_MEM_Q_PINLOC_1 = 1'b0, + parameter PORT_MEM_Q_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_0 = 1'b0 +) ( + // Reset + input logic global_reset_n, + + // PLL signals + input logic pll_ref_clk, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + + // OCT signals + input logic oct_rzqin, + + // Status signals + output logic local_cal_success, + output logic local_cal_fail, + + // VID cal done signal + input logic vid_cal_done_persist, + + // User reset signal going to core (for PHY + hard controller interfaces) + output logic emif_usr_reset_n, + output logic emif_usr_reset_n_sec, + + // User clock going to core (for PHY + hard controller interfaces) + output logic emif_usr_clk, + output logic emif_usr_clk_sec, + + // A clock that runs at half the frequency of emif_usr_clk going to core + output logic emif_usr_half_clk, + output logic emif_usr_half_clk_sec, + + // AFI reset going to core + output logic afi_reset_n, + + // AFI clock going to core + output logic afi_clk, + + // A clock that runs at half the frequency of afi_clk going to core + output logic afi_half_clk, + + // Signals required to share core clocking resources between across + // compatible interfaces. An interface can be configured as a "master" + // which exports the core clocks, or a "slave" which imports the + // core clocks from a master interface. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // Ports for "mem" interface + //AUTOGEN_BEGIN: Definition of memory ports + output logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + output logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + output logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + output logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + output logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + output logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + output logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + output logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + output logic [PORT_MEM_K_WIDTH-1:0] mem_k, + output logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + output logic [PORT_MEM_A_WIDTH-1:0] mem_a, + output logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + output logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + output logic [PORT_MEM_C_WIDTH-1:0] mem_c, + output logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + output logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + output logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + output logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + output logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + output logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + output logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + output logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + output logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + output logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + output logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + output logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + output logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + output logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + output logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + output logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + output logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + output logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + output logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + output logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + output logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + output logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + output logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + output logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + output logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + output logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + input logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + input logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + input logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + input logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + input logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + input logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + input logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + input logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + input logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n, + input logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + + // Ports for "afi" interface + //AUTOGEN_BEGIN: Definition of afi ports + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [PORT_AFI_RLAT_WIDTH-1:0] afi_rlat, + output logic [PORT_AFI_WLAT_WIDTH-1:0] afi_wlat, + output logic [PORT_AFI_SEQ_BUSY_WIDTH-1:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [PORT_AFI_ADDR_WIDTH-1:0] afi_addr, + input logic [PORT_AFI_BA_WIDTH-1:0] afi_ba, + input logic [PORT_AFI_BG_WIDTH-1:0] afi_bg, + input logic [PORT_AFI_C_WIDTH-1:0] afi_c, + input logic [PORT_AFI_CKE_WIDTH-1:0] afi_cke, + input logic [PORT_AFI_CS_N_WIDTH-1:0] afi_cs_n, + input logic [PORT_AFI_RM_WIDTH-1:0] afi_rm, + input logic [PORT_AFI_ODT_WIDTH-1:0] afi_odt, + input logic [PORT_AFI_RAS_N_WIDTH-1:0] afi_ras_n, + input logic [PORT_AFI_CAS_N_WIDTH-1:0] afi_cas_n, + input logic [PORT_AFI_WE_N_WIDTH-1:0] afi_we_n, + input logic [PORT_AFI_RST_N_WIDTH-1:0] afi_rst_n, + input logic [PORT_AFI_ACT_N_WIDTH-1:0] afi_act_n, + input logic [PORT_AFI_PAR_WIDTH-1:0] afi_par, + input logic [PORT_AFI_CA_WIDTH-1:0] afi_ca, + input logic [PORT_AFI_REF_N_WIDTH-1:0] afi_ref_n, + input logic [PORT_AFI_WPS_N_WIDTH-1:0] afi_wps_n, + input logic [PORT_AFI_RPS_N_WIDTH-1:0] afi_rps_n, + input logic [PORT_AFI_DOFF_N_WIDTH-1:0] afi_doff_n, + input logic [PORT_AFI_LD_N_WIDTH-1:0] afi_ld_n, + input logic [PORT_AFI_RW_N_WIDTH-1:0] afi_rw_n, + input logic [PORT_AFI_LBK0_N_WIDTH-1:0] afi_lbk0_n, + input logic [PORT_AFI_LBK1_N_WIDTH-1:0] afi_lbk1_n, + input logic [PORT_AFI_CFG_N_WIDTH-1:0] afi_cfg_n, + input logic [PORT_AFI_AP_WIDTH-1:0] afi_ap, + input logic [PORT_AFI_AINV_WIDTH-1:0] afi_ainv, + input logic [PORT_AFI_DM_WIDTH-1:0] afi_dm, + input logic [PORT_AFI_DM_N_WIDTH-1:0] afi_dm_n, + input logic [PORT_AFI_BWS_N_WIDTH-1:0] afi_bws_n, + output logic [PORT_AFI_RDATA_DBI_N_WIDTH-1:0] afi_rdata_dbi_n, + input logic [PORT_AFI_WDATA_DBI_N_WIDTH-1:0] afi_wdata_dbi_n, + output logic [PORT_AFI_RDATA_DINV_WIDTH-1:0] afi_rdata_dinv, + input logic [PORT_AFI_WDATA_DINV_WIDTH-1:0] afi_wdata_dinv, + input logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst, + input logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid, + input logic [PORT_AFI_WDATA_WIDTH-1:0] afi_wdata, + input logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full, + output logic [PORT_AFI_RDATA_WIDTH-1:0] afi_rdata, + output logic [PORT_AFI_RDATA_VALID_WIDTH-1:0] afi_rdata_valid, + input logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank, + input logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank, + output logic [PORT_AFI_ALERT_N_WIDTH-1:0] afi_alert_n, + output logic [PORT_AFI_PE_N_WIDTH-1:0] afi_pe_n, + + // Ports for "ctrl_ast_cmd" interfaces + output logic ast_cmd_ready_0, + input logic ast_cmd_valid_0, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_0, + + output logic ast_cmd_ready_1, + input logic ast_cmd_valid_1, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_1, + + // Ports for "ctrl_ast_wr" interfaces + output logic ast_wr_ready_0, + input logic ast_wr_valid_0, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_0, + + output logic ast_wr_ready_1, + input logic ast_wr_valid_1, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_1, + + // Ports for "ctrl_ast_rd" interfaces + input logic ast_rd_ready_0, + output logic ast_rd_valid_0, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_0, + + input logic ast_rd_ready_1, + output logic ast_rd_valid_1, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_1, + + // Ports for "ctrl_amm" interfaces + input logic amm_write_0, + input logic amm_read_0, + output logic amm_ready_0, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_0, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_0, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + + input logic amm_write_1, + input logic amm_read_1, + output logic amm_ready_1, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_1, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_1, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + + // Ports for "ctrl_user_priority" interface + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + + // Ports for "ctrl_auto_precharge" interface + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + + // Ports for "ctrl_user_refresh" interface + input logic [PORT_CTRL_USER_REFRESH_REQ_WIDTH-1:0] ctrl_user_refresh_req, + input logic [PORT_CTRL_USER_REFRESH_BANK_WIDTH-1:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + + // Ports for "ctrl_self_refresh" interface + input logic [PORT_CTRL_SELF_REFRESH_REQ_WIDTH-1:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + + // Ports for "ctrl_will_refresh" interface + output logic ctrl_will_refresh, + + // Ports for "ctrl_deep_power_down" interface + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + + // Ports for "ctrl_power_down" interface + output logic ctrl_power_down_ack, + + // Ports for "ctrl_zq_cal" interface + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_0, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_0, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_0, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_0, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_1, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_1, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_1, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_1, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_0, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_0, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_0, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_1, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_1, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_1, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + + // Ports for the HPS<->EMIF conduit + input logic [PORT_HPS_EMIF_H2E_WIDTH-1:0] hps_to_emif, + output logic [PORT_HPS_EMIF_E2H_WIDTH-1:0] emif_to_hps, + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + output logic [PORT_HPS_EMIF_E2H_GP_WIDTH-1:0] emif_to_hps_gp, + + // Output/input clock/reset intended for core slave logic that interacts with the sequencer CPU + output logic cal_slave_clk, + output logic cal_slave_reset_n, + input logic cal_slave_clk_in, + input logic cal_slave_reset_n_in, + + // Output clock/reset intended for core master logic that interacts with the sequencer CPU + output logic cal_master_clk, + output logic cal_master_reset_n, + + // Input clock/reset intended for core logic connected to the Avalon slave port of the sequencer CPU. + // The "out" clock/reset is intended for daisy-chaining logic from multiple interfaces. + input logic cal_debug_clk, + input logic cal_debug_reset_n, + output logic cal_debug_out_clk, + output logic cal_debug_out_reset_n, + + // Ports for "cal_debug" interface + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + // Ports for "cal_debug_out" interface + output logic [PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH-1:0] cal_debug_out_addr, + output logic [PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH-1:0] cal_debug_out_byteenable, + output logic cal_debug_out_read, + output logic cal_debug_out_write, + output logic [PORT_CAL_DEBUG_OUT_WDATA_WIDTH-1:0] cal_debug_out_write_data, + input logic [PORT_CAL_DEBUG_OUT_RDATA_WIDTH-1:0] cal_debug_out_read_data, + input logic cal_debug_out_read_data_valid, + input logic cal_debug_out_waitrequest, + + // Ports for "cal_master" interface + output logic [PORT_CAL_MASTER_ADDRESS_WIDTH-1:0] cal_master_addr, + output logic [PORT_CAL_MASTER_BYTEEN_WIDTH-1:0] cal_master_byteenable, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + output logic cal_master_read, + output logic cal_master_write, + output logic [PORT_CAL_MASTER_WDATA_WIDTH-1:0] cal_master_write_data, + input logic [PORT_CAL_MASTER_RDATA_WIDTH-1:0] cal_master_read_data, + input logic cal_master_read_data_valid, + input logic cal_master_waitrequest, + + // Ports for internal test and debug + input logic [PORT_DFT_NF_IOAUX_PIO_IN_WIDTH-1:0] ioaux_pio_in, + output logic [PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH-1:0] ioaux_pio_out, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_NF_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done, + output logic [PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // Below is used to override the user selection for ABSTRACT PHY for synthesis + // synthesis read_comments_as_HDL on + // `define DISABLE_ABSTRACT_PHY_FOR_SYNTH TRUE + // synthesis read_comments_as_HDL off + + `ifdef DISABLE_ABSTRACT_PHY_FOR_SYNTH + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = 0; + `else + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = DIAG_USE_ABSTRACT_PHY; + `endif + + // Assertions + initial begin + assert(LANES_USAGE_AUTOGEN_WCNT == 4) else $fatal("LANES_USAGE_AUTOGEN_WCNT != 4 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_USAGE_AUTOGEN_WCNT == 13) else $fatal("PINS_USAGE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_RATE_AUTOGEN_WCNT == 13) else $fatal("PINS_RATE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_WDB_AUTOGEN_WCNT == 39) else $fatal("PINS_WDB_AUTOGEN_WCNT != 39 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DATA_IN_MODE_AUTOGEN_WCNT == 39) else $fatal("PINS_DATA_IN_MODE_AUTOGEN_WCNT != 39 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_C2L_DRIVEN_AUTOGEN_WCNT == 13) else $fatal("PINS_C2L_DRIVEN_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_IN_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_IN_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_OUT_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_OUT_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_OE_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_OE_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_INVERT_WR_AUTOGEN_WCNT == 13) else $fatal("PINS_INVERT_WR_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_INVERT_OE_AUTOGEN_WCNT == 13) else $fatal("PINS_INVERT_OE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT == 13) else $fatal("PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_OCT_MODE_AUTOGEN_WCNT == 13) else $fatal("PINS_OCT_MODE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_GPIO_MODE_AUTOGEN_WCNT == 13) else $fatal("PINS_GPIO_MODE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT == 129) else $fatal("UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT != 129 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT == 11) else $fatal("UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT != 11 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(CENTER_TIDS_AUTOGEN_WCNT == 3) else $fatal("CENTER_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(HMC_TIDS_AUTOGEN_WCNT == 3) else $fatal("HMC_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(LANE_TIDS_AUTOGEN_WCNT == 10) else $fatal("LANE_TIDS_AUTOGEN_WCNT != 10 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_K_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_A_PINLOC_AUTOGEN_WCNT == 17) else $fatal("PORT_MEM_A_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_BA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BG_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_BG_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_C_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_C_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RM_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_RM_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CA_PINLOC_AUTOGEN_WCNT == 17) else $fatal("PORT_MEM_CA_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AP_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_AP_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DM_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DM_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_D_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_D_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT == 7) else $fatal("PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT != 7 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_Q_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_Q_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + end + + // Derive localparam values + //AUTOGEN_BEGIN: Derive bit-vector parameters + localparam LANES_USAGE = {LANES_USAGE_3[29:0],LANES_USAGE_2[29:0],LANES_USAGE_1[29:0],LANES_USAGE_0[29:0]}; + localparam PINS_USAGE = {PINS_USAGE_12[29:0],PINS_USAGE_11[29:0],PINS_USAGE_10[29:0],PINS_USAGE_9[29:0],PINS_USAGE_8[29:0],PINS_USAGE_7[29:0],PINS_USAGE_6[29:0],PINS_USAGE_5[29:0],PINS_USAGE_4[29:0],PINS_USAGE_3[29:0],PINS_USAGE_2[29:0],PINS_USAGE_1[29:0],PINS_USAGE_0[29:0]}; + localparam PINS_RATE = {PINS_RATE_12[29:0],PINS_RATE_11[29:0],PINS_RATE_10[29:0],PINS_RATE_9[29:0],PINS_RATE_8[29:0],PINS_RATE_7[29:0],PINS_RATE_6[29:0],PINS_RATE_5[29:0],PINS_RATE_4[29:0],PINS_RATE_3[29:0],PINS_RATE_2[29:0],PINS_RATE_1[29:0],PINS_RATE_0[29:0]}; + localparam PINS_WDB = {PINS_WDB_38[29:0],PINS_WDB_37[29:0],PINS_WDB_36[29:0],PINS_WDB_35[29:0],PINS_WDB_34[29:0],PINS_WDB_33[29:0],PINS_WDB_32[29:0],PINS_WDB_31[29:0],PINS_WDB_30[29:0],PINS_WDB_29[29:0],PINS_WDB_28[29:0],PINS_WDB_27[29:0],PINS_WDB_26[29:0],PINS_WDB_25[29:0],PINS_WDB_24[29:0],PINS_WDB_23[29:0],PINS_WDB_22[29:0],PINS_WDB_21[29:0],PINS_WDB_20[29:0],PINS_WDB_19[29:0],PINS_WDB_18[29:0],PINS_WDB_17[29:0],PINS_WDB_16[29:0],PINS_WDB_15[29:0],PINS_WDB_14[29:0],PINS_WDB_13[29:0],PINS_WDB_12[29:0],PINS_WDB_11[29:0],PINS_WDB_10[29:0],PINS_WDB_9[29:0],PINS_WDB_8[29:0],PINS_WDB_7[29:0],PINS_WDB_6[29:0],PINS_WDB_5[29:0],PINS_WDB_4[29:0],PINS_WDB_3[29:0],PINS_WDB_2[29:0],PINS_WDB_1[29:0],PINS_WDB_0[29:0]}; + localparam PINS_DATA_IN_MODE = {PINS_DATA_IN_MODE_38[29:0],PINS_DATA_IN_MODE_37[29:0],PINS_DATA_IN_MODE_36[29:0],PINS_DATA_IN_MODE_35[29:0],PINS_DATA_IN_MODE_34[29:0],PINS_DATA_IN_MODE_33[29:0],PINS_DATA_IN_MODE_32[29:0],PINS_DATA_IN_MODE_31[29:0],PINS_DATA_IN_MODE_30[29:0],PINS_DATA_IN_MODE_29[29:0],PINS_DATA_IN_MODE_28[29:0],PINS_DATA_IN_MODE_27[29:0],PINS_DATA_IN_MODE_26[29:0],PINS_DATA_IN_MODE_25[29:0],PINS_DATA_IN_MODE_24[29:0],PINS_DATA_IN_MODE_23[29:0],PINS_DATA_IN_MODE_22[29:0],PINS_DATA_IN_MODE_21[29:0],PINS_DATA_IN_MODE_20[29:0],PINS_DATA_IN_MODE_19[29:0],PINS_DATA_IN_MODE_18[29:0],PINS_DATA_IN_MODE_17[29:0],PINS_DATA_IN_MODE_16[29:0],PINS_DATA_IN_MODE_15[29:0],PINS_DATA_IN_MODE_14[29:0],PINS_DATA_IN_MODE_13[29:0],PINS_DATA_IN_MODE_12[29:0],PINS_DATA_IN_MODE_11[29:0],PINS_DATA_IN_MODE_10[29:0],PINS_DATA_IN_MODE_9[29:0],PINS_DATA_IN_MODE_8[29:0],PINS_DATA_IN_MODE_7[29:0],PINS_DATA_IN_MODE_6[29:0],PINS_DATA_IN_MODE_5[29:0],PINS_DATA_IN_MODE_4[29:0],PINS_DATA_IN_MODE_3[29:0],PINS_DATA_IN_MODE_2[29:0],PINS_DATA_IN_MODE_1[29:0],PINS_DATA_IN_MODE_0[29:0]}; + localparam PINS_C2L_DRIVEN = {PINS_C2L_DRIVEN_12[29:0],PINS_C2L_DRIVEN_11[29:0],PINS_C2L_DRIVEN_10[29:0],PINS_C2L_DRIVEN_9[29:0],PINS_C2L_DRIVEN_8[29:0],PINS_C2L_DRIVEN_7[29:0],PINS_C2L_DRIVEN_6[29:0],PINS_C2L_DRIVEN_5[29:0],PINS_C2L_DRIVEN_4[29:0],PINS_C2L_DRIVEN_3[29:0],PINS_C2L_DRIVEN_2[29:0],PINS_C2L_DRIVEN_1[29:0],PINS_C2L_DRIVEN_0[29:0]}; + localparam PINS_DB_IN_BYPASS = {PINS_DB_IN_BYPASS_12[29:0],PINS_DB_IN_BYPASS_11[29:0],PINS_DB_IN_BYPASS_10[29:0],PINS_DB_IN_BYPASS_9[29:0],PINS_DB_IN_BYPASS_8[29:0],PINS_DB_IN_BYPASS_7[29:0],PINS_DB_IN_BYPASS_6[29:0],PINS_DB_IN_BYPASS_5[29:0],PINS_DB_IN_BYPASS_4[29:0],PINS_DB_IN_BYPASS_3[29:0],PINS_DB_IN_BYPASS_2[29:0],PINS_DB_IN_BYPASS_1[29:0],PINS_DB_IN_BYPASS_0[29:0]}; + localparam PINS_DB_OUT_BYPASS = {PINS_DB_OUT_BYPASS_12[29:0],PINS_DB_OUT_BYPASS_11[29:0],PINS_DB_OUT_BYPASS_10[29:0],PINS_DB_OUT_BYPASS_9[29:0],PINS_DB_OUT_BYPASS_8[29:0],PINS_DB_OUT_BYPASS_7[29:0],PINS_DB_OUT_BYPASS_6[29:0],PINS_DB_OUT_BYPASS_5[29:0],PINS_DB_OUT_BYPASS_4[29:0],PINS_DB_OUT_BYPASS_3[29:0],PINS_DB_OUT_BYPASS_2[29:0],PINS_DB_OUT_BYPASS_1[29:0],PINS_DB_OUT_BYPASS_0[29:0]}; + localparam PINS_DB_OE_BYPASS = {PINS_DB_OE_BYPASS_12[29:0],PINS_DB_OE_BYPASS_11[29:0],PINS_DB_OE_BYPASS_10[29:0],PINS_DB_OE_BYPASS_9[29:0],PINS_DB_OE_BYPASS_8[29:0],PINS_DB_OE_BYPASS_7[29:0],PINS_DB_OE_BYPASS_6[29:0],PINS_DB_OE_BYPASS_5[29:0],PINS_DB_OE_BYPASS_4[29:0],PINS_DB_OE_BYPASS_3[29:0],PINS_DB_OE_BYPASS_2[29:0],PINS_DB_OE_BYPASS_1[29:0],PINS_DB_OE_BYPASS_0[29:0]}; + localparam PINS_INVERT_WR = {PINS_INVERT_WR_12[29:0],PINS_INVERT_WR_11[29:0],PINS_INVERT_WR_10[29:0],PINS_INVERT_WR_9[29:0],PINS_INVERT_WR_8[29:0],PINS_INVERT_WR_7[29:0],PINS_INVERT_WR_6[29:0],PINS_INVERT_WR_5[29:0],PINS_INVERT_WR_4[29:0],PINS_INVERT_WR_3[29:0],PINS_INVERT_WR_2[29:0],PINS_INVERT_WR_1[29:0],PINS_INVERT_WR_0[29:0]}; + localparam PINS_INVERT_OE = {PINS_INVERT_OE_12[29:0],PINS_INVERT_OE_11[29:0],PINS_INVERT_OE_10[29:0],PINS_INVERT_OE_9[29:0],PINS_INVERT_OE_8[29:0],PINS_INVERT_OE_7[29:0],PINS_INVERT_OE_6[29:0],PINS_INVERT_OE_5[29:0],PINS_INVERT_OE_4[29:0],PINS_INVERT_OE_3[29:0],PINS_INVERT_OE_2[29:0],PINS_INVERT_OE_1[29:0],PINS_INVERT_OE_0[29:0]}; + localparam PINS_AC_HMC_DATA_OVERRIDE_ENA = {PINS_AC_HMC_DATA_OVERRIDE_ENA_12[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_11[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_10[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_9[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_8[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_7[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_6[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_5[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_4[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_3[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_2[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_1[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_0[29:0]}; + localparam PINS_OCT_MODE = {PINS_OCT_MODE_12[29:0],PINS_OCT_MODE_11[29:0],PINS_OCT_MODE_10[29:0],PINS_OCT_MODE_9[29:0],PINS_OCT_MODE_8[29:0],PINS_OCT_MODE_7[29:0],PINS_OCT_MODE_6[29:0],PINS_OCT_MODE_5[29:0],PINS_OCT_MODE_4[29:0],PINS_OCT_MODE_3[29:0],PINS_OCT_MODE_2[29:0],PINS_OCT_MODE_1[29:0],PINS_OCT_MODE_0[29:0]}; + localparam PINS_GPIO_MODE = {PINS_GPIO_MODE_12[29:0],PINS_GPIO_MODE_11[29:0],PINS_GPIO_MODE_10[29:0],PINS_GPIO_MODE_9[29:0],PINS_GPIO_MODE_8[29:0],PINS_GPIO_MODE_7[29:0],PINS_GPIO_MODE_6[29:0],PINS_GPIO_MODE_5[29:0],PINS_GPIO_MODE_4[29:0],PINS_GPIO_MODE_3[29:0],PINS_GPIO_MODE_2[29:0],PINS_GPIO_MODE_1[29:0],PINS_GPIO_MODE_0[29:0]}; + localparam UNUSED_MEM_PINS_PINLOC = {UNUSED_MEM_PINS_PINLOC_128[29:0],UNUSED_MEM_PINS_PINLOC_127[29:0],UNUSED_MEM_PINS_PINLOC_126[29:0],UNUSED_MEM_PINS_PINLOC_125[29:0],UNUSED_MEM_PINS_PINLOC_124[29:0],UNUSED_MEM_PINS_PINLOC_123[29:0],UNUSED_MEM_PINS_PINLOC_122[29:0],UNUSED_MEM_PINS_PINLOC_121[29:0],UNUSED_MEM_PINS_PINLOC_120[29:0],UNUSED_MEM_PINS_PINLOC_119[29:0],UNUSED_MEM_PINS_PINLOC_118[29:0],UNUSED_MEM_PINS_PINLOC_117[29:0],UNUSED_MEM_PINS_PINLOC_116[29:0],UNUSED_MEM_PINS_PINLOC_115[29:0],UNUSED_MEM_PINS_PINLOC_114[29:0],UNUSED_MEM_PINS_PINLOC_113[29:0],UNUSED_MEM_PINS_PINLOC_112[29:0],UNUSED_MEM_PINS_PINLOC_111[29:0],UNUSED_MEM_PINS_PINLOC_110[29:0],UNUSED_MEM_PINS_PINLOC_109[29:0],UNUSED_MEM_PINS_PINLOC_108[29:0],UNUSED_MEM_PINS_PINLOC_107[29:0],UNUSED_MEM_PINS_PINLOC_106[29:0],UNUSED_MEM_PINS_PINLOC_105[29:0],UNUSED_MEM_PINS_PINLOC_104[29:0],UNUSED_MEM_PINS_PINLOC_103[29:0],UNUSED_MEM_PINS_PINLOC_102[29:0],UNUSED_MEM_PINS_PINLOC_101[29:0],UNUSED_MEM_PINS_PINLOC_100[29:0],UNUSED_MEM_PINS_PINLOC_99[29:0],UNUSED_MEM_PINS_PINLOC_98[29:0],UNUSED_MEM_PINS_PINLOC_97[29:0],UNUSED_MEM_PINS_PINLOC_96[29:0],UNUSED_MEM_PINS_PINLOC_95[29:0],UNUSED_MEM_PINS_PINLOC_94[29:0],UNUSED_MEM_PINS_PINLOC_93[29:0],UNUSED_MEM_PINS_PINLOC_92[29:0],UNUSED_MEM_PINS_PINLOC_91[29:0],UNUSED_MEM_PINS_PINLOC_90[29:0],UNUSED_MEM_PINS_PINLOC_89[29:0],UNUSED_MEM_PINS_PINLOC_88[29:0],UNUSED_MEM_PINS_PINLOC_87[29:0],UNUSED_MEM_PINS_PINLOC_86[29:0],UNUSED_MEM_PINS_PINLOC_85[29:0],UNUSED_MEM_PINS_PINLOC_84[29:0],UNUSED_MEM_PINS_PINLOC_83[29:0],UNUSED_MEM_PINS_PINLOC_82[29:0],UNUSED_MEM_PINS_PINLOC_81[29:0],UNUSED_MEM_PINS_PINLOC_80[29:0],UNUSED_MEM_PINS_PINLOC_79[29:0],UNUSED_MEM_PINS_PINLOC_78[29:0],UNUSED_MEM_PINS_PINLOC_77[29:0],UNUSED_MEM_PINS_PINLOC_76[29:0],UNUSED_MEM_PINS_PINLOC_75[29:0],UNUSED_MEM_PINS_PINLOC_74[29:0],UNUSED_MEM_PINS_PINLOC_73[29:0],UNUSED_MEM_PINS_PINLOC_72[29:0],UNUSED_MEM_PINS_PINLOC_71[29:0],UNUSED_MEM_PINS_PINLOC_70[29:0],UNUSED_MEM_PINS_PINLOC_69[29:0],UNUSED_MEM_PINS_PINLOC_68[29:0],UNUSED_MEM_PINS_PINLOC_67[29:0],UNUSED_MEM_PINS_PINLOC_66[29:0],UNUSED_MEM_PINS_PINLOC_65[29:0],UNUSED_MEM_PINS_PINLOC_64[29:0],UNUSED_MEM_PINS_PINLOC_63[29:0],UNUSED_MEM_PINS_PINLOC_62[29:0],UNUSED_MEM_PINS_PINLOC_61[29:0],UNUSED_MEM_PINS_PINLOC_60[29:0],UNUSED_MEM_PINS_PINLOC_59[29:0],UNUSED_MEM_PINS_PINLOC_58[29:0],UNUSED_MEM_PINS_PINLOC_57[29:0],UNUSED_MEM_PINS_PINLOC_56[29:0],UNUSED_MEM_PINS_PINLOC_55[29:0],UNUSED_MEM_PINS_PINLOC_54[29:0],UNUSED_MEM_PINS_PINLOC_53[29:0],UNUSED_MEM_PINS_PINLOC_52[29:0],UNUSED_MEM_PINS_PINLOC_51[29:0],UNUSED_MEM_PINS_PINLOC_50[29:0],UNUSED_MEM_PINS_PINLOC_49[29:0],UNUSED_MEM_PINS_PINLOC_48[29:0],UNUSED_MEM_PINS_PINLOC_47[29:0],UNUSED_MEM_PINS_PINLOC_46[29:0],UNUSED_MEM_PINS_PINLOC_45[29:0],UNUSED_MEM_PINS_PINLOC_44[29:0],UNUSED_MEM_PINS_PINLOC_43[29:0],UNUSED_MEM_PINS_PINLOC_42[29:0],UNUSED_MEM_PINS_PINLOC_41[29:0],UNUSED_MEM_PINS_PINLOC_40[29:0],UNUSED_MEM_PINS_PINLOC_39[29:0],UNUSED_MEM_PINS_PINLOC_38[29:0],UNUSED_MEM_PINS_PINLOC_37[29:0],UNUSED_MEM_PINS_PINLOC_36[29:0],UNUSED_MEM_PINS_PINLOC_35[29:0],UNUSED_MEM_PINS_PINLOC_34[29:0],UNUSED_MEM_PINS_PINLOC_33[29:0],UNUSED_MEM_PINS_PINLOC_32[29:0],UNUSED_MEM_PINS_PINLOC_31[29:0],UNUSED_MEM_PINS_PINLOC_30[29:0],UNUSED_MEM_PINS_PINLOC_29[29:0],UNUSED_MEM_PINS_PINLOC_28[29:0],UNUSED_MEM_PINS_PINLOC_27[29:0],UNUSED_MEM_PINS_PINLOC_26[29:0],UNUSED_MEM_PINS_PINLOC_25[29:0],UNUSED_MEM_PINS_PINLOC_24[29:0],UNUSED_MEM_PINS_PINLOC_23[29:0],UNUSED_MEM_PINS_PINLOC_22[29:0],UNUSED_MEM_PINS_PINLOC_21[29:0],UNUSED_MEM_PINS_PINLOC_20[29:0],UNUSED_MEM_PINS_PINLOC_19[29:0],UNUSED_MEM_PINS_PINLOC_18[29:0],UNUSED_MEM_PINS_PINLOC_17[29:0],UNUSED_MEM_PINS_PINLOC_16[29:0],UNUSED_MEM_PINS_PINLOC_15[29:0],UNUSED_MEM_PINS_PINLOC_14[29:0],UNUSED_MEM_PINS_PINLOC_13[29:0],UNUSED_MEM_PINS_PINLOC_12[29:0],UNUSED_MEM_PINS_PINLOC_11[29:0],UNUSED_MEM_PINS_PINLOC_10[29:0],UNUSED_MEM_PINS_PINLOC_9[29:0],UNUSED_MEM_PINS_PINLOC_8[29:0],UNUSED_MEM_PINS_PINLOC_7[29:0],UNUSED_MEM_PINS_PINLOC_6[29:0],UNUSED_MEM_PINS_PINLOC_5[29:0],UNUSED_MEM_PINS_PINLOC_4[29:0],UNUSED_MEM_PINS_PINLOC_3[29:0],UNUSED_MEM_PINS_PINLOC_2[29:0],UNUSED_MEM_PINS_PINLOC_1[29:0],UNUSED_MEM_PINS_PINLOC_0[29:0]}; + localparam UNUSED_DQS_BUSES_LANELOC = {UNUSED_DQS_BUSES_LANELOC_10[29:0],UNUSED_DQS_BUSES_LANELOC_9[29:0],UNUSED_DQS_BUSES_LANELOC_8[29:0],UNUSED_DQS_BUSES_LANELOC_7[29:0],UNUSED_DQS_BUSES_LANELOC_6[29:0],UNUSED_DQS_BUSES_LANELOC_5[29:0],UNUSED_DQS_BUSES_LANELOC_4[29:0],UNUSED_DQS_BUSES_LANELOC_3[29:0],UNUSED_DQS_BUSES_LANELOC_2[29:0],UNUSED_DQS_BUSES_LANELOC_1[29:0],UNUSED_DQS_BUSES_LANELOC_0[29:0]}; + localparam CENTER_TIDS = {CENTER_TIDS_2[29:0],CENTER_TIDS_1[29:0],CENTER_TIDS_0[29:0]}; + localparam HMC_TIDS = {HMC_TIDS_2[29:0],HMC_TIDS_1[29:0],HMC_TIDS_0[29:0]}; + localparam LANE_TIDS = {LANE_TIDS_9[29:0],LANE_TIDS_8[29:0],LANE_TIDS_7[29:0],LANE_TIDS_6[29:0],LANE_TIDS_5[29:0],LANE_TIDS_4[29:0],LANE_TIDS_3[29:0],LANE_TIDS_2[29:0],LANE_TIDS_1[29:0],LANE_TIDS_0[29:0]}; + localparam PORT_MEM_CK_PINLOC = {PORT_MEM_CK_PINLOC_5[29:0],PORT_MEM_CK_PINLOC_4[29:0],PORT_MEM_CK_PINLOC_3[29:0],PORT_MEM_CK_PINLOC_2[29:0],PORT_MEM_CK_PINLOC_1[29:0],PORT_MEM_CK_PINLOC_0[29:0]}; + localparam PORT_MEM_CK_N_PINLOC = {PORT_MEM_CK_N_PINLOC_5[29:0],PORT_MEM_CK_N_PINLOC_4[29:0],PORT_MEM_CK_N_PINLOC_3[29:0],PORT_MEM_CK_N_PINLOC_2[29:0],PORT_MEM_CK_N_PINLOC_1[29:0],PORT_MEM_CK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_PINLOC = {PORT_MEM_DK_PINLOC_5[29:0],PORT_MEM_DK_PINLOC_4[29:0],PORT_MEM_DK_PINLOC_3[29:0],PORT_MEM_DK_PINLOC_2[29:0],PORT_MEM_DK_PINLOC_1[29:0],PORT_MEM_DK_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_N_PINLOC = {PORT_MEM_DK_N_PINLOC_5[29:0],PORT_MEM_DK_N_PINLOC_4[29:0],PORT_MEM_DK_N_PINLOC_3[29:0],PORT_MEM_DK_N_PINLOC_2[29:0],PORT_MEM_DK_N_PINLOC_1[29:0],PORT_MEM_DK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_PINLOC = {PORT_MEM_DKA_PINLOC_5[29:0],PORT_MEM_DKA_PINLOC_4[29:0],PORT_MEM_DKA_PINLOC_3[29:0],PORT_MEM_DKA_PINLOC_2[29:0],PORT_MEM_DKA_PINLOC_1[29:0],PORT_MEM_DKA_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_N_PINLOC = {PORT_MEM_DKA_N_PINLOC_5[29:0],PORT_MEM_DKA_N_PINLOC_4[29:0],PORT_MEM_DKA_N_PINLOC_3[29:0],PORT_MEM_DKA_N_PINLOC_2[29:0],PORT_MEM_DKA_N_PINLOC_1[29:0],PORT_MEM_DKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_PINLOC = {PORT_MEM_DKB_PINLOC_5[29:0],PORT_MEM_DKB_PINLOC_4[29:0],PORT_MEM_DKB_PINLOC_3[29:0],PORT_MEM_DKB_PINLOC_2[29:0],PORT_MEM_DKB_PINLOC_1[29:0],PORT_MEM_DKB_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_N_PINLOC = {PORT_MEM_DKB_N_PINLOC_5[29:0],PORT_MEM_DKB_N_PINLOC_4[29:0],PORT_MEM_DKB_N_PINLOC_3[29:0],PORT_MEM_DKB_N_PINLOC_2[29:0],PORT_MEM_DKB_N_PINLOC_1[29:0],PORT_MEM_DKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_K_PINLOC = {PORT_MEM_K_PINLOC_5[29:0],PORT_MEM_K_PINLOC_4[29:0],PORT_MEM_K_PINLOC_3[29:0],PORT_MEM_K_PINLOC_2[29:0],PORT_MEM_K_PINLOC_1[29:0],PORT_MEM_K_PINLOC_0[29:0]}; + localparam PORT_MEM_K_N_PINLOC = {PORT_MEM_K_N_PINLOC_5[29:0],PORT_MEM_K_N_PINLOC_4[29:0],PORT_MEM_K_N_PINLOC_3[29:0],PORT_MEM_K_N_PINLOC_2[29:0],PORT_MEM_K_N_PINLOC_1[29:0],PORT_MEM_K_N_PINLOC_0[29:0]}; + localparam PORT_MEM_A_PINLOC = {PORT_MEM_A_PINLOC_16[29:0],PORT_MEM_A_PINLOC_15[29:0],PORT_MEM_A_PINLOC_14[29:0],PORT_MEM_A_PINLOC_13[29:0],PORT_MEM_A_PINLOC_12[29:0],PORT_MEM_A_PINLOC_11[29:0],PORT_MEM_A_PINLOC_10[29:0],PORT_MEM_A_PINLOC_9[29:0],PORT_MEM_A_PINLOC_8[29:0],PORT_MEM_A_PINLOC_7[29:0],PORT_MEM_A_PINLOC_6[29:0],PORT_MEM_A_PINLOC_5[29:0],PORT_MEM_A_PINLOC_4[29:0],PORT_MEM_A_PINLOC_3[29:0],PORT_MEM_A_PINLOC_2[29:0],PORT_MEM_A_PINLOC_1[29:0],PORT_MEM_A_PINLOC_0[29:0]}; + localparam PORT_MEM_BA_PINLOC = {PORT_MEM_BA_PINLOC_5[29:0],PORT_MEM_BA_PINLOC_4[29:0],PORT_MEM_BA_PINLOC_3[29:0],PORT_MEM_BA_PINLOC_2[29:0],PORT_MEM_BA_PINLOC_1[29:0],PORT_MEM_BA_PINLOC_0[29:0]}; + localparam PORT_MEM_BG_PINLOC = {PORT_MEM_BG_PINLOC_5[29:0],PORT_MEM_BG_PINLOC_4[29:0],PORT_MEM_BG_PINLOC_3[29:0],PORT_MEM_BG_PINLOC_2[29:0],PORT_MEM_BG_PINLOC_1[29:0],PORT_MEM_BG_PINLOC_0[29:0]}; + localparam PORT_MEM_C_PINLOC = {PORT_MEM_C_PINLOC_5[29:0],PORT_MEM_C_PINLOC_4[29:0],PORT_MEM_C_PINLOC_3[29:0],PORT_MEM_C_PINLOC_2[29:0],PORT_MEM_C_PINLOC_1[29:0],PORT_MEM_C_PINLOC_0[29:0]}; + localparam PORT_MEM_CKE_PINLOC = {PORT_MEM_CKE_PINLOC_5[29:0],PORT_MEM_CKE_PINLOC_4[29:0],PORT_MEM_CKE_PINLOC_3[29:0],PORT_MEM_CKE_PINLOC_2[29:0],PORT_MEM_CKE_PINLOC_1[29:0],PORT_MEM_CKE_PINLOC_0[29:0]}; + localparam PORT_MEM_CS_N_PINLOC = {PORT_MEM_CS_N_PINLOC_5[29:0],PORT_MEM_CS_N_PINLOC_4[29:0],PORT_MEM_CS_N_PINLOC_3[29:0],PORT_MEM_CS_N_PINLOC_2[29:0],PORT_MEM_CS_N_PINLOC_1[29:0],PORT_MEM_CS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RM_PINLOC = {PORT_MEM_RM_PINLOC_5[29:0],PORT_MEM_RM_PINLOC_4[29:0],PORT_MEM_RM_PINLOC_3[29:0],PORT_MEM_RM_PINLOC_2[29:0],PORT_MEM_RM_PINLOC_1[29:0],PORT_MEM_RM_PINLOC_0[29:0]}; + localparam PORT_MEM_ODT_PINLOC = {PORT_MEM_ODT_PINLOC_5[29:0],PORT_MEM_ODT_PINLOC_4[29:0],PORT_MEM_ODT_PINLOC_3[29:0],PORT_MEM_ODT_PINLOC_2[29:0],PORT_MEM_ODT_PINLOC_1[29:0],PORT_MEM_ODT_PINLOC_0[29:0]}; + localparam PORT_MEM_RAS_N_PINLOC = {PORT_MEM_RAS_N_PINLOC_1[29:0],PORT_MEM_RAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CAS_N_PINLOC = {PORT_MEM_CAS_N_PINLOC_1[29:0],PORT_MEM_CAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WE_N_PINLOC = {PORT_MEM_WE_N_PINLOC_1[29:0],PORT_MEM_WE_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RESET_N_PINLOC = {PORT_MEM_RESET_N_PINLOC_1[29:0],PORT_MEM_RESET_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ACT_N_PINLOC = {PORT_MEM_ACT_N_PINLOC_1[29:0],PORT_MEM_ACT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PAR_PINLOC = {PORT_MEM_PAR_PINLOC_1[29:0],PORT_MEM_PAR_PINLOC_0[29:0]}; + localparam PORT_MEM_CA_PINLOC = {PORT_MEM_CA_PINLOC_16[29:0],PORT_MEM_CA_PINLOC_15[29:0],PORT_MEM_CA_PINLOC_14[29:0],PORT_MEM_CA_PINLOC_13[29:0],PORT_MEM_CA_PINLOC_12[29:0],PORT_MEM_CA_PINLOC_11[29:0],PORT_MEM_CA_PINLOC_10[29:0],PORT_MEM_CA_PINLOC_9[29:0],PORT_MEM_CA_PINLOC_8[29:0],PORT_MEM_CA_PINLOC_7[29:0],PORT_MEM_CA_PINLOC_6[29:0],PORT_MEM_CA_PINLOC_5[29:0],PORT_MEM_CA_PINLOC_4[29:0],PORT_MEM_CA_PINLOC_3[29:0],PORT_MEM_CA_PINLOC_2[29:0],PORT_MEM_CA_PINLOC_1[29:0],PORT_MEM_CA_PINLOC_0[29:0]}; + localparam PORT_MEM_REF_N_PINLOC = {PORT_MEM_REF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WPS_N_PINLOC = {PORT_MEM_WPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RPS_N_PINLOC = {PORT_MEM_RPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DOFF_N_PINLOC = {PORT_MEM_DOFF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDA_N_PINLOC = {PORT_MEM_LDA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDB_N_PINLOC = {PORT_MEM_LDB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWA_N_PINLOC = {PORT_MEM_RWA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWB_N_PINLOC = {PORT_MEM_RWB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK0_N_PINLOC = {PORT_MEM_LBK0_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK1_N_PINLOC = {PORT_MEM_LBK1_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CFG_N_PINLOC = {PORT_MEM_CFG_N_PINLOC_0[29:0]}; + localparam PORT_MEM_AP_PINLOC = {PORT_MEM_AP_PINLOC_0[29:0]}; + localparam PORT_MEM_AINV_PINLOC = {PORT_MEM_AINV_PINLOC_0[29:0]}; + localparam PORT_MEM_DM_PINLOC = {PORT_MEM_DM_PINLOC_12[29:0],PORT_MEM_DM_PINLOC_11[29:0],PORT_MEM_DM_PINLOC_10[29:0],PORT_MEM_DM_PINLOC_9[29:0],PORT_MEM_DM_PINLOC_8[29:0],PORT_MEM_DM_PINLOC_7[29:0],PORT_MEM_DM_PINLOC_6[29:0],PORT_MEM_DM_PINLOC_5[29:0],PORT_MEM_DM_PINLOC_4[29:0],PORT_MEM_DM_PINLOC_3[29:0],PORT_MEM_DM_PINLOC_2[29:0],PORT_MEM_DM_PINLOC_1[29:0],PORT_MEM_DM_PINLOC_0[29:0]}; + localparam PORT_MEM_BWS_N_PINLOC = {PORT_MEM_BWS_N_PINLOC_2[29:0],PORT_MEM_BWS_N_PINLOC_1[29:0],PORT_MEM_BWS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_D_PINLOC = {PORT_MEM_D_PINLOC_48[29:0],PORT_MEM_D_PINLOC_47[29:0],PORT_MEM_D_PINLOC_46[29:0],PORT_MEM_D_PINLOC_45[29:0],PORT_MEM_D_PINLOC_44[29:0],PORT_MEM_D_PINLOC_43[29:0],PORT_MEM_D_PINLOC_42[29:0],PORT_MEM_D_PINLOC_41[29:0],PORT_MEM_D_PINLOC_40[29:0],PORT_MEM_D_PINLOC_39[29:0],PORT_MEM_D_PINLOC_38[29:0],PORT_MEM_D_PINLOC_37[29:0],PORT_MEM_D_PINLOC_36[29:0],PORT_MEM_D_PINLOC_35[29:0],PORT_MEM_D_PINLOC_34[29:0],PORT_MEM_D_PINLOC_33[29:0],PORT_MEM_D_PINLOC_32[29:0],PORT_MEM_D_PINLOC_31[29:0],PORT_MEM_D_PINLOC_30[29:0],PORT_MEM_D_PINLOC_29[29:0],PORT_MEM_D_PINLOC_28[29:0],PORT_MEM_D_PINLOC_27[29:0],PORT_MEM_D_PINLOC_26[29:0],PORT_MEM_D_PINLOC_25[29:0],PORT_MEM_D_PINLOC_24[29:0],PORT_MEM_D_PINLOC_23[29:0],PORT_MEM_D_PINLOC_22[29:0],PORT_MEM_D_PINLOC_21[29:0],PORT_MEM_D_PINLOC_20[29:0],PORT_MEM_D_PINLOC_19[29:0],PORT_MEM_D_PINLOC_18[29:0],PORT_MEM_D_PINLOC_17[29:0],PORT_MEM_D_PINLOC_16[29:0],PORT_MEM_D_PINLOC_15[29:0],PORT_MEM_D_PINLOC_14[29:0],PORT_MEM_D_PINLOC_13[29:0],PORT_MEM_D_PINLOC_12[29:0],PORT_MEM_D_PINLOC_11[29:0],PORT_MEM_D_PINLOC_10[29:0],PORT_MEM_D_PINLOC_9[29:0],PORT_MEM_D_PINLOC_8[29:0],PORT_MEM_D_PINLOC_7[29:0],PORT_MEM_D_PINLOC_6[29:0],PORT_MEM_D_PINLOC_5[29:0],PORT_MEM_D_PINLOC_4[29:0],PORT_MEM_D_PINLOC_3[29:0],PORT_MEM_D_PINLOC_2[29:0],PORT_MEM_D_PINLOC_1[29:0],PORT_MEM_D_PINLOC_0[29:0]}; + localparam PORT_MEM_DQ_PINLOC = {PORT_MEM_DQ_PINLOC_48[29:0],PORT_MEM_DQ_PINLOC_47[29:0],PORT_MEM_DQ_PINLOC_46[29:0],PORT_MEM_DQ_PINLOC_45[29:0],PORT_MEM_DQ_PINLOC_44[29:0],PORT_MEM_DQ_PINLOC_43[29:0],PORT_MEM_DQ_PINLOC_42[29:0],PORT_MEM_DQ_PINLOC_41[29:0],PORT_MEM_DQ_PINLOC_40[29:0],PORT_MEM_DQ_PINLOC_39[29:0],PORT_MEM_DQ_PINLOC_38[29:0],PORT_MEM_DQ_PINLOC_37[29:0],PORT_MEM_DQ_PINLOC_36[29:0],PORT_MEM_DQ_PINLOC_35[29:0],PORT_MEM_DQ_PINLOC_34[29:0],PORT_MEM_DQ_PINLOC_33[29:0],PORT_MEM_DQ_PINLOC_32[29:0],PORT_MEM_DQ_PINLOC_31[29:0],PORT_MEM_DQ_PINLOC_30[29:0],PORT_MEM_DQ_PINLOC_29[29:0],PORT_MEM_DQ_PINLOC_28[29:0],PORT_MEM_DQ_PINLOC_27[29:0],PORT_MEM_DQ_PINLOC_26[29:0],PORT_MEM_DQ_PINLOC_25[29:0],PORT_MEM_DQ_PINLOC_24[29:0],PORT_MEM_DQ_PINLOC_23[29:0],PORT_MEM_DQ_PINLOC_22[29:0],PORT_MEM_DQ_PINLOC_21[29:0],PORT_MEM_DQ_PINLOC_20[29:0],PORT_MEM_DQ_PINLOC_19[29:0],PORT_MEM_DQ_PINLOC_18[29:0],PORT_MEM_DQ_PINLOC_17[29:0],PORT_MEM_DQ_PINLOC_16[29:0],PORT_MEM_DQ_PINLOC_15[29:0],PORT_MEM_DQ_PINLOC_14[29:0],PORT_MEM_DQ_PINLOC_13[29:0],PORT_MEM_DQ_PINLOC_12[29:0],PORT_MEM_DQ_PINLOC_11[29:0],PORT_MEM_DQ_PINLOC_10[29:0],PORT_MEM_DQ_PINLOC_9[29:0],PORT_MEM_DQ_PINLOC_8[29:0],PORT_MEM_DQ_PINLOC_7[29:0],PORT_MEM_DQ_PINLOC_6[29:0],PORT_MEM_DQ_PINLOC_5[29:0],PORT_MEM_DQ_PINLOC_4[29:0],PORT_MEM_DQ_PINLOC_3[29:0],PORT_MEM_DQ_PINLOC_2[29:0],PORT_MEM_DQ_PINLOC_1[29:0],PORT_MEM_DQ_PINLOC_0[29:0]}; + localparam PORT_MEM_DBI_N_PINLOC = {PORT_MEM_DBI_N_PINLOC_6[29:0],PORT_MEM_DBI_N_PINLOC_5[29:0],PORT_MEM_DBI_N_PINLOC_4[29:0],PORT_MEM_DBI_N_PINLOC_3[29:0],PORT_MEM_DBI_N_PINLOC_2[29:0],PORT_MEM_DBI_N_PINLOC_1[29:0],PORT_MEM_DBI_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DQA_PINLOC = {PORT_MEM_DQA_PINLOC_48[29:0],PORT_MEM_DQA_PINLOC_47[29:0],PORT_MEM_DQA_PINLOC_46[29:0],PORT_MEM_DQA_PINLOC_45[29:0],PORT_MEM_DQA_PINLOC_44[29:0],PORT_MEM_DQA_PINLOC_43[29:0],PORT_MEM_DQA_PINLOC_42[29:0],PORT_MEM_DQA_PINLOC_41[29:0],PORT_MEM_DQA_PINLOC_40[29:0],PORT_MEM_DQA_PINLOC_39[29:0],PORT_MEM_DQA_PINLOC_38[29:0],PORT_MEM_DQA_PINLOC_37[29:0],PORT_MEM_DQA_PINLOC_36[29:0],PORT_MEM_DQA_PINLOC_35[29:0],PORT_MEM_DQA_PINLOC_34[29:0],PORT_MEM_DQA_PINLOC_33[29:0],PORT_MEM_DQA_PINLOC_32[29:0],PORT_MEM_DQA_PINLOC_31[29:0],PORT_MEM_DQA_PINLOC_30[29:0],PORT_MEM_DQA_PINLOC_29[29:0],PORT_MEM_DQA_PINLOC_28[29:0],PORT_MEM_DQA_PINLOC_27[29:0],PORT_MEM_DQA_PINLOC_26[29:0],PORT_MEM_DQA_PINLOC_25[29:0],PORT_MEM_DQA_PINLOC_24[29:0],PORT_MEM_DQA_PINLOC_23[29:0],PORT_MEM_DQA_PINLOC_22[29:0],PORT_MEM_DQA_PINLOC_21[29:0],PORT_MEM_DQA_PINLOC_20[29:0],PORT_MEM_DQA_PINLOC_19[29:0],PORT_MEM_DQA_PINLOC_18[29:0],PORT_MEM_DQA_PINLOC_17[29:0],PORT_MEM_DQA_PINLOC_16[29:0],PORT_MEM_DQA_PINLOC_15[29:0],PORT_MEM_DQA_PINLOC_14[29:0],PORT_MEM_DQA_PINLOC_13[29:0],PORT_MEM_DQA_PINLOC_12[29:0],PORT_MEM_DQA_PINLOC_11[29:0],PORT_MEM_DQA_PINLOC_10[29:0],PORT_MEM_DQA_PINLOC_9[29:0],PORT_MEM_DQA_PINLOC_8[29:0],PORT_MEM_DQA_PINLOC_7[29:0],PORT_MEM_DQA_PINLOC_6[29:0],PORT_MEM_DQA_PINLOC_5[29:0],PORT_MEM_DQA_PINLOC_4[29:0],PORT_MEM_DQA_PINLOC_3[29:0],PORT_MEM_DQA_PINLOC_2[29:0],PORT_MEM_DQA_PINLOC_1[29:0],PORT_MEM_DQA_PINLOC_0[29:0]}; + localparam PORT_MEM_DQB_PINLOC = {PORT_MEM_DQB_PINLOC_48[29:0],PORT_MEM_DQB_PINLOC_47[29:0],PORT_MEM_DQB_PINLOC_46[29:0],PORT_MEM_DQB_PINLOC_45[29:0],PORT_MEM_DQB_PINLOC_44[29:0],PORT_MEM_DQB_PINLOC_43[29:0],PORT_MEM_DQB_PINLOC_42[29:0],PORT_MEM_DQB_PINLOC_41[29:0],PORT_MEM_DQB_PINLOC_40[29:0],PORT_MEM_DQB_PINLOC_39[29:0],PORT_MEM_DQB_PINLOC_38[29:0],PORT_MEM_DQB_PINLOC_37[29:0],PORT_MEM_DQB_PINLOC_36[29:0],PORT_MEM_DQB_PINLOC_35[29:0],PORT_MEM_DQB_PINLOC_34[29:0],PORT_MEM_DQB_PINLOC_33[29:0],PORT_MEM_DQB_PINLOC_32[29:0],PORT_MEM_DQB_PINLOC_31[29:0],PORT_MEM_DQB_PINLOC_30[29:0],PORT_MEM_DQB_PINLOC_29[29:0],PORT_MEM_DQB_PINLOC_28[29:0],PORT_MEM_DQB_PINLOC_27[29:0],PORT_MEM_DQB_PINLOC_26[29:0],PORT_MEM_DQB_PINLOC_25[29:0],PORT_MEM_DQB_PINLOC_24[29:0],PORT_MEM_DQB_PINLOC_23[29:0],PORT_MEM_DQB_PINLOC_22[29:0],PORT_MEM_DQB_PINLOC_21[29:0],PORT_MEM_DQB_PINLOC_20[29:0],PORT_MEM_DQB_PINLOC_19[29:0],PORT_MEM_DQB_PINLOC_18[29:0],PORT_MEM_DQB_PINLOC_17[29:0],PORT_MEM_DQB_PINLOC_16[29:0],PORT_MEM_DQB_PINLOC_15[29:0],PORT_MEM_DQB_PINLOC_14[29:0],PORT_MEM_DQB_PINLOC_13[29:0],PORT_MEM_DQB_PINLOC_12[29:0],PORT_MEM_DQB_PINLOC_11[29:0],PORT_MEM_DQB_PINLOC_10[29:0],PORT_MEM_DQB_PINLOC_9[29:0],PORT_MEM_DQB_PINLOC_8[29:0],PORT_MEM_DQB_PINLOC_7[29:0],PORT_MEM_DQB_PINLOC_6[29:0],PORT_MEM_DQB_PINLOC_5[29:0],PORT_MEM_DQB_PINLOC_4[29:0],PORT_MEM_DQB_PINLOC_3[29:0],PORT_MEM_DQB_PINLOC_2[29:0],PORT_MEM_DQB_PINLOC_1[29:0],PORT_MEM_DQB_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVA_PINLOC = {PORT_MEM_DINVA_PINLOC_2[29:0],PORT_MEM_DINVA_PINLOC_1[29:0],PORT_MEM_DINVA_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVB_PINLOC = {PORT_MEM_DINVB_PINLOC_2[29:0],PORT_MEM_DINVB_PINLOC_1[29:0],PORT_MEM_DINVB_PINLOC_0[29:0]}; + localparam PORT_MEM_Q_PINLOC = {PORT_MEM_Q_PINLOC_48[29:0],PORT_MEM_Q_PINLOC_47[29:0],PORT_MEM_Q_PINLOC_46[29:0],PORT_MEM_Q_PINLOC_45[29:0],PORT_MEM_Q_PINLOC_44[29:0],PORT_MEM_Q_PINLOC_43[29:0],PORT_MEM_Q_PINLOC_42[29:0],PORT_MEM_Q_PINLOC_41[29:0],PORT_MEM_Q_PINLOC_40[29:0],PORT_MEM_Q_PINLOC_39[29:0],PORT_MEM_Q_PINLOC_38[29:0],PORT_MEM_Q_PINLOC_37[29:0],PORT_MEM_Q_PINLOC_36[29:0],PORT_MEM_Q_PINLOC_35[29:0],PORT_MEM_Q_PINLOC_34[29:0],PORT_MEM_Q_PINLOC_33[29:0],PORT_MEM_Q_PINLOC_32[29:0],PORT_MEM_Q_PINLOC_31[29:0],PORT_MEM_Q_PINLOC_30[29:0],PORT_MEM_Q_PINLOC_29[29:0],PORT_MEM_Q_PINLOC_28[29:0],PORT_MEM_Q_PINLOC_27[29:0],PORT_MEM_Q_PINLOC_26[29:0],PORT_MEM_Q_PINLOC_25[29:0],PORT_MEM_Q_PINLOC_24[29:0],PORT_MEM_Q_PINLOC_23[29:0],PORT_MEM_Q_PINLOC_22[29:0],PORT_MEM_Q_PINLOC_21[29:0],PORT_MEM_Q_PINLOC_20[29:0],PORT_MEM_Q_PINLOC_19[29:0],PORT_MEM_Q_PINLOC_18[29:0],PORT_MEM_Q_PINLOC_17[29:0],PORT_MEM_Q_PINLOC_16[29:0],PORT_MEM_Q_PINLOC_15[29:0],PORT_MEM_Q_PINLOC_14[29:0],PORT_MEM_Q_PINLOC_13[29:0],PORT_MEM_Q_PINLOC_12[29:0],PORT_MEM_Q_PINLOC_11[29:0],PORT_MEM_Q_PINLOC_10[29:0],PORT_MEM_Q_PINLOC_9[29:0],PORT_MEM_Q_PINLOC_8[29:0],PORT_MEM_Q_PINLOC_7[29:0],PORT_MEM_Q_PINLOC_6[29:0],PORT_MEM_Q_PINLOC_5[29:0],PORT_MEM_Q_PINLOC_4[29:0],PORT_MEM_Q_PINLOC_3[29:0],PORT_MEM_Q_PINLOC_2[29:0],PORT_MEM_Q_PINLOC_1[29:0],PORT_MEM_Q_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_PINLOC = {PORT_MEM_DQS_PINLOC_12[29:0],PORT_MEM_DQS_PINLOC_11[29:0],PORT_MEM_DQS_PINLOC_10[29:0],PORT_MEM_DQS_PINLOC_9[29:0],PORT_MEM_DQS_PINLOC_8[29:0],PORT_MEM_DQS_PINLOC_7[29:0],PORT_MEM_DQS_PINLOC_6[29:0],PORT_MEM_DQS_PINLOC_5[29:0],PORT_MEM_DQS_PINLOC_4[29:0],PORT_MEM_DQS_PINLOC_3[29:0],PORT_MEM_DQS_PINLOC_2[29:0],PORT_MEM_DQS_PINLOC_1[29:0],PORT_MEM_DQS_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_N_PINLOC = {PORT_MEM_DQS_N_PINLOC_12[29:0],PORT_MEM_DQS_N_PINLOC_11[29:0],PORT_MEM_DQS_N_PINLOC_10[29:0],PORT_MEM_DQS_N_PINLOC_9[29:0],PORT_MEM_DQS_N_PINLOC_8[29:0],PORT_MEM_DQS_N_PINLOC_7[29:0],PORT_MEM_DQS_N_PINLOC_6[29:0],PORT_MEM_DQS_N_PINLOC_5[29:0],PORT_MEM_DQS_N_PINLOC_4[29:0],PORT_MEM_DQS_N_PINLOC_3[29:0],PORT_MEM_DQS_N_PINLOC_2[29:0],PORT_MEM_DQS_N_PINLOC_1[29:0],PORT_MEM_DQS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_PINLOC = {PORT_MEM_QK_PINLOC_5[29:0],PORT_MEM_QK_PINLOC_4[29:0],PORT_MEM_QK_PINLOC_3[29:0],PORT_MEM_QK_PINLOC_2[29:0],PORT_MEM_QK_PINLOC_1[29:0],PORT_MEM_QK_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_N_PINLOC = {PORT_MEM_QK_N_PINLOC_5[29:0],PORT_MEM_QK_N_PINLOC_4[29:0],PORT_MEM_QK_N_PINLOC_3[29:0],PORT_MEM_QK_N_PINLOC_2[29:0],PORT_MEM_QK_N_PINLOC_1[29:0],PORT_MEM_QK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_PINLOC = {PORT_MEM_QKA_PINLOC_5[29:0],PORT_MEM_QKA_PINLOC_4[29:0],PORT_MEM_QKA_PINLOC_3[29:0],PORT_MEM_QKA_PINLOC_2[29:0],PORT_MEM_QKA_PINLOC_1[29:0],PORT_MEM_QKA_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_N_PINLOC = {PORT_MEM_QKA_N_PINLOC_5[29:0],PORT_MEM_QKA_N_PINLOC_4[29:0],PORT_MEM_QKA_N_PINLOC_3[29:0],PORT_MEM_QKA_N_PINLOC_2[29:0],PORT_MEM_QKA_N_PINLOC_1[29:0],PORT_MEM_QKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_PINLOC = {PORT_MEM_QKB_PINLOC_5[29:0],PORT_MEM_QKB_PINLOC_4[29:0],PORT_MEM_QKB_PINLOC_3[29:0],PORT_MEM_QKB_PINLOC_2[29:0],PORT_MEM_QKB_PINLOC_1[29:0],PORT_MEM_QKB_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_N_PINLOC = {PORT_MEM_QKB_N_PINLOC_5[29:0],PORT_MEM_QKB_N_PINLOC_4[29:0],PORT_MEM_QKB_N_PINLOC_3[29:0],PORT_MEM_QKB_N_PINLOC_2[29:0],PORT_MEM_QKB_N_PINLOC_1[29:0],PORT_MEM_QKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_PINLOC = {PORT_MEM_CQ_PINLOC_1[29:0],PORT_MEM_CQ_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_N_PINLOC = {PORT_MEM_CQ_N_PINLOC_1[29:0],PORT_MEM_CQ_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ALERT_N_PINLOC = {PORT_MEM_ALERT_N_PINLOC_1[29:0],PORT_MEM_ALERT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PE_N_PINLOC = {PORT_MEM_PE_N_PINLOC_1[29:0],PORT_MEM_PE_N_PINLOC_0[29:0]}; + + localparam LANES_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE; + localparam PINS_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE; + + // Select which DBC to use as shadow for the primary HMC. + // We always pick "dbc1_to_local" as it's guaranteed to be used by the interface (as an A/C lane). + // The exception is for HPS mode - HPS is only connected to lane 3 of the HMC tile for the + // various Avalon control signals, therefore we must denote lane 3 as shadow. + localparam PRI_HMC_DBC_SHADOW_LANE_INDEX = IS_HPS ? 3 : 1; + + // The actual reset signal, selected from either the local signal or from master + logic global_reset_n_int; + + // The actual PLL ref clock signal, selected from either the local signal or from master + logic pll_ref_clk_int; + + // Reset Signals + logic phy_reset_n; // Reset signal from tile that is completely asynchronous + + // Signals for various clocks + logic pll_dll_clk; // PLL -> DLL output clock + logic [7:0] phy_clk_phs; // FR PHY clock signals (8 phases, 45-deg apart) + logic [1:0] phy_clk; // {phy_clk[1], phy_clk[0]} + logic phy_fb_clk_to_tile; // PHY feedback clock (to tile) + logic phy_fb_clk_to_pll; // PHY feedback clock (to PLL) + logic [8:0] pll_c_counters; // PLL C counter outputs + logic pll_extra_clk_diag_ok; // Internal test signal for PLL extra clocks + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + logic [1:0] core_clks_from_cpa_pri; + logic [1:0] core_clks_locked_cpa_pri; + logic [1:0] core_clks_fb_to_cpa_pri; + logic [1:0] core_clks_from_cpa_sec; + logic [1:0] core_clks_locked_cpa_sec; + logic [1:0] core_clks_fb_to_cpa_sec; + logic dcc_stable; + + // Avalon interfaces between core and HMC + logic [59:0] core2ctl_avl_0; + logic [59:0] core2ctl_avl_1; + logic core2ctl_avl_rd_data_ready_0; + logic core2ctl_avl_rd_data_ready_1; + logic ctl2core_avl_cmd_ready_0; + logic ctl2core_avl_cmd_ready_1; + logic [12:0] ctl2core_avl_rdata_id_0; + logic [12:0] ctl2core_avl_rdata_id_1; + logic core2l_wr_data_vld_ast_0; + logic core2l_wr_data_vld_ast_1; + logic core2l_rd_data_rdy_ast_0; + logic core2l_rd_data_rdy_ast_1; + + // Avalon interfaces between core and lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast; + + // ECC signals between core and lanes + logic [12:0] core2l_wr_ecc_info_0; + logic [12:0] core2l_wr_ecc_info_1; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc; + + // Signals between core and data lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat; + + // Wires for wire-luts + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] wl1_l2core_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] wl2_l2core_data; + + // AFI signals between tile and core + logic [16:0] c2t_afi; + logic [25:0] t2c_afi; + + // Side-band signals between core and HMC + logic [41:0] core2ctl_sideband_0; + logic [13:0] ctl2core_sideband_0; + logic [41:0] core2ctl_sideband_1; + logic [13:0] ctl2core_sideband_1; + + // MMR signals between core and HMC + logic [33:0] ctl2core_mmr_0; + logic [50:0] core2ctl_mmr_0; + logic [33:0] ctl2core_mmr_1; + logic [50:0] core2ctl_mmr_1; + + // Signals for connecting OCT block to I/O buffers + logic [OCT_CONTROL_WIDTH-1:0] oct_stc; // serial-termination-control + logic [OCT_CONTROL_WIDTH-1:0] oct_ptc; // parallel-termination-control + logic oct_cal_req; // OCT manual calibration request + logic oct_cal_rdy; // OCT manual calibration ready + logic oct_recal_req; // OCT manual calibration request + logic oct_s2pload_rdy; // OCT manual calibration load ready + logic oct_s2pload_ena; // OCT manual calibration load stall + + // Signals for connecting emif signals between lanes/tiles and I/O buffers + logic [PINS_IN_RTL_TILES-1:0] l2b_data; // lane-to-buffer data + logic [PINS_IN_RTL_TILES-1:0] l2b_oe; // lane-to-buffer output-enable + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc; // lane-to-buffer dynamic-termination-control + logic [PINS_IN_RTL_TILES-1:0] b2l_data; // buffer-to-lane data + logic [LANES_IN_RTL_TILES-1:0] b2t_dqs; // buffer-to-tile DQS + logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb; // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between io_aux and tiles + logic cal_bus_clk; + logic cal_bus_avl_read; + logic cal_bus_avl_write; + logic [19:0] cal_bus_avl_address; + logic [31:0] cal_bus_avl_read_data; + logic [31:0] cal_bus_avl_write_data; + + // Internal signal for cal_counter + logic afi_cal_in_progress; + + assign local_cal_success = afi_cal_success & pll_extra_clk_diag_ok; + assign local_cal_fail = afi_cal_fail; + + assign afi_mps_ack = 1'b0; + + wire runAbstractPhySim; + wire global_reset_n_int_io_aux_in; + wire cal_debug_reset_n_io_aux_in; + wire cal_slave_reset_n_in_io_aux_in; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALP"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_success ( + .probe (local_cal_success) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALF"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_fail ( + .probe (local_cal_fail) + ); +`endif + + //////////////////////////////////////////////////////////////////////////// + // PLL + //////////////////////////////////////////////////////////////////////////// + generate + // synthesis translate_off + if (DIAG_FAST_SIM) begin : gen_fast_sim + altera_emif_arch_nf_pll_fast_sim # ( + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (PLL_SIM_CAL_SLAVE_CLK_FREQ_PS), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (PLL_SIM_CAL_MASTER_CLK_FREQ_PS), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH) + ) pll_inst ( + .* + ); + end else begin : gen_normal + // synthesis translate_on + altera_emif_arch_nf_pll # ( + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + .PLL_BW_SEL (PLL_BW_SEL) + ) pll_inst ( + .* + ); + // synthesis translate_off + end + // synthesis translate_on + endgenerate + + altera_emif_arch_nf_pll_extra_clks # ( + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE) + ) pll_extra_clks_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // OCT Block + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_oct # ( + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .PLL_REF_CLK_FREQ_PS (PLL_REF_CLK_FREQ_PS), + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .IS_HPS (IS_HPS) + ) oct_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Output clock and reset signals + //////////////////////////////////////////////////////////////////////////// + generate + if (IS_HPS) begin : hps + altera_emif_arch_nf_hps_clks_rsts # ( + .IS_VID (IS_VID), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_HPS_ENABLE_EARLY_RELEASE (PHY_HPS_ENABLE_EARLY_RELEASE) + ) hps_clks_rsts_inst ( + .* + ); + end else begin : non_hps + altera_emif_arch_nf_core_clks_rsts # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .IS_VID (IS_VID), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH) + ) core_clks_rsts_inst ( + .* + ); + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // I/O Buffers + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_bufs # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .PINS_PER_LANE (PINS_PER_LANE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .UNUSED_MEM_PINS_PINLOC (UNUSED_MEM_PINS_PINLOC), + .UNUSED_DQS_BUSES_LANELOC (UNUSED_DQS_BUSES_LANELOC), + + // Assignment of port widths for "mem" interface + //AUTOGEN_BEGIN: Assignment of memory port widths + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + + // Assignment of parameters describing logical pin allocation + //AUTOGEN_BEGIN: Assignment of memory port pinlocs + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT) + ) bufs_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // I/O Aux + //////////////////////////////////////////////////////////////////////////// + ed_sim_ddr4a_altera_emif_arch_nf_170_kledjpy_io_aux # ( + .SILICON_REV (SILICON_REV), + .IS_HPS (IS_HPS), + .SEQ_CODE_HEX_FILENAME (SEQ_CODE_HEX_FILENAME), + .SEQ_SYNTH_OSC_FREQ_MHZ (SEQ_SYNTH_OSC_FREQ_MHZ), + .SEQ_SYNTH_PARAMS_HEX_FILENAME (SEQ_SYNTH_PARAMS_HEX_FILENAME), + .SEQ_SYNTH_CPU_CLK_DIVIDE (SEQ_SYNTH_CPU_CLK_DIVIDE), + .SEQ_SYNTH_CAL_CLK_DIVIDE (SEQ_SYNTH_CAL_CLK_DIVIDE), + .SEQ_SIM_OSC_FREQ_MHZ (SEQ_SIM_OSC_FREQ_MHZ), + .SEQ_SIM_PARAMS_HEX_FILENAME (SEQ_SIM_PARAMS_HEX_FILENAME), + .SEQ_SIM_CPU_CLK_DIVIDE (SEQ_SIM_CPU_CLK_DIVIDE), + .SEQ_SIM_CAL_CLK_DIVIDE (SEQ_SIM_CAL_CLK_DIVIDE), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_ECLIPSE_DEBUG (DIAG_ECLIPSE_DEBUG), + .DIAG_EXPORT_VJI (DIAG_EXPORT_VJI), + .DIAG_INTERFACE_ID (DIAG_INTERFACE_ID), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH), + .PORT_CAL_MASTER_ADDRESS_WIDTH (PORT_CAL_MASTER_ADDRESS_WIDTH), + .PORT_CAL_MASTER_BYTEEN_WIDTH (PORT_CAL_MASTER_BYTEEN_WIDTH), + .PORT_CAL_MASTER_RDATA_WIDTH (PORT_CAL_MASTER_RDATA_WIDTH), + .PORT_CAL_MASTER_WDATA_WIDTH (PORT_CAL_MASTER_WDATA_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (PORT_DFT_NF_IOAUX_PIO_IN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH) + ) io_aux_inst ( + .global_reset_n_int (global_reset_n_int_io_aux_in), + .cal_debug_reset_n (cal_debug_reset_n_io_aux_in), + .cal_slave_reset_n_in (cal_slave_reset_n_in_io_aux_in), + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Tiles and Lanes + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_io_tiles_wrap # ( + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .PINS_WDB (PINS_WDB), + .PINS_DB_IN_BYPASS (PINS_DB_IN_BYPASS), + .PINS_DB_OUT_BYPASS (PINS_DB_OUT_BYPASS), + .PINS_DB_OE_BYPASS (PINS_DB_OE_BYPASS), + .PINS_INVERT_WR (PINS_INVERT_WR), + .PINS_INVERT_OE (PINS_INVERT_OE), + .PINS_AC_HMC_DATA_OVERRIDE_ENA (PINS_AC_HMC_DATA_OVERRIDE_ENA), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_GPIO_MODE (PINS_GPIO_MODE), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL) + ) io_tiles_wrap_inst ( + .l2core_data (l2core_data), + .runAbstractPhySim (runAbstractPhySim), + .* + ); + + generate + if (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD == 0) + begin : nonabphy_connections + assign global_reset_n_int_io_aux_in = global_reset_n_int; + assign cal_debug_reset_n_io_aux_in = cal_debug_reset_n; + assign cal_slave_reset_n_in_io_aux_in = cal_slave_reset_n_in; + end + else begin : abphy_connections + assign global_reset_n_int_io_aux_in = runAbstractPhySim==0 ? global_reset_n_int : 'b0; + assign cal_debug_reset_n_io_aux_in = runAbstractPhySim==0 ? cal_debug_reset_n : 'b0; + assign cal_slave_reset_n_in_io_aux_in = runAbstractPhySim==0 ? cal_slave_reset_n_in : 'b0; + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // Expose sequencer interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_seq_if # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .REGISTER_AFI (REGISTER_AFI), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_HAS_DCC (PHY_HAS_DCC), + .IS_HPS (IS_HPS) + ) seq_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC signals from io_tiles as proper Avalon signals + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_avl_if # ( + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH) + ) hmc_avl_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC sideband interfaces + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_sideband_if # ( + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH) + ) hmc_sideband_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC MMR interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_mmr_if # ( + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH) + ) hmc_mmr_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Rewire and expose data signals + //////////////////////////////////////////////////////////////////////////// + generate + if (NUM_OF_HMC_PORTS == 0) + begin : afi + altera_emif_arch_nf_afi_if # ( + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .REGISTER_AFI (REGISTER_AFI), + + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .LANES_USAGE (LANES_USAGE), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN), + .PINS_INVERT_OE (PINS_INVERT_OE), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO) + ) if_inst ( + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + + end else + begin : hmc + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM") + begin : amm + + altera_emif_arch_nf_hmc_amm_data_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .* + ); + + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + end else + begin : hmc_ast + altera_emif_arch_nf_hmc_ast_data_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + end + + assign afi_rdata_dbi_n = '0; + assign afi_rdata_dinv = '0; + assign afi_rdata = '0; + assign afi_rdata_valid = '0; + assign afi_alert_n = '0; + assign afi_pe_n = '0; + assign core2l_rdata_en_full = '0; + assign core2l_mrnk_read = '0; + assign core2l_mrnk_write = '0; + end + endgenerate + + altera_emif_arch_nf_cal_counter + cal_counter_inst ( + .* + ); + + assign emif_to_hps = '0; + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy.v new file mode 100644 index 000000000000..489328800461 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy.v @@ -0,0 +1,179 @@ +// ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy.v + +// This file was auto-generated from altera_emif_cal_slave_nf_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_ddr4a_altera_emif_cal_slave_nf_170_6qfmevy ( + output wire avl_waitrequest, // avl.waitrequest + output wire [31:0] avl_readdata, // .readdata + output wire avl_readdatavalid, // .readdatavalid + input wire [0:0] avl_burstcount, // .burstcount + input wire [31:0] avl_writedata, // .writedata + input wire [15:0] avl_address, // .address + input wire avl_write, // .write + input wire avl_read, // .read + input wire [3:0] avl_byteenable, // .byteenable + input wire avl_debugaccess, // .debugaccess + input wire clk_clk, // clk.clk + input wire rst_reset // rst.reset + ); + + wire ioaux_master_bridge_m0_waitrequest; // mm_interconnect_0:ioaux_master_bridge_m0_waitrequest -> ioaux_master_bridge:m0_waitrequest + wire [31:0] ioaux_master_bridge_m0_readdata; // mm_interconnect_0:ioaux_master_bridge_m0_readdata -> ioaux_master_bridge:m0_readdata + wire ioaux_master_bridge_m0_debugaccess; // ioaux_master_bridge:m0_debugaccess -> mm_interconnect_0:ioaux_master_bridge_m0_debugaccess + wire [15:0] ioaux_master_bridge_m0_address; // ioaux_master_bridge:m0_address -> mm_interconnect_0:ioaux_master_bridge_m0_address + wire ioaux_master_bridge_m0_read; // ioaux_master_bridge:m0_read -> mm_interconnect_0:ioaux_master_bridge_m0_read + wire [3:0] ioaux_master_bridge_m0_byteenable; // ioaux_master_bridge:m0_byteenable -> mm_interconnect_0:ioaux_master_bridge_m0_byteenable + wire ioaux_master_bridge_m0_readdatavalid; // mm_interconnect_0:ioaux_master_bridge_m0_readdatavalid -> ioaux_master_bridge:m0_readdatavalid + wire [31:0] ioaux_master_bridge_m0_writedata; // ioaux_master_bridge:m0_writedata -> mm_interconnect_0:ioaux_master_bridge_m0_writedata + wire ioaux_master_bridge_m0_write; // ioaux_master_bridge:m0_write -> mm_interconnect_0:ioaux_master_bridge_m0_write + wire [0:0] ioaux_master_bridge_m0_burstcount; // ioaux_master_bridge:m0_burstcount -> mm_interconnect_0:ioaux_master_bridge_m0_burstcount + wire mm_interconnect_0_ioaux_soft_ram_s1_chipselect; // mm_interconnect_0:ioaux_soft_ram_s1_chipselect -> ioaux_soft_ram:chipselect + wire [31:0] mm_interconnect_0_ioaux_soft_ram_s1_readdata; // ioaux_soft_ram:readdata -> mm_interconnect_0:ioaux_soft_ram_s1_readdata + wire mm_interconnect_0_ioaux_soft_ram_s1_debugaccess; // mm_interconnect_0:ioaux_soft_ram_s1_debugaccess -> ioaux_soft_ram:debugaccess + wire [11:0] mm_interconnect_0_ioaux_soft_ram_s1_address; // mm_interconnect_0:ioaux_soft_ram_s1_address -> ioaux_soft_ram:address + wire [3:0] mm_interconnect_0_ioaux_soft_ram_s1_byteenable; // mm_interconnect_0:ioaux_soft_ram_s1_byteenable -> ioaux_soft_ram:byteenable + wire mm_interconnect_0_ioaux_soft_ram_s1_write; // mm_interconnect_0:ioaux_soft_ram_s1_write -> ioaux_soft_ram:write + wire [31:0] mm_interconnect_0_ioaux_soft_ram_s1_writedata; // mm_interconnect_0:ioaux_soft_ram_s1_writedata -> ioaux_soft_ram:writedata + wire mm_interconnect_0_ioaux_soft_ram_s1_clken; // mm_interconnect_0:ioaux_soft_ram_s1_clken -> ioaux_soft_ram:clken + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [ioaux_master_bridge:reset, ioaux_soft_ram:reset, mm_interconnect_0:ioaux_master_bridge_reset_reset_bridge_in_reset_reset] + + altera_avalon_mm_bridge #( + .DATA_WIDTH (32), + .SYMBOL_WIDTH (8), + .HDL_ADDR_WIDTH (16), + .BURSTCOUNT_WIDTH (1), + .PIPELINE_COMMAND (1), + .PIPELINE_RESPONSE (1) + ) ioaux_master_bridge ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .s0_waitrequest (avl_waitrequest), // s0.waitrequest + .s0_readdata (avl_readdata), // .readdata + .s0_readdatavalid (avl_readdatavalid), // .readdatavalid + .s0_burstcount (avl_burstcount), // .burstcount + .s0_writedata (avl_writedata), // .writedata + .s0_address (avl_address), // .address + .s0_write (avl_write), // .write + .s0_read (avl_read), // .read + .s0_byteenable (avl_byteenable), // .byteenable + .s0_debugaccess (avl_debugaccess), // .debugaccess + .m0_waitrequest (ioaux_master_bridge_m0_waitrequest), // m0.waitrequest + .m0_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .m0_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .m0_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .m0_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .m0_address (ioaux_master_bridge_m0_address), // .address + .m0_write (ioaux_master_bridge_m0_write), // .write + .m0_read (ioaux_master_bridge_m0_read), // .read + .m0_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .m0_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .s0_response (), // (terminated) + .m0_response (2'b00) // (terminated) + ); + + ed_sim_ddr4a_altera_avalon_onchip_memory2_170_yroldmy ioaux_soft_ram ( + .clk (clk_clk), // clk1.clk + .address (mm_interconnect_0_ioaux_soft_ram_s1_address), // s1.address + .debugaccess (mm_interconnect_0_ioaux_soft_ram_s1_debugaccess), // .debugaccess + .clken (mm_interconnect_0_ioaux_soft_ram_s1_clken), // .clken + .chipselect (mm_interconnect_0_ioaux_soft_ram_s1_chipselect), // .chipselect + .write (mm_interconnect_0_ioaux_soft_ram_s1_write), // .write + .readdata (mm_interconnect_0_ioaux_soft_ram_s1_readdata), // .readdata + .writedata (mm_interconnect_0_ioaux_soft_ram_s1_writedata), // .writedata + .byteenable (mm_interconnect_0_ioaux_soft_ram_s1_byteenable), // .byteenable + .reset (rst_controller_reset_out_reset), // reset1.reset + .reset_req (1'b0), // (terminated) + .freeze (1'b0) // (terminated) + ); + + ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki mm_interconnect_0 ( + .clk_bridge_out_clk_clk (clk_clk), // clk_bridge_out_clk.clk + .ioaux_master_bridge_m0_address (ioaux_master_bridge_m0_address), // ioaux_master_bridge_m0.address + .ioaux_master_bridge_m0_waitrequest (ioaux_master_bridge_m0_waitrequest), // .waitrequest + .ioaux_master_bridge_m0_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .ioaux_master_bridge_m0_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .ioaux_master_bridge_m0_read (ioaux_master_bridge_m0_read), // .read + .ioaux_master_bridge_m0_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .ioaux_master_bridge_m0_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .ioaux_master_bridge_m0_write (ioaux_master_bridge_m0_write), // .write + .ioaux_master_bridge_m0_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .ioaux_master_bridge_m0_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .ioaux_master_bridge_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // ioaux_master_bridge_reset_reset_bridge_in_reset.reset + .ioaux_soft_ram_s1_address (mm_interconnect_0_ioaux_soft_ram_s1_address), // ioaux_soft_ram_s1.address + .ioaux_soft_ram_s1_write (mm_interconnect_0_ioaux_soft_ram_s1_write), // .write + .ioaux_soft_ram_s1_readdata (mm_interconnect_0_ioaux_soft_ram_s1_readdata), // .readdata + .ioaux_soft_ram_s1_writedata (mm_interconnect_0_ioaux_soft_ram_s1_writedata), // .writedata + .ioaux_soft_ram_s1_byteenable (mm_interconnect_0_ioaux_soft_ram_s1_byteenable), // .byteenable + .ioaux_soft_ram_s1_chipselect (mm_interconnect_0_ioaux_soft_ram_s1_chipselect), // .chipselect + .ioaux_soft_ram_s1_clken (mm_interconnect_0_ioaux_soft_ram_s1_clken), // .clken + .ioaux_soft_ram_s1_debugaccess (mm_interconnect_0_ioaux_soft_ram_s1_debugaccess) // .debugaccess + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (1), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (0), + .RESET_REQ_WAIT_TIME (1), + .MIN_RST_ASSERTION_TIME (3), + .RESET_REQ_EARLY_DSRT_TIME (1), + .USE_RESET_REQUEST_IN0 (0), + .USE_RESET_REQUEST_IN1 (0), + .USE_RESET_REQUEST_IN2 (0), + .USE_RESET_REQUEST_IN3 (0), + .USE_RESET_REQUEST_IN4 (0), + .USE_RESET_REQUEST_IN5 (0), + .USE_RESET_REQUEST_IN6 (0), + .USE_RESET_REQUEST_IN7 (0), + .USE_RESET_REQUEST_IN8 (0), + .USE_RESET_REQUEST_IN9 (0), + .USE_RESET_REQUEST_IN10 (0), + .USE_RESET_REQUEST_IN11 (0), + .USE_RESET_REQUEST_IN12 (0), + .USE_RESET_REQUEST_IN13 (0), + .USE_RESET_REQUEST_IN14 (0), + .USE_RESET_REQUEST_IN15 (0), + .ADAPT_RESET_REQUEST (0) + ) rst_controller ( + .reset_in0 (rst_reset), // reset_in0.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (), // (terminated) + .reset_req_in0 (1'b0), // (terminated) + .reset_in1 (1'b0), // (terminated) + .reset_req_in1 (1'b0), // (terminated) + .reset_in2 (1'b0), // (terminated) + .reset_req_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_req_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_req_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_req_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_req_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_req_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_req_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_req_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_req_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_req_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_req_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_req_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_req_in14 (1'b0), // (terminated) + .reset_in15 (1'b0), // (terminated) + .reset_req_in15 (1'b0) // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki.v new file mode 100644 index 000000000000..36d2ff6a39e1 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki.v @@ -0,0 +1,168 @@ +// ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki.v + +// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_ddr4a_altera_mm_interconnect_170_o2ys4ki ( + input wire clk_bridge_out_clk_clk, // clk_bridge_out_clk.clk + input wire [15:0] ioaux_master_bridge_m0_address, // ioaux_master_bridge_m0.address + output wire ioaux_master_bridge_m0_waitrequest, // .waitrequest + input wire [0:0] ioaux_master_bridge_m0_burstcount, // .burstcount + input wire [3:0] ioaux_master_bridge_m0_byteenable, // .byteenable + input wire ioaux_master_bridge_m0_read, // .read + output wire [31:0] ioaux_master_bridge_m0_readdata, // .readdata + output wire ioaux_master_bridge_m0_readdatavalid, // .readdatavalid + input wire ioaux_master_bridge_m0_write, // .write + input wire [31:0] ioaux_master_bridge_m0_writedata, // .writedata + input wire ioaux_master_bridge_m0_debugaccess, // .debugaccess + input wire ioaux_master_bridge_reset_reset_bridge_in_reset_reset, // ioaux_master_bridge_reset_reset_bridge_in_reset.reset + output wire [11:0] ioaux_soft_ram_s1_address, // ioaux_soft_ram_s1.address + output wire ioaux_soft_ram_s1_write, // .write + input wire [31:0] ioaux_soft_ram_s1_readdata, // .readdata + output wire [31:0] ioaux_soft_ram_s1_writedata, // .writedata + output wire [3:0] ioaux_soft_ram_s1_byteenable, // .byteenable + output wire ioaux_soft_ram_s1_chipselect, // .chipselect + output wire ioaux_soft_ram_s1_clken, // .clken + output wire ioaux_soft_ram_s1_debugaccess // .debugaccess + ); + + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest; // ioaux_soft_ram_s1_translator:uav_waitrequest -> ioaux_master_bridge_m0_translator:uav_waitrequest + wire [31:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata; // ioaux_soft_ram_s1_translator:uav_readdata -> ioaux_master_bridge_m0_translator:uav_readdata + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess; // ioaux_master_bridge_m0_translator:uav_debugaccess -> ioaux_soft_ram_s1_translator:uav_debugaccess + wire [15:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_address; // ioaux_master_bridge_m0_translator:uav_address -> ioaux_soft_ram_s1_translator:uav_address + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_read; // ioaux_master_bridge_m0_translator:uav_read -> ioaux_soft_ram_s1_translator:uav_read + wire [3:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable; // ioaux_master_bridge_m0_translator:uav_byteenable -> ioaux_soft_ram_s1_translator:uav_byteenable + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // ioaux_soft_ram_s1_translator:uav_readdatavalid -> ioaux_master_bridge_m0_translator:uav_readdatavalid + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock; // ioaux_master_bridge_m0_translator:uav_lock -> ioaux_soft_ram_s1_translator:uav_lock + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_write; // ioaux_master_bridge_m0_translator:uav_write -> ioaux_soft_ram_s1_translator:uav_write + wire [31:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata; // ioaux_master_bridge_m0_translator:uav_writedata -> ioaux_soft_ram_s1_translator:uav_writedata + wire [2:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount; // ioaux_master_bridge_m0_translator:uav_burstcount -> ioaux_soft_ram_s1_translator:uav_burstcount + + altera_merlin_master_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (16), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (1), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) ioaux_master_bridge_m0_translator ( + .clk (clk_bridge_out_clk_clk), // clk.clk + .reset (ioaux_master_bridge_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (ioaux_master_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (ioaux_master_bridge_m0_translator_avalon_universal_master_0_read), // .read + .uav_write (ioaux_master_bridge_m0_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (ioaux_master_bridge_m0_address), // avalon_anti_master_0.address + .av_waitrequest (ioaux_master_bridge_m0_waitrequest), // .waitrequest + .av_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .av_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .av_read (ioaux_master_bridge_m0_read), // .read + .av_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .av_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .av_write (ioaux_master_bridge_m0_write), // .write + .av_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .av_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (12), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (16), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) ioaux_soft_ram_s1_translator ( + .clk (clk_bridge_out_clk_clk), // clk.clk + .reset (ioaux_master_bridge_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (ioaux_master_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address + .uav_burstcount (ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (ioaux_master_bridge_m0_translator_avalon_universal_master_0_read), // .read + .uav_write (ioaux_master_bridge_m0_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (ioaux_soft_ram_s1_address), // avalon_anti_slave_0.address + .av_write (ioaux_soft_ram_s1_write), // .write + .av_readdata (ioaux_soft_ram_s1_readdata), // .readdata + .av_writedata (ioaux_soft_ram_s1_writedata), // .writedata + .av_byteenable (ioaux_soft_ram_s1_byteenable), // .byteenable + .av_chipselect (ioaux_soft_ram_s1_chipselect), // .chipselect + .av_clken (ioaux_soft_ram_s1_clken), // .clken + .av_debugaccess (ioaux_soft_ram_s1_debugaccess), // .debugaccess + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1.v new file mode 100644 index 000000000000..65b0a64265ac --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1.v @@ -0,0 +1,74 @@ +// ed_sim_emif_slave_1.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_emif_slave_1 ( + input wire [31:0] clks_sharing_slave_in, // clks_sharing_slave_in.clks_sharing + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n + input wire amm_read_0, // .read + input wire amm_write_0, // .write + input wire [25:0] amm_address_0, // .address + output wire [511:0] amm_readdata_0, // .readdata + input wire [511:0] amm_writedata_0, // .writedata + input wire [6:0] amm_burstcount_0, // .burstcount + input wire [63:0] amm_byteenable_0, // .byteenable + output wire amm_readdatavalid_0, // .readdatavalid + output wire emif_usr_clk, // emif_usr_clk.clk + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n + output wire [0:0] mem_ck, // mem.mem_ck + output wire [0:0] mem_ck_n, // .mem_ck_n + output wire [16:0] mem_a, // .mem_a + output wire [0:0] mem_act_n, // .mem_act_n + output wire [1:0] mem_ba, // .mem_ba + output wire [1:0] mem_bg, // .mem_bg + output wire [0:0] mem_cke, // .mem_cke + output wire [0:0] mem_cs_n, // .mem_cs_n + output wire [0:0] mem_odt, // .mem_odt + output wire [0:0] mem_reset_n, // .mem_reset_n + output wire [0:0] mem_par, // .mem_par + input wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n, // .mem_dbi_n + input wire oct_rzqin, // oct.oct_rzqin + output wire local_cal_success, // status.local_cal_success + output wire local_cal_fail // .local_cal_fail + ); + + ed_sim_emif_slave_1_altera_emif_170_elx56cq emif_slave_1 ( + .clks_sharing_slave_in (clks_sharing_slave_in), // clks_sharing_slave_in.clks_sharing + .amm_ready_0 (amm_ready_0), // ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // .read + .amm_write_0 (amm_write_0), // .write + .amm_address_0 (amm_address_0), // .address + .amm_readdata_0 (amm_readdata_0), // .readdata + .amm_writedata_0 (amm_writedata_0), // .writedata + .amm_burstcount_0 (amm_burstcount_0), // .burstcount + .amm_byteenable_0 (amm_byteenable_0), // .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0), // .readdatavalid + .emif_usr_clk (emif_usr_clk), // emif_usr_clk.clk + .emif_usr_reset_n (emif_usr_reset_n), // emif_usr_reset_n.reset_n + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .oct_rzqin (oct_rzqin), // oct.oct_rzqin + .local_cal_success (local_cal_success), // status.local_cal_success + .local_cal_fail (local_cal_fail) // .local_cal_fail + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_avalon_onchip_memory2_170_yroldmy.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_avalon_onchip_memory2_170_yroldmy.v new file mode 100644 index 000000000000..3fccc173c4d5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_avalon_onchip_memory2_170_yroldmy.v @@ -0,0 +1,105 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788 + +module ed_sim_emif_slave_1_altera_avalon_onchip_memory2_170_yroldmy ( + // inputs: + address, + byteenable, + chipselect, + clk, + clken, + debugaccess, + freeze, + reset, + reset_req, + write, + writedata, + + // outputs: + readdata + ) +; + + parameter INIT_FILE = "seq_cal_soft_m20k.hex"; + + + output [ 31: 0] readdata; + input [ 11: 0] address; + input [ 3: 0] byteenable; + input chipselect; + input clk; + input clken; + input debugaccess; + input freeze; + input reset; + input reset_req; + input write; + input [ 31: 0] writedata; + + +wire clocken0; +wire [ 31: 0] readdata; +wire wren; + assign wren = chipselect & write & debugaccess; + assign clocken0 = clken & ~reset_req; + altsyncram the_altsyncram + ( + .address_a (address), + .byteena_a (byteenable), + .clock0 (clk), + .clocken0 (clocken0), + .data_a (writedata), + .q_a (readdata), + .wren_a (wren) + ); + + defparam the_altsyncram.byte_size = 8, + the_altsyncram.init_file = INIT_FILE, + the_altsyncram.lpm_type = "altsyncram", + the_altsyncram.maximum_depth = 4096, + the_altsyncram.numwords_a = 4096, + the_altsyncram.operation_mode = "SINGLE_PORT", + the_altsyncram.outdata_reg_a = "UNREGISTERED", + the_altsyncram.ram_block_type = "AUTO", + the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", + the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", + the_altsyncram.width_a = 32, + the_altsyncram.width_byteena_a = 4, + the_altsyncram.widthad_a = 12; + + //s1, which is an e_avalon_slave + //s2, which is an e_avalon_slave + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_170_elx56cq.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_170_elx56cq.v new file mode 100644 index 000000000000..876e4ae3d539 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_170_elx56cq.v @@ -0,0 +1,1855 @@ +// ed_sim_emif_slave_1_altera_emif_170_elx56cq.v + +// This file was auto-generated from altera_emif_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_emif_slave_1_altera_emif_170_elx56cq ( + input wire [31:0] clks_sharing_slave_in, // clks_sharing_slave_in.clks_sharing + output wire amm_ready_0, // ctrl_amm_0.waitrequest_n + input wire amm_read_0, // .read + input wire amm_write_0, // .write + input wire [25:0] amm_address_0, // .address + output wire [511:0] amm_readdata_0, // .readdata + input wire [511:0] amm_writedata_0, // .writedata + input wire [6:0] amm_burstcount_0, // .burstcount + input wire [63:0] amm_byteenable_0, // .byteenable + output wire amm_readdatavalid_0, // .readdatavalid + output wire emif_usr_clk, // emif_usr_clk.clk + output wire emif_usr_reset_n, // emif_usr_reset_n.reset_n + output wire [0:0] mem_ck, // mem.mem_ck + output wire [0:0] mem_ck_n, // .mem_ck_n + output wire [16:0] mem_a, // .mem_a + output wire [0:0] mem_act_n, // .mem_act_n + output wire [1:0] mem_ba, // .mem_ba + output wire [1:0] mem_bg, // .mem_bg + output wire [0:0] mem_cke, // .mem_cke + output wire [0:0] mem_cs_n, // .mem_cs_n + output wire [0:0] mem_odt, // .mem_odt + output wire [0:0] mem_reset_n, // .mem_reset_n + output wire [0:0] mem_par, // .mem_par + input wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n, // .mem_dbi_n + input wire oct_rzqin, // oct.oct_rzqin + output wire local_cal_success, // status.local_cal_success + output wire local_cal_fail // .local_cal_fail + ); + + wire arch_cal_slave_clk_clk; // arch:cal_slave_clk -> [arch:cal_slave_clk_in, cal_slave_component:clk_clk] + wire arch_cal_slave_reset_n_reset; // arch:cal_slave_reset_n -> [arch:cal_slave_reset_n_in, cal_slave_component:rst_reset] + wire arch_cal_master_waitrequest; // cal_slave_component:avl_waitrequest -> arch:cal_master_waitrequest + wire [31:0] arch_cal_master_readdata; // cal_slave_component:avl_readdata -> arch:cal_master_read_data + wire arch_cal_master_debugaccess; // arch:cal_master_debugaccess -> cal_slave_component:avl_debugaccess + wire arch_cal_master_read; // arch:cal_master_read -> cal_slave_component:avl_read + wire [15:0] arch_cal_master_address; // arch:cal_master_addr -> cal_slave_component:avl_address + wire [3:0] arch_cal_master_byteenable; // arch:cal_master_byteenable -> cal_slave_component:avl_byteenable + wire arch_cal_master_readdatavalid; // cal_slave_component:avl_readdatavalid -> arch:cal_master_read_data_valid + wire arch_cal_master_write; // arch:cal_master_write -> cal_slave_component:avl_write + wire [31:0] arch_cal_master_writedata; // arch:cal_master_write_data -> cal_slave_component:avl_writedata + wire arch_cal_master_burstcount; // arch:cal_master_burstcount -> cal_slave_component:avl_burstcount + + ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa #( + .PROTOCOL_ENUM ("PROTOCOL_DDR4"), + .PHY_TARGET_IS_ES (0), + .PHY_TARGET_IS_ES2 (0), + .PHY_TARGET_IS_PRODUCTION (1), + .PHY_CONFIG_ENUM ("CONFIG_PHY_AND_HARD_CTRL"), + .PHY_PING_PONG_EN (0), + .PHY_CORE_CLKS_SHARING_ENUM ("CORE_CLKS_SHARING_SLAVE"), + .PHY_CALIBRATED_OCT (1), + .PHY_AC_CALIBRATED_OCT (0), + .PHY_CK_CALIBRATED_OCT (1), + .PHY_DATA_CALIBRATED_OCT (1), + .PHY_HPS_ENABLE_EARLY_RELEASE (0), + .PLL_NUM_OF_EXTRA_CLKS (0), + .MEM_FORMAT_ENUM ("MEM_FORMAT_DISCRETE"), + .MEM_BURST_LENGTH (8), + .MEM_DATA_MASK_EN (1), + .MEM_TTL_DATA_WIDTH (64), + .MEM_TTL_NUM_OF_READ_GROUPS (8), + .MEM_TTL_NUM_OF_WRITE_GROUPS (8), + .DIAG_SIM_REGTEST_MODE (0), + .DIAG_SYNTH_FOR_SIM (0), + .DIAG_VERBOSE_IOAUX (0), + .DIAG_ECLIPSE_DEBUG (0), + .DIAG_EXPORT_VJI (0), + .DIAG_INTERFACE_ID (0), + .DIAG_FAST_SIM (1), + .DIAG_USE_ABSTRACT_PHY (1), + .SILICON_REV ("20nm5"), + .IS_HPS (0), + .IS_VID (0), + .USER_CLK_RATIO (4), + .C2P_P2C_CLK_RATIO (4), + .PHY_HMC_CLK_RATIO (2), + .DIAG_ABSTRACT_PHY_WLAT (5), + .DIAG_ABSTRACT_PHY_RLAT (18), + .DIAG_CPA_OUT_1_EN (0), + .DIAG_USE_CPA_LOCK (0), + .DQS_BUS_MODE_ENUM ("DQS_BUS_MODE_X8_X9"), + .AC_PIN_MAP_SCHEME ("use_0_1_2_lane"), + .NUM_OF_HMC_PORTS (1), + .HMC_AVL_PROTOCOL_ENUM ("CTRL_AVL_PROTOCOL_MM"), + .HMC_CTRL_DIMM_TYPE ("component"), + .REGISTER_AFI (1), + .SEQ_SYNTH_CPU_CLK_DIVIDE (2), + .SEQ_SYNTH_CAL_CLK_DIVIDE (8), + .SEQ_SIM_CPU_CLK_DIVIDE (1), + .SEQ_SIM_CAL_CLK_DIVIDE (32), + .SEQ_SYNTH_OSC_FREQ_MHZ (450), + .SEQ_SIM_OSC_FREQ_MHZ (2123), + .NUM_OF_RTL_TILES (3), + .PRI_RDATA_TILE_INDEX (1), + .PRI_RDATA_LANE_INDEX (3), + .PRI_WDATA_TILE_INDEX (1), + .PRI_WDATA_LANE_INDEX (3), + .PRI_AC_TILE_INDEX (1), + .SEC_RDATA_TILE_INDEX (1), + .SEC_RDATA_LANE_INDEX (3), + .SEC_WDATA_TILE_INDEX (1), + .SEC_WDATA_LANE_INDEX (3), + .SEC_AC_TILE_INDEX (1), + .LANES_USAGE_0 (765762413), + .LANES_USAGE_1 (5), + .LANES_USAGE_2 (0), + .LANES_USAGE_3 (0), + .LANES_USAGE_AUTOGEN_WCNT (4), + .PINS_USAGE_0 (1056960511), + .PINS_USAGE_1 (763363263), + .PINS_USAGE_2 (1055887359), + .PINS_USAGE_3 (1073479615), + .PINS_USAGE_4 (4094), + .PINS_USAGE_5 (0), + .PINS_USAGE_6 (0), + .PINS_USAGE_7 (0), + .PINS_USAGE_8 (0), + .PINS_USAGE_9 (0), + .PINS_USAGE_10 (0), + .PINS_USAGE_11 (0), + .PINS_USAGE_12 (0), + .PINS_USAGE_AUTOGEN_WCNT (13), + .PINS_RATE_0 (1), + .PINS_RATE_1 (561774592), + .PINS_RATE_2 (15699967), + .PINS_RATE_3 (0), + .PINS_RATE_4 (0), + .PINS_RATE_5 (0), + .PINS_RATE_6 (0), + .PINS_RATE_7 (0), + .PINS_RATE_8 (0), + .PINS_RATE_9 (0), + .PINS_RATE_10 (0), + .PINS_RATE_11 (0), + .PINS_RATE_12 (0), + .PINS_RATE_AUTOGEN_WCNT (13), + .PINS_WDB_0 (920202678), + .PINS_WDB_1 (910912566), + .PINS_WDB_2 (316345782), + .PINS_WDB_3 (918777270), + .PINS_WDB_4 (165375378), + .PINS_WDB_5 (136581193), + .PINS_WDB_6 (153391689), + .PINS_WDB_7 (153387017), + .PINS_WDB_8 (316342856), + .PINS_WDB_9 (918777270), + .PINS_WDB_10 (819686802), + .PINS_WDB_11 (920347830), + .PINS_WDB_12 (920202672), + .PINS_WDB_13 (54), + .PINS_WDB_14 (0), + .PINS_WDB_15 (0), + .PINS_WDB_16 (0), + .PINS_WDB_17 (0), + .PINS_WDB_18 (0), + .PINS_WDB_19 (0), + .PINS_WDB_20 (0), + .PINS_WDB_21 (0), + .PINS_WDB_22 (0), + .PINS_WDB_23 (0), + .PINS_WDB_24 (0), + .PINS_WDB_25 (0), + .PINS_WDB_26 (0), + .PINS_WDB_27 (0), + .PINS_WDB_28 (0), + .PINS_WDB_29 (0), + .PINS_WDB_30 (0), + .PINS_WDB_31 (0), + .PINS_WDB_32 (0), + .PINS_WDB_33 (0), + .PINS_WDB_34 (0), + .PINS_WDB_35 (0), + .PINS_WDB_36 (0), + .PINS_WDB_37 (0), + .PINS_WDB_38 (0), + .PINS_WDB_AUTOGEN_WCNT (39), + .PINS_DATA_IN_MODE_0 (153612873), + .PINS_DATA_IN_MODE_1 (167547401), + .PINS_DATA_IN_MODE_2 (1059357257), + .PINS_DATA_IN_MODE_3 (153129545), + .PINS_DATA_IN_MODE_4 (153391743), + .PINS_DATA_IN_MODE_5 (150736969), + .PINS_DATA_IN_MODE_6 (153391689), + .PINS_DATA_IN_MODE_7 (153387017), + .PINS_DATA_IN_MODE_8 (1059357256), + .PINS_DATA_IN_MODE_9 (153129545), + .PINS_DATA_IN_MODE_10 (136614527), + .PINS_DATA_IN_MODE_11 (153395145), + .PINS_DATA_IN_MODE_12 (153612872), + .PINS_DATA_IN_MODE_13 (9), + .PINS_DATA_IN_MODE_14 (0), + .PINS_DATA_IN_MODE_15 (0), + .PINS_DATA_IN_MODE_16 (0), + .PINS_DATA_IN_MODE_17 (0), + .PINS_DATA_IN_MODE_18 (0), + .PINS_DATA_IN_MODE_19 (0), + .PINS_DATA_IN_MODE_20 (0), + .PINS_DATA_IN_MODE_21 (0), + .PINS_DATA_IN_MODE_22 (0), + .PINS_DATA_IN_MODE_23 (0), + .PINS_DATA_IN_MODE_24 (0), + .PINS_DATA_IN_MODE_25 (0), + .PINS_DATA_IN_MODE_26 (0), + .PINS_DATA_IN_MODE_27 (0), + .PINS_DATA_IN_MODE_28 (0), + .PINS_DATA_IN_MODE_29 (0), + .PINS_DATA_IN_MODE_30 (0), + .PINS_DATA_IN_MODE_31 (0), + .PINS_DATA_IN_MODE_32 (0), + .PINS_DATA_IN_MODE_33 (0), + .PINS_DATA_IN_MODE_34 (0), + .PINS_DATA_IN_MODE_35 (0), + .PINS_DATA_IN_MODE_36 (0), + .PINS_DATA_IN_MODE_37 (0), + .PINS_DATA_IN_MODE_38 (0), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (39), + .PINS_C2L_DRIVEN_0 (251457486), + .PINS_C2L_DRIVEN_1 (259007), + .PINS_C2L_DRIVEN_2 (234881024), + .PINS_C2L_DRIVEN_3 (1060893631), + .PINS_C2L_DRIVEN_4 (4046), + .PINS_C2L_DRIVEN_5 (0), + .PINS_C2L_DRIVEN_6 (0), + .PINS_C2L_DRIVEN_7 (0), + .PINS_C2L_DRIVEN_8 (0), + .PINS_C2L_DRIVEN_9 (0), + .PINS_C2L_DRIVEN_10 (0), + .PINS_C2L_DRIVEN_11 (0), + .PINS_C2L_DRIVEN_12 (0), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (13), + .PINS_DB_IN_BYPASS_0 (1), + .PINS_DB_IN_BYPASS_1 (763101184), + .PINS_DB_IN_BYPASS_2 (15699967), + .PINS_DB_IN_BYPASS_3 (0), + .PINS_DB_IN_BYPASS_4 (0), + .PINS_DB_IN_BYPASS_5 (0), + .PINS_DB_IN_BYPASS_6 (0), + .PINS_DB_IN_BYPASS_7 (0), + .PINS_DB_IN_BYPASS_8 (0), + .PINS_DB_IN_BYPASS_9 (0), + .PINS_DB_IN_BYPASS_10 (0), + .PINS_DB_IN_BYPASS_11 (0), + .PINS_DB_IN_BYPASS_12 (0), + .PINS_DB_IN_BYPASS_AUTOGEN_WCNT (13), + .PINS_DB_OUT_BYPASS_0 (1), + .PINS_DB_OUT_BYPASS_1 (763101184), + .PINS_DB_OUT_BYPASS_2 (15699967), + .PINS_DB_OUT_BYPASS_3 (0), + .PINS_DB_OUT_BYPASS_4 (0), + .PINS_DB_OUT_BYPASS_5 (0), + .PINS_DB_OUT_BYPASS_6 (0), + .PINS_DB_OUT_BYPASS_7 (0), + .PINS_DB_OUT_BYPASS_8 (0), + .PINS_DB_OUT_BYPASS_9 (0), + .PINS_DB_OUT_BYPASS_10 (0), + .PINS_DB_OUT_BYPASS_11 (0), + .PINS_DB_OUT_BYPASS_12 (0), + .PINS_DB_OUT_BYPASS_AUTOGEN_WCNT (13), + .PINS_DB_OE_BYPASS_0 (1), + .PINS_DB_OE_BYPASS_1 (763101184), + .PINS_DB_OE_BYPASS_2 (15699967), + .PINS_DB_OE_BYPASS_3 (0), + .PINS_DB_OE_BYPASS_4 (0), + .PINS_DB_OE_BYPASS_5 (0), + .PINS_DB_OE_BYPASS_6 (0), + .PINS_DB_OE_BYPASS_7 (0), + .PINS_DB_OE_BYPASS_8 (0), + .PINS_DB_OE_BYPASS_9 (0), + .PINS_DB_OE_BYPASS_10 (0), + .PINS_DB_OE_BYPASS_11 (0), + .PINS_DB_OE_BYPASS_12 (0), + .PINS_DB_OE_BYPASS_AUTOGEN_WCNT (13), + .PINS_INVERT_WR_0 (537002016), + .PINS_INVERT_WR_1 (2048), + .PINS_INVERT_WR_2 (536870912), + .PINS_INVERT_WR_3 (8390656), + .PINS_INVERT_WR_4 (32), + .PINS_INVERT_WR_5 (0), + .PINS_INVERT_WR_6 (0), + .PINS_INVERT_WR_7 (0), + .PINS_INVERT_WR_8 (0), + .PINS_INVERT_WR_9 (0), + .PINS_INVERT_WR_10 (0), + .PINS_INVERT_WR_11 (0), + .PINS_INVERT_WR_12 (0), + .PINS_INVERT_WR_AUTOGEN_WCNT (13), + .PINS_INVERT_OE_0 (1056960510), + .PINS_INVERT_OE_1 (763363263), + .PINS_INVERT_OE_2 (1055887359), + .PINS_INVERT_OE_3 (1073479615), + .PINS_INVERT_OE_4 (4094), + .PINS_INVERT_OE_5 (0), + .PINS_INVERT_OE_6 (0), + .PINS_INVERT_OE_7 (0), + .PINS_INVERT_OE_8 (0), + .PINS_INVERT_OE_9 (0), + .PINS_INVERT_OE_10 (0), + .PINS_INVERT_OE_11 (0), + .PINS_INVERT_OE_12 (0), + .PINS_INVERT_OE_AUTOGEN_WCNT (13), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_0 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_1 (201326592), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_2 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_3 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_4 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_5 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_6 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_7 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_8 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_9 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_10 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_11 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_12 (0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT (13), + .PINS_OCT_MODE_0 (1056960510), + .PINS_OCT_MODE_1 (262079), + .PINS_OCT_MODE_2 (1040187392), + .PINS_OCT_MODE_3 (1073479615), + .PINS_OCT_MODE_4 (4094), + .PINS_OCT_MODE_5 (0), + .PINS_OCT_MODE_6 (0), + .PINS_OCT_MODE_7 (0), + .PINS_OCT_MODE_8 (0), + .PINS_OCT_MODE_9 (0), + .PINS_OCT_MODE_10 (0), + .PINS_OCT_MODE_11 (0), + .PINS_OCT_MODE_12 (0), + .PINS_OCT_MODE_AUTOGEN_WCNT (13), + .PINS_GPIO_MODE_0 (1), + .PINS_GPIO_MODE_1 (0), + .PINS_GPIO_MODE_2 (0), + .PINS_GPIO_MODE_3 (0), + .PINS_GPIO_MODE_4 (0), + .PINS_GPIO_MODE_5 (0), + .PINS_GPIO_MODE_6 (0), + .PINS_GPIO_MODE_7 (0), + .PINS_GPIO_MODE_8 (0), + .PINS_GPIO_MODE_9 (0), + .PINS_GPIO_MODE_10 (0), + .PINS_GPIO_MODE_11 (0), + .PINS_GPIO_MODE_12 (0), + .PINS_GPIO_MODE_AUTOGEN_WCNT (13), + .UNUSED_MEM_PINS_PINLOC_0 (149044250), + .UNUSED_MEM_PINS_PINLOC_1 (145895565), + .UNUSED_MEM_PINS_PINLOC_2 (142746762), + .UNUSED_MEM_PINS_PINLOC_3 (139597959), + .UNUSED_MEM_PINS_PINLOC_4 (113369220), + .UNUSED_MEM_PINS_PINLOC_5 (83972192), + .UNUSED_MEM_PINS_PINLOC_6 (75572298), + .UNUSED_MEM_PINS_PINLOC_7 (55630906), + .UNUSED_MEM_PINS_PINLOC_8 (12607524), + .UNUSED_MEM_PINS_PINLOC_9 (0), + .UNUSED_MEM_PINS_PINLOC_10 (0), + .UNUSED_MEM_PINS_PINLOC_11 (0), + .UNUSED_MEM_PINS_PINLOC_12 (0), + .UNUSED_MEM_PINS_PINLOC_13 (0), + .UNUSED_MEM_PINS_PINLOC_14 (0), + .UNUSED_MEM_PINS_PINLOC_15 (0), + .UNUSED_MEM_PINS_PINLOC_16 (0), + .UNUSED_MEM_PINS_PINLOC_17 (0), + .UNUSED_MEM_PINS_PINLOC_18 (0), + .UNUSED_MEM_PINS_PINLOC_19 (0), + .UNUSED_MEM_PINS_PINLOC_20 (0), + .UNUSED_MEM_PINS_PINLOC_21 (0), + .UNUSED_MEM_PINS_PINLOC_22 (0), + .UNUSED_MEM_PINS_PINLOC_23 (0), + .UNUSED_MEM_PINS_PINLOC_24 (0), + .UNUSED_MEM_PINS_PINLOC_25 (0), + .UNUSED_MEM_PINS_PINLOC_26 (0), + .UNUSED_MEM_PINS_PINLOC_27 (0), + .UNUSED_MEM_PINS_PINLOC_28 (0), + .UNUSED_MEM_PINS_PINLOC_29 (0), + .UNUSED_MEM_PINS_PINLOC_30 (0), + .UNUSED_MEM_PINS_PINLOC_31 (0), + .UNUSED_MEM_PINS_PINLOC_32 (0), + .UNUSED_MEM_PINS_PINLOC_33 (0), + .UNUSED_MEM_PINS_PINLOC_34 (0), + .UNUSED_MEM_PINS_PINLOC_35 (0), + .UNUSED_MEM_PINS_PINLOC_36 (0), + .UNUSED_MEM_PINS_PINLOC_37 (0), + .UNUSED_MEM_PINS_PINLOC_38 (0), + .UNUSED_MEM_PINS_PINLOC_39 (0), + .UNUSED_MEM_PINS_PINLOC_40 (0), + .UNUSED_MEM_PINS_PINLOC_41 (0), + .UNUSED_MEM_PINS_PINLOC_42 (0), + .UNUSED_MEM_PINS_PINLOC_43 (0), + .UNUSED_MEM_PINS_PINLOC_44 (0), + .UNUSED_MEM_PINS_PINLOC_45 (0), + .UNUSED_MEM_PINS_PINLOC_46 (0), + .UNUSED_MEM_PINS_PINLOC_47 (0), + .UNUSED_MEM_PINS_PINLOC_48 (0), + .UNUSED_MEM_PINS_PINLOC_49 (0), + .UNUSED_MEM_PINS_PINLOC_50 (0), + .UNUSED_MEM_PINS_PINLOC_51 (0), + .UNUSED_MEM_PINS_PINLOC_52 (0), + .UNUSED_MEM_PINS_PINLOC_53 (0), + .UNUSED_MEM_PINS_PINLOC_54 (0), + .UNUSED_MEM_PINS_PINLOC_55 (0), + .UNUSED_MEM_PINS_PINLOC_56 (0), + .UNUSED_MEM_PINS_PINLOC_57 (0), + .UNUSED_MEM_PINS_PINLOC_58 (0), + .UNUSED_MEM_PINS_PINLOC_59 (0), + .UNUSED_MEM_PINS_PINLOC_60 (0), + .UNUSED_MEM_PINS_PINLOC_61 (0), + .UNUSED_MEM_PINS_PINLOC_62 (0), + .UNUSED_MEM_PINS_PINLOC_63 (0), + .UNUSED_MEM_PINS_PINLOC_64 (0), + .UNUSED_MEM_PINS_PINLOC_65 (0), + .UNUSED_MEM_PINS_PINLOC_66 (0), + .UNUSED_MEM_PINS_PINLOC_67 (0), + .UNUSED_MEM_PINS_PINLOC_68 (0), + .UNUSED_MEM_PINS_PINLOC_69 (0), + .UNUSED_MEM_PINS_PINLOC_70 (0), + .UNUSED_MEM_PINS_PINLOC_71 (0), + .UNUSED_MEM_PINS_PINLOC_72 (0), + .UNUSED_MEM_PINS_PINLOC_73 (0), + .UNUSED_MEM_PINS_PINLOC_74 (0), + .UNUSED_MEM_PINS_PINLOC_75 (0), + .UNUSED_MEM_PINS_PINLOC_76 (0), + .UNUSED_MEM_PINS_PINLOC_77 (0), + .UNUSED_MEM_PINS_PINLOC_78 (0), + .UNUSED_MEM_PINS_PINLOC_79 (0), + .UNUSED_MEM_PINS_PINLOC_80 (0), + .UNUSED_MEM_PINS_PINLOC_81 (0), + .UNUSED_MEM_PINS_PINLOC_82 (0), + .UNUSED_MEM_PINS_PINLOC_83 (0), + .UNUSED_MEM_PINS_PINLOC_84 (0), + .UNUSED_MEM_PINS_PINLOC_85 (0), + .UNUSED_MEM_PINS_PINLOC_86 (0), + .UNUSED_MEM_PINS_PINLOC_87 (0), + .UNUSED_MEM_PINS_PINLOC_88 (0), + .UNUSED_MEM_PINS_PINLOC_89 (0), + .UNUSED_MEM_PINS_PINLOC_90 (0), + .UNUSED_MEM_PINS_PINLOC_91 (0), + .UNUSED_MEM_PINS_PINLOC_92 (0), + .UNUSED_MEM_PINS_PINLOC_93 (0), + .UNUSED_MEM_PINS_PINLOC_94 (0), + .UNUSED_MEM_PINS_PINLOC_95 (0), + .UNUSED_MEM_PINS_PINLOC_96 (0), + .UNUSED_MEM_PINS_PINLOC_97 (0), + .UNUSED_MEM_PINS_PINLOC_98 (0), + .UNUSED_MEM_PINS_PINLOC_99 (0), + .UNUSED_MEM_PINS_PINLOC_100 (0), + .UNUSED_MEM_PINS_PINLOC_101 (0), + .UNUSED_MEM_PINS_PINLOC_102 (0), + .UNUSED_MEM_PINS_PINLOC_103 (0), + .UNUSED_MEM_PINS_PINLOC_104 (0), + .UNUSED_MEM_PINS_PINLOC_105 (0), + .UNUSED_MEM_PINS_PINLOC_106 (0), + .UNUSED_MEM_PINS_PINLOC_107 (0), + .UNUSED_MEM_PINS_PINLOC_108 (0), + .UNUSED_MEM_PINS_PINLOC_109 (0), + .UNUSED_MEM_PINS_PINLOC_110 (0), + .UNUSED_MEM_PINS_PINLOC_111 (0), + .UNUSED_MEM_PINS_PINLOC_112 (0), + .UNUSED_MEM_PINS_PINLOC_113 (0), + .UNUSED_MEM_PINS_PINLOC_114 (0), + .UNUSED_MEM_PINS_PINLOC_115 (0), + .UNUSED_MEM_PINS_PINLOC_116 (0), + .UNUSED_MEM_PINS_PINLOC_117 (0), + .UNUSED_MEM_PINS_PINLOC_118 (0), + .UNUSED_MEM_PINS_PINLOC_119 (0), + .UNUSED_MEM_PINS_PINLOC_120 (0), + .UNUSED_MEM_PINS_PINLOC_121 (0), + .UNUSED_MEM_PINS_PINLOC_122 (0), + .UNUSED_MEM_PINS_PINLOC_123 (0), + .UNUSED_MEM_PINS_PINLOC_124 (0), + .UNUSED_MEM_PINS_PINLOC_125 (0), + .UNUSED_MEM_PINS_PINLOC_126 (0), + .UNUSED_MEM_PINS_PINLOC_127 (0), + .UNUSED_MEM_PINS_PINLOC_128 (0), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (129), + .UNUSED_DQS_BUSES_LANELOC_0 (6302724), + .UNUSED_DQS_BUSES_LANELOC_1 (4101), + .UNUSED_DQS_BUSES_LANELOC_2 (0), + .UNUSED_DQS_BUSES_LANELOC_3 (0), + .UNUSED_DQS_BUSES_LANELOC_4 (0), + .UNUSED_DQS_BUSES_LANELOC_5 (0), + .UNUSED_DQS_BUSES_LANELOC_6 (0), + .UNUSED_DQS_BUSES_LANELOC_7 (0), + .UNUSED_DQS_BUSES_LANELOC_8 (0), + .UNUSED_DQS_BUSES_LANELOC_9 (0), + .UNUSED_DQS_BUSES_LANELOC_10 (0), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (11), + .CENTER_TIDS_0 (5249028), + .CENTER_TIDS_1 (0), + .CENTER_TIDS_2 (0), + .CENTER_TIDS_AUTOGEN_WCNT (3), + .HMC_TIDS_0 (5511685), + .HMC_TIDS_1 (0), + .HMC_TIDS_2 (0), + .HMC_TIDS_AUTOGEN_WCNT (3), + .LANE_TIDS_0 (403177984), + .LANE_TIDS_1 (168067584), + .LANE_TIDS_2 (35717208), + .LANE_TIDS_3 (9746), + .LANE_TIDS_4 (0), + .LANE_TIDS_5 (0), + .LANE_TIDS_6 (0), + .LANE_TIDS_7 (0), + .LANE_TIDS_8 (0), + .LANE_TIDS_9 (0), + .LANE_TIDS_AUTOGEN_WCNT (10), + .PREAMBLE_MODE ("preamble_one_cycle"), + .DBI_WR_ENABLE ("false"), + .DBI_RD_ENABLE ("true"), + .CRC_EN ("crc_disable"), + .SWAP_DQS_A_B ("false"), + .DQS_PACK_MODE ("packed"), + .OCT_SIZE (2), + .DBC_WB_RESERVED_ENTRY (8), + .DLL_MODE ("ctl_dynamic"), + .DLL_CODEWORD (0), + .ABPHY_WRITE_PROTOCOL (0), + .PHY_USERMODE_OCT (0), + .PHY_PERIODIC_OCT_RECAL (0), + .PHY_HAS_DCC (1), + .PRI_HMC_CFG_ENABLE_ECC ("disable"), + .PRI_HMC_CFG_REORDER_DATA ("enable"), + .PRI_HMC_CFG_REORDER_READ ("enable"), + .PRI_HMC_CFG_REORDER_RDATA ("enable"), + .PRI_HMC_CFG_STARVE_LIMIT (10), + .PRI_HMC_CFG_DQS_TRACKING_EN ("disable"), + .PRI_HMC_CFG_ARBITER_TYPE ("twot"), + .PRI_HMC_CFG_OPEN_PAGE_EN ("enable"), + .PRI_HMC_CFG_GEAR_DOWN_EN ("disable"), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE ("singlebank"), + .PRI_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .PRI_HMC_CFG_SLOT_ROTATE_EN (0), + .PRI_HMC_CFG_SLOT_OFFSET (2), + .PRI_HMC_CFG_COL_CMD_SLOT (2), + .PRI_HMC_CFG_ROW_CMD_SLOT (1), + .PRI_HMC_CFG_ENABLE_RC ("enable"), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (8), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (8), + .PRI_HMC_CFG_TCL (18), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (14), + .PRI_HMC_CFG_WRITE_ODT_CHIP (1), + .PRI_HMC_CFG_READ_ODT_CHIP (0), + .PRI_HMC_CFG_WR_ODT_ON (0), + .PRI_HMC_CFG_RD_ODT_ON (6), + .PRI_HMC_CFG_WR_ODT_PERIOD (6), + .PRI_HMC_CFG_RD_ODT_PERIOD (7), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (15), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (240), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (3840), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (61440), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (512), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (24), + .PRI_HMC_CFG_DQSTRK_TO_VALID (4), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (4), + .PRI_HMC_CFG_SB_CG_DISABLE ("disable"), + .PRI_HMC_CFG_USER_RFSH_EN ("disable"), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ("presrfexit"), + .PRI_HMC_CFG_SB_DDR4_MR3 (197120), + .PRI_HMC_CFG_SB_DDR4_MR4 (264192), + .PRI_HMC_CFG_SB_DDR4_MR5 (5152), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (0), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH ("col_width_10"), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH ("row_width_15"), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH ("bank_width_2"), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH ("bg_width_2"), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH ("cs_width_0"), + .PRI_HMC_CFG_ADDR_ORDER ("chip_row_bank_col"), + .PRI_HMC_CFG_ACT_TO_RDWR (7), + .PRI_HMC_CFG_ACT_TO_PCH (18), + .PRI_HMC_CFG_ACT_TO_ACT (25), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .PRI_HMC_CFG_RD_TO_RD (3), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .PRI_HMC_CFG_RD_TO_WR (9), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (9), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (9), + .PRI_HMC_CFG_RD_TO_PCH (5), + .PRI_HMC_CFG_RD_AP_TO_VALID (13), + .PRI_HMC_CFG_WR_TO_WR (3), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .PRI_HMC_CFG_WR_TO_RD (14), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (5), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (12), + .PRI_HMC_CFG_WR_TO_PCH (17), + .PRI_HMC_CFG_WR_AP_TO_VALID (25), + .PRI_HMC_CFG_PCH_TO_VALID (8), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (8), + .PRI_HMC_CFG_ARF_TO_VALID (140), + .PRI_HMC_CFG_PDN_TO_VALID (4), + .PRI_HMC_CFG_SRF_TO_VALID (513), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (449), + .PRI_HMC_CFG_ARF_PERIOD (4161), + .PRI_HMC_CFG_PDN_PERIOD (0), + .PRI_HMC_CFG_ZQCL_TO_VALID (257), + .PRI_HMC_CFG_ZQCS_TO_VALID (65), + .PRI_HMC_CFG_MRS_TO_VALID (7), + .PRI_HMC_CFG_MPS_TO_VALID (768), + .PRI_HMC_CFG_MRR_TO_VALID (0), + .PRI_HMC_CFG_MPR_TO_VALID (16), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (16), + .PRI_HMC_CFG_4_ACT_TO_ACT (11), + .PRI_HMC_CFG_16_ACT_TO_ACT (0), + .SEC_HMC_CFG_ENABLE_ECC ("disable"), + .SEC_HMC_CFG_REORDER_DATA ("enable"), + .SEC_HMC_CFG_REORDER_READ ("enable"), + .SEC_HMC_CFG_REORDER_RDATA ("enable"), + .SEC_HMC_CFG_STARVE_LIMIT (10), + .SEC_HMC_CFG_DQS_TRACKING_EN ("disable"), + .SEC_HMC_CFG_ARBITER_TYPE ("twot"), + .SEC_HMC_CFG_OPEN_PAGE_EN ("enable"), + .SEC_HMC_CFG_GEAR_DOWN_EN ("disable"), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE ("singlebank"), + .SEC_HMC_CFG_PING_PONG_MODE ("pingpong_off"), + .SEC_HMC_CFG_SLOT_ROTATE_EN (0), + .SEC_HMC_CFG_SLOT_OFFSET (2), + .SEC_HMC_CFG_COL_CMD_SLOT (2), + .SEC_HMC_CFG_ROW_CMD_SLOT (1), + .SEC_HMC_CFG_ENABLE_RC ("enable"), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (33825), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (8), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (8), + .SEC_HMC_CFG_TCL (18), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (3), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (14), + .SEC_HMC_CFG_WRITE_ODT_CHIP (1), + .SEC_HMC_CFG_READ_ODT_CHIP (0), + .SEC_HMC_CFG_WR_ODT_ON (0), + .SEC_HMC_CFG_RD_ODT_ON (6), + .SEC_HMC_CFG_WR_ODT_PERIOD (6), + .SEC_HMC_CFG_RD_ODT_PERIOD (7), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (15), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (240), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (3840), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (61440), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE ("disable"), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE ("disable"), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE ("disable"), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN ("disable"), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (512), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (24), + .SEC_HMC_CFG_DQSTRK_TO_VALID (4), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (4), + .SEC_HMC_CFG_SB_CG_DISABLE ("disable"), + .SEC_HMC_CFG_USER_RFSH_EN ("disable"), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN ("disable"), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK ("presrfexit"), + .SEC_HMC_CFG_SB_DDR4_MR3 (197120), + .SEC_HMC_CFG_SB_DDR4_MR4 (264192), + .SEC_HMC_CFG_SB_DDR4_MR5 (5152), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (0), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH ("col_width_10"), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH ("row_width_15"), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH ("bank_width_2"), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH ("bg_width_2"), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH ("cs_width_0"), + .SEC_HMC_CFG_ADDR_ORDER ("chip_row_bank_col"), + .SEC_HMC_CFG_ACT_TO_RDWR (7), + .SEC_HMC_CFG_ACT_TO_PCH (18), + .SEC_HMC_CFG_ACT_TO_ACT (25), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (3), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (2), + .SEC_HMC_CFG_RD_TO_RD (3), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (4), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (2), + .SEC_HMC_CFG_RD_TO_WR (9), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (9), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (9), + .SEC_HMC_CFG_RD_TO_PCH (5), + .SEC_HMC_CFG_RD_AP_TO_VALID (13), + .SEC_HMC_CFG_WR_TO_WR (3), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (3), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (2), + .SEC_HMC_CFG_WR_TO_RD (14), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (5), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (12), + .SEC_HMC_CFG_WR_TO_PCH (17), + .SEC_HMC_CFG_WR_AP_TO_VALID (25), + .SEC_HMC_CFG_PCH_TO_VALID (8), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (8), + .SEC_HMC_CFG_ARF_TO_VALID (140), + .SEC_HMC_CFG_PDN_TO_VALID (4), + .SEC_HMC_CFG_SRF_TO_VALID (513), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (449), + .SEC_HMC_CFG_ARF_PERIOD (4161), + .SEC_HMC_CFG_PDN_PERIOD (0), + .SEC_HMC_CFG_ZQCL_TO_VALID (257), + .SEC_HMC_CFG_ZQCS_TO_VALID (65), + .SEC_HMC_CFG_MRS_TO_VALID (7), + .SEC_HMC_CFG_MPS_TO_VALID (768), + .SEC_HMC_CFG_MRR_TO_VALID (0), + .SEC_HMC_CFG_MPR_TO_VALID (16), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (5), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (6), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (0), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (16), + .SEC_HMC_CFG_4_ACT_TO_ACT (11), + .SEC_HMC_CFG_16_ACT_TO_ACT (0), + .PINS_PER_LANE (12), + .LANES_PER_TILE (4), + .OCT_CONTROL_WIDTH (16), + .PORT_MEM_CK_WIDTH (1), + .PORT_MEM_CK_PINLOC_0 (57345), + .PORT_MEM_CK_PINLOC_1 (0), + .PORT_MEM_CK_PINLOC_2 (0), + .PORT_MEM_CK_PINLOC_3 (0), + .PORT_MEM_CK_PINLOC_4 (0), + .PORT_MEM_CK_PINLOC_5 (0), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CK_N_WIDTH (1), + .PORT_MEM_CK_N_PINLOC_0 (58369), + .PORT_MEM_CK_N_PINLOC_1 (0), + .PORT_MEM_CK_N_PINLOC_2 (0), + .PORT_MEM_CK_N_PINLOC_3 (0), + .PORT_MEM_CK_N_PINLOC_4 (0), + .PORT_MEM_CK_N_PINLOC_5 (0), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_WIDTH (1), + .PORT_MEM_DK_PINLOC_0 (0), + .PORT_MEM_DK_PINLOC_1 (0), + .PORT_MEM_DK_PINLOC_2 (0), + .PORT_MEM_DK_PINLOC_3 (0), + .PORT_MEM_DK_PINLOC_4 (0), + .PORT_MEM_DK_PINLOC_5 (0), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DK_N_WIDTH (1), + .PORT_MEM_DK_N_PINLOC_0 (0), + .PORT_MEM_DK_N_PINLOC_1 (0), + .PORT_MEM_DK_N_PINLOC_2 (0), + .PORT_MEM_DK_N_PINLOC_3 (0), + .PORT_MEM_DK_N_PINLOC_4 (0), + .PORT_MEM_DK_N_PINLOC_5 (0), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_WIDTH (1), + .PORT_MEM_DKA_PINLOC_0 (0), + .PORT_MEM_DKA_PINLOC_1 (0), + .PORT_MEM_DKA_PINLOC_2 (0), + .PORT_MEM_DKA_PINLOC_3 (0), + .PORT_MEM_DKA_PINLOC_4 (0), + .PORT_MEM_DKA_PINLOC_5 (0), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKA_N_WIDTH (1), + .PORT_MEM_DKA_N_PINLOC_0 (0), + .PORT_MEM_DKA_N_PINLOC_1 (0), + .PORT_MEM_DKA_N_PINLOC_2 (0), + .PORT_MEM_DKA_N_PINLOC_3 (0), + .PORT_MEM_DKA_N_PINLOC_4 (0), + .PORT_MEM_DKA_N_PINLOC_5 (0), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_WIDTH (1), + .PORT_MEM_DKB_PINLOC_0 (0), + .PORT_MEM_DKB_PINLOC_1 (0), + .PORT_MEM_DKB_PINLOC_2 (0), + .PORT_MEM_DKB_PINLOC_3 (0), + .PORT_MEM_DKB_PINLOC_4 (0), + .PORT_MEM_DKB_PINLOC_5 (0), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_DKB_N_WIDTH (1), + .PORT_MEM_DKB_N_PINLOC_0 (0), + .PORT_MEM_DKB_N_PINLOC_1 (0), + .PORT_MEM_DKB_N_PINLOC_2 (0), + .PORT_MEM_DKB_N_PINLOC_3 (0), + .PORT_MEM_DKB_N_PINLOC_4 (0), + .PORT_MEM_DKB_N_PINLOC_5 (0), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_WIDTH (1), + .PORT_MEM_K_PINLOC_0 (0), + .PORT_MEM_K_PINLOC_1 (0), + .PORT_MEM_K_PINLOC_2 (0), + .PORT_MEM_K_PINLOC_3 (0), + .PORT_MEM_K_PINLOC_4 (0), + .PORT_MEM_K_PINLOC_5 (0), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_K_N_WIDTH (1), + .PORT_MEM_K_N_PINLOC_0 (0), + .PORT_MEM_K_N_PINLOC_1 (0), + .PORT_MEM_K_N_PINLOC_2 (0), + .PORT_MEM_K_N_PINLOC_3 (0), + .PORT_MEM_K_N_PINLOC_4 (0), + .PORT_MEM_K_N_PINLOC_5 (0), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_A_WIDTH (17), + .PORT_MEM_A_PINLOC_0 (64024593), + .PORT_MEM_A_PINLOC_1 (67173438), + .PORT_MEM_A_PINLOC_2 (70322241), + .PORT_MEM_A_PINLOC_3 (73471044), + .PORT_MEM_A_PINLOC_4 (79768647), + .PORT_MEM_A_PINLOC_5 (82917453), + .PORT_MEM_A_PINLOC_6 (0), + .PORT_MEM_A_PINLOC_7 (0), + .PORT_MEM_A_PINLOC_8 (0), + .PORT_MEM_A_PINLOC_9 (0), + .PORT_MEM_A_PINLOC_10 (0), + .PORT_MEM_A_PINLOC_11 (0), + .PORT_MEM_A_PINLOC_12 (0), + .PORT_MEM_A_PINLOC_13 (0), + .PORT_MEM_A_PINLOC_14 (0), + .PORT_MEM_A_PINLOC_15 (0), + .PORT_MEM_A_PINLOC_16 (0), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_BA_WIDTH (2), + .PORT_MEM_BA_PINLOC_0 (86066178), + .PORT_MEM_BA_PINLOC_1 (0), + .PORT_MEM_BA_PINLOC_2 (0), + .PORT_MEM_BA_PINLOC_3 (0), + .PORT_MEM_BA_PINLOC_4 (0), + .PORT_MEM_BA_PINLOC_5 (0), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_BG_WIDTH (2), + .PORT_MEM_BG_PINLOC_0 (50416642), + .PORT_MEM_BG_PINLOC_1 (0), + .PORT_MEM_BG_PINLOC_2 (0), + .PORT_MEM_BG_PINLOC_3 (0), + .PORT_MEM_BG_PINLOC_4 (0), + .PORT_MEM_BG_PINLOC_5 (0), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_C_WIDTH (1), + .PORT_MEM_C_PINLOC_0 (0), + .PORT_MEM_C_PINLOC_1 (0), + .PORT_MEM_C_PINLOC_2 (0), + .PORT_MEM_C_PINLOC_3 (0), + .PORT_MEM_C_PINLOC_4 (0), + .PORT_MEM_C_PINLOC_5 (0), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CKE_WIDTH (1), + .PORT_MEM_CKE_PINLOC_0 (55297), + .PORT_MEM_CKE_PINLOC_1 (0), + .PORT_MEM_CKE_PINLOC_2 (0), + .PORT_MEM_CKE_PINLOC_3 (0), + .PORT_MEM_CKE_PINLOC_4 (0), + .PORT_MEM_CKE_PINLOC_5 (0), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CS_N_WIDTH (1), + .PORT_MEM_CS_N_PINLOC_0 (51201), + .PORT_MEM_CS_N_PINLOC_1 (0), + .PORT_MEM_CS_N_PINLOC_2 (0), + .PORT_MEM_CS_N_PINLOC_3 (0), + .PORT_MEM_CS_N_PINLOC_4 (0), + .PORT_MEM_CS_N_PINLOC_5 (0), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RM_WIDTH (1), + .PORT_MEM_RM_PINLOC_0 (0), + .PORT_MEM_RM_PINLOC_1 (0), + .PORT_MEM_RM_PINLOC_2 (0), + .PORT_MEM_RM_PINLOC_3 (0), + .PORT_MEM_RM_PINLOC_4 (0), + .PORT_MEM_RM_PINLOC_5 (0), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_ODT_WIDTH (1), + .PORT_MEM_ODT_PINLOC_0 (53249), + .PORT_MEM_ODT_PINLOC_1 (0), + .PORT_MEM_ODT_PINLOC_2 (0), + .PORT_MEM_ODT_PINLOC_3 (0), + .PORT_MEM_ODT_PINLOC_4 (0), + .PORT_MEM_ODT_PINLOC_5 (0), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_RAS_N_WIDTH (1), + .PORT_MEM_RAS_N_PINLOC_0 (0), + .PORT_MEM_RAS_N_PINLOC_1 (0), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CAS_N_WIDTH (1), + .PORT_MEM_CAS_N_PINLOC_0 (0), + .PORT_MEM_CAS_N_PINLOC_1 (0), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_WE_N_WIDTH (1), + .PORT_MEM_WE_N_PINLOC_0 (0), + .PORT_MEM_WE_N_PINLOC_1 (0), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_RESET_N_WIDTH (1), + .PORT_MEM_RESET_N_PINLOC_0 (50177), + .PORT_MEM_RESET_N_PINLOC_1 (0), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ACT_N_WIDTH (1), + .PORT_MEM_ACT_N_PINLOC_0 (52225), + .PORT_MEM_ACT_N_PINLOC_1 (0), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PAR_WIDTH (1), + .PORT_MEM_PAR_PINLOC_0 (60417), + .PORT_MEM_PAR_PINLOC_1 (0), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CA_WIDTH (1), + .PORT_MEM_CA_PINLOC_0 (0), + .PORT_MEM_CA_PINLOC_1 (0), + .PORT_MEM_CA_PINLOC_2 (0), + .PORT_MEM_CA_PINLOC_3 (0), + .PORT_MEM_CA_PINLOC_4 (0), + .PORT_MEM_CA_PINLOC_5 (0), + .PORT_MEM_CA_PINLOC_6 (0), + .PORT_MEM_CA_PINLOC_7 (0), + .PORT_MEM_CA_PINLOC_8 (0), + .PORT_MEM_CA_PINLOC_9 (0), + .PORT_MEM_CA_PINLOC_10 (0), + .PORT_MEM_CA_PINLOC_11 (0), + .PORT_MEM_CA_PINLOC_12 (0), + .PORT_MEM_CA_PINLOC_13 (0), + .PORT_MEM_CA_PINLOC_14 (0), + .PORT_MEM_CA_PINLOC_15 (0), + .PORT_MEM_CA_PINLOC_16 (0), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (17), + .PORT_MEM_REF_N_WIDTH (1), + .PORT_MEM_REF_N_PINLOC_0 (0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_WPS_N_WIDTH (1), + .PORT_MEM_WPS_N_PINLOC_0 (0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RPS_N_WIDTH (1), + .PORT_MEM_RPS_N_PINLOC_0 (0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DOFF_N_WIDTH (1), + .PORT_MEM_DOFF_N_PINLOC_0 (0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDA_N_WIDTH (1), + .PORT_MEM_LDA_N_PINLOC_0 (0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LDB_N_WIDTH (1), + .PORT_MEM_LDB_N_PINLOC_0 (0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWA_N_WIDTH (1), + .PORT_MEM_RWA_N_PINLOC_0 (0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_RWB_N_WIDTH (1), + .PORT_MEM_RWB_N_PINLOC_0 (0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK0_N_WIDTH (1), + .PORT_MEM_LBK0_N_PINLOC_0 (0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_LBK1_N_WIDTH (1), + .PORT_MEM_LBK1_N_PINLOC_0 (0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_CFG_N_WIDTH (1), + .PORT_MEM_CFG_N_PINLOC_0 (0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AP_WIDTH (1), + .PORT_MEM_AP_PINLOC_0 (0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_AINV_WIDTH (1), + .PORT_MEM_AINV_PINLOC_0 (0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (1), + .PORT_MEM_DM_WIDTH (1), + .PORT_MEM_DM_PINLOC_0 (0), + .PORT_MEM_DM_PINLOC_1 (0), + .PORT_MEM_DM_PINLOC_2 (0), + .PORT_MEM_DM_PINLOC_3 (0), + .PORT_MEM_DM_PINLOC_4 (0), + .PORT_MEM_DM_PINLOC_5 (0), + .PORT_MEM_DM_PINLOC_6 (0), + .PORT_MEM_DM_PINLOC_7 (0), + .PORT_MEM_DM_PINLOC_8 (0), + .PORT_MEM_DM_PINLOC_9 (0), + .PORT_MEM_DM_PINLOC_10 (0), + .PORT_MEM_DM_PINLOC_11 (0), + .PORT_MEM_DM_PINLOC_12 (0), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_BWS_N_WIDTH (1), + .PORT_MEM_BWS_N_PINLOC_0 (0), + .PORT_MEM_BWS_N_PINLOC_1 (0), + .PORT_MEM_BWS_N_PINLOC_2 (0), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_D_WIDTH (1), + .PORT_MEM_D_PINLOC_0 (0), + .PORT_MEM_D_PINLOC_1 (0), + .PORT_MEM_D_PINLOC_2 (0), + .PORT_MEM_D_PINLOC_3 (0), + .PORT_MEM_D_PINLOC_4 (0), + .PORT_MEM_D_PINLOC_5 (0), + .PORT_MEM_D_PINLOC_6 (0), + .PORT_MEM_D_PINLOC_7 (0), + .PORT_MEM_D_PINLOC_8 (0), + .PORT_MEM_D_PINLOC_9 (0), + .PORT_MEM_D_PINLOC_10 (0), + .PORT_MEM_D_PINLOC_11 (0), + .PORT_MEM_D_PINLOC_12 (0), + .PORT_MEM_D_PINLOC_13 (0), + .PORT_MEM_D_PINLOC_14 (0), + .PORT_MEM_D_PINLOC_15 (0), + .PORT_MEM_D_PINLOC_16 (0), + .PORT_MEM_D_PINLOC_17 (0), + .PORT_MEM_D_PINLOC_18 (0), + .PORT_MEM_D_PINLOC_19 (0), + .PORT_MEM_D_PINLOC_20 (0), + .PORT_MEM_D_PINLOC_21 (0), + .PORT_MEM_D_PINLOC_22 (0), + .PORT_MEM_D_PINLOC_23 (0), + .PORT_MEM_D_PINLOC_24 (0), + .PORT_MEM_D_PINLOC_25 (0), + .PORT_MEM_D_PINLOC_26 (0), + .PORT_MEM_D_PINLOC_27 (0), + .PORT_MEM_D_PINLOC_28 (0), + .PORT_MEM_D_PINLOC_29 (0), + .PORT_MEM_D_PINLOC_30 (0), + .PORT_MEM_D_PINLOC_31 (0), + .PORT_MEM_D_PINLOC_32 (0), + .PORT_MEM_D_PINLOC_33 (0), + .PORT_MEM_D_PINLOC_34 (0), + .PORT_MEM_D_PINLOC_35 (0), + .PORT_MEM_D_PINLOC_36 (0), + .PORT_MEM_D_PINLOC_37 (0), + .PORT_MEM_D_PINLOC_38 (0), + .PORT_MEM_D_PINLOC_39 (0), + .PORT_MEM_D_PINLOC_40 (0), + .PORT_MEM_D_PINLOC_41 (0), + .PORT_MEM_D_PINLOC_42 (0), + .PORT_MEM_D_PINLOC_43 (0), + .PORT_MEM_D_PINLOC_44 (0), + .PORT_MEM_D_PINLOC_45 (0), + .PORT_MEM_D_PINLOC_46 (0), + .PORT_MEM_D_PINLOC_47 (0), + .PORT_MEM_D_PINLOC_48 (0), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQ_WIDTH (64), + .PORT_MEM_DQ_PINLOC_0 (2098240), + .PORT_MEM_DQ_PINLOC_1 (7346179), + .PORT_MEM_DQ_PINLOC_2 (10494984), + .PORT_MEM_DQ_PINLOC_3 (15742989), + .PORT_MEM_DQ_PINLOC_4 (20990994), + .PORT_MEM_DQ_PINLOC_5 (26236949), + .PORT_MEM_DQ_PINLOC_6 (31484954), + .PORT_MEM_DQ_PINLOC_7 (34635807), + .PORT_MEM_DQ_PINLOC_8 (39883810), + .PORT_MEM_DQ_PINLOC_9 (45131815), + .PORT_MEM_DQ_PINLOC_10 (48280620), + .PORT_MEM_DQ_PINLOC_11 (91314261), + .PORT_MEM_DQ_PINLOC_12 (96562266), + .PORT_MEM_DQ_PINLOC_13 (101808221), + .PORT_MEM_DQ_PINLOC_14 (107056226), + .PORT_MEM_DQ_PINLOC_15 (110207079), + .PORT_MEM_DQ_PINLOC_16 (115455082), + .PORT_MEM_DQ_PINLOC_17 (120703087), + .PORT_MEM_DQ_PINLOC_18 (123851892), + .PORT_MEM_DQ_PINLOC_19 (129099897), + .PORT_MEM_DQ_PINLOC_20 (134347902), + .PORT_MEM_DQ_PINLOC_21 (133249), + .PORT_MEM_DQ_PINLOC_22 (0), + .PORT_MEM_DQ_PINLOC_23 (0), + .PORT_MEM_DQ_PINLOC_24 (0), + .PORT_MEM_DQ_PINLOC_25 (0), + .PORT_MEM_DQ_PINLOC_26 (0), + .PORT_MEM_DQ_PINLOC_27 (0), + .PORT_MEM_DQ_PINLOC_28 (0), + .PORT_MEM_DQ_PINLOC_29 (0), + .PORT_MEM_DQ_PINLOC_30 (0), + .PORT_MEM_DQ_PINLOC_31 (0), + .PORT_MEM_DQ_PINLOC_32 (0), + .PORT_MEM_DQ_PINLOC_33 (0), + .PORT_MEM_DQ_PINLOC_34 (0), + .PORT_MEM_DQ_PINLOC_35 (0), + .PORT_MEM_DQ_PINLOC_36 (0), + .PORT_MEM_DQ_PINLOC_37 (0), + .PORT_MEM_DQ_PINLOC_38 (0), + .PORT_MEM_DQ_PINLOC_39 (0), + .PORT_MEM_DQ_PINLOC_40 (0), + .PORT_MEM_DQ_PINLOC_41 (0), + .PORT_MEM_DQ_PINLOC_42 (0), + .PORT_MEM_DQ_PINLOC_43 (0), + .PORT_MEM_DQ_PINLOC_44 (0), + .PORT_MEM_DQ_PINLOC_45 (0), + .PORT_MEM_DQ_PINLOC_46 (0), + .PORT_MEM_DQ_PINLOC_47 (0), + .PORT_MEM_DQ_PINLOC_48 (0), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DBI_N_WIDTH (8), + .PORT_MEM_DBI_N_PINLOC_0 (24128520), + .PORT_MEM_DBI_N_PINLOC_1 (99662883), + .PORT_MEM_DBI_N_PINLOC_2 (137485419), + .PORT_MEM_DBI_N_PINLOC_3 (0), + .PORT_MEM_DBI_N_PINLOC_4 (0), + .PORT_MEM_DBI_N_PINLOC_5 (0), + .PORT_MEM_DBI_N_PINLOC_6 (0), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (7), + .PORT_MEM_DQA_WIDTH (1), + .PORT_MEM_DQA_PINLOC_0 (0), + .PORT_MEM_DQA_PINLOC_1 (0), + .PORT_MEM_DQA_PINLOC_2 (0), + .PORT_MEM_DQA_PINLOC_3 (0), + .PORT_MEM_DQA_PINLOC_4 (0), + .PORT_MEM_DQA_PINLOC_5 (0), + .PORT_MEM_DQA_PINLOC_6 (0), + .PORT_MEM_DQA_PINLOC_7 (0), + .PORT_MEM_DQA_PINLOC_8 (0), + .PORT_MEM_DQA_PINLOC_9 (0), + .PORT_MEM_DQA_PINLOC_10 (0), + .PORT_MEM_DQA_PINLOC_11 (0), + .PORT_MEM_DQA_PINLOC_12 (0), + .PORT_MEM_DQA_PINLOC_13 (0), + .PORT_MEM_DQA_PINLOC_14 (0), + .PORT_MEM_DQA_PINLOC_15 (0), + .PORT_MEM_DQA_PINLOC_16 (0), + .PORT_MEM_DQA_PINLOC_17 (0), + .PORT_MEM_DQA_PINLOC_18 (0), + .PORT_MEM_DQA_PINLOC_19 (0), + .PORT_MEM_DQA_PINLOC_20 (0), + .PORT_MEM_DQA_PINLOC_21 (0), + .PORT_MEM_DQA_PINLOC_22 (0), + .PORT_MEM_DQA_PINLOC_23 (0), + .PORT_MEM_DQA_PINLOC_24 (0), + .PORT_MEM_DQA_PINLOC_25 (0), + .PORT_MEM_DQA_PINLOC_26 (0), + .PORT_MEM_DQA_PINLOC_27 (0), + .PORT_MEM_DQA_PINLOC_28 (0), + .PORT_MEM_DQA_PINLOC_29 (0), + .PORT_MEM_DQA_PINLOC_30 (0), + .PORT_MEM_DQA_PINLOC_31 (0), + .PORT_MEM_DQA_PINLOC_32 (0), + .PORT_MEM_DQA_PINLOC_33 (0), + .PORT_MEM_DQA_PINLOC_34 (0), + .PORT_MEM_DQA_PINLOC_35 (0), + .PORT_MEM_DQA_PINLOC_36 (0), + .PORT_MEM_DQA_PINLOC_37 (0), + .PORT_MEM_DQA_PINLOC_38 (0), + .PORT_MEM_DQA_PINLOC_39 (0), + .PORT_MEM_DQA_PINLOC_40 (0), + .PORT_MEM_DQA_PINLOC_41 (0), + .PORT_MEM_DQA_PINLOC_42 (0), + .PORT_MEM_DQA_PINLOC_43 (0), + .PORT_MEM_DQA_PINLOC_44 (0), + .PORT_MEM_DQA_PINLOC_45 (0), + .PORT_MEM_DQA_PINLOC_46 (0), + .PORT_MEM_DQA_PINLOC_47 (0), + .PORT_MEM_DQA_PINLOC_48 (0), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQB_WIDTH (1), + .PORT_MEM_DQB_PINLOC_0 (0), + .PORT_MEM_DQB_PINLOC_1 (0), + .PORT_MEM_DQB_PINLOC_2 (0), + .PORT_MEM_DQB_PINLOC_3 (0), + .PORT_MEM_DQB_PINLOC_4 (0), + .PORT_MEM_DQB_PINLOC_5 (0), + .PORT_MEM_DQB_PINLOC_6 (0), + .PORT_MEM_DQB_PINLOC_7 (0), + .PORT_MEM_DQB_PINLOC_8 (0), + .PORT_MEM_DQB_PINLOC_9 (0), + .PORT_MEM_DQB_PINLOC_10 (0), + .PORT_MEM_DQB_PINLOC_11 (0), + .PORT_MEM_DQB_PINLOC_12 (0), + .PORT_MEM_DQB_PINLOC_13 (0), + .PORT_MEM_DQB_PINLOC_14 (0), + .PORT_MEM_DQB_PINLOC_15 (0), + .PORT_MEM_DQB_PINLOC_16 (0), + .PORT_MEM_DQB_PINLOC_17 (0), + .PORT_MEM_DQB_PINLOC_18 (0), + .PORT_MEM_DQB_PINLOC_19 (0), + .PORT_MEM_DQB_PINLOC_20 (0), + .PORT_MEM_DQB_PINLOC_21 (0), + .PORT_MEM_DQB_PINLOC_22 (0), + .PORT_MEM_DQB_PINLOC_23 (0), + .PORT_MEM_DQB_PINLOC_24 (0), + .PORT_MEM_DQB_PINLOC_25 (0), + .PORT_MEM_DQB_PINLOC_26 (0), + .PORT_MEM_DQB_PINLOC_27 (0), + .PORT_MEM_DQB_PINLOC_28 (0), + .PORT_MEM_DQB_PINLOC_29 (0), + .PORT_MEM_DQB_PINLOC_30 (0), + .PORT_MEM_DQB_PINLOC_31 (0), + .PORT_MEM_DQB_PINLOC_32 (0), + .PORT_MEM_DQB_PINLOC_33 (0), + .PORT_MEM_DQB_PINLOC_34 (0), + .PORT_MEM_DQB_PINLOC_35 (0), + .PORT_MEM_DQB_PINLOC_36 (0), + .PORT_MEM_DQB_PINLOC_37 (0), + .PORT_MEM_DQB_PINLOC_38 (0), + .PORT_MEM_DQB_PINLOC_39 (0), + .PORT_MEM_DQB_PINLOC_40 (0), + .PORT_MEM_DQB_PINLOC_41 (0), + .PORT_MEM_DQB_PINLOC_42 (0), + .PORT_MEM_DQB_PINLOC_43 (0), + .PORT_MEM_DQB_PINLOC_44 (0), + .PORT_MEM_DQB_PINLOC_45 (0), + .PORT_MEM_DQB_PINLOC_46 (0), + .PORT_MEM_DQB_PINLOC_47 (0), + .PORT_MEM_DQB_PINLOC_48 (0), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DINVA_WIDTH (1), + .PORT_MEM_DINVA_PINLOC_0 (0), + .PORT_MEM_DINVA_PINLOC_1 (0), + .PORT_MEM_DINVA_PINLOC_2 (0), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_DINVB_WIDTH (1), + .PORT_MEM_DINVB_PINLOC_0 (0), + .PORT_MEM_DINVB_PINLOC_1 (0), + .PORT_MEM_DINVB_PINLOC_2 (0), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (3), + .PORT_MEM_Q_WIDTH (1), + .PORT_MEM_Q_PINLOC_0 (0), + .PORT_MEM_Q_PINLOC_1 (0), + .PORT_MEM_Q_PINLOC_2 (0), + .PORT_MEM_Q_PINLOC_3 (0), + .PORT_MEM_Q_PINLOC_4 (0), + .PORT_MEM_Q_PINLOC_5 (0), + .PORT_MEM_Q_PINLOC_6 (0), + .PORT_MEM_Q_PINLOC_7 (0), + .PORT_MEM_Q_PINLOC_8 (0), + .PORT_MEM_Q_PINLOC_9 (0), + .PORT_MEM_Q_PINLOC_10 (0), + .PORT_MEM_Q_PINLOC_11 (0), + .PORT_MEM_Q_PINLOC_12 (0), + .PORT_MEM_Q_PINLOC_13 (0), + .PORT_MEM_Q_PINLOC_14 (0), + .PORT_MEM_Q_PINLOC_15 (0), + .PORT_MEM_Q_PINLOC_16 (0), + .PORT_MEM_Q_PINLOC_17 (0), + .PORT_MEM_Q_PINLOC_18 (0), + .PORT_MEM_Q_PINLOC_19 (0), + .PORT_MEM_Q_PINLOC_20 (0), + .PORT_MEM_Q_PINLOC_21 (0), + .PORT_MEM_Q_PINLOC_22 (0), + .PORT_MEM_Q_PINLOC_23 (0), + .PORT_MEM_Q_PINLOC_24 (0), + .PORT_MEM_Q_PINLOC_25 (0), + .PORT_MEM_Q_PINLOC_26 (0), + .PORT_MEM_Q_PINLOC_27 (0), + .PORT_MEM_Q_PINLOC_28 (0), + .PORT_MEM_Q_PINLOC_29 (0), + .PORT_MEM_Q_PINLOC_30 (0), + .PORT_MEM_Q_PINLOC_31 (0), + .PORT_MEM_Q_PINLOC_32 (0), + .PORT_MEM_Q_PINLOC_33 (0), + .PORT_MEM_Q_PINLOC_34 (0), + .PORT_MEM_Q_PINLOC_35 (0), + .PORT_MEM_Q_PINLOC_36 (0), + .PORT_MEM_Q_PINLOC_37 (0), + .PORT_MEM_Q_PINLOC_38 (0), + .PORT_MEM_Q_PINLOC_39 (0), + .PORT_MEM_Q_PINLOC_40 (0), + .PORT_MEM_Q_PINLOC_41 (0), + .PORT_MEM_Q_PINLOC_42 (0), + .PORT_MEM_Q_PINLOC_43 (0), + .PORT_MEM_Q_PINLOC_44 (0), + .PORT_MEM_Q_PINLOC_45 (0), + .PORT_MEM_Q_PINLOC_46 (0), + .PORT_MEM_Q_PINLOC_47 (0), + .PORT_MEM_Q_PINLOC_48 (0), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (49), + .PORT_MEM_DQS_WIDTH (8), + .PORT_MEM_DQS_PINLOC_0 (16781320), + .PORT_MEM_DQS_PINLOC_1 (92315676), + .PORT_MEM_DQS_PINLOC_2 (130138212), + .PORT_MEM_DQS_PINLOC_3 (0), + .PORT_MEM_DQS_PINLOC_4 (0), + .PORT_MEM_DQS_PINLOC_5 (0), + .PORT_MEM_DQS_PINLOC_6 (0), + .PORT_MEM_DQS_PINLOC_7 (0), + .PORT_MEM_DQS_PINLOC_8 (0), + .PORT_MEM_DQS_PINLOC_9 (0), + .PORT_MEM_DQS_PINLOC_10 (0), + .PORT_MEM_DQS_PINLOC_11 (0), + .PORT_MEM_DQS_PINLOC_12 (0), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_DQS_N_WIDTH (8), + .PORT_MEM_DQS_N_PINLOC_0 (17830920), + .PORT_MEM_DQS_N_PINLOC_1 (93365277), + .PORT_MEM_DQS_N_PINLOC_2 (131187813), + .PORT_MEM_DQS_N_PINLOC_3 (0), + .PORT_MEM_DQS_N_PINLOC_4 (0), + .PORT_MEM_DQS_N_PINLOC_5 (0), + .PORT_MEM_DQS_N_PINLOC_6 (0), + .PORT_MEM_DQS_N_PINLOC_7 (0), + .PORT_MEM_DQS_N_PINLOC_8 (0), + .PORT_MEM_DQS_N_PINLOC_9 (0), + .PORT_MEM_DQS_N_PINLOC_10 (0), + .PORT_MEM_DQS_N_PINLOC_11 (0), + .PORT_MEM_DQS_N_PINLOC_12 (0), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (13), + .PORT_MEM_QK_WIDTH (1), + .PORT_MEM_QK_PINLOC_0 (0), + .PORT_MEM_QK_PINLOC_1 (0), + .PORT_MEM_QK_PINLOC_2 (0), + .PORT_MEM_QK_PINLOC_3 (0), + .PORT_MEM_QK_PINLOC_4 (0), + .PORT_MEM_QK_PINLOC_5 (0), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QK_N_WIDTH (1), + .PORT_MEM_QK_N_PINLOC_0 (0), + .PORT_MEM_QK_N_PINLOC_1 (0), + .PORT_MEM_QK_N_PINLOC_2 (0), + .PORT_MEM_QK_N_PINLOC_3 (0), + .PORT_MEM_QK_N_PINLOC_4 (0), + .PORT_MEM_QK_N_PINLOC_5 (0), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_WIDTH (1), + .PORT_MEM_QKA_PINLOC_0 (0), + .PORT_MEM_QKA_PINLOC_1 (0), + .PORT_MEM_QKA_PINLOC_2 (0), + .PORT_MEM_QKA_PINLOC_3 (0), + .PORT_MEM_QKA_PINLOC_4 (0), + .PORT_MEM_QKA_PINLOC_5 (0), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKA_N_WIDTH (1), + .PORT_MEM_QKA_N_PINLOC_0 (0), + .PORT_MEM_QKA_N_PINLOC_1 (0), + .PORT_MEM_QKA_N_PINLOC_2 (0), + .PORT_MEM_QKA_N_PINLOC_3 (0), + .PORT_MEM_QKA_N_PINLOC_4 (0), + .PORT_MEM_QKA_N_PINLOC_5 (0), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_WIDTH (1), + .PORT_MEM_QKB_PINLOC_0 (0), + .PORT_MEM_QKB_PINLOC_1 (0), + .PORT_MEM_QKB_PINLOC_2 (0), + .PORT_MEM_QKB_PINLOC_3 (0), + .PORT_MEM_QKB_PINLOC_4 (0), + .PORT_MEM_QKB_PINLOC_5 (0), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_QKB_N_WIDTH (1), + .PORT_MEM_QKB_N_PINLOC_0 (0), + .PORT_MEM_QKB_N_PINLOC_1 (0), + .PORT_MEM_QKB_N_PINLOC_2 (0), + .PORT_MEM_QKB_N_PINLOC_3 (0), + .PORT_MEM_QKB_N_PINLOC_4 (0), + .PORT_MEM_QKB_N_PINLOC_5 (0), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (6), + .PORT_MEM_CQ_WIDTH (1), + .PORT_MEM_CQ_PINLOC_0 (0), + .PORT_MEM_CQ_PINLOC_1 (0), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_CQ_N_WIDTH (1), + .PORT_MEM_CQ_N_PINLOC_0 (0), + .PORT_MEM_CQ_N_PINLOC_1 (0), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_ALERT_N_PINLOC_0 (1), + .PORT_MEM_ALERT_N_PINLOC_1 (0), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_MEM_PE_N_WIDTH (1), + .PORT_MEM_PE_N_PINLOC_0 (0), + .PORT_MEM_PE_N_PINLOC_1 (0), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (2), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (32), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (32), + .PORT_AFI_RLAT_WIDTH (6), + .PORT_AFI_WLAT_WIDTH (6), + .PORT_AFI_SEQ_BUSY_WIDTH (4), + .PORT_AFI_ADDR_WIDTH (1), + .PORT_AFI_BA_WIDTH (1), + .PORT_AFI_BG_WIDTH (1), + .PORT_AFI_C_WIDTH (1), + .PORT_AFI_CKE_WIDTH (1), + .PORT_AFI_CS_N_WIDTH (1), + .PORT_AFI_RM_WIDTH (1), + .PORT_AFI_ODT_WIDTH (1), + .PORT_AFI_RAS_N_WIDTH (1), + .PORT_AFI_CAS_N_WIDTH (1), + .PORT_AFI_WE_N_WIDTH (1), + .PORT_AFI_RST_N_WIDTH (1), + .PORT_AFI_ACT_N_WIDTH (1), + .PORT_AFI_PAR_WIDTH (1), + .PORT_AFI_CA_WIDTH (1), + .PORT_AFI_REF_N_WIDTH (1), + .PORT_AFI_WPS_N_WIDTH (1), + .PORT_AFI_RPS_N_WIDTH (1), + .PORT_AFI_DOFF_N_WIDTH (1), + .PORT_AFI_LD_N_WIDTH (1), + .PORT_AFI_RW_N_WIDTH (1), + .PORT_AFI_LBK0_N_WIDTH (1), + .PORT_AFI_LBK1_N_WIDTH (1), + .PORT_AFI_CFG_N_WIDTH (1), + .PORT_AFI_AP_WIDTH (1), + .PORT_AFI_AINV_WIDTH (1), + .PORT_AFI_DM_WIDTH (1), + .PORT_AFI_DM_N_WIDTH (1), + .PORT_AFI_BWS_N_WIDTH (1), + .PORT_AFI_RDATA_DBI_N_WIDTH (1), + .PORT_AFI_WDATA_DBI_N_WIDTH (1), + .PORT_AFI_RDATA_DINV_WIDTH (1), + .PORT_AFI_WDATA_DINV_WIDTH (1), + .PORT_AFI_DQS_BURST_WIDTH (1), + .PORT_AFI_WDATA_VALID_WIDTH (1), + .PORT_AFI_WDATA_WIDTH (1), + .PORT_AFI_RDATA_EN_FULL_WIDTH (1), + .PORT_AFI_RDATA_WIDTH (1), + .PORT_AFI_RDATA_VALID_WIDTH (1), + .PORT_AFI_RRANK_WIDTH (1), + .PORT_AFI_WRANK_WIDTH (1), + .PORT_AFI_ALERT_N_WIDTH (1), + .PORT_AFI_PE_N_WIDTH (1), + .PORT_CTRL_AST_CMD_DATA_WIDTH (1), + .PORT_CTRL_AST_WR_DATA_WIDTH (1), + .PORT_CTRL_AST_RD_DATA_WIDTH (1), + .PORT_CTRL_AMM_ADDRESS_WIDTH (26), + .PORT_CTRL_AMM_RDATA_WIDTH (512), + .PORT_CTRL_AMM_WDATA_WIDTH (512), + .PORT_CTRL_AMM_BCOUNT_WIDTH (7), + .PORT_CTRL_AMM_BYTEEN_WIDTH (64), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (16), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (4), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (15), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (13), + .PORT_CTRL_ECC_READ_INFO_WIDTH (3), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (3), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (12), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (10), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (32), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (2), + .PORT_HPS_EMIF_H2E_WIDTH (4096), + .PORT_HPS_EMIF_E2H_WIDTH (4096), + .PORT_HPS_EMIF_H2E_GP_WIDTH (2), + .PORT_HPS_EMIF_E2H_GP_WIDTH (1), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (24), + .PORT_CAL_DEBUG_RDATA_WIDTH (32), + .PORT_CAL_DEBUG_WDATA_WIDTH (32), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (4), + .PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH (24), + .PORT_CAL_DEBUG_OUT_RDATA_WIDTH (32), + .PORT_CAL_DEBUG_OUT_WDATA_WIDTH (32), + .PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH (4), + .PORT_CAL_MASTER_ADDRESS_WIDTH (16), + .PORT_CAL_MASTER_RDATA_WIDTH (32), + .PORT_CAL_MASTER_WDATA_WIDTH (32), + .PORT_CAL_MASTER_BYTEEN_WIDTH (4), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (8), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (8), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (9), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (8), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (8), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (4), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (3), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (2), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (2), + .PLL_VCO_FREQ_MHZ_INT (1067), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (1), + .PLL_PHY_CLK_VCO_PHASE (1), + .PLL_VCO_FREQ_PS_STR ("938 ps"), + .PLL_REF_CLK_FREQ_PS_STR ("3752 ps"), + .PLL_REF_CLK_FREQ_PS (3752), + .PLL_SIM_VCO_FREQ_PS (944), + .PLL_SIM_PHYCLK_0_FREQ_PS (1888), + .PLL_SIM_PHYCLK_1_FREQ_PS (3776), + .PLL_SIM_PHYCLK_FB_FREQ_PS (3776), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (118), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (6608), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (6608), + .PLL_M_CNT_HIGH (2), + .PLL_M_CNT_LOW (2), + .PLL_N_CNT_HIGH (256), + .PLL_N_CNT_LOW (256), + .PLL_M_CNT_BYPASS_EN ("false"), + .PLL_N_CNT_BYPASS_EN ("true"), + .PLL_M_CNT_EVEN_DUTY_EN ("false"), + .PLL_N_CNT_EVEN_DUTY_EN ("false"), + .PLL_FBCLK_MUX_1 ("pll_fbclk_mux_1_glb"), + .PLL_FBCLK_MUX_2 ("pll_fbclk_mux_2_m_cnt"), + .PLL_M_CNT_IN_SRC ("c_m_cnt_in_src_ph_mux_clk"), + .PLL_CP_SETTING ("pll_cp_setting15"), + .PLL_BW_CTRL ("pll_bw_res_setting2"), + .PLL_BW_SEL ("high"), + .PLL_C_CNT_HIGH_0 (2), + .PLL_C_CNT_LOW_0 (2), + .PLL_C_CNT_PRST_0 (1), + .PLL_C_CNT_PH_MUX_PRST_0 (1), + .PLL_C_CNT_BYPASS_EN_0 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_0 ("false"), + .PLL_C_CNT_FREQ_PS_STR_0 ("3752 ps"), + .PLL_C_CNT_PHASE_PS_STR_0 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_0 (50), + .PLL_C_CNT_OUT_EN_0 ("true"), + .PLL_C_CNT_HIGH_1 (1), + .PLL_C_CNT_LOW_1 (1), + .PLL_C_CNT_PRST_1 (1), + .PLL_C_CNT_PH_MUX_PRST_1 (1), + .PLL_C_CNT_BYPASS_EN_1 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_1 ("false"), + .PLL_C_CNT_FREQ_PS_STR_1 ("1876 ps"), + .PLL_C_CNT_PHASE_PS_STR_1 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_1 (50), + .PLL_C_CNT_OUT_EN_1 ("true"), + .PLL_C_CNT_HIGH_2 (2), + .PLL_C_CNT_LOW_2 (2), + .PLL_C_CNT_PRST_2 (1), + .PLL_C_CNT_PH_MUX_PRST_2 (1), + .PLL_C_CNT_BYPASS_EN_2 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_2 ("false"), + .PLL_C_CNT_FREQ_PS_STR_2 ("3752 ps"), + .PLL_C_CNT_PHASE_PS_STR_2 ("117 ps"), + .PLL_C_CNT_DUTY_CYCLE_2 (50), + .PLL_C_CNT_OUT_EN_2 ("true"), + .PLL_C_CNT_HIGH_3 (4), + .PLL_C_CNT_LOW_3 (3), + .PLL_C_CNT_PRST_3 (1), + .PLL_C_CNT_PH_MUX_PRST_3 (0), + .PLL_C_CNT_BYPASS_EN_3 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_3 ("true"), + .PLL_C_CNT_FREQ_PS_STR_3 ("6566 ps"), + .PLL_C_CNT_PHASE_PS_STR_3 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_3 (50), + .PLL_C_CNT_OUT_EN_3 ("true"), + .PLL_C_CNT_HIGH_4 (4), + .PLL_C_CNT_LOW_4 (3), + .PLL_C_CNT_PRST_4 (1), + .PLL_C_CNT_PH_MUX_PRST_4 (0), + .PLL_C_CNT_BYPASS_EN_4 ("false"), + .PLL_C_CNT_EVEN_DUTY_EN_4 ("true"), + .PLL_C_CNT_FREQ_PS_STR_4 ("6566 ps"), + .PLL_C_CNT_PHASE_PS_STR_4 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_4 (50), + .PLL_C_CNT_OUT_EN_4 ("true"), + .PLL_C_CNT_HIGH_5 (256), + .PLL_C_CNT_LOW_5 (256), + .PLL_C_CNT_PRST_5 (1), + .PLL_C_CNT_PH_MUX_PRST_5 (0), + .PLL_C_CNT_BYPASS_EN_5 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_5 ("false"), + .PLL_C_CNT_FREQ_PS_STR_5 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_5 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_5 (50), + .PLL_C_CNT_OUT_EN_5 ("false"), + .PLL_C_CNT_HIGH_6 (256), + .PLL_C_CNT_LOW_6 (256), + .PLL_C_CNT_PRST_6 (1), + .PLL_C_CNT_PH_MUX_PRST_6 (0), + .PLL_C_CNT_BYPASS_EN_6 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_6 ("false"), + .PLL_C_CNT_FREQ_PS_STR_6 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_6 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_6 (50), + .PLL_C_CNT_OUT_EN_6 ("false"), + .PLL_C_CNT_HIGH_7 (256), + .PLL_C_CNT_LOW_7 (256), + .PLL_C_CNT_PRST_7 (1), + .PLL_C_CNT_PH_MUX_PRST_7 (0), + .PLL_C_CNT_BYPASS_EN_7 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_7 ("false"), + .PLL_C_CNT_FREQ_PS_STR_7 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_7 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_7 (50), + .PLL_C_CNT_OUT_EN_7 ("false"), + .PLL_C_CNT_HIGH_8 (256), + .PLL_C_CNT_LOW_8 (256), + .PLL_C_CNT_PRST_8 (1), + .PLL_C_CNT_PH_MUX_PRST_8 (0), + .PLL_C_CNT_BYPASS_EN_8 ("true"), + .PLL_C_CNT_EVEN_DUTY_EN_8 ("false"), + .PLL_C_CNT_FREQ_PS_STR_8 ("0.0 MHz"), + .PLL_C_CNT_PHASE_PS_STR_8 ("0 ps"), + .PLL_C_CNT_DUTY_CYCLE_8 (50), + .PLL_C_CNT_OUT_EN_8 ("false") + ) arch ( + .oct_rzqin (oct_rzqin), // oct.oct_rzqin + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .local_cal_success (local_cal_success), // status.local_cal_success + .local_cal_fail (local_cal_fail), // .local_cal_fail + .emif_usr_reset_n (emif_usr_reset_n), // emif_usr_reset_n.reset_n + .emif_usr_clk (emif_usr_clk), // emif_usr_clk.clk + .cal_slave_reset_n (arch_cal_slave_reset_n_reset), // cal_slave_reset_n.reset_n + .cal_slave_clk (arch_cal_slave_clk_clk), // cal_slave_clk.clk + .cal_slave_reset_n_in (arch_cal_slave_reset_n_reset), // cal_slave_reset_n_in.reset_n + .cal_slave_clk_in (arch_cal_slave_clk_clk), // cal_slave_clk_in.clk + .clks_sharing_slave_in (clks_sharing_slave_in), // clks_sharing_slave_in.clks_sharing + .amm_ready_0 (amm_ready_0), // ctrl_amm_0.waitrequest_n + .amm_read_0 (amm_read_0), // .read + .amm_write_0 (amm_write_0), // .write + .amm_address_0 (amm_address_0), // .address + .amm_readdata_0 (amm_readdata_0), // .readdata + .amm_writedata_0 (amm_writedata_0), // .writedata + .amm_burstcount_0 (amm_burstcount_0), // .burstcount + .amm_byteenable_0 (amm_byteenable_0), // .byteenable + .amm_readdatavalid_0 (amm_readdatavalid_0), // .readdatavalid + .cal_master_waitrequest (arch_cal_master_waitrequest), // cal_master.waitrequest + .cal_master_read (arch_cal_master_read), // .read + .cal_master_write (arch_cal_master_write), // .write + .cal_master_addr (arch_cal_master_address), // .address + .cal_master_read_data (arch_cal_master_readdata), // .readdata + .cal_master_write_data (arch_cal_master_writedata), // .writedata + .cal_master_byteenable (arch_cal_master_byteenable), // .byteenable + .cal_master_read_data_valid (arch_cal_master_readdatavalid), // .readdatavalid + .cal_master_burstcount (arch_cal_master_burstcount), // .burstcount + .cal_master_debugaccess (arch_cal_master_debugaccess), // .debugaccess + .global_reset_n (1'b0), // (terminated) + .pll_ref_clk (1'b0), // (terminated) + .pll_locked (), // (terminated) + .pll_extra_clk_0 (), // (terminated) + .pll_extra_clk_1 (), // (terminated) + .pll_extra_clk_2 (), // (terminated) + .pll_extra_clk_3 (), // (terminated) + .mem_c (), // (terminated) + .mem_rm (), // (terminated) + .mem_dk (), // (terminated) + .mem_dk_n (), // (terminated) + .mem_dka (), // (terminated) + .mem_dka_n (), // (terminated) + .mem_dkb (), // (terminated) + .mem_dkb_n (), // (terminated) + .mem_k (), // (terminated) + .mem_k_n (), // (terminated) + .mem_ras_n (), // (terminated) + .mem_cas_n (), // (terminated) + .mem_we_n (), // (terminated) + .mem_ca (), // (terminated) + .mem_ref_n (), // (terminated) + .mem_wps_n (), // (terminated) + .mem_rps_n (), // (terminated) + .mem_doff_n (), // (terminated) + .mem_lda_n (), // (terminated) + .mem_ldb_n (), // (terminated) + .mem_rwa_n (), // (terminated) + .mem_rwb_n (), // (terminated) + .mem_lbk0_n (), // (terminated) + .mem_lbk1_n (), // (terminated) + .mem_cfg_n (), // (terminated) + .mem_ap (), // (terminated) + .mem_ainv (), // (terminated) + .mem_dm (), // (terminated) + .mem_bws_n (), // (terminated) + .mem_d (), // (terminated) + .mem_dqa (), // (terminated) + .mem_dqb (), // (terminated) + .mem_dinva (), // (terminated) + .mem_dinvb (), // (terminated) + .mem_q (1'b0), // (terminated) + .mem_qk (1'b0), // (terminated) + .mem_qk_n (1'b0), // (terminated) + .mem_qka (1'b0), // (terminated) + .mem_qka_n (1'b0), // (terminated) + .mem_qkb (1'b0), // (terminated) + .mem_qkb_n (1'b0), // (terminated) + .mem_cq (1'b0), // (terminated) + .mem_cq_n (1'b0), // (terminated) + .mem_pe_n (1'b0), // (terminated) + .vid_cal_done_persist (1'b0), // (terminated) + .afi_reset_n (), // (terminated) + .afi_clk (), // (terminated) + .afi_half_clk (), // (terminated) + .emif_usr_half_clk (), // (terminated) + .emif_usr_reset_n_sec (), // (terminated) + .emif_usr_clk_sec (), // (terminated) + .emif_usr_half_clk_sec (), // (terminated) + .cal_master_reset_n (), // (terminated) + .cal_master_clk (), // (terminated) + .cal_debug_reset_n (1'b0), // (terminated) + .cal_debug_clk (1'b0), // (terminated) + .cal_debug_out_reset_n (), // (terminated) + .cal_debug_out_clk (), // (terminated) + .clks_sharing_master_out (), // (terminated) + .afi_cal_success (), // (terminated) + .afi_cal_fail (), // (terminated) + .afi_cal_req (1'b0), // (terminated) + .afi_rlat (), // (terminated) + .afi_wlat (), // (terminated) + .afi_seq_busy (), // (terminated) + .afi_ctl_refresh_done (1'b0), // (terminated) + .afi_ctl_long_idle (1'b0), // (terminated) + .afi_mps_req (1'b0), // (terminated) + .afi_mps_ack (), // (terminated) + .afi_addr (1'b0), // (terminated) + .afi_ba (1'b0), // (terminated) + .afi_bg (1'b0), // (terminated) + .afi_c (1'b0), // (terminated) + .afi_cke (1'b0), // (terminated) + .afi_cs_n (1'b0), // (terminated) + .afi_rm (1'b0), // (terminated) + .afi_odt (1'b0), // (terminated) + .afi_ras_n (1'b0), // (terminated) + .afi_cas_n (1'b0), // (terminated) + .afi_we_n (1'b0), // (terminated) + .afi_rst_n (1'b0), // (terminated) + .afi_act_n (1'b0), // (terminated) + .afi_par (1'b0), // (terminated) + .afi_ca (1'b0), // (terminated) + .afi_ref_n (1'b0), // (terminated) + .afi_wps_n (1'b0), // (terminated) + .afi_rps_n (1'b0), // (terminated) + .afi_doff_n (1'b0), // (terminated) + .afi_ld_n (1'b0), // (terminated) + .afi_rw_n (1'b0), // (terminated) + .afi_lbk0_n (1'b0), // (terminated) + .afi_lbk1_n (1'b0), // (terminated) + .afi_cfg_n (1'b0), // (terminated) + .afi_ap (1'b0), // (terminated) + .afi_ainv (1'b0), // (terminated) + .afi_dm (1'b0), // (terminated) + .afi_dm_n (1'b0), // (terminated) + .afi_bws_n (1'b0), // (terminated) + .afi_rdata_dbi_n (), // (terminated) + .afi_wdata_dbi_n (1'b0), // (terminated) + .afi_rdata_dinv (), // (terminated) + .afi_wdata_dinv (1'b0), // (terminated) + .afi_dqs_burst (1'b0), // (terminated) + .afi_wdata_valid (1'b0), // (terminated) + .afi_wdata (1'b0), // (terminated) + .afi_rdata_en_full (1'b0), // (terminated) + .afi_rdata (), // (terminated) + .afi_rdata_valid (), // (terminated) + .afi_rrank (1'b0), // (terminated) + .afi_wrank (1'b0), // (terminated) + .afi_alert_n (), // (terminated) + .afi_pe_n (), // (terminated) + .ast_cmd_data_0 (1'b0), // (terminated) + .ast_cmd_valid_0 (1'b0), // (terminated) + .ast_cmd_ready_0 (), // (terminated) + .ast_cmd_data_1 (1'b0), // (terminated) + .ast_cmd_valid_1 (1'b0), // (terminated) + .ast_cmd_ready_1 (), // (terminated) + .ast_wr_data_0 (1'b0), // (terminated) + .ast_wr_valid_0 (1'b0), // (terminated) + .ast_wr_ready_0 (), // (terminated) + .ast_wr_data_1 (1'b0), // (terminated) + .ast_wr_valid_1 (1'b0), // (terminated) + .ast_wr_ready_1 (), // (terminated) + .ast_rd_data_0 (), // (terminated) + .ast_rd_valid_0 (), // (terminated) + .ast_rd_ready_0 (1'b0), // (terminated) + .ast_rd_data_1 (), // (terminated) + .ast_rd_valid_1 (), // (terminated) + .ast_rd_ready_1 (1'b0), // (terminated) + .amm_beginbursttransfer_0 (1'b0), // (terminated) + .amm_beginbursttransfer_1 (1'b0), // (terminated) + .ctrl_user_priority_hi_0 (1'b0), // (terminated) + .ctrl_user_priority_hi_1 (1'b0), // (terminated) + .ctrl_auto_precharge_req_0 (1'b0), // (terminated) + .ctrl_auto_precharge_req_1 (1'b0), // (terminated) + .ctrl_user_refresh_req (4'b0000), // (terminated) + .ctrl_user_refresh_bank (16'b0000000000000000), // (terminated) + .ctrl_user_refresh_ack (), // (terminated) + .ctrl_self_refresh_req (4'b0000), // (terminated) + .ctrl_self_refresh_ack (), // (terminated) + .ctrl_will_refresh (), // (terminated) + .ctrl_deep_power_down_req (1'b0), // (terminated) + .ctrl_deep_power_down_ack (), // (terminated) + .ctrl_power_down_ack (), // (terminated) + .ctrl_zq_cal_long_req (1'b0), // (terminated) + .ctrl_zq_cal_short_req (1'b0), // (terminated) + .ctrl_zq_cal_ack (), // (terminated) + .ctrl_ecc_write_info_0 (15'b000000000000000), // (terminated) + .ctrl_ecc_rdata_id_0 (), // (terminated) + .ctrl_ecc_read_info_0 (), // (terminated) + .ctrl_ecc_cmd_info_0 (), // (terminated) + .ctrl_ecc_idle_0 (), // (terminated) + .ctrl_ecc_wr_pointer_info_0 (), // (terminated) + .ctrl_ecc_write_info_1 (15'b000000000000000), // (terminated) + .ctrl_ecc_rdata_id_1 (), // (terminated) + .ctrl_ecc_read_info_1 (), // (terminated) + .ctrl_ecc_cmd_info_1 (), // (terminated) + .ctrl_ecc_idle_1 (), // (terminated) + .ctrl_ecc_wr_pointer_info_1 (), // (terminated) + .mmr_slave_waitrequest_0 (), // (terminated) + .mmr_slave_read_0 (1'b0), // (terminated) + .mmr_slave_write_0 (1'b0), // (terminated) + .mmr_slave_address_0 (10'b0000000000), // (terminated) + .mmr_slave_readdata_0 (), // (terminated) + .mmr_slave_writedata_0 (32'b00000000000000000000000000000000), // (terminated) + .mmr_slave_burstcount_0 (2'b00), // (terminated) + .mmr_slave_beginbursttransfer_0 (1'b0), // (terminated) + .mmr_slave_readdatavalid_0 (), // (terminated) + .mmr_slave_waitrequest_1 (), // (terminated) + .mmr_slave_read_1 (1'b0), // (terminated) + .mmr_slave_write_1 (1'b0), // (terminated) + .mmr_slave_address_1 (10'b0000000000), // (terminated) + .mmr_slave_readdata_1 (), // (terminated) + .mmr_slave_writedata_1 (32'b00000000000000000000000000000000), // (terminated) + .mmr_slave_burstcount_1 (2'b00), // (terminated) + .mmr_slave_beginbursttransfer_1 (1'b0), // (terminated) + .mmr_slave_readdatavalid_1 (), // (terminated) + .hps_to_emif (4096'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .emif_to_hps (), // (terminated) + .hps_to_emif_gp (2'b00), // (terminated) + .emif_to_hps_gp (), // (terminated) + .cal_debug_waitrequest (), // (terminated) + .cal_debug_read (1'b0), // (terminated) + .cal_debug_write (1'b0), // (terminated) + .cal_debug_addr (24'b000000000000000000000000), // (terminated) + .cal_debug_read_data (), // (terminated) + .cal_debug_write_data (32'b00000000000000000000000000000000), // (terminated) + .cal_debug_byteenable (4'b0000), // (terminated) + .cal_debug_read_data_valid (), // (terminated) + .cal_debug_out_waitrequest (1'b0), // (terminated) + .cal_debug_out_read (), // (terminated) + .cal_debug_out_write (), // (terminated) + .cal_debug_out_addr (), // (terminated) + .cal_debug_out_read_data (32'b00000000000000000000000000000000), // (terminated) + .cal_debug_out_write_data (), // (terminated) + .cal_debug_out_byteenable (), // (terminated) + .cal_debug_out_read_data_valid (1'b0), // (terminated) + .ioaux_pio_in (8'b00000000), // (terminated) + .ioaux_pio_out (), // (terminated) + .pa_dprio_clk (1'b0), // (terminated) + .pa_dprio_read (1'b0), // (terminated) + .pa_dprio_reg_addr (9'b000000000), // (terminated) + .pa_dprio_rst_n (1'b0), // (terminated) + .pa_dprio_write (1'b0), // (terminated) + .pa_dprio_writedata (8'b00000000), // (terminated) + .pa_dprio_block_select (), // (terminated) + .pa_dprio_readdata (), // (terminated) + .pll_phase_en (1'b0), // (terminated) + .pll_up_dn (1'b0), // (terminated) + .pll_cnt_sel (4'b0000), // (terminated) + .pll_num_phase_shifts (3'b000), // (terminated) + .pll_phase_done (), // (terminated) + .dft_core_clk_buf_out (), // (terminated) + .dft_core_clk_locked (), // (terminated) + .amm_ready_1 (), // (terminated) + .amm_read_1 (1'b0), // (terminated) + .amm_write_1 (1'b0), // (terminated) + .amm_address_1 (26'b00000000000000000000000000), // (terminated) + .amm_readdata_1 (), // (terminated) + .amm_writedata_1 (512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .amm_burstcount_1 (7'b0000000), // (terminated) + .amm_byteenable_1 (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated) + .amm_readdatavalid_1 () // (terminated) + ); + + ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy cal_slave_component ( + .avl_waitrequest (arch_cal_master_waitrequest), // avl.waitrequest + .avl_readdata (arch_cal_master_readdata), // .readdata + .avl_readdatavalid (arch_cal_master_readdatavalid), // .readdatavalid + .avl_burstcount (arch_cal_master_burstcount), // .burstcount + .avl_writedata (arch_cal_master_writedata), // .writedata + .avl_address (arch_cal_master_address), // .address + .avl_write (arch_cal_master_write), // .write + .avl_read (arch_cal_master_read), // .read + .avl_byteenable (arch_cal_master_byteenable), // .byteenable + .avl_debugaccess (arch_cal_master_debugaccess), // .debugaccess + .clk_clk (arch_cal_slave_clk_clk), // clk.clk + .rst_reset (~arch_cal_slave_reset_n_reset) // rst.reset + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa.sv new file mode 100644 index 000000000000..331052487757 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa.sv @@ -0,0 +1,3573 @@ +module ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa #( + parameter PROTOCOL_ENUM = "", + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 0, + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_CALIBRATED_OCT = 0, + parameter PHY_AC_CALIBRATED_OCT = 0, + parameter PHY_CK_CALIBRATED_OCT = 0, + parameter PHY_DATA_CALIBRATED_OCT = 0, + parameter PHY_HPS_ENABLE_EARLY_RELEASE = 0, + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter MEM_FORMAT_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 0, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter SILICON_REV = "", + parameter IS_HPS = 0, + parameter IS_VID = 0, + parameter USER_CLK_RATIO = 0, + parameter C2P_P2C_CLK_RATIO = 0, + parameter PHY_HMC_CLK_RATIO = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 0, + parameter DIAG_ABSTRACT_PHY_RLAT = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 0, + parameter DQS_BUS_MODE_ENUM = "", + parameter AC_PIN_MAP_SCHEME = "", + parameter NUM_OF_HMC_PORTS = 0, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + parameter REGISTER_AFI = 0, + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 0, + parameter SEQ_SIM_OSC_FREQ_MHZ = 0, + parameter NUM_OF_RTL_TILES = 0, + parameter PRI_RDATA_TILE_INDEX = 0, + parameter PRI_RDATA_LANE_INDEX = 0, + parameter PRI_WDATA_TILE_INDEX = 0, + parameter PRI_WDATA_LANE_INDEX = 0, + parameter PRI_AC_TILE_INDEX = 0, + parameter SEC_RDATA_TILE_INDEX = 0, + parameter SEC_RDATA_LANE_INDEX = 0, + parameter SEC_WDATA_TILE_INDEX = 0, + parameter SEC_WDATA_LANE_INDEX = 0, + parameter SEC_AC_TILE_INDEX = 0, + parameter LANES_USAGE_0 = 0, + parameter LANES_USAGE_1 = 0, + parameter LANES_USAGE_2 = 0, + parameter LANES_USAGE_3 = 0, + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_0 = 0, + parameter PINS_USAGE_1 = 0, + parameter PINS_USAGE_2 = 0, + parameter PINS_USAGE_3 = 0, + parameter PINS_USAGE_4 = 0, + parameter PINS_USAGE_5 = 0, + parameter PINS_USAGE_6 = 0, + parameter PINS_USAGE_7 = 0, + parameter PINS_USAGE_8 = 0, + parameter PINS_USAGE_9 = 0, + parameter PINS_USAGE_10 = 0, + parameter PINS_USAGE_11 = 0, + parameter PINS_USAGE_12 = 0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_0 = 0, + parameter PINS_RATE_1 = 0, + parameter PINS_RATE_2 = 0, + parameter PINS_RATE_3 = 0, + parameter PINS_RATE_4 = 0, + parameter PINS_RATE_5 = 0, + parameter PINS_RATE_6 = 0, + parameter PINS_RATE_7 = 0, + parameter PINS_RATE_8 = 0, + parameter PINS_RATE_9 = 0, + parameter PINS_RATE_10 = 0, + parameter PINS_RATE_11 = 0, + parameter PINS_RATE_12 = 0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter PINS_WDB_0 = 0, + parameter PINS_WDB_1 = 0, + parameter PINS_WDB_2 = 0, + parameter PINS_WDB_3 = 0, + parameter PINS_WDB_4 = 0, + parameter PINS_WDB_5 = 0, + parameter PINS_WDB_6 = 0, + parameter PINS_WDB_7 = 0, + parameter PINS_WDB_8 = 0, + parameter PINS_WDB_9 = 0, + parameter PINS_WDB_10 = 0, + parameter PINS_WDB_11 = 0, + parameter PINS_WDB_12 = 0, + parameter PINS_WDB_13 = 0, + parameter PINS_WDB_14 = 0, + parameter PINS_WDB_15 = 0, + parameter PINS_WDB_16 = 0, + parameter PINS_WDB_17 = 0, + parameter PINS_WDB_18 = 0, + parameter PINS_WDB_19 = 0, + parameter PINS_WDB_20 = 0, + parameter PINS_WDB_21 = 0, + parameter PINS_WDB_22 = 0, + parameter PINS_WDB_23 = 0, + parameter PINS_WDB_24 = 0, + parameter PINS_WDB_25 = 0, + parameter PINS_WDB_26 = 0, + parameter PINS_WDB_27 = 0, + parameter PINS_WDB_28 = 0, + parameter PINS_WDB_29 = 0, + parameter PINS_WDB_30 = 0, + parameter PINS_WDB_31 = 0, + parameter PINS_WDB_32 = 0, + parameter PINS_WDB_33 = 0, + parameter PINS_WDB_34 = 0, + parameter PINS_WDB_35 = 0, + parameter PINS_WDB_36 = 0, + parameter PINS_WDB_37 = 0, + parameter PINS_WDB_38 = 0, + parameter PINS_WDB_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_0 = 0, + parameter PINS_DATA_IN_MODE_1 = 0, + parameter PINS_DATA_IN_MODE_2 = 0, + parameter PINS_DATA_IN_MODE_3 = 0, + parameter PINS_DATA_IN_MODE_4 = 0, + parameter PINS_DATA_IN_MODE_5 = 0, + parameter PINS_DATA_IN_MODE_6 = 0, + parameter PINS_DATA_IN_MODE_7 = 0, + parameter PINS_DATA_IN_MODE_8 = 0, + parameter PINS_DATA_IN_MODE_9 = 0, + parameter PINS_DATA_IN_MODE_10 = 0, + parameter PINS_DATA_IN_MODE_11 = 0, + parameter PINS_DATA_IN_MODE_12 = 0, + parameter PINS_DATA_IN_MODE_13 = 0, + parameter PINS_DATA_IN_MODE_14 = 0, + parameter PINS_DATA_IN_MODE_15 = 0, + parameter PINS_DATA_IN_MODE_16 = 0, + parameter PINS_DATA_IN_MODE_17 = 0, + parameter PINS_DATA_IN_MODE_18 = 0, + parameter PINS_DATA_IN_MODE_19 = 0, + parameter PINS_DATA_IN_MODE_20 = 0, + parameter PINS_DATA_IN_MODE_21 = 0, + parameter PINS_DATA_IN_MODE_22 = 0, + parameter PINS_DATA_IN_MODE_23 = 0, + parameter PINS_DATA_IN_MODE_24 = 0, + parameter PINS_DATA_IN_MODE_25 = 0, + parameter PINS_DATA_IN_MODE_26 = 0, + parameter PINS_DATA_IN_MODE_27 = 0, + parameter PINS_DATA_IN_MODE_28 = 0, + parameter PINS_DATA_IN_MODE_29 = 0, + parameter PINS_DATA_IN_MODE_30 = 0, + parameter PINS_DATA_IN_MODE_31 = 0, + parameter PINS_DATA_IN_MODE_32 = 0, + parameter PINS_DATA_IN_MODE_33 = 0, + parameter PINS_DATA_IN_MODE_34 = 0, + parameter PINS_DATA_IN_MODE_35 = 0, + parameter PINS_DATA_IN_MODE_36 = 0, + parameter PINS_DATA_IN_MODE_37 = 0, + parameter PINS_DATA_IN_MODE_38 = 0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_0 = 0, + parameter PINS_C2L_DRIVEN_1 = 0, + parameter PINS_C2L_DRIVEN_2 = 0, + parameter PINS_C2L_DRIVEN_3 = 0, + parameter PINS_C2L_DRIVEN_4 = 0, + parameter PINS_C2L_DRIVEN_5 = 0, + parameter PINS_C2L_DRIVEN_6 = 0, + parameter PINS_C2L_DRIVEN_7 = 0, + parameter PINS_C2L_DRIVEN_8 = 0, + parameter PINS_C2L_DRIVEN_9 = 0, + parameter PINS_C2L_DRIVEN_10 = 0, + parameter PINS_C2L_DRIVEN_11 = 0, + parameter PINS_C2L_DRIVEN_12 = 0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_DB_IN_BYPASS_0 = 0, + parameter PINS_DB_IN_BYPASS_1 = 0, + parameter PINS_DB_IN_BYPASS_2 = 0, + parameter PINS_DB_IN_BYPASS_3 = 0, + parameter PINS_DB_IN_BYPASS_4 = 0, + parameter PINS_DB_IN_BYPASS_5 = 0, + parameter PINS_DB_IN_BYPASS_6 = 0, + parameter PINS_DB_IN_BYPASS_7 = 0, + parameter PINS_DB_IN_BYPASS_8 = 0, + parameter PINS_DB_IN_BYPASS_9 = 0, + parameter PINS_DB_IN_BYPASS_10 = 0, + parameter PINS_DB_IN_BYPASS_11 = 0, + parameter PINS_DB_IN_BYPASS_12 = 0, + parameter PINS_DB_IN_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OUT_BYPASS_0 = 0, + parameter PINS_DB_OUT_BYPASS_1 = 0, + parameter PINS_DB_OUT_BYPASS_2 = 0, + parameter PINS_DB_OUT_BYPASS_3 = 0, + parameter PINS_DB_OUT_BYPASS_4 = 0, + parameter PINS_DB_OUT_BYPASS_5 = 0, + parameter PINS_DB_OUT_BYPASS_6 = 0, + parameter PINS_DB_OUT_BYPASS_7 = 0, + parameter PINS_DB_OUT_BYPASS_8 = 0, + parameter PINS_DB_OUT_BYPASS_9 = 0, + parameter PINS_DB_OUT_BYPASS_10 = 0, + parameter PINS_DB_OUT_BYPASS_11 = 0, + parameter PINS_DB_OUT_BYPASS_12 = 0, + parameter PINS_DB_OUT_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OE_BYPASS_0 = 0, + parameter PINS_DB_OE_BYPASS_1 = 0, + parameter PINS_DB_OE_BYPASS_2 = 0, + parameter PINS_DB_OE_BYPASS_3 = 0, + parameter PINS_DB_OE_BYPASS_4 = 0, + parameter PINS_DB_OE_BYPASS_5 = 0, + parameter PINS_DB_OE_BYPASS_6 = 0, + parameter PINS_DB_OE_BYPASS_7 = 0, + parameter PINS_DB_OE_BYPASS_8 = 0, + parameter PINS_DB_OE_BYPASS_9 = 0, + parameter PINS_DB_OE_BYPASS_10 = 0, + parameter PINS_DB_OE_BYPASS_11 = 0, + parameter PINS_DB_OE_BYPASS_12 = 0, + parameter PINS_DB_OE_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_WR_0 = 0, + parameter PINS_INVERT_WR_1 = 0, + parameter PINS_INVERT_WR_2 = 0, + parameter PINS_INVERT_WR_3 = 0, + parameter PINS_INVERT_WR_4 = 0, + parameter PINS_INVERT_WR_5 = 0, + parameter PINS_INVERT_WR_6 = 0, + parameter PINS_INVERT_WR_7 = 0, + parameter PINS_INVERT_WR_8 = 0, + parameter PINS_INVERT_WR_9 = 0, + parameter PINS_INVERT_WR_10 = 0, + parameter PINS_INVERT_WR_11 = 0, + parameter PINS_INVERT_WR_12 = 0, + parameter PINS_INVERT_WR_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_OE_0 = 0, + parameter PINS_INVERT_OE_1 = 0, + parameter PINS_INVERT_OE_2 = 0, + parameter PINS_INVERT_OE_3 = 0, + parameter PINS_INVERT_OE_4 = 0, + parameter PINS_INVERT_OE_5 = 0, + parameter PINS_INVERT_OE_6 = 0, + parameter PINS_INVERT_OE_7 = 0, + parameter PINS_INVERT_OE_8 = 0, + parameter PINS_INVERT_OE_9 = 0, + parameter PINS_INVERT_OE_10 = 0, + parameter PINS_INVERT_OE_11 = 0, + parameter PINS_INVERT_OE_12 = 0, + parameter PINS_INVERT_OE_AUTOGEN_WCNT = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_0 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_1 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_2 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_3 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_4 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_5 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_6 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_7 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_8 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_9 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_10 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_11 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_12 = 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_0 = 0, + parameter PINS_OCT_MODE_1 = 0, + parameter PINS_OCT_MODE_2 = 0, + parameter PINS_OCT_MODE_3 = 0, + parameter PINS_OCT_MODE_4 = 0, + parameter PINS_OCT_MODE_5 = 0, + parameter PINS_OCT_MODE_6 = 0, + parameter PINS_OCT_MODE_7 = 0, + parameter PINS_OCT_MODE_8 = 0, + parameter PINS_OCT_MODE_9 = 0, + parameter PINS_OCT_MODE_10 = 0, + parameter PINS_OCT_MODE_11 = 0, + parameter PINS_OCT_MODE_12 = 0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_GPIO_MODE_0 = 0, + parameter PINS_GPIO_MODE_1 = 0, + parameter PINS_GPIO_MODE_2 = 0, + parameter PINS_GPIO_MODE_3 = 0, + parameter PINS_GPIO_MODE_4 = 0, + parameter PINS_GPIO_MODE_5 = 0, + parameter PINS_GPIO_MODE_6 = 0, + parameter PINS_GPIO_MODE_7 = 0, + parameter PINS_GPIO_MODE_8 = 0, + parameter PINS_GPIO_MODE_9 = 0, + parameter PINS_GPIO_MODE_10 = 0, + parameter PINS_GPIO_MODE_11 = 0, + parameter PINS_GPIO_MODE_12 = 0, + parameter PINS_GPIO_MODE_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_0 = 0, + parameter CENTER_TIDS_1 = 0, + parameter CENTER_TIDS_2 = 0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_0 = 0, + parameter HMC_TIDS_1 = 0, + parameter HMC_TIDS_2 = 0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_0 = 0, + parameter LANE_TIDS_1 = 0, + parameter LANE_TIDS_2 = 0, + parameter LANE_TIDS_3 = 0, + parameter LANE_TIDS_4 = 0, + parameter LANE_TIDS_5 = 0, + parameter LANE_TIDS_6 = 0, + parameter LANE_TIDS_7 = 0, + parameter LANE_TIDS_8 = 0, + parameter LANE_TIDS_9 = 0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 0, + parameter DBC_WB_RESERVED_ENTRY = 0, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + parameter ABPHY_WRITE_PROTOCOL = 0, + parameter PHY_USERMODE_OCT = 0, + parameter PHY_PERIODIC_OCT_RECAL = 0, + parameter PHY_HAS_DCC = 0, + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter PRI_HMC_CFG_TCL = 0, + parameter PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter PRI_HMC_CFG_WR_ODT_ON = 0, + parameter PRI_HMC_CFG_RD_ODT_ON = 0, + parameter PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_RD = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_WR = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_RD_TO_PCH = 0, + parameter PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_WR_TO_WR = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_RD = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter PRI_HMC_CFG_WR_TO_PCH = 0, + parameter PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter PRI_HMC_CFG_ARF_PERIOD = 0, + parameter PRI_HMC_CFG_PDN_PERIOD = 0, + parameter PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter PRI_HMC_CFG_16_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter SEC_HMC_CFG_TCL = 0, + parameter SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter SEC_HMC_CFG_WR_ODT_ON = 0, + parameter SEC_HMC_CFG_RD_ODT_ON = 0, + parameter SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_RD = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_WR = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_RD_TO_PCH = 0, + parameter SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_WR_TO_WR = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_RD = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter SEC_HMC_CFG_WR_TO_PCH = 0, + parameter SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter SEC_HMC_CFG_ARF_PERIOD = 0, + parameter SEC_HMC_CFG_PDN_PERIOD = 0, + parameter SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter SEC_HMC_CFG_16_ACT_TO_ACT = 0, + parameter PINS_PER_LANE = 0, + parameter LANES_PER_TILE = 0, + parameter OCT_CONTROL_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_CK_PINLOC_0 = 0, + parameter PORT_MEM_CK_PINLOC_1 = 0, + parameter PORT_MEM_CK_PINLOC_2 = 0, + parameter PORT_MEM_CK_PINLOC_3 = 0, + parameter PORT_MEM_CK_PINLOC_4 = 0, + parameter PORT_MEM_CK_PINLOC_5 = 0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_WIDTH = 0, + parameter PORT_MEM_CK_N_PINLOC_0 = 0, + parameter PORT_MEM_CK_N_PINLOC_1 = 0, + parameter PORT_MEM_CK_N_PINLOC_2 = 0, + parameter PORT_MEM_CK_N_PINLOC_3 = 0, + parameter PORT_MEM_CK_N_PINLOC_4 = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_WIDTH = 0, + parameter PORT_MEM_DK_PINLOC_0 = 0, + parameter PORT_MEM_DK_PINLOC_1 = 0, + parameter PORT_MEM_DK_PINLOC_2 = 0, + parameter PORT_MEM_DK_PINLOC_3 = 0, + parameter PORT_MEM_DK_PINLOC_4 = 0, + parameter PORT_MEM_DK_PINLOC_5 = 0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_WIDTH = 0, + parameter PORT_MEM_DK_N_PINLOC_0 = 0, + parameter PORT_MEM_DK_N_PINLOC_1 = 0, + parameter PORT_MEM_DK_N_PINLOC_2 = 0, + parameter PORT_MEM_DK_N_PINLOC_3 = 0, + parameter PORT_MEM_DK_N_PINLOC_4 = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_WIDTH = 0, + parameter PORT_MEM_DKA_PINLOC_0 = 0, + parameter PORT_MEM_DKA_PINLOC_1 = 0, + parameter PORT_MEM_DKA_PINLOC_2 = 0, + parameter PORT_MEM_DKA_PINLOC_3 = 0, + parameter PORT_MEM_DKA_PINLOC_4 = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_WIDTH = 0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_WIDTH = 0, + parameter PORT_MEM_DKB_PINLOC_0 = 0, + parameter PORT_MEM_DKB_PINLOC_1 = 0, + parameter PORT_MEM_DKB_PINLOC_2 = 0, + parameter PORT_MEM_DKB_PINLOC_3 = 0, + parameter PORT_MEM_DKB_PINLOC_4 = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_WIDTH = 0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_WIDTH = 0, + parameter PORT_MEM_K_PINLOC_0 = 0, + parameter PORT_MEM_K_PINLOC_1 = 0, + parameter PORT_MEM_K_PINLOC_2 = 0, + parameter PORT_MEM_K_PINLOC_3 = 0, + parameter PORT_MEM_K_PINLOC_4 = 0, + parameter PORT_MEM_K_PINLOC_5 = 0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_WIDTH = 0, + parameter PORT_MEM_K_N_PINLOC_0 = 0, + parameter PORT_MEM_K_N_PINLOC_1 = 0, + parameter PORT_MEM_K_N_PINLOC_2 = 0, + parameter PORT_MEM_K_N_PINLOC_3 = 0, + parameter PORT_MEM_K_N_PINLOC_4 = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_A_PINLOC_0 = 0, + parameter PORT_MEM_A_PINLOC_1 = 0, + parameter PORT_MEM_A_PINLOC_2 = 0, + parameter PORT_MEM_A_PINLOC_3 = 0, + parameter PORT_MEM_A_PINLOC_4 = 0, + parameter PORT_MEM_A_PINLOC_5 = 0, + parameter PORT_MEM_A_PINLOC_6 = 0, + parameter PORT_MEM_A_PINLOC_7 = 0, + parameter PORT_MEM_A_PINLOC_8 = 0, + parameter PORT_MEM_A_PINLOC_9 = 0, + parameter PORT_MEM_A_PINLOC_10 = 0, + parameter PORT_MEM_A_PINLOC_11 = 0, + parameter PORT_MEM_A_PINLOC_12 = 0, + parameter PORT_MEM_A_PINLOC_13 = 0, + parameter PORT_MEM_A_PINLOC_14 = 0, + parameter PORT_MEM_A_PINLOC_15 = 0, + parameter PORT_MEM_A_PINLOC_16 = 0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BA_PINLOC_0 = 0, + parameter PORT_MEM_BA_PINLOC_1 = 0, + parameter PORT_MEM_BA_PINLOC_2 = 0, + parameter PORT_MEM_BA_PINLOC_3 = 0, + parameter PORT_MEM_BA_PINLOC_4 = 0, + parameter PORT_MEM_BA_PINLOC_5 = 0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_BG_PINLOC_0 = 0, + parameter PORT_MEM_BG_PINLOC_1 = 0, + parameter PORT_MEM_BG_PINLOC_2 = 0, + parameter PORT_MEM_BG_PINLOC_3 = 0, + parameter PORT_MEM_BG_PINLOC_4 = 0, + parameter PORT_MEM_BG_PINLOC_5 = 0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_WIDTH = 0, + parameter PORT_MEM_C_PINLOC_0 = 0, + parameter PORT_MEM_C_PINLOC_1 = 0, + parameter PORT_MEM_C_PINLOC_2 = 0, + parameter PORT_MEM_C_PINLOC_3 = 0, + parameter PORT_MEM_C_PINLOC_4 = 0, + parameter PORT_MEM_C_PINLOC_5 = 0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_WIDTH = 0, + parameter PORT_MEM_CKE_PINLOC_0 = 0, + parameter PORT_MEM_CKE_PINLOC_1 = 0, + parameter PORT_MEM_CKE_PINLOC_2 = 0, + parameter PORT_MEM_CKE_PINLOC_3 = 0, + parameter PORT_MEM_CKE_PINLOC_4 = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_CS_N_PINLOC_0 = 0, + parameter PORT_MEM_CS_N_PINLOC_1 = 0, + parameter PORT_MEM_CS_N_PINLOC_2 = 0, + parameter PORT_MEM_CS_N_PINLOC_3 = 0, + parameter PORT_MEM_CS_N_PINLOC_4 = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_WIDTH = 0, + parameter PORT_MEM_RM_PINLOC_0 = 0, + parameter PORT_MEM_RM_PINLOC_1 = 0, + parameter PORT_MEM_RM_PINLOC_2 = 0, + parameter PORT_MEM_RM_PINLOC_3 = 0, + parameter PORT_MEM_RM_PINLOC_4 = 0, + parameter PORT_MEM_RM_PINLOC_5 = 0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_WIDTH = 0, + parameter PORT_MEM_ODT_PINLOC_0 = 0, + parameter PORT_MEM_ODT_PINLOC_1 = 0, + parameter PORT_MEM_ODT_PINLOC_2 = 0, + parameter PORT_MEM_ODT_PINLOC_3 = 0, + parameter PORT_MEM_ODT_PINLOC_4 = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_WE_N_PINLOC_0 = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_WIDTH = 0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_WIDTH = 0, + parameter PORT_MEM_PAR_PINLOC_0 = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_WIDTH = 0, + parameter PORT_MEM_CA_PINLOC_0 = 0, + parameter PORT_MEM_CA_PINLOC_1 = 0, + parameter PORT_MEM_CA_PINLOC_2 = 0, + parameter PORT_MEM_CA_PINLOC_3 = 0, + parameter PORT_MEM_CA_PINLOC_4 = 0, + parameter PORT_MEM_CA_PINLOC_5 = 0, + parameter PORT_MEM_CA_PINLOC_6 = 0, + parameter PORT_MEM_CA_PINLOC_7 = 0, + parameter PORT_MEM_CA_PINLOC_8 = 0, + parameter PORT_MEM_CA_PINLOC_9 = 0, + parameter PORT_MEM_CA_PINLOC_10 = 0, + parameter PORT_MEM_CA_PINLOC_11 = 0, + parameter PORT_MEM_CA_PINLOC_12 = 0, + parameter PORT_MEM_CA_PINLOC_13 = 0, + parameter PORT_MEM_CA_PINLOC_14 = 0, + parameter PORT_MEM_CA_PINLOC_15 = 0, + parameter PORT_MEM_CA_PINLOC_16 = 0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_WIDTH = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_WIDTH = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_WIDTH = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_WIDTH = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_WIDTH = 0, + parameter PORT_MEM_AP_PINLOC_0 = 0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_DM_PINLOC_0 = 0, + parameter PORT_MEM_DM_PINLOC_1 = 0, + parameter PORT_MEM_DM_PINLOC_2 = 0, + parameter PORT_MEM_DM_PINLOC_3 = 0, + parameter PORT_MEM_DM_PINLOC_4 = 0, + parameter PORT_MEM_DM_PINLOC_5 = 0, + parameter PORT_MEM_DM_PINLOC_6 = 0, + parameter PORT_MEM_DM_PINLOC_7 = 0, + parameter PORT_MEM_DM_PINLOC_8 = 0, + parameter PORT_MEM_DM_PINLOC_9 = 0, + parameter PORT_MEM_DM_PINLOC_10 = 0, + parameter PORT_MEM_DM_PINLOC_11 = 0, + parameter PORT_MEM_DM_PINLOC_12 = 0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_D_PINLOC_0 = 0, + parameter PORT_MEM_D_PINLOC_1 = 0, + parameter PORT_MEM_D_PINLOC_2 = 0, + parameter PORT_MEM_D_PINLOC_3 = 0, + parameter PORT_MEM_D_PINLOC_4 = 0, + parameter PORT_MEM_D_PINLOC_5 = 0, + parameter PORT_MEM_D_PINLOC_6 = 0, + parameter PORT_MEM_D_PINLOC_7 = 0, + parameter PORT_MEM_D_PINLOC_8 = 0, + parameter PORT_MEM_D_PINLOC_9 = 0, + parameter PORT_MEM_D_PINLOC_10 = 0, + parameter PORT_MEM_D_PINLOC_11 = 0, + parameter PORT_MEM_D_PINLOC_12 = 0, + parameter PORT_MEM_D_PINLOC_13 = 0, + parameter PORT_MEM_D_PINLOC_14 = 0, + parameter PORT_MEM_D_PINLOC_15 = 0, + parameter PORT_MEM_D_PINLOC_16 = 0, + parameter PORT_MEM_D_PINLOC_17 = 0, + parameter PORT_MEM_D_PINLOC_18 = 0, + parameter PORT_MEM_D_PINLOC_19 = 0, + parameter PORT_MEM_D_PINLOC_20 = 0, + parameter PORT_MEM_D_PINLOC_21 = 0, + parameter PORT_MEM_D_PINLOC_22 = 0, + parameter PORT_MEM_D_PINLOC_23 = 0, + parameter PORT_MEM_D_PINLOC_24 = 0, + parameter PORT_MEM_D_PINLOC_25 = 0, + parameter PORT_MEM_D_PINLOC_26 = 0, + parameter PORT_MEM_D_PINLOC_27 = 0, + parameter PORT_MEM_D_PINLOC_28 = 0, + parameter PORT_MEM_D_PINLOC_29 = 0, + parameter PORT_MEM_D_PINLOC_30 = 0, + parameter PORT_MEM_D_PINLOC_31 = 0, + parameter PORT_MEM_D_PINLOC_32 = 0, + parameter PORT_MEM_D_PINLOC_33 = 0, + parameter PORT_MEM_D_PINLOC_34 = 0, + parameter PORT_MEM_D_PINLOC_35 = 0, + parameter PORT_MEM_D_PINLOC_36 = 0, + parameter PORT_MEM_D_PINLOC_37 = 0, + parameter PORT_MEM_D_PINLOC_38 = 0, + parameter PORT_MEM_D_PINLOC_39 = 0, + parameter PORT_MEM_D_PINLOC_40 = 0, + parameter PORT_MEM_D_PINLOC_41 = 0, + parameter PORT_MEM_D_PINLOC_42 = 0, + parameter PORT_MEM_D_PINLOC_43 = 0, + parameter PORT_MEM_D_PINLOC_44 = 0, + parameter PORT_MEM_D_PINLOC_45 = 0, + parameter PORT_MEM_D_PINLOC_46 = 0, + parameter PORT_MEM_D_PINLOC_47 = 0, + parameter PORT_MEM_D_PINLOC_48 = 0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_WIDTH = 0, + parameter PORT_MEM_DQ_PINLOC_0 = 0, + parameter PORT_MEM_DQ_PINLOC_1 = 0, + parameter PORT_MEM_DQ_PINLOC_2 = 0, + parameter PORT_MEM_DQ_PINLOC_3 = 0, + parameter PORT_MEM_DQ_PINLOC_4 = 0, + parameter PORT_MEM_DQ_PINLOC_5 = 0, + parameter PORT_MEM_DQ_PINLOC_6 = 0, + parameter PORT_MEM_DQ_PINLOC_7 = 0, + parameter PORT_MEM_DQ_PINLOC_8 = 0, + parameter PORT_MEM_DQ_PINLOC_9 = 0, + parameter PORT_MEM_DQ_PINLOC_10 = 0, + parameter PORT_MEM_DQ_PINLOC_11 = 0, + parameter PORT_MEM_DQ_PINLOC_12 = 0, + parameter PORT_MEM_DQ_PINLOC_13 = 0, + parameter PORT_MEM_DQ_PINLOC_14 = 0, + parameter PORT_MEM_DQ_PINLOC_15 = 0, + parameter PORT_MEM_DQ_PINLOC_16 = 0, + parameter PORT_MEM_DQ_PINLOC_17 = 0, + parameter PORT_MEM_DQ_PINLOC_18 = 0, + parameter PORT_MEM_DQ_PINLOC_19 = 0, + parameter PORT_MEM_DQ_PINLOC_20 = 0, + parameter PORT_MEM_DQ_PINLOC_21 = 0, + parameter PORT_MEM_DQ_PINLOC_22 = 0, + parameter PORT_MEM_DQ_PINLOC_23 = 0, + parameter PORT_MEM_DQ_PINLOC_24 = 0, + parameter PORT_MEM_DQ_PINLOC_25 = 0, + parameter PORT_MEM_DQ_PINLOC_26 = 0, + parameter PORT_MEM_DQ_PINLOC_27 = 0, + parameter PORT_MEM_DQ_PINLOC_28 = 0, + parameter PORT_MEM_DQ_PINLOC_29 = 0, + parameter PORT_MEM_DQ_PINLOC_30 = 0, + parameter PORT_MEM_DQ_PINLOC_31 = 0, + parameter PORT_MEM_DQ_PINLOC_32 = 0, + parameter PORT_MEM_DQ_PINLOC_33 = 0, + parameter PORT_MEM_DQ_PINLOC_34 = 0, + parameter PORT_MEM_DQ_PINLOC_35 = 0, + parameter PORT_MEM_DQ_PINLOC_36 = 0, + parameter PORT_MEM_DQ_PINLOC_37 = 0, + parameter PORT_MEM_DQ_PINLOC_38 = 0, + parameter PORT_MEM_DQ_PINLOC_39 = 0, + parameter PORT_MEM_DQ_PINLOC_40 = 0, + parameter PORT_MEM_DQ_PINLOC_41 = 0, + parameter PORT_MEM_DQ_PINLOC_42 = 0, + parameter PORT_MEM_DQ_PINLOC_43 = 0, + parameter PORT_MEM_DQ_PINLOC_44 = 0, + parameter PORT_MEM_DQ_PINLOC_45 = 0, + parameter PORT_MEM_DQ_PINLOC_46 = 0, + parameter PORT_MEM_DQ_PINLOC_47 = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQA_PINLOC_0 = 0, + parameter PORT_MEM_DQA_PINLOC_1 = 0, + parameter PORT_MEM_DQA_PINLOC_2 = 0, + parameter PORT_MEM_DQA_PINLOC_3 = 0, + parameter PORT_MEM_DQA_PINLOC_4 = 0, + parameter PORT_MEM_DQA_PINLOC_5 = 0, + parameter PORT_MEM_DQA_PINLOC_6 = 0, + parameter PORT_MEM_DQA_PINLOC_7 = 0, + parameter PORT_MEM_DQA_PINLOC_8 = 0, + parameter PORT_MEM_DQA_PINLOC_9 = 0, + parameter PORT_MEM_DQA_PINLOC_10 = 0, + parameter PORT_MEM_DQA_PINLOC_11 = 0, + parameter PORT_MEM_DQA_PINLOC_12 = 0, + parameter PORT_MEM_DQA_PINLOC_13 = 0, + parameter PORT_MEM_DQA_PINLOC_14 = 0, + parameter PORT_MEM_DQA_PINLOC_15 = 0, + parameter PORT_MEM_DQA_PINLOC_16 = 0, + parameter PORT_MEM_DQA_PINLOC_17 = 0, + parameter PORT_MEM_DQA_PINLOC_18 = 0, + parameter PORT_MEM_DQA_PINLOC_19 = 0, + parameter PORT_MEM_DQA_PINLOC_20 = 0, + parameter PORT_MEM_DQA_PINLOC_21 = 0, + parameter PORT_MEM_DQA_PINLOC_22 = 0, + parameter PORT_MEM_DQA_PINLOC_23 = 0, + parameter PORT_MEM_DQA_PINLOC_24 = 0, + parameter PORT_MEM_DQA_PINLOC_25 = 0, + parameter PORT_MEM_DQA_PINLOC_26 = 0, + parameter PORT_MEM_DQA_PINLOC_27 = 0, + parameter PORT_MEM_DQA_PINLOC_28 = 0, + parameter PORT_MEM_DQA_PINLOC_29 = 0, + parameter PORT_MEM_DQA_PINLOC_30 = 0, + parameter PORT_MEM_DQA_PINLOC_31 = 0, + parameter PORT_MEM_DQA_PINLOC_32 = 0, + parameter PORT_MEM_DQA_PINLOC_33 = 0, + parameter PORT_MEM_DQA_PINLOC_34 = 0, + parameter PORT_MEM_DQA_PINLOC_35 = 0, + parameter PORT_MEM_DQA_PINLOC_36 = 0, + parameter PORT_MEM_DQA_PINLOC_37 = 0, + parameter PORT_MEM_DQA_PINLOC_38 = 0, + parameter PORT_MEM_DQA_PINLOC_39 = 0, + parameter PORT_MEM_DQA_PINLOC_40 = 0, + parameter PORT_MEM_DQA_PINLOC_41 = 0, + parameter PORT_MEM_DQA_PINLOC_42 = 0, + parameter PORT_MEM_DQA_PINLOC_43 = 0, + parameter PORT_MEM_DQA_PINLOC_44 = 0, + parameter PORT_MEM_DQA_PINLOC_45 = 0, + parameter PORT_MEM_DQA_PINLOC_46 = 0, + parameter PORT_MEM_DQA_PINLOC_47 = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_DQB_PINLOC_0 = 0, + parameter PORT_MEM_DQB_PINLOC_1 = 0, + parameter PORT_MEM_DQB_PINLOC_2 = 0, + parameter PORT_MEM_DQB_PINLOC_3 = 0, + parameter PORT_MEM_DQB_PINLOC_4 = 0, + parameter PORT_MEM_DQB_PINLOC_5 = 0, + parameter PORT_MEM_DQB_PINLOC_6 = 0, + parameter PORT_MEM_DQB_PINLOC_7 = 0, + parameter PORT_MEM_DQB_PINLOC_8 = 0, + parameter PORT_MEM_DQB_PINLOC_9 = 0, + parameter PORT_MEM_DQB_PINLOC_10 = 0, + parameter PORT_MEM_DQB_PINLOC_11 = 0, + parameter PORT_MEM_DQB_PINLOC_12 = 0, + parameter PORT_MEM_DQB_PINLOC_13 = 0, + parameter PORT_MEM_DQB_PINLOC_14 = 0, + parameter PORT_MEM_DQB_PINLOC_15 = 0, + parameter PORT_MEM_DQB_PINLOC_16 = 0, + parameter PORT_MEM_DQB_PINLOC_17 = 0, + parameter PORT_MEM_DQB_PINLOC_18 = 0, + parameter PORT_MEM_DQB_PINLOC_19 = 0, + parameter PORT_MEM_DQB_PINLOC_20 = 0, + parameter PORT_MEM_DQB_PINLOC_21 = 0, + parameter PORT_MEM_DQB_PINLOC_22 = 0, + parameter PORT_MEM_DQB_PINLOC_23 = 0, + parameter PORT_MEM_DQB_PINLOC_24 = 0, + parameter PORT_MEM_DQB_PINLOC_25 = 0, + parameter PORT_MEM_DQB_PINLOC_26 = 0, + parameter PORT_MEM_DQB_PINLOC_27 = 0, + parameter PORT_MEM_DQB_PINLOC_28 = 0, + parameter PORT_MEM_DQB_PINLOC_29 = 0, + parameter PORT_MEM_DQB_PINLOC_30 = 0, + parameter PORT_MEM_DQB_PINLOC_31 = 0, + parameter PORT_MEM_DQB_PINLOC_32 = 0, + parameter PORT_MEM_DQB_PINLOC_33 = 0, + parameter PORT_MEM_DQB_PINLOC_34 = 0, + parameter PORT_MEM_DQB_PINLOC_35 = 0, + parameter PORT_MEM_DQB_PINLOC_36 = 0, + parameter PORT_MEM_DQB_PINLOC_37 = 0, + parameter PORT_MEM_DQB_PINLOC_38 = 0, + parameter PORT_MEM_DQB_PINLOC_39 = 0, + parameter PORT_MEM_DQB_PINLOC_40 = 0, + parameter PORT_MEM_DQB_PINLOC_41 = 0, + parameter PORT_MEM_DQB_PINLOC_42 = 0, + parameter PORT_MEM_DQB_PINLOC_43 = 0, + parameter PORT_MEM_DQB_PINLOC_44 = 0, + parameter PORT_MEM_DQB_PINLOC_45 = 0, + parameter PORT_MEM_DQB_PINLOC_46 = 0, + parameter PORT_MEM_DQB_PINLOC_47 = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVA_PINLOC_0 = 0, + parameter PORT_MEM_DINVA_PINLOC_1 = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_DINVB_PINLOC_0 = 0, + parameter PORT_MEM_DINVB_PINLOC_1 = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_Q_PINLOC_0 = 0, + parameter PORT_MEM_Q_PINLOC_1 = 0, + parameter PORT_MEM_Q_PINLOC_2 = 0, + parameter PORT_MEM_Q_PINLOC_3 = 0, + parameter PORT_MEM_Q_PINLOC_4 = 0, + parameter PORT_MEM_Q_PINLOC_5 = 0, + parameter PORT_MEM_Q_PINLOC_6 = 0, + parameter PORT_MEM_Q_PINLOC_7 = 0, + parameter PORT_MEM_Q_PINLOC_8 = 0, + parameter PORT_MEM_Q_PINLOC_9 = 0, + parameter PORT_MEM_Q_PINLOC_10 = 0, + parameter PORT_MEM_Q_PINLOC_11 = 0, + parameter PORT_MEM_Q_PINLOC_12 = 0, + parameter PORT_MEM_Q_PINLOC_13 = 0, + parameter PORT_MEM_Q_PINLOC_14 = 0, + parameter PORT_MEM_Q_PINLOC_15 = 0, + parameter PORT_MEM_Q_PINLOC_16 = 0, + parameter PORT_MEM_Q_PINLOC_17 = 0, + parameter PORT_MEM_Q_PINLOC_18 = 0, + parameter PORT_MEM_Q_PINLOC_19 = 0, + parameter PORT_MEM_Q_PINLOC_20 = 0, + parameter PORT_MEM_Q_PINLOC_21 = 0, + parameter PORT_MEM_Q_PINLOC_22 = 0, + parameter PORT_MEM_Q_PINLOC_23 = 0, + parameter PORT_MEM_Q_PINLOC_24 = 0, + parameter PORT_MEM_Q_PINLOC_25 = 0, + parameter PORT_MEM_Q_PINLOC_26 = 0, + parameter PORT_MEM_Q_PINLOC_27 = 0, + parameter PORT_MEM_Q_PINLOC_28 = 0, + parameter PORT_MEM_Q_PINLOC_29 = 0, + parameter PORT_MEM_Q_PINLOC_30 = 0, + parameter PORT_MEM_Q_PINLOC_31 = 0, + parameter PORT_MEM_Q_PINLOC_32 = 0, + parameter PORT_MEM_Q_PINLOC_33 = 0, + parameter PORT_MEM_Q_PINLOC_34 = 0, + parameter PORT_MEM_Q_PINLOC_35 = 0, + parameter PORT_MEM_Q_PINLOC_36 = 0, + parameter PORT_MEM_Q_PINLOC_37 = 0, + parameter PORT_MEM_Q_PINLOC_38 = 0, + parameter PORT_MEM_Q_PINLOC_39 = 0, + parameter PORT_MEM_Q_PINLOC_40 = 0, + parameter PORT_MEM_Q_PINLOC_41 = 0, + parameter PORT_MEM_Q_PINLOC_42 = 0, + parameter PORT_MEM_Q_PINLOC_43 = 0, + parameter PORT_MEM_Q_PINLOC_44 = 0, + parameter PORT_MEM_Q_PINLOC_45 = 0, + parameter PORT_MEM_Q_PINLOC_46 = 0, + parameter PORT_MEM_Q_PINLOC_47 = 0, + parameter PORT_MEM_Q_PINLOC_48 = 0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_WIDTH = 0, + parameter PORT_MEM_DQS_PINLOC_0 = 0, + parameter PORT_MEM_DQS_PINLOC_1 = 0, + parameter PORT_MEM_DQS_PINLOC_2 = 0, + parameter PORT_MEM_DQS_PINLOC_3 = 0, + parameter PORT_MEM_DQS_PINLOC_4 = 0, + parameter PORT_MEM_DQS_PINLOC_5 = 0, + parameter PORT_MEM_DQS_PINLOC_6 = 0, + parameter PORT_MEM_DQS_PINLOC_7 = 0, + parameter PORT_MEM_DQS_PINLOC_8 = 0, + parameter PORT_MEM_DQS_PINLOC_9 = 0, + parameter PORT_MEM_DQS_PINLOC_10 = 0, + parameter PORT_MEM_DQS_PINLOC_11 = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_WIDTH = 0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_WIDTH = 0, + parameter PORT_MEM_QK_PINLOC_0 = 0, + parameter PORT_MEM_QK_PINLOC_1 = 0, + parameter PORT_MEM_QK_PINLOC_2 = 0, + parameter PORT_MEM_QK_PINLOC_3 = 0, + parameter PORT_MEM_QK_PINLOC_4 = 0, + parameter PORT_MEM_QK_PINLOC_5 = 0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_WIDTH = 0, + parameter PORT_MEM_QK_N_PINLOC_0 = 0, + parameter PORT_MEM_QK_N_PINLOC_1 = 0, + parameter PORT_MEM_QK_N_PINLOC_2 = 0, + parameter PORT_MEM_QK_N_PINLOC_3 = 0, + parameter PORT_MEM_QK_N_PINLOC_4 = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKA_PINLOC_0 = 0, + parameter PORT_MEM_QKA_PINLOC_1 = 0, + parameter PORT_MEM_QKA_PINLOC_2 = 0, + parameter PORT_MEM_QKA_PINLOC_3 = 0, + parameter PORT_MEM_QKA_PINLOC_4 = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_WIDTH = 0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_QKB_PINLOC_0 = 0, + parameter PORT_MEM_QKB_PINLOC_1 = 0, + parameter PORT_MEM_QKB_PINLOC_2 = 0, + parameter PORT_MEM_QKB_PINLOC_3 = 0, + parameter PORT_MEM_QKB_PINLOC_4 = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_WIDTH = 0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_WIDTH = 0, + parameter PORT_MEM_CQ_PINLOC_0 = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_WIDTH = 0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_WIDTH = 0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_WIDTH = 0, + parameter PORT_MEM_PE_N_PINLOC_0 = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 0, + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 0, + parameter PORT_AFI_RLAT_WIDTH = 0, + parameter PORT_AFI_WLAT_WIDTH = 0, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 0, + parameter PORT_AFI_ADDR_WIDTH = 0, + parameter PORT_AFI_BA_WIDTH = 0, + parameter PORT_AFI_BG_WIDTH = 0, + parameter PORT_AFI_C_WIDTH = 0, + parameter PORT_AFI_CKE_WIDTH = 0, + parameter PORT_AFI_CS_N_WIDTH = 0, + parameter PORT_AFI_RM_WIDTH = 0, + parameter PORT_AFI_ODT_WIDTH = 0, + parameter PORT_AFI_RAS_N_WIDTH = 0, + parameter PORT_AFI_CAS_N_WIDTH = 0, + parameter PORT_AFI_WE_N_WIDTH = 0, + parameter PORT_AFI_RST_N_WIDTH = 0, + parameter PORT_AFI_ACT_N_WIDTH = 0, + parameter PORT_AFI_PAR_WIDTH = 0, + parameter PORT_AFI_CA_WIDTH = 0, + parameter PORT_AFI_REF_N_WIDTH = 0, + parameter PORT_AFI_WPS_N_WIDTH = 0, + parameter PORT_AFI_RPS_N_WIDTH = 0, + parameter PORT_AFI_DOFF_N_WIDTH = 0, + parameter PORT_AFI_LD_N_WIDTH = 0, + parameter PORT_AFI_RW_N_WIDTH = 0, + parameter PORT_AFI_LBK0_N_WIDTH = 0, + parameter PORT_AFI_LBK1_N_WIDTH = 0, + parameter PORT_AFI_CFG_N_WIDTH = 0, + parameter PORT_AFI_AP_WIDTH = 0, + parameter PORT_AFI_AINV_WIDTH = 0, + parameter PORT_AFI_DM_WIDTH = 0, + parameter PORT_AFI_DM_N_WIDTH = 0, + parameter PORT_AFI_BWS_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 0, + parameter PORT_AFI_RDATA_DINV_WIDTH = 0, + parameter PORT_AFI_WDATA_DINV_WIDTH = 0, + parameter PORT_AFI_DQS_BURST_WIDTH = 0, + parameter PORT_AFI_WDATA_VALID_WIDTH = 0, + parameter PORT_AFI_WDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 0, + parameter PORT_AFI_RDATA_WIDTH = 0, + parameter PORT_AFI_RDATA_VALID_WIDTH = 0, + parameter PORT_AFI_RRANK_WIDTH = 0, + parameter PORT_AFI_WRANK_WIDTH = 0, + parameter PORT_AFI_ALERT_N_WIDTH = 0, + parameter PORT_AFI_PE_N_WIDTH = 0, + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 0, + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 0, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_AMM_RDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 0, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 0, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 0, + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 0, + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 0, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 0, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 0, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_WIDTH = 0, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 0, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 0, + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 0, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_RDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_WDATA_WIDTH = 0, + parameter PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH = 0, + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 0, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 0, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 0, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 0, + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 0, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 0, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 0, + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 0, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 0, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 0, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 0, + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 0, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_SIM_CAL_SLAVE_CLK_FREQ_PS = 0, + parameter PLL_SIM_CAL_MASTER_CLK_FREQ_PS = 0, + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_8 = "" +) ( + input logic global_reset_n, + input logic pll_ref_clk, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + input logic oct_rzqin, + output logic [0:0] mem_ck, + output logic [0:0] mem_ck_n, + output logic [16:0] mem_a, + output logic [0:0] mem_act_n, + output logic [1:0] mem_ba, + output logic [1:0] mem_bg, + output logic [0:0] mem_c, + output logic [0:0] mem_cke, + output logic [0:0] mem_cs_n, + output logic [0:0] mem_rm, + output logic [0:0] mem_odt, + output logic [0:0] mem_reset_n, + output logic [0:0] mem_par, + input logic [0:0] mem_alert_n, + inout tri [7:0] mem_dqs, + inout tri [7:0] mem_dqs_n, + inout tri [63:0] mem_dq, + inout tri [7:0] mem_dbi_n, + output logic [0:0] mem_dk, + output logic [0:0] mem_dk_n, + output logic [0:0] mem_dka, + output logic [0:0] mem_dka_n, + output logic [0:0] mem_dkb, + output logic [0:0] mem_dkb_n, + output logic [0:0] mem_k, + output logic [0:0] mem_k_n, + output logic [0:0] mem_ras_n, + output logic [0:0] mem_cas_n, + output logic [0:0] mem_we_n, + output logic [0:0] mem_ca, + output logic [0:0] mem_ref_n, + output logic [0:0] mem_wps_n, + output logic [0:0] mem_rps_n, + output logic [0:0] mem_doff_n, + output logic [0:0] mem_lda_n, + output logic [0:0] mem_ldb_n, + output logic [0:0] mem_rwa_n, + output logic [0:0] mem_rwb_n, + output logic [0:0] mem_lbk0_n, + output logic [0:0] mem_lbk1_n, + output logic [0:0] mem_cfg_n, + output logic [0:0] mem_ap, + output logic [0:0] mem_ainv, + output logic [0:0] mem_dm, + output logic [0:0] mem_bws_n, + output logic [0:0] mem_d, + inout tri [0:0] mem_dqa, + inout tri [0:0] mem_dqb, + inout tri [0:0] mem_dinva, + inout tri [0:0] mem_dinvb, + input logic [0:0] mem_q, + input logic [0:0] mem_qk, + input logic [0:0] mem_qk_n, + input logic [0:0] mem_qka, + input logic [0:0] mem_qka_n, + input logic [0:0] mem_qkb, + input logic [0:0] mem_qkb_n, + input logic [0:0] mem_cq, + input logic [0:0] mem_cq_n, + input logic [0:0] mem_pe_n, + output logic local_cal_success, + output logic local_cal_fail, + input logic vid_cal_done_persist, + output logic afi_reset_n, + output logic afi_clk, + output logic afi_half_clk, + output logic emif_usr_reset_n, + output logic emif_usr_clk, + output logic emif_usr_half_clk, + output logic emif_usr_reset_n_sec, + output logic emif_usr_clk_sec, + output logic emif_usr_half_clk_sec, + output logic cal_master_reset_n, + output logic cal_master_clk, + output logic cal_slave_reset_n, + output logic cal_slave_clk, + input logic cal_slave_reset_n_in, + input logic cal_slave_clk_in, + input logic cal_debug_reset_n, + input logic cal_debug_clk, + output logic cal_debug_out_reset_n, + output logic cal_debug_out_clk, + output logic [31:0] clks_sharing_master_out, + input logic [31:0] clks_sharing_slave_in, + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [5:0] afi_rlat, + output logic [5:0] afi_wlat, + output logic [3:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [0:0] afi_addr, + input logic [0:0] afi_ba, + input logic [0:0] afi_bg, + input logic [0:0] afi_c, + input logic [0:0] afi_cke, + input logic [0:0] afi_cs_n, + input logic [0:0] afi_rm, + input logic [0:0] afi_odt, + input logic [0:0] afi_ras_n, + input logic [0:0] afi_cas_n, + input logic [0:0] afi_we_n, + input logic [0:0] afi_rst_n, + input logic [0:0] afi_act_n, + input logic [0:0] afi_par, + input logic [0:0] afi_ca, + input logic [0:0] afi_ref_n, + input logic [0:0] afi_wps_n, + input logic [0:0] afi_rps_n, + input logic [0:0] afi_doff_n, + input logic [0:0] afi_ld_n, + input logic [0:0] afi_rw_n, + input logic [0:0] afi_lbk0_n, + input logic [0:0] afi_lbk1_n, + input logic [0:0] afi_cfg_n, + input logic [0:0] afi_ap, + input logic [0:0] afi_ainv, + input logic [0:0] afi_dm, + input logic [0:0] afi_dm_n, + input logic [0:0] afi_bws_n, + output logic [0:0] afi_rdata_dbi_n, + input logic [0:0] afi_wdata_dbi_n, + output logic [0:0] afi_rdata_dinv, + input logic [0:0] afi_wdata_dinv, + input logic [0:0] afi_dqs_burst, + input logic [0:0] afi_wdata_valid, + input logic [0:0] afi_wdata, + input logic [0:0] afi_rdata_en_full, + output logic [0:0] afi_rdata, + output logic [0:0] afi_rdata_valid, + input logic [0:0] afi_rrank, + input logic [0:0] afi_wrank, + output logic [0:0] afi_alert_n, + output logic [0:0] afi_pe_n, + input logic [0:0] ast_cmd_data_0, + input logic ast_cmd_valid_0, + output logic ast_cmd_ready_0, + input logic [0:0] ast_cmd_data_1, + input logic ast_cmd_valid_1, + output logic ast_cmd_ready_1, + input logic [0:0] ast_wr_data_0, + input logic ast_wr_valid_0, + output logic ast_wr_ready_0, + input logic [0:0] ast_wr_data_1, + input logic ast_wr_valid_1, + output logic ast_wr_ready_1, + output logic [0:0] ast_rd_data_0, + output logic ast_rd_valid_0, + input logic ast_rd_ready_0, + output logic [0:0] ast_rd_data_1, + output logic ast_rd_valid_1, + input logic ast_rd_ready_1, + output logic amm_ready_0, + input logic amm_read_0, + input logic amm_write_0, + input logic [25:0] amm_address_0, + output logic [511:0] amm_readdata_0, + input logic [511:0] amm_writedata_0, + input logic [6:0] amm_burstcount_0, + input logic [63:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + output logic amm_ready_1, + input logic amm_read_1, + input logic amm_write_1, + input logic [25:0] amm_address_1, + output logic [511:0] amm_readdata_1, + input logic [511:0] amm_writedata_1, + input logic [6:0] amm_burstcount_1, + input logic [63:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + input logic [3:0] ctrl_user_refresh_req, + input logic [15:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + input logic [3:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + output logic ctrl_will_refresh, + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + output logic ctrl_power_down_ack, + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + input logic [14:0] ctrl_ecc_write_info_0, + output logic [12:0] ctrl_ecc_rdata_id_0, + output logic [2:0] ctrl_ecc_read_info_0, + output logic [2:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + output logic [11:0] ctrl_ecc_wr_pointer_info_0, + input logic [14:0] ctrl_ecc_write_info_1, + output logic [12:0] ctrl_ecc_rdata_id_1, + output logic [2:0] ctrl_ecc_read_info_1, + output logic [2:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + output logic [11:0] ctrl_ecc_wr_pointer_info_1, + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [9:0] mmr_slave_address_0, + output logic [31:0] mmr_slave_readdata_0, + input logic [31:0] mmr_slave_writedata_0, + input logic [1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [9:0] mmr_slave_address_1, + output logic [31:0] mmr_slave_readdata_1, + input logic [31:0] mmr_slave_writedata_1, + input logic [1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + input logic [4095:0] hps_to_emif, + output logic [4095:0] emif_to_hps, + input logic [1:0] hps_to_emif_gp, + output logic [0:0] emif_to_hps_gp, + output logic cal_debug_waitrequest, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [23:0] cal_debug_addr, + output logic [31:0] cal_debug_read_data, + input logic [31:0] cal_debug_write_data, + input logic [3:0] cal_debug_byteenable, + output logic cal_debug_read_data_valid, + input logic cal_debug_out_waitrequest, + output logic cal_debug_out_read, + output logic cal_debug_out_write, + output logic [23:0] cal_debug_out_addr, + input logic [31:0] cal_debug_out_read_data, + output logic [31:0] cal_debug_out_write_data, + output logic [3:0] cal_debug_out_byteenable, + input logic cal_debug_out_read_data_valid, + input logic cal_master_waitrequest, + output logic cal_master_read, + output logic cal_master_write, + output logic [15:0] cal_master_addr, + input logic [31:0] cal_master_read_data, + output logic [31:0] cal_master_write_data, + output logic [3:0] cal_master_byteenable, + input logic cal_master_read_data_valid, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + input logic [7:0] ioaux_pio_in, + output logic [7:0] ioaux_pio_out, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [8:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [7:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [7:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [3:0] pll_cnt_sel, + input logic [2:0] pll_num_phase_shifts, + output logic pll_phase_done, + output logic [1:0] dft_core_clk_buf_out, + output logic [1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_top # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_TARGET_IS_ES (PHY_TARGET_IS_ES), + .PHY_TARGET_IS_ES2 (PHY_TARGET_IS_ES2), + .PHY_TARGET_IS_PRODUCTION (PHY_TARGET_IS_PRODUCTION), + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT), + .PHY_HPS_ENABLE_EARLY_RELEASE (PHY_HPS_ENABLE_EARLY_RELEASE), + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_ECLIPSE_DEBUG (DIAG_ECLIPSE_DEBUG), + .DIAG_EXPORT_VJI (DIAG_EXPORT_VJI), + .DIAG_INTERFACE_ID (DIAG_INTERFACE_ID), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY), + .SILICON_REV (SILICON_REV), + .IS_HPS (IS_HPS), + .IS_VID (IS_VID), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .REGISTER_AFI (REGISTER_AFI), + .SEQ_SYNTH_CPU_CLK_DIVIDE (SEQ_SYNTH_CPU_CLK_DIVIDE), + .SEQ_SYNTH_CAL_CLK_DIVIDE (SEQ_SYNTH_CAL_CLK_DIVIDE), + .SEQ_SIM_CPU_CLK_DIVIDE (SEQ_SIM_CPU_CLK_DIVIDE), + .SEQ_SIM_CAL_CLK_DIVIDE (SEQ_SIM_CAL_CLK_DIVIDE), + .SEQ_SYNTH_OSC_FREQ_MHZ (SEQ_SYNTH_OSC_FREQ_MHZ), + .SEQ_SIM_OSC_FREQ_MHZ (SEQ_SIM_OSC_FREQ_MHZ), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .LANES_USAGE_0 (LANES_USAGE_0), + .LANES_USAGE_1 (LANES_USAGE_1), + .LANES_USAGE_2 (LANES_USAGE_2), + .LANES_USAGE_3 (LANES_USAGE_3), + .LANES_USAGE_AUTOGEN_WCNT (LANES_USAGE_AUTOGEN_WCNT), + .PINS_USAGE_0 (PINS_USAGE_0), + .PINS_USAGE_1 (PINS_USAGE_1), + .PINS_USAGE_2 (PINS_USAGE_2), + .PINS_USAGE_3 (PINS_USAGE_3), + .PINS_USAGE_4 (PINS_USAGE_4), + .PINS_USAGE_5 (PINS_USAGE_5), + .PINS_USAGE_6 (PINS_USAGE_6), + .PINS_USAGE_7 (PINS_USAGE_7), + .PINS_USAGE_8 (PINS_USAGE_8), + .PINS_USAGE_9 (PINS_USAGE_9), + .PINS_USAGE_10 (PINS_USAGE_10), + .PINS_USAGE_11 (PINS_USAGE_11), + .PINS_USAGE_12 (PINS_USAGE_12), + .PINS_USAGE_AUTOGEN_WCNT (PINS_USAGE_AUTOGEN_WCNT), + .PINS_RATE_0 (PINS_RATE_0), + .PINS_RATE_1 (PINS_RATE_1), + .PINS_RATE_2 (PINS_RATE_2), + .PINS_RATE_3 (PINS_RATE_3), + .PINS_RATE_4 (PINS_RATE_4), + .PINS_RATE_5 (PINS_RATE_5), + .PINS_RATE_6 (PINS_RATE_6), + .PINS_RATE_7 (PINS_RATE_7), + .PINS_RATE_8 (PINS_RATE_8), + .PINS_RATE_9 (PINS_RATE_9), + .PINS_RATE_10 (PINS_RATE_10), + .PINS_RATE_11 (PINS_RATE_11), + .PINS_RATE_12 (PINS_RATE_12), + .PINS_RATE_AUTOGEN_WCNT (PINS_RATE_AUTOGEN_WCNT), + .PINS_WDB_0 (PINS_WDB_0), + .PINS_WDB_1 (PINS_WDB_1), + .PINS_WDB_2 (PINS_WDB_2), + .PINS_WDB_3 (PINS_WDB_3), + .PINS_WDB_4 (PINS_WDB_4), + .PINS_WDB_5 (PINS_WDB_5), + .PINS_WDB_6 (PINS_WDB_6), + .PINS_WDB_7 (PINS_WDB_7), + .PINS_WDB_8 (PINS_WDB_8), + .PINS_WDB_9 (PINS_WDB_9), + .PINS_WDB_10 (PINS_WDB_10), + .PINS_WDB_11 (PINS_WDB_11), + .PINS_WDB_12 (PINS_WDB_12), + .PINS_WDB_13 (PINS_WDB_13), + .PINS_WDB_14 (PINS_WDB_14), + .PINS_WDB_15 (PINS_WDB_15), + .PINS_WDB_16 (PINS_WDB_16), + .PINS_WDB_17 (PINS_WDB_17), + .PINS_WDB_18 (PINS_WDB_18), + .PINS_WDB_19 (PINS_WDB_19), + .PINS_WDB_20 (PINS_WDB_20), + .PINS_WDB_21 (PINS_WDB_21), + .PINS_WDB_22 (PINS_WDB_22), + .PINS_WDB_23 (PINS_WDB_23), + .PINS_WDB_24 (PINS_WDB_24), + .PINS_WDB_25 (PINS_WDB_25), + .PINS_WDB_26 (PINS_WDB_26), + .PINS_WDB_27 (PINS_WDB_27), + .PINS_WDB_28 (PINS_WDB_28), + .PINS_WDB_29 (PINS_WDB_29), + .PINS_WDB_30 (PINS_WDB_30), + .PINS_WDB_31 (PINS_WDB_31), + .PINS_WDB_32 (PINS_WDB_32), + .PINS_WDB_33 (PINS_WDB_33), + .PINS_WDB_34 (PINS_WDB_34), + .PINS_WDB_35 (PINS_WDB_35), + .PINS_WDB_36 (PINS_WDB_36), + .PINS_WDB_37 (PINS_WDB_37), + .PINS_WDB_38 (PINS_WDB_38), + .PINS_WDB_AUTOGEN_WCNT (PINS_WDB_AUTOGEN_WCNT), + .PINS_DATA_IN_MODE_0 (PINS_DATA_IN_MODE_0), + .PINS_DATA_IN_MODE_1 (PINS_DATA_IN_MODE_1), + .PINS_DATA_IN_MODE_2 (PINS_DATA_IN_MODE_2), + .PINS_DATA_IN_MODE_3 (PINS_DATA_IN_MODE_3), + .PINS_DATA_IN_MODE_4 (PINS_DATA_IN_MODE_4), + .PINS_DATA_IN_MODE_5 (PINS_DATA_IN_MODE_5), + .PINS_DATA_IN_MODE_6 (PINS_DATA_IN_MODE_6), + .PINS_DATA_IN_MODE_7 (PINS_DATA_IN_MODE_7), + .PINS_DATA_IN_MODE_8 (PINS_DATA_IN_MODE_8), + .PINS_DATA_IN_MODE_9 (PINS_DATA_IN_MODE_9), + .PINS_DATA_IN_MODE_10 (PINS_DATA_IN_MODE_10), + .PINS_DATA_IN_MODE_11 (PINS_DATA_IN_MODE_11), + .PINS_DATA_IN_MODE_12 (PINS_DATA_IN_MODE_12), + .PINS_DATA_IN_MODE_13 (PINS_DATA_IN_MODE_13), + .PINS_DATA_IN_MODE_14 (PINS_DATA_IN_MODE_14), + .PINS_DATA_IN_MODE_15 (PINS_DATA_IN_MODE_15), + .PINS_DATA_IN_MODE_16 (PINS_DATA_IN_MODE_16), + .PINS_DATA_IN_MODE_17 (PINS_DATA_IN_MODE_17), + .PINS_DATA_IN_MODE_18 (PINS_DATA_IN_MODE_18), + .PINS_DATA_IN_MODE_19 (PINS_DATA_IN_MODE_19), + .PINS_DATA_IN_MODE_20 (PINS_DATA_IN_MODE_20), + .PINS_DATA_IN_MODE_21 (PINS_DATA_IN_MODE_21), + .PINS_DATA_IN_MODE_22 (PINS_DATA_IN_MODE_22), + .PINS_DATA_IN_MODE_23 (PINS_DATA_IN_MODE_23), + .PINS_DATA_IN_MODE_24 (PINS_DATA_IN_MODE_24), + .PINS_DATA_IN_MODE_25 (PINS_DATA_IN_MODE_25), + .PINS_DATA_IN_MODE_26 (PINS_DATA_IN_MODE_26), + .PINS_DATA_IN_MODE_27 (PINS_DATA_IN_MODE_27), + .PINS_DATA_IN_MODE_28 (PINS_DATA_IN_MODE_28), + .PINS_DATA_IN_MODE_29 (PINS_DATA_IN_MODE_29), + .PINS_DATA_IN_MODE_30 (PINS_DATA_IN_MODE_30), + .PINS_DATA_IN_MODE_31 (PINS_DATA_IN_MODE_31), + .PINS_DATA_IN_MODE_32 (PINS_DATA_IN_MODE_32), + .PINS_DATA_IN_MODE_33 (PINS_DATA_IN_MODE_33), + .PINS_DATA_IN_MODE_34 (PINS_DATA_IN_MODE_34), + .PINS_DATA_IN_MODE_35 (PINS_DATA_IN_MODE_35), + .PINS_DATA_IN_MODE_36 (PINS_DATA_IN_MODE_36), + .PINS_DATA_IN_MODE_37 (PINS_DATA_IN_MODE_37), + .PINS_DATA_IN_MODE_38 (PINS_DATA_IN_MODE_38), + .PINS_DATA_IN_MODE_AUTOGEN_WCNT (PINS_DATA_IN_MODE_AUTOGEN_WCNT), + .PINS_C2L_DRIVEN_0 (PINS_C2L_DRIVEN_0), + .PINS_C2L_DRIVEN_1 (PINS_C2L_DRIVEN_1), + .PINS_C2L_DRIVEN_2 (PINS_C2L_DRIVEN_2), + .PINS_C2L_DRIVEN_3 (PINS_C2L_DRIVEN_3), + .PINS_C2L_DRIVEN_4 (PINS_C2L_DRIVEN_4), + .PINS_C2L_DRIVEN_5 (PINS_C2L_DRIVEN_5), + .PINS_C2L_DRIVEN_6 (PINS_C2L_DRIVEN_6), + .PINS_C2L_DRIVEN_7 (PINS_C2L_DRIVEN_7), + .PINS_C2L_DRIVEN_8 (PINS_C2L_DRIVEN_8), + .PINS_C2L_DRIVEN_9 (PINS_C2L_DRIVEN_9), + .PINS_C2L_DRIVEN_10 (PINS_C2L_DRIVEN_10), + .PINS_C2L_DRIVEN_11 (PINS_C2L_DRIVEN_11), + .PINS_C2L_DRIVEN_12 (PINS_C2L_DRIVEN_12), + .PINS_C2L_DRIVEN_AUTOGEN_WCNT (PINS_C2L_DRIVEN_AUTOGEN_WCNT), + .PINS_DB_IN_BYPASS_0 (PINS_DB_IN_BYPASS_0), + .PINS_DB_IN_BYPASS_1 (PINS_DB_IN_BYPASS_1), + .PINS_DB_IN_BYPASS_2 (PINS_DB_IN_BYPASS_2), + .PINS_DB_IN_BYPASS_3 (PINS_DB_IN_BYPASS_3), + .PINS_DB_IN_BYPASS_4 (PINS_DB_IN_BYPASS_4), + .PINS_DB_IN_BYPASS_5 (PINS_DB_IN_BYPASS_5), + .PINS_DB_IN_BYPASS_6 (PINS_DB_IN_BYPASS_6), + .PINS_DB_IN_BYPASS_7 (PINS_DB_IN_BYPASS_7), + .PINS_DB_IN_BYPASS_8 (PINS_DB_IN_BYPASS_8), + .PINS_DB_IN_BYPASS_9 (PINS_DB_IN_BYPASS_9), + .PINS_DB_IN_BYPASS_10 (PINS_DB_IN_BYPASS_10), + .PINS_DB_IN_BYPASS_11 (PINS_DB_IN_BYPASS_11), + .PINS_DB_IN_BYPASS_12 (PINS_DB_IN_BYPASS_12), + .PINS_DB_IN_BYPASS_AUTOGEN_WCNT (PINS_DB_IN_BYPASS_AUTOGEN_WCNT), + .PINS_DB_OUT_BYPASS_0 (PINS_DB_OUT_BYPASS_0), + .PINS_DB_OUT_BYPASS_1 (PINS_DB_OUT_BYPASS_1), + .PINS_DB_OUT_BYPASS_2 (PINS_DB_OUT_BYPASS_2), + .PINS_DB_OUT_BYPASS_3 (PINS_DB_OUT_BYPASS_3), + .PINS_DB_OUT_BYPASS_4 (PINS_DB_OUT_BYPASS_4), + .PINS_DB_OUT_BYPASS_5 (PINS_DB_OUT_BYPASS_5), + .PINS_DB_OUT_BYPASS_6 (PINS_DB_OUT_BYPASS_6), + .PINS_DB_OUT_BYPASS_7 (PINS_DB_OUT_BYPASS_7), + .PINS_DB_OUT_BYPASS_8 (PINS_DB_OUT_BYPASS_8), + .PINS_DB_OUT_BYPASS_9 (PINS_DB_OUT_BYPASS_9), + .PINS_DB_OUT_BYPASS_10 (PINS_DB_OUT_BYPASS_10), + .PINS_DB_OUT_BYPASS_11 (PINS_DB_OUT_BYPASS_11), + .PINS_DB_OUT_BYPASS_12 (PINS_DB_OUT_BYPASS_12), + .PINS_DB_OUT_BYPASS_AUTOGEN_WCNT (PINS_DB_OUT_BYPASS_AUTOGEN_WCNT), + .PINS_DB_OE_BYPASS_0 (PINS_DB_OE_BYPASS_0), + .PINS_DB_OE_BYPASS_1 (PINS_DB_OE_BYPASS_1), + .PINS_DB_OE_BYPASS_2 (PINS_DB_OE_BYPASS_2), + .PINS_DB_OE_BYPASS_3 (PINS_DB_OE_BYPASS_3), + .PINS_DB_OE_BYPASS_4 (PINS_DB_OE_BYPASS_4), + .PINS_DB_OE_BYPASS_5 (PINS_DB_OE_BYPASS_5), + .PINS_DB_OE_BYPASS_6 (PINS_DB_OE_BYPASS_6), + .PINS_DB_OE_BYPASS_7 (PINS_DB_OE_BYPASS_7), + .PINS_DB_OE_BYPASS_8 (PINS_DB_OE_BYPASS_8), + .PINS_DB_OE_BYPASS_9 (PINS_DB_OE_BYPASS_9), + .PINS_DB_OE_BYPASS_10 (PINS_DB_OE_BYPASS_10), + .PINS_DB_OE_BYPASS_11 (PINS_DB_OE_BYPASS_11), + .PINS_DB_OE_BYPASS_12 (PINS_DB_OE_BYPASS_12), + .PINS_DB_OE_BYPASS_AUTOGEN_WCNT (PINS_DB_OE_BYPASS_AUTOGEN_WCNT), + .PINS_INVERT_WR_0 (PINS_INVERT_WR_0), + .PINS_INVERT_WR_1 (PINS_INVERT_WR_1), + .PINS_INVERT_WR_2 (PINS_INVERT_WR_2), + .PINS_INVERT_WR_3 (PINS_INVERT_WR_3), + .PINS_INVERT_WR_4 (PINS_INVERT_WR_4), + .PINS_INVERT_WR_5 (PINS_INVERT_WR_5), + .PINS_INVERT_WR_6 (PINS_INVERT_WR_6), + .PINS_INVERT_WR_7 (PINS_INVERT_WR_7), + .PINS_INVERT_WR_8 (PINS_INVERT_WR_8), + .PINS_INVERT_WR_9 (PINS_INVERT_WR_9), + .PINS_INVERT_WR_10 (PINS_INVERT_WR_10), + .PINS_INVERT_WR_11 (PINS_INVERT_WR_11), + .PINS_INVERT_WR_12 (PINS_INVERT_WR_12), + .PINS_INVERT_WR_AUTOGEN_WCNT (PINS_INVERT_WR_AUTOGEN_WCNT), + .PINS_INVERT_OE_0 (PINS_INVERT_OE_0), + .PINS_INVERT_OE_1 (PINS_INVERT_OE_1), + .PINS_INVERT_OE_2 (PINS_INVERT_OE_2), + .PINS_INVERT_OE_3 (PINS_INVERT_OE_3), + .PINS_INVERT_OE_4 (PINS_INVERT_OE_4), + .PINS_INVERT_OE_5 (PINS_INVERT_OE_5), + .PINS_INVERT_OE_6 (PINS_INVERT_OE_6), + .PINS_INVERT_OE_7 (PINS_INVERT_OE_7), + .PINS_INVERT_OE_8 (PINS_INVERT_OE_8), + .PINS_INVERT_OE_9 (PINS_INVERT_OE_9), + .PINS_INVERT_OE_10 (PINS_INVERT_OE_10), + .PINS_INVERT_OE_11 (PINS_INVERT_OE_11), + .PINS_INVERT_OE_12 (PINS_INVERT_OE_12), + .PINS_INVERT_OE_AUTOGEN_WCNT (PINS_INVERT_OE_AUTOGEN_WCNT), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_0 (PINS_AC_HMC_DATA_OVERRIDE_ENA_0), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_1 (PINS_AC_HMC_DATA_OVERRIDE_ENA_1), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_2 (PINS_AC_HMC_DATA_OVERRIDE_ENA_2), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_3 (PINS_AC_HMC_DATA_OVERRIDE_ENA_3), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_4 (PINS_AC_HMC_DATA_OVERRIDE_ENA_4), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_5 (PINS_AC_HMC_DATA_OVERRIDE_ENA_5), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_6 (PINS_AC_HMC_DATA_OVERRIDE_ENA_6), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_7 (PINS_AC_HMC_DATA_OVERRIDE_ENA_7), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_8 (PINS_AC_HMC_DATA_OVERRIDE_ENA_8), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_9 (PINS_AC_HMC_DATA_OVERRIDE_ENA_9), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_10 (PINS_AC_HMC_DATA_OVERRIDE_ENA_10), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_11 (PINS_AC_HMC_DATA_OVERRIDE_ENA_11), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_12 (PINS_AC_HMC_DATA_OVERRIDE_ENA_12), + .PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT (PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT), + .PINS_OCT_MODE_0 (PINS_OCT_MODE_0), + .PINS_OCT_MODE_1 (PINS_OCT_MODE_1), + .PINS_OCT_MODE_2 (PINS_OCT_MODE_2), + .PINS_OCT_MODE_3 (PINS_OCT_MODE_3), + .PINS_OCT_MODE_4 (PINS_OCT_MODE_4), + .PINS_OCT_MODE_5 (PINS_OCT_MODE_5), + .PINS_OCT_MODE_6 (PINS_OCT_MODE_6), + .PINS_OCT_MODE_7 (PINS_OCT_MODE_7), + .PINS_OCT_MODE_8 (PINS_OCT_MODE_8), + .PINS_OCT_MODE_9 (PINS_OCT_MODE_9), + .PINS_OCT_MODE_10 (PINS_OCT_MODE_10), + .PINS_OCT_MODE_11 (PINS_OCT_MODE_11), + .PINS_OCT_MODE_12 (PINS_OCT_MODE_12), + .PINS_OCT_MODE_AUTOGEN_WCNT (PINS_OCT_MODE_AUTOGEN_WCNT), + .PINS_GPIO_MODE_0 (PINS_GPIO_MODE_0), + .PINS_GPIO_MODE_1 (PINS_GPIO_MODE_1), + .PINS_GPIO_MODE_2 (PINS_GPIO_MODE_2), + .PINS_GPIO_MODE_3 (PINS_GPIO_MODE_3), + .PINS_GPIO_MODE_4 (PINS_GPIO_MODE_4), + .PINS_GPIO_MODE_5 (PINS_GPIO_MODE_5), + .PINS_GPIO_MODE_6 (PINS_GPIO_MODE_6), + .PINS_GPIO_MODE_7 (PINS_GPIO_MODE_7), + .PINS_GPIO_MODE_8 (PINS_GPIO_MODE_8), + .PINS_GPIO_MODE_9 (PINS_GPIO_MODE_9), + .PINS_GPIO_MODE_10 (PINS_GPIO_MODE_10), + .PINS_GPIO_MODE_11 (PINS_GPIO_MODE_11), + .PINS_GPIO_MODE_12 (PINS_GPIO_MODE_12), + .PINS_GPIO_MODE_AUTOGEN_WCNT (PINS_GPIO_MODE_AUTOGEN_WCNT), + .UNUSED_MEM_PINS_PINLOC_0 (UNUSED_MEM_PINS_PINLOC_0), + .UNUSED_MEM_PINS_PINLOC_1 (UNUSED_MEM_PINS_PINLOC_1), + .UNUSED_MEM_PINS_PINLOC_2 (UNUSED_MEM_PINS_PINLOC_2), + .UNUSED_MEM_PINS_PINLOC_3 (UNUSED_MEM_PINS_PINLOC_3), + .UNUSED_MEM_PINS_PINLOC_4 (UNUSED_MEM_PINS_PINLOC_4), + .UNUSED_MEM_PINS_PINLOC_5 (UNUSED_MEM_PINS_PINLOC_5), + .UNUSED_MEM_PINS_PINLOC_6 (UNUSED_MEM_PINS_PINLOC_6), + .UNUSED_MEM_PINS_PINLOC_7 (UNUSED_MEM_PINS_PINLOC_7), + .UNUSED_MEM_PINS_PINLOC_8 (UNUSED_MEM_PINS_PINLOC_8), + .UNUSED_MEM_PINS_PINLOC_9 (UNUSED_MEM_PINS_PINLOC_9), + .UNUSED_MEM_PINS_PINLOC_10 (UNUSED_MEM_PINS_PINLOC_10), + .UNUSED_MEM_PINS_PINLOC_11 (UNUSED_MEM_PINS_PINLOC_11), + .UNUSED_MEM_PINS_PINLOC_12 (UNUSED_MEM_PINS_PINLOC_12), + .UNUSED_MEM_PINS_PINLOC_13 (UNUSED_MEM_PINS_PINLOC_13), + .UNUSED_MEM_PINS_PINLOC_14 (UNUSED_MEM_PINS_PINLOC_14), + .UNUSED_MEM_PINS_PINLOC_15 (UNUSED_MEM_PINS_PINLOC_15), + .UNUSED_MEM_PINS_PINLOC_16 (UNUSED_MEM_PINS_PINLOC_16), + .UNUSED_MEM_PINS_PINLOC_17 (UNUSED_MEM_PINS_PINLOC_17), + .UNUSED_MEM_PINS_PINLOC_18 (UNUSED_MEM_PINS_PINLOC_18), + .UNUSED_MEM_PINS_PINLOC_19 (UNUSED_MEM_PINS_PINLOC_19), + .UNUSED_MEM_PINS_PINLOC_20 (UNUSED_MEM_PINS_PINLOC_20), + .UNUSED_MEM_PINS_PINLOC_21 (UNUSED_MEM_PINS_PINLOC_21), + .UNUSED_MEM_PINS_PINLOC_22 (UNUSED_MEM_PINS_PINLOC_22), + .UNUSED_MEM_PINS_PINLOC_23 (UNUSED_MEM_PINS_PINLOC_23), + .UNUSED_MEM_PINS_PINLOC_24 (UNUSED_MEM_PINS_PINLOC_24), + .UNUSED_MEM_PINS_PINLOC_25 (UNUSED_MEM_PINS_PINLOC_25), + .UNUSED_MEM_PINS_PINLOC_26 (UNUSED_MEM_PINS_PINLOC_26), + .UNUSED_MEM_PINS_PINLOC_27 (UNUSED_MEM_PINS_PINLOC_27), + .UNUSED_MEM_PINS_PINLOC_28 (UNUSED_MEM_PINS_PINLOC_28), + .UNUSED_MEM_PINS_PINLOC_29 (UNUSED_MEM_PINS_PINLOC_29), + .UNUSED_MEM_PINS_PINLOC_30 (UNUSED_MEM_PINS_PINLOC_30), + .UNUSED_MEM_PINS_PINLOC_31 (UNUSED_MEM_PINS_PINLOC_31), + .UNUSED_MEM_PINS_PINLOC_32 (UNUSED_MEM_PINS_PINLOC_32), + .UNUSED_MEM_PINS_PINLOC_33 (UNUSED_MEM_PINS_PINLOC_33), + .UNUSED_MEM_PINS_PINLOC_34 (UNUSED_MEM_PINS_PINLOC_34), + .UNUSED_MEM_PINS_PINLOC_35 (UNUSED_MEM_PINS_PINLOC_35), + .UNUSED_MEM_PINS_PINLOC_36 (UNUSED_MEM_PINS_PINLOC_36), + .UNUSED_MEM_PINS_PINLOC_37 (UNUSED_MEM_PINS_PINLOC_37), + .UNUSED_MEM_PINS_PINLOC_38 (UNUSED_MEM_PINS_PINLOC_38), + .UNUSED_MEM_PINS_PINLOC_39 (UNUSED_MEM_PINS_PINLOC_39), + .UNUSED_MEM_PINS_PINLOC_40 (UNUSED_MEM_PINS_PINLOC_40), + .UNUSED_MEM_PINS_PINLOC_41 (UNUSED_MEM_PINS_PINLOC_41), + .UNUSED_MEM_PINS_PINLOC_42 (UNUSED_MEM_PINS_PINLOC_42), + .UNUSED_MEM_PINS_PINLOC_43 (UNUSED_MEM_PINS_PINLOC_43), + .UNUSED_MEM_PINS_PINLOC_44 (UNUSED_MEM_PINS_PINLOC_44), + .UNUSED_MEM_PINS_PINLOC_45 (UNUSED_MEM_PINS_PINLOC_45), + .UNUSED_MEM_PINS_PINLOC_46 (UNUSED_MEM_PINS_PINLOC_46), + .UNUSED_MEM_PINS_PINLOC_47 (UNUSED_MEM_PINS_PINLOC_47), + .UNUSED_MEM_PINS_PINLOC_48 (UNUSED_MEM_PINS_PINLOC_48), + .UNUSED_MEM_PINS_PINLOC_49 (UNUSED_MEM_PINS_PINLOC_49), + .UNUSED_MEM_PINS_PINLOC_50 (UNUSED_MEM_PINS_PINLOC_50), + .UNUSED_MEM_PINS_PINLOC_51 (UNUSED_MEM_PINS_PINLOC_51), + .UNUSED_MEM_PINS_PINLOC_52 (UNUSED_MEM_PINS_PINLOC_52), + .UNUSED_MEM_PINS_PINLOC_53 (UNUSED_MEM_PINS_PINLOC_53), + .UNUSED_MEM_PINS_PINLOC_54 (UNUSED_MEM_PINS_PINLOC_54), + .UNUSED_MEM_PINS_PINLOC_55 (UNUSED_MEM_PINS_PINLOC_55), + .UNUSED_MEM_PINS_PINLOC_56 (UNUSED_MEM_PINS_PINLOC_56), + .UNUSED_MEM_PINS_PINLOC_57 (UNUSED_MEM_PINS_PINLOC_57), + .UNUSED_MEM_PINS_PINLOC_58 (UNUSED_MEM_PINS_PINLOC_58), + .UNUSED_MEM_PINS_PINLOC_59 (UNUSED_MEM_PINS_PINLOC_59), + .UNUSED_MEM_PINS_PINLOC_60 (UNUSED_MEM_PINS_PINLOC_60), + .UNUSED_MEM_PINS_PINLOC_61 (UNUSED_MEM_PINS_PINLOC_61), + .UNUSED_MEM_PINS_PINLOC_62 (UNUSED_MEM_PINS_PINLOC_62), + .UNUSED_MEM_PINS_PINLOC_63 (UNUSED_MEM_PINS_PINLOC_63), + .UNUSED_MEM_PINS_PINLOC_64 (UNUSED_MEM_PINS_PINLOC_64), + .UNUSED_MEM_PINS_PINLOC_65 (UNUSED_MEM_PINS_PINLOC_65), + .UNUSED_MEM_PINS_PINLOC_66 (UNUSED_MEM_PINS_PINLOC_66), + .UNUSED_MEM_PINS_PINLOC_67 (UNUSED_MEM_PINS_PINLOC_67), + .UNUSED_MEM_PINS_PINLOC_68 (UNUSED_MEM_PINS_PINLOC_68), + .UNUSED_MEM_PINS_PINLOC_69 (UNUSED_MEM_PINS_PINLOC_69), + .UNUSED_MEM_PINS_PINLOC_70 (UNUSED_MEM_PINS_PINLOC_70), + .UNUSED_MEM_PINS_PINLOC_71 (UNUSED_MEM_PINS_PINLOC_71), + .UNUSED_MEM_PINS_PINLOC_72 (UNUSED_MEM_PINS_PINLOC_72), + .UNUSED_MEM_PINS_PINLOC_73 (UNUSED_MEM_PINS_PINLOC_73), + .UNUSED_MEM_PINS_PINLOC_74 (UNUSED_MEM_PINS_PINLOC_74), + .UNUSED_MEM_PINS_PINLOC_75 (UNUSED_MEM_PINS_PINLOC_75), + .UNUSED_MEM_PINS_PINLOC_76 (UNUSED_MEM_PINS_PINLOC_76), + .UNUSED_MEM_PINS_PINLOC_77 (UNUSED_MEM_PINS_PINLOC_77), + .UNUSED_MEM_PINS_PINLOC_78 (UNUSED_MEM_PINS_PINLOC_78), + .UNUSED_MEM_PINS_PINLOC_79 (UNUSED_MEM_PINS_PINLOC_79), + .UNUSED_MEM_PINS_PINLOC_80 (UNUSED_MEM_PINS_PINLOC_80), + .UNUSED_MEM_PINS_PINLOC_81 (UNUSED_MEM_PINS_PINLOC_81), + .UNUSED_MEM_PINS_PINLOC_82 (UNUSED_MEM_PINS_PINLOC_82), + .UNUSED_MEM_PINS_PINLOC_83 (UNUSED_MEM_PINS_PINLOC_83), + .UNUSED_MEM_PINS_PINLOC_84 (UNUSED_MEM_PINS_PINLOC_84), + .UNUSED_MEM_PINS_PINLOC_85 (UNUSED_MEM_PINS_PINLOC_85), + .UNUSED_MEM_PINS_PINLOC_86 (UNUSED_MEM_PINS_PINLOC_86), + .UNUSED_MEM_PINS_PINLOC_87 (UNUSED_MEM_PINS_PINLOC_87), + .UNUSED_MEM_PINS_PINLOC_88 (UNUSED_MEM_PINS_PINLOC_88), + .UNUSED_MEM_PINS_PINLOC_89 (UNUSED_MEM_PINS_PINLOC_89), + .UNUSED_MEM_PINS_PINLOC_90 (UNUSED_MEM_PINS_PINLOC_90), + .UNUSED_MEM_PINS_PINLOC_91 (UNUSED_MEM_PINS_PINLOC_91), + .UNUSED_MEM_PINS_PINLOC_92 (UNUSED_MEM_PINS_PINLOC_92), + .UNUSED_MEM_PINS_PINLOC_93 (UNUSED_MEM_PINS_PINLOC_93), + .UNUSED_MEM_PINS_PINLOC_94 (UNUSED_MEM_PINS_PINLOC_94), + .UNUSED_MEM_PINS_PINLOC_95 (UNUSED_MEM_PINS_PINLOC_95), + .UNUSED_MEM_PINS_PINLOC_96 (UNUSED_MEM_PINS_PINLOC_96), + .UNUSED_MEM_PINS_PINLOC_97 (UNUSED_MEM_PINS_PINLOC_97), + .UNUSED_MEM_PINS_PINLOC_98 (UNUSED_MEM_PINS_PINLOC_98), + .UNUSED_MEM_PINS_PINLOC_99 (UNUSED_MEM_PINS_PINLOC_99), + .UNUSED_MEM_PINS_PINLOC_100 (UNUSED_MEM_PINS_PINLOC_100), + .UNUSED_MEM_PINS_PINLOC_101 (UNUSED_MEM_PINS_PINLOC_101), + .UNUSED_MEM_PINS_PINLOC_102 (UNUSED_MEM_PINS_PINLOC_102), + .UNUSED_MEM_PINS_PINLOC_103 (UNUSED_MEM_PINS_PINLOC_103), + .UNUSED_MEM_PINS_PINLOC_104 (UNUSED_MEM_PINS_PINLOC_104), + .UNUSED_MEM_PINS_PINLOC_105 (UNUSED_MEM_PINS_PINLOC_105), + .UNUSED_MEM_PINS_PINLOC_106 (UNUSED_MEM_PINS_PINLOC_106), + .UNUSED_MEM_PINS_PINLOC_107 (UNUSED_MEM_PINS_PINLOC_107), + .UNUSED_MEM_PINS_PINLOC_108 (UNUSED_MEM_PINS_PINLOC_108), + .UNUSED_MEM_PINS_PINLOC_109 (UNUSED_MEM_PINS_PINLOC_109), + .UNUSED_MEM_PINS_PINLOC_110 (UNUSED_MEM_PINS_PINLOC_110), + .UNUSED_MEM_PINS_PINLOC_111 (UNUSED_MEM_PINS_PINLOC_111), + .UNUSED_MEM_PINS_PINLOC_112 (UNUSED_MEM_PINS_PINLOC_112), + .UNUSED_MEM_PINS_PINLOC_113 (UNUSED_MEM_PINS_PINLOC_113), + .UNUSED_MEM_PINS_PINLOC_114 (UNUSED_MEM_PINS_PINLOC_114), + .UNUSED_MEM_PINS_PINLOC_115 (UNUSED_MEM_PINS_PINLOC_115), + .UNUSED_MEM_PINS_PINLOC_116 (UNUSED_MEM_PINS_PINLOC_116), + .UNUSED_MEM_PINS_PINLOC_117 (UNUSED_MEM_PINS_PINLOC_117), + .UNUSED_MEM_PINS_PINLOC_118 (UNUSED_MEM_PINS_PINLOC_118), + .UNUSED_MEM_PINS_PINLOC_119 (UNUSED_MEM_PINS_PINLOC_119), + .UNUSED_MEM_PINS_PINLOC_120 (UNUSED_MEM_PINS_PINLOC_120), + .UNUSED_MEM_PINS_PINLOC_121 (UNUSED_MEM_PINS_PINLOC_121), + .UNUSED_MEM_PINS_PINLOC_122 (UNUSED_MEM_PINS_PINLOC_122), + .UNUSED_MEM_PINS_PINLOC_123 (UNUSED_MEM_PINS_PINLOC_123), + .UNUSED_MEM_PINS_PINLOC_124 (UNUSED_MEM_PINS_PINLOC_124), + .UNUSED_MEM_PINS_PINLOC_125 (UNUSED_MEM_PINS_PINLOC_125), + .UNUSED_MEM_PINS_PINLOC_126 (UNUSED_MEM_PINS_PINLOC_126), + .UNUSED_MEM_PINS_PINLOC_127 (UNUSED_MEM_PINS_PINLOC_127), + .UNUSED_MEM_PINS_PINLOC_128 (UNUSED_MEM_PINS_PINLOC_128), + .UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT (UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT), + .UNUSED_DQS_BUSES_LANELOC_0 (UNUSED_DQS_BUSES_LANELOC_0), + .UNUSED_DQS_BUSES_LANELOC_1 (UNUSED_DQS_BUSES_LANELOC_1), + .UNUSED_DQS_BUSES_LANELOC_2 (UNUSED_DQS_BUSES_LANELOC_2), + .UNUSED_DQS_BUSES_LANELOC_3 (UNUSED_DQS_BUSES_LANELOC_3), + .UNUSED_DQS_BUSES_LANELOC_4 (UNUSED_DQS_BUSES_LANELOC_4), + .UNUSED_DQS_BUSES_LANELOC_5 (UNUSED_DQS_BUSES_LANELOC_5), + .UNUSED_DQS_BUSES_LANELOC_6 (UNUSED_DQS_BUSES_LANELOC_6), + .UNUSED_DQS_BUSES_LANELOC_7 (UNUSED_DQS_BUSES_LANELOC_7), + .UNUSED_DQS_BUSES_LANELOC_8 (UNUSED_DQS_BUSES_LANELOC_8), + .UNUSED_DQS_BUSES_LANELOC_9 (UNUSED_DQS_BUSES_LANELOC_9), + .UNUSED_DQS_BUSES_LANELOC_10 (UNUSED_DQS_BUSES_LANELOC_10), + .UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT (UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT), + .CENTER_TIDS_0 (CENTER_TIDS_0), + .CENTER_TIDS_1 (CENTER_TIDS_1), + .CENTER_TIDS_2 (CENTER_TIDS_2), + .CENTER_TIDS_AUTOGEN_WCNT (CENTER_TIDS_AUTOGEN_WCNT), + .HMC_TIDS_0 (HMC_TIDS_0), + .HMC_TIDS_1 (HMC_TIDS_1), + .HMC_TIDS_2 (HMC_TIDS_2), + .HMC_TIDS_AUTOGEN_WCNT (HMC_TIDS_AUTOGEN_WCNT), + .LANE_TIDS_0 (LANE_TIDS_0), + .LANE_TIDS_1 (LANE_TIDS_1), + .LANE_TIDS_2 (LANE_TIDS_2), + .LANE_TIDS_3 (LANE_TIDS_3), + .LANE_TIDS_4 (LANE_TIDS_4), + .LANE_TIDS_5 (LANE_TIDS_5), + .LANE_TIDS_6 (LANE_TIDS_6), + .LANE_TIDS_7 (LANE_TIDS_7), + .LANE_TIDS_8 (LANE_TIDS_8), + .LANE_TIDS_9 (LANE_TIDS_9), + .LANE_TIDS_AUTOGEN_WCNT (LANE_TIDS_AUTOGEN_WCNT), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_HAS_DCC (PHY_HAS_DCC), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC (SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_PINLOC_0 (PORT_MEM_CK_PINLOC_0), + .PORT_MEM_CK_PINLOC_1 (PORT_MEM_CK_PINLOC_1), + .PORT_MEM_CK_PINLOC_2 (PORT_MEM_CK_PINLOC_2), + .PORT_MEM_CK_PINLOC_3 (PORT_MEM_CK_PINLOC_3), + .PORT_MEM_CK_PINLOC_4 (PORT_MEM_CK_PINLOC_4), + .PORT_MEM_CK_PINLOC_5 (PORT_MEM_CK_PINLOC_5), + .PORT_MEM_CK_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_CK_N_PINLOC_0 (PORT_MEM_CK_N_PINLOC_0), + .PORT_MEM_CK_N_PINLOC_1 (PORT_MEM_CK_N_PINLOC_1), + .PORT_MEM_CK_N_PINLOC_2 (PORT_MEM_CK_N_PINLOC_2), + .PORT_MEM_CK_N_PINLOC_3 (PORT_MEM_CK_N_PINLOC_3), + .PORT_MEM_CK_N_PINLOC_4 (PORT_MEM_CK_N_PINLOC_4), + .PORT_MEM_CK_N_PINLOC_5 (PORT_MEM_CK_N_PINLOC_5), + .PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_PINLOC_0 (PORT_MEM_DK_PINLOC_0), + .PORT_MEM_DK_PINLOC_1 (PORT_MEM_DK_PINLOC_1), + .PORT_MEM_DK_PINLOC_2 (PORT_MEM_DK_PINLOC_2), + .PORT_MEM_DK_PINLOC_3 (PORT_MEM_DK_PINLOC_3), + .PORT_MEM_DK_PINLOC_4 (PORT_MEM_DK_PINLOC_4), + .PORT_MEM_DK_PINLOC_5 (PORT_MEM_DK_PINLOC_5), + .PORT_MEM_DK_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DK_N_PINLOC_0 (PORT_MEM_DK_N_PINLOC_0), + .PORT_MEM_DK_N_PINLOC_1 (PORT_MEM_DK_N_PINLOC_1), + .PORT_MEM_DK_N_PINLOC_2 (PORT_MEM_DK_N_PINLOC_2), + .PORT_MEM_DK_N_PINLOC_3 (PORT_MEM_DK_N_PINLOC_3), + .PORT_MEM_DK_N_PINLOC_4 (PORT_MEM_DK_N_PINLOC_4), + .PORT_MEM_DK_N_PINLOC_5 (PORT_MEM_DK_N_PINLOC_5), + .PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_PINLOC_0 (PORT_MEM_DKA_PINLOC_0), + .PORT_MEM_DKA_PINLOC_1 (PORT_MEM_DKA_PINLOC_1), + .PORT_MEM_DKA_PINLOC_2 (PORT_MEM_DKA_PINLOC_2), + .PORT_MEM_DKA_PINLOC_3 (PORT_MEM_DKA_PINLOC_3), + .PORT_MEM_DKA_PINLOC_4 (PORT_MEM_DKA_PINLOC_4), + .PORT_MEM_DKA_PINLOC_5 (PORT_MEM_DKA_PINLOC_5), + .PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKA_N_PINLOC_0 (PORT_MEM_DKA_N_PINLOC_0), + .PORT_MEM_DKA_N_PINLOC_1 (PORT_MEM_DKA_N_PINLOC_1), + .PORT_MEM_DKA_N_PINLOC_2 (PORT_MEM_DKA_N_PINLOC_2), + .PORT_MEM_DKA_N_PINLOC_3 (PORT_MEM_DKA_N_PINLOC_3), + .PORT_MEM_DKA_N_PINLOC_4 (PORT_MEM_DKA_N_PINLOC_4), + .PORT_MEM_DKA_N_PINLOC_5 (PORT_MEM_DKA_N_PINLOC_5), + .PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_PINLOC_0 (PORT_MEM_DKB_PINLOC_0), + .PORT_MEM_DKB_PINLOC_1 (PORT_MEM_DKB_PINLOC_1), + .PORT_MEM_DKB_PINLOC_2 (PORT_MEM_DKB_PINLOC_2), + .PORT_MEM_DKB_PINLOC_3 (PORT_MEM_DKB_PINLOC_3), + .PORT_MEM_DKB_PINLOC_4 (PORT_MEM_DKB_PINLOC_4), + .PORT_MEM_DKB_PINLOC_5 (PORT_MEM_DKB_PINLOC_5), + .PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_DKB_N_PINLOC_0 (PORT_MEM_DKB_N_PINLOC_0), + .PORT_MEM_DKB_N_PINLOC_1 (PORT_MEM_DKB_N_PINLOC_1), + .PORT_MEM_DKB_N_PINLOC_2 (PORT_MEM_DKB_N_PINLOC_2), + .PORT_MEM_DKB_N_PINLOC_3 (PORT_MEM_DKB_N_PINLOC_3), + .PORT_MEM_DKB_N_PINLOC_4 (PORT_MEM_DKB_N_PINLOC_4), + .PORT_MEM_DKB_N_PINLOC_5 (PORT_MEM_DKB_N_PINLOC_5), + .PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_PINLOC_0 (PORT_MEM_K_PINLOC_0), + .PORT_MEM_K_PINLOC_1 (PORT_MEM_K_PINLOC_1), + .PORT_MEM_K_PINLOC_2 (PORT_MEM_K_PINLOC_2), + .PORT_MEM_K_PINLOC_3 (PORT_MEM_K_PINLOC_3), + .PORT_MEM_K_PINLOC_4 (PORT_MEM_K_PINLOC_4), + .PORT_MEM_K_PINLOC_5 (PORT_MEM_K_PINLOC_5), + .PORT_MEM_K_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_K_N_PINLOC_0 (PORT_MEM_K_N_PINLOC_0), + .PORT_MEM_K_N_PINLOC_1 (PORT_MEM_K_N_PINLOC_1), + .PORT_MEM_K_N_PINLOC_2 (PORT_MEM_K_N_PINLOC_2), + .PORT_MEM_K_N_PINLOC_3 (PORT_MEM_K_N_PINLOC_3), + .PORT_MEM_K_N_PINLOC_4 (PORT_MEM_K_N_PINLOC_4), + .PORT_MEM_K_N_PINLOC_5 (PORT_MEM_K_N_PINLOC_5), + .PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_A_PINLOC_0 (PORT_MEM_A_PINLOC_0), + .PORT_MEM_A_PINLOC_1 (PORT_MEM_A_PINLOC_1), + .PORT_MEM_A_PINLOC_2 (PORT_MEM_A_PINLOC_2), + .PORT_MEM_A_PINLOC_3 (PORT_MEM_A_PINLOC_3), + .PORT_MEM_A_PINLOC_4 (PORT_MEM_A_PINLOC_4), + .PORT_MEM_A_PINLOC_5 (PORT_MEM_A_PINLOC_5), + .PORT_MEM_A_PINLOC_6 (PORT_MEM_A_PINLOC_6), + .PORT_MEM_A_PINLOC_7 (PORT_MEM_A_PINLOC_7), + .PORT_MEM_A_PINLOC_8 (PORT_MEM_A_PINLOC_8), + .PORT_MEM_A_PINLOC_9 (PORT_MEM_A_PINLOC_9), + .PORT_MEM_A_PINLOC_10 (PORT_MEM_A_PINLOC_10), + .PORT_MEM_A_PINLOC_11 (PORT_MEM_A_PINLOC_11), + .PORT_MEM_A_PINLOC_12 (PORT_MEM_A_PINLOC_12), + .PORT_MEM_A_PINLOC_13 (PORT_MEM_A_PINLOC_13), + .PORT_MEM_A_PINLOC_14 (PORT_MEM_A_PINLOC_14), + .PORT_MEM_A_PINLOC_15 (PORT_MEM_A_PINLOC_15), + .PORT_MEM_A_PINLOC_16 (PORT_MEM_A_PINLOC_16), + .PORT_MEM_A_PINLOC_AUTOGEN_WCNT (PORT_MEM_A_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BA_PINLOC_0 (PORT_MEM_BA_PINLOC_0), + .PORT_MEM_BA_PINLOC_1 (PORT_MEM_BA_PINLOC_1), + .PORT_MEM_BA_PINLOC_2 (PORT_MEM_BA_PINLOC_2), + .PORT_MEM_BA_PINLOC_3 (PORT_MEM_BA_PINLOC_3), + .PORT_MEM_BA_PINLOC_4 (PORT_MEM_BA_PINLOC_4), + .PORT_MEM_BA_PINLOC_5 (PORT_MEM_BA_PINLOC_5), + .PORT_MEM_BA_PINLOC_AUTOGEN_WCNT (PORT_MEM_BA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_BG_PINLOC_0 (PORT_MEM_BG_PINLOC_0), + .PORT_MEM_BG_PINLOC_1 (PORT_MEM_BG_PINLOC_1), + .PORT_MEM_BG_PINLOC_2 (PORT_MEM_BG_PINLOC_2), + .PORT_MEM_BG_PINLOC_3 (PORT_MEM_BG_PINLOC_3), + .PORT_MEM_BG_PINLOC_4 (PORT_MEM_BG_PINLOC_4), + .PORT_MEM_BG_PINLOC_5 (PORT_MEM_BG_PINLOC_5), + .PORT_MEM_BG_PINLOC_AUTOGEN_WCNT (PORT_MEM_BG_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_C_PINLOC_0 (PORT_MEM_C_PINLOC_0), + .PORT_MEM_C_PINLOC_1 (PORT_MEM_C_PINLOC_1), + .PORT_MEM_C_PINLOC_2 (PORT_MEM_C_PINLOC_2), + .PORT_MEM_C_PINLOC_3 (PORT_MEM_C_PINLOC_3), + .PORT_MEM_C_PINLOC_4 (PORT_MEM_C_PINLOC_4), + .PORT_MEM_C_PINLOC_5 (PORT_MEM_C_PINLOC_5), + .PORT_MEM_C_PINLOC_AUTOGEN_WCNT (PORT_MEM_C_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CKE_PINLOC_0 (PORT_MEM_CKE_PINLOC_0), + .PORT_MEM_CKE_PINLOC_1 (PORT_MEM_CKE_PINLOC_1), + .PORT_MEM_CKE_PINLOC_2 (PORT_MEM_CKE_PINLOC_2), + .PORT_MEM_CKE_PINLOC_3 (PORT_MEM_CKE_PINLOC_3), + .PORT_MEM_CKE_PINLOC_4 (PORT_MEM_CKE_PINLOC_4), + .PORT_MEM_CKE_PINLOC_5 (PORT_MEM_CKE_PINLOC_5), + .PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT (PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_CS_N_PINLOC_0 (PORT_MEM_CS_N_PINLOC_0), + .PORT_MEM_CS_N_PINLOC_1 (PORT_MEM_CS_N_PINLOC_1), + .PORT_MEM_CS_N_PINLOC_2 (PORT_MEM_CS_N_PINLOC_2), + .PORT_MEM_CS_N_PINLOC_3 (PORT_MEM_CS_N_PINLOC_3), + .PORT_MEM_CS_N_PINLOC_4 (PORT_MEM_CS_N_PINLOC_4), + .PORT_MEM_CS_N_PINLOC_5 (PORT_MEM_CS_N_PINLOC_5), + .PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_RM_PINLOC_0 (PORT_MEM_RM_PINLOC_0), + .PORT_MEM_RM_PINLOC_1 (PORT_MEM_RM_PINLOC_1), + .PORT_MEM_RM_PINLOC_2 (PORT_MEM_RM_PINLOC_2), + .PORT_MEM_RM_PINLOC_3 (PORT_MEM_RM_PINLOC_3), + .PORT_MEM_RM_PINLOC_4 (PORT_MEM_RM_PINLOC_4), + .PORT_MEM_RM_PINLOC_5 (PORT_MEM_RM_PINLOC_5), + .PORT_MEM_RM_PINLOC_AUTOGEN_WCNT (PORT_MEM_RM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_ODT_PINLOC_0 (PORT_MEM_ODT_PINLOC_0), + .PORT_MEM_ODT_PINLOC_1 (PORT_MEM_ODT_PINLOC_1), + .PORT_MEM_ODT_PINLOC_2 (PORT_MEM_ODT_PINLOC_2), + .PORT_MEM_ODT_PINLOC_3 (PORT_MEM_ODT_PINLOC_3), + .PORT_MEM_ODT_PINLOC_4 (PORT_MEM_ODT_PINLOC_4), + .PORT_MEM_ODT_PINLOC_5 (PORT_MEM_ODT_PINLOC_5), + .PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT (PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_RAS_N_PINLOC_0 (PORT_MEM_RAS_N_PINLOC_0), + .PORT_MEM_RAS_N_PINLOC_1 (PORT_MEM_RAS_N_PINLOC_1), + .PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_CAS_N_PINLOC_0 (PORT_MEM_CAS_N_PINLOC_0), + .PORT_MEM_CAS_N_PINLOC_1 (PORT_MEM_CAS_N_PINLOC_1), + .PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_WE_N_PINLOC_0 (PORT_MEM_WE_N_PINLOC_0), + .PORT_MEM_WE_N_PINLOC_1 (PORT_MEM_WE_N_PINLOC_1), + .PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_RESET_N_PINLOC_0 (PORT_MEM_RESET_N_PINLOC_0), + .PORT_MEM_RESET_N_PINLOC_1 (PORT_MEM_RESET_N_PINLOC_1), + .PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_ACT_N_PINLOC_0 (PORT_MEM_ACT_N_PINLOC_0), + .PORT_MEM_ACT_N_PINLOC_1 (PORT_MEM_ACT_N_PINLOC_1), + .PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_PAR_PINLOC_0 (PORT_MEM_PAR_PINLOC_0), + .PORT_MEM_PAR_PINLOC_1 (PORT_MEM_PAR_PINLOC_1), + .PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT (PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_CA_PINLOC_0 (PORT_MEM_CA_PINLOC_0), + .PORT_MEM_CA_PINLOC_1 (PORT_MEM_CA_PINLOC_1), + .PORT_MEM_CA_PINLOC_2 (PORT_MEM_CA_PINLOC_2), + .PORT_MEM_CA_PINLOC_3 (PORT_MEM_CA_PINLOC_3), + .PORT_MEM_CA_PINLOC_4 (PORT_MEM_CA_PINLOC_4), + .PORT_MEM_CA_PINLOC_5 (PORT_MEM_CA_PINLOC_5), + .PORT_MEM_CA_PINLOC_6 (PORT_MEM_CA_PINLOC_6), + .PORT_MEM_CA_PINLOC_7 (PORT_MEM_CA_PINLOC_7), + .PORT_MEM_CA_PINLOC_8 (PORT_MEM_CA_PINLOC_8), + .PORT_MEM_CA_PINLOC_9 (PORT_MEM_CA_PINLOC_9), + .PORT_MEM_CA_PINLOC_10 (PORT_MEM_CA_PINLOC_10), + .PORT_MEM_CA_PINLOC_11 (PORT_MEM_CA_PINLOC_11), + .PORT_MEM_CA_PINLOC_12 (PORT_MEM_CA_PINLOC_12), + .PORT_MEM_CA_PINLOC_13 (PORT_MEM_CA_PINLOC_13), + .PORT_MEM_CA_PINLOC_14 (PORT_MEM_CA_PINLOC_14), + .PORT_MEM_CA_PINLOC_15 (PORT_MEM_CA_PINLOC_15), + .PORT_MEM_CA_PINLOC_16 (PORT_MEM_CA_PINLOC_16), + .PORT_MEM_CA_PINLOC_AUTOGEN_WCNT (PORT_MEM_CA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_REF_N_PINLOC_0 (PORT_MEM_REF_N_PINLOC_0), + .PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_WPS_N_PINLOC_0 (PORT_MEM_WPS_N_PINLOC_0), + .PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_RPS_N_PINLOC_0 (PORT_MEM_RPS_N_PINLOC_0), + .PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_DOFF_N_PINLOC_0 (PORT_MEM_DOFF_N_PINLOC_0), + .PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDA_N_PINLOC_0 (PORT_MEM_LDA_N_PINLOC_0), + .PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_LDB_N_PINLOC_0 (PORT_MEM_LDB_N_PINLOC_0), + .PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWA_N_PINLOC_0 (PORT_MEM_RWA_N_PINLOC_0), + .PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_RWB_N_PINLOC_0 (PORT_MEM_RWB_N_PINLOC_0), + .PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK0_N_PINLOC_0 (PORT_MEM_LBK0_N_PINLOC_0), + .PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_LBK1_N_PINLOC_0 (PORT_MEM_LBK1_N_PINLOC_0), + .PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_CFG_N_PINLOC_0 (PORT_MEM_CFG_N_PINLOC_0), + .PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AP_PINLOC_0 (PORT_MEM_AP_PINLOC_0), + .PORT_MEM_AP_PINLOC_AUTOGEN_WCNT (PORT_MEM_AP_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_AINV_PINLOC_0 (PORT_MEM_AINV_PINLOC_0), + .PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT (PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_DM_PINLOC_0 (PORT_MEM_DM_PINLOC_0), + .PORT_MEM_DM_PINLOC_1 (PORT_MEM_DM_PINLOC_1), + .PORT_MEM_DM_PINLOC_2 (PORT_MEM_DM_PINLOC_2), + .PORT_MEM_DM_PINLOC_3 (PORT_MEM_DM_PINLOC_3), + .PORT_MEM_DM_PINLOC_4 (PORT_MEM_DM_PINLOC_4), + .PORT_MEM_DM_PINLOC_5 (PORT_MEM_DM_PINLOC_5), + .PORT_MEM_DM_PINLOC_6 (PORT_MEM_DM_PINLOC_6), + .PORT_MEM_DM_PINLOC_7 (PORT_MEM_DM_PINLOC_7), + .PORT_MEM_DM_PINLOC_8 (PORT_MEM_DM_PINLOC_8), + .PORT_MEM_DM_PINLOC_9 (PORT_MEM_DM_PINLOC_9), + .PORT_MEM_DM_PINLOC_10 (PORT_MEM_DM_PINLOC_10), + .PORT_MEM_DM_PINLOC_11 (PORT_MEM_DM_PINLOC_11), + .PORT_MEM_DM_PINLOC_12 (PORT_MEM_DM_PINLOC_12), + .PORT_MEM_DM_PINLOC_AUTOGEN_WCNT (PORT_MEM_DM_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_BWS_N_PINLOC_0 (PORT_MEM_BWS_N_PINLOC_0), + .PORT_MEM_BWS_N_PINLOC_1 (PORT_MEM_BWS_N_PINLOC_1), + .PORT_MEM_BWS_N_PINLOC_2 (PORT_MEM_BWS_N_PINLOC_2), + .PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_D_PINLOC_0 (PORT_MEM_D_PINLOC_0), + .PORT_MEM_D_PINLOC_1 (PORT_MEM_D_PINLOC_1), + .PORT_MEM_D_PINLOC_2 (PORT_MEM_D_PINLOC_2), + .PORT_MEM_D_PINLOC_3 (PORT_MEM_D_PINLOC_3), + .PORT_MEM_D_PINLOC_4 (PORT_MEM_D_PINLOC_4), + .PORT_MEM_D_PINLOC_5 (PORT_MEM_D_PINLOC_5), + .PORT_MEM_D_PINLOC_6 (PORT_MEM_D_PINLOC_6), + .PORT_MEM_D_PINLOC_7 (PORT_MEM_D_PINLOC_7), + .PORT_MEM_D_PINLOC_8 (PORT_MEM_D_PINLOC_8), + .PORT_MEM_D_PINLOC_9 (PORT_MEM_D_PINLOC_9), + .PORT_MEM_D_PINLOC_10 (PORT_MEM_D_PINLOC_10), + .PORT_MEM_D_PINLOC_11 (PORT_MEM_D_PINLOC_11), + .PORT_MEM_D_PINLOC_12 (PORT_MEM_D_PINLOC_12), + .PORT_MEM_D_PINLOC_13 (PORT_MEM_D_PINLOC_13), + .PORT_MEM_D_PINLOC_14 (PORT_MEM_D_PINLOC_14), + .PORT_MEM_D_PINLOC_15 (PORT_MEM_D_PINLOC_15), + .PORT_MEM_D_PINLOC_16 (PORT_MEM_D_PINLOC_16), + .PORT_MEM_D_PINLOC_17 (PORT_MEM_D_PINLOC_17), + .PORT_MEM_D_PINLOC_18 (PORT_MEM_D_PINLOC_18), + .PORT_MEM_D_PINLOC_19 (PORT_MEM_D_PINLOC_19), + .PORT_MEM_D_PINLOC_20 (PORT_MEM_D_PINLOC_20), + .PORT_MEM_D_PINLOC_21 (PORT_MEM_D_PINLOC_21), + .PORT_MEM_D_PINLOC_22 (PORT_MEM_D_PINLOC_22), + .PORT_MEM_D_PINLOC_23 (PORT_MEM_D_PINLOC_23), + .PORT_MEM_D_PINLOC_24 (PORT_MEM_D_PINLOC_24), + .PORT_MEM_D_PINLOC_25 (PORT_MEM_D_PINLOC_25), + .PORT_MEM_D_PINLOC_26 (PORT_MEM_D_PINLOC_26), + .PORT_MEM_D_PINLOC_27 (PORT_MEM_D_PINLOC_27), + .PORT_MEM_D_PINLOC_28 (PORT_MEM_D_PINLOC_28), + .PORT_MEM_D_PINLOC_29 (PORT_MEM_D_PINLOC_29), + .PORT_MEM_D_PINLOC_30 (PORT_MEM_D_PINLOC_30), + .PORT_MEM_D_PINLOC_31 (PORT_MEM_D_PINLOC_31), + .PORT_MEM_D_PINLOC_32 (PORT_MEM_D_PINLOC_32), + .PORT_MEM_D_PINLOC_33 (PORT_MEM_D_PINLOC_33), + .PORT_MEM_D_PINLOC_34 (PORT_MEM_D_PINLOC_34), + .PORT_MEM_D_PINLOC_35 (PORT_MEM_D_PINLOC_35), + .PORT_MEM_D_PINLOC_36 (PORT_MEM_D_PINLOC_36), + .PORT_MEM_D_PINLOC_37 (PORT_MEM_D_PINLOC_37), + .PORT_MEM_D_PINLOC_38 (PORT_MEM_D_PINLOC_38), + .PORT_MEM_D_PINLOC_39 (PORT_MEM_D_PINLOC_39), + .PORT_MEM_D_PINLOC_40 (PORT_MEM_D_PINLOC_40), + .PORT_MEM_D_PINLOC_41 (PORT_MEM_D_PINLOC_41), + .PORT_MEM_D_PINLOC_42 (PORT_MEM_D_PINLOC_42), + .PORT_MEM_D_PINLOC_43 (PORT_MEM_D_PINLOC_43), + .PORT_MEM_D_PINLOC_44 (PORT_MEM_D_PINLOC_44), + .PORT_MEM_D_PINLOC_45 (PORT_MEM_D_PINLOC_45), + .PORT_MEM_D_PINLOC_46 (PORT_MEM_D_PINLOC_46), + .PORT_MEM_D_PINLOC_47 (PORT_MEM_D_PINLOC_47), + .PORT_MEM_D_PINLOC_48 (PORT_MEM_D_PINLOC_48), + .PORT_MEM_D_PINLOC_AUTOGEN_WCNT (PORT_MEM_D_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DQ_PINLOC_0 (PORT_MEM_DQ_PINLOC_0), + .PORT_MEM_DQ_PINLOC_1 (PORT_MEM_DQ_PINLOC_1), + .PORT_MEM_DQ_PINLOC_2 (PORT_MEM_DQ_PINLOC_2), + .PORT_MEM_DQ_PINLOC_3 (PORT_MEM_DQ_PINLOC_3), + .PORT_MEM_DQ_PINLOC_4 (PORT_MEM_DQ_PINLOC_4), + .PORT_MEM_DQ_PINLOC_5 (PORT_MEM_DQ_PINLOC_5), + .PORT_MEM_DQ_PINLOC_6 (PORT_MEM_DQ_PINLOC_6), + .PORT_MEM_DQ_PINLOC_7 (PORT_MEM_DQ_PINLOC_7), + .PORT_MEM_DQ_PINLOC_8 (PORT_MEM_DQ_PINLOC_8), + .PORT_MEM_DQ_PINLOC_9 (PORT_MEM_DQ_PINLOC_9), + .PORT_MEM_DQ_PINLOC_10 (PORT_MEM_DQ_PINLOC_10), + .PORT_MEM_DQ_PINLOC_11 (PORT_MEM_DQ_PINLOC_11), + .PORT_MEM_DQ_PINLOC_12 (PORT_MEM_DQ_PINLOC_12), + .PORT_MEM_DQ_PINLOC_13 (PORT_MEM_DQ_PINLOC_13), + .PORT_MEM_DQ_PINLOC_14 (PORT_MEM_DQ_PINLOC_14), + .PORT_MEM_DQ_PINLOC_15 (PORT_MEM_DQ_PINLOC_15), + .PORT_MEM_DQ_PINLOC_16 (PORT_MEM_DQ_PINLOC_16), + .PORT_MEM_DQ_PINLOC_17 (PORT_MEM_DQ_PINLOC_17), + .PORT_MEM_DQ_PINLOC_18 (PORT_MEM_DQ_PINLOC_18), + .PORT_MEM_DQ_PINLOC_19 (PORT_MEM_DQ_PINLOC_19), + .PORT_MEM_DQ_PINLOC_20 (PORT_MEM_DQ_PINLOC_20), + .PORT_MEM_DQ_PINLOC_21 (PORT_MEM_DQ_PINLOC_21), + .PORT_MEM_DQ_PINLOC_22 (PORT_MEM_DQ_PINLOC_22), + .PORT_MEM_DQ_PINLOC_23 (PORT_MEM_DQ_PINLOC_23), + .PORT_MEM_DQ_PINLOC_24 (PORT_MEM_DQ_PINLOC_24), + .PORT_MEM_DQ_PINLOC_25 (PORT_MEM_DQ_PINLOC_25), + .PORT_MEM_DQ_PINLOC_26 (PORT_MEM_DQ_PINLOC_26), + .PORT_MEM_DQ_PINLOC_27 (PORT_MEM_DQ_PINLOC_27), + .PORT_MEM_DQ_PINLOC_28 (PORT_MEM_DQ_PINLOC_28), + .PORT_MEM_DQ_PINLOC_29 (PORT_MEM_DQ_PINLOC_29), + .PORT_MEM_DQ_PINLOC_30 (PORT_MEM_DQ_PINLOC_30), + .PORT_MEM_DQ_PINLOC_31 (PORT_MEM_DQ_PINLOC_31), + .PORT_MEM_DQ_PINLOC_32 (PORT_MEM_DQ_PINLOC_32), + .PORT_MEM_DQ_PINLOC_33 (PORT_MEM_DQ_PINLOC_33), + .PORT_MEM_DQ_PINLOC_34 (PORT_MEM_DQ_PINLOC_34), + .PORT_MEM_DQ_PINLOC_35 (PORT_MEM_DQ_PINLOC_35), + .PORT_MEM_DQ_PINLOC_36 (PORT_MEM_DQ_PINLOC_36), + .PORT_MEM_DQ_PINLOC_37 (PORT_MEM_DQ_PINLOC_37), + .PORT_MEM_DQ_PINLOC_38 (PORT_MEM_DQ_PINLOC_38), + .PORT_MEM_DQ_PINLOC_39 (PORT_MEM_DQ_PINLOC_39), + .PORT_MEM_DQ_PINLOC_40 (PORT_MEM_DQ_PINLOC_40), + .PORT_MEM_DQ_PINLOC_41 (PORT_MEM_DQ_PINLOC_41), + .PORT_MEM_DQ_PINLOC_42 (PORT_MEM_DQ_PINLOC_42), + .PORT_MEM_DQ_PINLOC_43 (PORT_MEM_DQ_PINLOC_43), + .PORT_MEM_DQ_PINLOC_44 (PORT_MEM_DQ_PINLOC_44), + .PORT_MEM_DQ_PINLOC_45 (PORT_MEM_DQ_PINLOC_45), + .PORT_MEM_DQ_PINLOC_46 (PORT_MEM_DQ_PINLOC_46), + .PORT_MEM_DQ_PINLOC_47 (PORT_MEM_DQ_PINLOC_47), + .PORT_MEM_DQ_PINLOC_48 (PORT_MEM_DQ_PINLOC_48), + .PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DBI_N_PINLOC_0 (PORT_MEM_DBI_N_PINLOC_0), + .PORT_MEM_DBI_N_PINLOC_1 (PORT_MEM_DBI_N_PINLOC_1), + .PORT_MEM_DBI_N_PINLOC_2 (PORT_MEM_DBI_N_PINLOC_2), + .PORT_MEM_DBI_N_PINLOC_3 (PORT_MEM_DBI_N_PINLOC_3), + .PORT_MEM_DBI_N_PINLOC_4 (PORT_MEM_DBI_N_PINLOC_4), + .PORT_MEM_DBI_N_PINLOC_5 (PORT_MEM_DBI_N_PINLOC_5), + .PORT_MEM_DBI_N_PINLOC_6 (PORT_MEM_DBI_N_PINLOC_6), + .PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQA_PINLOC_0 (PORT_MEM_DQA_PINLOC_0), + .PORT_MEM_DQA_PINLOC_1 (PORT_MEM_DQA_PINLOC_1), + .PORT_MEM_DQA_PINLOC_2 (PORT_MEM_DQA_PINLOC_2), + .PORT_MEM_DQA_PINLOC_3 (PORT_MEM_DQA_PINLOC_3), + .PORT_MEM_DQA_PINLOC_4 (PORT_MEM_DQA_PINLOC_4), + .PORT_MEM_DQA_PINLOC_5 (PORT_MEM_DQA_PINLOC_5), + .PORT_MEM_DQA_PINLOC_6 (PORT_MEM_DQA_PINLOC_6), + .PORT_MEM_DQA_PINLOC_7 (PORT_MEM_DQA_PINLOC_7), + .PORT_MEM_DQA_PINLOC_8 (PORT_MEM_DQA_PINLOC_8), + .PORT_MEM_DQA_PINLOC_9 (PORT_MEM_DQA_PINLOC_9), + .PORT_MEM_DQA_PINLOC_10 (PORT_MEM_DQA_PINLOC_10), + .PORT_MEM_DQA_PINLOC_11 (PORT_MEM_DQA_PINLOC_11), + .PORT_MEM_DQA_PINLOC_12 (PORT_MEM_DQA_PINLOC_12), + .PORT_MEM_DQA_PINLOC_13 (PORT_MEM_DQA_PINLOC_13), + .PORT_MEM_DQA_PINLOC_14 (PORT_MEM_DQA_PINLOC_14), + .PORT_MEM_DQA_PINLOC_15 (PORT_MEM_DQA_PINLOC_15), + .PORT_MEM_DQA_PINLOC_16 (PORT_MEM_DQA_PINLOC_16), + .PORT_MEM_DQA_PINLOC_17 (PORT_MEM_DQA_PINLOC_17), + .PORT_MEM_DQA_PINLOC_18 (PORT_MEM_DQA_PINLOC_18), + .PORT_MEM_DQA_PINLOC_19 (PORT_MEM_DQA_PINLOC_19), + .PORT_MEM_DQA_PINLOC_20 (PORT_MEM_DQA_PINLOC_20), + .PORT_MEM_DQA_PINLOC_21 (PORT_MEM_DQA_PINLOC_21), + .PORT_MEM_DQA_PINLOC_22 (PORT_MEM_DQA_PINLOC_22), + .PORT_MEM_DQA_PINLOC_23 (PORT_MEM_DQA_PINLOC_23), + .PORT_MEM_DQA_PINLOC_24 (PORT_MEM_DQA_PINLOC_24), + .PORT_MEM_DQA_PINLOC_25 (PORT_MEM_DQA_PINLOC_25), + .PORT_MEM_DQA_PINLOC_26 (PORT_MEM_DQA_PINLOC_26), + .PORT_MEM_DQA_PINLOC_27 (PORT_MEM_DQA_PINLOC_27), + .PORT_MEM_DQA_PINLOC_28 (PORT_MEM_DQA_PINLOC_28), + .PORT_MEM_DQA_PINLOC_29 (PORT_MEM_DQA_PINLOC_29), + .PORT_MEM_DQA_PINLOC_30 (PORT_MEM_DQA_PINLOC_30), + .PORT_MEM_DQA_PINLOC_31 (PORT_MEM_DQA_PINLOC_31), + .PORT_MEM_DQA_PINLOC_32 (PORT_MEM_DQA_PINLOC_32), + .PORT_MEM_DQA_PINLOC_33 (PORT_MEM_DQA_PINLOC_33), + .PORT_MEM_DQA_PINLOC_34 (PORT_MEM_DQA_PINLOC_34), + .PORT_MEM_DQA_PINLOC_35 (PORT_MEM_DQA_PINLOC_35), + .PORT_MEM_DQA_PINLOC_36 (PORT_MEM_DQA_PINLOC_36), + .PORT_MEM_DQA_PINLOC_37 (PORT_MEM_DQA_PINLOC_37), + .PORT_MEM_DQA_PINLOC_38 (PORT_MEM_DQA_PINLOC_38), + .PORT_MEM_DQA_PINLOC_39 (PORT_MEM_DQA_PINLOC_39), + .PORT_MEM_DQA_PINLOC_40 (PORT_MEM_DQA_PINLOC_40), + .PORT_MEM_DQA_PINLOC_41 (PORT_MEM_DQA_PINLOC_41), + .PORT_MEM_DQA_PINLOC_42 (PORT_MEM_DQA_PINLOC_42), + .PORT_MEM_DQA_PINLOC_43 (PORT_MEM_DQA_PINLOC_43), + .PORT_MEM_DQA_PINLOC_44 (PORT_MEM_DQA_PINLOC_44), + .PORT_MEM_DQA_PINLOC_45 (PORT_MEM_DQA_PINLOC_45), + .PORT_MEM_DQA_PINLOC_46 (PORT_MEM_DQA_PINLOC_46), + .PORT_MEM_DQA_PINLOC_47 (PORT_MEM_DQA_PINLOC_47), + .PORT_MEM_DQA_PINLOC_48 (PORT_MEM_DQA_PINLOC_48), + .PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DQB_PINLOC_0 (PORT_MEM_DQB_PINLOC_0), + .PORT_MEM_DQB_PINLOC_1 (PORT_MEM_DQB_PINLOC_1), + .PORT_MEM_DQB_PINLOC_2 (PORT_MEM_DQB_PINLOC_2), + .PORT_MEM_DQB_PINLOC_3 (PORT_MEM_DQB_PINLOC_3), + .PORT_MEM_DQB_PINLOC_4 (PORT_MEM_DQB_PINLOC_4), + .PORT_MEM_DQB_PINLOC_5 (PORT_MEM_DQB_PINLOC_5), + .PORT_MEM_DQB_PINLOC_6 (PORT_MEM_DQB_PINLOC_6), + .PORT_MEM_DQB_PINLOC_7 (PORT_MEM_DQB_PINLOC_7), + .PORT_MEM_DQB_PINLOC_8 (PORT_MEM_DQB_PINLOC_8), + .PORT_MEM_DQB_PINLOC_9 (PORT_MEM_DQB_PINLOC_9), + .PORT_MEM_DQB_PINLOC_10 (PORT_MEM_DQB_PINLOC_10), + .PORT_MEM_DQB_PINLOC_11 (PORT_MEM_DQB_PINLOC_11), + .PORT_MEM_DQB_PINLOC_12 (PORT_MEM_DQB_PINLOC_12), + .PORT_MEM_DQB_PINLOC_13 (PORT_MEM_DQB_PINLOC_13), + .PORT_MEM_DQB_PINLOC_14 (PORT_MEM_DQB_PINLOC_14), + .PORT_MEM_DQB_PINLOC_15 (PORT_MEM_DQB_PINLOC_15), + .PORT_MEM_DQB_PINLOC_16 (PORT_MEM_DQB_PINLOC_16), + .PORT_MEM_DQB_PINLOC_17 (PORT_MEM_DQB_PINLOC_17), + .PORT_MEM_DQB_PINLOC_18 (PORT_MEM_DQB_PINLOC_18), + .PORT_MEM_DQB_PINLOC_19 (PORT_MEM_DQB_PINLOC_19), + .PORT_MEM_DQB_PINLOC_20 (PORT_MEM_DQB_PINLOC_20), + .PORT_MEM_DQB_PINLOC_21 (PORT_MEM_DQB_PINLOC_21), + .PORT_MEM_DQB_PINLOC_22 (PORT_MEM_DQB_PINLOC_22), + .PORT_MEM_DQB_PINLOC_23 (PORT_MEM_DQB_PINLOC_23), + .PORT_MEM_DQB_PINLOC_24 (PORT_MEM_DQB_PINLOC_24), + .PORT_MEM_DQB_PINLOC_25 (PORT_MEM_DQB_PINLOC_25), + .PORT_MEM_DQB_PINLOC_26 (PORT_MEM_DQB_PINLOC_26), + .PORT_MEM_DQB_PINLOC_27 (PORT_MEM_DQB_PINLOC_27), + .PORT_MEM_DQB_PINLOC_28 (PORT_MEM_DQB_PINLOC_28), + .PORT_MEM_DQB_PINLOC_29 (PORT_MEM_DQB_PINLOC_29), + .PORT_MEM_DQB_PINLOC_30 (PORT_MEM_DQB_PINLOC_30), + .PORT_MEM_DQB_PINLOC_31 (PORT_MEM_DQB_PINLOC_31), + .PORT_MEM_DQB_PINLOC_32 (PORT_MEM_DQB_PINLOC_32), + .PORT_MEM_DQB_PINLOC_33 (PORT_MEM_DQB_PINLOC_33), + .PORT_MEM_DQB_PINLOC_34 (PORT_MEM_DQB_PINLOC_34), + .PORT_MEM_DQB_PINLOC_35 (PORT_MEM_DQB_PINLOC_35), + .PORT_MEM_DQB_PINLOC_36 (PORT_MEM_DQB_PINLOC_36), + .PORT_MEM_DQB_PINLOC_37 (PORT_MEM_DQB_PINLOC_37), + .PORT_MEM_DQB_PINLOC_38 (PORT_MEM_DQB_PINLOC_38), + .PORT_MEM_DQB_PINLOC_39 (PORT_MEM_DQB_PINLOC_39), + .PORT_MEM_DQB_PINLOC_40 (PORT_MEM_DQB_PINLOC_40), + .PORT_MEM_DQB_PINLOC_41 (PORT_MEM_DQB_PINLOC_41), + .PORT_MEM_DQB_PINLOC_42 (PORT_MEM_DQB_PINLOC_42), + .PORT_MEM_DQB_PINLOC_43 (PORT_MEM_DQB_PINLOC_43), + .PORT_MEM_DQB_PINLOC_44 (PORT_MEM_DQB_PINLOC_44), + .PORT_MEM_DQB_PINLOC_45 (PORT_MEM_DQB_PINLOC_45), + .PORT_MEM_DQB_PINLOC_46 (PORT_MEM_DQB_PINLOC_46), + .PORT_MEM_DQB_PINLOC_47 (PORT_MEM_DQB_PINLOC_47), + .PORT_MEM_DQB_PINLOC_48 (PORT_MEM_DQB_PINLOC_48), + .PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVA_PINLOC_0 (PORT_MEM_DINVA_PINLOC_0), + .PORT_MEM_DINVA_PINLOC_1 (PORT_MEM_DINVA_PINLOC_1), + .PORT_MEM_DINVA_PINLOC_2 (PORT_MEM_DINVA_PINLOC_2), + .PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_DINVB_PINLOC_0 (PORT_MEM_DINVB_PINLOC_0), + .PORT_MEM_DINVB_PINLOC_1 (PORT_MEM_DINVB_PINLOC_1), + .PORT_MEM_DINVB_PINLOC_2 (PORT_MEM_DINVB_PINLOC_2), + .PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT (PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_Q_PINLOC_0 (PORT_MEM_Q_PINLOC_0), + .PORT_MEM_Q_PINLOC_1 (PORT_MEM_Q_PINLOC_1), + .PORT_MEM_Q_PINLOC_2 (PORT_MEM_Q_PINLOC_2), + .PORT_MEM_Q_PINLOC_3 (PORT_MEM_Q_PINLOC_3), + .PORT_MEM_Q_PINLOC_4 (PORT_MEM_Q_PINLOC_4), + .PORT_MEM_Q_PINLOC_5 (PORT_MEM_Q_PINLOC_5), + .PORT_MEM_Q_PINLOC_6 (PORT_MEM_Q_PINLOC_6), + .PORT_MEM_Q_PINLOC_7 (PORT_MEM_Q_PINLOC_7), + .PORT_MEM_Q_PINLOC_8 (PORT_MEM_Q_PINLOC_8), + .PORT_MEM_Q_PINLOC_9 (PORT_MEM_Q_PINLOC_9), + .PORT_MEM_Q_PINLOC_10 (PORT_MEM_Q_PINLOC_10), + .PORT_MEM_Q_PINLOC_11 (PORT_MEM_Q_PINLOC_11), + .PORT_MEM_Q_PINLOC_12 (PORT_MEM_Q_PINLOC_12), + .PORT_MEM_Q_PINLOC_13 (PORT_MEM_Q_PINLOC_13), + .PORT_MEM_Q_PINLOC_14 (PORT_MEM_Q_PINLOC_14), + .PORT_MEM_Q_PINLOC_15 (PORT_MEM_Q_PINLOC_15), + .PORT_MEM_Q_PINLOC_16 (PORT_MEM_Q_PINLOC_16), + .PORT_MEM_Q_PINLOC_17 (PORT_MEM_Q_PINLOC_17), + .PORT_MEM_Q_PINLOC_18 (PORT_MEM_Q_PINLOC_18), + .PORT_MEM_Q_PINLOC_19 (PORT_MEM_Q_PINLOC_19), + .PORT_MEM_Q_PINLOC_20 (PORT_MEM_Q_PINLOC_20), + .PORT_MEM_Q_PINLOC_21 (PORT_MEM_Q_PINLOC_21), + .PORT_MEM_Q_PINLOC_22 (PORT_MEM_Q_PINLOC_22), + .PORT_MEM_Q_PINLOC_23 (PORT_MEM_Q_PINLOC_23), + .PORT_MEM_Q_PINLOC_24 (PORT_MEM_Q_PINLOC_24), + .PORT_MEM_Q_PINLOC_25 (PORT_MEM_Q_PINLOC_25), + .PORT_MEM_Q_PINLOC_26 (PORT_MEM_Q_PINLOC_26), + .PORT_MEM_Q_PINLOC_27 (PORT_MEM_Q_PINLOC_27), + .PORT_MEM_Q_PINLOC_28 (PORT_MEM_Q_PINLOC_28), + .PORT_MEM_Q_PINLOC_29 (PORT_MEM_Q_PINLOC_29), + .PORT_MEM_Q_PINLOC_30 (PORT_MEM_Q_PINLOC_30), + .PORT_MEM_Q_PINLOC_31 (PORT_MEM_Q_PINLOC_31), + .PORT_MEM_Q_PINLOC_32 (PORT_MEM_Q_PINLOC_32), + .PORT_MEM_Q_PINLOC_33 (PORT_MEM_Q_PINLOC_33), + .PORT_MEM_Q_PINLOC_34 (PORT_MEM_Q_PINLOC_34), + .PORT_MEM_Q_PINLOC_35 (PORT_MEM_Q_PINLOC_35), + .PORT_MEM_Q_PINLOC_36 (PORT_MEM_Q_PINLOC_36), + .PORT_MEM_Q_PINLOC_37 (PORT_MEM_Q_PINLOC_37), + .PORT_MEM_Q_PINLOC_38 (PORT_MEM_Q_PINLOC_38), + .PORT_MEM_Q_PINLOC_39 (PORT_MEM_Q_PINLOC_39), + .PORT_MEM_Q_PINLOC_40 (PORT_MEM_Q_PINLOC_40), + .PORT_MEM_Q_PINLOC_41 (PORT_MEM_Q_PINLOC_41), + .PORT_MEM_Q_PINLOC_42 (PORT_MEM_Q_PINLOC_42), + .PORT_MEM_Q_PINLOC_43 (PORT_MEM_Q_PINLOC_43), + .PORT_MEM_Q_PINLOC_44 (PORT_MEM_Q_PINLOC_44), + .PORT_MEM_Q_PINLOC_45 (PORT_MEM_Q_PINLOC_45), + .PORT_MEM_Q_PINLOC_46 (PORT_MEM_Q_PINLOC_46), + .PORT_MEM_Q_PINLOC_47 (PORT_MEM_Q_PINLOC_47), + .PORT_MEM_Q_PINLOC_48 (PORT_MEM_Q_PINLOC_48), + .PORT_MEM_Q_PINLOC_AUTOGEN_WCNT (PORT_MEM_Q_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_PINLOC_0 (PORT_MEM_DQS_PINLOC_0), + .PORT_MEM_DQS_PINLOC_1 (PORT_MEM_DQS_PINLOC_1), + .PORT_MEM_DQS_PINLOC_2 (PORT_MEM_DQS_PINLOC_2), + .PORT_MEM_DQS_PINLOC_3 (PORT_MEM_DQS_PINLOC_3), + .PORT_MEM_DQS_PINLOC_4 (PORT_MEM_DQS_PINLOC_4), + .PORT_MEM_DQS_PINLOC_5 (PORT_MEM_DQS_PINLOC_5), + .PORT_MEM_DQS_PINLOC_6 (PORT_MEM_DQS_PINLOC_6), + .PORT_MEM_DQS_PINLOC_7 (PORT_MEM_DQS_PINLOC_7), + .PORT_MEM_DQS_PINLOC_8 (PORT_MEM_DQS_PINLOC_8), + .PORT_MEM_DQS_PINLOC_9 (PORT_MEM_DQS_PINLOC_9), + .PORT_MEM_DQS_PINLOC_10 (PORT_MEM_DQS_PINLOC_10), + .PORT_MEM_DQS_PINLOC_11 (PORT_MEM_DQS_PINLOC_11), + .PORT_MEM_DQS_PINLOC_12 (PORT_MEM_DQS_PINLOC_12), + .PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_DQS_N_PINLOC_0 (PORT_MEM_DQS_N_PINLOC_0), + .PORT_MEM_DQS_N_PINLOC_1 (PORT_MEM_DQS_N_PINLOC_1), + .PORT_MEM_DQS_N_PINLOC_2 (PORT_MEM_DQS_N_PINLOC_2), + .PORT_MEM_DQS_N_PINLOC_3 (PORT_MEM_DQS_N_PINLOC_3), + .PORT_MEM_DQS_N_PINLOC_4 (PORT_MEM_DQS_N_PINLOC_4), + .PORT_MEM_DQS_N_PINLOC_5 (PORT_MEM_DQS_N_PINLOC_5), + .PORT_MEM_DQS_N_PINLOC_6 (PORT_MEM_DQS_N_PINLOC_6), + .PORT_MEM_DQS_N_PINLOC_7 (PORT_MEM_DQS_N_PINLOC_7), + .PORT_MEM_DQS_N_PINLOC_8 (PORT_MEM_DQS_N_PINLOC_8), + .PORT_MEM_DQS_N_PINLOC_9 (PORT_MEM_DQS_N_PINLOC_9), + .PORT_MEM_DQS_N_PINLOC_10 (PORT_MEM_DQS_N_PINLOC_10), + .PORT_MEM_DQS_N_PINLOC_11 (PORT_MEM_DQS_N_PINLOC_11), + .PORT_MEM_DQS_N_PINLOC_12 (PORT_MEM_DQS_N_PINLOC_12), + .PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_PINLOC_0 (PORT_MEM_QK_PINLOC_0), + .PORT_MEM_QK_PINLOC_1 (PORT_MEM_QK_PINLOC_1), + .PORT_MEM_QK_PINLOC_2 (PORT_MEM_QK_PINLOC_2), + .PORT_MEM_QK_PINLOC_3 (PORT_MEM_QK_PINLOC_3), + .PORT_MEM_QK_PINLOC_4 (PORT_MEM_QK_PINLOC_4), + .PORT_MEM_QK_PINLOC_5 (PORT_MEM_QK_PINLOC_5), + .PORT_MEM_QK_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QK_N_PINLOC_0 (PORT_MEM_QK_N_PINLOC_0), + .PORT_MEM_QK_N_PINLOC_1 (PORT_MEM_QK_N_PINLOC_1), + .PORT_MEM_QK_N_PINLOC_2 (PORT_MEM_QK_N_PINLOC_2), + .PORT_MEM_QK_N_PINLOC_3 (PORT_MEM_QK_N_PINLOC_3), + .PORT_MEM_QK_N_PINLOC_4 (PORT_MEM_QK_N_PINLOC_4), + .PORT_MEM_QK_N_PINLOC_5 (PORT_MEM_QK_N_PINLOC_5), + .PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_PINLOC_0 (PORT_MEM_QKA_PINLOC_0), + .PORT_MEM_QKA_PINLOC_1 (PORT_MEM_QKA_PINLOC_1), + .PORT_MEM_QKA_PINLOC_2 (PORT_MEM_QKA_PINLOC_2), + .PORT_MEM_QKA_PINLOC_3 (PORT_MEM_QKA_PINLOC_3), + .PORT_MEM_QKA_PINLOC_4 (PORT_MEM_QKA_PINLOC_4), + .PORT_MEM_QKA_PINLOC_5 (PORT_MEM_QKA_PINLOC_5), + .PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKA_N_PINLOC_0 (PORT_MEM_QKA_N_PINLOC_0), + .PORT_MEM_QKA_N_PINLOC_1 (PORT_MEM_QKA_N_PINLOC_1), + .PORT_MEM_QKA_N_PINLOC_2 (PORT_MEM_QKA_N_PINLOC_2), + .PORT_MEM_QKA_N_PINLOC_3 (PORT_MEM_QKA_N_PINLOC_3), + .PORT_MEM_QKA_N_PINLOC_4 (PORT_MEM_QKA_N_PINLOC_4), + .PORT_MEM_QKA_N_PINLOC_5 (PORT_MEM_QKA_N_PINLOC_5), + .PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_PINLOC_0 (PORT_MEM_QKB_PINLOC_0), + .PORT_MEM_QKB_PINLOC_1 (PORT_MEM_QKB_PINLOC_1), + .PORT_MEM_QKB_PINLOC_2 (PORT_MEM_QKB_PINLOC_2), + .PORT_MEM_QKB_PINLOC_3 (PORT_MEM_QKB_PINLOC_3), + .PORT_MEM_QKB_PINLOC_4 (PORT_MEM_QKB_PINLOC_4), + .PORT_MEM_QKB_PINLOC_5 (PORT_MEM_QKB_PINLOC_5), + .PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_QKB_N_PINLOC_0 (PORT_MEM_QKB_N_PINLOC_0), + .PORT_MEM_QKB_N_PINLOC_1 (PORT_MEM_QKB_N_PINLOC_1), + .PORT_MEM_QKB_N_PINLOC_2 (PORT_MEM_QKB_N_PINLOC_2), + .PORT_MEM_QKB_N_PINLOC_3 (PORT_MEM_QKB_N_PINLOC_3), + .PORT_MEM_QKB_N_PINLOC_4 (PORT_MEM_QKB_N_PINLOC_4), + .PORT_MEM_QKB_N_PINLOC_5 (PORT_MEM_QKB_N_PINLOC_5), + .PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_PINLOC_0 (PORT_MEM_CQ_PINLOC_0), + .PORT_MEM_CQ_PINLOC_1 (PORT_MEM_CQ_PINLOC_1), + .PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_CQ_N_PINLOC_0 (PORT_MEM_CQ_N_PINLOC_0), + .PORT_MEM_CQ_N_PINLOC_1 (PORT_MEM_CQ_N_PINLOC_1), + .PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_ALERT_N_PINLOC_0 (PORT_MEM_ALERT_N_PINLOC_0), + .PORT_MEM_ALERT_N_PINLOC_1 (PORT_MEM_ALERT_N_PINLOC_1), + .PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_PE_N_PINLOC_0 (PORT_MEM_PE_N_PINLOC_0), + .PORT_MEM_PE_N_PINLOC_1 (PORT_MEM_PE_N_PINLOC_1), + .PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT (PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH), + .PORT_HPS_EMIF_H2E_WIDTH (PORT_HPS_EMIF_H2E_WIDTH), + .PORT_HPS_EMIF_E2H_WIDTH (PORT_HPS_EMIF_E2H_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH (PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_OUT_RDATA_WIDTH (PORT_CAL_DEBUG_OUT_RDATA_WIDTH), + .PORT_CAL_DEBUG_OUT_WDATA_WIDTH (PORT_CAL_DEBUG_OUT_WDATA_WIDTH), + .PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH (PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH), + .PORT_CAL_MASTER_ADDRESS_WIDTH (PORT_CAL_MASTER_ADDRESS_WIDTH), + .PORT_CAL_MASTER_RDATA_WIDTH (PORT_CAL_MASTER_RDATA_WIDTH), + .PORT_CAL_MASTER_WDATA_WIDTH (PORT_CAL_MASTER_WDATA_WIDTH), + .PORT_CAL_MASTER_BYTEEN_WIDTH (PORT_CAL_MASTER_BYTEEN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (PORT_DFT_NF_IOAUX_PIO_IN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .PLL_PHY_CLK_VCO_PHASE (PLL_PHY_CLK_VCO_PHASE), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_REF_CLK_FREQ_PS (PLL_REF_CLK_FREQ_PS), + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (PLL_SIM_CAL_SLAVE_CLK_FREQ_PS), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (PLL_SIM_CAL_MASTER_CLK_FREQ_PS), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_BW_SEL (PLL_BW_SEL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .SEQ_SYNTH_PARAMS_HEX_FILENAME ("ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_params_synth.hex"), + .SEQ_SIM_PARAMS_HEX_FILENAME ("ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_params_sim.hex"), + .SEQ_CODE_HEX_FILENAME ("ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_cal.hex") + ) arch_inst ( + .global_reset_n (global_reset_n), + .pll_ref_clk (pll_ref_clk), + .pll_locked (pll_locked), + .pll_extra_clk_0 (pll_extra_clk_0), + .pll_extra_clk_1 (pll_extra_clk_1), + .pll_extra_clk_2 (pll_extra_clk_2), + .pll_extra_clk_3 (pll_extra_clk_3), + .oct_rzqin (oct_rzqin), + .mem_ck (mem_ck), + .mem_ck_n (mem_ck_n), + .mem_a (mem_a), + .mem_act_n (mem_act_n), + .mem_ba (mem_ba), + .mem_bg (mem_bg), + .mem_c (mem_c), + .mem_cke (mem_cke), + .mem_cs_n (mem_cs_n), + .mem_rm (mem_rm), + .mem_odt (mem_odt), + .mem_reset_n (mem_reset_n), + .mem_par (mem_par), + .mem_alert_n (mem_alert_n), + .mem_dqs (mem_dqs), + .mem_dqs_n (mem_dqs_n), + .mem_dq (mem_dq), + .mem_dbi_n (mem_dbi_n), + .mem_dk (mem_dk), + .mem_dk_n (mem_dk_n), + .mem_dka (mem_dka), + .mem_dka_n (mem_dka_n), + .mem_dkb (mem_dkb), + .mem_dkb_n (mem_dkb_n), + .mem_k (mem_k), + .mem_k_n (mem_k_n), + .mem_ras_n (mem_ras_n), + .mem_cas_n (mem_cas_n), + .mem_we_n (mem_we_n), + .mem_ca (mem_ca), + .mem_ref_n (mem_ref_n), + .mem_wps_n (mem_wps_n), + .mem_rps_n (mem_rps_n), + .mem_doff_n (mem_doff_n), + .mem_lda_n (mem_lda_n), + .mem_ldb_n (mem_ldb_n), + .mem_rwa_n (mem_rwa_n), + .mem_rwb_n (mem_rwb_n), + .mem_lbk0_n (mem_lbk0_n), + .mem_lbk1_n (mem_lbk1_n), + .mem_cfg_n (mem_cfg_n), + .mem_ap (mem_ap), + .mem_ainv (mem_ainv), + .mem_dm (mem_dm), + .mem_bws_n (mem_bws_n), + .mem_d (mem_d), + .mem_dqa (mem_dqa), + .mem_dqb (mem_dqb), + .mem_dinva (mem_dinva), + .mem_dinvb (mem_dinvb), + .mem_q (mem_q), + .mem_qk (mem_qk), + .mem_qk_n (mem_qk_n), + .mem_qka (mem_qka), + .mem_qka_n (mem_qka_n), + .mem_qkb (mem_qkb), + .mem_qkb_n (mem_qkb_n), + .mem_cq (mem_cq), + .mem_cq_n (mem_cq_n), + .mem_pe_n (mem_pe_n), + .local_cal_success (local_cal_success), + .local_cal_fail (local_cal_fail), + .vid_cal_done_persist (vid_cal_done_persist), + .afi_reset_n (afi_reset_n), + .afi_clk (afi_clk), + .afi_half_clk (afi_half_clk), + .emif_usr_reset_n (emif_usr_reset_n), + .emif_usr_clk (emif_usr_clk), + .emif_usr_half_clk (emif_usr_half_clk), + .emif_usr_reset_n_sec (emif_usr_reset_n_sec), + .emif_usr_clk_sec (emif_usr_clk_sec), + .emif_usr_half_clk_sec (emif_usr_half_clk_sec), + .cal_master_reset_n (cal_master_reset_n), + .cal_master_clk (cal_master_clk), + .cal_slave_reset_n (cal_slave_reset_n), + .cal_slave_clk (cal_slave_clk), + .cal_slave_reset_n_in (cal_slave_reset_n_in), + .cal_slave_clk_in (cal_slave_clk_in), + .cal_debug_reset_n (cal_debug_reset_n), + .cal_debug_clk (cal_debug_clk), + .cal_debug_out_reset_n (cal_debug_out_reset_n), + .cal_debug_out_clk (cal_debug_out_clk), + .clks_sharing_master_out (clks_sharing_master_out), + .clks_sharing_slave_in (clks_sharing_slave_in), + .afi_cal_success (afi_cal_success), + .afi_cal_fail (afi_cal_fail), + .afi_cal_req (afi_cal_req), + .afi_rlat (afi_rlat), + .afi_wlat (afi_wlat), + .afi_seq_busy (afi_seq_busy), + .afi_ctl_refresh_done (afi_ctl_refresh_done), + .afi_ctl_long_idle (afi_ctl_long_idle), + .afi_mps_req (afi_mps_req), + .afi_mps_ack (afi_mps_ack), + .afi_addr (afi_addr), + .afi_ba (afi_ba), + .afi_bg (afi_bg), + .afi_c (afi_c), + .afi_cke (afi_cke), + .afi_cs_n (afi_cs_n), + .afi_rm (afi_rm), + .afi_odt (afi_odt), + .afi_ras_n (afi_ras_n), + .afi_cas_n (afi_cas_n), + .afi_we_n (afi_we_n), + .afi_rst_n (afi_rst_n), + .afi_act_n (afi_act_n), + .afi_par (afi_par), + .afi_ca (afi_ca), + .afi_ref_n (afi_ref_n), + .afi_wps_n (afi_wps_n), + .afi_rps_n (afi_rps_n), + .afi_doff_n (afi_doff_n), + .afi_ld_n (afi_ld_n), + .afi_rw_n (afi_rw_n), + .afi_lbk0_n (afi_lbk0_n), + .afi_lbk1_n (afi_lbk1_n), + .afi_cfg_n (afi_cfg_n), + .afi_ap (afi_ap), + .afi_ainv (afi_ainv), + .afi_dm (afi_dm), + .afi_dm_n (afi_dm_n), + .afi_bws_n (afi_bws_n), + .afi_rdata_dbi_n (afi_rdata_dbi_n), + .afi_wdata_dbi_n (afi_wdata_dbi_n), + .afi_rdata_dinv (afi_rdata_dinv), + .afi_wdata_dinv (afi_wdata_dinv), + .afi_dqs_burst (afi_dqs_burst), + .afi_wdata_valid (afi_wdata_valid), + .afi_wdata (afi_wdata), + .afi_rdata_en_full (afi_rdata_en_full), + .afi_rdata (afi_rdata), + .afi_rdata_valid (afi_rdata_valid), + .afi_rrank (afi_rrank), + .afi_wrank (afi_wrank), + .afi_alert_n (afi_alert_n), + .afi_pe_n (afi_pe_n), + .ast_cmd_data_0 (ast_cmd_data_0), + .ast_cmd_valid_0 (ast_cmd_valid_0), + .ast_cmd_ready_0 (ast_cmd_ready_0), + .ast_cmd_data_1 (ast_cmd_data_1), + .ast_cmd_valid_1 (ast_cmd_valid_1), + .ast_cmd_ready_1 (ast_cmd_ready_1), + .ast_wr_data_0 (ast_wr_data_0), + .ast_wr_valid_0 (ast_wr_valid_0), + .ast_wr_ready_0 (ast_wr_ready_0), + .ast_wr_data_1 (ast_wr_data_1), + .ast_wr_valid_1 (ast_wr_valid_1), + .ast_wr_ready_1 (ast_wr_ready_1), + .ast_rd_data_0 (ast_rd_data_0), + .ast_rd_valid_0 (ast_rd_valid_0), + .ast_rd_ready_0 (ast_rd_ready_0), + .ast_rd_data_1 (ast_rd_data_1), + .ast_rd_valid_1 (ast_rd_valid_1), + .ast_rd_ready_1 (ast_rd_ready_1), + .amm_ready_0 (amm_ready_0), + .amm_read_0 (amm_read_0), + .amm_write_0 (amm_write_0), + .amm_address_0 (amm_address_0), + .amm_readdata_0 (amm_readdata_0), + .amm_writedata_0 (amm_writedata_0), + .amm_burstcount_0 (amm_burstcount_0), + .amm_byteenable_0 (amm_byteenable_0), + .amm_beginbursttransfer_0 (amm_beginbursttransfer_0), + .amm_readdatavalid_0 (amm_readdatavalid_0), + .amm_ready_1 (amm_ready_1), + .amm_read_1 (amm_read_1), + .amm_write_1 (amm_write_1), + .amm_address_1 (amm_address_1), + .amm_readdata_1 (amm_readdata_1), + .amm_writedata_1 (amm_writedata_1), + .amm_burstcount_1 (amm_burstcount_1), + .amm_byteenable_1 (amm_byteenable_1), + .amm_beginbursttransfer_1 (amm_beginbursttransfer_1), + .amm_readdatavalid_1 (amm_readdatavalid_1), + .ctrl_user_priority_hi_0 (ctrl_user_priority_hi_0), + .ctrl_user_priority_hi_1 (ctrl_user_priority_hi_1), + .ctrl_auto_precharge_req_0 (ctrl_auto_precharge_req_0), + .ctrl_auto_precharge_req_1 (ctrl_auto_precharge_req_1), + .ctrl_user_refresh_req (ctrl_user_refresh_req), + .ctrl_user_refresh_bank (ctrl_user_refresh_bank), + .ctrl_user_refresh_ack (ctrl_user_refresh_ack), + .ctrl_self_refresh_req (ctrl_self_refresh_req), + .ctrl_self_refresh_ack (ctrl_self_refresh_ack), + .ctrl_will_refresh (ctrl_will_refresh), + .ctrl_deep_power_down_req (ctrl_deep_power_down_req), + .ctrl_deep_power_down_ack (ctrl_deep_power_down_ack), + .ctrl_power_down_ack (ctrl_power_down_ack), + .ctrl_zq_cal_long_req (ctrl_zq_cal_long_req), + .ctrl_zq_cal_short_req (ctrl_zq_cal_short_req), + .ctrl_zq_cal_ack (ctrl_zq_cal_ack), + .ctrl_ecc_write_info_0 (ctrl_ecc_write_info_0), + .ctrl_ecc_rdata_id_0 (ctrl_ecc_rdata_id_0), + .ctrl_ecc_read_info_0 (ctrl_ecc_read_info_0), + .ctrl_ecc_cmd_info_0 (ctrl_ecc_cmd_info_0), + .ctrl_ecc_idle_0 (ctrl_ecc_idle_0), + .ctrl_ecc_wr_pointer_info_0 (ctrl_ecc_wr_pointer_info_0), + .ctrl_ecc_write_info_1 (ctrl_ecc_write_info_1), + .ctrl_ecc_rdata_id_1 (ctrl_ecc_rdata_id_1), + .ctrl_ecc_read_info_1 (ctrl_ecc_read_info_1), + .ctrl_ecc_cmd_info_1 (ctrl_ecc_cmd_info_1), + .ctrl_ecc_idle_1 (ctrl_ecc_idle_1), + .ctrl_ecc_wr_pointer_info_1 (ctrl_ecc_wr_pointer_info_1), + .mmr_slave_waitrequest_0 (mmr_slave_waitrequest_0), + .mmr_slave_read_0 (mmr_slave_read_0), + .mmr_slave_write_0 (mmr_slave_write_0), + .mmr_slave_address_0 (mmr_slave_address_0), + .mmr_slave_readdata_0 (mmr_slave_readdata_0), + .mmr_slave_writedata_0 (mmr_slave_writedata_0), + .mmr_slave_burstcount_0 (mmr_slave_burstcount_0), + .mmr_slave_beginbursttransfer_0 (mmr_slave_beginbursttransfer_0), + .mmr_slave_readdatavalid_0 (mmr_slave_readdatavalid_0), + .mmr_slave_waitrequest_1 (mmr_slave_waitrequest_1), + .mmr_slave_read_1 (mmr_slave_read_1), + .mmr_slave_write_1 (mmr_slave_write_1), + .mmr_slave_address_1 (mmr_slave_address_1), + .mmr_slave_readdata_1 (mmr_slave_readdata_1), + .mmr_slave_writedata_1 (mmr_slave_writedata_1), + .mmr_slave_burstcount_1 (mmr_slave_burstcount_1), + .mmr_slave_beginbursttransfer_1 (mmr_slave_beginbursttransfer_1), + .mmr_slave_readdatavalid_1 (mmr_slave_readdatavalid_1), + .hps_to_emif (hps_to_emif), + .emif_to_hps (emif_to_hps), + .hps_to_emif_gp (hps_to_emif_gp), + .emif_to_hps_gp (emif_to_hps_gp), + .cal_debug_waitrequest (cal_debug_waitrequest), + .cal_debug_read (cal_debug_read), + .cal_debug_write (cal_debug_write), + .cal_debug_addr (cal_debug_addr), + .cal_debug_read_data (cal_debug_read_data), + .cal_debug_write_data (cal_debug_write_data), + .cal_debug_byteenable (cal_debug_byteenable), + .cal_debug_read_data_valid (cal_debug_read_data_valid), + .cal_debug_out_waitrequest (cal_debug_out_waitrequest), + .cal_debug_out_read (cal_debug_out_read), + .cal_debug_out_write (cal_debug_out_write), + .cal_debug_out_addr (cal_debug_out_addr), + .cal_debug_out_read_data (cal_debug_out_read_data), + .cal_debug_out_write_data (cal_debug_out_write_data), + .cal_debug_out_byteenable (cal_debug_out_byteenable), + .cal_debug_out_read_data_valid (cal_debug_out_read_data_valid), + .cal_master_waitrequest (cal_master_waitrequest), + .cal_master_read (cal_master_read), + .cal_master_write (cal_master_write), + .cal_master_addr (cal_master_addr), + .cal_master_read_data (cal_master_read_data), + .cal_master_write_data (cal_master_write_data), + .cal_master_byteenable (cal_master_byteenable), + .cal_master_read_data_valid (cal_master_read_data_valid), + .cal_master_burstcount (cal_master_burstcount), + .cal_master_debugaccess (cal_master_debugaccess), + .ioaux_pio_in (ioaux_pio_in), + .ioaux_pio_out (ioaux_pio_out), + .pa_dprio_clk (pa_dprio_clk), + .pa_dprio_read (pa_dprio_read), + .pa_dprio_reg_addr (pa_dprio_reg_addr), + .pa_dprio_rst_n (pa_dprio_rst_n), + .pa_dprio_write (pa_dprio_write), + .pa_dprio_writedata (pa_dprio_writedata), + .pa_dprio_block_select (pa_dprio_block_select), + .pa_dprio_readdata (pa_dprio_readdata), + .pll_phase_en (pll_phase_en), + .pll_up_dn (pll_up_dn), + .pll_cnt_sel (pll_cnt_sel), + .pll_num_phase_shifts (pll_num_phase_shifts), + .pll_phase_done (pll_phase_done), + .dft_core_clk_buf_out (dft_core_clk_buf_out), + .dft_core_clk_locked (dft_core_clk_locked) + ); +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_io_aux.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_io_aux.sv new file mode 100644 index 000000000000..53e9c91e3c44 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_io_aux.sv @@ -0,0 +1,276 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +module ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_io_aux #( + // Device parameters + parameter SILICON_REV = "", + parameter IS_HPS = 0, + parameter SEQ_CODE_HEX_FILENAME = "", + + // Synthesis Parameters + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 800, + parameter SEQ_SYNTH_PARAMS_HEX_FILENAME = "", + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + + // Simulation Parameters + parameter SEQ_SIM_OSC_FREQ_MHZ = 800, + parameter SEQ_SIM_PARAMS_HEX_FILENAME = "", + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + + // Debug Parameters + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + + // Port widths for core debug access + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 1, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 1, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 1 +) ( + input logic global_reset_n_int, + output logic cal_bus_clk, + output logic cal_bus_avl_read, + output logic cal_bus_avl_write, + output logic [19:0] cal_bus_avl_address, + input logic [31:0] cal_bus_avl_read_data, + output logic [31:0] cal_bus_avl_write_data, + + // Toolkit/On-Chip Debug Access + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_clk, + input logic cal_debug_read, + input logic cal_debug_reset_n, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + input logic cal_slave_clk_in, + input logic cal_slave_reset_n_in, + + + // Avalon Master to core + output logic [PORT_CAL_MASTER_ADDRESS_WIDTH-1:0] cal_master_addr, + output logic [PORT_CAL_MASTER_BYTEEN_WIDTH-1:0] cal_master_byteenable, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + output logic cal_master_read, + output logic cal_master_write, + output logic [PORT_CAL_MASTER_WDATA_WIDTH-1:0] cal_master_write_data, + input logic [PORT_CAL_MASTER_RDATA_WIDTH-1:0] cal_master_read_data, + input logic cal_master_read_data_valid, + input logic cal_master_waitrequest, + + // Toolkit/On-Chip Debug connection to next interface in column + output logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_out_addr, + output logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_out_byteenable, + output logic cal_debug_out_clk, + output logic cal_debug_out_read, + output logic cal_debug_out_reset_n, + output logic cal_debug_out_write, + output logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_out_write_data, + input logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_out_read_data, + input logic cal_debug_out_read_data_valid, + input logic cal_debug_out_waitrequest, + + // Internal test and debug + input logic [PORT_DFT_NF_IOAUX_PIO_IN_WIDTH-1:0] ioaux_pio_in, + output logic [PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH-1:0] ioaux_pio_out +); + timeunit 1ns; + timeprecision 1ps; + + // Derive localparam values + // The following is evaluated for simulation + // synthesis translate_off + localparam SEQ_PARAMS_HEX_FILENAME = SEQ_SIM_PARAMS_HEX_FILENAME; + localparam SEQ_CPU_CLK_DIVIDE = SEQ_SIM_CPU_CLK_DIVIDE; + localparam SEQ_CAL_CLK_DIVIDE = SEQ_SIM_CAL_CLK_DIVIDE; + localparam SEQ_OSC_FREQ_MHZ = SEQ_SIM_OSC_FREQ_MHZ; + // synthesis translate_on + + // The following is evaluated for synthesis. + // Typically we synthesize full-calibration behavior for hardware, + // except when DIAG_SYNTH_FOR_SIM is set, which allows flows such + // as post-fit simulation to adopt RTL simulation behavior. + // synthesis read_comments_as_HDL on + // localparam SEQ_PARAMS_HEX_FILENAME = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_PARAMS_HEX_FILENAME : SEQ_SYNTH_PARAMS_HEX_FILENAME; + // localparam SEQ_CPU_CLK_DIVIDE = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_CPU_CLK_DIVIDE : SEQ_SYNTH_CPU_CLK_DIVIDE; + // localparam SEQ_CAL_CLK_DIVIDE = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_CAL_CLK_DIVIDE : SEQ_SYNTH_CAL_CLK_DIVIDE; + // localparam SEQ_OSC_FREQ_MHZ = DIAG_SYNTH_FOR_SIM ? SEQ_SIM_OSC_FREQ_MHZ : SEQ_SYNTH_OSC_FREQ_MHZ; + // synthesis read_comments_as_HDL off + + wire w_core_clk; + wire w_debug_clk; + wire [ 3: 0] w_debug_select; + wire w_mcu_en; + wire w_mode; + wire [31: 0] w_uc_read_data; + wire w_usrmode; + wire [21: 0] w_debug_out; + wire [ 8: 0] w_soft_nios_ctl_sig_bidir_out; + wire [19: 0] w_uc_address; + wire w_uc_av_bus_clk; + wire w_uc_read; + wire w_uc_write; + wire [31: 0] w_uc_write_data; + + assign cal_bus_clk = w_uc_av_bus_clk; + assign cal_bus_avl_read = w_uc_read; + assign cal_bus_avl_write = w_uc_write; + assign cal_bus_avl_write_data[31: 0] = w_uc_write_data[31: 0]; + assign cal_bus_avl_address[19: 0] = w_uc_address[19: 0]; + assign w_uc_read_data[31: 0] = cal_bus_avl_read_data[31: 0]; + assign w_core_clk = 1'b0; + + assign cal_master_debugaccess = 1'b0; + twentynm_io_aux # ( + .silicon_rev(SILICON_REV), + .sys_clk_source("int_osc_clk"), + .config_hps(IS_HPS ? "true" : "false"), + .config_io_aux_bypass("false"), + .config_power_down("false"), + .config_ram(38'h306420c0), + .config_spare(8'h00), + .nios_break_vector_word_addr(16'h8200), + .nios_exception_vector_word_addr(16'h0008), + .nios_reset_vector_word_addr(16'h0000), + .simulation_osc_freq_mhz(SEQ_OSC_FREQ_MHZ), + .sys_clk_div(SEQ_CPU_CLK_DIVIDE), + .cal_clk_div(SEQ_CAL_CLK_DIVIDE), + .nios_code_hex_file(SEQ_CODE_HEX_FILENAME), + .parameter_table_hex_file (SEQ_PARAMS_HEX_FILENAME), + .interface_id(DIAG_INTERFACE_ID), + .verbose_ioaux(DIAG_VERBOSE_IOAUX ? "true" : "false") + ) io_aux ( + .core_clk(w_core_clk), + .core_usr_reset_n(global_reset_n_int), + .debug_clk(w_debug_clk), + .debug_select(w_debug_select), + .mcu_en(w_mcu_en), + .mode(w_mode), + .soft_nios_addr(cal_debug_addr), + // synthesis translate_off + //This is needed to allow simulation of core logic driving the cal bus. + .soft_nios_burstcount(1'b1), + // synthesis translate_on + .soft_nios_byteenable(cal_debug_byteenable), + .soft_nios_clk(cal_debug_clk), + .soft_nios_read(cal_debug_read), + .soft_nios_reset_n(cal_debug_reset_n), + .soft_nios_write(cal_debug_write), + .soft_nios_write_data(cal_debug_write_data), + .soft_ram_clk(cal_slave_clk_in), + .soft_ram_reset_n(cal_slave_reset_n_in), + .soft_ram_read_data(cal_master_read_data), + .soft_ram_rdata_valid(cal_master_read_data_valid), + .soft_ram_waitrequest(cal_master_waitrequest), + .uc_read_data(w_uc_read_data), + .usrmode(w_usrmode), + .vji_cdr_to_the_hard_nios(), + .vji_ir_in_to_the_hard_nios(), + .vji_rti_to_the_hard_nios(), + .vji_sdr_to_the_hard_nios(), + .vji_tck_to_the_hard_nios(), + .vji_tdi_to_the_hard_nios(), + .vji_udr_to_the_hard_nios(), + .vji_uir_to_the_hard_nios(), + .debug_out(w_debug_out), + .soft_nios_read_data(cal_debug_read_data), + .soft_nios_read_data_valid(cal_debug_read_data_valid), + .soft_nios_waitrequest(cal_debug_waitrequest), + .soft_ram_addr(cal_master_addr), + .soft_ram_burstcount(cal_master_burstcount), + .soft_ram_byteenable(cal_master_byteenable), + .soft_ram_debugaccess(), + .soft_ram_read(cal_master_read), + .soft_ram_rst_n(), + .soft_ram_write(cal_master_write), + .soft_ram_write_data(cal_master_write_data), + .uc_address(w_uc_address), + .uc_av_bus_clk(w_uc_av_bus_clk), + .uc_read(w_uc_read), + .uc_write(w_uc_write), + .uc_write_data(w_uc_write_data), + .vji_ir_out_from_the_hard_nios(), + .vji_tdo_from_the_hard_nios(), + .soft_nios_out_addr(cal_debug_out_addr), + .soft_nios_out_burstcount(), + .soft_nios_out_byteenable(cal_debug_out_byteenable), + .soft_nios_out_clk(cal_debug_out_clk), + .soft_nios_out_read(cal_debug_out_read), + .soft_nios_out_reset_n(cal_debug_out_reset_n), + .soft_nios_out_write(cal_debug_out_write), + .soft_nios_out_write_data(cal_debug_out_write_data), + .soft_nios_out_read_data(cal_debug_out_read_data), + .soft_nios_out_read_data_valid(cal_debug_out_read_data_valid), + .soft_nios_out_waitrequest(cal_debug_out_waitrequest), + .pio_in(ioaux_pio_in), + .pio_out(ioaux_pio_out) + ); + + // Debug print + // synthesis translate_off + string debug_str = ""; + logic [31:0] chars; + always @ (posedge w_uc_av_bus_clk) begin + if (w_uc_address == 20'h1_0000 && w_uc_write) begin + chars = w_uc_write_data; + + while (chars[7:0] != 8'b0) begin + debug_str = {debug_str, string'(chars[7:0])}; + chars = chars >> 8; + end + + if ((w_uc_write_data & 32'hff) == 32'b0 || + (w_uc_write_data & 32'hff00) == 32'b0 || + (w_uc_write_data & 32'hff0000) == 32'b0 || + (w_uc_write_data & 32'hff000000) == 32'b0 ) begin + $display("%s", debug_str); + debug_str = ""; + end + end + end + // synthesis translate_on + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_cal.hex b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_cal.hex new file mode 100644 index 000000000000..916f51ac6b0f --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_seq_cal.hex @@ -0,0 +1,15362 @@ +:020000020000FC +:040000000081001467 +:040001001001483A68 +:0400020010BFF8042F +:0400030000BFFD1627 +:040004000040003484 +:040005000840081493 +:040006000800683A4C +:0400070000000000F5 +:0400080006C00034FA +:04000900DEF8001409 +:04000A0006800074F8 +:04000B00D690011476 +:04000C00008000343C +:04000D0010B00F140C +:04000E0000C00034FA +:04000F0018F31114BD +:0400100010C00326F3 +:0400110010000015C6 +:040012001080010455 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+:043856000005142035 +:043857000006086AF5 +:00000001FF diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_top.sv b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_top.sv new file mode 100644 index 000000000000..4d231e99abbc --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_top.sv @@ -0,0 +1,3382 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +/////////////////////////////////////////////////////////////////////////////// +// Top-level wrapper of 20nm hardened EMIF component. +// +/////////////////////////////////////////////////////////////////////////////// +module ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_top #( + + // Interface properties + parameter PROTOCOL_ENUM = "", + parameter MEM_FORMAT_ENUM = "", + parameter PHY_CONFIG_ENUM = "", + parameter PHY_PING_PONG_EN = 0, + parameter PHY_CORE_CLKS_SHARING_ENUM = "", + parameter PHY_HPS_ENABLE_EARLY_RELEASE = 0, + parameter IS_HPS = 0, + parameter IS_VID = 0, + parameter PHY_TARGET_IS_ES = 0, + parameter PHY_TARGET_IS_ES2 = 0, + parameter PHY_TARGET_IS_PRODUCTION = 1, + parameter SILICON_REV = "", + parameter PHY_HAS_DCC = 0, + parameter PLL_NUM_OF_EXTRA_CLKS = 0, + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter C2P_P2C_CLK_RATIO = 1, + parameter DQS_BUS_MODE_ENUM = "", + parameter MEM_BURST_LENGTH = 0, + parameter MEM_DATA_MASK_EN = 1, + parameter MEM_TTL_DATA_WIDTH = 0, + parameter MEM_TTL_NUM_OF_READ_GROUPS = 0, + parameter MEM_TTL_NUM_OF_WRITE_GROUPS = 0, + + // Core logic related properties + parameter REGISTER_AFI = 0, + + // OCT-related properties + parameter PHY_CALIBRATED_OCT = 1, + parameter PHY_AC_CALIBRATED_OCT = 1, + parameter PHY_CK_CALIBRATED_OCT = 1, + parameter PHY_DATA_CALIBRATED_OCT = 1, + parameter PHY_USERMODE_OCT = 1, + parameter PHY_PERIODIC_OCT_RECAL = 1, + + // Debug parameters + parameter DIAG_SIM_REGTEST_MODE = 0, + parameter DIAG_SYNTH_FOR_SIM = 0, + parameter DIAG_FAST_SIM = 0, + parameter DIAG_VERBOSE_IOAUX = 0, + parameter DIAG_INTERFACE_ID = 0, + parameter DIAG_CPA_OUT_1_EN = 0, + parameter DIAG_USE_CPA_LOCK = 1, + parameter DIAG_ECLIPSE_DEBUG = 0, + parameter DIAG_EXPORT_VJI = 0, + parameter DIAG_USE_ABSTRACT_PHY = 0, + parameter DIAG_ABSTRACT_PHY_WLAT = 3, + parameter DIAG_ABSTRACT_PHY_RLAT = 8, + parameter ABPHY_WRITE_PROTOCOL = 1, + + // Calibration algorithm and parameter table + parameter SEQ_CODE_HEX_FILENAME = "", + + parameter SEQ_SYNTH_OSC_FREQ_MHZ = 0, + parameter SEQ_SYNTH_PARAMS_HEX_FILENAME = "", + parameter SEQ_SYNTH_CPU_CLK_DIVIDE = 0, + parameter SEQ_SYNTH_CAL_CLK_DIVIDE = 0, + + parameter SEQ_SIM_OSC_FREQ_MHZ = 0, + parameter SEQ_SIM_PARAMS_HEX_FILENAME = "", + parameter SEQ_SIM_CPU_CLK_DIVIDE = 0, + parameter SEQ_SIM_CAL_CLK_DIVIDE = 0, + + // Family traits + parameter LANES_PER_TILE = 1, + parameter PINS_PER_LANE = 1, + parameter OCT_CONTROL_WIDTH = 1, + + // PLL parameters + parameter PLL_VCO_FREQ_MHZ_INT = 0, + parameter PLL_REF_CLK_FREQ_PS = 0, + parameter PLL_VCO_TO_MEM_CLK_FREQ_RATIO = 1, + parameter PLL_PHY_CLK_VCO_PHASE = 0, + parameter PLL_SIM_VCO_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_0_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_1_FREQ_PS = 0, + parameter PLL_SIM_PHYCLK_FB_FREQ_PS = 0, + parameter PLL_SIM_PHY_CLK_VCO_PHASE_PS = 0, + parameter PLL_SIM_CAL_SLAVE_CLK_FREQ_PS = 0, + parameter PLL_SIM_CAL_MASTER_CLK_FREQ_PS = 0, + parameter PLL_REF_CLK_FREQ_PS_STR = "", + parameter PLL_VCO_FREQ_PS_STR = "", + parameter PLL_M_CNT_HIGH = 0, + parameter PLL_M_CNT_LOW = 0, + parameter PLL_N_CNT_HIGH = 0, + parameter PLL_N_CNT_LOW = 0, + parameter PLL_M_CNT_BYPASS_EN = "", + parameter PLL_N_CNT_BYPASS_EN = "", + parameter PLL_M_CNT_EVEN_DUTY_EN = "", + parameter PLL_N_CNT_EVEN_DUTY_EN = "", + parameter PLL_FBCLK_MUX_1 = "", + parameter PLL_FBCLK_MUX_2 = "", + parameter PLL_M_CNT_IN_SRC = "", + parameter PLL_CP_SETTING = "", + parameter PLL_BW_CTRL = "", + parameter PLL_BW_SEL = "", + parameter PLL_C_CNT_HIGH_0 = 0, + parameter PLL_C_CNT_LOW_0 = 0, + parameter PLL_C_CNT_PRST_0 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_0 = 0, + parameter PLL_C_CNT_BYPASS_EN_0 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_0 = "", + parameter PLL_C_CNT_HIGH_1 = 0, + parameter PLL_C_CNT_LOW_1 = 0, + parameter PLL_C_CNT_PRST_1 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_1 = 0, + parameter PLL_C_CNT_BYPASS_EN_1 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_1 = "", + parameter PLL_C_CNT_HIGH_2 = 0, + parameter PLL_C_CNT_LOW_2 = 0, + parameter PLL_C_CNT_PRST_2 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_2 = 0, + parameter PLL_C_CNT_BYPASS_EN_2 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_2 = "", + parameter PLL_C_CNT_HIGH_3 = 0, + parameter PLL_C_CNT_LOW_3 = 0, + parameter PLL_C_CNT_PRST_3 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_3 = 0, + parameter PLL_C_CNT_BYPASS_EN_3 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_3 = "", + parameter PLL_C_CNT_HIGH_4 = 0, + parameter PLL_C_CNT_LOW_4 = 0, + parameter PLL_C_CNT_PRST_4 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_4 = 0, + parameter PLL_C_CNT_BYPASS_EN_4 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_4 = "", + parameter PLL_C_CNT_HIGH_5 = 0, + parameter PLL_C_CNT_LOW_5 = 0, + parameter PLL_C_CNT_PRST_5 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_5 = 0, + parameter PLL_C_CNT_BYPASS_EN_5 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_5 = "", + parameter PLL_C_CNT_HIGH_6 = 0, + parameter PLL_C_CNT_LOW_6 = 0, + parameter PLL_C_CNT_PRST_6 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_6 = 0, + parameter PLL_C_CNT_BYPASS_EN_6 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_6 = "", + parameter PLL_C_CNT_HIGH_7 = 0, + parameter PLL_C_CNT_LOW_7 = 0, + parameter PLL_C_CNT_PRST_7 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_7 = 0, + parameter PLL_C_CNT_BYPASS_EN_7 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_7 = "", + parameter PLL_C_CNT_HIGH_8 = 0, + parameter PLL_C_CNT_LOW_8 = 0, + parameter PLL_C_CNT_PRST_8 = 0, + parameter PLL_C_CNT_PH_MUX_PRST_8 = 0, + parameter PLL_C_CNT_BYPASS_EN_8 = "", + parameter PLL_C_CNT_EVEN_DUTY_EN_8 = "", + parameter PLL_C_CNT_FREQ_PS_STR_0 = "", + parameter PLL_C_CNT_PHASE_PS_STR_0 = "", + parameter PLL_C_CNT_DUTY_CYCLE_0 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_1 = "", + parameter PLL_C_CNT_PHASE_PS_STR_1 = "", + parameter PLL_C_CNT_DUTY_CYCLE_1 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_2 = "", + parameter PLL_C_CNT_PHASE_PS_STR_2 = "", + parameter PLL_C_CNT_DUTY_CYCLE_2 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_3 = "", + parameter PLL_C_CNT_PHASE_PS_STR_3 = "", + parameter PLL_C_CNT_DUTY_CYCLE_3 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_4 = "", + parameter PLL_C_CNT_PHASE_PS_STR_4 = "", + parameter PLL_C_CNT_DUTY_CYCLE_4 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_5 = "", + parameter PLL_C_CNT_PHASE_PS_STR_5 = "", + parameter PLL_C_CNT_DUTY_CYCLE_5 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_6 = "", + parameter PLL_C_CNT_PHASE_PS_STR_6 = "", + parameter PLL_C_CNT_DUTY_CYCLE_6 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_7 = "", + parameter PLL_C_CNT_PHASE_PS_STR_7 = "", + parameter PLL_C_CNT_DUTY_CYCLE_7 = 0, + parameter PLL_C_CNT_FREQ_PS_STR_8 = "", + parameter PLL_C_CNT_PHASE_PS_STR_8 = "", + parameter PLL_C_CNT_DUTY_CYCLE_8 = 0, + parameter PLL_C_CNT_OUT_EN_0 = "", + parameter PLL_C_CNT_OUT_EN_1 = "", + parameter PLL_C_CNT_OUT_EN_2 = "", + parameter PLL_C_CNT_OUT_EN_3 = "", + parameter PLL_C_CNT_OUT_EN_4 = "", + parameter PLL_C_CNT_OUT_EN_5 = "", + parameter PLL_C_CNT_OUT_EN_6 = "", + parameter PLL_C_CNT_OUT_EN_7 = "", + parameter PLL_C_CNT_OUT_EN_8 = "", + + // Parameters describing HMC configuration + parameter NUM_OF_HMC_PORTS = 1, + parameter HMC_AVL_PROTOCOL_ENUM = "", + parameter HMC_CTRL_DIMM_TYPE = "", + + parameter PRI_HMC_CFG_ENABLE_ECC = "", + parameter PRI_HMC_CFG_REORDER_DATA = "", + parameter PRI_HMC_CFG_REORDER_READ = "", + parameter PRI_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] PRI_HMC_CFG_STARVE_LIMIT = 0, + parameter PRI_HMC_CFG_DQS_TRACKING_EN = "", + parameter PRI_HMC_CFG_ARBITER_TYPE = "", + parameter PRI_HMC_CFG_OPEN_PAGE_EN = "", + parameter PRI_HMC_CFG_GEAR_DOWN_EN = "", + parameter PRI_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter PRI_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] PRI_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] PRI_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] PRI_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] PRI_HMC_CFG_ROW_CMD_SLOT = 0, + parameter PRI_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] PRI_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] PRI_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] PRI_HMC_CFG_TCL = 0, + parameter [ 5: 0] PRI_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] PRI_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] PRI_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] PRI_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter PRI_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter PRI_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] PRI_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter PRI_HMC_CFG_SB_CG_DISABLE = "", + parameter PRI_HMC_CFG_USER_RFSH_EN = "", + parameter PRI_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] PRI_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] PRI_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter PRI_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter PRI_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] PRI_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] PRI_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] PRI_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] PRI_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] PRI_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] PRI_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] PRI_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] PRI_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] PRI_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] PRI_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] PRI_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter SEC_HMC_CFG_ENABLE_ECC = "", + parameter SEC_HMC_CFG_REORDER_DATA = "", + parameter SEC_HMC_CFG_REORDER_READ = "", + parameter SEC_HMC_CFG_REORDER_RDATA = "", + parameter [ 5: 0] SEC_HMC_CFG_STARVE_LIMIT = 0, + parameter SEC_HMC_CFG_DQS_TRACKING_EN = "", + parameter SEC_HMC_CFG_ARBITER_TYPE = "", + parameter SEC_HMC_CFG_OPEN_PAGE_EN = "", + parameter SEC_HMC_CFG_GEAR_DOWN_EN = "", + parameter SEC_HMC_CFG_RLD3_MULTIBANK_MODE = "", + parameter SEC_HMC_CFG_PING_PONG_MODE = "", + parameter [ 1: 0] SEC_HMC_CFG_SLOT_ROTATE_EN = 0, + parameter [ 1: 0] SEC_HMC_CFG_SLOT_OFFSET = 0, + parameter [ 3: 0] SEC_HMC_CFG_COL_CMD_SLOT = 0, + parameter [ 3: 0] SEC_HMC_CFG_ROW_CMD_SLOT = 0, + parameter SEC_HMC_CFG_ENABLE_RC = "", + parameter [ 15: 0] SEC_HMC_CFG_CS_TO_CHIP_MAPPING = 0, + parameter [ 6: 0] SEC_HMC_CFG_RB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_WB_RESERVED_ENTRY = 0, + parameter [ 6: 0] SEC_HMC_CFG_TCL = 0, + parameter [ 5: 0] SEC_HMC_CFG_POWER_SAVING_EXIT_CYC = 0, + parameter [ 5: 0] SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC = 0, + parameter [ 15: 0] SEC_HMC_CFG_WRITE_ODT_CHIP = 0, + parameter [ 15: 0] SEC_HMC_CFG_READ_ODT_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_ON = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_ODT_PERIOD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_ODT_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ0 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ1 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ2 = 0, + parameter [ 15: 0] SEC_HMC_CFG_RLD3_REFRESH_SEQ3 = 0, + parameter SEC_HMC_CFG_SRF_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_ZQCAL_DISABLE = "", + parameter SEC_HMC_CFG_MPS_DQSTRK_DISABLE = "", + parameter SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN = "", + parameter SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN = "", + parameter [ 15: 0] SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID_LAST = 0, + parameter [ 7: 0] SEC_HMC_CFG_DQSTRK_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_RFSH_WARN_THRESHOLD = 0, + parameter SEC_HMC_CFG_SB_CG_DISABLE = "", + parameter SEC_HMC_CFG_USER_RFSH_EN = "", + parameter SEC_HMC_CFG_SRF_AUTOEXIT_EN = "", + parameter SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK = "", + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR3 = 0, + parameter [ 19: 0] SEC_HMC_CFG_SB_DDR4_MR4 = 0, + parameter [ 15: 0] SEC_HMC_CFG_SB_DDR4_MR5 = 0, + parameter [ 0: 0] SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR = 0, + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH = "", + parameter SEC_HMC_CFG_LOCAL_IF_CS_WIDTH = "", + parameter SEC_HMC_CFG_ADDR_ORDER = "", + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_RDWR = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK = 0, + parameter [ 5: 0] SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_RD_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_WR_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_RD_DIFF_BG = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_TO_PCH = 0, + parameter [ 5: 0] SEC_HMC_CFG_WR_AP_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PCH_ALL_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_ARF_TO_VALID = 0, + parameter [ 5: 0] SEC_HMC_CFG_PDN_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_SRF_TO_ZQ_CAL = 0, + parameter [ 12: 0] SEC_HMC_CFG_ARF_PERIOD = 0, + parameter [ 15: 0] SEC_HMC_CFG_PDN_PERIOD = 0, + parameter [ 8: 0] SEC_HMC_CFG_ZQCL_TO_VALID = 0, + parameter [ 6: 0] SEC_HMC_CFG_ZQCS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRS_TO_VALID = 0, + parameter [ 9: 0] SEC_HMC_CFG_MPS_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MRR_TO_VALID = 0, + parameter [ 4: 0] SEC_HMC_CFG_MPR_TO_VALID = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE = 0, + parameter [ 3: 0] SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS = 0, + parameter [ 2: 0] SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY = 0, + parameter [ 7: 0] SEC_HMC_CFG_MMR_CMD_TO_VALID = 0, + parameter [ 7: 0] SEC_HMC_CFG_4_ACT_TO_ACT = 0, + parameter [ 7: 0] SEC_HMC_CFG_16_ACT_TO_ACT = 0, + + parameter PREAMBLE_MODE = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter CRC_EN = "", + parameter SWAP_DQS_A_B = "", + parameter DQS_PACK_MODE = "", + parameter OCT_SIZE = 1, + parameter [6:0] DBC_WB_RESERVED_ENTRY = 4, + parameter DLL_MODE = "", + parameter DLL_CODEWORD = 0, + + // Parameters describing logical tile/lane/pin allocation in the RTL + parameter NUM_OF_RTL_TILES = 1, + parameter AC_PIN_MAP_SCHEME = "", + parameter PRI_AC_TILE_INDEX = -1, + parameter PRI_RDATA_TILE_INDEX = -1, + parameter PRI_RDATA_LANE_INDEX = -1, + parameter PRI_WDATA_TILE_INDEX = -1, + parameter PRI_WDATA_LANE_INDEX = -1, + parameter SEC_AC_TILE_INDEX = -1, + parameter SEC_RDATA_TILE_INDEX = -1, + parameter SEC_RDATA_LANE_INDEX = -1, + parameter SEC_WDATA_TILE_INDEX = -1, + parameter SEC_WDATA_LANE_INDEX = -1, + + // Definition of port widhts for "clks_sharing_master_out" interface + parameter PORT_CLKS_SHARING_MASTER_OUT_WIDTH = 1, + + // Definition of port widhts for "clks_sharing_slave_in" interface + parameter PORT_CLKS_SHARING_SLAVE_IN_WIDTH = 1, + + // Definition of port widths for "mem" interface + //AUTOGEN_BEGIN: Definition of memory port widths + parameter PORT_MEM_CK_WIDTH = 1, + parameter PORT_MEM_CK_N_WIDTH = 1, + parameter PORT_MEM_DK_WIDTH = 1, + parameter PORT_MEM_DK_N_WIDTH = 1, + parameter PORT_MEM_DKA_WIDTH = 1, + parameter PORT_MEM_DKA_N_WIDTH = 1, + parameter PORT_MEM_DKB_WIDTH = 1, + parameter PORT_MEM_DKB_N_WIDTH = 1, + parameter PORT_MEM_K_WIDTH = 1, + parameter PORT_MEM_K_N_WIDTH = 1, + parameter PORT_MEM_A_WIDTH = 1, + parameter PORT_MEM_BA_WIDTH = 1, + parameter PORT_MEM_BG_WIDTH = 1, + parameter PORT_MEM_C_WIDTH = 1, + parameter PORT_MEM_CKE_WIDTH = 1, + parameter PORT_MEM_CS_N_WIDTH = 1, + parameter PORT_MEM_RM_WIDTH = 1, + parameter PORT_MEM_ODT_WIDTH = 1, + parameter PORT_MEM_RAS_N_WIDTH = 1, + parameter PORT_MEM_CAS_N_WIDTH = 1, + parameter PORT_MEM_WE_N_WIDTH = 1, + parameter PORT_MEM_RESET_N_WIDTH = 1, + parameter PORT_MEM_ACT_N_WIDTH = 1, + parameter PORT_MEM_PAR_WIDTH = 1, + parameter PORT_MEM_CA_WIDTH = 1, + parameter PORT_MEM_REF_N_WIDTH = 1, + parameter PORT_MEM_WPS_N_WIDTH = 1, + parameter PORT_MEM_RPS_N_WIDTH = 1, + parameter PORT_MEM_DOFF_N_WIDTH = 1, + parameter PORT_MEM_LDA_N_WIDTH = 1, + parameter PORT_MEM_LDB_N_WIDTH = 1, + parameter PORT_MEM_RWA_N_WIDTH = 1, + parameter PORT_MEM_RWB_N_WIDTH = 1, + parameter PORT_MEM_LBK0_N_WIDTH = 1, + parameter PORT_MEM_LBK1_N_WIDTH = 1, + parameter PORT_MEM_CFG_N_WIDTH = 1, + parameter PORT_MEM_AP_WIDTH = 1, + parameter PORT_MEM_AINV_WIDTH = 1, + parameter PORT_MEM_DM_WIDTH = 1, + parameter PORT_MEM_BWS_N_WIDTH = 1, + parameter PORT_MEM_D_WIDTH = 1, + parameter PORT_MEM_DQ_WIDTH = 1, + parameter PORT_MEM_DBI_N_WIDTH = 1, + parameter PORT_MEM_DQA_WIDTH = 1, + parameter PORT_MEM_DQB_WIDTH = 1, + parameter PORT_MEM_DINVA_WIDTH = 1, + parameter PORT_MEM_DINVB_WIDTH = 1, + parameter PORT_MEM_Q_WIDTH = 1, + parameter PORT_MEM_DQS_WIDTH = 1, + parameter PORT_MEM_DQS_N_WIDTH = 1, + parameter PORT_MEM_QK_WIDTH = 1, + parameter PORT_MEM_QK_N_WIDTH = 1, + parameter PORT_MEM_QKA_WIDTH = 1, + parameter PORT_MEM_QKA_N_WIDTH = 1, + parameter PORT_MEM_QKB_WIDTH = 1, + parameter PORT_MEM_QKB_N_WIDTH = 1, + parameter PORT_MEM_CQ_WIDTH = 1, + parameter PORT_MEM_CQ_N_WIDTH = 1, + parameter PORT_MEM_ALERT_N_WIDTH = 1, + parameter PORT_MEM_PE_N_WIDTH = 1, + + // Definition of port widths for "afi" interface + //AUTOGEN_BEGIN: Definition of afi port widths + parameter PORT_AFI_RLAT_WIDTH = 1, + parameter PORT_AFI_WLAT_WIDTH = 1, + parameter PORT_AFI_SEQ_BUSY_WIDTH = 1, + parameter PORT_AFI_ADDR_WIDTH = 1, + parameter PORT_AFI_BA_WIDTH = 1, + parameter PORT_AFI_BG_WIDTH = 1, + parameter PORT_AFI_C_WIDTH = 1, + parameter PORT_AFI_CKE_WIDTH = 1, + parameter PORT_AFI_CS_N_WIDTH = 1, + parameter PORT_AFI_RM_WIDTH = 1, + parameter PORT_AFI_ODT_WIDTH = 1, + parameter PORT_AFI_RAS_N_WIDTH = 1, + parameter PORT_AFI_CAS_N_WIDTH = 1, + parameter PORT_AFI_WE_N_WIDTH = 1, + parameter PORT_AFI_RST_N_WIDTH = 1, + parameter PORT_AFI_ACT_N_WIDTH = 1, + parameter PORT_AFI_PAR_WIDTH = 1, + parameter PORT_AFI_CA_WIDTH = 1, + parameter PORT_AFI_REF_N_WIDTH = 1, + parameter PORT_AFI_WPS_N_WIDTH = 1, + parameter PORT_AFI_RPS_N_WIDTH = 1, + parameter PORT_AFI_DOFF_N_WIDTH = 1, + parameter PORT_AFI_LD_N_WIDTH = 1, + parameter PORT_AFI_RW_N_WIDTH = 1, + parameter PORT_AFI_LBK0_N_WIDTH = 1, + parameter PORT_AFI_LBK1_N_WIDTH = 1, + parameter PORT_AFI_CFG_N_WIDTH = 1, + parameter PORT_AFI_AP_WIDTH = 1, + parameter PORT_AFI_AINV_WIDTH = 1, + parameter PORT_AFI_DM_WIDTH = 1, + parameter PORT_AFI_DM_N_WIDTH = 1, + parameter PORT_AFI_BWS_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_WDATA_DBI_N_WIDTH = 1, + parameter PORT_AFI_RDATA_DINV_WIDTH = 1, + parameter PORT_AFI_WDATA_DINV_WIDTH = 1, + parameter PORT_AFI_DQS_BURST_WIDTH = 1, + parameter PORT_AFI_WDATA_VALID_WIDTH = 1, + parameter PORT_AFI_WDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_EN_FULL_WIDTH = 1, + parameter PORT_AFI_RDATA_WIDTH = 1, + parameter PORT_AFI_RDATA_VALID_WIDTH = 1, + parameter PORT_AFI_RRANK_WIDTH = 1, + parameter PORT_AFI_WRANK_WIDTH = 1, + parameter PORT_AFI_ALERT_N_WIDTH = 1, + parameter PORT_AFI_PE_N_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_cmd" interface + parameter PORT_CTRL_AST_CMD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_wr" interface + parameter PORT_CTRL_AST_WR_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_ast_rd" interface + parameter PORT_CTRL_AST_RD_DATA_WIDTH = 1, + + // Definition of port widths for "ctrl_amm" interface + parameter PORT_CTRL_AMM_RDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_AMM_WDATA_WIDTH = 1, + parameter PORT_CTRL_AMM_BCOUNT_WIDTH = 1, + parameter PORT_CTRL_AMM_BYTEEN_WIDTH = 1, + + // Definition of port widths for "ctrl_user_refresh" interface + parameter PORT_CTRL_USER_REFRESH_REQ_WIDTH = 1, + parameter PORT_CTRL_USER_REFRESH_BANK_WIDTH = 1, + + // Definition of port widths for "ctrl_self_refresh" interface + parameter PORT_CTRL_SELF_REFRESH_REQ_WIDTH = 1, + + // Definition of port widths for "ctrl_ecc" interface + parameter PORT_CTRL_ECC_WRITE_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_READ_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_CMD_INFO_WIDTH = 1, + parameter PORT_CTRL_ECC_WB_POINTER_WIDTH = 1, + parameter PORT_CTRL_ECC_RDATA_ID_WIDTH = 1, + + // Definition of port widths for "ctrl_mmr" interface + parameter PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_RDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_WDATA_WIDTH = 1, + parameter PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH = 1, + + // Definition of port widths for "hps_emif" interface + parameter PORT_HPS_EMIF_H2E_WIDTH = 1, + parameter PORT_HPS_EMIF_E2H_WIDTH = 1, + parameter PORT_HPS_EMIF_H2E_GP_WIDTH = 2, + parameter PORT_HPS_EMIF_E2H_GP_WIDTH = 1, + + // Definition of port widths for "cal_debug" interface + parameter PORT_CAL_DEBUG_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_WDATA_WIDTH = 1, + + // Definition of port widths for "cal_debug_out" interface + parameter PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_RDATA_WIDTH = 1, + parameter PORT_CAL_DEBUG_OUT_WDATA_WIDTH = 1, + + // Definition of port widths for "cal_master" interface + parameter PORT_CAL_MASTER_ADDRESS_WIDTH = 1, + parameter PORT_CAL_MASTER_BYTEEN_WIDTH = 1, + parameter PORT_CAL_MASTER_RDATA_WIDTH = 1, + parameter PORT_CAL_MASTER_WDATA_WIDTH = 1, + + // Definition of port widths for "dft_nf" interface + parameter PORT_DFT_NF_IOAUX_PIO_IN_WIDTH = 1, + parameter PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH = 1, + parameter PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH = 1, + parameter PORT_DFT_NF_PLL_CNTSEL_WIDTH = 1, + parameter PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH = 1, + parameter PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH = 1, + + // Definition of port widths for "vji" interface + parameter PORT_VJI_IR_IN_WIDTH = 1, + parameter PORT_VJI_IR_OUT_WIDTH = 1, + + parameter LANES_USAGE_AUTOGEN_WCNT = 0, + parameter LANES_USAGE_3 = 1'b0, + parameter LANES_USAGE_2 = 1'b0, + parameter LANES_USAGE_1 = 1'b0, + parameter LANES_USAGE_0 = 1'b0, + parameter PINS_USAGE_AUTOGEN_WCNT = 0, + parameter PINS_USAGE_12 = 1'b0, + parameter PINS_USAGE_11 = 1'b0, + parameter PINS_USAGE_10 = 1'b0, + parameter PINS_USAGE_9 = 1'b0, + parameter PINS_USAGE_8 = 1'b0, + parameter PINS_USAGE_7 = 1'b0, + parameter PINS_USAGE_6 = 1'b0, + parameter PINS_USAGE_5 = 1'b0, + parameter PINS_USAGE_4 = 1'b0, + parameter PINS_USAGE_3 = 1'b0, + parameter PINS_USAGE_2 = 1'b0, + parameter PINS_USAGE_1 = 1'b0, + parameter PINS_USAGE_0 = 1'b0, + parameter PINS_RATE_AUTOGEN_WCNT = 0, + parameter PINS_RATE_12 = 1'b0, + parameter PINS_RATE_11 = 1'b0, + parameter PINS_RATE_10 = 1'b0, + parameter PINS_RATE_9 = 1'b0, + parameter PINS_RATE_8 = 1'b0, + parameter PINS_RATE_7 = 1'b0, + parameter PINS_RATE_6 = 1'b0, + parameter PINS_RATE_5 = 1'b0, + parameter PINS_RATE_4 = 1'b0, + parameter PINS_RATE_3 = 1'b0, + parameter PINS_RATE_2 = 1'b0, + parameter PINS_RATE_1 = 1'b0, + parameter PINS_RATE_0 = 1'b0, + parameter PINS_WDB_AUTOGEN_WCNT = 0, + parameter PINS_WDB_38 = 1'b0, + parameter PINS_WDB_37 = 1'b0, + parameter PINS_WDB_36 = 1'b0, + parameter PINS_WDB_35 = 1'b0, + parameter PINS_WDB_34 = 1'b0, + parameter PINS_WDB_33 = 1'b0, + parameter PINS_WDB_32 = 1'b0, + parameter PINS_WDB_31 = 1'b0, + parameter PINS_WDB_30 = 1'b0, + parameter PINS_WDB_29 = 1'b0, + parameter PINS_WDB_28 = 1'b0, + parameter PINS_WDB_27 = 1'b0, + parameter PINS_WDB_26 = 1'b0, + parameter PINS_WDB_25 = 1'b0, + parameter PINS_WDB_24 = 1'b0, + parameter PINS_WDB_23 = 1'b0, + parameter PINS_WDB_22 = 1'b0, + parameter PINS_WDB_21 = 1'b0, + parameter PINS_WDB_20 = 1'b0, + parameter PINS_WDB_19 = 1'b0, + parameter PINS_WDB_18 = 1'b0, + parameter PINS_WDB_17 = 1'b0, + parameter PINS_WDB_16 = 1'b0, + parameter PINS_WDB_15 = 1'b0, + parameter PINS_WDB_14 = 1'b0, + parameter PINS_WDB_13 = 1'b0, + parameter PINS_WDB_12 = 1'b0, + parameter PINS_WDB_11 = 1'b0, + parameter PINS_WDB_10 = 1'b0, + parameter PINS_WDB_9 = 1'b0, + parameter PINS_WDB_8 = 1'b0, + parameter PINS_WDB_7 = 1'b0, + parameter PINS_WDB_6 = 1'b0, + parameter PINS_WDB_5 = 1'b0, + parameter PINS_WDB_4 = 1'b0, + parameter PINS_WDB_3 = 1'b0, + parameter PINS_WDB_2 = 1'b0, + parameter PINS_WDB_1 = 1'b0, + parameter PINS_WDB_0 = 1'b0, + parameter PINS_DATA_IN_MODE_AUTOGEN_WCNT = 0, + parameter PINS_DATA_IN_MODE_38 = 1'b0, + parameter PINS_DATA_IN_MODE_37 = 1'b0, + parameter PINS_DATA_IN_MODE_36 = 1'b0, + parameter PINS_DATA_IN_MODE_35 = 1'b0, + parameter PINS_DATA_IN_MODE_34 = 1'b0, + parameter PINS_DATA_IN_MODE_33 = 1'b0, + parameter PINS_DATA_IN_MODE_32 = 1'b0, + parameter PINS_DATA_IN_MODE_31 = 1'b0, + parameter PINS_DATA_IN_MODE_30 = 1'b0, + parameter PINS_DATA_IN_MODE_29 = 1'b0, + parameter PINS_DATA_IN_MODE_28 = 1'b0, + parameter PINS_DATA_IN_MODE_27 = 1'b0, + parameter PINS_DATA_IN_MODE_26 = 1'b0, + parameter PINS_DATA_IN_MODE_25 = 1'b0, + parameter PINS_DATA_IN_MODE_24 = 1'b0, + parameter PINS_DATA_IN_MODE_23 = 1'b0, + parameter PINS_DATA_IN_MODE_22 = 1'b0, + parameter PINS_DATA_IN_MODE_21 = 1'b0, + parameter PINS_DATA_IN_MODE_20 = 1'b0, + parameter PINS_DATA_IN_MODE_19 = 1'b0, + parameter PINS_DATA_IN_MODE_18 = 1'b0, + parameter PINS_DATA_IN_MODE_17 = 1'b0, + parameter PINS_DATA_IN_MODE_16 = 1'b0, + parameter PINS_DATA_IN_MODE_15 = 1'b0, + parameter PINS_DATA_IN_MODE_14 = 1'b0, + parameter PINS_DATA_IN_MODE_13 = 1'b0, + parameter PINS_DATA_IN_MODE_12 = 1'b0, + parameter PINS_DATA_IN_MODE_11 = 1'b0, + parameter PINS_DATA_IN_MODE_10 = 1'b0, + parameter PINS_DATA_IN_MODE_9 = 1'b0, + parameter PINS_DATA_IN_MODE_8 = 1'b0, + parameter PINS_DATA_IN_MODE_7 = 1'b0, + parameter PINS_DATA_IN_MODE_6 = 1'b0, + parameter PINS_DATA_IN_MODE_5 = 1'b0, + parameter PINS_DATA_IN_MODE_4 = 1'b0, + parameter PINS_DATA_IN_MODE_3 = 1'b0, + parameter PINS_DATA_IN_MODE_2 = 1'b0, + parameter PINS_DATA_IN_MODE_1 = 1'b0, + parameter PINS_DATA_IN_MODE_0 = 1'b0, + parameter PINS_C2L_DRIVEN_AUTOGEN_WCNT = 0, + parameter PINS_C2L_DRIVEN_12 = 1'b0, + parameter PINS_C2L_DRIVEN_11 = 1'b0, + parameter PINS_C2L_DRIVEN_10 = 1'b0, + parameter PINS_C2L_DRIVEN_9 = 1'b0, + parameter PINS_C2L_DRIVEN_8 = 1'b0, + parameter PINS_C2L_DRIVEN_7 = 1'b0, + parameter PINS_C2L_DRIVEN_6 = 1'b0, + parameter PINS_C2L_DRIVEN_5 = 1'b0, + parameter PINS_C2L_DRIVEN_4 = 1'b0, + parameter PINS_C2L_DRIVEN_3 = 1'b0, + parameter PINS_C2L_DRIVEN_2 = 1'b0, + parameter PINS_C2L_DRIVEN_1 = 1'b0, + parameter PINS_C2L_DRIVEN_0 = 1'b0, + parameter PINS_DB_IN_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_IN_BYPASS_12 = 1'b0, + parameter PINS_DB_IN_BYPASS_11 = 1'b0, + parameter PINS_DB_IN_BYPASS_10 = 1'b0, + parameter PINS_DB_IN_BYPASS_9 = 1'b0, + parameter PINS_DB_IN_BYPASS_8 = 1'b0, + parameter PINS_DB_IN_BYPASS_7 = 1'b0, + parameter PINS_DB_IN_BYPASS_6 = 1'b0, + parameter PINS_DB_IN_BYPASS_5 = 1'b0, + parameter PINS_DB_IN_BYPASS_4 = 1'b0, + parameter PINS_DB_IN_BYPASS_3 = 1'b0, + parameter PINS_DB_IN_BYPASS_2 = 1'b0, + parameter PINS_DB_IN_BYPASS_1 = 1'b0, + parameter PINS_DB_IN_BYPASS_0 = 1'b0, + parameter PINS_DB_OUT_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OUT_BYPASS_12 = 1'b0, + parameter PINS_DB_OUT_BYPASS_11 = 1'b0, + parameter PINS_DB_OUT_BYPASS_10 = 1'b0, + parameter PINS_DB_OUT_BYPASS_9 = 1'b0, + parameter PINS_DB_OUT_BYPASS_8 = 1'b0, + parameter PINS_DB_OUT_BYPASS_7 = 1'b0, + parameter PINS_DB_OUT_BYPASS_6 = 1'b0, + parameter PINS_DB_OUT_BYPASS_5 = 1'b0, + parameter PINS_DB_OUT_BYPASS_4 = 1'b0, + parameter PINS_DB_OUT_BYPASS_3 = 1'b0, + parameter PINS_DB_OUT_BYPASS_2 = 1'b0, + parameter PINS_DB_OUT_BYPASS_1 = 1'b0, + parameter PINS_DB_OUT_BYPASS_0 = 1'b0, + parameter PINS_DB_OE_BYPASS_AUTOGEN_WCNT = 0, + parameter PINS_DB_OE_BYPASS_12 = 1'b0, + parameter PINS_DB_OE_BYPASS_11 = 1'b0, + parameter PINS_DB_OE_BYPASS_10 = 1'b0, + parameter PINS_DB_OE_BYPASS_9 = 1'b0, + parameter PINS_DB_OE_BYPASS_8 = 1'b0, + parameter PINS_DB_OE_BYPASS_7 = 1'b0, + parameter PINS_DB_OE_BYPASS_6 = 1'b0, + parameter PINS_DB_OE_BYPASS_5 = 1'b0, + parameter PINS_DB_OE_BYPASS_4 = 1'b0, + parameter PINS_DB_OE_BYPASS_3 = 1'b0, + parameter PINS_DB_OE_BYPASS_2 = 1'b0, + parameter PINS_DB_OE_BYPASS_1 = 1'b0, + parameter PINS_DB_OE_BYPASS_0 = 1'b0, + parameter PINS_INVERT_WR_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_WR_12 = 1'b0, + parameter PINS_INVERT_WR_11 = 1'b0, + parameter PINS_INVERT_WR_10 = 1'b0, + parameter PINS_INVERT_WR_9 = 1'b0, + parameter PINS_INVERT_WR_8 = 1'b0, + parameter PINS_INVERT_WR_7 = 1'b0, + parameter PINS_INVERT_WR_6 = 1'b0, + parameter PINS_INVERT_WR_5 = 1'b0, + parameter PINS_INVERT_WR_4 = 1'b0, + parameter PINS_INVERT_WR_3 = 1'b0, + parameter PINS_INVERT_WR_2 = 1'b0, + parameter PINS_INVERT_WR_1 = 1'b0, + parameter PINS_INVERT_WR_0 = 1'b0, + parameter PINS_INVERT_OE_AUTOGEN_WCNT = 0, + parameter PINS_INVERT_OE_12 = 1'b0, + parameter PINS_INVERT_OE_11 = 1'b0, + parameter PINS_INVERT_OE_10 = 1'b0, + parameter PINS_INVERT_OE_9 = 1'b0, + parameter PINS_INVERT_OE_8 = 1'b0, + parameter PINS_INVERT_OE_7 = 1'b0, + parameter PINS_INVERT_OE_6 = 1'b0, + parameter PINS_INVERT_OE_5 = 1'b0, + parameter PINS_INVERT_OE_4 = 1'b0, + parameter PINS_INVERT_OE_3 = 1'b0, + parameter PINS_INVERT_OE_2 = 1'b0, + parameter PINS_INVERT_OE_1 = 1'b0, + parameter PINS_INVERT_OE_0 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT= 0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_12 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_11 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_10 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_9 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_8 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_7 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_6 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_5 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_4 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_3 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_2 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_1 = 1'b0, + parameter PINS_AC_HMC_DATA_OVERRIDE_ENA_0 = 1'b0, + parameter PINS_OCT_MODE_AUTOGEN_WCNT = 0, + parameter PINS_OCT_MODE_12 = 1'b0, + parameter PINS_OCT_MODE_11 = 1'b0, + parameter PINS_OCT_MODE_10 = 1'b0, + parameter PINS_OCT_MODE_9 = 1'b0, + parameter PINS_OCT_MODE_8 = 1'b0, + parameter PINS_OCT_MODE_7 = 1'b0, + parameter PINS_OCT_MODE_6 = 1'b0, + parameter PINS_OCT_MODE_5 = 1'b0, + parameter PINS_OCT_MODE_4 = 1'b0, + parameter PINS_OCT_MODE_3 = 1'b0, + parameter PINS_OCT_MODE_2 = 1'b0, + parameter PINS_OCT_MODE_1 = 1'b0, + parameter PINS_OCT_MODE_0 = 1'b0, + parameter PINS_GPIO_MODE_AUTOGEN_WCNT = 0, + parameter PINS_GPIO_MODE_12 = 1'b0, + parameter PINS_GPIO_MODE_11 = 1'b0, + parameter PINS_GPIO_MODE_10 = 1'b0, + parameter PINS_GPIO_MODE_9 = 1'b0, + parameter PINS_GPIO_MODE_8 = 1'b0, + parameter PINS_GPIO_MODE_7 = 1'b0, + parameter PINS_GPIO_MODE_6 = 1'b0, + parameter PINS_GPIO_MODE_5 = 1'b0, + parameter PINS_GPIO_MODE_4 = 1'b0, + parameter PINS_GPIO_MODE_3 = 1'b0, + parameter PINS_GPIO_MODE_2 = 1'b0, + parameter PINS_GPIO_MODE_1 = 1'b0, + parameter PINS_GPIO_MODE_0 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT = 0, + parameter UNUSED_MEM_PINS_PINLOC_128 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_127 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_126 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_125 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_124 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_123 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_122 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_121 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_120 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_119 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_118 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_117 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_116 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_115 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_114 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_113 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_112 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_111 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_110 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_109 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_108 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_107 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_106 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_105 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_104 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_103 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_102 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_101 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_100 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_99 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_98 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_97 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_96 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_95 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_94 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_93 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_92 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_91 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_90 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_89 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_88 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_87 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_86 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_85 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_84 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_83 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_82 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_81 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_80 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_79 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_78 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_77 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_76 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_75 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_74 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_73 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_72 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_71 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_70 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_69 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_68 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_67 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_66 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_65 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_64 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_63 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_62 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_61 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_60 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_59 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_58 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_57 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_56 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_55 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_54 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_53 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_52 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_51 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_50 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_49 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_48 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_47 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_46 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_45 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_44 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_43 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_42 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_41 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_40 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_39 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_38 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_37 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_36 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_35 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_34 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_33 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_32 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_31 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_30 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_29 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_28 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_27 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_26 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_25 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_24 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_23 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_22 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_21 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_20 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_19 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_18 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_17 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_16 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_15 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_14 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_13 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_12 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_11 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_10 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_9 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_8 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_7 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_6 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_5 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_4 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_3 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_2 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_1 = 1'b0, + parameter UNUSED_MEM_PINS_PINLOC_0 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT = 0, + parameter UNUSED_DQS_BUSES_LANELOC_10 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_9 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_8 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_7 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_6 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_5 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_4 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_3 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_2 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_1 = 1'b0, + parameter UNUSED_DQS_BUSES_LANELOC_0 = 1'b0, + parameter CENTER_TIDS_AUTOGEN_WCNT = 0, + parameter CENTER_TIDS_2 = 1'b0, + parameter CENTER_TIDS_1 = 1'b0, + parameter CENTER_TIDS_0 = 1'b0, + parameter HMC_TIDS_AUTOGEN_WCNT = 0, + parameter HMC_TIDS_2 = 1'b0, + parameter HMC_TIDS_1 = 1'b0, + parameter HMC_TIDS_0 = 1'b0, + parameter LANE_TIDS_AUTOGEN_WCNT = 0, + parameter LANE_TIDS_9 = 1'b0, + parameter LANE_TIDS_8 = 1'b0, + parameter LANE_TIDS_7 = 1'b0, + parameter LANE_TIDS_6 = 1'b0, + parameter LANE_TIDS_5 = 1'b0, + parameter LANE_TIDS_4 = 1'b0, + parameter LANE_TIDS_3 = 1'b0, + parameter LANE_TIDS_2 = 1'b0, + parameter LANE_TIDS_1 = 1'b0, + parameter LANE_TIDS_0 = 1'b0, + parameter PORT_MEM_CK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_PINLOC_0 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_PINLOC_0 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_PINLOC_0 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_K_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_K_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_A_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_A_PINLOC_16 = 1'b0, + parameter PORT_MEM_A_PINLOC_15 = 1'b0, + parameter PORT_MEM_A_PINLOC_14 = 1'b0, + parameter PORT_MEM_A_PINLOC_13 = 1'b0, + parameter PORT_MEM_A_PINLOC_12 = 1'b0, + parameter PORT_MEM_A_PINLOC_11 = 1'b0, + parameter PORT_MEM_A_PINLOC_10 = 1'b0, + parameter PORT_MEM_A_PINLOC_9 = 1'b0, + parameter PORT_MEM_A_PINLOC_8 = 1'b0, + parameter PORT_MEM_A_PINLOC_7 = 1'b0, + parameter PORT_MEM_A_PINLOC_6 = 1'b0, + parameter PORT_MEM_A_PINLOC_5 = 1'b0, + parameter PORT_MEM_A_PINLOC_4 = 1'b0, + parameter PORT_MEM_A_PINLOC_3 = 1'b0, + parameter PORT_MEM_A_PINLOC_2 = 1'b0, + parameter PORT_MEM_A_PINLOC_1 = 1'b0, + parameter PORT_MEM_A_PINLOC_0 = 1'b0, + parameter PORT_MEM_BA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BA_PINLOC_5 = 1'b0, + parameter PORT_MEM_BA_PINLOC_4 = 1'b0, + parameter PORT_MEM_BA_PINLOC_3 = 1'b0, + parameter PORT_MEM_BA_PINLOC_2 = 1'b0, + parameter PORT_MEM_BA_PINLOC_1 = 1'b0, + parameter PORT_MEM_BA_PINLOC_0 = 1'b0, + parameter PORT_MEM_BG_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BG_PINLOC_5 = 1'b0, + parameter PORT_MEM_BG_PINLOC_4 = 1'b0, + parameter PORT_MEM_BG_PINLOC_3 = 1'b0, + parameter PORT_MEM_BG_PINLOC_2 = 1'b0, + parameter PORT_MEM_BG_PINLOC_1 = 1'b0, + parameter PORT_MEM_BG_PINLOC_0 = 1'b0, + parameter PORT_MEM_C_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_C_PINLOC_5 = 1'b0, + parameter PORT_MEM_C_PINLOC_4 = 1'b0, + parameter PORT_MEM_C_PINLOC_3 = 1'b0, + parameter PORT_MEM_C_PINLOC_2 = 1'b0, + parameter PORT_MEM_C_PINLOC_1 = 1'b0, + parameter PORT_MEM_C_PINLOC_0 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CKE_PINLOC_5 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_4 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_3 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_2 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_1 = 1'b0, + parameter PORT_MEM_CKE_PINLOC_0 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RM_PINLOC_5 = 1'b0, + parameter PORT_MEM_RM_PINLOC_4 = 1'b0, + parameter PORT_MEM_RM_PINLOC_3 = 1'b0, + parameter PORT_MEM_RM_PINLOC_2 = 1'b0, + parameter PORT_MEM_RM_PINLOC_1 = 1'b0, + parameter PORT_MEM_RM_PINLOC_0 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ODT_PINLOC_5 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_4 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_3 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_2 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_1 = 1'b0, + parameter PORT_MEM_ODT_PINLOC_0 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CAS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CAS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_WE_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RESET_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_RESET_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ACT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ACT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PAR_PINLOC_1 = 1'b0, + parameter PORT_MEM_PAR_PINLOC_0 = 1'b0, + parameter PORT_MEM_CA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CA_PINLOC_16 = 1'b0, + parameter PORT_MEM_CA_PINLOC_15 = 1'b0, + parameter PORT_MEM_CA_PINLOC_14 = 1'b0, + parameter PORT_MEM_CA_PINLOC_13 = 1'b0, + parameter PORT_MEM_CA_PINLOC_12 = 1'b0, + parameter PORT_MEM_CA_PINLOC_11 = 1'b0, + parameter PORT_MEM_CA_PINLOC_10 = 1'b0, + parameter PORT_MEM_CA_PINLOC_9 = 1'b0, + parameter PORT_MEM_CA_PINLOC_8 = 1'b0, + parameter PORT_MEM_CA_PINLOC_7 = 1'b0, + parameter PORT_MEM_CA_PINLOC_6 = 1'b0, + parameter PORT_MEM_CA_PINLOC_5 = 1'b0, + parameter PORT_MEM_CA_PINLOC_4 = 1'b0, + parameter PORT_MEM_CA_PINLOC_3 = 1'b0, + parameter PORT_MEM_CA_PINLOC_2 = 1'b0, + parameter PORT_MEM_CA_PINLOC_1 = 1'b0, + parameter PORT_MEM_CA_PINLOC_0 = 1'b0, + parameter PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_REF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_WPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RPS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DOFF_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LDB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_RWB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK0_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_LBK1_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CFG_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_AP_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AP_PINLOC_0 = 1'b0, + parameter PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_AINV_PINLOC_0 = 1'b0, + parameter PORT_MEM_DM_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DM_PINLOC_12 = 1'b0, + parameter PORT_MEM_DM_PINLOC_11 = 1'b0, + parameter PORT_MEM_DM_PINLOC_10 = 1'b0, + parameter PORT_MEM_DM_PINLOC_9 = 1'b0, + parameter PORT_MEM_DM_PINLOC_8 = 1'b0, + parameter PORT_MEM_DM_PINLOC_7 = 1'b0, + parameter PORT_MEM_DM_PINLOC_6 = 1'b0, + parameter PORT_MEM_DM_PINLOC_5 = 1'b0, + parameter PORT_MEM_DM_PINLOC_4 = 1'b0, + parameter PORT_MEM_DM_PINLOC_3 = 1'b0, + parameter PORT_MEM_DM_PINLOC_2 = 1'b0, + parameter PORT_MEM_DM_PINLOC_1 = 1'b0, + parameter PORT_MEM_DM_PINLOC_0 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_BWS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_BWS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_D_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_D_PINLOC_48 = 1'b0, + parameter PORT_MEM_D_PINLOC_47 = 1'b0, + parameter PORT_MEM_D_PINLOC_46 = 1'b0, + parameter PORT_MEM_D_PINLOC_45 = 1'b0, + parameter PORT_MEM_D_PINLOC_44 = 1'b0, + parameter PORT_MEM_D_PINLOC_43 = 1'b0, + parameter PORT_MEM_D_PINLOC_42 = 1'b0, + parameter PORT_MEM_D_PINLOC_41 = 1'b0, + parameter PORT_MEM_D_PINLOC_40 = 1'b0, + parameter PORT_MEM_D_PINLOC_39 = 1'b0, + parameter PORT_MEM_D_PINLOC_38 = 1'b0, + parameter PORT_MEM_D_PINLOC_37 = 1'b0, + parameter PORT_MEM_D_PINLOC_36 = 1'b0, + parameter PORT_MEM_D_PINLOC_35 = 1'b0, + parameter PORT_MEM_D_PINLOC_34 = 1'b0, + parameter PORT_MEM_D_PINLOC_33 = 1'b0, + parameter PORT_MEM_D_PINLOC_32 = 1'b0, + parameter PORT_MEM_D_PINLOC_31 = 1'b0, + parameter PORT_MEM_D_PINLOC_30 = 1'b0, + parameter PORT_MEM_D_PINLOC_29 = 1'b0, + parameter PORT_MEM_D_PINLOC_28 = 1'b0, + parameter PORT_MEM_D_PINLOC_27 = 1'b0, + parameter PORT_MEM_D_PINLOC_26 = 1'b0, + parameter PORT_MEM_D_PINLOC_25 = 1'b0, + parameter PORT_MEM_D_PINLOC_24 = 1'b0, + parameter PORT_MEM_D_PINLOC_23 = 1'b0, + parameter PORT_MEM_D_PINLOC_22 = 1'b0, + parameter PORT_MEM_D_PINLOC_21 = 1'b0, + parameter PORT_MEM_D_PINLOC_20 = 1'b0, + parameter PORT_MEM_D_PINLOC_19 = 1'b0, + parameter PORT_MEM_D_PINLOC_18 = 1'b0, + parameter PORT_MEM_D_PINLOC_17 = 1'b0, + parameter PORT_MEM_D_PINLOC_16 = 1'b0, + parameter PORT_MEM_D_PINLOC_15 = 1'b0, + parameter PORT_MEM_D_PINLOC_14 = 1'b0, + parameter PORT_MEM_D_PINLOC_13 = 1'b0, + parameter PORT_MEM_D_PINLOC_12 = 1'b0, + parameter PORT_MEM_D_PINLOC_11 = 1'b0, + parameter PORT_MEM_D_PINLOC_10 = 1'b0, + parameter PORT_MEM_D_PINLOC_9 = 1'b0, + parameter PORT_MEM_D_PINLOC_8 = 1'b0, + parameter PORT_MEM_D_PINLOC_7 = 1'b0, + parameter PORT_MEM_D_PINLOC_6 = 1'b0, + parameter PORT_MEM_D_PINLOC_5 = 1'b0, + parameter PORT_MEM_D_PINLOC_4 = 1'b0, + parameter PORT_MEM_D_PINLOC_3 = 1'b0, + parameter PORT_MEM_D_PINLOC_2 = 1'b0, + parameter PORT_MEM_D_PINLOC_1 = 1'b0, + parameter PORT_MEM_D_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQ_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DBI_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DBI_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQA_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQB_PINLOC_48 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_47 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_46 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_45 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_44 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_43 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_42 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_41 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_40 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_39 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_38 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_37 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_36 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_35 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_34 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_33 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_32 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_31 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_30 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_29 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_28 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_27 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_26 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_25 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_24 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_23 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_22 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_21 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_20 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_19 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_18 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_17 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_16 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_15 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_14 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_13 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQB_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVA_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVA_PINLOC_0 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DINVB_PINLOC_2 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_1 = 1'b0, + parameter PORT_MEM_DINVB_PINLOC_0 = 1'b0, + parameter PORT_MEM_Q_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_Q_PINLOC_48 = 1'b0, + parameter PORT_MEM_Q_PINLOC_47 = 1'b0, + parameter PORT_MEM_Q_PINLOC_46 = 1'b0, + parameter PORT_MEM_Q_PINLOC_45 = 1'b0, + parameter PORT_MEM_Q_PINLOC_44 = 1'b0, + parameter PORT_MEM_Q_PINLOC_43 = 1'b0, + parameter PORT_MEM_Q_PINLOC_42 = 1'b0, + parameter PORT_MEM_Q_PINLOC_41 = 1'b0, + parameter PORT_MEM_Q_PINLOC_40 = 1'b0, + parameter PORT_MEM_Q_PINLOC_39 = 1'b0, + parameter PORT_MEM_Q_PINLOC_38 = 1'b0, + parameter PORT_MEM_Q_PINLOC_37 = 1'b0, + parameter PORT_MEM_Q_PINLOC_36 = 1'b0, + parameter PORT_MEM_Q_PINLOC_35 = 1'b0, + parameter PORT_MEM_Q_PINLOC_34 = 1'b0, + parameter PORT_MEM_Q_PINLOC_33 = 1'b0, + parameter PORT_MEM_Q_PINLOC_32 = 1'b0, + parameter PORT_MEM_Q_PINLOC_31 = 1'b0, + parameter PORT_MEM_Q_PINLOC_30 = 1'b0, + parameter PORT_MEM_Q_PINLOC_29 = 1'b0, + parameter PORT_MEM_Q_PINLOC_28 = 1'b0, + parameter PORT_MEM_Q_PINLOC_27 = 1'b0, + parameter PORT_MEM_Q_PINLOC_26 = 1'b0, + parameter PORT_MEM_Q_PINLOC_25 = 1'b0, + parameter PORT_MEM_Q_PINLOC_24 = 1'b0, + parameter PORT_MEM_Q_PINLOC_23 = 1'b0, + parameter PORT_MEM_Q_PINLOC_22 = 1'b0, + parameter PORT_MEM_Q_PINLOC_21 = 1'b0, + parameter PORT_MEM_Q_PINLOC_20 = 1'b0, + parameter PORT_MEM_Q_PINLOC_19 = 1'b0, + parameter PORT_MEM_Q_PINLOC_18 = 1'b0, + parameter PORT_MEM_Q_PINLOC_17 = 1'b0, + parameter PORT_MEM_Q_PINLOC_16 = 1'b0, + parameter PORT_MEM_Q_PINLOC_15 = 1'b0, + parameter PORT_MEM_Q_PINLOC_14 = 1'b0, + parameter PORT_MEM_Q_PINLOC_13 = 1'b0, + parameter PORT_MEM_Q_PINLOC_12 = 1'b0, + parameter PORT_MEM_Q_PINLOC_11 = 1'b0, + parameter PORT_MEM_Q_PINLOC_10 = 1'b0, + parameter PORT_MEM_Q_PINLOC_9 = 1'b0, + parameter PORT_MEM_Q_PINLOC_8 = 1'b0, + parameter PORT_MEM_Q_PINLOC_7 = 1'b0, + parameter PORT_MEM_Q_PINLOC_6 = 1'b0, + parameter PORT_MEM_Q_PINLOC_5 = 1'b0, + parameter PORT_MEM_Q_PINLOC_4 = 1'b0, + parameter PORT_MEM_Q_PINLOC_3 = 1'b0, + parameter PORT_MEM_Q_PINLOC_2 = 1'b0, + parameter PORT_MEM_Q_PINLOC_1 = 1'b0, + parameter PORT_MEM_Q_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_PINLOC_0 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_DQS_N_PINLOC_12 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_11 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_10 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_9 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_8 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_7 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_6 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_DQS_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_PINLOC_0 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QK_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QK_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKA_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKA_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_PINLOC_0 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_QKB_N_PINLOC_5 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_4 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_3 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_2 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_QKB_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_PINLOC_0 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_CQ_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_CQ_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_ALERT_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_ALERT_N_PINLOC_0 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT = 0, + parameter PORT_MEM_PE_N_PINLOC_1 = 1'b0, + parameter PORT_MEM_PE_N_PINLOC_0 = 1'b0 +) ( + // Reset + input logic global_reset_n, + + // PLL signals + input logic pll_ref_clk, + output logic pll_locked, + output logic pll_extra_clk_0, + output logic pll_extra_clk_1, + output logic pll_extra_clk_2, + output logic pll_extra_clk_3, + + // OCT signals + input logic oct_rzqin, + + // Status signals + output logic local_cal_success, + output logic local_cal_fail, + + // VID cal done signal + input logic vid_cal_done_persist, + + // User reset signal going to core (for PHY + hard controller interfaces) + output logic emif_usr_reset_n, + output logic emif_usr_reset_n_sec, + + // User clock going to core (for PHY + hard controller interfaces) + output logic emif_usr_clk, + output logic emif_usr_clk_sec, + + // A clock that runs at half the frequency of emif_usr_clk going to core + output logic emif_usr_half_clk, + output logic emif_usr_half_clk_sec, + + // AFI reset going to core + output logic afi_reset_n, + + // AFI clock going to core + output logic afi_clk, + + // A clock that runs at half the frequency of afi_clk going to core + output logic afi_half_clk, + + // Signals required to share core clocking resources between across + // compatible interfaces. An interface can be configured as a "master" + // which exports the core clocks, or a "slave" which imports the + // core clocks from a master interface. + input logic [PORT_CLKS_SHARING_SLAVE_IN_WIDTH-1:0] clks_sharing_slave_in, + output logic [PORT_CLKS_SHARING_MASTER_OUT_WIDTH-1:0] clks_sharing_master_out, + + // Ports for "mem" interface + //AUTOGEN_BEGIN: Definition of memory ports + output logic [PORT_MEM_CK_WIDTH-1:0] mem_ck, + output logic [PORT_MEM_CK_N_WIDTH-1:0] mem_ck_n, + output logic [PORT_MEM_DK_WIDTH-1:0] mem_dk, + output logic [PORT_MEM_DK_N_WIDTH-1:0] mem_dk_n, + output logic [PORT_MEM_DKA_WIDTH-1:0] mem_dka, + output logic [PORT_MEM_DKA_N_WIDTH-1:0] mem_dka_n, + output logic [PORT_MEM_DKB_WIDTH-1:0] mem_dkb, + output logic [PORT_MEM_DKB_N_WIDTH-1:0] mem_dkb_n, + output logic [PORT_MEM_K_WIDTH-1:0] mem_k, + output logic [PORT_MEM_K_N_WIDTH-1:0] mem_k_n, + output logic [PORT_MEM_A_WIDTH-1:0] mem_a, + output logic [PORT_MEM_BA_WIDTH-1:0] mem_ba, + output logic [PORT_MEM_BG_WIDTH-1:0] mem_bg, + output logic [PORT_MEM_C_WIDTH-1:0] mem_c, + output logic [PORT_MEM_CKE_WIDTH-1:0] mem_cke, + output logic [PORT_MEM_CS_N_WIDTH-1:0] mem_cs_n, + output logic [PORT_MEM_RM_WIDTH-1:0] mem_rm, + output logic [PORT_MEM_ODT_WIDTH-1:0] mem_odt, + output logic [PORT_MEM_RAS_N_WIDTH-1:0] mem_ras_n, + output logic [PORT_MEM_CAS_N_WIDTH-1:0] mem_cas_n, + output logic [PORT_MEM_WE_N_WIDTH-1:0] mem_we_n, + output logic [PORT_MEM_RESET_N_WIDTH-1:0] mem_reset_n, + output logic [PORT_MEM_ACT_N_WIDTH-1:0] mem_act_n, + output logic [PORT_MEM_PAR_WIDTH-1:0] mem_par, + output logic [PORT_MEM_CA_WIDTH-1:0] mem_ca, + output logic [PORT_MEM_REF_N_WIDTH-1:0] mem_ref_n, + output logic [PORT_MEM_WPS_N_WIDTH-1:0] mem_wps_n, + output logic [PORT_MEM_RPS_N_WIDTH-1:0] mem_rps_n, + output logic [PORT_MEM_DOFF_N_WIDTH-1:0] mem_doff_n, + output logic [PORT_MEM_LDA_N_WIDTH-1:0] mem_lda_n, + output logic [PORT_MEM_LDB_N_WIDTH-1:0] mem_ldb_n, + output logic [PORT_MEM_RWA_N_WIDTH-1:0] mem_rwa_n, + output logic [PORT_MEM_RWB_N_WIDTH-1:0] mem_rwb_n, + output logic [PORT_MEM_LBK0_N_WIDTH-1:0] mem_lbk0_n, + output logic [PORT_MEM_LBK1_N_WIDTH-1:0] mem_lbk1_n, + output logic [PORT_MEM_CFG_N_WIDTH-1:0] mem_cfg_n, + output logic [PORT_MEM_AP_WIDTH-1:0] mem_ap, + output logic [PORT_MEM_AINV_WIDTH-1:0] mem_ainv, + output logic [PORT_MEM_DM_WIDTH-1:0] mem_dm, + output logic [PORT_MEM_BWS_N_WIDTH-1:0] mem_bws_n, + output logic [PORT_MEM_D_WIDTH-1:0] mem_d, + inout tri [PORT_MEM_DQ_WIDTH-1:0] mem_dq, + inout tri [PORT_MEM_DBI_N_WIDTH-1:0] mem_dbi_n, + inout tri [PORT_MEM_DQA_WIDTH-1:0] mem_dqa, + inout tri [PORT_MEM_DQB_WIDTH-1:0] mem_dqb, + inout tri [PORT_MEM_DINVA_WIDTH-1:0] mem_dinva, + inout tri [PORT_MEM_DINVB_WIDTH-1:0] mem_dinvb, + input logic [PORT_MEM_Q_WIDTH-1:0] mem_q, + inout tri [PORT_MEM_DQS_WIDTH-1:0] mem_dqs, + inout tri [PORT_MEM_DQS_N_WIDTH-1:0] mem_dqs_n, + input logic [PORT_MEM_QK_WIDTH-1:0] mem_qk, + input logic [PORT_MEM_QK_N_WIDTH-1:0] mem_qk_n, + input logic [PORT_MEM_QKA_WIDTH-1:0] mem_qka, + input logic [PORT_MEM_QKA_N_WIDTH-1:0] mem_qka_n, + input logic [PORT_MEM_QKB_WIDTH-1:0] mem_qkb, + input logic [PORT_MEM_QKB_N_WIDTH-1:0] mem_qkb_n, + input logic [PORT_MEM_CQ_WIDTH-1:0] mem_cq, + input logic [PORT_MEM_CQ_N_WIDTH-1:0] mem_cq_n, + input logic [PORT_MEM_ALERT_N_WIDTH-1:0] mem_alert_n, + input logic [PORT_MEM_PE_N_WIDTH-1:0] mem_pe_n, + + // Ports for "afi" interface + //AUTOGEN_BEGIN: Definition of afi ports + output logic afi_cal_success, + output logic afi_cal_fail, + input logic afi_cal_req, + output logic [PORT_AFI_RLAT_WIDTH-1:0] afi_rlat, + output logic [PORT_AFI_WLAT_WIDTH-1:0] afi_wlat, + output logic [PORT_AFI_SEQ_BUSY_WIDTH-1:0] afi_seq_busy, + input logic afi_ctl_refresh_done, + input logic afi_ctl_long_idle, + input logic afi_mps_req, + output logic afi_mps_ack, + input logic [PORT_AFI_ADDR_WIDTH-1:0] afi_addr, + input logic [PORT_AFI_BA_WIDTH-1:0] afi_ba, + input logic [PORT_AFI_BG_WIDTH-1:0] afi_bg, + input logic [PORT_AFI_C_WIDTH-1:0] afi_c, + input logic [PORT_AFI_CKE_WIDTH-1:0] afi_cke, + input logic [PORT_AFI_CS_N_WIDTH-1:0] afi_cs_n, + input logic [PORT_AFI_RM_WIDTH-1:0] afi_rm, + input logic [PORT_AFI_ODT_WIDTH-1:0] afi_odt, + input logic [PORT_AFI_RAS_N_WIDTH-1:0] afi_ras_n, + input logic [PORT_AFI_CAS_N_WIDTH-1:0] afi_cas_n, + input logic [PORT_AFI_WE_N_WIDTH-1:0] afi_we_n, + input logic [PORT_AFI_RST_N_WIDTH-1:0] afi_rst_n, + input logic [PORT_AFI_ACT_N_WIDTH-1:0] afi_act_n, + input logic [PORT_AFI_PAR_WIDTH-1:0] afi_par, + input logic [PORT_AFI_CA_WIDTH-1:0] afi_ca, + input logic [PORT_AFI_REF_N_WIDTH-1:0] afi_ref_n, + input logic [PORT_AFI_WPS_N_WIDTH-1:0] afi_wps_n, + input logic [PORT_AFI_RPS_N_WIDTH-1:0] afi_rps_n, + input logic [PORT_AFI_DOFF_N_WIDTH-1:0] afi_doff_n, + input logic [PORT_AFI_LD_N_WIDTH-1:0] afi_ld_n, + input logic [PORT_AFI_RW_N_WIDTH-1:0] afi_rw_n, + input logic [PORT_AFI_LBK0_N_WIDTH-1:0] afi_lbk0_n, + input logic [PORT_AFI_LBK1_N_WIDTH-1:0] afi_lbk1_n, + input logic [PORT_AFI_CFG_N_WIDTH-1:0] afi_cfg_n, + input logic [PORT_AFI_AP_WIDTH-1:0] afi_ap, + input logic [PORT_AFI_AINV_WIDTH-1:0] afi_ainv, + input logic [PORT_AFI_DM_WIDTH-1:0] afi_dm, + input logic [PORT_AFI_DM_N_WIDTH-1:0] afi_dm_n, + input logic [PORT_AFI_BWS_N_WIDTH-1:0] afi_bws_n, + output logic [PORT_AFI_RDATA_DBI_N_WIDTH-1:0] afi_rdata_dbi_n, + input logic [PORT_AFI_WDATA_DBI_N_WIDTH-1:0] afi_wdata_dbi_n, + output logic [PORT_AFI_RDATA_DINV_WIDTH-1:0] afi_rdata_dinv, + input logic [PORT_AFI_WDATA_DINV_WIDTH-1:0] afi_wdata_dinv, + input logic [PORT_AFI_DQS_BURST_WIDTH-1:0] afi_dqs_burst, + input logic [PORT_AFI_WDATA_VALID_WIDTH-1:0] afi_wdata_valid, + input logic [PORT_AFI_WDATA_WIDTH-1:0] afi_wdata, + input logic [PORT_AFI_RDATA_EN_FULL_WIDTH-1:0] afi_rdata_en_full, + output logic [PORT_AFI_RDATA_WIDTH-1:0] afi_rdata, + output logic [PORT_AFI_RDATA_VALID_WIDTH-1:0] afi_rdata_valid, + input logic [PORT_AFI_RRANK_WIDTH-1:0] afi_rrank, + input logic [PORT_AFI_WRANK_WIDTH-1:0] afi_wrank, + output logic [PORT_AFI_ALERT_N_WIDTH-1:0] afi_alert_n, + output logic [PORT_AFI_PE_N_WIDTH-1:0] afi_pe_n, + + // Ports for "ctrl_ast_cmd" interfaces + output logic ast_cmd_ready_0, + input logic ast_cmd_valid_0, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_0, + + output logic ast_cmd_ready_1, + input logic ast_cmd_valid_1, + input logic [PORT_CTRL_AST_CMD_DATA_WIDTH-1:0] ast_cmd_data_1, + + // Ports for "ctrl_ast_wr" interfaces + output logic ast_wr_ready_0, + input logic ast_wr_valid_0, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_0, + + output logic ast_wr_ready_1, + input logic ast_wr_valid_1, + input logic [PORT_CTRL_AST_WR_DATA_WIDTH-1:0] ast_wr_data_1, + + // Ports for "ctrl_ast_rd" interfaces + input logic ast_rd_ready_0, + output logic ast_rd_valid_0, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_0, + + input logic ast_rd_ready_1, + output logic ast_rd_valid_1, + output logic [PORT_CTRL_AST_RD_DATA_WIDTH-1:0] ast_rd_data_1, + + // Ports for "ctrl_amm" interfaces + input logic amm_write_0, + input logic amm_read_0, + output logic amm_ready_0, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_0, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_0, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_0, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_0, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_0, + input logic amm_beginbursttransfer_0, + output logic amm_readdatavalid_0, + + input logic amm_write_1, + input logic amm_read_1, + output logic amm_ready_1, + output logic [PORT_CTRL_AMM_RDATA_WIDTH-1:0] amm_readdata_1, + input logic [PORT_CTRL_AMM_ADDRESS_WIDTH-1:0] amm_address_1, + input logic [PORT_CTRL_AMM_WDATA_WIDTH-1:0] amm_writedata_1, + input logic [PORT_CTRL_AMM_BCOUNT_WIDTH-1:0] amm_burstcount_1, + input logic [PORT_CTRL_AMM_BYTEEN_WIDTH-1:0] amm_byteenable_1, + input logic amm_beginbursttransfer_1, + output logic amm_readdatavalid_1, + + // Ports for "ctrl_user_priority" interface + input logic ctrl_user_priority_hi_0, + input logic ctrl_user_priority_hi_1, + + // Ports for "ctrl_auto_precharge" interface + input logic ctrl_auto_precharge_req_0, + input logic ctrl_auto_precharge_req_1, + + // Ports for "ctrl_user_refresh" interface + input logic [PORT_CTRL_USER_REFRESH_REQ_WIDTH-1:0] ctrl_user_refresh_req, + input logic [PORT_CTRL_USER_REFRESH_BANK_WIDTH-1:0] ctrl_user_refresh_bank, + output logic ctrl_user_refresh_ack, + + // Ports for "ctrl_self_refresh" interface + input logic [PORT_CTRL_SELF_REFRESH_REQ_WIDTH-1:0] ctrl_self_refresh_req, + output logic ctrl_self_refresh_ack, + + // Ports for "ctrl_will_refresh" interface + output logic ctrl_will_refresh, + + // Ports for "ctrl_deep_power_down" interface + input logic ctrl_deep_power_down_req, + output logic ctrl_deep_power_down_ack, + + // Ports for "ctrl_power_down" interface + output logic ctrl_power_down_ack, + + // Ports for "ctrl_zq_cal" interface + input logic ctrl_zq_cal_long_req, + input logic ctrl_zq_cal_short_req, + output logic ctrl_zq_cal_ack, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_0, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_0, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_0, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_0, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_0, + output logic ctrl_ecc_idle_0, + + // Ports for "ctrl_ecc" interface + input logic [PORT_CTRL_ECC_WRITE_INFO_WIDTH-1:0] ctrl_ecc_write_info_1, + output logic [PORT_CTRL_ECC_RDATA_ID_WIDTH-1:0] ctrl_ecc_rdata_id_1, + output logic [PORT_CTRL_ECC_WB_POINTER_WIDTH-1:0] ctrl_ecc_wr_pointer_info_1, + output logic [PORT_CTRL_ECC_READ_INFO_WIDTH-1:0] ctrl_ecc_read_info_1, + output logic [PORT_CTRL_ECC_CMD_INFO_WIDTH-1:0] ctrl_ecc_cmd_info_1, + output logic ctrl_ecc_idle_1, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_0, + input logic mmr_slave_read_0, + input logic mmr_slave_write_0, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_0, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_0, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_0, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_0, + input logic mmr_slave_beginbursttransfer_0, + output logic mmr_slave_readdatavalid_0, + + // Ports for "ctrl_mmr" interface + output logic mmr_slave_waitrequest_1, + input logic mmr_slave_read_1, + input logic mmr_slave_write_1, + input logic [PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH-1:0] mmr_slave_address_1, + output logic [PORT_CTRL_MMR_SLAVE_RDATA_WIDTH-1:0] mmr_slave_readdata_1, + input logic [PORT_CTRL_MMR_SLAVE_WDATA_WIDTH-1:0] mmr_slave_writedata_1, + input logic [PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH-1:0] mmr_slave_burstcount_1, + input logic mmr_slave_beginbursttransfer_1, + output logic mmr_slave_readdatavalid_1, + + // Ports for the HPS<->EMIF conduit + input logic [PORT_HPS_EMIF_H2E_WIDTH-1:0] hps_to_emif, + output logic [PORT_HPS_EMIF_E2H_WIDTH-1:0] emif_to_hps, + input logic [PORT_HPS_EMIF_H2E_GP_WIDTH-1:0] hps_to_emif_gp, + output logic [PORT_HPS_EMIF_E2H_GP_WIDTH-1:0] emif_to_hps_gp, + + // Output/input clock/reset intended for core slave logic that interacts with the sequencer CPU + output logic cal_slave_clk, + output logic cal_slave_reset_n, + input logic cal_slave_clk_in, + input logic cal_slave_reset_n_in, + + // Output clock/reset intended for core master logic that interacts with the sequencer CPU + output logic cal_master_clk, + output logic cal_master_reset_n, + + // Input clock/reset intended for core logic connected to the Avalon slave port of the sequencer CPU. + // The "out" clock/reset is intended for daisy-chaining logic from multiple interfaces. + input logic cal_debug_clk, + input logic cal_debug_reset_n, + output logic cal_debug_out_clk, + output logic cal_debug_out_reset_n, + + // Ports for "cal_debug" interface + input logic [PORT_CAL_DEBUG_ADDRESS_WIDTH-1:0] cal_debug_addr, + input logic [PORT_CAL_DEBUG_BYTEEN_WIDTH-1:0] cal_debug_byteenable, + input logic cal_debug_read, + input logic cal_debug_write, + input logic [PORT_CAL_DEBUG_WDATA_WIDTH-1:0] cal_debug_write_data, + output logic [PORT_CAL_DEBUG_RDATA_WIDTH-1:0] cal_debug_read_data, + output logic cal_debug_read_data_valid, + output logic cal_debug_waitrequest, + + // Ports for "cal_debug_out" interface + output logic [PORT_CAL_DEBUG_OUT_ADDRESS_WIDTH-1:0] cal_debug_out_addr, + output logic [PORT_CAL_DEBUG_OUT_BYTEEN_WIDTH-1:0] cal_debug_out_byteenable, + output logic cal_debug_out_read, + output logic cal_debug_out_write, + output logic [PORT_CAL_DEBUG_OUT_WDATA_WIDTH-1:0] cal_debug_out_write_data, + input logic [PORT_CAL_DEBUG_OUT_RDATA_WIDTH-1:0] cal_debug_out_read_data, + input logic cal_debug_out_read_data_valid, + input logic cal_debug_out_waitrequest, + + // Ports for "cal_master" interface + output logic [PORT_CAL_MASTER_ADDRESS_WIDTH-1:0] cal_master_addr, + output logic [PORT_CAL_MASTER_BYTEEN_WIDTH-1:0] cal_master_byteenable, + output logic cal_master_burstcount, + output logic cal_master_debugaccess, + output logic cal_master_read, + output logic cal_master_write, + output logic [PORT_CAL_MASTER_WDATA_WIDTH-1:0] cal_master_write_data, + input logic [PORT_CAL_MASTER_RDATA_WIDTH-1:0] cal_master_read_data, + input logic cal_master_read_data_valid, + input logic cal_master_waitrequest, + + // Ports for internal test and debug + input logic [PORT_DFT_NF_IOAUX_PIO_IN_WIDTH-1:0] ioaux_pio_in, + output logic [PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH-1:0] ioaux_pio_out, + input logic pa_dprio_clk, + input logic pa_dprio_read, + input logic [PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH-1:0] pa_dprio_reg_addr, + input logic pa_dprio_rst_n, + input logic pa_dprio_write, + input logic [PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH-1:0] pa_dprio_writedata, + output logic pa_dprio_block_select, + output logic [PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH-1:0] pa_dprio_readdata, + input logic pll_phase_en, + input logic pll_up_dn, + input logic [PORT_DFT_NF_PLL_CNTSEL_WIDTH-1:0] pll_cnt_sel, + input logic [PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH-1:0] pll_num_phase_shifts, + output logic pll_phase_done, + output logic [PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH-1:0] dft_core_clk_buf_out, + output logic [PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH-1:0] dft_core_clk_locked +); + timeunit 1ns; + timeprecision 1ps; + + // Below is used to override the user selection for ABSTRACT PHY for synthesis + // synthesis read_comments_as_HDL on + // `define DISABLE_ABSTRACT_PHY_FOR_SYNTH TRUE + // synthesis read_comments_as_HDL off + + `ifdef DISABLE_ABSTRACT_PHY_FOR_SYNTH + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = 0; + `else + localparam DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD = DIAG_USE_ABSTRACT_PHY; + `endif + + // Assertions + initial begin + assert(LANES_USAGE_AUTOGEN_WCNT == 4) else $fatal("LANES_USAGE_AUTOGEN_WCNT != 4 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_USAGE_AUTOGEN_WCNT == 13) else $fatal("PINS_USAGE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_RATE_AUTOGEN_WCNT == 13) else $fatal("PINS_RATE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_WDB_AUTOGEN_WCNT == 39) else $fatal("PINS_WDB_AUTOGEN_WCNT != 39 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DATA_IN_MODE_AUTOGEN_WCNT == 39) else $fatal("PINS_DATA_IN_MODE_AUTOGEN_WCNT != 39 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_C2L_DRIVEN_AUTOGEN_WCNT == 13) else $fatal("PINS_C2L_DRIVEN_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_IN_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_IN_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_OUT_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_OUT_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_DB_OE_BYPASS_AUTOGEN_WCNT == 13) else $fatal("PINS_DB_OE_BYPASS_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_INVERT_WR_AUTOGEN_WCNT == 13) else $fatal("PINS_INVERT_WR_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_INVERT_OE_AUTOGEN_WCNT == 13) else $fatal("PINS_INVERT_OE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT == 13) else $fatal("PINS_AC_HMC_DATA_OVERRIDE_ENA_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_OCT_MODE_AUTOGEN_WCNT == 13) else $fatal("PINS_OCT_MODE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PINS_GPIO_MODE_AUTOGEN_WCNT == 13) else $fatal("PINS_GPIO_MODE_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT == 129) else $fatal("UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT != 129 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT == 11) else $fatal("UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT != 11 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(CENTER_TIDS_AUTOGEN_WCNT == 3) else $fatal("CENTER_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(HMC_TIDS_AUTOGEN_WCNT == 3) else $fatal("HMC_TIDS_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(LANE_TIDS_AUTOGEN_WCNT == 10) else $fatal("LANE_TIDS_AUTOGEN_WCNT != 10 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_K_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_A_PINLOC_AUTOGEN_WCNT == 17) else $fatal("PORT_MEM_A_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_BA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BG_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_BG_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_C_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_C_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RM_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_RM_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CA_PINLOC_AUTOGEN_WCNT == 17) else $fatal("PORT_MEM_CA_PINLOC_AUTOGEN_WCNT != 17 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AP_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_AP_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT == 1) else $fatal("PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT != 1 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DM_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DM_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_D_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_D_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT == 7) else $fatal("PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT != 7 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT == 3) else $fatal("PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT != 3 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_Q_PINLOC_AUTOGEN_WCNT == 49) else $fatal("PORT_MEM_Q_PINLOC_AUTOGEN_WCNT != 49 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT == 13) else $fatal("PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT != 13 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QK_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT == 6) else $fatal("PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT != 6 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + assert(PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT == 2) else $fatal("PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT != 2 - Parameter definitions in RTL and Tcl generation code are out of sync!"); + end + + // Derive localparam values + //AUTOGEN_BEGIN: Derive bit-vector parameters + localparam LANES_USAGE = {LANES_USAGE_3[29:0],LANES_USAGE_2[29:0],LANES_USAGE_1[29:0],LANES_USAGE_0[29:0]}; + localparam PINS_USAGE = {PINS_USAGE_12[29:0],PINS_USAGE_11[29:0],PINS_USAGE_10[29:0],PINS_USAGE_9[29:0],PINS_USAGE_8[29:0],PINS_USAGE_7[29:0],PINS_USAGE_6[29:0],PINS_USAGE_5[29:0],PINS_USAGE_4[29:0],PINS_USAGE_3[29:0],PINS_USAGE_2[29:0],PINS_USAGE_1[29:0],PINS_USAGE_0[29:0]}; + localparam PINS_RATE = {PINS_RATE_12[29:0],PINS_RATE_11[29:0],PINS_RATE_10[29:0],PINS_RATE_9[29:0],PINS_RATE_8[29:0],PINS_RATE_7[29:0],PINS_RATE_6[29:0],PINS_RATE_5[29:0],PINS_RATE_4[29:0],PINS_RATE_3[29:0],PINS_RATE_2[29:0],PINS_RATE_1[29:0],PINS_RATE_0[29:0]}; + localparam PINS_WDB = {PINS_WDB_38[29:0],PINS_WDB_37[29:0],PINS_WDB_36[29:0],PINS_WDB_35[29:0],PINS_WDB_34[29:0],PINS_WDB_33[29:0],PINS_WDB_32[29:0],PINS_WDB_31[29:0],PINS_WDB_30[29:0],PINS_WDB_29[29:0],PINS_WDB_28[29:0],PINS_WDB_27[29:0],PINS_WDB_26[29:0],PINS_WDB_25[29:0],PINS_WDB_24[29:0],PINS_WDB_23[29:0],PINS_WDB_22[29:0],PINS_WDB_21[29:0],PINS_WDB_20[29:0],PINS_WDB_19[29:0],PINS_WDB_18[29:0],PINS_WDB_17[29:0],PINS_WDB_16[29:0],PINS_WDB_15[29:0],PINS_WDB_14[29:0],PINS_WDB_13[29:0],PINS_WDB_12[29:0],PINS_WDB_11[29:0],PINS_WDB_10[29:0],PINS_WDB_9[29:0],PINS_WDB_8[29:0],PINS_WDB_7[29:0],PINS_WDB_6[29:0],PINS_WDB_5[29:0],PINS_WDB_4[29:0],PINS_WDB_3[29:0],PINS_WDB_2[29:0],PINS_WDB_1[29:0],PINS_WDB_0[29:0]}; + localparam PINS_DATA_IN_MODE = {PINS_DATA_IN_MODE_38[29:0],PINS_DATA_IN_MODE_37[29:0],PINS_DATA_IN_MODE_36[29:0],PINS_DATA_IN_MODE_35[29:0],PINS_DATA_IN_MODE_34[29:0],PINS_DATA_IN_MODE_33[29:0],PINS_DATA_IN_MODE_32[29:0],PINS_DATA_IN_MODE_31[29:0],PINS_DATA_IN_MODE_30[29:0],PINS_DATA_IN_MODE_29[29:0],PINS_DATA_IN_MODE_28[29:0],PINS_DATA_IN_MODE_27[29:0],PINS_DATA_IN_MODE_26[29:0],PINS_DATA_IN_MODE_25[29:0],PINS_DATA_IN_MODE_24[29:0],PINS_DATA_IN_MODE_23[29:0],PINS_DATA_IN_MODE_22[29:0],PINS_DATA_IN_MODE_21[29:0],PINS_DATA_IN_MODE_20[29:0],PINS_DATA_IN_MODE_19[29:0],PINS_DATA_IN_MODE_18[29:0],PINS_DATA_IN_MODE_17[29:0],PINS_DATA_IN_MODE_16[29:0],PINS_DATA_IN_MODE_15[29:0],PINS_DATA_IN_MODE_14[29:0],PINS_DATA_IN_MODE_13[29:0],PINS_DATA_IN_MODE_12[29:0],PINS_DATA_IN_MODE_11[29:0],PINS_DATA_IN_MODE_10[29:0],PINS_DATA_IN_MODE_9[29:0],PINS_DATA_IN_MODE_8[29:0],PINS_DATA_IN_MODE_7[29:0],PINS_DATA_IN_MODE_6[29:0],PINS_DATA_IN_MODE_5[29:0],PINS_DATA_IN_MODE_4[29:0],PINS_DATA_IN_MODE_3[29:0],PINS_DATA_IN_MODE_2[29:0],PINS_DATA_IN_MODE_1[29:0],PINS_DATA_IN_MODE_0[29:0]}; + localparam PINS_C2L_DRIVEN = {PINS_C2L_DRIVEN_12[29:0],PINS_C2L_DRIVEN_11[29:0],PINS_C2L_DRIVEN_10[29:0],PINS_C2L_DRIVEN_9[29:0],PINS_C2L_DRIVEN_8[29:0],PINS_C2L_DRIVEN_7[29:0],PINS_C2L_DRIVEN_6[29:0],PINS_C2L_DRIVEN_5[29:0],PINS_C2L_DRIVEN_4[29:0],PINS_C2L_DRIVEN_3[29:0],PINS_C2L_DRIVEN_2[29:0],PINS_C2L_DRIVEN_1[29:0],PINS_C2L_DRIVEN_0[29:0]}; + localparam PINS_DB_IN_BYPASS = {PINS_DB_IN_BYPASS_12[29:0],PINS_DB_IN_BYPASS_11[29:0],PINS_DB_IN_BYPASS_10[29:0],PINS_DB_IN_BYPASS_9[29:0],PINS_DB_IN_BYPASS_8[29:0],PINS_DB_IN_BYPASS_7[29:0],PINS_DB_IN_BYPASS_6[29:0],PINS_DB_IN_BYPASS_5[29:0],PINS_DB_IN_BYPASS_4[29:0],PINS_DB_IN_BYPASS_3[29:0],PINS_DB_IN_BYPASS_2[29:0],PINS_DB_IN_BYPASS_1[29:0],PINS_DB_IN_BYPASS_0[29:0]}; + localparam PINS_DB_OUT_BYPASS = {PINS_DB_OUT_BYPASS_12[29:0],PINS_DB_OUT_BYPASS_11[29:0],PINS_DB_OUT_BYPASS_10[29:0],PINS_DB_OUT_BYPASS_9[29:0],PINS_DB_OUT_BYPASS_8[29:0],PINS_DB_OUT_BYPASS_7[29:0],PINS_DB_OUT_BYPASS_6[29:0],PINS_DB_OUT_BYPASS_5[29:0],PINS_DB_OUT_BYPASS_4[29:0],PINS_DB_OUT_BYPASS_3[29:0],PINS_DB_OUT_BYPASS_2[29:0],PINS_DB_OUT_BYPASS_1[29:0],PINS_DB_OUT_BYPASS_0[29:0]}; + localparam PINS_DB_OE_BYPASS = {PINS_DB_OE_BYPASS_12[29:0],PINS_DB_OE_BYPASS_11[29:0],PINS_DB_OE_BYPASS_10[29:0],PINS_DB_OE_BYPASS_9[29:0],PINS_DB_OE_BYPASS_8[29:0],PINS_DB_OE_BYPASS_7[29:0],PINS_DB_OE_BYPASS_6[29:0],PINS_DB_OE_BYPASS_5[29:0],PINS_DB_OE_BYPASS_4[29:0],PINS_DB_OE_BYPASS_3[29:0],PINS_DB_OE_BYPASS_2[29:0],PINS_DB_OE_BYPASS_1[29:0],PINS_DB_OE_BYPASS_0[29:0]}; + localparam PINS_INVERT_WR = {PINS_INVERT_WR_12[29:0],PINS_INVERT_WR_11[29:0],PINS_INVERT_WR_10[29:0],PINS_INVERT_WR_9[29:0],PINS_INVERT_WR_8[29:0],PINS_INVERT_WR_7[29:0],PINS_INVERT_WR_6[29:0],PINS_INVERT_WR_5[29:0],PINS_INVERT_WR_4[29:0],PINS_INVERT_WR_3[29:0],PINS_INVERT_WR_2[29:0],PINS_INVERT_WR_1[29:0],PINS_INVERT_WR_0[29:0]}; + localparam PINS_INVERT_OE = {PINS_INVERT_OE_12[29:0],PINS_INVERT_OE_11[29:0],PINS_INVERT_OE_10[29:0],PINS_INVERT_OE_9[29:0],PINS_INVERT_OE_8[29:0],PINS_INVERT_OE_7[29:0],PINS_INVERT_OE_6[29:0],PINS_INVERT_OE_5[29:0],PINS_INVERT_OE_4[29:0],PINS_INVERT_OE_3[29:0],PINS_INVERT_OE_2[29:0],PINS_INVERT_OE_1[29:0],PINS_INVERT_OE_0[29:0]}; + localparam PINS_AC_HMC_DATA_OVERRIDE_ENA = {PINS_AC_HMC_DATA_OVERRIDE_ENA_12[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_11[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_10[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_9[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_8[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_7[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_6[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_5[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_4[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_3[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_2[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_1[29:0],PINS_AC_HMC_DATA_OVERRIDE_ENA_0[29:0]}; + localparam PINS_OCT_MODE = {PINS_OCT_MODE_12[29:0],PINS_OCT_MODE_11[29:0],PINS_OCT_MODE_10[29:0],PINS_OCT_MODE_9[29:0],PINS_OCT_MODE_8[29:0],PINS_OCT_MODE_7[29:0],PINS_OCT_MODE_6[29:0],PINS_OCT_MODE_5[29:0],PINS_OCT_MODE_4[29:0],PINS_OCT_MODE_3[29:0],PINS_OCT_MODE_2[29:0],PINS_OCT_MODE_1[29:0],PINS_OCT_MODE_0[29:0]}; + localparam PINS_GPIO_MODE = {PINS_GPIO_MODE_12[29:0],PINS_GPIO_MODE_11[29:0],PINS_GPIO_MODE_10[29:0],PINS_GPIO_MODE_9[29:0],PINS_GPIO_MODE_8[29:0],PINS_GPIO_MODE_7[29:0],PINS_GPIO_MODE_6[29:0],PINS_GPIO_MODE_5[29:0],PINS_GPIO_MODE_4[29:0],PINS_GPIO_MODE_3[29:0],PINS_GPIO_MODE_2[29:0],PINS_GPIO_MODE_1[29:0],PINS_GPIO_MODE_0[29:0]}; + localparam UNUSED_MEM_PINS_PINLOC = {UNUSED_MEM_PINS_PINLOC_128[29:0],UNUSED_MEM_PINS_PINLOC_127[29:0],UNUSED_MEM_PINS_PINLOC_126[29:0],UNUSED_MEM_PINS_PINLOC_125[29:0],UNUSED_MEM_PINS_PINLOC_124[29:0],UNUSED_MEM_PINS_PINLOC_123[29:0],UNUSED_MEM_PINS_PINLOC_122[29:0],UNUSED_MEM_PINS_PINLOC_121[29:0],UNUSED_MEM_PINS_PINLOC_120[29:0],UNUSED_MEM_PINS_PINLOC_119[29:0],UNUSED_MEM_PINS_PINLOC_118[29:0],UNUSED_MEM_PINS_PINLOC_117[29:0],UNUSED_MEM_PINS_PINLOC_116[29:0],UNUSED_MEM_PINS_PINLOC_115[29:0],UNUSED_MEM_PINS_PINLOC_114[29:0],UNUSED_MEM_PINS_PINLOC_113[29:0],UNUSED_MEM_PINS_PINLOC_112[29:0],UNUSED_MEM_PINS_PINLOC_111[29:0],UNUSED_MEM_PINS_PINLOC_110[29:0],UNUSED_MEM_PINS_PINLOC_109[29:0],UNUSED_MEM_PINS_PINLOC_108[29:0],UNUSED_MEM_PINS_PINLOC_107[29:0],UNUSED_MEM_PINS_PINLOC_106[29:0],UNUSED_MEM_PINS_PINLOC_105[29:0],UNUSED_MEM_PINS_PINLOC_104[29:0],UNUSED_MEM_PINS_PINLOC_103[29:0],UNUSED_MEM_PINS_PINLOC_102[29:0],UNUSED_MEM_PINS_PINLOC_101[29:0],UNUSED_MEM_PINS_PINLOC_100[29:0],UNUSED_MEM_PINS_PINLOC_99[29:0],UNUSED_MEM_PINS_PINLOC_98[29:0],UNUSED_MEM_PINS_PINLOC_97[29:0],UNUSED_MEM_PINS_PINLOC_96[29:0],UNUSED_MEM_PINS_PINLOC_95[29:0],UNUSED_MEM_PINS_PINLOC_94[29:0],UNUSED_MEM_PINS_PINLOC_93[29:0],UNUSED_MEM_PINS_PINLOC_92[29:0],UNUSED_MEM_PINS_PINLOC_91[29:0],UNUSED_MEM_PINS_PINLOC_90[29:0],UNUSED_MEM_PINS_PINLOC_89[29:0],UNUSED_MEM_PINS_PINLOC_88[29:0],UNUSED_MEM_PINS_PINLOC_87[29:0],UNUSED_MEM_PINS_PINLOC_86[29:0],UNUSED_MEM_PINS_PINLOC_85[29:0],UNUSED_MEM_PINS_PINLOC_84[29:0],UNUSED_MEM_PINS_PINLOC_83[29:0],UNUSED_MEM_PINS_PINLOC_82[29:0],UNUSED_MEM_PINS_PINLOC_81[29:0],UNUSED_MEM_PINS_PINLOC_80[29:0],UNUSED_MEM_PINS_PINLOC_79[29:0],UNUSED_MEM_PINS_PINLOC_78[29:0],UNUSED_MEM_PINS_PINLOC_77[29:0],UNUSED_MEM_PINS_PINLOC_76[29:0],UNUSED_MEM_PINS_PINLOC_75[29:0],UNUSED_MEM_PINS_PINLOC_74[29:0],UNUSED_MEM_PINS_PINLOC_73[29:0],UNUSED_MEM_PINS_PINLOC_72[29:0],UNUSED_MEM_PINS_PINLOC_71[29:0],UNUSED_MEM_PINS_PINLOC_70[29:0],UNUSED_MEM_PINS_PINLOC_69[29:0],UNUSED_MEM_PINS_PINLOC_68[29:0],UNUSED_MEM_PINS_PINLOC_67[29:0],UNUSED_MEM_PINS_PINLOC_66[29:0],UNUSED_MEM_PINS_PINLOC_65[29:0],UNUSED_MEM_PINS_PINLOC_64[29:0],UNUSED_MEM_PINS_PINLOC_63[29:0],UNUSED_MEM_PINS_PINLOC_62[29:0],UNUSED_MEM_PINS_PINLOC_61[29:0],UNUSED_MEM_PINS_PINLOC_60[29:0],UNUSED_MEM_PINS_PINLOC_59[29:0],UNUSED_MEM_PINS_PINLOC_58[29:0],UNUSED_MEM_PINS_PINLOC_57[29:0],UNUSED_MEM_PINS_PINLOC_56[29:0],UNUSED_MEM_PINS_PINLOC_55[29:0],UNUSED_MEM_PINS_PINLOC_54[29:0],UNUSED_MEM_PINS_PINLOC_53[29:0],UNUSED_MEM_PINS_PINLOC_52[29:0],UNUSED_MEM_PINS_PINLOC_51[29:0],UNUSED_MEM_PINS_PINLOC_50[29:0],UNUSED_MEM_PINS_PINLOC_49[29:0],UNUSED_MEM_PINS_PINLOC_48[29:0],UNUSED_MEM_PINS_PINLOC_47[29:0],UNUSED_MEM_PINS_PINLOC_46[29:0],UNUSED_MEM_PINS_PINLOC_45[29:0],UNUSED_MEM_PINS_PINLOC_44[29:0],UNUSED_MEM_PINS_PINLOC_43[29:0],UNUSED_MEM_PINS_PINLOC_42[29:0],UNUSED_MEM_PINS_PINLOC_41[29:0],UNUSED_MEM_PINS_PINLOC_40[29:0],UNUSED_MEM_PINS_PINLOC_39[29:0],UNUSED_MEM_PINS_PINLOC_38[29:0],UNUSED_MEM_PINS_PINLOC_37[29:0],UNUSED_MEM_PINS_PINLOC_36[29:0],UNUSED_MEM_PINS_PINLOC_35[29:0],UNUSED_MEM_PINS_PINLOC_34[29:0],UNUSED_MEM_PINS_PINLOC_33[29:0],UNUSED_MEM_PINS_PINLOC_32[29:0],UNUSED_MEM_PINS_PINLOC_31[29:0],UNUSED_MEM_PINS_PINLOC_30[29:0],UNUSED_MEM_PINS_PINLOC_29[29:0],UNUSED_MEM_PINS_PINLOC_28[29:0],UNUSED_MEM_PINS_PINLOC_27[29:0],UNUSED_MEM_PINS_PINLOC_26[29:0],UNUSED_MEM_PINS_PINLOC_25[29:0],UNUSED_MEM_PINS_PINLOC_24[29:0],UNUSED_MEM_PINS_PINLOC_23[29:0],UNUSED_MEM_PINS_PINLOC_22[29:0],UNUSED_MEM_PINS_PINLOC_21[29:0],UNUSED_MEM_PINS_PINLOC_20[29:0],UNUSED_MEM_PINS_PINLOC_19[29:0],UNUSED_MEM_PINS_PINLOC_18[29:0],UNUSED_MEM_PINS_PINLOC_17[29:0],UNUSED_MEM_PINS_PINLOC_16[29:0],UNUSED_MEM_PINS_PINLOC_15[29:0],UNUSED_MEM_PINS_PINLOC_14[29:0],UNUSED_MEM_PINS_PINLOC_13[29:0],UNUSED_MEM_PINS_PINLOC_12[29:0],UNUSED_MEM_PINS_PINLOC_11[29:0],UNUSED_MEM_PINS_PINLOC_10[29:0],UNUSED_MEM_PINS_PINLOC_9[29:0],UNUSED_MEM_PINS_PINLOC_8[29:0],UNUSED_MEM_PINS_PINLOC_7[29:0],UNUSED_MEM_PINS_PINLOC_6[29:0],UNUSED_MEM_PINS_PINLOC_5[29:0],UNUSED_MEM_PINS_PINLOC_4[29:0],UNUSED_MEM_PINS_PINLOC_3[29:0],UNUSED_MEM_PINS_PINLOC_2[29:0],UNUSED_MEM_PINS_PINLOC_1[29:0],UNUSED_MEM_PINS_PINLOC_0[29:0]}; + localparam UNUSED_DQS_BUSES_LANELOC = {UNUSED_DQS_BUSES_LANELOC_10[29:0],UNUSED_DQS_BUSES_LANELOC_9[29:0],UNUSED_DQS_BUSES_LANELOC_8[29:0],UNUSED_DQS_BUSES_LANELOC_7[29:0],UNUSED_DQS_BUSES_LANELOC_6[29:0],UNUSED_DQS_BUSES_LANELOC_5[29:0],UNUSED_DQS_BUSES_LANELOC_4[29:0],UNUSED_DQS_BUSES_LANELOC_3[29:0],UNUSED_DQS_BUSES_LANELOC_2[29:0],UNUSED_DQS_BUSES_LANELOC_1[29:0],UNUSED_DQS_BUSES_LANELOC_0[29:0]}; + localparam CENTER_TIDS = {CENTER_TIDS_2[29:0],CENTER_TIDS_1[29:0],CENTER_TIDS_0[29:0]}; + localparam HMC_TIDS = {HMC_TIDS_2[29:0],HMC_TIDS_1[29:0],HMC_TIDS_0[29:0]}; + localparam LANE_TIDS = {LANE_TIDS_9[29:0],LANE_TIDS_8[29:0],LANE_TIDS_7[29:0],LANE_TIDS_6[29:0],LANE_TIDS_5[29:0],LANE_TIDS_4[29:0],LANE_TIDS_3[29:0],LANE_TIDS_2[29:0],LANE_TIDS_1[29:0],LANE_TIDS_0[29:0]}; + localparam PORT_MEM_CK_PINLOC = {PORT_MEM_CK_PINLOC_5[29:0],PORT_MEM_CK_PINLOC_4[29:0],PORT_MEM_CK_PINLOC_3[29:0],PORT_MEM_CK_PINLOC_2[29:0],PORT_MEM_CK_PINLOC_1[29:0],PORT_MEM_CK_PINLOC_0[29:0]}; + localparam PORT_MEM_CK_N_PINLOC = {PORT_MEM_CK_N_PINLOC_5[29:0],PORT_MEM_CK_N_PINLOC_4[29:0],PORT_MEM_CK_N_PINLOC_3[29:0],PORT_MEM_CK_N_PINLOC_2[29:0],PORT_MEM_CK_N_PINLOC_1[29:0],PORT_MEM_CK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_PINLOC = {PORT_MEM_DK_PINLOC_5[29:0],PORT_MEM_DK_PINLOC_4[29:0],PORT_MEM_DK_PINLOC_3[29:0],PORT_MEM_DK_PINLOC_2[29:0],PORT_MEM_DK_PINLOC_1[29:0],PORT_MEM_DK_PINLOC_0[29:0]}; + localparam PORT_MEM_DK_N_PINLOC = {PORT_MEM_DK_N_PINLOC_5[29:0],PORT_MEM_DK_N_PINLOC_4[29:0],PORT_MEM_DK_N_PINLOC_3[29:0],PORT_MEM_DK_N_PINLOC_2[29:0],PORT_MEM_DK_N_PINLOC_1[29:0],PORT_MEM_DK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_PINLOC = {PORT_MEM_DKA_PINLOC_5[29:0],PORT_MEM_DKA_PINLOC_4[29:0],PORT_MEM_DKA_PINLOC_3[29:0],PORT_MEM_DKA_PINLOC_2[29:0],PORT_MEM_DKA_PINLOC_1[29:0],PORT_MEM_DKA_PINLOC_0[29:0]}; + localparam PORT_MEM_DKA_N_PINLOC = {PORT_MEM_DKA_N_PINLOC_5[29:0],PORT_MEM_DKA_N_PINLOC_4[29:0],PORT_MEM_DKA_N_PINLOC_3[29:0],PORT_MEM_DKA_N_PINLOC_2[29:0],PORT_MEM_DKA_N_PINLOC_1[29:0],PORT_MEM_DKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_PINLOC = {PORT_MEM_DKB_PINLOC_5[29:0],PORT_MEM_DKB_PINLOC_4[29:0],PORT_MEM_DKB_PINLOC_3[29:0],PORT_MEM_DKB_PINLOC_2[29:0],PORT_MEM_DKB_PINLOC_1[29:0],PORT_MEM_DKB_PINLOC_0[29:0]}; + localparam PORT_MEM_DKB_N_PINLOC = {PORT_MEM_DKB_N_PINLOC_5[29:0],PORT_MEM_DKB_N_PINLOC_4[29:0],PORT_MEM_DKB_N_PINLOC_3[29:0],PORT_MEM_DKB_N_PINLOC_2[29:0],PORT_MEM_DKB_N_PINLOC_1[29:0],PORT_MEM_DKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_K_PINLOC = {PORT_MEM_K_PINLOC_5[29:0],PORT_MEM_K_PINLOC_4[29:0],PORT_MEM_K_PINLOC_3[29:0],PORT_MEM_K_PINLOC_2[29:0],PORT_MEM_K_PINLOC_1[29:0],PORT_MEM_K_PINLOC_0[29:0]}; + localparam PORT_MEM_K_N_PINLOC = {PORT_MEM_K_N_PINLOC_5[29:0],PORT_MEM_K_N_PINLOC_4[29:0],PORT_MEM_K_N_PINLOC_3[29:0],PORT_MEM_K_N_PINLOC_2[29:0],PORT_MEM_K_N_PINLOC_1[29:0],PORT_MEM_K_N_PINLOC_0[29:0]}; + localparam PORT_MEM_A_PINLOC = {PORT_MEM_A_PINLOC_16[29:0],PORT_MEM_A_PINLOC_15[29:0],PORT_MEM_A_PINLOC_14[29:0],PORT_MEM_A_PINLOC_13[29:0],PORT_MEM_A_PINLOC_12[29:0],PORT_MEM_A_PINLOC_11[29:0],PORT_MEM_A_PINLOC_10[29:0],PORT_MEM_A_PINLOC_9[29:0],PORT_MEM_A_PINLOC_8[29:0],PORT_MEM_A_PINLOC_7[29:0],PORT_MEM_A_PINLOC_6[29:0],PORT_MEM_A_PINLOC_5[29:0],PORT_MEM_A_PINLOC_4[29:0],PORT_MEM_A_PINLOC_3[29:0],PORT_MEM_A_PINLOC_2[29:0],PORT_MEM_A_PINLOC_1[29:0],PORT_MEM_A_PINLOC_0[29:0]}; + localparam PORT_MEM_BA_PINLOC = {PORT_MEM_BA_PINLOC_5[29:0],PORT_MEM_BA_PINLOC_4[29:0],PORT_MEM_BA_PINLOC_3[29:0],PORT_MEM_BA_PINLOC_2[29:0],PORT_MEM_BA_PINLOC_1[29:0],PORT_MEM_BA_PINLOC_0[29:0]}; + localparam PORT_MEM_BG_PINLOC = {PORT_MEM_BG_PINLOC_5[29:0],PORT_MEM_BG_PINLOC_4[29:0],PORT_MEM_BG_PINLOC_3[29:0],PORT_MEM_BG_PINLOC_2[29:0],PORT_MEM_BG_PINLOC_1[29:0],PORT_MEM_BG_PINLOC_0[29:0]}; + localparam PORT_MEM_C_PINLOC = {PORT_MEM_C_PINLOC_5[29:0],PORT_MEM_C_PINLOC_4[29:0],PORT_MEM_C_PINLOC_3[29:0],PORT_MEM_C_PINLOC_2[29:0],PORT_MEM_C_PINLOC_1[29:0],PORT_MEM_C_PINLOC_0[29:0]}; + localparam PORT_MEM_CKE_PINLOC = {PORT_MEM_CKE_PINLOC_5[29:0],PORT_MEM_CKE_PINLOC_4[29:0],PORT_MEM_CKE_PINLOC_3[29:0],PORT_MEM_CKE_PINLOC_2[29:0],PORT_MEM_CKE_PINLOC_1[29:0],PORT_MEM_CKE_PINLOC_0[29:0]}; + localparam PORT_MEM_CS_N_PINLOC = {PORT_MEM_CS_N_PINLOC_5[29:0],PORT_MEM_CS_N_PINLOC_4[29:0],PORT_MEM_CS_N_PINLOC_3[29:0],PORT_MEM_CS_N_PINLOC_2[29:0],PORT_MEM_CS_N_PINLOC_1[29:0],PORT_MEM_CS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RM_PINLOC = {PORT_MEM_RM_PINLOC_5[29:0],PORT_MEM_RM_PINLOC_4[29:0],PORT_MEM_RM_PINLOC_3[29:0],PORT_MEM_RM_PINLOC_2[29:0],PORT_MEM_RM_PINLOC_1[29:0],PORT_MEM_RM_PINLOC_0[29:0]}; + localparam PORT_MEM_ODT_PINLOC = {PORT_MEM_ODT_PINLOC_5[29:0],PORT_MEM_ODT_PINLOC_4[29:0],PORT_MEM_ODT_PINLOC_3[29:0],PORT_MEM_ODT_PINLOC_2[29:0],PORT_MEM_ODT_PINLOC_1[29:0],PORT_MEM_ODT_PINLOC_0[29:0]}; + localparam PORT_MEM_RAS_N_PINLOC = {PORT_MEM_RAS_N_PINLOC_1[29:0],PORT_MEM_RAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CAS_N_PINLOC = {PORT_MEM_CAS_N_PINLOC_1[29:0],PORT_MEM_CAS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WE_N_PINLOC = {PORT_MEM_WE_N_PINLOC_1[29:0],PORT_MEM_WE_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RESET_N_PINLOC = {PORT_MEM_RESET_N_PINLOC_1[29:0],PORT_MEM_RESET_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ACT_N_PINLOC = {PORT_MEM_ACT_N_PINLOC_1[29:0],PORT_MEM_ACT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PAR_PINLOC = {PORT_MEM_PAR_PINLOC_1[29:0],PORT_MEM_PAR_PINLOC_0[29:0]}; + localparam PORT_MEM_CA_PINLOC = {PORT_MEM_CA_PINLOC_16[29:0],PORT_MEM_CA_PINLOC_15[29:0],PORT_MEM_CA_PINLOC_14[29:0],PORT_MEM_CA_PINLOC_13[29:0],PORT_MEM_CA_PINLOC_12[29:0],PORT_MEM_CA_PINLOC_11[29:0],PORT_MEM_CA_PINLOC_10[29:0],PORT_MEM_CA_PINLOC_9[29:0],PORT_MEM_CA_PINLOC_8[29:0],PORT_MEM_CA_PINLOC_7[29:0],PORT_MEM_CA_PINLOC_6[29:0],PORT_MEM_CA_PINLOC_5[29:0],PORT_MEM_CA_PINLOC_4[29:0],PORT_MEM_CA_PINLOC_3[29:0],PORT_MEM_CA_PINLOC_2[29:0],PORT_MEM_CA_PINLOC_1[29:0],PORT_MEM_CA_PINLOC_0[29:0]}; + localparam PORT_MEM_REF_N_PINLOC = {PORT_MEM_REF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_WPS_N_PINLOC = {PORT_MEM_WPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RPS_N_PINLOC = {PORT_MEM_RPS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DOFF_N_PINLOC = {PORT_MEM_DOFF_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDA_N_PINLOC = {PORT_MEM_LDA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LDB_N_PINLOC = {PORT_MEM_LDB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWA_N_PINLOC = {PORT_MEM_RWA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_RWB_N_PINLOC = {PORT_MEM_RWB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK0_N_PINLOC = {PORT_MEM_LBK0_N_PINLOC_0[29:0]}; + localparam PORT_MEM_LBK1_N_PINLOC = {PORT_MEM_LBK1_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CFG_N_PINLOC = {PORT_MEM_CFG_N_PINLOC_0[29:0]}; + localparam PORT_MEM_AP_PINLOC = {PORT_MEM_AP_PINLOC_0[29:0]}; + localparam PORT_MEM_AINV_PINLOC = {PORT_MEM_AINV_PINLOC_0[29:0]}; + localparam PORT_MEM_DM_PINLOC = {PORT_MEM_DM_PINLOC_12[29:0],PORT_MEM_DM_PINLOC_11[29:0],PORT_MEM_DM_PINLOC_10[29:0],PORT_MEM_DM_PINLOC_9[29:0],PORT_MEM_DM_PINLOC_8[29:0],PORT_MEM_DM_PINLOC_7[29:0],PORT_MEM_DM_PINLOC_6[29:0],PORT_MEM_DM_PINLOC_5[29:0],PORT_MEM_DM_PINLOC_4[29:0],PORT_MEM_DM_PINLOC_3[29:0],PORT_MEM_DM_PINLOC_2[29:0],PORT_MEM_DM_PINLOC_1[29:0],PORT_MEM_DM_PINLOC_0[29:0]}; + localparam PORT_MEM_BWS_N_PINLOC = {PORT_MEM_BWS_N_PINLOC_2[29:0],PORT_MEM_BWS_N_PINLOC_1[29:0],PORT_MEM_BWS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_D_PINLOC = {PORT_MEM_D_PINLOC_48[29:0],PORT_MEM_D_PINLOC_47[29:0],PORT_MEM_D_PINLOC_46[29:0],PORT_MEM_D_PINLOC_45[29:0],PORT_MEM_D_PINLOC_44[29:0],PORT_MEM_D_PINLOC_43[29:0],PORT_MEM_D_PINLOC_42[29:0],PORT_MEM_D_PINLOC_41[29:0],PORT_MEM_D_PINLOC_40[29:0],PORT_MEM_D_PINLOC_39[29:0],PORT_MEM_D_PINLOC_38[29:0],PORT_MEM_D_PINLOC_37[29:0],PORT_MEM_D_PINLOC_36[29:0],PORT_MEM_D_PINLOC_35[29:0],PORT_MEM_D_PINLOC_34[29:0],PORT_MEM_D_PINLOC_33[29:0],PORT_MEM_D_PINLOC_32[29:0],PORT_MEM_D_PINLOC_31[29:0],PORT_MEM_D_PINLOC_30[29:0],PORT_MEM_D_PINLOC_29[29:0],PORT_MEM_D_PINLOC_28[29:0],PORT_MEM_D_PINLOC_27[29:0],PORT_MEM_D_PINLOC_26[29:0],PORT_MEM_D_PINLOC_25[29:0],PORT_MEM_D_PINLOC_24[29:0],PORT_MEM_D_PINLOC_23[29:0],PORT_MEM_D_PINLOC_22[29:0],PORT_MEM_D_PINLOC_21[29:0],PORT_MEM_D_PINLOC_20[29:0],PORT_MEM_D_PINLOC_19[29:0],PORT_MEM_D_PINLOC_18[29:0],PORT_MEM_D_PINLOC_17[29:0],PORT_MEM_D_PINLOC_16[29:0],PORT_MEM_D_PINLOC_15[29:0],PORT_MEM_D_PINLOC_14[29:0],PORT_MEM_D_PINLOC_13[29:0],PORT_MEM_D_PINLOC_12[29:0],PORT_MEM_D_PINLOC_11[29:0],PORT_MEM_D_PINLOC_10[29:0],PORT_MEM_D_PINLOC_9[29:0],PORT_MEM_D_PINLOC_8[29:0],PORT_MEM_D_PINLOC_7[29:0],PORT_MEM_D_PINLOC_6[29:0],PORT_MEM_D_PINLOC_5[29:0],PORT_MEM_D_PINLOC_4[29:0],PORT_MEM_D_PINLOC_3[29:0],PORT_MEM_D_PINLOC_2[29:0],PORT_MEM_D_PINLOC_1[29:0],PORT_MEM_D_PINLOC_0[29:0]}; + localparam PORT_MEM_DQ_PINLOC = {PORT_MEM_DQ_PINLOC_48[29:0],PORT_MEM_DQ_PINLOC_47[29:0],PORT_MEM_DQ_PINLOC_46[29:0],PORT_MEM_DQ_PINLOC_45[29:0],PORT_MEM_DQ_PINLOC_44[29:0],PORT_MEM_DQ_PINLOC_43[29:0],PORT_MEM_DQ_PINLOC_42[29:0],PORT_MEM_DQ_PINLOC_41[29:0],PORT_MEM_DQ_PINLOC_40[29:0],PORT_MEM_DQ_PINLOC_39[29:0],PORT_MEM_DQ_PINLOC_38[29:0],PORT_MEM_DQ_PINLOC_37[29:0],PORT_MEM_DQ_PINLOC_36[29:0],PORT_MEM_DQ_PINLOC_35[29:0],PORT_MEM_DQ_PINLOC_34[29:0],PORT_MEM_DQ_PINLOC_33[29:0],PORT_MEM_DQ_PINLOC_32[29:0],PORT_MEM_DQ_PINLOC_31[29:0],PORT_MEM_DQ_PINLOC_30[29:0],PORT_MEM_DQ_PINLOC_29[29:0],PORT_MEM_DQ_PINLOC_28[29:0],PORT_MEM_DQ_PINLOC_27[29:0],PORT_MEM_DQ_PINLOC_26[29:0],PORT_MEM_DQ_PINLOC_25[29:0],PORT_MEM_DQ_PINLOC_24[29:0],PORT_MEM_DQ_PINLOC_23[29:0],PORT_MEM_DQ_PINLOC_22[29:0],PORT_MEM_DQ_PINLOC_21[29:0],PORT_MEM_DQ_PINLOC_20[29:0],PORT_MEM_DQ_PINLOC_19[29:0],PORT_MEM_DQ_PINLOC_18[29:0],PORT_MEM_DQ_PINLOC_17[29:0],PORT_MEM_DQ_PINLOC_16[29:0],PORT_MEM_DQ_PINLOC_15[29:0],PORT_MEM_DQ_PINLOC_14[29:0],PORT_MEM_DQ_PINLOC_13[29:0],PORT_MEM_DQ_PINLOC_12[29:0],PORT_MEM_DQ_PINLOC_11[29:0],PORT_MEM_DQ_PINLOC_10[29:0],PORT_MEM_DQ_PINLOC_9[29:0],PORT_MEM_DQ_PINLOC_8[29:0],PORT_MEM_DQ_PINLOC_7[29:0],PORT_MEM_DQ_PINLOC_6[29:0],PORT_MEM_DQ_PINLOC_5[29:0],PORT_MEM_DQ_PINLOC_4[29:0],PORT_MEM_DQ_PINLOC_3[29:0],PORT_MEM_DQ_PINLOC_2[29:0],PORT_MEM_DQ_PINLOC_1[29:0],PORT_MEM_DQ_PINLOC_0[29:0]}; + localparam PORT_MEM_DBI_N_PINLOC = {PORT_MEM_DBI_N_PINLOC_6[29:0],PORT_MEM_DBI_N_PINLOC_5[29:0],PORT_MEM_DBI_N_PINLOC_4[29:0],PORT_MEM_DBI_N_PINLOC_3[29:0],PORT_MEM_DBI_N_PINLOC_2[29:0],PORT_MEM_DBI_N_PINLOC_1[29:0],PORT_MEM_DBI_N_PINLOC_0[29:0]}; + localparam PORT_MEM_DQA_PINLOC = {PORT_MEM_DQA_PINLOC_48[29:0],PORT_MEM_DQA_PINLOC_47[29:0],PORT_MEM_DQA_PINLOC_46[29:0],PORT_MEM_DQA_PINLOC_45[29:0],PORT_MEM_DQA_PINLOC_44[29:0],PORT_MEM_DQA_PINLOC_43[29:0],PORT_MEM_DQA_PINLOC_42[29:0],PORT_MEM_DQA_PINLOC_41[29:0],PORT_MEM_DQA_PINLOC_40[29:0],PORT_MEM_DQA_PINLOC_39[29:0],PORT_MEM_DQA_PINLOC_38[29:0],PORT_MEM_DQA_PINLOC_37[29:0],PORT_MEM_DQA_PINLOC_36[29:0],PORT_MEM_DQA_PINLOC_35[29:0],PORT_MEM_DQA_PINLOC_34[29:0],PORT_MEM_DQA_PINLOC_33[29:0],PORT_MEM_DQA_PINLOC_32[29:0],PORT_MEM_DQA_PINLOC_31[29:0],PORT_MEM_DQA_PINLOC_30[29:0],PORT_MEM_DQA_PINLOC_29[29:0],PORT_MEM_DQA_PINLOC_28[29:0],PORT_MEM_DQA_PINLOC_27[29:0],PORT_MEM_DQA_PINLOC_26[29:0],PORT_MEM_DQA_PINLOC_25[29:0],PORT_MEM_DQA_PINLOC_24[29:0],PORT_MEM_DQA_PINLOC_23[29:0],PORT_MEM_DQA_PINLOC_22[29:0],PORT_MEM_DQA_PINLOC_21[29:0],PORT_MEM_DQA_PINLOC_20[29:0],PORT_MEM_DQA_PINLOC_19[29:0],PORT_MEM_DQA_PINLOC_18[29:0],PORT_MEM_DQA_PINLOC_17[29:0],PORT_MEM_DQA_PINLOC_16[29:0],PORT_MEM_DQA_PINLOC_15[29:0],PORT_MEM_DQA_PINLOC_14[29:0],PORT_MEM_DQA_PINLOC_13[29:0],PORT_MEM_DQA_PINLOC_12[29:0],PORT_MEM_DQA_PINLOC_11[29:0],PORT_MEM_DQA_PINLOC_10[29:0],PORT_MEM_DQA_PINLOC_9[29:0],PORT_MEM_DQA_PINLOC_8[29:0],PORT_MEM_DQA_PINLOC_7[29:0],PORT_MEM_DQA_PINLOC_6[29:0],PORT_MEM_DQA_PINLOC_5[29:0],PORT_MEM_DQA_PINLOC_4[29:0],PORT_MEM_DQA_PINLOC_3[29:0],PORT_MEM_DQA_PINLOC_2[29:0],PORT_MEM_DQA_PINLOC_1[29:0],PORT_MEM_DQA_PINLOC_0[29:0]}; + localparam PORT_MEM_DQB_PINLOC = {PORT_MEM_DQB_PINLOC_48[29:0],PORT_MEM_DQB_PINLOC_47[29:0],PORT_MEM_DQB_PINLOC_46[29:0],PORT_MEM_DQB_PINLOC_45[29:0],PORT_MEM_DQB_PINLOC_44[29:0],PORT_MEM_DQB_PINLOC_43[29:0],PORT_MEM_DQB_PINLOC_42[29:0],PORT_MEM_DQB_PINLOC_41[29:0],PORT_MEM_DQB_PINLOC_40[29:0],PORT_MEM_DQB_PINLOC_39[29:0],PORT_MEM_DQB_PINLOC_38[29:0],PORT_MEM_DQB_PINLOC_37[29:0],PORT_MEM_DQB_PINLOC_36[29:0],PORT_MEM_DQB_PINLOC_35[29:0],PORT_MEM_DQB_PINLOC_34[29:0],PORT_MEM_DQB_PINLOC_33[29:0],PORT_MEM_DQB_PINLOC_32[29:0],PORT_MEM_DQB_PINLOC_31[29:0],PORT_MEM_DQB_PINLOC_30[29:0],PORT_MEM_DQB_PINLOC_29[29:0],PORT_MEM_DQB_PINLOC_28[29:0],PORT_MEM_DQB_PINLOC_27[29:0],PORT_MEM_DQB_PINLOC_26[29:0],PORT_MEM_DQB_PINLOC_25[29:0],PORT_MEM_DQB_PINLOC_24[29:0],PORT_MEM_DQB_PINLOC_23[29:0],PORT_MEM_DQB_PINLOC_22[29:0],PORT_MEM_DQB_PINLOC_21[29:0],PORT_MEM_DQB_PINLOC_20[29:0],PORT_MEM_DQB_PINLOC_19[29:0],PORT_MEM_DQB_PINLOC_18[29:0],PORT_MEM_DQB_PINLOC_17[29:0],PORT_MEM_DQB_PINLOC_16[29:0],PORT_MEM_DQB_PINLOC_15[29:0],PORT_MEM_DQB_PINLOC_14[29:0],PORT_MEM_DQB_PINLOC_13[29:0],PORT_MEM_DQB_PINLOC_12[29:0],PORT_MEM_DQB_PINLOC_11[29:0],PORT_MEM_DQB_PINLOC_10[29:0],PORT_MEM_DQB_PINLOC_9[29:0],PORT_MEM_DQB_PINLOC_8[29:0],PORT_MEM_DQB_PINLOC_7[29:0],PORT_MEM_DQB_PINLOC_6[29:0],PORT_MEM_DQB_PINLOC_5[29:0],PORT_MEM_DQB_PINLOC_4[29:0],PORT_MEM_DQB_PINLOC_3[29:0],PORT_MEM_DQB_PINLOC_2[29:0],PORT_MEM_DQB_PINLOC_1[29:0],PORT_MEM_DQB_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVA_PINLOC = {PORT_MEM_DINVA_PINLOC_2[29:0],PORT_MEM_DINVA_PINLOC_1[29:0],PORT_MEM_DINVA_PINLOC_0[29:0]}; + localparam PORT_MEM_DINVB_PINLOC = {PORT_MEM_DINVB_PINLOC_2[29:0],PORT_MEM_DINVB_PINLOC_1[29:0],PORT_MEM_DINVB_PINLOC_0[29:0]}; + localparam PORT_MEM_Q_PINLOC = {PORT_MEM_Q_PINLOC_48[29:0],PORT_MEM_Q_PINLOC_47[29:0],PORT_MEM_Q_PINLOC_46[29:0],PORT_MEM_Q_PINLOC_45[29:0],PORT_MEM_Q_PINLOC_44[29:0],PORT_MEM_Q_PINLOC_43[29:0],PORT_MEM_Q_PINLOC_42[29:0],PORT_MEM_Q_PINLOC_41[29:0],PORT_MEM_Q_PINLOC_40[29:0],PORT_MEM_Q_PINLOC_39[29:0],PORT_MEM_Q_PINLOC_38[29:0],PORT_MEM_Q_PINLOC_37[29:0],PORT_MEM_Q_PINLOC_36[29:0],PORT_MEM_Q_PINLOC_35[29:0],PORT_MEM_Q_PINLOC_34[29:0],PORT_MEM_Q_PINLOC_33[29:0],PORT_MEM_Q_PINLOC_32[29:0],PORT_MEM_Q_PINLOC_31[29:0],PORT_MEM_Q_PINLOC_30[29:0],PORT_MEM_Q_PINLOC_29[29:0],PORT_MEM_Q_PINLOC_28[29:0],PORT_MEM_Q_PINLOC_27[29:0],PORT_MEM_Q_PINLOC_26[29:0],PORT_MEM_Q_PINLOC_25[29:0],PORT_MEM_Q_PINLOC_24[29:0],PORT_MEM_Q_PINLOC_23[29:0],PORT_MEM_Q_PINLOC_22[29:0],PORT_MEM_Q_PINLOC_21[29:0],PORT_MEM_Q_PINLOC_20[29:0],PORT_MEM_Q_PINLOC_19[29:0],PORT_MEM_Q_PINLOC_18[29:0],PORT_MEM_Q_PINLOC_17[29:0],PORT_MEM_Q_PINLOC_16[29:0],PORT_MEM_Q_PINLOC_15[29:0],PORT_MEM_Q_PINLOC_14[29:0],PORT_MEM_Q_PINLOC_13[29:0],PORT_MEM_Q_PINLOC_12[29:0],PORT_MEM_Q_PINLOC_11[29:0],PORT_MEM_Q_PINLOC_10[29:0],PORT_MEM_Q_PINLOC_9[29:0],PORT_MEM_Q_PINLOC_8[29:0],PORT_MEM_Q_PINLOC_7[29:0],PORT_MEM_Q_PINLOC_6[29:0],PORT_MEM_Q_PINLOC_5[29:0],PORT_MEM_Q_PINLOC_4[29:0],PORT_MEM_Q_PINLOC_3[29:0],PORT_MEM_Q_PINLOC_2[29:0],PORT_MEM_Q_PINLOC_1[29:0],PORT_MEM_Q_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_PINLOC = {PORT_MEM_DQS_PINLOC_12[29:0],PORT_MEM_DQS_PINLOC_11[29:0],PORT_MEM_DQS_PINLOC_10[29:0],PORT_MEM_DQS_PINLOC_9[29:0],PORT_MEM_DQS_PINLOC_8[29:0],PORT_MEM_DQS_PINLOC_7[29:0],PORT_MEM_DQS_PINLOC_6[29:0],PORT_MEM_DQS_PINLOC_5[29:0],PORT_MEM_DQS_PINLOC_4[29:0],PORT_MEM_DQS_PINLOC_3[29:0],PORT_MEM_DQS_PINLOC_2[29:0],PORT_MEM_DQS_PINLOC_1[29:0],PORT_MEM_DQS_PINLOC_0[29:0]}; + localparam PORT_MEM_DQS_N_PINLOC = {PORT_MEM_DQS_N_PINLOC_12[29:0],PORT_MEM_DQS_N_PINLOC_11[29:0],PORT_MEM_DQS_N_PINLOC_10[29:0],PORT_MEM_DQS_N_PINLOC_9[29:0],PORT_MEM_DQS_N_PINLOC_8[29:0],PORT_MEM_DQS_N_PINLOC_7[29:0],PORT_MEM_DQS_N_PINLOC_6[29:0],PORT_MEM_DQS_N_PINLOC_5[29:0],PORT_MEM_DQS_N_PINLOC_4[29:0],PORT_MEM_DQS_N_PINLOC_3[29:0],PORT_MEM_DQS_N_PINLOC_2[29:0],PORT_MEM_DQS_N_PINLOC_1[29:0],PORT_MEM_DQS_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_PINLOC = {PORT_MEM_QK_PINLOC_5[29:0],PORT_MEM_QK_PINLOC_4[29:0],PORT_MEM_QK_PINLOC_3[29:0],PORT_MEM_QK_PINLOC_2[29:0],PORT_MEM_QK_PINLOC_1[29:0],PORT_MEM_QK_PINLOC_0[29:0]}; + localparam PORT_MEM_QK_N_PINLOC = {PORT_MEM_QK_N_PINLOC_5[29:0],PORT_MEM_QK_N_PINLOC_4[29:0],PORT_MEM_QK_N_PINLOC_3[29:0],PORT_MEM_QK_N_PINLOC_2[29:0],PORT_MEM_QK_N_PINLOC_1[29:0],PORT_MEM_QK_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_PINLOC = {PORT_MEM_QKA_PINLOC_5[29:0],PORT_MEM_QKA_PINLOC_4[29:0],PORT_MEM_QKA_PINLOC_3[29:0],PORT_MEM_QKA_PINLOC_2[29:0],PORT_MEM_QKA_PINLOC_1[29:0],PORT_MEM_QKA_PINLOC_0[29:0]}; + localparam PORT_MEM_QKA_N_PINLOC = {PORT_MEM_QKA_N_PINLOC_5[29:0],PORT_MEM_QKA_N_PINLOC_4[29:0],PORT_MEM_QKA_N_PINLOC_3[29:0],PORT_MEM_QKA_N_PINLOC_2[29:0],PORT_MEM_QKA_N_PINLOC_1[29:0],PORT_MEM_QKA_N_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_PINLOC = {PORT_MEM_QKB_PINLOC_5[29:0],PORT_MEM_QKB_PINLOC_4[29:0],PORT_MEM_QKB_PINLOC_3[29:0],PORT_MEM_QKB_PINLOC_2[29:0],PORT_MEM_QKB_PINLOC_1[29:0],PORT_MEM_QKB_PINLOC_0[29:0]}; + localparam PORT_MEM_QKB_N_PINLOC = {PORT_MEM_QKB_N_PINLOC_5[29:0],PORT_MEM_QKB_N_PINLOC_4[29:0],PORT_MEM_QKB_N_PINLOC_3[29:0],PORT_MEM_QKB_N_PINLOC_2[29:0],PORT_MEM_QKB_N_PINLOC_1[29:0],PORT_MEM_QKB_N_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_PINLOC = {PORT_MEM_CQ_PINLOC_1[29:0],PORT_MEM_CQ_PINLOC_0[29:0]}; + localparam PORT_MEM_CQ_N_PINLOC = {PORT_MEM_CQ_N_PINLOC_1[29:0],PORT_MEM_CQ_N_PINLOC_0[29:0]}; + localparam PORT_MEM_ALERT_N_PINLOC = {PORT_MEM_ALERT_N_PINLOC_1[29:0],PORT_MEM_ALERT_N_PINLOC_0[29:0]}; + localparam PORT_MEM_PE_N_PINLOC = {PORT_MEM_PE_N_PINLOC_1[29:0],PORT_MEM_PE_N_PINLOC_0[29:0]}; + + localparam LANES_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE; + localparam PINS_IN_RTL_TILES = NUM_OF_RTL_TILES * LANES_PER_TILE * PINS_PER_LANE; + + // Select which DBC to use as shadow for the primary HMC. + // We always pick "dbc1_to_local" as it's guaranteed to be used by the interface (as an A/C lane). + // The exception is for HPS mode - HPS is only connected to lane 3 of the HMC tile for the + // various Avalon control signals, therefore we must denote lane 3 as shadow. + localparam PRI_HMC_DBC_SHADOW_LANE_INDEX = IS_HPS ? 3 : 1; + + // The actual reset signal, selected from either the local signal or from master + logic global_reset_n_int; + + // The actual PLL ref clock signal, selected from either the local signal or from master + logic pll_ref_clk_int; + + // Reset Signals + logic phy_reset_n; // Reset signal from tile that is completely asynchronous + + // Signals for various clocks + logic pll_dll_clk; // PLL -> DLL output clock + logic [7:0] phy_clk_phs; // FR PHY clock signals (8 phases, 45-deg apart) + logic [1:0] phy_clk; // {phy_clk[1], phy_clk[0]} + logic phy_fb_clk_to_tile; // PHY feedback clock (to tile) + logic phy_fb_clk_to_pll; // PHY feedback clock (to PLL) + logic [8:0] pll_c_counters; // PLL C counter outputs + logic pll_extra_clk_diag_ok; // Internal test signal for PLL extra clocks + + // Core clock signals from/to the Clock Phase Alignment (CPA) block + logic [1:0] core_clks_from_cpa_pri; + logic [1:0] core_clks_locked_cpa_pri; + logic [1:0] core_clks_fb_to_cpa_pri; + logic [1:0] core_clks_from_cpa_sec; + logic [1:0] core_clks_locked_cpa_sec; + logic [1:0] core_clks_fb_to_cpa_sec; + logic dcc_stable; + + // Avalon interfaces between core and HMC + logic [59:0] core2ctl_avl_0; + logic [59:0] core2ctl_avl_1; + logic core2ctl_avl_rd_data_ready_0; + logic core2ctl_avl_rd_data_ready_1; + logic ctl2core_avl_cmd_ready_0; + logic ctl2core_avl_cmd_ready_1; + logic [12:0] ctl2core_avl_rdata_id_0; + logic [12:0] ctl2core_avl_rdata_id_1; + logic core2l_wr_data_vld_ast_0; + logic core2l_wr_data_vld_ast_1; + logic core2l_rd_data_rdy_ast_0; + logic core2l_rd_data_rdy_ast_1; + + // Avalon interfaces between core and lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_rd_data_vld_avl0; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0] l2core_wr_data_rdy_ast; + + // ECC signals between core and lanes + logic [12:0] core2l_wr_ecc_info_0; + logic [12:0] core2l_wr_ecc_info_1; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][11:0] l2core_wb_pointer_for_ecc; + + // Signals between core and data lanes + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] core2l_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] l2core_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 4 - 1:0] core2l_oe; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] core2l_rdata_en_full; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_read; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][15:0] core2l_mrnk_write; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][3:0] l2core_rdata_valid; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_rlat; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] l2core_afi_wlat; + + // Wires for wire-luts + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] wl1_l2core_data; + logic [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][PINS_PER_LANE * 8 - 1:0] wl2_l2core_data; + + // AFI signals between tile and core + logic [16:0] c2t_afi; + logic [25:0] t2c_afi; + + // Side-band signals between core and HMC + logic [41:0] core2ctl_sideband_0; + logic [13:0] ctl2core_sideband_0; + logic [41:0] core2ctl_sideband_1; + logic [13:0] ctl2core_sideband_1; + + // MMR signals between core and HMC + logic [33:0] ctl2core_mmr_0; + logic [50:0] core2ctl_mmr_0; + logic [33:0] ctl2core_mmr_1; + logic [50:0] core2ctl_mmr_1; + + // Signals for connecting OCT block to I/O buffers + logic [OCT_CONTROL_WIDTH-1:0] oct_stc; // serial-termination-control + logic [OCT_CONTROL_WIDTH-1:0] oct_ptc; // parallel-termination-control + logic oct_cal_req; // OCT manual calibration request + logic oct_cal_rdy; // OCT manual calibration ready + logic oct_recal_req; // OCT manual calibration request + logic oct_s2pload_rdy; // OCT manual calibration load ready + logic oct_s2pload_ena; // OCT manual calibration load stall + + // Signals for connecting emif signals between lanes/tiles and I/O buffers + logic [PINS_IN_RTL_TILES-1:0] l2b_data; // lane-to-buffer data + logic [PINS_IN_RTL_TILES-1:0] l2b_oe; // lane-to-buffer output-enable + logic [PINS_IN_RTL_TILES-1:0] l2b_dtc; // lane-to-buffer dynamic-termination-control + logic [PINS_IN_RTL_TILES-1:0] b2l_data; // buffer-to-lane data + logic [LANES_IN_RTL_TILES-1:0] b2t_dqs; // buffer-to-tile DQS + logic [LANES_IN_RTL_TILES-1:0] b2t_dqsb; // buffer-to-tile DQSb + + // Avalon-MM bus for the calibration commands between io_aux and tiles + logic cal_bus_clk; + logic cal_bus_avl_read; + logic cal_bus_avl_write; + logic [19:0] cal_bus_avl_address; + logic [31:0] cal_bus_avl_read_data; + logic [31:0] cal_bus_avl_write_data; + + // Internal signal for cal_counter + logic afi_cal_in_progress; + + assign local_cal_success = afi_cal_success & pll_extra_clk_diag_ok; + assign local_cal_fail = afi_cal_fail; + + assign afi_mps_ack = 1'b0; + + wire runAbstractPhySim; + wire global_reset_n_int_io_aux_in; + wire cal_debug_reset_n_io_aux_in; + wire cal_slave_reset_n_in_io_aux_in; + +`ifdef ALTERA_EMIF_ENABLE_ISSP + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALP"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_success ( + .probe (local_cal_success) + ); + + altsource_probe #( + .sld_auto_instance_index ("YES"), + .sld_instance_index (0), + .instance_id ("CALF"), + .probe_width (1), + .source_width (0), + .source_initial_value ("0"), + .enable_metastability ("NO") + ) cal_fail ( + .probe (local_cal_fail) + ); +`endif + + //////////////////////////////////////////////////////////////////////////// + // PLL + //////////////////////////////////////////////////////////////////////////// + generate + // synthesis translate_off + if (DIAG_FAST_SIM) begin : gen_fast_sim + altera_emif_arch_nf_pll_fast_sim # ( + .PLL_SIM_VCO_FREQ_PS (PLL_SIM_VCO_FREQ_PS), + .PLL_SIM_PHYCLK_0_FREQ_PS (PLL_SIM_PHYCLK_0_FREQ_PS), + .PLL_SIM_PHYCLK_1_FREQ_PS (PLL_SIM_PHYCLK_1_FREQ_PS), + .PLL_SIM_PHYCLK_FB_FREQ_PS (PLL_SIM_PHYCLK_FB_FREQ_PS), + .PLL_SIM_PHY_CLK_VCO_PHASE_PS (PLL_SIM_PHY_CLK_VCO_PHASE_PS), + .PLL_SIM_CAL_SLAVE_CLK_FREQ_PS (PLL_SIM_CAL_SLAVE_CLK_FREQ_PS), + .PLL_SIM_CAL_MASTER_CLK_FREQ_PS (PLL_SIM_CAL_MASTER_CLK_FREQ_PS), + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH) + ) pll_inst ( + .* + ); + end else begin : gen_normal + // synthesis translate_on + altera_emif_arch_nf_pll # ( + .PORT_DFT_NF_PLL_CNTSEL_WIDTH (PORT_DFT_NF_PLL_CNTSEL_WIDTH), + .PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH (PORT_DFT_NF_PLL_NUM_SHIFT_WIDTH), + .PLL_REF_CLK_FREQ_PS_STR (PLL_REF_CLK_FREQ_PS_STR), + .PLL_VCO_FREQ_PS_STR (PLL_VCO_FREQ_PS_STR), + .PLL_M_CNT_HIGH (PLL_M_CNT_HIGH), + .PLL_M_CNT_LOW (PLL_M_CNT_LOW), + .PLL_N_CNT_HIGH (PLL_N_CNT_HIGH), + .PLL_N_CNT_LOW (PLL_N_CNT_LOW), + .PLL_M_CNT_BYPASS_EN (PLL_M_CNT_BYPASS_EN), + .PLL_N_CNT_BYPASS_EN (PLL_N_CNT_BYPASS_EN), + .PLL_M_CNT_EVEN_DUTY_EN (PLL_M_CNT_EVEN_DUTY_EN), + .PLL_N_CNT_EVEN_DUTY_EN (PLL_N_CNT_EVEN_DUTY_EN), + .PLL_CP_SETTING (PLL_CP_SETTING), + .PLL_BW_CTRL (PLL_BW_CTRL), + .PLL_C_CNT_HIGH_0 (PLL_C_CNT_HIGH_0), + .PLL_C_CNT_LOW_0 (PLL_C_CNT_LOW_0), + .PLL_C_CNT_PRST_0 (PLL_C_CNT_PRST_0), + .PLL_C_CNT_PH_MUX_PRST_0 (PLL_C_CNT_PH_MUX_PRST_0), + .PLL_C_CNT_BYPASS_EN_0 (PLL_C_CNT_BYPASS_EN_0), + .PLL_C_CNT_EVEN_DUTY_EN_0 (PLL_C_CNT_EVEN_DUTY_EN_0), + .PLL_C_CNT_HIGH_1 (PLL_C_CNT_HIGH_1), + .PLL_C_CNT_LOW_1 (PLL_C_CNT_LOW_1), + .PLL_C_CNT_PRST_1 (PLL_C_CNT_PRST_1), + .PLL_C_CNT_PH_MUX_PRST_1 (PLL_C_CNT_PH_MUX_PRST_1), + .PLL_C_CNT_BYPASS_EN_1 (PLL_C_CNT_BYPASS_EN_1), + .PLL_C_CNT_EVEN_DUTY_EN_1 (PLL_C_CNT_EVEN_DUTY_EN_1), + .PLL_C_CNT_HIGH_2 (PLL_C_CNT_HIGH_2), + .PLL_C_CNT_LOW_2 (PLL_C_CNT_LOW_2), + .PLL_C_CNT_PRST_2 (PLL_C_CNT_PRST_2), + .PLL_C_CNT_PH_MUX_PRST_2 (PLL_C_CNT_PH_MUX_PRST_2), + .PLL_C_CNT_BYPASS_EN_2 (PLL_C_CNT_BYPASS_EN_2), + .PLL_C_CNT_EVEN_DUTY_EN_2 (PLL_C_CNT_EVEN_DUTY_EN_2), + .PLL_C_CNT_HIGH_3 (PLL_C_CNT_HIGH_3), + .PLL_C_CNT_LOW_3 (PLL_C_CNT_LOW_3), + .PLL_C_CNT_PRST_3 (PLL_C_CNT_PRST_3), + .PLL_C_CNT_PH_MUX_PRST_3 (PLL_C_CNT_PH_MUX_PRST_3), + .PLL_C_CNT_BYPASS_EN_3 (PLL_C_CNT_BYPASS_EN_3), + .PLL_C_CNT_EVEN_DUTY_EN_3 (PLL_C_CNT_EVEN_DUTY_EN_3), + .PLL_C_CNT_HIGH_4 (PLL_C_CNT_HIGH_4), + .PLL_C_CNT_LOW_4 (PLL_C_CNT_LOW_4), + .PLL_C_CNT_PRST_4 (PLL_C_CNT_PRST_4), + .PLL_C_CNT_PH_MUX_PRST_4 (PLL_C_CNT_PH_MUX_PRST_4), + .PLL_C_CNT_BYPASS_EN_4 (PLL_C_CNT_BYPASS_EN_4), + .PLL_C_CNT_EVEN_DUTY_EN_4 (PLL_C_CNT_EVEN_DUTY_EN_4), + .PLL_C_CNT_HIGH_5 (PLL_C_CNT_HIGH_5), + .PLL_C_CNT_LOW_5 (PLL_C_CNT_LOW_5), + .PLL_C_CNT_PRST_5 (PLL_C_CNT_PRST_5), + .PLL_C_CNT_PH_MUX_PRST_5 (PLL_C_CNT_PH_MUX_PRST_5), + .PLL_C_CNT_BYPASS_EN_5 (PLL_C_CNT_BYPASS_EN_5), + .PLL_C_CNT_EVEN_DUTY_EN_5 (PLL_C_CNT_EVEN_DUTY_EN_5), + .PLL_C_CNT_HIGH_6 (PLL_C_CNT_HIGH_6), + .PLL_C_CNT_LOW_6 (PLL_C_CNT_LOW_6), + .PLL_C_CNT_PRST_6 (PLL_C_CNT_PRST_6), + .PLL_C_CNT_PH_MUX_PRST_6 (PLL_C_CNT_PH_MUX_PRST_6), + .PLL_C_CNT_BYPASS_EN_6 (PLL_C_CNT_BYPASS_EN_6), + .PLL_C_CNT_EVEN_DUTY_EN_6 (PLL_C_CNT_EVEN_DUTY_EN_6), + .PLL_C_CNT_HIGH_7 (PLL_C_CNT_HIGH_7), + .PLL_C_CNT_LOW_7 (PLL_C_CNT_LOW_7), + .PLL_C_CNT_PRST_7 (PLL_C_CNT_PRST_7), + .PLL_C_CNT_PH_MUX_PRST_7 (PLL_C_CNT_PH_MUX_PRST_7), + .PLL_C_CNT_BYPASS_EN_7 (PLL_C_CNT_BYPASS_EN_7), + .PLL_C_CNT_EVEN_DUTY_EN_7 (PLL_C_CNT_EVEN_DUTY_EN_7), + .PLL_C_CNT_HIGH_8 (PLL_C_CNT_HIGH_8), + .PLL_C_CNT_LOW_8 (PLL_C_CNT_LOW_8), + .PLL_C_CNT_PRST_8 (PLL_C_CNT_PRST_8), + .PLL_C_CNT_PH_MUX_PRST_8 (PLL_C_CNT_PH_MUX_PRST_8), + .PLL_C_CNT_BYPASS_EN_8 (PLL_C_CNT_BYPASS_EN_8), + .PLL_C_CNT_EVEN_DUTY_EN_8 (PLL_C_CNT_EVEN_DUTY_EN_8), + .PLL_C_CNT_FREQ_PS_STR_0 (PLL_C_CNT_FREQ_PS_STR_0), + .PLL_C_CNT_PHASE_PS_STR_0 (PLL_C_CNT_PHASE_PS_STR_0), + .PLL_C_CNT_DUTY_CYCLE_0 (PLL_C_CNT_DUTY_CYCLE_0), + .PLL_C_CNT_FREQ_PS_STR_1 (PLL_C_CNT_FREQ_PS_STR_1), + .PLL_C_CNT_PHASE_PS_STR_1 (PLL_C_CNT_PHASE_PS_STR_1), + .PLL_C_CNT_DUTY_CYCLE_1 (PLL_C_CNT_DUTY_CYCLE_1), + .PLL_C_CNT_FREQ_PS_STR_2 (PLL_C_CNT_FREQ_PS_STR_2), + .PLL_C_CNT_PHASE_PS_STR_2 (PLL_C_CNT_PHASE_PS_STR_2), + .PLL_C_CNT_DUTY_CYCLE_2 (PLL_C_CNT_DUTY_CYCLE_2), + .PLL_C_CNT_FREQ_PS_STR_3 (PLL_C_CNT_FREQ_PS_STR_3), + .PLL_C_CNT_PHASE_PS_STR_3 (PLL_C_CNT_PHASE_PS_STR_3), + .PLL_C_CNT_DUTY_CYCLE_3 (PLL_C_CNT_DUTY_CYCLE_3), + .PLL_C_CNT_FREQ_PS_STR_4 (PLL_C_CNT_FREQ_PS_STR_4), + .PLL_C_CNT_PHASE_PS_STR_4 (PLL_C_CNT_PHASE_PS_STR_4), + .PLL_C_CNT_DUTY_CYCLE_4 (PLL_C_CNT_DUTY_CYCLE_4), + .PLL_C_CNT_FREQ_PS_STR_5 (PLL_C_CNT_FREQ_PS_STR_5), + .PLL_C_CNT_PHASE_PS_STR_5 (PLL_C_CNT_PHASE_PS_STR_5), + .PLL_C_CNT_DUTY_CYCLE_5 (PLL_C_CNT_DUTY_CYCLE_5), + .PLL_C_CNT_FREQ_PS_STR_6 (PLL_C_CNT_FREQ_PS_STR_6), + .PLL_C_CNT_PHASE_PS_STR_6 (PLL_C_CNT_PHASE_PS_STR_6), + .PLL_C_CNT_DUTY_CYCLE_6 (PLL_C_CNT_DUTY_CYCLE_6), + .PLL_C_CNT_FREQ_PS_STR_7 (PLL_C_CNT_FREQ_PS_STR_7), + .PLL_C_CNT_PHASE_PS_STR_7 (PLL_C_CNT_PHASE_PS_STR_7), + .PLL_C_CNT_DUTY_CYCLE_7 (PLL_C_CNT_DUTY_CYCLE_7), + .PLL_C_CNT_FREQ_PS_STR_8 (PLL_C_CNT_FREQ_PS_STR_8), + .PLL_C_CNT_PHASE_PS_STR_8 (PLL_C_CNT_PHASE_PS_STR_8), + .PLL_C_CNT_DUTY_CYCLE_8 (PLL_C_CNT_DUTY_CYCLE_8), + .PLL_C_CNT_OUT_EN_0 (PLL_C_CNT_OUT_EN_0), + .PLL_C_CNT_OUT_EN_1 (PLL_C_CNT_OUT_EN_1), + .PLL_C_CNT_OUT_EN_2 (PLL_C_CNT_OUT_EN_2), + .PLL_C_CNT_OUT_EN_3 (PLL_C_CNT_OUT_EN_3), + .PLL_C_CNT_OUT_EN_4 (PLL_C_CNT_OUT_EN_4), + .PLL_C_CNT_OUT_EN_5 (PLL_C_CNT_OUT_EN_5), + .PLL_C_CNT_OUT_EN_6 (PLL_C_CNT_OUT_EN_6), + .PLL_C_CNT_OUT_EN_7 (PLL_C_CNT_OUT_EN_7), + .PLL_C_CNT_OUT_EN_8 (PLL_C_CNT_OUT_EN_8), + .PLL_FBCLK_MUX_1 (PLL_FBCLK_MUX_1), + .PLL_FBCLK_MUX_2 (PLL_FBCLK_MUX_2), + .PLL_M_CNT_IN_SRC (PLL_M_CNT_IN_SRC), + .PLL_BW_SEL (PLL_BW_SEL) + ) pll_inst ( + .* + ); + // synthesis translate_off + end + // synthesis translate_on + endgenerate + + altera_emif_arch_nf_pll_extra_clks # ( + .PLL_NUM_OF_EXTRA_CLKS (PLL_NUM_OF_EXTRA_CLKS), + .DIAG_SIM_REGTEST_MODE (DIAG_SIM_REGTEST_MODE) + ) pll_extra_clks_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // OCT Block + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_oct # ( + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .PLL_REF_CLK_FREQ_PS (PLL_REF_CLK_FREQ_PS), + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .IS_HPS (IS_HPS) + ) oct_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Output clock and reset signals + //////////////////////////////////////////////////////////////////////////// + generate + if (IS_HPS) begin : hps + altera_emif_arch_nf_hps_clks_rsts # ( + .IS_VID (IS_VID), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_HPS_ENABLE_EARLY_RELEASE (PHY_HPS_ENABLE_EARLY_RELEASE) + ) hps_clks_rsts_inst ( + .* + ); + end else begin : non_hps + altera_emif_arch_nf_core_clks_rsts # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .PHY_CORE_CLKS_SHARING_ENUM (PHY_CORE_CLKS_SHARING_ENUM), + .IS_VID (IS_VID), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .USER_CLK_RATIO (USER_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PORT_CLKS_SHARING_MASTER_OUT_WIDTH (PORT_CLKS_SHARING_MASTER_OUT_WIDTH), + .PORT_CLKS_SHARING_SLAVE_IN_WIDTH (PORT_CLKS_SHARING_SLAVE_IN_WIDTH), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_USE_CPA_LOCK (DIAG_USE_CPA_LOCK), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH (PORT_DFT_NF_CORE_CLK_BUF_OUT_WIDTH), + .PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH (PORT_DFT_NF_CORE_CLK_LOCKED_WIDTH) + ) core_clks_rsts_inst ( + .* + ); + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // I/O Buffers + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_bufs # ( + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .MEM_FORMAT_ENUM (MEM_FORMAT_ENUM), + .PINS_PER_LANE (PINS_PER_LANE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .OCT_CONTROL_WIDTH (OCT_CONTROL_WIDTH), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .UNUSED_MEM_PINS_PINLOC (UNUSED_MEM_PINS_PINLOC), + .UNUSED_DQS_BUSES_LANELOC (UNUSED_DQS_BUSES_LANELOC), + + // Assignment of port widths for "mem" interface + //AUTOGEN_BEGIN: Assignment of memory port widths + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + + // Assignment of parameters describing logical pin allocation + //AUTOGEN_BEGIN: Assignment of memory port pinlocs + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + + .PHY_CALIBRATED_OCT (PHY_CALIBRATED_OCT), + .PHY_AC_CALIBRATED_OCT (PHY_AC_CALIBRATED_OCT), + .PHY_CK_CALIBRATED_OCT (PHY_CK_CALIBRATED_OCT), + .PHY_DATA_CALIBRATED_OCT (PHY_DATA_CALIBRATED_OCT) + ) bufs_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // I/O Aux + //////////////////////////////////////////////////////////////////////////// + ed_sim_emif_slave_1_altera_emif_arch_nf_170_oflfupa_io_aux # ( + .SILICON_REV (SILICON_REV), + .IS_HPS (IS_HPS), + .SEQ_CODE_HEX_FILENAME (SEQ_CODE_HEX_FILENAME), + .SEQ_SYNTH_OSC_FREQ_MHZ (SEQ_SYNTH_OSC_FREQ_MHZ), + .SEQ_SYNTH_PARAMS_HEX_FILENAME (SEQ_SYNTH_PARAMS_HEX_FILENAME), + .SEQ_SYNTH_CPU_CLK_DIVIDE (SEQ_SYNTH_CPU_CLK_DIVIDE), + .SEQ_SYNTH_CAL_CLK_DIVIDE (SEQ_SYNTH_CAL_CLK_DIVIDE), + .SEQ_SIM_OSC_FREQ_MHZ (SEQ_SIM_OSC_FREQ_MHZ), + .SEQ_SIM_PARAMS_HEX_FILENAME (SEQ_SIM_PARAMS_HEX_FILENAME), + .SEQ_SIM_CPU_CLK_DIVIDE (SEQ_SIM_CPU_CLK_DIVIDE), + .SEQ_SIM_CAL_CLK_DIVIDE (SEQ_SIM_CAL_CLK_DIVIDE), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_ECLIPSE_DEBUG (DIAG_ECLIPSE_DEBUG), + .DIAG_EXPORT_VJI (DIAG_EXPORT_VJI), + .DIAG_INTERFACE_ID (DIAG_INTERFACE_ID), + .PORT_CAL_DEBUG_ADDRESS_WIDTH (PORT_CAL_DEBUG_ADDRESS_WIDTH), + .PORT_CAL_DEBUG_BYTEEN_WIDTH (PORT_CAL_DEBUG_BYTEEN_WIDTH), + .PORT_CAL_DEBUG_RDATA_WIDTH (PORT_CAL_DEBUG_RDATA_WIDTH), + .PORT_CAL_DEBUG_WDATA_WIDTH (PORT_CAL_DEBUG_WDATA_WIDTH), + .PORT_CAL_MASTER_ADDRESS_WIDTH (PORT_CAL_MASTER_ADDRESS_WIDTH), + .PORT_CAL_MASTER_BYTEEN_WIDTH (PORT_CAL_MASTER_BYTEEN_WIDTH), + .PORT_CAL_MASTER_RDATA_WIDTH (PORT_CAL_MASTER_RDATA_WIDTH), + .PORT_CAL_MASTER_WDATA_WIDTH (PORT_CAL_MASTER_WDATA_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_IN_WIDTH (PORT_DFT_NF_IOAUX_PIO_IN_WIDTH), + .PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH (PORT_DFT_NF_IOAUX_PIO_OUT_WIDTH) + ) io_aux_inst ( + .global_reset_n_int (global_reset_n_int_io_aux_in), + .cal_debug_reset_n (cal_debug_reset_n_io_aux_in), + .cal_slave_reset_n_in (cal_slave_reset_n_in_io_aux_in), + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Tiles and Lanes + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_io_tiles_wrap # ( + .DIAG_VERBOSE_IOAUX (DIAG_VERBOSE_IOAUX), + .DIAG_SYNTH_FOR_SIM (DIAG_SYNTH_FOR_SIM), + .DIAG_CPA_OUT_1_EN (DIAG_CPA_OUT_1_EN), + .DIAG_FAST_SIM (DIAG_FAST_SIM), + .IS_HPS (IS_HPS), + .SILICON_REV (SILICON_REV), + .PROTOCOL_ENUM (PROTOCOL_ENUM), + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .DQS_BUS_MODE_ENUM (DQS_BUS_MODE_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO), + .C2P_P2C_CLK_RATIO (C2P_P2C_CLK_RATIO), + .PLL_VCO_FREQ_MHZ_INT (PLL_VCO_FREQ_MHZ_INT), + .PLL_VCO_TO_MEM_CLK_FREQ_RATIO (PLL_VCO_TO_MEM_CLK_FREQ_RATIO), + .MEM_BURST_LENGTH (MEM_BURST_LENGTH), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .HMC_CTRL_DIMM_TYPE (HMC_CTRL_DIMM_TYPE), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .PRI_HMC_CFG_REORDER_DATA (PRI_HMC_CFG_REORDER_DATA), + .PRI_HMC_CFG_REORDER_READ (PRI_HMC_CFG_REORDER_READ), + .PRI_HMC_CFG_REORDER_RDATA (PRI_HMC_CFG_REORDER_RDATA), + .PRI_HMC_CFG_STARVE_LIMIT (PRI_HMC_CFG_STARVE_LIMIT), + .PRI_HMC_CFG_DQS_TRACKING_EN (PRI_HMC_CFG_DQS_TRACKING_EN), + .PRI_HMC_CFG_ARBITER_TYPE (PRI_HMC_CFG_ARBITER_TYPE), + .PRI_HMC_CFG_OPEN_PAGE_EN (PRI_HMC_CFG_OPEN_PAGE_EN), + .PRI_HMC_CFG_GEAR_DOWN_EN (PRI_HMC_CFG_GEAR_DOWN_EN), + .PRI_HMC_CFG_RLD3_MULTIBANK_MODE (PRI_HMC_CFG_RLD3_MULTIBANK_MODE), + .PRI_HMC_CFG_PING_PONG_MODE (PRI_HMC_CFG_PING_PONG_MODE), + .PRI_HMC_CFG_SLOT_ROTATE_EN (PRI_HMC_CFG_SLOT_ROTATE_EN), + .PRI_HMC_CFG_SLOT_OFFSET (PRI_HMC_CFG_SLOT_OFFSET), + .PRI_HMC_CFG_COL_CMD_SLOT (PRI_HMC_CFG_COL_CMD_SLOT), + .PRI_HMC_CFG_ROW_CMD_SLOT (PRI_HMC_CFG_ROW_CMD_SLOT), + .PRI_HMC_CFG_ENABLE_RC (PRI_HMC_CFG_ENABLE_RC), + .PRI_HMC_CFG_CS_TO_CHIP_MAPPING (PRI_HMC_CFG_CS_TO_CHIP_MAPPING), + .PRI_HMC_CFG_RB_RESERVED_ENTRY (PRI_HMC_CFG_RB_RESERVED_ENTRY), + .PRI_HMC_CFG_WB_RESERVED_ENTRY (PRI_HMC_CFG_WB_RESERVED_ENTRY), + .PRI_HMC_CFG_TCL (PRI_HMC_CFG_TCL), + .PRI_HMC_CFG_POWER_SAVING_EXIT_CYC (PRI_HMC_CFG_POWER_SAVING_EXIT_CYC), + .PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .PRI_HMC_CFG_WRITE_ODT_CHIP (PRI_HMC_CFG_WRITE_ODT_CHIP), + .PRI_HMC_CFG_READ_ODT_CHIP (PRI_HMC_CFG_READ_ODT_CHIP), + .PRI_HMC_CFG_WR_ODT_ON (PRI_HMC_CFG_WR_ODT_ON), + .PRI_HMC_CFG_RD_ODT_ON (PRI_HMC_CFG_RD_ODT_ON), + .PRI_HMC_CFG_WR_ODT_PERIOD (PRI_HMC_CFG_WR_ODT_PERIOD), + .PRI_HMC_CFG_RD_ODT_PERIOD (PRI_HMC_CFG_RD_ODT_PERIOD), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ0 (PRI_HMC_CFG_RLD3_REFRESH_SEQ0), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ1 (PRI_HMC_CFG_RLD3_REFRESH_SEQ1), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ2 (PRI_HMC_CFG_RLD3_REFRESH_SEQ2), + .PRI_HMC_CFG_RLD3_REFRESH_SEQ3 (PRI_HMC_CFG_RLD3_REFRESH_SEQ3), + .PRI_HMC_CFG_SRF_ZQCAL_DISABLE (PRI_HMC_CFG_SRF_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_ZQCAL_DISABLE (PRI_HMC_CFG_MPS_ZQCAL_DISABLE), + .PRI_HMC_CFG_MPS_DQSTRK_DISABLE (PRI_HMC_CFG_MPS_DQSTRK_DISABLE), + .PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN (PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL (PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .PRI_HMC_CFG_DQSTRK_TO_VALID_LAST (PRI_HMC_CFG_DQSTRK_TO_VALID_LAST), + .PRI_HMC_CFG_DQSTRK_TO_VALID (PRI_HMC_CFG_DQSTRK_TO_VALID), + .PRI_HMC_CFG_RFSH_WARN_THRESHOLD (PRI_HMC_CFG_RFSH_WARN_THRESHOLD), + .PRI_HMC_CFG_SB_CG_DISABLE (PRI_HMC_CFG_SB_CG_DISABLE), + .PRI_HMC_CFG_USER_RFSH_EN (PRI_HMC_CFG_USER_RFSH_EN), + .PRI_HMC_CFG_SRF_AUTOEXIT_EN (PRI_HMC_CFG_SRF_AUTOEXIT_EN), + .PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .PRI_HMC_CFG_SB_DDR4_MR3 (PRI_HMC_CFG_SB_DDR4_MR3), + .PRI_HMC_CFG_SB_DDR4_MR4 (PRI_HMC_CFG_SB_DDR4_MR4), + .PRI_HMC_CFG_SB_DDR4_MR5 (PRI_HMC_CFG_SB_DDR4_MR5), + .PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR (PRI_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH (PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH (PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH (PRI_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .PRI_HMC_CFG_LOCAL_IF_CS_WIDTH (PRI_HMC_CFG_LOCAL_IF_CS_WIDTH), + .PRI_HMC_CFG_ADDR_ORDER (PRI_HMC_CFG_ADDR_ORDER), + .PRI_HMC_CFG_ACT_TO_RDWR (PRI_HMC_CFG_ACT_TO_RDWR), + .PRI_HMC_CFG_ACT_TO_PCH (PRI_HMC_CFG_ACT_TO_PCH), + .PRI_HMC_CFG_ACT_TO_ACT (PRI_HMC_CFG_ACT_TO_ACT), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG (PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .PRI_HMC_CFG_RD_TO_RD (PRI_HMC_CFG_RD_TO_RD), + .PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP (PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_RD_DIFF_BG (PRI_HMC_CFG_RD_TO_RD_DIFF_BG), + .PRI_HMC_CFG_RD_TO_WR (PRI_HMC_CFG_RD_TO_WR), + .PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP (PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_RD_TO_WR_DIFF_BG (PRI_HMC_CFG_RD_TO_WR_DIFF_BG), + .PRI_HMC_CFG_RD_TO_PCH (PRI_HMC_CFG_RD_TO_PCH), + .PRI_HMC_CFG_RD_AP_TO_VALID (PRI_HMC_CFG_RD_AP_TO_VALID), + .PRI_HMC_CFG_WR_TO_WR (PRI_HMC_CFG_WR_TO_WR), + .PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP (PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_WR_DIFF_BG (PRI_HMC_CFG_WR_TO_WR_DIFF_BG), + .PRI_HMC_CFG_WR_TO_RD (PRI_HMC_CFG_WR_TO_RD), + .PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP (PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .PRI_HMC_CFG_WR_TO_RD_DIFF_BG (PRI_HMC_CFG_WR_TO_RD_DIFF_BG), + .PRI_HMC_CFG_WR_TO_PCH (PRI_HMC_CFG_WR_TO_PCH), + .PRI_HMC_CFG_WR_AP_TO_VALID (PRI_HMC_CFG_WR_AP_TO_VALID), + .PRI_HMC_CFG_PCH_TO_VALID (PRI_HMC_CFG_PCH_TO_VALID), + .PRI_HMC_CFG_PCH_ALL_TO_VALID (PRI_HMC_CFG_PCH_ALL_TO_VALID), + .PRI_HMC_CFG_ARF_TO_VALID (PRI_HMC_CFG_ARF_TO_VALID), + .PRI_HMC_CFG_PDN_TO_VALID (PRI_HMC_CFG_PDN_TO_VALID), + .PRI_HMC_CFG_SRF_TO_VALID (PRI_HMC_CFG_SRF_TO_VALID), + .PRI_HMC_CFG_SRF_TO_ZQ_CAL (PRI_HMC_CFG_SRF_TO_ZQ_CAL), + .PRI_HMC_CFG_ARF_PERIOD (PRI_HMC_CFG_ARF_PERIOD), + .PRI_HMC_CFG_PDN_PERIOD (PRI_HMC_CFG_PDN_PERIOD), + .PRI_HMC_CFG_ZQCL_TO_VALID (PRI_HMC_CFG_ZQCL_TO_VALID), + .PRI_HMC_CFG_ZQCS_TO_VALID (PRI_HMC_CFG_ZQCS_TO_VALID), + .PRI_HMC_CFG_MRS_TO_VALID (PRI_HMC_CFG_MRS_TO_VALID), + .PRI_HMC_CFG_MPS_TO_VALID (PRI_HMC_CFG_MPS_TO_VALID), + .PRI_HMC_CFG_MRR_TO_VALID (PRI_HMC_CFG_MRR_TO_VALID), + .PRI_HMC_CFG_MPR_TO_VALID (PRI_HMC_CFG_MPR_TO_VALID), + .PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE (PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS (PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .PRI_HMC_CFG_MMR_CMD_TO_VALID (PRI_HMC_CFG_MMR_CMD_TO_VALID), + .PRI_HMC_CFG_4_ACT_TO_ACT (PRI_HMC_CFG_4_ACT_TO_ACT), + .PRI_HMC_CFG_16_ACT_TO_ACT (PRI_HMC_CFG_16_ACT_TO_ACT), + + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_REORDER_DATA (SEC_HMC_CFG_REORDER_DATA), + .SEC_HMC_CFG_REORDER_READ (SEC_HMC_CFG_REORDER_READ), + .SEC_HMC_CFG_REORDER_RDATA (SEC_HMC_CFG_REORDER_RDATA), + .SEC_HMC_CFG_STARVE_LIMIT (SEC_HMC_CFG_STARVE_LIMIT), + .SEC_HMC_CFG_DQS_TRACKING_EN (SEC_HMC_CFG_DQS_TRACKING_EN), + .SEC_HMC_CFG_ARBITER_TYPE (SEC_HMC_CFG_ARBITER_TYPE), + .SEC_HMC_CFG_OPEN_PAGE_EN (SEC_HMC_CFG_OPEN_PAGE_EN), + .SEC_HMC_CFG_GEAR_DOWN_EN (SEC_HMC_CFG_GEAR_DOWN_EN), + .SEC_HMC_CFG_RLD3_MULTIBANK_MODE (SEC_HMC_CFG_RLD3_MULTIBANK_MODE), + .SEC_HMC_CFG_PING_PONG_MODE (SEC_HMC_CFG_PING_PONG_MODE), + .SEC_HMC_CFG_SLOT_ROTATE_EN (SEC_HMC_CFG_SLOT_ROTATE_EN), + .SEC_HMC_CFG_SLOT_OFFSET (SEC_HMC_CFG_SLOT_OFFSET), + .SEC_HMC_CFG_COL_CMD_SLOT (SEC_HMC_CFG_COL_CMD_SLOT), + .SEC_HMC_CFG_ROW_CMD_SLOT (SEC_HMC_CFG_ROW_CMD_SLOT), + .SEC_HMC_CFG_ENABLE_RC (SEC_HMC_CFG_ENABLE_RC), + .SEC_HMC_CFG_CS_TO_CHIP_MAPPING (SEC_HMC_CFG_CS_TO_CHIP_MAPPING), + .SEC_HMC_CFG_RB_RESERVED_ENTRY (SEC_HMC_CFG_RB_RESERVED_ENTRY), + .SEC_HMC_CFG_WB_RESERVED_ENTRY (SEC_HMC_CFG_WB_RESERVED_ENTRY), + .SEC_HMC_CFG_TCL (SEC_HMC_CFG_TCL), + .SEC_HMC_CFG_POWER_SAVING_EXIT_CYC (SEC_HMC_CFG_POWER_SAVING_EXIT_CYC), + .SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC(SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC), + .SEC_HMC_CFG_WRITE_ODT_CHIP (SEC_HMC_CFG_WRITE_ODT_CHIP), + .SEC_HMC_CFG_READ_ODT_CHIP (SEC_HMC_CFG_READ_ODT_CHIP), + .SEC_HMC_CFG_WR_ODT_ON (SEC_HMC_CFG_WR_ODT_ON), + .SEC_HMC_CFG_RD_ODT_ON (SEC_HMC_CFG_RD_ODT_ON), + .SEC_HMC_CFG_WR_ODT_PERIOD (SEC_HMC_CFG_WR_ODT_PERIOD), + .SEC_HMC_CFG_RD_ODT_PERIOD (SEC_HMC_CFG_RD_ODT_PERIOD), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ0 (SEC_HMC_CFG_RLD3_REFRESH_SEQ0), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ1 (SEC_HMC_CFG_RLD3_REFRESH_SEQ1), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ2 (SEC_HMC_CFG_RLD3_REFRESH_SEQ2), + .SEC_HMC_CFG_RLD3_REFRESH_SEQ3 (SEC_HMC_CFG_RLD3_REFRESH_SEQ3), + .SEC_HMC_CFG_SRF_ZQCAL_DISABLE (SEC_HMC_CFG_SRF_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_ZQCAL_DISABLE (SEC_HMC_CFG_MPS_ZQCAL_DISABLE), + .SEC_HMC_CFG_MPS_DQSTRK_DISABLE (SEC_HMC_CFG_MPS_DQSTRK_DISABLE), + .SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN (SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN (SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN), + .SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL (SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL), + .SEC_HMC_CFG_DQSTRK_TO_VALID_LAST (SEC_HMC_CFG_DQSTRK_TO_VALID_LAST), + .SEC_HMC_CFG_DQSTRK_TO_VALID (SEC_HMC_CFG_DQSTRK_TO_VALID), + .SEC_HMC_CFG_RFSH_WARN_THRESHOLD (SEC_HMC_CFG_RFSH_WARN_THRESHOLD), + .SEC_HMC_CFG_SB_CG_DISABLE (SEC_HMC_CFG_SB_CG_DISABLE), + .SEC_HMC_CFG_USER_RFSH_EN (SEC_HMC_CFG_USER_RFSH_EN), + .SEC_HMC_CFG_SRF_AUTOEXIT_EN (SEC_HMC_CFG_SRF_AUTOEXIT_EN), + .SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK (SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK), + .SEC_HMC_CFG_SB_DDR4_MR3 (SEC_HMC_CFG_SB_DDR4_MR3), + .SEC_HMC_CFG_SB_DDR4_MR4 (SEC_HMC_CFG_SB_DDR4_MR4), + .SEC_HMC_CFG_SB_DDR4_MR5 (SEC_HMC_CFG_SB_DDR4_MR5), + .SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR (SEC_HMC_CFG_DDR4_MPS_ADDR_MIRROR), + .SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH (SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH (SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BANKADDR_WIDTH), + .SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH (SEC_HMC_CFG_MEM_IF_BGADDR_WIDTH), + .SEC_HMC_CFG_LOCAL_IF_CS_WIDTH (SEC_HMC_CFG_LOCAL_IF_CS_WIDTH), + .SEC_HMC_CFG_ADDR_ORDER (SEC_HMC_CFG_ADDR_ORDER), + .SEC_HMC_CFG_ACT_TO_RDWR (SEC_HMC_CFG_ACT_TO_RDWR), + .SEC_HMC_CFG_ACT_TO_PCH (SEC_HMC_CFG_ACT_TO_PCH), + .SEC_HMC_CFG_ACT_TO_ACT (SEC_HMC_CFG_ACT_TO_ACT), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK), + .SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG (SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG), + .SEC_HMC_CFG_RD_TO_RD (SEC_HMC_CFG_RD_TO_RD), + .SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP (SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_RD_DIFF_BG (SEC_HMC_CFG_RD_TO_RD_DIFF_BG), + .SEC_HMC_CFG_RD_TO_WR (SEC_HMC_CFG_RD_TO_WR), + .SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP (SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_RD_TO_WR_DIFF_BG (SEC_HMC_CFG_RD_TO_WR_DIFF_BG), + .SEC_HMC_CFG_RD_TO_PCH (SEC_HMC_CFG_RD_TO_PCH), + .SEC_HMC_CFG_RD_AP_TO_VALID (SEC_HMC_CFG_RD_AP_TO_VALID), + .SEC_HMC_CFG_WR_TO_WR (SEC_HMC_CFG_WR_TO_WR), + .SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP (SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_WR_DIFF_BG (SEC_HMC_CFG_WR_TO_WR_DIFF_BG), + .SEC_HMC_CFG_WR_TO_RD (SEC_HMC_CFG_WR_TO_RD), + .SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP (SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP), + .SEC_HMC_CFG_WR_TO_RD_DIFF_BG (SEC_HMC_CFG_WR_TO_RD_DIFF_BG), + .SEC_HMC_CFG_WR_TO_PCH (SEC_HMC_CFG_WR_TO_PCH), + .SEC_HMC_CFG_WR_AP_TO_VALID (SEC_HMC_CFG_WR_AP_TO_VALID), + .SEC_HMC_CFG_PCH_TO_VALID (SEC_HMC_CFG_PCH_TO_VALID), + .SEC_HMC_CFG_PCH_ALL_TO_VALID (SEC_HMC_CFG_PCH_ALL_TO_VALID), + .SEC_HMC_CFG_ARF_TO_VALID (SEC_HMC_CFG_ARF_TO_VALID), + .SEC_HMC_CFG_PDN_TO_VALID (SEC_HMC_CFG_PDN_TO_VALID), + .SEC_HMC_CFG_SRF_TO_VALID (SEC_HMC_CFG_SRF_TO_VALID), + .SEC_HMC_CFG_SRF_TO_ZQ_CAL (SEC_HMC_CFG_SRF_TO_ZQ_CAL), + .SEC_HMC_CFG_ARF_PERIOD (SEC_HMC_CFG_ARF_PERIOD), + .SEC_HMC_CFG_PDN_PERIOD (SEC_HMC_CFG_PDN_PERIOD), + .SEC_HMC_CFG_ZQCL_TO_VALID (SEC_HMC_CFG_ZQCL_TO_VALID), + .SEC_HMC_CFG_ZQCS_TO_VALID (SEC_HMC_CFG_ZQCS_TO_VALID), + .SEC_HMC_CFG_MRS_TO_VALID (SEC_HMC_CFG_MRS_TO_VALID), + .SEC_HMC_CFG_MPS_TO_VALID (SEC_HMC_CFG_MPS_TO_VALID), + .SEC_HMC_CFG_MRR_TO_VALID (SEC_HMC_CFG_MRR_TO_VALID), + .SEC_HMC_CFG_MPR_TO_VALID (SEC_HMC_CFG_MPR_TO_VALID), + .SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE (SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE), + .SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS (SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS), + .SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY (SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY), + .SEC_HMC_CFG_MMR_CMD_TO_VALID (SEC_HMC_CFG_MMR_CMD_TO_VALID), + .SEC_HMC_CFG_4_ACT_TO_ACT (SEC_HMC_CFG_4_ACT_TO_ACT), + .SEC_HMC_CFG_16_ACT_TO_ACT (SEC_HMC_CFG_16_ACT_TO_ACT), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .PINS_IN_RTL_TILES (PINS_IN_RTL_TILES), + .LANES_IN_RTL_TILES (LANES_IN_RTL_TILES), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .AC_PIN_MAP_SCHEME (AC_PIN_MAP_SCHEME), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .LANES_USAGE (LANES_USAGE), + .PINS_USAGE (PINS_USAGE), + .PINS_RATE (PINS_RATE), + .PINS_WDB (PINS_WDB), + .PINS_DB_IN_BYPASS (PINS_DB_IN_BYPASS), + .PINS_DB_OUT_BYPASS (PINS_DB_OUT_BYPASS), + .PINS_DB_OE_BYPASS (PINS_DB_OE_BYPASS), + .PINS_INVERT_WR (PINS_INVERT_WR), + .PINS_INVERT_OE (PINS_INVERT_OE), + .PINS_AC_HMC_DATA_OVERRIDE_ENA (PINS_AC_HMC_DATA_OVERRIDE_ENA), + .PINS_DATA_IN_MODE (PINS_DATA_IN_MODE), + .PINS_OCT_MODE (PINS_OCT_MODE), + .PINS_GPIO_MODE (PINS_GPIO_MODE), + .CENTER_TIDS (CENTER_TIDS), + .HMC_TIDS (HMC_TIDS), + .LANE_TIDS (LANE_TIDS), + .PREAMBLE_MODE (PREAMBLE_MODE), + .DBI_WR_ENABLE (DBI_WR_ENABLE), + .DBI_RD_ENABLE (DBI_RD_ENABLE), + .CRC_EN (CRC_EN), + .SWAP_DQS_A_B (SWAP_DQS_A_B), + .DQS_PACK_MODE (DQS_PACK_MODE), + .OCT_SIZE (OCT_SIZE), + .DBC_WB_RESERVED_ENTRY (DBC_WB_RESERVED_ENTRY), + .DLL_MODE (DLL_MODE), + .DLL_CODEWORD (DLL_CODEWORD), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH (PORT_DFT_NF_PA_DPRIO_REG_ADDR_WIDTH), + .PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_WRITEDATA_WIDTH), + .PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH (PORT_DFT_NF_PA_DPRIO_READDATA_WIDTH), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .DIAG_USE_ABSTRACT_PHY (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD), + .DIAG_ABSTRACT_PHY_WLAT (DIAG_ABSTRACT_PHY_WLAT), + .DIAG_ABSTRACT_PHY_RLAT (DIAG_ABSTRACT_PHY_RLAT), + .ABPHY_WRITE_PROTOCOL (ABPHY_WRITE_PROTOCOL) + ) io_tiles_wrap_inst ( + .l2core_data (l2core_data), + .runAbstractPhySim (runAbstractPhySim), + .* + ); + + generate + if (DIAG_USE_ABSTRACT_PHY_AFT_SYNTH_OVRD == 0) + begin : nonabphy_connections + assign global_reset_n_int_io_aux_in = global_reset_n_int; + assign cal_debug_reset_n_io_aux_in = cal_debug_reset_n; + assign cal_slave_reset_n_in_io_aux_in = cal_slave_reset_n_in; + end + else begin : abphy_connections + assign global_reset_n_int_io_aux_in = runAbstractPhySim==0 ? global_reset_n_int : 'b0; + assign cal_debug_reset_n_io_aux_in = runAbstractPhySim==0 ? cal_debug_reset_n : 'b0; + assign cal_slave_reset_n_in_io_aux_in = runAbstractPhySim==0 ? cal_slave_reset_n_in : 'b0; + end + endgenerate + + //////////////////////////////////////////////////////////////////////////// + // Expose sequencer interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_seq_if # ( + .PHY_CONFIG_ENUM (PHY_CONFIG_ENUM), + .USER_CLK_RATIO (USER_CLK_RATIO), + .REGISTER_AFI (REGISTER_AFI), + .PORT_AFI_RLAT_WIDTH (PORT_AFI_RLAT_WIDTH), + .PORT_AFI_WLAT_WIDTH (PORT_AFI_WLAT_WIDTH), + .PORT_AFI_SEQ_BUSY_WIDTH (PORT_AFI_SEQ_BUSY_WIDTH), + .PORT_HPS_EMIF_E2H_GP_WIDTH (PORT_HPS_EMIF_E2H_GP_WIDTH), + .PORT_HPS_EMIF_H2E_GP_WIDTH (PORT_HPS_EMIF_H2E_GP_WIDTH), + .PHY_USERMODE_OCT (PHY_USERMODE_OCT), + .PHY_PERIODIC_OCT_RECAL (PHY_PERIODIC_OCT_RECAL), + .PHY_HAS_DCC (PHY_HAS_DCC), + .IS_HPS (IS_HPS) + ) seq_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC signals from io_tiles as proper Avalon signals + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_avl_if # ( + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .HMC_AVL_PROTOCOL_ENUM (HMC_AVL_PROTOCOL_ENUM), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PORT_CTRL_AST_CMD_DATA_WIDTH (PORT_CTRL_AST_CMD_DATA_WIDTH), + .PORT_CTRL_AMM_ADDRESS_WIDTH (PORT_CTRL_AMM_ADDRESS_WIDTH), + .PORT_CTRL_AMM_BCOUNT_WIDTH (PORT_CTRL_AMM_BCOUNT_WIDTH) + ) hmc_avl_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC sideband interfaces + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_sideband_if # ( + .PHY_PING_PONG_EN (PHY_PING_PONG_EN), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .PRI_AC_TILE_INDEX (PRI_AC_TILE_INDEX), + .SEC_AC_TILE_INDEX (SEC_AC_TILE_INDEX), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PRI_HMC_DBC_SHADOW_LANE_INDEX (PRI_HMC_DBC_SHADOW_LANE_INDEX), + .PRI_HMC_CFG_ENABLE_ECC (PRI_HMC_CFG_ENABLE_ECC), + .SEC_HMC_CFG_ENABLE_ECC (SEC_HMC_CFG_ENABLE_ECC), + .PORT_CTRL_USER_REFRESH_REQ_WIDTH (PORT_CTRL_USER_REFRESH_REQ_WIDTH), + .PORT_CTRL_USER_REFRESH_BANK_WIDTH (PORT_CTRL_USER_REFRESH_BANK_WIDTH), + .PORT_CTRL_SELF_REFRESH_REQ_WIDTH (PORT_CTRL_SELF_REFRESH_REQ_WIDTH), + .PORT_CTRL_ECC_WRITE_INFO_WIDTH (PORT_CTRL_ECC_WRITE_INFO_WIDTH), + .PORT_CTRL_ECC_READ_INFO_WIDTH (PORT_CTRL_ECC_READ_INFO_WIDTH), + .PORT_CTRL_ECC_CMD_INFO_WIDTH (PORT_CTRL_ECC_CMD_INFO_WIDTH), + .PORT_CTRL_ECC_WB_POINTER_WIDTH (PORT_CTRL_ECC_WB_POINTER_WIDTH), + .PORT_CTRL_ECC_RDATA_ID_WIDTH (PORT_CTRL_ECC_RDATA_ID_WIDTH) + ) hmc_sideband_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Expose HMC MMR interface + //////////////////////////////////////////////////////////////////////////// + altera_emif_arch_nf_hmc_mmr_if # ( + .PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH (PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH), + .PORT_CTRL_MMR_SLAVE_RDATA_WIDTH (PORT_CTRL_MMR_SLAVE_RDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_WDATA_WIDTH (PORT_CTRL_MMR_SLAVE_WDATA_WIDTH), + .PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH (PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH) + ) hmc_mmr_if_inst ( + .* + ); + + //////////////////////////////////////////////////////////////////////////// + // Rewire and expose data signals + //////////////////////////////////////////////////////////////////////////// + generate + if (NUM_OF_HMC_PORTS == 0) + begin : afi + altera_emif_arch_nf_afi_if # ( + .MEM_TTL_DATA_WIDTH (MEM_TTL_DATA_WIDTH), + .MEM_TTL_NUM_OF_READ_GROUPS (MEM_TTL_NUM_OF_READ_GROUPS), + .MEM_TTL_NUM_OF_WRITE_GROUPS (MEM_TTL_NUM_OF_WRITE_GROUPS), + .REGISTER_AFI (REGISTER_AFI), + + .PORT_AFI_ADDR_WIDTH (PORT_AFI_ADDR_WIDTH), + .PORT_AFI_BA_WIDTH (PORT_AFI_BA_WIDTH), + .PORT_AFI_BG_WIDTH (PORT_AFI_BG_WIDTH), + .PORT_AFI_C_WIDTH (PORT_AFI_C_WIDTH), + .PORT_AFI_CKE_WIDTH (PORT_AFI_CKE_WIDTH), + .PORT_AFI_CS_N_WIDTH (PORT_AFI_CS_N_WIDTH), + .PORT_AFI_RM_WIDTH (PORT_AFI_RM_WIDTH), + .PORT_AFI_ODT_WIDTH (PORT_AFI_ODT_WIDTH), + .PORT_AFI_RAS_N_WIDTH (PORT_AFI_RAS_N_WIDTH), + .PORT_AFI_CAS_N_WIDTH (PORT_AFI_CAS_N_WIDTH), + .PORT_AFI_WE_N_WIDTH (PORT_AFI_WE_N_WIDTH), + .PORT_AFI_RST_N_WIDTH (PORT_AFI_RST_N_WIDTH), + .PORT_AFI_ACT_N_WIDTH (PORT_AFI_ACT_N_WIDTH), + .PORT_AFI_PAR_WIDTH (PORT_AFI_PAR_WIDTH), + .PORT_AFI_CA_WIDTH (PORT_AFI_CA_WIDTH), + .PORT_AFI_REF_N_WIDTH (PORT_AFI_REF_N_WIDTH), + .PORT_AFI_WPS_N_WIDTH (PORT_AFI_WPS_N_WIDTH), + .PORT_AFI_RPS_N_WIDTH (PORT_AFI_RPS_N_WIDTH), + .PORT_AFI_DOFF_N_WIDTH (PORT_AFI_DOFF_N_WIDTH), + .PORT_AFI_LD_N_WIDTH (PORT_AFI_LD_N_WIDTH), + .PORT_AFI_RW_N_WIDTH (PORT_AFI_RW_N_WIDTH), + .PORT_AFI_LBK0_N_WIDTH (PORT_AFI_LBK0_N_WIDTH), + .PORT_AFI_LBK1_N_WIDTH (PORT_AFI_LBK1_N_WIDTH), + .PORT_AFI_CFG_N_WIDTH (PORT_AFI_CFG_N_WIDTH), + .PORT_AFI_AP_WIDTH (PORT_AFI_AP_WIDTH), + .PORT_AFI_AINV_WIDTH (PORT_AFI_AINV_WIDTH), + .PORT_AFI_DM_WIDTH (PORT_AFI_DM_WIDTH), + .PORT_AFI_DM_N_WIDTH (PORT_AFI_DM_N_WIDTH), + .PORT_AFI_BWS_N_WIDTH (PORT_AFI_BWS_N_WIDTH), + .PORT_AFI_RDATA_DBI_N_WIDTH (PORT_AFI_RDATA_DBI_N_WIDTH), + .PORT_AFI_WDATA_DBI_N_WIDTH (PORT_AFI_WDATA_DBI_N_WIDTH), + .PORT_AFI_RDATA_DINV_WIDTH (PORT_AFI_RDATA_DINV_WIDTH), + .PORT_AFI_WDATA_DINV_WIDTH (PORT_AFI_WDATA_DINV_WIDTH), + .PORT_AFI_DQS_BURST_WIDTH (PORT_AFI_DQS_BURST_WIDTH), + .PORT_AFI_WDATA_VALID_WIDTH (PORT_AFI_WDATA_VALID_WIDTH), + .PORT_AFI_WDATA_WIDTH (PORT_AFI_WDATA_WIDTH), + .PORT_AFI_RDATA_EN_FULL_WIDTH (PORT_AFI_RDATA_EN_FULL_WIDTH), + .PORT_AFI_RDATA_WIDTH (PORT_AFI_RDATA_WIDTH), + .PORT_AFI_RDATA_VALID_WIDTH (PORT_AFI_RDATA_VALID_WIDTH), + .PORT_AFI_RRANK_WIDTH (PORT_AFI_RRANK_WIDTH), + .PORT_AFI_WRANK_WIDTH (PORT_AFI_WRANK_WIDTH), + .PORT_AFI_ALERT_N_WIDTH (PORT_AFI_ALERT_N_WIDTH), + .PORT_AFI_PE_N_WIDTH (PORT_AFI_PE_N_WIDTH), + .PORT_MEM_CK_WIDTH (PORT_MEM_CK_WIDTH), + .PORT_MEM_CK_N_WIDTH (PORT_MEM_CK_N_WIDTH), + .PORT_MEM_DK_WIDTH (PORT_MEM_DK_WIDTH), + .PORT_MEM_DK_N_WIDTH (PORT_MEM_DK_N_WIDTH), + .PORT_MEM_DKA_WIDTH (PORT_MEM_DKA_WIDTH), + .PORT_MEM_DKA_N_WIDTH (PORT_MEM_DKA_N_WIDTH), + .PORT_MEM_DKB_WIDTH (PORT_MEM_DKB_WIDTH), + .PORT_MEM_DKB_N_WIDTH (PORT_MEM_DKB_N_WIDTH), + .PORT_MEM_K_WIDTH (PORT_MEM_K_WIDTH), + .PORT_MEM_K_N_WIDTH (PORT_MEM_K_N_WIDTH), + .PORT_MEM_A_WIDTH (PORT_MEM_A_WIDTH), + .PORT_MEM_BA_WIDTH (PORT_MEM_BA_WIDTH), + .PORT_MEM_BG_WIDTH (PORT_MEM_BG_WIDTH), + .PORT_MEM_C_WIDTH (PORT_MEM_C_WIDTH), + .PORT_MEM_CKE_WIDTH (PORT_MEM_CKE_WIDTH), + .PORT_MEM_CS_N_WIDTH (PORT_MEM_CS_N_WIDTH), + .PORT_MEM_RM_WIDTH (PORT_MEM_RM_WIDTH), + .PORT_MEM_ODT_WIDTH (PORT_MEM_ODT_WIDTH), + .PORT_MEM_RAS_N_WIDTH (PORT_MEM_RAS_N_WIDTH), + .PORT_MEM_CAS_N_WIDTH (PORT_MEM_CAS_N_WIDTH), + .PORT_MEM_WE_N_WIDTH (PORT_MEM_WE_N_WIDTH), + .PORT_MEM_RESET_N_WIDTH (PORT_MEM_RESET_N_WIDTH), + .PORT_MEM_ACT_N_WIDTH (PORT_MEM_ACT_N_WIDTH), + .PORT_MEM_PAR_WIDTH (PORT_MEM_PAR_WIDTH), + .PORT_MEM_CA_WIDTH (PORT_MEM_CA_WIDTH), + .PORT_MEM_REF_N_WIDTH (PORT_MEM_REF_N_WIDTH), + .PORT_MEM_WPS_N_WIDTH (PORT_MEM_WPS_N_WIDTH), + .PORT_MEM_RPS_N_WIDTH (PORT_MEM_RPS_N_WIDTH), + .PORT_MEM_DOFF_N_WIDTH (PORT_MEM_DOFF_N_WIDTH), + .PORT_MEM_LDA_N_WIDTH (PORT_MEM_LDA_N_WIDTH), + .PORT_MEM_LDB_N_WIDTH (PORT_MEM_LDB_N_WIDTH), + .PORT_MEM_RWA_N_WIDTH (PORT_MEM_RWA_N_WIDTH), + .PORT_MEM_RWB_N_WIDTH (PORT_MEM_RWB_N_WIDTH), + .PORT_MEM_LBK0_N_WIDTH (PORT_MEM_LBK0_N_WIDTH), + .PORT_MEM_LBK1_N_WIDTH (PORT_MEM_LBK1_N_WIDTH), + .PORT_MEM_CFG_N_WIDTH (PORT_MEM_CFG_N_WIDTH), + .PORT_MEM_AP_WIDTH (PORT_MEM_AP_WIDTH), + .PORT_MEM_AINV_WIDTH (PORT_MEM_AINV_WIDTH), + .PORT_MEM_DM_WIDTH (PORT_MEM_DM_WIDTH), + .PORT_MEM_BWS_N_WIDTH (PORT_MEM_BWS_N_WIDTH), + .PORT_MEM_D_WIDTH (PORT_MEM_D_WIDTH), + .PORT_MEM_DQ_WIDTH (PORT_MEM_DQ_WIDTH), + .PORT_MEM_DBI_N_WIDTH (PORT_MEM_DBI_N_WIDTH), + .PORT_MEM_DQA_WIDTH (PORT_MEM_DQA_WIDTH), + .PORT_MEM_DQB_WIDTH (PORT_MEM_DQB_WIDTH), + .PORT_MEM_DINVA_WIDTH (PORT_MEM_DINVA_WIDTH), + .PORT_MEM_DINVB_WIDTH (PORT_MEM_DINVB_WIDTH), + .PORT_MEM_Q_WIDTH (PORT_MEM_Q_WIDTH), + .PORT_MEM_DQS_WIDTH (PORT_MEM_DQS_WIDTH), + .PORT_MEM_DQS_N_WIDTH (PORT_MEM_DQS_N_WIDTH), + .PORT_MEM_QK_WIDTH (PORT_MEM_QK_WIDTH), + .PORT_MEM_QK_N_WIDTH (PORT_MEM_QK_N_WIDTH), + .PORT_MEM_QKA_WIDTH (PORT_MEM_QKA_WIDTH), + .PORT_MEM_QKA_N_WIDTH (PORT_MEM_QKA_N_WIDTH), + .PORT_MEM_QKB_WIDTH (PORT_MEM_QKB_WIDTH), + .PORT_MEM_QKB_N_WIDTH (PORT_MEM_QKB_N_WIDTH), + .PORT_MEM_CQ_WIDTH (PORT_MEM_CQ_WIDTH), + .PORT_MEM_CQ_N_WIDTH (PORT_MEM_CQ_N_WIDTH), + .PORT_MEM_ALERT_N_WIDTH (PORT_MEM_ALERT_N_WIDTH), + .PORT_MEM_PE_N_WIDTH (PORT_MEM_PE_N_WIDTH), + .PORT_MEM_CK_PINLOC (PORT_MEM_CK_PINLOC), + .PORT_MEM_CK_N_PINLOC (PORT_MEM_CK_N_PINLOC), + .PORT_MEM_DK_PINLOC (PORT_MEM_DK_PINLOC), + .PORT_MEM_DK_N_PINLOC (PORT_MEM_DK_N_PINLOC), + .PORT_MEM_DKA_PINLOC (PORT_MEM_DKA_PINLOC), + .PORT_MEM_DKA_N_PINLOC (PORT_MEM_DKA_N_PINLOC), + .PORT_MEM_DKB_PINLOC (PORT_MEM_DKB_PINLOC), + .PORT_MEM_DKB_N_PINLOC (PORT_MEM_DKB_N_PINLOC), + .PORT_MEM_K_PINLOC (PORT_MEM_K_PINLOC), + .PORT_MEM_K_N_PINLOC (PORT_MEM_K_N_PINLOC), + .PORT_MEM_A_PINLOC (PORT_MEM_A_PINLOC), + .PORT_MEM_BA_PINLOC (PORT_MEM_BA_PINLOC), + .PORT_MEM_BG_PINLOC (PORT_MEM_BG_PINLOC), + .PORT_MEM_C_PINLOC (PORT_MEM_C_PINLOC), + .PORT_MEM_CKE_PINLOC (PORT_MEM_CKE_PINLOC), + .PORT_MEM_CS_N_PINLOC (PORT_MEM_CS_N_PINLOC), + .PORT_MEM_RM_PINLOC (PORT_MEM_RM_PINLOC), + .PORT_MEM_ODT_PINLOC (PORT_MEM_ODT_PINLOC), + .PORT_MEM_RAS_N_PINLOC (PORT_MEM_RAS_N_PINLOC), + .PORT_MEM_CAS_N_PINLOC (PORT_MEM_CAS_N_PINLOC), + .PORT_MEM_WE_N_PINLOC (PORT_MEM_WE_N_PINLOC), + .PORT_MEM_RESET_N_PINLOC (PORT_MEM_RESET_N_PINLOC), + .PORT_MEM_ACT_N_PINLOC (PORT_MEM_ACT_N_PINLOC), + .PORT_MEM_PAR_PINLOC (PORT_MEM_PAR_PINLOC), + .PORT_MEM_CA_PINLOC (PORT_MEM_CA_PINLOC), + .PORT_MEM_REF_N_PINLOC (PORT_MEM_REF_N_PINLOC), + .PORT_MEM_WPS_N_PINLOC (PORT_MEM_WPS_N_PINLOC), + .PORT_MEM_RPS_N_PINLOC (PORT_MEM_RPS_N_PINLOC), + .PORT_MEM_DOFF_N_PINLOC (PORT_MEM_DOFF_N_PINLOC), + .PORT_MEM_LDA_N_PINLOC (PORT_MEM_LDA_N_PINLOC), + .PORT_MEM_LDB_N_PINLOC (PORT_MEM_LDB_N_PINLOC), + .PORT_MEM_RWA_N_PINLOC (PORT_MEM_RWA_N_PINLOC), + .PORT_MEM_RWB_N_PINLOC (PORT_MEM_RWB_N_PINLOC), + .PORT_MEM_LBK0_N_PINLOC (PORT_MEM_LBK0_N_PINLOC), + .PORT_MEM_LBK1_N_PINLOC (PORT_MEM_LBK1_N_PINLOC), + .PORT_MEM_CFG_N_PINLOC (PORT_MEM_CFG_N_PINLOC), + .PORT_MEM_AP_PINLOC (PORT_MEM_AP_PINLOC), + .PORT_MEM_AINV_PINLOC (PORT_MEM_AINV_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_DQA_PINLOC (PORT_MEM_DQA_PINLOC), + .PORT_MEM_DQB_PINLOC (PORT_MEM_DQB_PINLOC), + .PORT_MEM_DINVA_PINLOC (PORT_MEM_DINVA_PINLOC), + .PORT_MEM_DINVB_PINLOC (PORT_MEM_DINVB_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DQS_PINLOC (PORT_MEM_DQS_PINLOC), + .PORT_MEM_DQS_N_PINLOC (PORT_MEM_DQS_N_PINLOC), + .PORT_MEM_QK_PINLOC (PORT_MEM_QK_PINLOC), + .PORT_MEM_QK_N_PINLOC (PORT_MEM_QK_N_PINLOC), + .PORT_MEM_QKA_PINLOC (PORT_MEM_QKA_PINLOC), + .PORT_MEM_QKA_N_PINLOC (PORT_MEM_QKA_N_PINLOC), + .PORT_MEM_QKB_PINLOC (PORT_MEM_QKB_PINLOC), + .PORT_MEM_QKB_N_PINLOC (PORT_MEM_QKB_N_PINLOC), + .PORT_MEM_CQ_PINLOC (PORT_MEM_CQ_PINLOC), + .PORT_MEM_CQ_N_PINLOC (PORT_MEM_CQ_N_PINLOC), + .PORT_MEM_ALERT_N_PINLOC (PORT_MEM_ALERT_N_PINLOC), + .PORT_MEM_PE_N_PINLOC (PORT_MEM_PE_N_PINLOC), + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .LANES_USAGE (LANES_USAGE), + .PRI_RDATA_TILE_INDEX (PRI_RDATA_TILE_INDEX), + .PRI_RDATA_LANE_INDEX (PRI_RDATA_LANE_INDEX), + .PRI_WDATA_TILE_INDEX (PRI_WDATA_TILE_INDEX), + .PRI_WDATA_LANE_INDEX (PRI_WDATA_LANE_INDEX), + .SEC_RDATA_TILE_INDEX (SEC_RDATA_TILE_INDEX), + .SEC_RDATA_LANE_INDEX (SEC_RDATA_LANE_INDEX), + .SEC_WDATA_TILE_INDEX (SEC_WDATA_TILE_INDEX), + .SEC_WDATA_LANE_INDEX (SEC_WDATA_LANE_INDEX), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN), + .PINS_INVERT_OE (PINS_INVERT_OE), + .MEM_DATA_MASK_EN (MEM_DATA_MASK_EN), + .PHY_HMC_CLK_RATIO (PHY_HMC_CLK_RATIO) + ) if_inst ( + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + + end else + begin : hmc + if (HMC_AVL_PROTOCOL_ENUM == "CTRL_AVL_PROTOCOL_MM") + begin : amm + + altera_emif_arch_nf_hmc_amm_data_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AMM_RDATA_WIDTH (PORT_CTRL_AMM_RDATA_WIDTH), + .PORT_CTRL_AMM_WDATA_WIDTH (PORT_CTRL_AMM_WDATA_WIDTH), + .PORT_CTRL_AMM_BYTEEN_WIDTH (PORT_CTRL_AMM_BYTEEN_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .* + ); + + assign ast_rd_data_0 = '0; + assign ast_rd_data_1 = '0; + end else + begin : hmc_ast + altera_emif_arch_nf_hmc_ast_data_if # ( + .PINS_PER_LANE (PINS_PER_LANE), + .LANES_PER_TILE (LANES_PER_TILE), + .NUM_OF_RTL_TILES (NUM_OF_RTL_TILES), + .NUM_OF_HMC_PORTS (NUM_OF_HMC_PORTS), + .PORT_CTRL_AST_WR_DATA_WIDTH (PORT_CTRL_AST_WR_DATA_WIDTH), + .PORT_CTRL_AST_RD_DATA_WIDTH (PORT_CTRL_AST_RD_DATA_WIDTH), + .PORT_MEM_D_PINLOC (PORT_MEM_D_PINLOC), + .PORT_MEM_DQ_PINLOC (PORT_MEM_DQ_PINLOC), + .PORT_MEM_Q_PINLOC (PORT_MEM_Q_PINLOC), + .PORT_MEM_DM_PINLOC (PORT_MEM_DM_PINLOC), + .PORT_MEM_DBI_N_PINLOC (PORT_MEM_DBI_N_PINLOC), + .PORT_MEM_BWS_N_PINLOC (PORT_MEM_BWS_N_PINLOC), + .PINS_C2L_DRIVEN (PINS_C2L_DRIVEN) + ) data_if_inst ( + .* + ); + + assign amm_readdata_0 = '0; + assign amm_readdata_1 = '0; + end + + assign afi_rdata_dbi_n = '0; + assign afi_rdata_dinv = '0; + assign afi_rdata = '0; + assign afi_rdata_valid = '0; + assign afi_alert_n = '0; + assign afi_pe_n = '0; + assign core2l_rdata_en_full = '0; + assign core2l_mrnk_read = '0; + assign core2l_mrnk_write = '0; + end + endgenerate + + altera_emif_arch_nf_cal_counter + cal_counter_inst ( + .* + ); + + assign emif_to_hps = '0; + +endmodule + diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy.v new file mode 100644 index 000000000000..3d48103c1ea0 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy.v @@ -0,0 +1,179 @@ +// ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy.v + +// This file was auto-generated from altera_emif_cal_slave_nf_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_emif_slave_1_altera_emif_cal_slave_nf_170_6qfmevy ( + output wire avl_waitrequest, // avl.waitrequest + output wire [31:0] avl_readdata, // .readdata + output wire avl_readdatavalid, // .readdatavalid + input wire [0:0] avl_burstcount, // .burstcount + input wire [31:0] avl_writedata, // .writedata + input wire [15:0] avl_address, // .address + input wire avl_write, // .write + input wire avl_read, // .read + input wire [3:0] avl_byteenable, // .byteenable + input wire avl_debugaccess, // .debugaccess + input wire clk_clk, // clk.clk + input wire rst_reset // rst.reset + ); + + wire ioaux_master_bridge_m0_waitrequest; // mm_interconnect_0:ioaux_master_bridge_m0_waitrequest -> ioaux_master_bridge:m0_waitrequest + wire [31:0] ioaux_master_bridge_m0_readdata; // mm_interconnect_0:ioaux_master_bridge_m0_readdata -> ioaux_master_bridge:m0_readdata + wire ioaux_master_bridge_m0_debugaccess; // ioaux_master_bridge:m0_debugaccess -> mm_interconnect_0:ioaux_master_bridge_m0_debugaccess + wire [15:0] ioaux_master_bridge_m0_address; // ioaux_master_bridge:m0_address -> mm_interconnect_0:ioaux_master_bridge_m0_address + wire ioaux_master_bridge_m0_read; // ioaux_master_bridge:m0_read -> mm_interconnect_0:ioaux_master_bridge_m0_read + wire [3:0] ioaux_master_bridge_m0_byteenable; // ioaux_master_bridge:m0_byteenable -> mm_interconnect_0:ioaux_master_bridge_m0_byteenable + wire ioaux_master_bridge_m0_readdatavalid; // mm_interconnect_0:ioaux_master_bridge_m0_readdatavalid -> ioaux_master_bridge:m0_readdatavalid + wire [31:0] ioaux_master_bridge_m0_writedata; // ioaux_master_bridge:m0_writedata -> mm_interconnect_0:ioaux_master_bridge_m0_writedata + wire ioaux_master_bridge_m0_write; // ioaux_master_bridge:m0_write -> mm_interconnect_0:ioaux_master_bridge_m0_write + wire [0:0] ioaux_master_bridge_m0_burstcount; // ioaux_master_bridge:m0_burstcount -> mm_interconnect_0:ioaux_master_bridge_m0_burstcount + wire mm_interconnect_0_ioaux_soft_ram_s1_chipselect; // mm_interconnect_0:ioaux_soft_ram_s1_chipselect -> ioaux_soft_ram:chipselect + wire [31:0] mm_interconnect_0_ioaux_soft_ram_s1_readdata; // ioaux_soft_ram:readdata -> mm_interconnect_0:ioaux_soft_ram_s1_readdata + wire mm_interconnect_0_ioaux_soft_ram_s1_debugaccess; // mm_interconnect_0:ioaux_soft_ram_s1_debugaccess -> ioaux_soft_ram:debugaccess + wire [11:0] mm_interconnect_0_ioaux_soft_ram_s1_address; // mm_interconnect_0:ioaux_soft_ram_s1_address -> ioaux_soft_ram:address + wire [3:0] mm_interconnect_0_ioaux_soft_ram_s1_byteenable; // mm_interconnect_0:ioaux_soft_ram_s1_byteenable -> ioaux_soft_ram:byteenable + wire mm_interconnect_0_ioaux_soft_ram_s1_write; // mm_interconnect_0:ioaux_soft_ram_s1_write -> ioaux_soft_ram:write + wire [31:0] mm_interconnect_0_ioaux_soft_ram_s1_writedata; // mm_interconnect_0:ioaux_soft_ram_s1_writedata -> ioaux_soft_ram:writedata + wire mm_interconnect_0_ioaux_soft_ram_s1_clken; // mm_interconnect_0:ioaux_soft_ram_s1_clken -> ioaux_soft_ram:clken + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [ioaux_master_bridge:reset, ioaux_soft_ram:reset, mm_interconnect_0:ioaux_master_bridge_reset_reset_bridge_in_reset_reset] + + altera_avalon_mm_bridge #( + .DATA_WIDTH (32), + .SYMBOL_WIDTH (8), + .HDL_ADDR_WIDTH (16), + .BURSTCOUNT_WIDTH (1), + .PIPELINE_COMMAND (1), + .PIPELINE_RESPONSE (1) + ) ioaux_master_bridge ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .s0_waitrequest (avl_waitrequest), // s0.waitrequest + .s0_readdata (avl_readdata), // .readdata + .s0_readdatavalid (avl_readdatavalid), // .readdatavalid + .s0_burstcount (avl_burstcount), // .burstcount + .s0_writedata (avl_writedata), // .writedata + .s0_address (avl_address), // .address + .s0_write (avl_write), // .write + .s0_read (avl_read), // .read + .s0_byteenable (avl_byteenable), // .byteenable + .s0_debugaccess (avl_debugaccess), // .debugaccess + .m0_waitrequest (ioaux_master_bridge_m0_waitrequest), // m0.waitrequest + .m0_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .m0_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .m0_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .m0_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .m0_address (ioaux_master_bridge_m0_address), // .address + .m0_write (ioaux_master_bridge_m0_write), // .write + .m0_read (ioaux_master_bridge_m0_read), // .read + .m0_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .m0_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .s0_response (), // (terminated) + .m0_response (2'b00) // (terminated) + ); + + ed_sim_emif_slave_1_altera_avalon_onchip_memory2_170_yroldmy ioaux_soft_ram ( + .clk (clk_clk), // clk1.clk + .address (mm_interconnect_0_ioaux_soft_ram_s1_address), // s1.address + .debugaccess (mm_interconnect_0_ioaux_soft_ram_s1_debugaccess), // .debugaccess + .clken (mm_interconnect_0_ioaux_soft_ram_s1_clken), // .clken + .chipselect (mm_interconnect_0_ioaux_soft_ram_s1_chipselect), // .chipselect + .write (mm_interconnect_0_ioaux_soft_ram_s1_write), // .write + .readdata (mm_interconnect_0_ioaux_soft_ram_s1_readdata), // .readdata + .writedata (mm_interconnect_0_ioaux_soft_ram_s1_writedata), // .writedata + .byteenable (mm_interconnect_0_ioaux_soft_ram_s1_byteenable), // .byteenable + .reset (rst_controller_reset_out_reset), // reset1.reset + .reset_req (1'b0), // (terminated) + .freeze (1'b0) // (terminated) + ); + + ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki mm_interconnect_0 ( + .clk_bridge_out_clk_clk (clk_clk), // clk_bridge_out_clk.clk + .ioaux_master_bridge_m0_address (ioaux_master_bridge_m0_address), // ioaux_master_bridge_m0.address + .ioaux_master_bridge_m0_waitrequest (ioaux_master_bridge_m0_waitrequest), // .waitrequest + .ioaux_master_bridge_m0_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .ioaux_master_bridge_m0_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .ioaux_master_bridge_m0_read (ioaux_master_bridge_m0_read), // .read + .ioaux_master_bridge_m0_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .ioaux_master_bridge_m0_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .ioaux_master_bridge_m0_write (ioaux_master_bridge_m0_write), // .write + .ioaux_master_bridge_m0_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .ioaux_master_bridge_m0_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .ioaux_master_bridge_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // ioaux_master_bridge_reset_reset_bridge_in_reset.reset + .ioaux_soft_ram_s1_address (mm_interconnect_0_ioaux_soft_ram_s1_address), // ioaux_soft_ram_s1.address + .ioaux_soft_ram_s1_write (mm_interconnect_0_ioaux_soft_ram_s1_write), // .write + .ioaux_soft_ram_s1_readdata (mm_interconnect_0_ioaux_soft_ram_s1_readdata), // .readdata + .ioaux_soft_ram_s1_writedata (mm_interconnect_0_ioaux_soft_ram_s1_writedata), // .writedata + .ioaux_soft_ram_s1_byteenable (mm_interconnect_0_ioaux_soft_ram_s1_byteenable), // .byteenable + .ioaux_soft_ram_s1_chipselect (mm_interconnect_0_ioaux_soft_ram_s1_chipselect), // .chipselect + .ioaux_soft_ram_s1_clken (mm_interconnect_0_ioaux_soft_ram_s1_clken), // .clken + .ioaux_soft_ram_s1_debugaccess (mm_interconnect_0_ioaux_soft_ram_s1_debugaccess) // .debugaccess + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (1), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (0), + .RESET_REQ_WAIT_TIME (1), + .MIN_RST_ASSERTION_TIME (3), + .RESET_REQ_EARLY_DSRT_TIME (1), + .USE_RESET_REQUEST_IN0 (0), + .USE_RESET_REQUEST_IN1 (0), + .USE_RESET_REQUEST_IN2 (0), + .USE_RESET_REQUEST_IN3 (0), + .USE_RESET_REQUEST_IN4 (0), + .USE_RESET_REQUEST_IN5 (0), + .USE_RESET_REQUEST_IN6 (0), + .USE_RESET_REQUEST_IN7 (0), + .USE_RESET_REQUEST_IN8 (0), + .USE_RESET_REQUEST_IN9 (0), + .USE_RESET_REQUEST_IN10 (0), + .USE_RESET_REQUEST_IN11 (0), + .USE_RESET_REQUEST_IN12 (0), + .USE_RESET_REQUEST_IN13 (0), + .USE_RESET_REQUEST_IN14 (0), + .USE_RESET_REQUEST_IN15 (0), + .ADAPT_RESET_REQUEST (0) + ) rst_controller ( + .reset_in0 (rst_reset), // reset_in0.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (), // (terminated) + .reset_req_in0 (1'b0), // (terminated) + .reset_in1 (1'b0), // (terminated) + .reset_req_in1 (1'b0), // (terminated) + .reset_in2 (1'b0), // (terminated) + .reset_req_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_req_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_req_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_req_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_req_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_req_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_req_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_req_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_req_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_req_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_req_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_req_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_req_in14 (1'b0), // (terminated) + .reset_in15 (1'b0), // (terminated) + .reset_req_in15 (1'b0) // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki.v new file mode 100644 index 000000000000..e9f0dccb303a --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki.v @@ -0,0 +1,168 @@ +// ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki.v + +// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_emif_slave_1_altera_mm_interconnect_170_o2ys4ki ( + input wire clk_bridge_out_clk_clk, // clk_bridge_out_clk.clk + input wire [15:0] ioaux_master_bridge_m0_address, // ioaux_master_bridge_m0.address + output wire ioaux_master_bridge_m0_waitrequest, // .waitrequest + input wire [0:0] ioaux_master_bridge_m0_burstcount, // .burstcount + input wire [3:0] ioaux_master_bridge_m0_byteenable, // .byteenable + input wire ioaux_master_bridge_m0_read, // .read + output wire [31:0] ioaux_master_bridge_m0_readdata, // .readdata + output wire ioaux_master_bridge_m0_readdatavalid, // .readdatavalid + input wire ioaux_master_bridge_m0_write, // .write + input wire [31:0] ioaux_master_bridge_m0_writedata, // .writedata + input wire ioaux_master_bridge_m0_debugaccess, // .debugaccess + input wire ioaux_master_bridge_reset_reset_bridge_in_reset_reset, // ioaux_master_bridge_reset_reset_bridge_in_reset.reset + output wire [11:0] ioaux_soft_ram_s1_address, // ioaux_soft_ram_s1.address + output wire ioaux_soft_ram_s1_write, // .write + input wire [31:0] ioaux_soft_ram_s1_readdata, // .readdata + output wire [31:0] ioaux_soft_ram_s1_writedata, // .writedata + output wire [3:0] ioaux_soft_ram_s1_byteenable, // .byteenable + output wire ioaux_soft_ram_s1_chipselect, // .chipselect + output wire ioaux_soft_ram_s1_clken, // .clken + output wire ioaux_soft_ram_s1_debugaccess // .debugaccess + ); + + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest; // ioaux_soft_ram_s1_translator:uav_waitrequest -> ioaux_master_bridge_m0_translator:uav_waitrequest + wire [31:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata; // ioaux_soft_ram_s1_translator:uav_readdata -> ioaux_master_bridge_m0_translator:uav_readdata + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess; // ioaux_master_bridge_m0_translator:uav_debugaccess -> ioaux_soft_ram_s1_translator:uav_debugaccess + wire [15:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_address; // ioaux_master_bridge_m0_translator:uav_address -> ioaux_soft_ram_s1_translator:uav_address + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_read; // ioaux_master_bridge_m0_translator:uav_read -> ioaux_soft_ram_s1_translator:uav_read + wire [3:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable; // ioaux_master_bridge_m0_translator:uav_byteenable -> ioaux_soft_ram_s1_translator:uav_byteenable + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid; // ioaux_soft_ram_s1_translator:uav_readdatavalid -> ioaux_master_bridge_m0_translator:uav_readdatavalid + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock; // ioaux_master_bridge_m0_translator:uav_lock -> ioaux_soft_ram_s1_translator:uav_lock + wire ioaux_master_bridge_m0_translator_avalon_universal_master_0_write; // ioaux_master_bridge_m0_translator:uav_write -> ioaux_soft_ram_s1_translator:uav_write + wire [31:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata; // ioaux_master_bridge_m0_translator:uav_writedata -> ioaux_soft_ram_s1_translator:uav_writedata + wire [2:0] ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount; // ioaux_master_bridge_m0_translator:uav_burstcount -> ioaux_soft_ram_s1_translator:uav_burstcount + + altera_merlin_master_translator #( + .AV_ADDRESS_W (16), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (16), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (1), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) ioaux_master_bridge_m0_translator ( + .clk (clk_bridge_out_clk_clk), // clk.clk + .reset (ioaux_master_bridge_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (ioaux_master_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (ioaux_master_bridge_m0_translator_avalon_universal_master_0_read), // .read + .uav_write (ioaux_master_bridge_m0_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (ioaux_master_bridge_m0_address), // avalon_anti_master_0.address + .av_waitrequest (ioaux_master_bridge_m0_waitrequest), // .waitrequest + .av_burstcount (ioaux_master_bridge_m0_burstcount), // .burstcount + .av_byteenable (ioaux_master_bridge_m0_byteenable), // .byteenable + .av_read (ioaux_master_bridge_m0_read), // .read + .av_readdata (ioaux_master_bridge_m0_readdata), // .readdata + .av_readdatavalid (ioaux_master_bridge_m0_readdatavalid), // .readdatavalid + .av_write (ioaux_master_bridge_m0_write), // .write + .av_writedata (ioaux_master_bridge_m0_writedata), // .writedata + .av_debugaccess (ioaux_master_bridge_m0_debugaccess), // .debugaccess + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1), // (terminated) + .uav_response (2'b00), // (terminated) + .av_response (), // (terminated) + .uav_writeresponsevalid (1'b0), // (terminated) + .av_writeresponsevalid () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (12), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (16), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .USE_READRESPONSE (0), + .USE_WRITERESPONSE (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) ioaux_soft_ram_s1_translator ( + .clk (clk_bridge_out_clk_clk), // clk.clk + .reset (ioaux_master_bridge_reset_reset_bridge_in_reset_reset), // reset.reset + .uav_address (ioaux_master_bridge_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address + .uav_burstcount (ioaux_master_bridge_m0_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (ioaux_master_bridge_m0_translator_avalon_universal_master_0_read), // .read + .uav_write (ioaux_master_bridge_m0_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (ioaux_master_bridge_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (ioaux_master_bridge_m0_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (ioaux_master_bridge_m0_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (ioaux_master_bridge_m0_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (ioaux_master_bridge_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (ioaux_soft_ram_s1_address), // avalon_anti_slave_0.address + .av_write (ioaux_soft_ram_s1_write), // .write + .av_readdata (ioaux_soft_ram_s1_readdata), // .readdata + .av_writedata (ioaux_soft_ram_s1_writedata), // .writedata + .av_byteenable (ioaux_soft_ram_s1_byteenable), // .byteenable + .av_chipselect (ioaux_soft_ram_s1_chipselect), // .chipselect + .av_clken (ioaux_soft_ram_s1_clken), // .clken + .av_debugaccess (ioaux_soft_ram_s1_debugaccess), // .debugaccess + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_outputenable (), // (terminated) + .uav_response (), // (terminated) + .av_response (2'b00), // (terminated) + .uav_writeresponsevalid (), // (terminated) + .av_writeresponsevalid (1'b0) // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_source.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_source.v new file mode 100644 index 000000000000..9d0fc9194cf8 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_source.v @@ -0,0 +1,19 @@ +// ed_sim_global_reset_n_source.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_global_reset_n_source ( + input wire clk, // clk.clk + output wire reset // reset.reset_n + ); + + altera_avalon_reset_source #( + .ASSERT_HIGH_RESET (0), + .INITIAL_RESET_CYCLES (5) + ) global_reset_n_source ( + .reset (reset), // reset.reset_n + .clk (clk) // clk.clk + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_splitter.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_splitter.v new file mode 100644 index 000000000000..ad30225aba11 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_global_reset_n_splitter.v @@ -0,0 +1,13 @@ +// ed_sim_global_reset_n_splitter.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_global_reset_n_splitter ( + input wire sig_input, // sig_input_if.reset_n + output wire sig_output_0 // sig_output_if_0.reset_n + ); + + assign sig_output_0 = sig_input; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0.v new file mode 100644 index 000000000000..31038d63d67e --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0.v @@ -0,0 +1,44 @@ +// ed_sim_mem_0.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_mem_0 ( + input wire [0:0] mem_ck, // mem.mem_ck + input wire [0:0] mem_ck_n, // .mem_ck_n + input wire [16:0] mem_a, // .mem_a + input wire [0:0] mem_act_n, // .mem_act_n + input wire [1:0] mem_ba, // .mem_ba + input wire [1:0] mem_bg, // .mem_bg + input wire [0:0] mem_cke, // .mem_cke + input wire [0:0] mem_cs_n, // .mem_cs_n + input wire [0:0] mem_odt, // .mem_odt + input wire [0:0] mem_reset_n, // .mem_reset_n + input wire [0:0] mem_par, // .mem_par + output wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n // .mem_dbi_n + ); + + ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q mem_0 ( + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n) // .mem_dbi_n + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q.v new file mode 100644 index 000000000000..55d5c9c8bfb5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q.v @@ -0,0 +1,172 @@ +// ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q.v + +// This file was auto-generated from altera_emif_mem_model_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_mem_0_altera_emif_mem_model_170_nzcko3q ( + input wire [0:0] mem_ck, // mem.mem_ck + input wire [0:0] mem_ck_n, // .mem_ck_n + input wire [16:0] mem_a, // .mem_a + input wire [0:0] mem_act_n, // .mem_act_n + input wire [1:0] mem_ba, // .mem_ba + input wire [1:0] mem_bg, // .mem_bg + input wire [0:0] mem_cke, // .mem_cke + input wire [0:0] mem_cs_n, // .mem_cs_n + input wire [0:0] mem_odt, // .mem_odt + input wire [0:0] mem_reset_n, // .mem_reset_n + input wire [0:0] mem_par, // .mem_par + output wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n // .mem_dbi_n + ); + + altera_emif_ddrx_model #( + .PROTOCOL_ENUM ("PROTOCOL_DDR4"), + .PHY_PING_PONG_EN (0), + .MEM_FORMAT_ENUM ("MEM_FORMAT_DISCRETE"), + .PORT_MEM_CK_WIDTH (1), + .PORT_MEM_CK_N_WIDTH (1), + .PORT_MEM_DK_WIDTH (1), + .PORT_MEM_DK_N_WIDTH (1), + .PORT_MEM_DKA_WIDTH (1), + .PORT_MEM_DKA_N_WIDTH (1), + .PORT_MEM_DKB_WIDTH (1), + .PORT_MEM_DKB_N_WIDTH (1), + .PORT_MEM_K_WIDTH (1), + .PORT_MEM_K_N_WIDTH (1), + .PORT_MEM_A_WIDTH (17), + .PORT_MEM_BA_WIDTH (2), + .PORT_MEM_BG_WIDTH (2), + .PORT_MEM_C_WIDTH (1), + .PORT_MEM_CKE_WIDTH (1), + .PORT_MEM_CS_N_WIDTH (1), + .PORT_MEM_RM_WIDTH (1), + .PORT_MEM_ODT_WIDTH (1), + .PORT_MEM_RAS_N_WIDTH (1), + .PORT_MEM_CAS_N_WIDTH (1), + .PORT_MEM_WE_N_WIDTH (1), + .PORT_MEM_RESET_N_WIDTH (1), + .PORT_MEM_ACT_N_WIDTH (1), + .PORT_MEM_PAR_WIDTH (1), + .PORT_MEM_CA_WIDTH (1), + .PORT_MEM_REF_N_WIDTH (1), + .PORT_MEM_WPS_N_WIDTH (1), + .PORT_MEM_RPS_N_WIDTH (1), + .PORT_MEM_DOFF_N_WIDTH (1), + .PORT_MEM_LDA_N_WIDTH (1), + .PORT_MEM_LDB_N_WIDTH (1), + .PORT_MEM_RWA_N_WIDTH (1), + .PORT_MEM_RWB_N_WIDTH (1), + .PORT_MEM_LBK0_N_WIDTH (1), + .PORT_MEM_LBK1_N_WIDTH (1), + .PORT_MEM_CFG_N_WIDTH (1), + .PORT_MEM_AP_WIDTH (1), + .PORT_MEM_AINV_WIDTH (1), + .PORT_MEM_DM_WIDTH (1), + .PORT_MEM_BWS_N_WIDTH (1), + .PORT_MEM_D_WIDTH (1), + .PORT_MEM_DQ_WIDTH (64), + .PORT_MEM_DBI_N_WIDTH (8), + .PORT_MEM_DQA_WIDTH (1), + .PORT_MEM_DQB_WIDTH (1), + .PORT_MEM_DINVA_WIDTH (1), + .PORT_MEM_DINVB_WIDTH (1), + .PORT_MEM_Q_WIDTH (1), + .PORT_MEM_DQS_WIDTH (8), + .PORT_MEM_DQS_N_WIDTH (8), + .PORT_MEM_QK_WIDTH (1), + .PORT_MEM_QK_N_WIDTH (1), + .PORT_MEM_QKA_WIDTH (1), + .PORT_MEM_QKA_N_WIDTH (1), + .PORT_MEM_QKB_WIDTH (1), + .PORT_MEM_QKB_N_WIDTH (1), + .PORT_MEM_CQ_WIDTH (1), + .PORT_MEM_CQ_N_WIDTH (1), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_PE_N_WIDTH (1), + .MEM_DISCRETE_CS_WIDTH (1), + .MEM_CHIP_ID_WIDTH (0), + .MEM_ROW_ADDR_WIDTH (15), + .MEM_COL_ADDR_WIDTH (10), + .MEM_TRTP (9), + .MEM_TRCD (15), + .MEM_RANKS_PER_DIMM (1), + .MEM_NUM_OF_DIMMS (1), + .MEM_DM_EN (1), + .MEM_DISCRETE_MIRROR_ADDRESSING_EN (0), + .MEM_MIRROR_ADDRESSING_EN (1), + .MEM_INIT_MRS0 (0), + .MEM_INIT_MRS1 (0), + .MEM_INIT_MRS2 (0), + .MEM_INIT_MRS3 (0), + .MEM_CFG_GEN_SBE (0), + .MEM_CFG_GEN_DBE (0) + ) core ( + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .mem_c (1'b0), // (terminated) + .mem_rm (1'b0), // (terminated) + .mem_dk (1'b0), // (terminated) + .mem_dk_n (1'b0), // (terminated) + .mem_dka (1'b0), // (terminated) + .mem_dka_n (1'b0), // (terminated) + .mem_dkb (1'b0), // (terminated) + .mem_dkb_n (1'b0), // (terminated) + .mem_k (1'b0), // (terminated) + .mem_k_n (1'b0), // (terminated) + .mem_ras_n (1'b0), // (terminated) + .mem_cas_n (1'b0), // (terminated) + .mem_we_n (1'b0), // (terminated) + .mem_ca (1'b0), // (terminated) + .mem_ref_n (1'b0), // (terminated) + .mem_wps_n (1'b0), // (terminated) + .mem_rps_n (1'b0), // (terminated) + .mem_doff_n (1'b0), // (terminated) + .mem_lda_n (1'b0), // (terminated) + .mem_ldb_n (1'b0), // (terminated) + .mem_rwa_n (1'b0), // (terminated) + .mem_rwb_n (1'b0), // (terminated) + .mem_lbk0_n (1'b0), // (terminated) + .mem_lbk1_n (1'b0), // (terminated) + .mem_cfg_n (1'b0), // (terminated) + .mem_ap (1'b0), // (terminated) + .mem_ainv (1'b0), // (terminated) + .mem_dm (1'b0), // (terminated) + .mem_bws_n (1'b0), // (terminated) + .mem_d (1'b0), // (terminated) + .mem_dqa (), // (terminated) + .mem_dqb (), // (terminated) + .mem_dinva (), // (terminated) + .mem_dinvb (), // (terminated) + .mem_q (), // (terminated) + .mem_qk (), // (terminated) + .mem_qk_n (), // (terminated) + .mem_qka (), // (terminated) + .mem_qka_n (), // (terminated) + .mem_qkb (), // (terminated) + .mem_qkb_n (), // (terminated) + .mem_cq (), // (terminated) + .mem_cq_n (), // (terminated) + .mem_pe_n () // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1.v new file mode 100644 index 000000000000..a7a19e585b19 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1.v @@ -0,0 +1,44 @@ +// ed_sim_mem_1.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_mem_1 ( + input wire [0:0] mem_ck, // mem.mem_ck + input wire [0:0] mem_ck_n, // .mem_ck_n + input wire [16:0] mem_a, // .mem_a + input wire [0:0] mem_act_n, // .mem_act_n + input wire [1:0] mem_ba, // .mem_ba + input wire [1:0] mem_bg, // .mem_bg + input wire [0:0] mem_cke, // .mem_cke + input wire [0:0] mem_cs_n, // .mem_cs_n + input wire [0:0] mem_odt, // .mem_odt + input wire [0:0] mem_reset_n, // .mem_reset_n + input wire [0:0] mem_par, // .mem_par + output wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n // .mem_dbi_n + ); + + ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q mem_1 ( + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n) // .mem_dbi_n + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q.v new file mode 100644 index 000000000000..48140b288671 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q.v @@ -0,0 +1,172 @@ +// ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q.v + +// This file was auto-generated from altera_emif_mem_model_hw.tcl. If you edit it your changes +// will probably be lost. +// +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_mem_1_altera_emif_mem_model_170_nzcko3q ( + input wire [0:0] mem_ck, // mem.mem_ck + input wire [0:0] mem_ck_n, // .mem_ck_n + input wire [16:0] mem_a, // .mem_a + input wire [0:0] mem_act_n, // .mem_act_n + input wire [1:0] mem_ba, // .mem_ba + input wire [1:0] mem_bg, // .mem_bg + input wire [0:0] mem_cke, // .mem_cke + input wire [0:0] mem_cs_n, // .mem_cs_n + input wire [0:0] mem_odt, // .mem_odt + input wire [0:0] mem_reset_n, // .mem_reset_n + input wire [0:0] mem_par, // .mem_par + output wire [0:0] mem_alert_n, // .mem_alert_n + inout wire [7:0] mem_dqs, // .mem_dqs + inout wire [7:0] mem_dqs_n, // .mem_dqs_n + inout wire [63:0] mem_dq, // .mem_dq + inout wire [7:0] mem_dbi_n // .mem_dbi_n + ); + + altera_emif_ddrx_model #( + .PROTOCOL_ENUM ("PROTOCOL_DDR4"), + .PHY_PING_PONG_EN (0), + .MEM_FORMAT_ENUM ("MEM_FORMAT_DISCRETE"), + .PORT_MEM_CK_WIDTH (1), + .PORT_MEM_CK_N_WIDTH (1), + .PORT_MEM_DK_WIDTH (1), + .PORT_MEM_DK_N_WIDTH (1), + .PORT_MEM_DKA_WIDTH (1), + .PORT_MEM_DKA_N_WIDTH (1), + .PORT_MEM_DKB_WIDTH (1), + .PORT_MEM_DKB_N_WIDTH (1), + .PORT_MEM_K_WIDTH (1), + .PORT_MEM_K_N_WIDTH (1), + .PORT_MEM_A_WIDTH (17), + .PORT_MEM_BA_WIDTH (2), + .PORT_MEM_BG_WIDTH (2), + .PORT_MEM_C_WIDTH (1), + .PORT_MEM_CKE_WIDTH (1), + .PORT_MEM_CS_N_WIDTH (1), + .PORT_MEM_RM_WIDTH (1), + .PORT_MEM_ODT_WIDTH (1), + .PORT_MEM_RAS_N_WIDTH (1), + .PORT_MEM_CAS_N_WIDTH (1), + .PORT_MEM_WE_N_WIDTH (1), + .PORT_MEM_RESET_N_WIDTH (1), + .PORT_MEM_ACT_N_WIDTH (1), + .PORT_MEM_PAR_WIDTH (1), + .PORT_MEM_CA_WIDTH (1), + .PORT_MEM_REF_N_WIDTH (1), + .PORT_MEM_WPS_N_WIDTH (1), + .PORT_MEM_RPS_N_WIDTH (1), + .PORT_MEM_DOFF_N_WIDTH (1), + .PORT_MEM_LDA_N_WIDTH (1), + .PORT_MEM_LDB_N_WIDTH (1), + .PORT_MEM_RWA_N_WIDTH (1), + .PORT_MEM_RWB_N_WIDTH (1), + .PORT_MEM_LBK0_N_WIDTH (1), + .PORT_MEM_LBK1_N_WIDTH (1), + .PORT_MEM_CFG_N_WIDTH (1), + .PORT_MEM_AP_WIDTH (1), + .PORT_MEM_AINV_WIDTH (1), + .PORT_MEM_DM_WIDTH (1), + .PORT_MEM_BWS_N_WIDTH (1), + .PORT_MEM_D_WIDTH (1), + .PORT_MEM_DQ_WIDTH (64), + .PORT_MEM_DBI_N_WIDTH (8), + .PORT_MEM_DQA_WIDTH (1), + .PORT_MEM_DQB_WIDTH (1), + .PORT_MEM_DINVA_WIDTH (1), + .PORT_MEM_DINVB_WIDTH (1), + .PORT_MEM_Q_WIDTH (1), + .PORT_MEM_DQS_WIDTH (8), + .PORT_MEM_DQS_N_WIDTH (8), + .PORT_MEM_QK_WIDTH (1), + .PORT_MEM_QK_N_WIDTH (1), + .PORT_MEM_QKA_WIDTH (1), + .PORT_MEM_QKA_N_WIDTH (1), + .PORT_MEM_QKB_WIDTH (1), + .PORT_MEM_QKB_N_WIDTH (1), + .PORT_MEM_CQ_WIDTH (1), + .PORT_MEM_CQ_N_WIDTH (1), + .PORT_MEM_ALERT_N_WIDTH (1), + .PORT_MEM_PE_N_WIDTH (1), + .MEM_DISCRETE_CS_WIDTH (1), + .MEM_CHIP_ID_WIDTH (0), + .MEM_ROW_ADDR_WIDTH (15), + .MEM_COL_ADDR_WIDTH (10), + .MEM_TRTP (9), + .MEM_TRCD (15), + .MEM_RANKS_PER_DIMM (1), + .MEM_NUM_OF_DIMMS (1), + .MEM_DM_EN (1), + .MEM_DISCRETE_MIRROR_ADDRESSING_EN (0), + .MEM_MIRROR_ADDRESSING_EN (1), + .MEM_INIT_MRS0 (0), + .MEM_INIT_MRS1 (0), + .MEM_INIT_MRS2 (0), + .MEM_INIT_MRS3 (0), + .MEM_CFG_GEN_SBE (0), + .MEM_CFG_GEN_DBE (0) + ) core ( + .mem_ck (mem_ck), // mem.mem_ck + .mem_ck_n (mem_ck_n), // .mem_ck_n + .mem_a (mem_a), // .mem_a + .mem_act_n (mem_act_n), // .mem_act_n + .mem_ba (mem_ba), // .mem_ba + .mem_bg (mem_bg), // .mem_bg + .mem_cke (mem_cke), // .mem_cke + .mem_cs_n (mem_cs_n), // .mem_cs_n + .mem_odt (mem_odt), // .mem_odt + .mem_reset_n (mem_reset_n), // .mem_reset_n + .mem_par (mem_par), // .mem_par + .mem_alert_n (mem_alert_n), // .mem_alert_n + .mem_dqs (mem_dqs), // .mem_dqs + .mem_dqs_n (mem_dqs_n), // .mem_dqs_n + .mem_dq (mem_dq), // .mem_dq + .mem_dbi_n (mem_dbi_n), // .mem_dbi_n + .mem_c (1'b0), // (terminated) + .mem_rm (1'b0), // (terminated) + .mem_dk (1'b0), // (terminated) + .mem_dk_n (1'b0), // (terminated) + .mem_dka (1'b0), // (terminated) + .mem_dka_n (1'b0), // (terminated) + .mem_dkb (1'b0), // (terminated) + .mem_dkb_n (1'b0), // (terminated) + .mem_k (1'b0), // (terminated) + .mem_k_n (1'b0), // (terminated) + .mem_ras_n (1'b0), // (terminated) + .mem_cas_n (1'b0), // (terminated) + .mem_we_n (1'b0), // (terminated) + .mem_ca (1'b0), // (terminated) + .mem_ref_n (1'b0), // (terminated) + .mem_wps_n (1'b0), // (terminated) + .mem_rps_n (1'b0), // (terminated) + .mem_doff_n (1'b0), // (terminated) + .mem_lda_n (1'b0), // (terminated) + .mem_ldb_n (1'b0), // (terminated) + .mem_rwa_n (1'b0), // (terminated) + .mem_rwb_n (1'b0), // (terminated) + .mem_lbk0_n (1'b0), // (terminated) + .mem_lbk1_n (1'b0), // (terminated) + .mem_cfg_n (1'b0), // (terminated) + .mem_ap (1'b0), // (terminated) + .mem_ainv (1'b0), // (terminated) + .mem_dm (1'b0), // (terminated) + .mem_bws_n (1'b0), // (terminated) + .mem_d (1'b0), // (terminated) + .mem_dqa (), // (terminated) + .mem_dqb (), // (terminated) + .mem_dinva (), // (terminated) + .mem_dinvb (), // (terminated) + .mem_q (), // (terminated) + .mem_qk (), // (terminated) + .mem_qk_n (), // (terminated) + .mem_qka (), // (terminated) + .mem_qka_n (), // (terminated) + .mem_qkb (), // (terminated) + .mem_qkb_n (), // (terminated) + .mem_cq (), // (terminated) + .mem_cq_n (), // (terminated) + .mem_pe_n () // (terminated) + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/ed_sim_pll_ref_clk_source.v b/ase/rtl/device_models/dcp_emif_model/ed_sim_pll_ref_clk_source.v new file mode 100644 index 000000000000..116c91589d8e --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/ed_sim_pll_ref_clk_source.v @@ -0,0 +1,17 @@ +// ed_sim_pll_ref_clk_source.v + +// Generated using ACDS version 17.0 290 + +`timescale 1 ps / 1 ps +module ed_sim_pll_ref_clk_source ( + output wire clk // clk.clk + ); + + altera_avalon_clock_source #( + .CLOCK_RATE (266667000), + .CLOCK_UNIT (1) + ) pll_ref_clk_source ( + .clk (clk) // clk.clk + ); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/io_12_lane__nf5es_abphy.sv b/ase/rtl/device_models/dcp_emif_model/io_12_lane__nf5es_abphy.sv new file mode 100644 index 000000000000..21060575b3c5 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/io_12_lane__nf5es_abphy.sv @@ -0,0 +1,2114 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module io_12_lane__nf5es_abphy ( + input i50u_ref, + input ibp50u, + input ibp50u_cal, + output atbi_0, + output atbi_1, + input regulator_clk, + input reset_n, + input [7:0] phy_clk_phs, + input [4:0] phy_clk, + input broadcast_in_top, + input broadcast_in_bot, + output broadcast_out_top, + output broadcast_out_bot, + input [5:0] switch_up, + input [5:0] switch_dn, + input [5:0] up_ph, + input [5:0] dzoutx, + output [5:0] crnt_clk, + output [5:0] n_crnt_clk, + output [5:0] next_clk, + output [5:0] n_next_clk, + output [5:0] ioereg_locked, + output [11:0] weak_pullup_enable, + output [11:0] codin_p, + output [11:0] codin_pb, + output [11:0] codin_n, + output [11:0] codin_nb, + output [11:0] oct_enable, + input [23:0] dq_diff_in, + input [23:0] dq_sstl_in, + input [1:0] dqs_diff_in_0, + input [1:0] dqs_diff_in_1, + input [1:0] dqs_diff_in_2, + input [1:0] dqs_diff_in_3, + input [1:0] dqs_sstl_p_0, + input [1:0] dqs_sstl_p_1, + input [1:0] dqs_sstl_p_2, + input [1:0] dqs_sstl_p_3, + input [1:0] dqs_sstl_n_0, + input [1:0] dqs_sstl_n_1, + input [1:0] dqs_sstl_n_2, + input [1:0] dqs_sstl_n_3, + input avl_clk_in, + output avl_clk_out, + input [19:0] avl_address_in, + output [19:0] avl_address_out, + input avl_write_in, + output avl_write_out, + input avl_read_in, + output avl_read_out, + input [31:0] avl_writedata_in, + output [31:0] avl_writedata_out, + input [31:0] avl_readdata_in, + output [31:0] avl_readdata_out, + input csr_clk, + input csr_in, + input csr_en, + input csr_shift_n, + output csr_out, + input pll_locked, + + input frzreg, + input niotri, + input [12*1-1:0] ncein, + input [12*1-1:0] nceout, + input [12*1-1:0] naclr, + input [12*1-1:0] nsclr, + input [12*1-1:0] fr_in_clk, + input [12*1-1:0] hr_in_clk, + input [12*1-1:0] fr_out_clk, + input [12*1-1:0] hr_out_clk, + input pll_clk, + + input osc_sel_n, + input osc_en_n, + output osc_rocount_to_core, + input osc_enable_in, + input osc_mode_in, + output x1024_osc_out, + input test_fr_clk_en_n, + input test_hr_clk_en_n, + input test_tdf_select_n, + input atpg_en_n, + input pipeline_global_en_n, + input test_clr_n, + input [12*1-1:0] tpin, + input [12*1-1:0] tpctl, + input [12*1-1:0] progctl, + input [12*1-1:0] progout, + input [12*1-1:0] progoe, + input scan_shift_n, + input [5:0] scanin, + input test_clk, + output [5:0] scanout, + output [12*1-1:0] tpdata, + output test_xor_clk, + input test_pst_clk_en_n, + input test_phy_clk_lane_en_n, + input test_int_clk_en_n, + input test_interp_clk_en_n, + input test_clk_ph_buf_en_n, + input test_datovr_en_n, + input test_avl_clk_in_en_n, + input test_dqs_enable_en_n, + input [11:0] test_dbg_out, + output [11:0] test_dbg_in, + + input jtag_shftdr, + input jtag_clk, + input jtag_highz, + input jtag_sdin, + input jtag_updtdr, + input jtag_mode, + output jtag_sdout, + + input [47:0] oeb_from_core, + input [95:0] data_from_core, + output [95:0] data_to_core, + input [15:0] mrnk_read_core, + input [15:0] mrnk_write_core, + input [3:0] rdata_en_full_core, + output [3:0] rdata_valid_core, + output [5:0] afi_wlat_core, + output [5:0] afi_rlat_core, + input core2dbc_wr_data_vld0, + input core2dbc_wr_data_vld1, + output dbc2core_wr_data_rdy, + output dbc2core_rd_data_vld0, + output dbc2core_rd_data_vld1, + output dbc2core_rd_type, + input core2dbc_rd_data_rdy, + input [12:0] core2dbc_wr_ecc_info, + output [11:0] dbc2core_wb_pointer, + input test_phy_clk_en_n, + input dft_prbs_ena_n, + output dft_prbs_pass, + output dft_prbs_done, + input [7:0] dft_core2db, + output [7:0] dft_db2core, + output [1:0] dft_phy_clk, + input test_pst_dll_i, + output test_pst_dll_o, + output lane_cal_done, + + input [95:0] ac_hmc, + input ctl2dbc_wrdata_vld0, + input ctl2dbc_mask_entry0, + input ctl2dbc_wb_rdptr_vld0, + input [5:0] ctl2dbc_wb_rdptr0, + input ctl2dbc_rb_wrptr_vld0, + input [5:0] ctl2dbc_rb_wrptr0, + input [1:0] ctl2dbc_rb_rdptr_vld0, + input [11:0] ctl2dbc_rb_rdptr0, + input [3:0] ctl2dbc_rdata_en_full0, + input [7:0] ctl2dbc_mrnk_read0, + input ctl2dbc_seq_en0, + input ctl2dbc_nop0, + input [1:0] ctl2dbc_cs0, + input ctl2dbc_rd_type0, + input [3:0] ctl2dbc_misc0, + input ctl2dbc_wrdata_vld1, + input ctl2dbc_mask_entry1, + input ctl2dbc_wb_rdptr_vld1, + input [5:0] ctl2dbc_wb_rdptr1, + input ctl2dbc_rb_wrptr_vld1, + input [5:0] ctl2dbc_rb_wrptr1, + input [1:0] ctl2dbc_rb_rdptr_vld1, + input [11:0] ctl2dbc_rb_rdptr1, + input [3:0] ctl2dbc_rdata_en_full1, + input [7:0] ctl2dbc_mrnk_read1, + input ctl2dbc_seq_en1, + input ctl2dbc_nop1, + input [1:0] ctl2dbc_cs1, + input ctl2dbc_rd_type1, + input [3:0] ctl2dbc_misc1, + output dbc2ctl_wb_retire_ptr_vld, + output [5:0] dbc2ctl_wb_retire_ptr, + output dbc2ctl_rb_retire_ptr_vld, + output [5:0] dbc2ctl_rb_retire_ptr, + output dbc2ctl_rd_data_vld, + output dbc2ctl_all_rd_done, + output dbc2db_wb_wrptr_vld, + output [5:0] dbc2db_wb_wrptr, + input cfg_dbc_ctrl_sel, + input cfg_reorder_rdata, + input cfg_rmw_en, + input cfg_output_regd, + input cfg_dbc_in_protocol, + input cfg_dbc_dualport_en, + input [2:0] cfg_dbc_pipe_lat, + input [2:0] cfg_cmd_rate, + input cfg_dbc_rc_en, + input [2:0] cfg_dbc_slot_rotate_en, + input [1:0] cfg_dbc_slot_offset, + + input vref_ext, +`ifdef WREAL_VREF + output real vref_int, +`else + output vref_int, +`endif + output xor_vref, + + input sync_clk_bot_in, + input sync_data_bot_in, + output sync_clk_bot_out, + output sync_data_bot_out, + input sync_clk_top_in, + input sync_data_top_in, + output sync_clk_top_out, + output sync_data_top_out, + + input [2:0] core_dll, + input clk_pll, + input reinit, + input entest, + input test_clk_pll_en_n, + output [12:0] dll_core, + + output [1:0] lvds_rx_clk_chnl0, + output [1:0] lvds_tx_clk_chnl0, + output [1:0] lvds_rx_clk_chnl1, + output [1:0] lvds_tx_clk_chnl1, + output [1:0] lvds_rx_clk_chnl2, + output [1:0] lvds_tx_clk_chnl2, + output [1:0] lvds_rx_clk_chnl3, + output [1:0] lvds_tx_clk_chnl3, + output [1:0] lvds_rx_clk_chnl4, + output [1:0] lvds_tx_clk_chnl4, + output [1:0] lvds_rx_clk_chnl5, + output [1:0] lvds_tx_clk_chnl5, + output [2:0] fb_clkout, + input wire early_csren, + input wire bhniotri, + input wire early_bhniotri, + input wire enrnsl, + input wire early_enrnsl, + input wire early_frzreg, + input wire nfrzdrv, + input wire early_nfrzdrv, + input wire early_niotri, + input wire plniotri, + input wire early_plniotri, + input wire usrmode, + input wire early_usrmode, + input wire wkpullup, + output wire local_bhniotri, + output wire local_enrnsl, + output wire local_frzreg, + output wire local_nfrzdrv, + output wire local_niotri, + output wire local_plniotri, + output wire local_usrmode, + output wire local_wkpullup, + output wire hps_to_core_ctrl_en, + input wire xprio_clk, + input wire xprio_sync, + input wire [7:0] xprio_xbus, + input test_db_csr_in, + input test_dqs_csr_in, + output test_ioereg2_csr_out, + output test_vref_csr_out, + input wire [4:0] cas_csrdin, + output wire [4:0] cas_csrdout, + output csr_clk_left, + output csr_en_left +); + timeunit 1ps; + timeprecision 1ps; + + + + wire [9:0] pvt_ref_gry; + wire [95:0] data_from_ioreg; + wire [95:0] data_from_ioreg_abphy; + wire [47:0] avl_readchain_bot; + wire [47:0] avl_readchain_top; + wire [9:0] ioereg_csrout; + wire [4:0] ioereg_scanout; + wire [4:0] ioereg_jtag_sdout; + wire [19:0] avl_address_dbc; + wire [3:0] avl_wr_address_top; + wire [3:0] avl_wr_address_bot; + wire [3:0] avl_rd_address_top; + wire [3:0] avl_rd_address_bot; + wire [31:0] avl_writedata_dbc; + wire [15:0] avl_writedata_top; + wire [15:0] avl_writedata_bot; + wire [31:0] avl_readdata_dbc; + wire [1:0] avl_write_dbc; + wire avl_sync_write_top; + wire avl_sync_write_bot; + wire avl_destruct_read_top; + wire avl_destruct_read_bot; + wire [3:0] rdata_valid_local; + wire chk_x12_track_out_up_top; + wire chk_x12_track_out_up_bot; + wire chk_x12_track_out_dn_top; + wire chk_x12_track_out_dn_bot; + wire [1:0] fifo_pack_select_top; + wire fifo_read_enable_top; + wire fifo_reset_n_top; + wire fifo_rank_sel_top; + wire [1:0] fifo_pack_select_bot; + wire fifo_read_enable_bot; + wire fifo_reset_n_bot; + wire fifo_rank_sel_bot; + wire [5:0] pvt_write; + wire [2:0] pvt_address_top; + wire [2:0] pvt_address_bot; + wire [8:0] pvt_data_top; + wire [8:0] pvt_data_bot; + wire [1:0] dqs_out_a_n; + wire [1:0] dqs_out_b_n; + wire [1:0] rank_in_a_top; + wire [1:0] rank_in_a_bot; + wire [1:0] rank_in_b_top; + wire [1:0] rank_in_b_bot; + wire [7:0] rank_out_top; + wire [7:0] rank_out_bot; + wire oct_enable_out_top; + wire oct_enable_out_bot; + wire rb_phy_clk_mode_bot; + wire [3:0] rb_track_speed_bot; + wire [1:0] rb_kicker_size_bot; + wire [1:0] rb_mode_rate_in_bot; + wire [1:0] rb_mode_rate_out_bot; + wire [1:0] rb_filter_code_bot; + wire rb_phy_clk_mode_top; + wire [3:0] rb_track_speed_top; + wire [1:0] rb_kicker_size_top; + wire [1:0] rb_mode_rate_in_top; + wire [1:0] rb_mode_rate_out_top; + wire [1:0] rb_filter_code_top; + wire rb_phy_clk_mode_right; + wire [5:0] sel_vref; + wire csr_clk_top; + wire csr_clk_bot; + wire csr_clk_dbc; + wire csr_en_top; + wire csr_en_bot; + wire csr_en_dbc; + wire csr_shift_n_top; + wire csr_shift_n_bot; + wire csr_shift_n_left; + wire csr_shift_n_dbc; + wire nfrzdrv_top; + wire nfrzdrv_bot; + wire frzreg_top; + wire frzreg_bot; + wire atpg_en_n_top; + wire atpg_en_n_bot; + wire atpg_en_n_left; + wire pipeline_global_en_n_top; + wire pipeline_global_en_n_bot; + wire pipeline_global_en_n_left; + wire test_clr_n_top; + wire test_clr_n_bot; + wire test_fr_clk_en_n_top; + wire test_fr_clk_en_n_bot; + wire test_hr_clk_en_n_top; + wire test_hr_clk_en_n_bot; + wire test_tdf_select_n_top; + wire test_tdf_select_n_bot; + wire niotri_top; + wire niotri_bot; + wire test_clk_top; + wire test_clk_bot; + wire test_clk_left; + wire scan_shift_n_top; + wire scan_shift_n_bot; + wire scan_shift_n_dbc; + wire scan_shift_n_left; + wire jtag_shftdr_top; + wire jtag_shftdr_bot; + wire jtag_clk_top; + wire jtag_clk_bot; + wire jtag_highz_top; + wire jtag_highz_bot; + wire jtag_updtdr_top; + wire jtag_updtdr_bot; + wire jtag_mode_top; + wire jtag_mode_bot; + wire [12:0] avl_select_ioereg; + wire [47:0] oeb_to_ioreg; + wire [95:0] data_to_ioreg; + wire [11:0] chk_x1_track_in_up; + wire [11:0] chk_x1_track_in_dn; + wire [11:0] chk_x1_track_out_up; + wire [11:0] chk_x1_track_out_dn; + wire chk_x12_track_in_up; + wire chk_x12_track_in_dn; + wire chk_x12_track_out_up; + wire chk_x12_track_out_dn; + wire [3:0] rdata_en_full_local; + wire [7:0] mrnk_read_local; + wire [7:0] mrnk_write_local; + wire [23:0] dqs_clk_a; + wire [23:0] dqs_clk_b; + wire [5:0] xor_clk; + wire test_phy_clk_lane_en_n_top; + wire test_phy_clk_lane_en_n_bot; + wire test_int_clk_en_n_top; + wire test_int_clk_en_n_bot; + wire test_interp_clk_en_n_top; + wire test_interp_clk_en_n_bot; + wire test_clk_ph_buf_en_n_top; + wire test_clk_ph_buf_en_n_bot; + wire test_datovr_en_n_top; + wire test_datovr_en_n_bot; + wire [11:0] dqs_probe; + wire [35:0] rd_probe; + wire [11:0] link_gpio_dout_n; + wire [11:0] link_gpio_oeb; + wire [11:0] select_ac_hmc; + wire [23:0] dq_in_del_n; + wire [23:0] dq_in_tree; + wire [11:0] test_dbg_out_local; + wire [5:0] sync_clk_up_chn; + wire [5:0] sync_data_up_chn; + wire [5:0] sync_clk_dn_chn; + wire [5:0] sync_data_dn_chn; + wire [7:0] x64_osc_chain_p; + wire [7:0] x64_osc_chain_n; + wire x64_osc_mode_out; + + wire [3:0] interpolator_clk_0; + wire [3:0] d_out_p_mux_0; + wire [3:0] d_out_n_mux_0; + wire [5:0] rb_dq_select_0; + wire [1:0] datovr_0; + wire [1:0] datovrb_0; + wire [1:0] data_dq_0; + wire [1:0] data_dqb_0; + wire [1:0] struct_latch_open_n_0; + wire [1:0] nfrzdrv_struct_0; + + wire [3:0] interpolator_clk_1; + wire [3:0] d_out_p_mux_1; + wire [3:0] d_out_n_mux_1; + wire [5:0] rb_dq_select_1; + wire [1:0] datovr_1; + wire [1:0] datovrb_1; + wire [1:0] data_dq_1; + wire [1:0] data_dqb_1; + wire [1:0] struct_latch_open_n_1; + wire [1:0] nfrzdrv_struct_1; + wire [3:0] interpolator_clk_2; + wire [3:0] d_out_p_mux_2; + wire [3:0] d_out_n_mux_2; + wire [5:0] rb_dq_select_2; + wire [1:0] datovr_2; + wire [1:0] datovrb_2; + wire [1:0] data_dq_2; + wire [1:0] data_dqb_2; + wire [1:0] struct_latch_open_n_2; + wire [1:0] nfrzdrv_struct_2; + wire [3:0] interpolator_clk_3; + wire [3:0] d_out_p_mux_3; + wire [3:0] d_out_n_mux_3; + wire [5:0] rb_dq_select_3; + wire [1:0] datovr_3; + wire [1:0] datovrb_3; + wire [1:0] data_dq_3; + wire [1:0] data_dqb_3; + wire [1:0] struct_latch_open_n_3; + wire [1:0] nfrzdrv_struct_3; + wire [3:0] interpolator_clk_4; + wire [3:0] d_out_p_mux_4; + wire [3:0] d_out_n_mux_4; + wire [5:0] rb_dq_select_4; + wire [1:0] datovr_4; + wire [1:0] datovrb_4; + wire [1:0] data_dq_4; + wire [1:0] data_dqb_4; + wire [1:0] struct_latch_open_n_4; + wire [1:0] nfrzdrv_struct_4; + wire [3:0] interpolator_clk_5; + wire [3:0] d_out_p_mux_5; + wire [3:0] d_out_n_mux_5; + wire [5:0] rb_dq_select_5; + wire [1:0] datovr_5; + wire [1:0] datovrb_5; + wire [1:0] data_dq_5; + wire [1:0] data_dqb_5; + wire [1:0] struct_latch_open_n_5; + wire [1:0] nfrzdrv_struct_5; + + wire [5:1] osc_in_up; + wire [5:0] osc_out_dn; + wire osc_start_in; + wire osc_start_out; + + wire ioereg_reset_n; + wire [1:0] dqs_loop_back_0; + wire [1:0] dqs_loop_back_1; + + wire dll_test_si1; + wire dll_test_si2; + wire dll_test_so1; + wire dll_test_so2; + + wire xpr_clk_bot; + wire xpr_clk_top; + wire [2:0] xpr_write_bot; + wire [2:0] xpr_write_top; + wire [7:0] xpr_data_bot; + wire [7:0] xpr_data_top; + wire test_i_n_dll; + wire test_i_p_pst; + wire test_dqs_o1; + wire test_dqs_o2; + + wire vcc_regphy; + wire db_csrin; + wire dqs_csrin; + + wire afi_cal_success; + +io_dft_mux__nf5es xdb_csrin_mux ( +.testin (test_db_csr_in), +.usrin (csr_in), +.s (scan_shift_n), +.out (db_csrin) +); + +io_dft_mux__nf5es xdqs_csrin_mux ( +.testin (test_dqs_csr_in), +.usrin ( ioereg_csrout[3]), +.s (scan_shift_n), +.out (dqs_csrin) + +); + +assign test_ioereg2_csr_out = ioereg_csrout[3]; +assign test_vref_csr_out = csr_out; + +io_ioereg_top__nf5es ioereg_top_0_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[1:0] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[1:0] ), +.core_data_out ( data_to_ioreg[15:0] ), +.core_oeb ( oeb_to_ioreg[7:0] ), +.core_data_in ( data_from_ioreg[15:0] ), +.avl_select ( avl_select_ioereg[1:0] ), +.dpa_track_out_up ( switch_up[0] ), +.dpa_track_out_dn ( switch_dn[0] ), +.phase_kicker ( dzoutx[0] ), +.phase_direction ( up_ph[0] ), +.interpolator_clk_p ( {next_clk[0],crnt_clk[0]} ), +.interpolator_clk_n ( {n_next_clk[0],n_crnt_clk[0]} ), +.codin_p ( codin_p[1:0] ), +.codin_pb ( codin_pb[1:0] ), +.codin_n ( codin_n[1:0] ), +.codin_nb ( codin_nb[1:0] ), +.dq_diff_in ( dq_diff_in[3:0] ), +.dq_sstl_in ( dq_sstl_in[3:0] ), +.dqs_clk_a ( dqs_clk_a[3:0] ), +.dqs_clk_b ( dqs_clk_b[3:0] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_bot ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_bot ), +.rb_phy_clk_mode ( rb_phy_clk_mode_bot ), +.rb_track_speed ( rb_track_speed_bot[3:0] ), +.rb_kicker_size ( rb_kicker_size_bot[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_bot[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_bot[1:0] ), +.rb_filter_code ( rb_filter_code_bot[1:0] ), +.fifo_pack_select ( fifo_pack_select_bot[1:0] ), +.fifo_read_enable ( fifo_read_enable_bot ), +.fifo_reset_n ( fifo_reset_n_bot ), +.fifo_rank_sel ( fifo_rank_sel_bot ), +.rank_in_a ( rank_in_a_bot[1:0] ), +.rank_in_b ( rank_in_b_bot[1:0] ), +.rank_out ( rank_out_bot[7:0] ), +.oct_enable_out ( oct_enable_out_bot ), +.oct_enable_pin ( oct_enable[1:0] ), +.avl_wr_address ( avl_wr_address_bot[3:0] ), +.avl_rd_address ( avl_rd_address_bot[3:0] ), +.avl_sync_write ( avl_sync_write_bot ), +.avl_destruct_read ( avl_destruct_read_bot ), +.avl_writedata ( avl_writedata_bot[15:0] ), +.avl_readchain_in ( 16'h0000 ), +.avl_readchain_out ( avl_readchain_bot[15:0] ), +.pvt_write ( pvt_write[0] ), +.pvt_address ( pvt_address_bot[2:0] ), +.pvt_data ( pvt_data_bot[8:0] ), +.csr_clk ( csr_clk_bot ), +.csr_in ( ioereg_csrout[0] ), +.csr_en ( csr_en_bot ), +.csr_shift_n ( 1'b1 ), +.csr_out ( ioereg_csrout[1] ), +.nfrzdrv ( nfrzdrv_bot ), +.frzreg ( frzreg_bot ), +.ncein ( ncein[1:0] ), +.nceout ( nceout[1:0] ), +.naclr ( naclr[1:0] ), +.nsclr ( nsclr[1:0] ), +.fr_in_clk ( fr_in_clk[1:0] ), +.hr_in_clk ( hr_in_clk[1:0] ), +.fr_out_clk ( fr_out_clk[1:0] ), +.hr_out_clk ( hr_out_clk[1:0] ), +.pll_clk ( 1'b0 ), +.atpg_en_n ( atpg_en_n_bot ), +.pipeline_global_en_n ( pipeline_global_en_n_bot ), +.test_clr_n ( test_clr_n_bot ), +.test_fr_clk_en_n ( test_fr_clk_en_n_bot ), +.test_hr_clk_en_n ( test_hr_clk_en_n_bot ), +.test_tdf_select_n ( test_tdf_select_n_bot ), +.tpin ( tpin[1:0] ), +.tpctl ( tpctl[1:0] ), +.tpdata ( tpdata[1:0] ), +.niotri ( niotri_bot ), +.progctl ( progctl[1:0] ), +.progout ( progout[1:0] ), +.progoe ( progoe[1:0] ), +.test_clk ( test_clk_bot ), +.scan_shift_n ( scan_shift_n_bot ), +.scan_in ( scanin[0] ), +.scan_out ( scanout[0] ), +.xor_clk ( xor_clk[0] ), +.test_dbg_out ( test_dbg_out_local[1:0] ), +.test_dbg_in ( test_dbg_in[1:0] ), +.probe_out ( {dqs_probe[1:0],rd_probe[17:0]}), +.read_path_probe ( rd_probe[5:0] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_bot ), +.test_int_clk_en_n ( test_int_clk_en_n_bot ), +.test_interp_clk_en_n ( test_interp_clk_en_n_bot ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_bot ), +.test_datovr_en_n ( test_datovr_en_n_bot ), +.jtag_shftdr ( jtag_shftdr_bot ), +.jtag_clk ( jtag_clk_bot ), +.jtag_highz ( jtag_highz_bot ), +.jtag_sdin ( jtag_sdin ), +.jtag_updtdr ( jtag_updtdr_bot ), +.jtag_mode ( jtag_mode_bot ), +.jtag_sdout ( ioereg_jtag_sdout[0] ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_out_dn[1] ), +.osc_in_up ( osc_out_dn[0] ), +.osc_out_dn ( osc_out_dn[0] ), +.osc_out_up ( osc_in_up[1] ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[0] ), +.x64_osc_in_n ( x64_osc_chain_n[0] ), +.x64_osc_out_p ( x64_osc_chain_p[1] ), +.x64_osc_out_n ( x64_osc_chain_n[1] ), +.sync_clk_bot_in ( sync_clk_bot_in ), +.sync_data_bot_in ( sync_data_bot_in ), +.sync_clk_bot_out ( sync_clk_bot_out ), +.sync_data_bot_out ( sync_data_bot_out ), +.sync_clk_top_in ( sync_clk_dn_chn[0] ), +.sync_data_top_in ( sync_data_dn_chn[0] ), +.sync_clk_top_out ( sync_clk_up_chn[0] ), +.sync_data_top_out ( sync_data_up_chn[0] ), +.interpolator_clk_out ( interpolator_clk_0[3:0] ), +.interpolator_clk_in ( interpolator_clk_0[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_0[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_0[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_0[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_0[3:0] ), +.rb_dq_select ( rb_dq_select_0[5:0] ), +.rb_dq_select_in ( rb_dq_select_0[5:0] ), +.datovr_out ( datovr_0[1:0] ), +.datovr_in ( datovr_0[1:0] ), +.datovrb_out ( datovrb_0[1:0] ), +.datovrb_in ( datovrb_0[1:0] ), +.data_dq_out ( data_dq_0[1:0] ), +.data_dq_in ( data_dq_0[1:0] ), +.data_dqb_out ( data_dqb_0[1:0] ), +.data_dqb_in ( data_dqb_0[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_0[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_0[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_0[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_0[1:0] ), +.ac_hmc ( ac_hmc[15:0] ), +.select_ac_hmc ( select_ac_hmc[1:0] ), +.dq_in_del ( dq_in_del_n[3:0] ), +.dq_in_tree ( dq_in_tree[3:0] ), +.dqs_loop_back ( ), +.xpr_clk ( xpr_clk_bot ), +.xpr_write ( xpr_write_bot[0] ), +.xpr_data ( xpr_data_bot[7:0] ), +.ioereg_locked ( ioereg_locked[0] ), +.weak_pullup_enable ( weak_pullup_enable[1:0] ) +); + +io_ioereg_top__nf5es ioereg_top_1_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[3:2] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[3:2] ), +.core_data_out ( data_to_ioreg[31:16] ), +.core_oeb ( oeb_to_ioreg[15:8] ), +.core_data_in ( data_from_ioreg[31:16] ), +.avl_select ( avl_select_ioereg[3:2] ), +.dpa_track_out_up ( switch_up[1] ), +.dpa_track_out_dn ( switch_dn[1] ), +.phase_kicker ( dzoutx[1] ), +.phase_direction ( up_ph[1] ), +.interpolator_clk_p ( {next_clk[1],crnt_clk[1]} ), +.interpolator_clk_n ( {n_next_clk[1],n_crnt_clk[1]} ), +.codin_p ( codin_p[3:2] ), +.codin_pb ( codin_pb[3:2] ), +.codin_n ( codin_n[3:2] ), +.codin_nb ( codin_nb[3:2] ), +.dq_diff_in ( dq_diff_in[7:4] ), +.dq_sstl_in ( dq_sstl_in[7:4] ), +.dqs_clk_a ( dqs_clk_a[7:4] ), +.dqs_clk_b ( dqs_clk_b[7:4] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_bot ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_bot ), +.rb_phy_clk_mode ( rb_phy_clk_mode_bot ), +.rb_track_speed ( rb_track_speed_bot[3:0] ), +.rb_kicker_size ( rb_kicker_size_bot[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_bot[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_bot[1:0] ), +.rb_filter_code ( rb_filter_code_bot[1:0] ), +.fifo_pack_select ( fifo_pack_select_bot[1:0] ), +.fifo_read_enable ( fifo_read_enable_bot ), +.fifo_reset_n ( fifo_reset_n_bot ), +.fifo_rank_sel ( fifo_rank_sel_bot ), +.rank_in_a ( rank_in_a_bot[1:0] ), +.rank_in_b ( rank_in_b_bot[1:0] ), +.rank_out ( rank_out_bot[7:0] ), +.oct_enable_out ( oct_enable_out_bot ), +.oct_enable_pin ( oct_enable[3:2] ), +.avl_wr_address ( avl_wr_address_bot[3:0] ), +.avl_rd_address ( avl_rd_address_bot[3:0] ), +.avl_sync_write ( avl_sync_write_bot ), +.avl_destruct_read ( avl_destruct_read_bot ), +.avl_writedata ( avl_writedata_bot[15:0] ), +.avl_readchain_in ( avl_readchain_bot[15:0] ), +.avl_readchain_out ( avl_readchain_bot[31:16] ), +.pvt_write ( pvt_write[1] ), +.pvt_address ( pvt_address_bot[2:0] ), +.pvt_data ( pvt_data_bot[8:0] ), +.csr_clk ( csr_clk_bot ), +.csr_in ( ioereg_csrout[1] ), +.csr_en ( csr_en_bot ), +.csr_shift_n ( 1'b1 ), +.csr_out ( ioereg_csrout[2] ), +.nfrzdrv ( nfrzdrv_bot ), +.frzreg ( frzreg_bot ), +.ncein ( ncein[3:2] ), +.nceout ( nceout[3:2] ), +.naclr ( naclr[3:2] ), +.nsclr ( nsclr[3:2] ), +.fr_in_clk ( fr_in_clk[3:2] ), +.hr_in_clk ( hr_in_clk[3:2] ), +.fr_out_clk ( fr_out_clk[3:2] ), +.hr_out_clk ( hr_out_clk[3:2] ), +.pll_clk ( 1'b0 ), +.atpg_en_n ( atpg_en_n_bot ), +.pipeline_global_en_n ( pipeline_global_en_n_bot ), +.test_clr_n ( test_clr_n_bot ), +.test_fr_clk_en_n ( test_fr_clk_en_n_bot ), +.test_hr_clk_en_n ( test_hr_clk_en_n_bot ), +.test_tdf_select_n ( test_tdf_select_n_bot ), +.tpin ( tpin[3:2] ), +.tpctl ( tpctl[3:2] ), +.tpdata ( tpdata[3:2] ), +.niotri ( niotri_bot ), +.progctl ( progctl[3:2] ), +.progout ( progout[3:2] ), +.progoe ( progoe[3:2] ), +.test_clk ( test_clk_bot ), +.scan_shift_n ( scan_shift_n_bot ), +.scan_in ( scanin[1] ), +.scan_out ( scanout[1] ), +.xor_clk ( xor_clk[1] ), +.test_dbg_out ( test_dbg_out_local[3:2] ), +.test_dbg_in ( test_dbg_in[3:2] ), +.probe_out ( {dqs_probe[3:2],rd_probe[17:0]}), +.read_path_probe ( rd_probe[11:6] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_bot ), +.test_int_clk_en_n ( test_int_clk_en_n_bot ), +.test_interp_clk_en_n ( test_interp_clk_en_n_bot ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_bot ), +.test_datovr_en_n ( test_datovr_en_n_bot ), +.jtag_shftdr ( jtag_shftdr_bot ), +.jtag_clk ( jtag_clk_bot ), +.jtag_highz ( jtag_highz_bot ), +.jtag_sdin ( ioereg_jtag_sdout[0] ), +.jtag_updtdr ( jtag_updtdr_bot ), +.jtag_mode ( jtag_mode_bot ), +.jtag_sdout ( ioereg_jtag_sdout[1] ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_out_dn[2] ), +.osc_in_up ( osc_in_up[1] ), +.osc_out_dn ( osc_out_dn[1] ), +.osc_out_up ( osc_in_up[2] ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[1] ), +.x64_osc_in_n ( x64_osc_chain_n[1] ), +.x64_osc_out_p ( x64_osc_chain_p[2] ), +.x64_osc_out_n ( x64_osc_chain_n[2] ), +.sync_clk_bot_in ( sync_clk_up_chn[0] ), +.sync_data_bot_in ( sync_data_up_chn[0] ), +.sync_clk_bot_out ( sync_clk_dn_chn[0] ), +.sync_data_bot_out ( sync_data_dn_chn[0] ), +.sync_clk_top_in ( sync_clk_dn_chn[1] ), +.sync_data_top_in ( sync_data_dn_chn[1] ), +.sync_clk_top_out ( sync_clk_up_chn[1] ), +.sync_data_top_out ( sync_data_up_chn[1] ), +.interpolator_clk_out ( interpolator_clk_1[3:0] ), +.interpolator_clk_in ( interpolator_clk_1[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_1[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_1[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_1[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_1[3:0] ), +.rb_dq_select ( rb_dq_select_1[5:0] ), +.rb_dq_select_in ( rb_dq_select_1[5:0] ), +.datovr_out ( datovr_1[1:0] ), +.datovr_in ( datovr_1[1:0] ), +.datovrb_out ( datovrb_1[1:0] ), +.datovrb_in ( datovrb_1[1:0] ), +.data_dq_out ( data_dq_1[1:0] ), +.data_dq_in ( data_dq_1[1:0] ), +.data_dqb_out ( data_dqb_1[1:0] ), +.data_dqb_in ( data_dqb_1[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_1[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_1[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_1[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_1[1:0] ), +.ac_hmc ( ac_hmc[31:16] ), +.select_ac_hmc ( select_ac_hmc[3:2] ), +.dq_in_del ( dq_in_del_n[7:4] ), +.dq_in_tree ( dq_in_tree[7:4] ), +.dqs_loop_back ( ), +.xpr_clk ( xpr_clk_bot ), +.xpr_write ( xpr_write_bot[1] ), +.xpr_data ( xpr_data_bot[7:0] ), +.ioereg_locked ( ioereg_locked[1] ), +.weak_pullup_enable ( weak_pullup_enable[3:2] ) +); + +io_ioereg_top__nf5es ioereg_top_2_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[5:4] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[5:4] ), +.core_data_out ( data_to_ioreg[47:32] ), +.core_oeb ( oeb_to_ioreg[23:16] ), +.core_data_in ( data_from_ioreg[47:32] ), +.avl_select ( avl_select_ioereg[5:4] ), +.dpa_track_out_up ( switch_up[2] ), +.dpa_track_out_dn ( switch_dn[2] ), +.phase_kicker ( dzoutx[2] ), +.phase_direction ( up_ph[2] ), +.interpolator_clk_p ( {next_clk[2],crnt_clk[2]} ), +.interpolator_clk_n ( {n_next_clk[2],n_crnt_clk[2]} ), +.codin_p ( codin_p[5:4] ), +.codin_pb ( codin_pb[5:4] ), +.codin_n ( codin_n[5:4] ), +.codin_nb ( codin_nb[5:4] ), +.dq_diff_in ( dq_diff_in[11:8] ), +.dq_sstl_in ( dq_sstl_in[11:8] ), +.dqs_clk_a ( dqs_clk_a[11:8] ), +.dqs_clk_b ( dqs_clk_b[11:8] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_bot ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_bot ), +.rb_phy_clk_mode ( rb_phy_clk_mode_bot ), +.rb_track_speed ( rb_track_speed_bot[3:0] ), +.rb_kicker_size ( rb_kicker_size_bot[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_bot[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_bot[1:0] ), +.rb_filter_code ( rb_filter_code_bot[1:0] ), +.fifo_pack_select ( fifo_pack_select_bot[1:0] ), +.fifo_read_enable ( fifo_read_enable_bot ), +.fifo_reset_n ( fifo_reset_n_bot ), +.fifo_rank_sel ( fifo_rank_sel_bot ), +.rank_in_a ( rank_in_a_bot[1:0] ), +.rank_in_b ( rank_in_b_bot[1:0] ), +.rank_out ( rank_out_bot[7:0] ), +.oct_enable_out ( oct_enable_out_bot ), +.oct_enable_pin ( oct_enable[5:4] ), +.avl_wr_address ( avl_wr_address_bot[3:0] ), +.avl_rd_address ( avl_rd_address_bot[3:0] ), +.avl_sync_write ( avl_sync_write_bot ), +.avl_destruct_read ( avl_destruct_read_bot ), +.avl_writedata ( avl_writedata_bot[15:0] ), +.avl_readchain_in ( avl_readchain_bot[31:16] ), +.avl_readchain_out ( avl_readchain_bot[47:32] ), +.pvt_write ( pvt_write[2] ), +.pvt_address ( pvt_address_bot[2:0] ), +.pvt_data ( pvt_data_bot[8:0] ), +.csr_clk ( csr_clk_bot ), +.csr_in ( ioereg_csrout[2] ), +.csr_en ( csr_en_bot ), +.csr_shift_n ( csr_shift_n_bot ), +.csr_out ( ioereg_csrout[3] ), +.nfrzdrv ( nfrzdrv_bot ), +.frzreg ( frzreg_bot ), +.ncein ( ncein[5:4] ), +.nceout ( nceout[5:4] ), +.naclr ( naclr[5:4] ), +.nsclr ( nsclr[5:4] ), +.fr_in_clk ( fr_in_clk[5:4] ), +.hr_in_clk ( hr_in_clk[5:4] ), +.fr_out_clk ( fr_out_clk[5:4] ), +.hr_out_clk ( hr_out_clk[5:4] ), +.pll_clk ( pll_clk ), +.atpg_en_n ( atpg_en_n_bot ), +.pipeline_global_en_n ( pipeline_global_en_n_bot ), +.test_clr_n ( test_clr_n_bot ), +.test_fr_clk_en_n ( test_fr_clk_en_n_bot ), +.test_hr_clk_en_n ( test_hr_clk_en_n_bot ), +.test_tdf_select_n ( test_tdf_select_n_bot ), +.tpin ( tpin[5:4] ), +.tpctl ( tpctl[5:4] ), +.tpdata ( tpdata[5:4] ), +.niotri ( niotri_bot ), +.progctl ( progctl[5:4] ), +.progout ( progout[5:4] ), +.progoe ( progoe[5:4] ), +.test_clk ( test_clk_bot ), +.scan_shift_n ( scan_shift_n_bot ), +.scan_in ( scanin[2] ), +.scan_out ( scanout[2] ), +.xor_clk ( xor_clk[2] ), +.test_dbg_out ( test_dbg_out_local[5:4] ), +.test_dbg_in ( test_dbg_in[5:4] ), +.probe_out ( {dqs_probe[5:4],rd_probe[17:0]}), +.read_path_probe ( rd_probe[17:12] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_bot ), +.test_int_clk_en_n ( test_int_clk_en_n_bot ), +.test_interp_clk_en_n ( test_interp_clk_en_n_bot ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_bot ), +.test_datovr_en_n ( test_datovr_en_n_bot ), +.jtag_shftdr ( jtag_shftdr_bot ), +.jtag_clk ( jtag_clk_bot ), +.jtag_highz ( jtag_highz_bot ), +.jtag_sdin ( ioereg_jtag_sdout[1] ), +.jtag_updtdr ( jtag_updtdr_bot ), +.jtag_mode ( jtag_mode_bot ), +.jtag_sdout ( ioereg_jtag_sdout[2] ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_out_dn[3] ), +.osc_in_up ( osc_in_up[2] ), +.osc_out_dn ( osc_out_dn[2] ), +.osc_out_up ( osc_in_up[3] ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[2] ), +.x64_osc_in_n ( x64_osc_chain_n[2] ), +.x64_osc_out_p ( x64_osc_chain_p[3] ), +.x64_osc_out_n ( x64_osc_chain_n[3] ), +.sync_clk_bot_in ( sync_clk_up_chn[1] ), +.sync_data_bot_in ( sync_data_up_chn[1] ), +.sync_clk_bot_out ( sync_clk_dn_chn[1] ), +.sync_data_bot_out ( sync_data_dn_chn[1] ), +.sync_clk_top_in ( sync_clk_dn_chn[2] ), +.sync_data_top_in ( sync_data_dn_chn[2] ), +.sync_clk_top_out ( sync_clk_up_chn[2] ), +.sync_data_top_out ( sync_data_up_chn[2] ), +.interpolator_clk_out ( interpolator_clk_2[3:0] ), +.interpolator_clk_in ( interpolator_clk_2[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_2[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_2[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_2[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_2[3:0] ), +.rb_dq_select ( rb_dq_select_2[5:0] ), +.rb_dq_select_in ( rb_dq_select_2[5:0] ), +.datovr_out ( datovr_2[1:0] ), +.datovr_in ( datovr_2[1:0] ), +.datovrb_out ( datovrb_2[1:0] ), +.datovrb_in ( datovrb_2[1:0] ), +.data_dq_out ( data_dq_2[1:0] ), +.data_dq_in ( data_dq_2[1:0] ), +.data_dqb_out ( data_dqb_2[1:0] ), +.data_dqb_in ( data_dqb_2[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_2[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_2[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_2[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_2[1:0] ), +.ac_hmc ( ac_hmc[47:32] ), +.select_ac_hmc ( select_ac_hmc[5:4] ), +.dq_in_del ( dq_in_del_n[11:8] ), +.dq_in_tree ( dq_in_tree[11:8] ), +.dqs_loop_back ( dqs_loop_back_0[1:0] ), +.xpr_clk ( xpr_clk_bot ), +.xpr_write ( xpr_write_bot[2] ), +.xpr_data ( xpr_data_bot[7:0] ), +.ioereg_locked ( ioereg_locked[2] ), +.weak_pullup_enable ( weak_pullup_enable[5:4] ) +); + +io_ioereg_top__nf5es ioereg_top_3_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[7:6] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[7:6] ), +.core_data_out ( data_to_ioreg[63:48] ), +.core_oeb ( oeb_to_ioreg[31:24] ), +.core_data_in ( data_from_ioreg[63:48] ), +.avl_select ( avl_select_ioereg[7:6] ), +.dpa_track_out_up ( switch_up[3] ), +.dpa_track_out_dn ( switch_dn[3] ), +.phase_kicker ( dzoutx[3] ), +.phase_direction ( up_ph[3] ), +.interpolator_clk_p ( {next_clk[3],crnt_clk[3]} ), +.interpolator_clk_n ( {n_next_clk[3],n_crnt_clk[3]} ), +.codin_p ( codin_p[7:6] ), +.codin_pb ( codin_pb[7:6] ), +.codin_n ( codin_n[7:6] ), +.codin_nb ( codin_nb[7:6] ), +.dq_diff_in ( dq_diff_in[15:12] ), +.dq_sstl_in ( dq_sstl_in[15:12] ), +.dqs_clk_a ( dqs_clk_a[15:12] ), +.dqs_clk_b ( dqs_clk_b[15:12] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_top ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_top ), +.rb_phy_clk_mode ( rb_phy_clk_mode_top ), +.rb_track_speed ( rb_track_speed_top[3:0] ), +.rb_kicker_size ( rb_kicker_size_top[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_top[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_top[1:0] ), +.rb_filter_code ( rb_filter_code_top[1:0] ), +.fifo_pack_select ( fifo_pack_select_top[1:0] ), +.fifo_read_enable ( fifo_read_enable_top ), +.fifo_reset_n ( fifo_reset_n_top ), +.fifo_rank_sel ( fifo_rank_sel_top ), +.rank_in_a ( rank_in_a_top[1:0] ), +.rank_in_b ( rank_in_b_top[1:0] ), +.rank_out ( rank_out_top[7:0] ), +.oct_enable_out ( oct_enable_out_top ), +.oct_enable_pin ( oct_enable[7:6] ), +.avl_wr_address ( avl_wr_address_top[3:0] ), +.avl_rd_address ( avl_rd_address_top[3:0] ), +.avl_sync_write ( avl_sync_write_top ), +.avl_destruct_read ( avl_destruct_read_top ), +.avl_writedata ( avl_writedata_top[15:0] ), +.avl_readchain_in ( avl_readchain_top[31:16] ), +.avl_readchain_out ( avl_readchain_top[47:32] ), +.pvt_write ( pvt_write[3] ), +.pvt_address ( pvt_address_top[2:0] ), +.pvt_data ( pvt_data_top[8:0] ), +.csr_clk ( csr_clk_top ), +.csr_in ( ioereg_csrout[4] ), +.csr_en ( csr_en_top ), +.csr_shift_n ( 1'b1 ), +.csr_out ( ioereg_csrout[5] ), +.nfrzdrv ( nfrzdrv_top ), +.frzreg ( frzreg_top ), +.ncein ( ncein[7:6] ), +.nceout ( nceout[7:6] ), +.naclr ( naclr[7:6] ), +.nsclr ( nsclr[7:6] ), +.fr_in_clk ( fr_in_clk[7:6] ), +.hr_in_clk ( hr_in_clk[7:6] ), +.fr_out_clk ( fr_out_clk[7:6] ), +.hr_out_clk ( hr_out_clk[7:6] ), +.pll_clk ( pll_clk ), +.atpg_en_n ( atpg_en_n_top ), +.pipeline_global_en_n ( pipeline_global_en_n_top ), +.test_clr_n ( test_clr_n_top ), +.test_fr_clk_en_n ( test_fr_clk_en_n_top ), +.test_hr_clk_en_n ( test_hr_clk_en_n_top ), +.test_tdf_select_n ( test_tdf_select_n_top ), +.tpin ( tpin[7:6] ), +.tpctl ( tpctl[7:6] ), +.tpdata ( tpdata[7:6] ), +.niotri ( niotri_top ), +.progctl ( progctl[7:6] ), +.progout ( progout[7:6] ), +.progoe ( progoe[7:6] ), +.test_clk ( test_clk_top ), +.scan_shift_n ( scan_shift_n_top ), +.scan_in ( scanin[3] ), +.scan_out ( scanout[3] ), +.xor_clk ( xor_clk[3] ), +.test_dbg_out ( test_dbg_out_local[7:6] ), +.test_dbg_in ( test_dbg_in[7:6] ), +.probe_out ( {dqs_probe[7:6],rd_probe[35:18]} ), +.read_path_probe ( rd_probe[23:18] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_top ), +.test_int_clk_en_n ( test_int_clk_en_n_top ), +.test_interp_clk_en_n ( test_interp_clk_en_n_top ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_top ), +.test_datovr_en_n ( test_datovr_en_n_top ), +.jtag_shftdr ( jtag_shftdr_top ), +.jtag_clk ( jtag_clk_top ), +.jtag_highz ( jtag_highz_top ), +.jtag_sdin ( ioereg_jtag_sdout[2] ), +.jtag_updtdr ( jtag_updtdr_top ), +.jtag_mode ( jtag_mode_top ), +.jtag_sdout ( ioereg_jtag_sdout[3] ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_out_dn[4] ), +.osc_in_up ( osc_in_up[3] ), +.osc_out_dn ( osc_out_dn[3] ), +.osc_out_up ( osc_in_up[4] ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[3] ), +.x64_osc_in_n ( x64_osc_chain_n[3] ), +.x64_osc_out_p ( x64_osc_chain_p[4] ), +.x64_osc_out_n ( x64_osc_chain_n[4] ), +.sync_clk_bot_in ( sync_clk_up_chn[3] ), +.sync_data_bot_in ( sync_data_up_chn[3] ), +.sync_clk_bot_out ( sync_clk_dn_chn[3] ), +.sync_data_bot_out ( sync_data_dn_chn[3] ), +.sync_clk_top_in ( sync_clk_dn_chn[4] ), +.sync_data_top_in ( sync_data_dn_chn[4] ), +.sync_clk_top_out ( sync_clk_up_chn[4] ), +.sync_data_top_out ( sync_data_up_chn[4] ), +.interpolator_clk_out ( interpolator_clk_3[3:0] ), +.interpolator_clk_in ( interpolator_clk_3[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_3[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_3[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_3[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_3[3:0] ), +.rb_dq_select ( rb_dq_select_3[5:0] ), +.rb_dq_select_in ( rb_dq_select_3[5:0] ), +.datovr_out ( datovr_3[1:0] ), +.datovr_in ( datovr_3[1:0] ), +.datovrb_out ( datovrb_3[1:0] ), +.datovrb_in ( datovrb_3[1:0] ), +.data_dq_out ( data_dq_3[1:0] ), +.data_dq_in ( data_dq_3[1:0] ), +.data_dqb_out ( data_dqb_3[1:0] ), +.data_dqb_in ( data_dqb_3[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_3[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_3[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_3[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_3[1:0] ), +.ac_hmc ( ac_hmc[63:48] ), +.select_ac_hmc ( select_ac_hmc[7:6] ), +.dq_in_del ( dq_in_del_n[15:12] ), +.dq_in_tree ( dq_in_tree[15:12] ), +.dqs_loop_back ( dqs_loop_back_1[1:0] ), +.xpr_clk ( xpr_clk_top ), +.xpr_write ( xpr_write_top[0] ), +.xpr_data ( xpr_data_top[7:0] ), +.ioereg_locked ( ioereg_locked[3] ), +.weak_pullup_enable ( weak_pullup_enable[7:6] ) +); + +io_ioereg_top__nf5es ioereg_top_4_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[9:8] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[9:8] ), +.core_data_out ( data_to_ioreg[79:64] ), +.core_oeb ( oeb_to_ioreg[39:32] ), +.core_data_in ( data_from_ioreg[79:64] ), +.avl_select ( avl_select_ioereg[9:8] ), +.dpa_track_out_up ( switch_up[4] ), +.dpa_track_out_dn ( switch_dn[4] ), +.phase_kicker ( dzoutx[4] ), +.phase_direction ( up_ph[4] ), +.interpolator_clk_p ( {next_clk[4],crnt_clk[4]} ), +.interpolator_clk_n ( {n_next_clk[4],n_crnt_clk[4]} ), +.codin_p ( codin_p[9:8] ), +.codin_pb ( codin_pb[9:8] ), +.codin_n ( codin_n[9:8] ), +.codin_nb ( codin_nb[9:8] ), +.dq_diff_in ( dq_diff_in[19:16] ), +.dq_sstl_in ( dq_sstl_in[19:16] ), +.dqs_clk_a ( dqs_clk_a[19:16] ), +.dqs_clk_b ( dqs_clk_b[19:16] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_top ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_top ), +.rb_phy_clk_mode ( rb_phy_clk_mode_top ), +.rb_track_speed ( rb_track_speed_top[3:0] ), +.rb_kicker_size ( rb_kicker_size_top[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_top[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_top[1:0] ), +.rb_filter_code ( rb_filter_code_top[1:0] ), +.fifo_pack_select ( fifo_pack_select_top[1:0] ), +.fifo_read_enable ( fifo_read_enable_top ), +.fifo_reset_n ( fifo_reset_n_top ), +.fifo_rank_sel ( fifo_rank_sel_top ), +.rank_in_a ( rank_in_a_top[1:0] ), +.rank_in_b ( rank_in_b_top[1:0] ), +.rank_out ( rank_out_top[7:0] ), +.oct_enable_out ( oct_enable_out_top ), +.oct_enable_pin ( oct_enable[9:8] ), +.avl_wr_address ( avl_wr_address_top[3:0] ), +.avl_rd_address ( avl_rd_address_top[3:0] ), +.avl_sync_write ( avl_sync_write_top ), +.avl_destruct_read ( avl_destruct_read_top ), +.avl_writedata ( avl_writedata_top[15:0] ), +.avl_readchain_in ( avl_readchain_top[15:0] ), +.avl_readchain_out ( avl_readchain_top[31:16] ), +.pvt_write ( pvt_write[4] ), +.pvt_address ( pvt_address_top[2:0] ), +.pvt_data ( pvt_data_top[8:0] ), +.csr_clk ( csr_clk_top ), +.csr_in ( ioereg_csrout[5] ), +.csr_en ( csr_en_top ), +.csr_shift_n ( 1'b1 ), +.csr_out ( ioereg_csrout[6] ), +.nfrzdrv ( nfrzdrv_top ), +.frzreg ( frzreg_top ), +.ncein ( ncein[9:8] ), +.nceout ( nceout[9:8] ), +.naclr ( naclr[9:8] ), +.nsclr ( nsclr[9:8] ), +.fr_in_clk ( fr_in_clk[9:8] ), +.hr_in_clk ( hr_in_clk[9:8] ), +.fr_out_clk ( fr_out_clk[9:8] ), +.hr_out_clk ( hr_out_clk[9:8] ), +.pll_clk ( 1'b0 ), +.atpg_en_n ( atpg_en_n_top ), +.pipeline_global_en_n ( pipeline_global_en_n_top ), +.test_clr_n ( test_clr_n_top ), +.test_fr_clk_en_n ( test_fr_clk_en_n_top ), +.test_hr_clk_en_n ( test_hr_clk_en_n_top ), +.test_tdf_select_n ( test_tdf_select_n_top ), +.tpin ( tpin[9:8] ), +.tpctl ( tpctl[9:8] ), +.tpdata ( tpdata[9:8] ), +.niotri ( niotri_top ), +.progctl ( progctl[9:8] ), +.progout ( progout[9:8] ), +.progoe ( progoe[9:8] ), +.test_clk ( test_clk_top ), +.scan_shift_n ( scan_shift_n_top ), +.scan_in ( scanin[4] ), +.scan_out ( scanout[4] ), +.xor_clk ( xor_clk[4] ), +.test_dbg_out ( test_dbg_out_local[9:8] ), +.test_dbg_in ( test_dbg_in[9:8] ), +.probe_out ( {dqs_probe[9:8],rd_probe[35:18]} ), +.read_path_probe ( rd_probe[29:24] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_top ), +.test_int_clk_en_n ( test_int_clk_en_n_top ), +.test_interp_clk_en_n ( test_interp_clk_en_n_top ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_top ), +.test_datovr_en_n ( test_datovr_en_n_top ), +.jtag_shftdr ( jtag_shftdr_top ), +.jtag_clk ( jtag_clk_top ), +.jtag_highz ( jtag_highz_top ), +.jtag_sdin ( ioereg_jtag_sdout[3] ), +.jtag_updtdr ( jtag_updtdr_top ), +.jtag_mode ( jtag_mode_top ), +.jtag_sdout ( ioereg_jtag_sdout[4] ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_out_dn[5] ), +.osc_in_up ( osc_in_up[4] ), +.osc_out_dn ( osc_out_dn[4] ), +.osc_out_up ( osc_in_up[5] ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[4] ), +.x64_osc_in_n ( x64_osc_chain_n[4] ), +.x64_osc_out_p ( x64_osc_chain_p[5] ), +.x64_osc_out_n ( x64_osc_chain_n[5] ), +.sync_clk_bot_in ( sync_clk_up_chn[4] ), +.sync_data_bot_in ( sync_data_up_chn[4] ), +.sync_clk_bot_out ( sync_clk_dn_chn[4] ), +.sync_data_bot_out ( sync_data_dn_chn[4] ), +.sync_clk_top_in ( sync_clk_dn_chn[5] ), +.sync_data_top_in ( sync_data_dn_chn[5] ), +.sync_clk_top_out ( sync_clk_up_chn[5] ), +.sync_data_top_out ( sync_data_up_chn[5] ), +.interpolator_clk_out ( interpolator_clk_4[3:0] ), +.interpolator_clk_in ( interpolator_clk_4[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_4[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_4[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_4[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_4[3:0] ), +.rb_dq_select ( rb_dq_select_4[5:0] ), +.rb_dq_select_in ( rb_dq_select_4[5:0] ), +.datovr_out ( datovr_4[1:0] ), +.datovr_in ( datovr_4[1:0] ), +.datovrb_out ( datovrb_4[1:0] ), +.datovrb_in ( datovrb_4[1:0] ), +.data_dq_out ( data_dq_4[1:0] ), +.data_dq_in ( data_dq_4[1:0] ), +.data_dqb_out ( data_dqb_4[1:0] ), +.data_dqb_in ( data_dqb_4[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_4[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_4[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_4[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_4[1:0] ), +.ac_hmc ( ac_hmc[79:64] ), +.select_ac_hmc ( select_ac_hmc[9:8] ), +.dq_in_del ( dq_in_del_n[19:16] ), +.dq_in_tree ( dq_in_tree[19:16] ), +.dqs_loop_back ( ), +.xpr_clk ( xpr_clk_top ), +.xpr_write ( xpr_write_top[1] ), +.xpr_data ( xpr_data_top[7:0] ), +.ioereg_locked ( ioereg_locked[4] ), +.weak_pullup_enable ( weak_pullup_enable[9:8] ) +); + +io_ioereg_top__nf5es ioereg_top_5_ ( +.reset_n ( ioereg_reset_n ), +.phy_clk_phs ( 8'd0 ), +.phy_clk ( 'd0 ), +.chk_x1_track_out_up ( chk_x1_track_out_up[11:10] ), +.chk_x1_track_out_dn ( chk_x1_track_out_dn[11:10] ), +.core_data_out ( data_to_ioreg[95:80] ), +.core_oeb ( oeb_to_ioreg[47:40] ), +.core_data_in ( data_from_ioreg[95:80] ), +.avl_select ( avl_select_ioereg[11:10] ), +.dpa_track_out_up ( switch_up[5] ), +.dpa_track_out_dn ( switch_dn[5] ), +.phase_kicker ( dzoutx[5] ), +.phase_direction ( up_ph[5] ), +.interpolator_clk_p ( {next_clk[5],crnt_clk[5]} ), +.interpolator_clk_n ( {n_next_clk[5],n_crnt_clk[5]} ), +.codin_p ( codin_p[11:10] ), +.codin_pb ( codin_pb[11:10] ), +.codin_n ( codin_n[11:10] ), +.codin_nb ( codin_nb[11:10] ), +.dq_diff_in ( dq_diff_in[23:20] ), +.dq_sstl_in ( dq_sstl_in[23:20] ), +.dqs_clk_a ( dqs_clk_a[23:20] ), +.dqs_clk_b ( dqs_clk_b[23:20] ), +.chk_x12_track_out_up ( chk_x12_track_out_up_top ), +.chk_x12_track_out_dn ( chk_x12_track_out_dn_top ), +.rb_phy_clk_mode ( rb_phy_clk_mode_top ), +.rb_track_speed ( rb_track_speed_top[3:0] ), +.rb_kicker_size ( rb_kicker_size_top[1:0] ), +.rb_mode_rate_in ( rb_mode_rate_in_top[1:0] ), +.rb_mode_rate_out ( rb_mode_rate_out_top[1:0] ), +.rb_filter_code ( rb_filter_code_top[1:0] ), +.fifo_pack_select ( fifo_pack_select_top[1:0] ), +.fifo_read_enable ( fifo_read_enable_top ), +.fifo_reset_n ( fifo_reset_n_top ), +.fifo_rank_sel ( fifo_rank_sel_top ), +.rank_in_a ( rank_in_a_top[1:0] ), +.rank_in_b ( rank_in_b_top[1:0] ), +.rank_out ( rank_out_top[7:0] ), +.oct_enable_out ( oct_enable_out_top ), +.oct_enable_pin ( oct_enable[11:10] ), +.avl_wr_address ( avl_wr_address_top[3:0] ), +.avl_rd_address ( avl_rd_address_top[3:0] ), +.avl_sync_write ( avl_sync_write_top ), +.avl_destruct_read ( avl_destruct_read_top ), +.avl_writedata ( avl_writedata_top[15:0] ), +.avl_readchain_in ( 16'h0000 ), +.avl_readchain_out ( avl_readchain_top[15:0] ), +.pvt_write ( pvt_write[5] ), +.pvt_address ( pvt_address_top[2:0] ), +.pvt_data ( pvt_data_top[8:0] ), +.csr_clk ( csr_clk_top ), +.csr_in ( ioereg_csrout[6] ), +.csr_en ( csr_en_top ), +.csr_shift_n ( 1'b1 ), +.csr_out ( ioereg_csrout[7] ), +.nfrzdrv ( nfrzdrv_top ), +.frzreg ( frzreg_top ), +.ncein ( ncein[11:10] ), +.nceout ( nceout[11:10] ), +.naclr ( naclr[11:10] ), +.nsclr ( nsclr[11:10] ), +.fr_in_clk ( fr_in_clk[11:10] ), +.hr_in_clk ( hr_in_clk[11:10] ), +.fr_out_clk ( fr_out_clk[11:10] ), +.hr_out_clk ( hr_out_clk[11:10] ), +.pll_clk ( 1'b0 ), +.atpg_en_n ( atpg_en_n_top ), +.pipeline_global_en_n ( pipeline_global_en_n_top ), +.test_clr_n ( test_clr_n_top ), +.test_fr_clk_en_n ( test_fr_clk_en_n_top ), +.test_hr_clk_en_n ( test_hr_clk_en_n_top ), +.test_tdf_select_n ( test_tdf_select_n_top ), +.tpin ( tpin[11:10] ), +.tpctl ( tpctl[11:10] ), +.tpdata ( tpdata[11:10] ), +.niotri ( niotri_top ), +.progctl ( progctl[11:10] ), +.progout ( progout[11:10] ), +.progoe ( progoe[11:10] ), +.test_clk ( test_clk_top ), +.scan_shift_n ( scan_shift_n_top ), +.scan_in ( scanin[5] ), +.scan_out ( scanout[5] ), +.xor_clk ( xor_clk[5] ), +.test_dbg_out ( test_dbg_out_local[11:10] ), +.test_dbg_in ( test_dbg_in[11:10] ), +.probe_out ( {dqs_probe[11:10],rd_probe[35:18]}), +.read_path_probe ( rd_probe[35:30] ), +.test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n_top ), +.test_int_clk_en_n ( test_int_clk_en_n_top ), +.test_interp_clk_en_n ( test_interp_clk_en_n_top ), +.test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n_top ), +.test_datovr_en_n ( test_datovr_en_n_top ), +.jtag_shftdr ( jtag_shftdr_top ), +.jtag_clk ( jtag_clk_top ), +.jtag_highz ( jtag_highz_top ), +.jtag_sdin ( ioereg_jtag_sdout[4] ), +.jtag_updtdr ( jtag_updtdr_top ), +.jtag_mode ( jtag_mode_top ), +.jtag_sdout ( jtag_sdout ), +.osc_sel_n ( osc_sel_n ), +.osc_in_dn ( osc_start_in ), +.osc_in_up ( osc_in_up[5] ), +.osc_out_dn ( osc_out_dn[5] ), +.osc_out_up ( osc_start_out ), +.x64_osc_mode ( x64_osc_mode_out ), +.x64_osc_in_p ( x64_osc_chain_p[5] ), +.x64_osc_in_n ( x64_osc_chain_n[5] ), +.x64_osc_out_p ( x64_osc_chain_p[6] ), +.x64_osc_out_n ( x64_osc_chain_n[6] ), +.sync_clk_bot_in ( sync_clk_up_chn[5] ), +.sync_data_bot_in ( sync_data_up_chn[5] ), +.sync_clk_bot_out ( sync_clk_dn_chn[5] ), +.sync_data_bot_out ( sync_data_dn_chn[5] ), +.sync_clk_top_in ( sync_clk_top_in ), +.sync_data_top_in ( sync_data_top_in ), +.sync_clk_top_out ( sync_clk_top_out ), +.sync_data_top_out ( sync_data_top_out ), +.interpolator_clk_out ( interpolator_clk_5[3:0] ), +.interpolator_clk_in ( interpolator_clk_5[3:0] ), +.d_out_p_mux_out ( d_out_p_mux_5[3:0] ), +.d_out_p_mux_in ( d_out_p_mux_5[3:0] ), +.d_out_n_mux_out ( d_out_n_mux_5[3:0] ), +.d_out_n_mux_in ( d_out_n_mux_5[3:0] ), +.rb_dq_select ( rb_dq_select_5[5:0] ), +.rb_dq_select_in ( rb_dq_select_5[5:0] ), +.datovr_out ( datovr_5[1:0] ), +.datovr_in ( datovr_5[1:0] ), +.datovrb_out ( datovrb_5[1:0] ), +.datovrb_in ( datovrb_5[1:0] ), +.data_dq_out ( data_dq_5[1:0] ), +.data_dq_in ( data_dq_5[1:0] ), +.data_dqb_out ( data_dqb_5[1:0] ), +.data_dqb_in ( data_dqb_5[1:0] ), +.struct_latch_open_n_out( struct_latch_open_n_5[1:0] ), +.nfrzdrv_struct_out ( nfrzdrv_struct_5[1:0] ), +.struct_latch_open_n_in ( struct_latch_open_n_5[1:0] ), +.nfrzdrv_struct_in ( nfrzdrv_struct_5[1:0] ), +.ac_hmc ( ac_hmc[95:80] ), +.select_ac_hmc ( select_ac_hmc[11:10] ), +.dq_in_del ( dq_in_del_n[23:20] ), +.dq_in_tree ( dq_in_tree[23:20] ), +.dqs_loop_back ( ), +.xpr_clk ( xpr_clk_top ), +.xpr_write ( xpr_write_top[2] ), +.xpr_data ( xpr_data_top[7:0] ), +.ioereg_locked ( ioereg_locked[5] ), +.weak_pullup_enable ( weak_pullup_enable[11:10] ) +); + +io_dqs_lgc_top__nf5es xio_dqs_lgc_top ( + .reset_n ( ioereg_reset_n ), + .phy_clk_phs ( 8'd0 ), + .phy_clk ( afi_cal_success ? 'd0 : phy_clk[1:0] ), + .broadcast_in_top ( broadcast_in_top ), + .broadcast_in_bot ( broadcast_in_bot ), + .broadcast_out_top ( broadcast_out_top ), + .broadcast_out_bot ( broadcast_out_bot ), + .avl_clk_in ( avl_clk_in ), + .avl_clk_out ( avl_clk_out ), + .avl_address_in ( avl_address_in[19:0] ), + .avl_address_out ( avl_address_out[19:0] ), + .avl_address_dbc ( avl_address_dbc[19:0] ), + .avl_wr_address_top ( avl_wr_address_top[3:0] ), + .avl_rd_address_top ( avl_rd_address_top[3:0] ), + .avl_wr_address_bot ( avl_wr_address_bot[3:0] ), + .avl_rd_address_bot ( avl_rd_address_bot[3:0] ), + .avl_writedata_in ( avl_writedata_in[31:0] ), + .avl_writedata_out ( avl_writedata_out[31:0] ), + .avl_writedata_dbc ( avl_writedata_dbc[31:0] ), + .avl_writedata_top ( avl_writedata_top[15:0] ), + .avl_writedata_bot ( avl_writedata_bot[15:0] ), + .avl_readdata_in ( avl_readdata_in[31:0] ), + .avl_readdata_out ( avl_readdata_out[31:0] ), + .avl_readdata_dbc ( avl_readdata_dbc[31:0] ), + .avl_readchain_top ( avl_readchain_top[47:32] ), + .avl_readchain_bot ( avl_readchain_bot[47:32] ), + .avl_write_in ( avl_write_in ), + .avl_write_out ( avl_write_out ), + .avl_write_dbc ( avl_write_dbc[1:0] ), + .avl_sync_write_top ( avl_sync_write_top ), + .avl_sync_write_bot ( avl_sync_write_bot ), + .avl_read_in ( avl_read_in ), + .avl_read_out ( avl_read_out ), + .avl_destruct_read_top ( avl_destruct_read_top ), + .avl_destruct_read_bot ( avl_destruct_read_bot ), + .avl_select ( avl_select_ioereg[12] ), + .afi_rddata_en_full ( rdata_en_full_local[3:0] ), + .afi_mrnk_read ( mrnk_read_local[7:0] ), + .afi_mrnk_write ( mrnk_write_local[7:0] ), + .afi_rddata_valid ( ), + .chk_x1_track_in_up ( chk_x1_track_in_up[11:0] ), + .chk_x1_track_in_dn ( chk_x1_track_in_dn[11:0] ), + .chk_x12_track_in_up ( chk_x12_track_in_up ), + .chk_x12_track_in_dn ( chk_x12_track_in_dn ), + .chk_x12_track_out_up ( chk_x12_track_out_up ), + .chk_x12_track_out_dn ( chk_x12_track_out_dn ), + .chk_x12_track_out_up_top ( chk_x12_track_out_up_top ), + .chk_x12_track_out_up_bot ( chk_x12_track_out_up_bot ), + .chk_x12_track_out_dn_top ( chk_x12_track_out_dn_top ), + .chk_x12_track_out_dn_bot ( chk_x12_track_out_dn_bot ), + .fifo_pack_select_top ( fifo_pack_select_top[1:0] ), + .fifo_read_enable_top ( fifo_read_enable_top ), + .fifo_reset_n_top ( fifo_reset_n_top ), + .fifo_rank_sel_top ( fifo_rank_sel_top ), + .fifo_pack_select_bot ( fifo_pack_select_bot[1:0] ), + .fifo_read_enable_bot ( fifo_read_enable_bot ), + .fifo_reset_n_bot ( fifo_reset_n_bot ), + .fifo_rank_sel_bot ( fifo_rank_sel_bot ), + .dqs_diff_in_0 ( dqs_diff_in_0[1:0] ), + .dqs_diff_in_1 ( dqs_diff_in_1[1:0] ), + .dqs_diff_in_2 ( dqs_diff_in_2[1:0] ), + .dqs_diff_in_3 ( dqs_diff_in_3[1:0] ), + .dqs_sstl_p_0 ( dqs_sstl_p_0[1:0] ), + .dqs_sstl_p_1 ( dqs_sstl_p_1[1:0] ), + .dqs_sstl_p_2 ( dqs_sstl_p_2[1:0] ), + .dqs_sstl_p_3 ( dqs_sstl_p_3[1:0] ), + .dqs_sstl_n_0 ( dqs_sstl_n_0[1:0] ), + .dqs_sstl_n_1 ( dqs_sstl_n_1[1:0] ), + .dqs_sstl_n_2 ( dqs_sstl_n_2[1:0] ), + .dqs_sstl_n_3 ( dqs_sstl_n_3[1:0] ), + .pvt_ref_gry ( pvt_ref_gry[9:0] ), + .pvt_write ( pvt_write[5:0] ), + .pvt_address_top ( pvt_address_top[2:0] ), + .pvt_address_bot ( pvt_address_bot[2:0] ), + .pvt_data_top ( pvt_data_top[8:0] ), + .pvt_data_bot ( pvt_data_bot[8:0] ), + .dqs_out_a ( dqs_out_a_n[1:0] ), + .dqs_out_b ( dqs_out_b_n[1:0] ), + .rank_in_a_top ( rank_in_a_top[1:0] ), + .rank_in_a_bot ( rank_in_a_bot[1:0] ), + .rank_in_b_top ( rank_in_b_top[1:0] ), + .rank_in_b_bot ( rank_in_b_bot[1:0] ), + .rank_out_top ( rank_out_top[7:0] ), + .rank_out_bot ( rank_out_bot[7:0] ), + .oct_enable_out_top ( oct_enable_out_top ), + .oct_enable_out_bot ( oct_enable_out_bot ), + .rb_phy_clk_mode_bot ( rb_phy_clk_mode_bot ), + .rb_track_speed_bot ( rb_track_speed_bot[3:0] ), + .rb_kicker_size_bot ( rb_kicker_size_bot[1:0] ), + .rb_mode_rate_in_bot ( rb_mode_rate_in_bot[1:0] ), + .rb_mode_rate_out_bot ( rb_mode_rate_out_bot[1:0] ), + .rb_filter_code_bot ( rb_filter_code_bot[1:0] ), + .rb_phy_clk_mode_top ( rb_phy_clk_mode_top ), + .rb_track_speed_top ( rb_track_speed_top[3:0] ), + .rb_kicker_size_top ( rb_kicker_size_top[1:0] ), + .rb_mode_rate_in_top ( rb_mode_rate_in_top[1:0] ), + .rb_mode_rate_out_top ( rb_mode_rate_out_top[1:0] ), + .rb_filter_code_top ( rb_filter_code_top[1:0] ), + .rb_phy_clk_mode_right ( rb_phy_clk_mode_right ), + .sel_vref ( sel_vref[5:0] ), + .csr_clk ( csr_clk ), + .csr_clk_top ( csr_clk_top ), + .csr_clk_bot ( csr_clk_bot ), + .csr_clk_left ( csr_clk_left ), + .csr_clk_dbc ( csr_clk_dbc ), + .csr_in ( dqs_csrin ), + .csr_out ( ioereg_csrout[4] ), + .csr_en ( csr_en ), + .csr_en_top ( csr_en_top ), + .csr_en_bot ( csr_en_bot ), + .csr_en_left ( csr_en_left ), + .csr_en_dbc ( csr_en_dbc ), + .csr_shift_n ( csr_shift_n ), + .csr_shift_n_top ( csr_shift_n_top ), + .csr_shift_n_bot ( csr_shift_n_bot ), + .csr_shift_n_left ( csr_shift_n_left ), + .csr_shift_n_dbc ( csr_shift_n_dbc ), + .nfrzdrv ( local_nfrzdrv ), + .nfrzdrv_top ( nfrzdrv_top ), + .nfrzdrv_bot ( nfrzdrv_bot ), + .frzreg ( local_frzreg ), + .frzreg_top ( frzreg_top ), + .frzreg_bot ( frzreg_bot ), + .dll_lock ( dll_core[10] ), + .test_fr_clk_en_n ( test_fr_clk_en_n ), + .test_fr_clk_en_n_top ( test_fr_clk_en_n_top ), + .test_fr_clk_en_n_bot ( test_fr_clk_en_n_bot ), + .test_hr_clk_en_n ( test_hr_clk_en_n ), + .test_hr_clk_en_n_top ( test_hr_clk_en_n_top ), + .test_hr_clk_en_n_bot ( test_hr_clk_en_n_bot ), + .test_tdf_select_n ( test_tdf_select_n ), + .test_tdf_select_n_top ( test_tdf_select_n_top ), + .test_tdf_select_n_bot ( test_tdf_select_n_bot ), + .atpg_en_n ( atpg_en_n ), + .atpg_en_n_top ( atpg_en_n_top ), + .atpg_en_n_bot ( atpg_en_n_bot ), + .atpg_en_n_left ( atpg_en_n_left ), + .pipeline_global_en_n ( pipeline_global_en_n ), + .pipeline_global_en_n_top ( pipeline_global_en_n_top ), + .pipeline_global_en_n_bot ( pipeline_global_en_n_bot ), + .pipeline_global_en_n_left ( pipeline_global_en_n_left ), + .test_clr_n ( test_clr_n ), + .test_clr_n_top ( test_clr_n_top ), + .test_clr_n_bot ( test_clr_n_bot ), + .niotri ( local_niotri ), + .niotri_top ( niotri_top ), + .niotri_bot ( niotri_bot ), + .test_clk ( test_clk ), + .test_clk_top ( test_clk_top ), + .test_clk_bot ( test_clk_bot ), + .test_clk_left ( test_clk_left ), + .scan_shift_n ( scan_shift_n ), + .scan_shift_n_top ( scan_shift_n_top ), + .scan_shift_n_bot ( scan_shift_n_bot ), + .scan_shift_n_dbc ( scan_shift_n_dbc ), + .scan_shift_n_left ( scan_shift_n_left ), + .jtag_shftdr ( jtag_shftdr ), + .jtag_shftdr_top ( jtag_shftdr_top ), + .jtag_shftdr_bot ( jtag_shftdr_bot ), + .jtag_clk ( jtag_clk ), + .jtag_clk_top ( jtag_clk_top ), + .jtag_clk_bot ( jtag_clk_bot ), + .jtag_highz ( jtag_highz ), + .jtag_highz_top ( jtag_highz_top ), + .jtag_highz_bot ( jtag_highz_bot ), + .jtag_updtdr ( jtag_updtdr ), + .jtag_updtdr_top ( jtag_updtdr_top ), + .jtag_updtdr_bot ( jtag_updtdr_bot ), + .jtag_mode ( jtag_mode ), + .jtag_mode_top ( jtag_mode_top ), + .jtag_mode_bot ( jtag_mode_bot ), + .xor_clk ( xor_clk[5:0] ), + .test_xor_clk ( test_xor_clk ), + .test_phy_clk_lane_en_n ( test_phy_clk_lane_en_n ), + .test_phy_clk_lane_en_n_bot ( test_phy_clk_lane_en_n_bot ), + .test_phy_clk_lane_en_n_top ( test_phy_clk_lane_en_n_top ), + .test_int_clk_en_n ( test_int_clk_en_n ), + .test_int_clk_en_n_bot ( test_int_clk_en_n_bot ), + .test_int_clk_en_n_top ( test_int_clk_en_n_top ), + .test_interp_clk_en_n ( test_interp_clk_en_n ), + .test_interp_clk_en_n_bot ( test_interp_clk_en_n_bot ), + .test_interp_clk_en_n_top ( test_interp_clk_en_n_top ), + .test_clk_ph_buf_en_n ( test_clk_ph_buf_en_n ), + .test_clk_ph_buf_en_n_bot ( test_clk_ph_buf_en_n_bot ), + .test_clk_ph_buf_en_n_top ( test_clk_ph_buf_en_n_top ), + .test_datovr_en_n ( test_datovr_en_n ), + .test_datovr_en_n_bot ( test_datovr_en_n_bot ), + .test_datovr_en_n_top ( test_datovr_en_n_top ), + .test_avl_clk_in_en_n ( test_avl_clk_in_en_n ), + .test_dqs_enable_en_n ( test_dqs_enable_en_n ), + .probe_out ( dqs_probe[11:0] ), + .sync_data_bot_in ( sync_data_up_chn[2] ), + .sync_clk_bot_out ( sync_clk_dn_chn[2] ), + .sync_data_bot_out ( sync_data_dn_chn[2] ), + .sync_data_top_in ( sync_data_dn_chn[3] ), + .sync_clk_top_out ( sync_clk_up_chn[3] ), + .sync_data_top_out ( sync_data_up_chn[3] ), + .pst_test_i_n ( test_pst_dll_i ), + .pst_test_o_n ( test_i_n_dll ), + .pst_test_i_p ( test_i_p_pst ), + .pst_test_o_p ( test_pst_dll_o ), + .test_dqs_i1 ( core_dll[0] ), + .test_dqs_i2 ( core_dll[1] ), + .test_dqs_o1 ( test_dqs_o1 ), + .test_dqs_o2 ( test_dqs_o2 ), + .test_pst_clk_en_n_a ( test_pst_clk_en_n ), + .test_pst_clk_en_n_b ( test_pst_clk_en_n ), + .xprio_clk ( xprio_clk ), + .xprio_sync ( xprio_sync ), + .xprio_xbus ( xprio_xbus[7:0] ), + .xpr_clk_bot ( xpr_clk_bot ), + .xpr_clk_top ( xpr_clk_top ), + .xpr_write_bot ( xpr_write_bot[2:0] ), + .xpr_write_top ( xpr_write_top[2:0] ), + .xpr_data_bot ( xpr_data_bot[7:0] ), + .xpr_data_top ( xpr_data_top[7:0] ), + .dqs_loop_back_0a ( dqs_loop_back_0[1:0] ), + .dqs_loop_back_1a ( dqs_loop_back_1[1:0] ), + .dqs_loop_back_0b ( dqs_loop_back_0[1:0] ), + .dqs_loop_back_1b ( dqs_loop_back_1[1:0] ), + .x128_osc_in_p ( x64_osc_chain_p[7] ), + .x128_osc_in_n ( x64_osc_chain_n[7] ), + .x128_osc_out_p ( x64_osc_chain_p[0] ), + .x128_osc_out_n ( x64_osc_chain_n[0] ), + .osc_enable_in ( osc_enable_in ), + .osc_mode_in ( osc_mode_in ), + .osc_mode_out ( x64_osc_mode_out ), + .x1024_osc_out ( x1024_osc_out ) +); + + +wire [5:0] dummy_a, dummy_b; + +io_data_buffer__nf5es data_buffer ( + .phy_clk ( phy_clk[1:0] ), + .frzreg ( local_frzreg ), + .pll_locked ( pll_locked ), + .global_reset_n ( reset_n ), + .scan_shift_n ( scan_shift_n_dbc ), + .csr_scan_shift_n ( 1'b1 ), + .atpg_en_n ( atpg_en_n ), + .dft_pipeline_global_en_n ( pipeline_global_en_n ), + .test_clk ( test_clk ), + .test_phy_clk_en_n ( test_phy_clk_en_n ), + .dft_prbs_ena_n ( dft_prbs_ena_n ), + .dft_prbs_pass ( dft_prbs_pass ), + .dft_prbs_done ( dft_prbs_done ), + .dft_core2db ( dft_core2db[7:0] ), + .dft_db2core ( dft_db2core[7:0] ), + .dft_phy_clk ( dft_phy_clk[1:0] ), + .avl_address ( avl_address_dbc[19:0] ), + .avl_write ( avl_write_dbc[1:0] ), + .avl_writedata ( avl_writedata_dbc[31:0] ), + .avl_readdata ( avl_readdata_dbc[31:0] ), + .avl_select ( avl_select_ioereg[12:0] ), + .ctl2dbc_wrdata_vld0 ( ctl2dbc_wrdata_vld0 ), + .ctl2dbc_mask_entry0 ( ctl2dbc_mask_entry0 ), + .ctl2dbc_wb_rdptr_vld0 ( ctl2dbc_wb_rdptr_vld0 ), + .ctl2dbc_wb_rdptr0 ( ctl2dbc_wb_rdptr0[5:0] ), + .ctl2dbc_rb_wrptr_vld0 ( ctl2dbc_rb_wrptr_vld0 ), + .ctl2dbc_rb_wrptr0 ( ctl2dbc_rb_wrptr0[5:0] ), + .ctl2dbc_rb_rdptr_vld0 ( ctl2dbc_rb_rdptr_vld0[1:0] ), + .ctl2dbc_rb_rdptr0 ( ctl2dbc_rb_rdptr0[11:0] ), + .ctl2dbc_rdata_en_full0 ( ctl2dbc_rdata_en_full0[3:0] ), + .ctl2dbc_mrnk_read0 ( ctl2dbc_mrnk_read0[7:0] ), + .ctl2dbc_seq_en0 ( ctl2dbc_seq_en0 ), + .ctl2dbc_nop0 ( ctl2dbc_nop0 ), + .ctl2dbc_cs0 ( ctl2dbc_cs0[1:0] ), + .ctl2dbc_rd_type0 ( ctl2dbc_rd_type0 ), + .ctl2dbc_misc0 ( ctl2dbc_misc0[3:0] ), + .ctl2dbc_wrdata_vld1 ( ctl2dbc_wrdata_vld1 ), + .ctl2dbc_mask_entry1 ( ctl2dbc_mask_entry1 ), + .ctl2dbc_wb_rdptr_vld1 ( ctl2dbc_wb_rdptr_vld1 ), + .ctl2dbc_wb_rdptr1 ( ctl2dbc_wb_rdptr1[5:0] ), + .ctl2dbc_rb_wrptr_vld1 ( ctl2dbc_rb_wrptr_vld1 ), + .ctl2dbc_rb_wrptr1 ( ctl2dbc_rb_wrptr1[5:0] ), + .ctl2dbc_rb_rdptr_vld1 ( ctl2dbc_rb_rdptr_vld1[1:0] ), + .ctl2dbc_rb_rdptr1 ( ctl2dbc_rb_rdptr1[11:0] ), + .ctl2dbc_rdata_en_full1 ( ctl2dbc_rdata_en_full1[3:0] ), + .ctl2dbc_mrnk_read1 ( ctl2dbc_mrnk_read1[7:0] ), + .ctl2dbc_seq_en1 ( ctl2dbc_seq_en1 ), + .ctl2dbc_nop1 ( ctl2dbc_nop1 ), + .ctl2dbc_cs1 ( ctl2dbc_cs1[1:0] ), + .ctl2dbc_rd_type1 ( ctl2dbc_rd_type1 ), + .ctl2dbc_misc1 ( ctl2dbc_misc1[3:0] ), + .dbc2ctl_wb_retire_ptr_vld ( dbc2ctl_wb_retire_ptr_vld ), + .dbc2ctl_wb_retire_ptr ( dbc2ctl_wb_retire_ptr[5:0] ), + .dbc2ctl_rb_retire_ptr_vld ( dbc2ctl_rb_retire_ptr_vld ), + .dbc2ctl_rb_retire_ptr ( dbc2ctl_rb_retire_ptr[5:0] ), + .dbc2ctl_rd_data_vld ( dbc2ctl_rd_data_vld ), + .dbc2ctl_all_rd_done ( dbc2ctl_all_rd_done ), + .dbc2db_wb_wrptr_vld ( dbc2db_wb_wrptr_vld ), + .dbc2db_wb_wrptr ( dbc2db_wb_wrptr[5:0] ), + .cfg_dbc_ctrl_sel ( cfg_dbc_ctrl_sel ), + .cfg_reorder_rdata ( cfg_reorder_rdata ), + .cfg_rmw_en ( cfg_rmw_en ), + .cfg_output_regd ( cfg_output_regd ), + .cfg_dbc_in_protocol ( cfg_dbc_in_protocol ), + .cfg_dbc_dualport_en ( cfg_dbc_dualport_en ), + .cfg_dbc_pipe_lat ( cfg_dbc_pipe_lat[2:0] ), + .cfg_cmd_rate ( cfg_cmd_rate[2:0] ), + .cfg_dbc_rc_en ( cfg_dbc_rc_en ), + .cfg_dbc_slot_rotate_en ( cfg_dbc_slot_rotate_en[2:0] ), + .cfg_dbc_slot_offset ( cfg_dbc_slot_offset[1:0] ), + .rb_phy_clk_mode ( rb_phy_clk_mode_right ), + .oe_to_ioreg ( oeb_to_ioreg[47:0] ), + .data_to_ioreg ( data_to_ioreg[95:0] ), + .data_from_ioreg ( data_from_ioreg_abphy[95:0] ), + .read_data_valid ( rdata_valid_local[3:0] ), + .dq_in_dly_up ( chk_x1_track_in_up[11:0] ), + .dq_in_dly_dn ( chk_x1_track_in_dn[11:0] ), + .dq_out_dly_up ( chk_x1_track_out_up[11:0] ), + .dq_out_dly_dn ( chk_x1_track_out_dn[11:0] ), + .dqs_in_dly_up ( chk_x12_track_in_up ), + .dqs_in_dly_dn ( chk_x12_track_in_dn ), + .dqs_out_dly_up ( chk_x12_track_out_up ), + .dqs_out_dly_dn ( chk_x12_track_out_dn ), + .rdata_en_full ( rdata_en_full_local[3:0] ), + .mrnk_read ( mrnk_read_local[7:0] ), + .mrnk_write ( mrnk_write_local[7:0] ), + .select_ac_hmc ( select_ac_hmc[11:0] ), + .ioereg_reset_n ( ioereg_reset_n ), + .test_dbg_in ( test_dbg_in[11:0] ), + .test_dbg_out_db_in ( test_dbg_out[11:0] ), + .test_dbg_out_db_out ( test_dbg_out_local[11:0] ), + .oe_from_core ( oeb_from_core[47:0] ), + .data_from_core ( data_from_core[95:0] ), + .data_to_core ( data_to_core[95:0] ), + .rdata_en_full_core ( rdata_en_full_core[3:0] ), + .mrnk_read_core ( mrnk_read_core[15:0] ), + .mrnk_write_core ( mrnk_write_core[15:0] ), + .rdata_valid_core ( rdata_valid_core[3:0] ), + .afi_wlat_core ( afi_wlat_core[5:0] ), + .afi_rlat_core ( afi_rlat_core[5:0] ), + .core2dbc_wr_data_vld0 ( core2dbc_wr_data_vld0 ), + .core2dbc_wr_data_vld1 ( core2dbc_wr_data_vld1 ), + .dbc2core_wr_data_rdy ( dbc2core_wr_data_rdy ), + .dbc2core_rd_data_vld0 ( dbc2core_rd_data_vld0 ), + .dbc2core_rd_data_vld1 ( dbc2core_rd_data_vld1 ), + .dbc2core_rd_type ( dbc2core_rd_type ), + .core2dbc_rd_data_rdy ( core2dbc_rd_data_rdy ), + .core2dbc_wr_ecc_info ( core2dbc_wr_ecc_info[12:0] ), + .dbc2core_wb_pointer ( dbc2core_wb_pointer[11:0] ), + .csr_clk ( csr_clk_dbc ), + .csr_ena ( csr_en_dbc ), + .csr_din ( db_csrin ), + .csr_dout ( ioereg_csrout[0] ) +); + + +io_phy_ckt__nf5es phy_ckt ( +.lvds_rxloaden_in ( {7{phy_clk[0]}} ), +.lvds_rxclk_in ( {7{phy_clk[1]}} ), +.fb_clkin ( {21{phy_clk[2]}} ), +.lvds_txloaden_in ( {6{phy_clk[3]}} ), +.lvds_txclk_in ( {6{phy_clk[4]}} ), +.lvds_rx_clk_chnl0 ( lvds_rx_clk_chnl0[1:0] ), +.lvds_tx_clk_chnl0 ( lvds_tx_clk_chnl0[1:0] ), +.lvds_rx_clk_chnl1 ( lvds_rx_clk_chnl1[1:0] ), +.lvds_tx_clk_chnl1 ( lvds_tx_clk_chnl1[1:0] ), +.lvds_rx_clk_chnl2 ( lvds_rx_clk_chnl2[1:0] ), +.lvds_tx_clk_chnl2 ( lvds_tx_clk_chnl2[1:0] ), +.lvds_rx_clk_chnl3 ( lvds_rx_clk_chnl3[1:0] ), +.lvds_tx_clk_chnl3 ( lvds_tx_clk_chnl3[1:0] ), +.lvds_rx_clk_chnl4 ( lvds_rx_clk_chnl4[1:0] ), +.lvds_tx_clk_chnl4 ( lvds_tx_clk_chnl4[1:0] ), +.lvds_rx_clk_chnl5 ( lvds_rx_clk_chnl5[1:0] ), +.lvds_tx_clk_chnl5 ( lvds_tx_clk_chnl5[1:0] ), +.phy_clk0fb ( fb_clkout[0] ), +.phy_clk1fb ( fb_clkout[1] ), +.fb_clkout ( fb_clkout[2] ) +); + + +io_dqs_ckt__nf5es dqs_ckt ( +.dqsin_a ( dqs_out_a_n[1:0] ), +.dqsin_b ( dqs_out_b_n[1:0] ), +.dq0_in ( dq_in_del_n[1:0] ), +.dq1_in ( dq_in_del_n[3:2] ), +.dq2_in ( dq_in_del_n[5:4] ), +.dq3_in ( dq_in_del_n[7:6] ), +.dq4_in ( dq_in_del_n[9:8] ), +.dq5_in ( dq_in_del_n[11:10] ), +.dq6_in ( dq_in_del_n[13:12] ), +.dq7_in ( dq_in_del_n[15:14] ), +.dq8_in ( dq_in_del_n[17:16] ), +.dq9_in ( dq_in_del_n[19:18] ), +.dq10_in ( dq_in_del_n[21:20] ), +.dq11_in ( dq_in_del_n[23:22] ), +.n_dqsout_a_ioreg0 ( dqs_clk_a[1:0] ), +.n_dqsout_b_ioreg0 ( dqs_clk_b[1:0] ), +.n_dqsout_a_ioreg1 ( dqs_clk_a[3:2] ), +.n_dqsout_b_ioreg1 ( dqs_clk_b[3:2] ), +.n_dqsout_a_ioreg2 ( dqs_clk_a[5:4] ), +.n_dqsout_b_ioreg2 ( dqs_clk_b[5:4] ), +.n_dqsout_a_ioreg3 ( dqs_clk_a[7:6] ), +.n_dqsout_b_ioreg3 ( dqs_clk_b[7:6] ), +.n_dqsout_a_ioreg4 ( dqs_clk_a[9:8] ), +.n_dqsout_b_ioreg4 ( dqs_clk_b[9:8] ), +.n_dqsout_a_ioreg5 ( dqs_clk_a[11:10] ), +.n_dqsout_b_ioreg5 ( dqs_clk_b[11:10] ), +.n_dqsout_a_ioreg6 ( dqs_clk_a[13:12] ), +.n_dqsout_b_ioreg6 ( dqs_clk_b[13:12] ), +.n_dqsout_a_ioreg7 ( dqs_clk_a[15:14] ), +.n_dqsout_b_ioreg7 ( dqs_clk_b[15:14] ), +.n_dqsout_a_ioreg8 ( dqs_clk_a[17:16] ), +.n_dqsout_b_ioreg8 ( dqs_clk_b[17:16] ), +.n_dqsout_a_ioreg9 ( dqs_clk_a[19:18] ), +.n_dqsout_b_ioreg9 ( dqs_clk_b[19:18] ), +.n_dqsout_a_ioreg10 ( dqs_clk_a[21:20] ), +.n_dqsout_b_ioreg10 ( dqs_clk_b[21:20] ), +.n_dqsout_a_ioreg11 ( dqs_clk_a[23:22] ), +.n_dqsout_b_ioreg11 ( dqs_clk_b[23:22] ), +.n_dq0out ( dq_in_tree[1:0] ), +.n_dq1out ( dq_in_tree[3:2] ), +.n_dq2out ( dq_in_tree[5:4] ), +.n_dq3out ( dq_in_tree[7:6] ), +.n_dq4out ( dq_in_tree[9:8] ), +.n_dq5out ( dq_in_tree[11:10] ), +.n_dq6out ( dq_in_tree[13:12] ), +.n_dq7out ( dq_in_tree[15:14] ), +.n_dq8out ( dq_in_tree[17:16] ), +.n_dq9out ( dq_in_tree[19:18] ), +.n_dq10out ( dq_in_tree[21:20] ), +.n_dq11out ( dq_in_tree[23:22] ) +); + + +io_dll_top__nf5es xio_dll_top ( +.core_dll ( 'd0 ), +.csrclk ( csr_clk_left ), +.csren ( csr_en_left ), +.early_csren ( early_csren ), +.csrdatain ( ioereg_csrout[7] ), +.clk_pll ( 'd0 ), +.reinit ( 'd0 ), +.entest ( entest ), +.csr_scan_shift_n ( 1'b1 ), +.cas_csrdin ( cas_csrdin[4:0] ), +.cas_csrdout ( cas_csrdout[4:0] ), +.scan_shift_n ( scan_shift_n_left ), +.atpg_en_n ( atpg_en_n_left ), +.dll_core ( dll_core[12:0] ), +.pvt_ref_gry ( pvt_ref_gry[9:0] ), +.csrdataout ( ioereg_csrout[8] ), +.dft_pipeline_global_en_n ( pipeline_global_en_n_left ), +.test_clk ( test_clk_left ), +.test_clr_n ( test_clr_n_bot ), +.test_clk_pll_en_n ( test_clk_pll_en_n ), +.bhniotri ( bhniotri ), +.early_bhniotri ( early_bhniotri ), +.enrnsl ( enrnsl ), +.early_enrnsl ( early_enrnsl ), +.frzreg ( frzreg ), +.early_frzreg ( early_frzreg ), +.nfrzdrv ( nfrzdrv ), +.early_nfrzdrv ( early_nfrzdrv ), +.niotri ( niotri ), +.early_niotri ( early_niotri ), +.plniotri ( plniotri ), +.early_plniotri ( early_plniotri ), +.usermode ( usrmode ), +.early_usermode ( early_usrmode ), +.wkpullup ( wkpullup ), +.local_bhniotri ( local_bhniotri ), +.local_enrnsl ( local_enrnsl ), +.local_frzreg ( local_frzreg ), +.local_nfrzdrv ( local_nfrzdrv ), +.local_niotri ( local_niotri ), +.local_plniotri ( local_plniotri ), +.local_usermode ( local_usrmode ), +.local_wkpullup ( local_wkpullup ), +.hps_to_core_ctrl_en ( hps_to_core_ctrl_en ), +.test_si_dll ( test_i_n_dll ), +.test_so_dll ( test_i_p_pst ), +.test_dqs_o1 ( test_dqs_o1 ), +.test_dqs_o2 ( test_dqs_o2 ), +.osc_mode ( x64_osc_mode_out ), +.osc_in_p ( 'd0 ), +.osc_in_n ( 'd0 ), +.osc_out_p ( x64_osc_chain_p[7] ), +.osc_out_n ( x64_osc_chain_n[7] ) +); + +io_regulator__nf5es xio_regulator ( +.ibp50u ( ibp50u ), +.clk ( regulator_clk ), +.vfb ( vcc_regphy ), +.ibp50u_cal ( ibp50u_cal ), +.vcca_io ( 1'b1 ), +.vcc_io ( 1'b1 ), +.vss_io ( 1'b0 ), +.atbi_0 ( atbi_0 ), +.atbi_1 ( atbi_1 ), +.cal_done ( lane_cal_done ), +.vcc_regphy ( vcc_regphy ), +.csr_shift_n ( 1'b1 ), +.csr_in ( ioereg_csrout[8] ), +.csr_en ( csr_en_left ), +.csr_clk ( csr_clk_left ), +.csr_out ( ioereg_csrout[9] ) +); + + +io_vref__nf5es vref ( +.vref_ext ( vref_ext ), +.sel_vref ( sel_vref[5:0] ), +.vref_int ( vref_int ), +.i50u_ref ( i50u_ref ), +.xor_vref ( xor_vref ), +.csrdin ( ioereg_csrout[9] ), +.csrclk ( csr_clk_left ), +.csren ( csr_en_left ), +.csr_scan_shift_n ( csr_shift_n_left ), +.csrdout ( csr_out ) +); + + +io_gpio_osc_en__nf5es xio_gpio_osc_en ( +.osc_en_n ( osc_en_n ), +.osc_in ( osc_start_out ), +.osc_out ( osc_start_in ), +.rocount_to_core ( osc_rocount_to_core ) +); + + +`ifdef ENABLE_IO_12_LANE_ASSERTIONS + + +wire phy_clk_lane; + +assign phy_clk_lane = rb_phy_clk_mode_right ? phy_clk[1] : phy_clk[0]; + + +reg valid_state; +time phy_clk_lane_period; +time old_phy_clk_lane_time; +time phy_clk_phs_period; +time old_phy_clk_phs_time; +real expected_ratio; +real frequency_ratio; +reg delayed_reset_pulse; + +always @(posedge phy_clk_lane) + begin + phy_clk_lane_period = $time - old_phy_clk_lane_time; + old_phy_clk_lane_time = $time; + end + +always @(posedge phy_clk_phs[0]) + begin + phy_clk_phs_period = $time - old_phy_clk_phs_time; + old_phy_clk_phs_time = $time; + end + +always @(*) frequency_ratio = real'(phy_clk_lane_period) / real'(phy_clk_phs_period); + +always @(posedge reset_n) + begin + #10000 delayed_reset_pulse = reset_n; + #1 delayed_reset_pulse = 1'b0; + end + +initial valid_state = 1; + +always @(*) + begin + if (~reset_n) valid_state = 0; + else if (delayed_reset_pulse) + casez ({rb_mode_rate_out_bot[1:0],rb_mode_rate_in_bot[1:0]}) + 4'b00_0? : if ((frequency_ratio > 26) && (frequency_ratio < 38) ) begin valid_state = 1; expected_ratio = 32.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 32.0; display_bad_clock; end + 4'b00_10 : if ((frequency_ratio > 13) && (frequency_ratio < 19) ) begin valid_state = 1; expected_ratio = 16.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 16.0; display_bad_clock; end + 4'b00_11 : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 4'b01_0? : if ((frequency_ratio > 13) && (frequency_ratio < 19) ) begin valid_state = 1; expected_ratio = 16.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 16.0; display_bad_clock; end + 4'b01_10 : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 4'b01_11 : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 4'b10_0? : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 4'b10_10 : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 4'b10_11 : if ((frequency_ratio > 1.6) && (frequency_ratio < 2.4)) begin valid_state = 1; expected_ratio = 2.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 2.0; display_bad_clock; end + 4'b11_0? : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 4'b11_10 : if ((frequency_ratio > 1.6) && (frequency_ratio < 2.4)) begin valid_state = 1; expected_ratio = 2.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 2.0; display_bad_clock; end + 4'b11_11 : if ((frequency_ratio > 0.8) && (frequency_ratio < 1.2)) begin valid_state = 1; expected_ratio = 1.0; display_good_clock; end + else begin valid_state = 0; expected_ratio = 1.0; display_bad_clock; end + endcase + else if ($time < 300) valid_state = 0; + else casez ({valid_state,rb_mode_rate_out_bot[1:0],rb_mode_rate_in_bot[1:0]}) + 5'b0_00_0? : if ((frequency_ratio > 26) && (frequency_ratio < 38) ) begin valid_state = 1; expected_ratio = 32.0; display_good_clock; end + 5'b0_00_10 : if ((frequency_ratio > 13) && (frequency_ratio < 19) ) begin valid_state = 1; expected_ratio = 16.0; display_good_clock; end + 5'b0_00_11 : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + 5'b0_01_0? : if ((frequency_ratio > 13) && (frequency_ratio < 19) ) begin valid_state = 1; expected_ratio = 16.0; display_good_clock; end + 5'b0_01_10 : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + 5'b0_01_11 : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + 5'b0_10_0? : if ((frequency_ratio > 6.4) && (frequency_ratio < 9.6)) begin valid_state = 1; expected_ratio = 8.0; display_good_clock; end + 5'b0_10_10 : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + 5'b0_10_11 : if ((frequency_ratio > 1.6) && (frequency_ratio < 2.4)) begin valid_state = 1; expected_ratio = 2.0; display_good_clock; end + 5'b0_11_0? : if ((frequency_ratio > 3.2) && (frequency_ratio < 4.8)) begin valid_state = 1; expected_ratio = 4.0; display_good_clock; end + 5'b0_11_10 : if ((frequency_ratio > 1.6) && (frequency_ratio < 2.4)) begin valid_state = 1; expected_ratio = 2.0; display_good_clock; end + 5'b0_11_11 : if ((frequency_ratio > 0.8) && (frequency_ratio < 1.2)) begin valid_state = 1; expected_ratio = 1.0; display_good_clock; end + 5'b1_00_0? : if ((frequency_ratio < 26) || (frequency_ratio > 38) ) begin valid_state = 0; expected_ratio = 32.0; display_bad_clock; end + 5'b1_00_10 : if ((frequency_ratio < 13) || (frequency_ratio > 19) ) begin valid_state = 0; expected_ratio = 16.0; display_bad_clock; end + 5'b1_00_11 : if ((frequency_ratio < 6.4) || (frequency_ratio > 9.6)) begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 5'b1_01_0? : if ((frequency_ratio < 13) || (frequency_ratio > 19) ) begin valid_state = 0; expected_ratio = 16.0; display_bad_clock; end + 5'b1_01_10 : if ((frequency_ratio < 6.4) || (frequency_ratio > 9.6)) begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 5'b1_01_11 : if ((frequency_ratio < 3.2) || (frequency_ratio > 4.8)) begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 5'b1_10_0? : if ((frequency_ratio < 6.4) || (frequency_ratio > 9.6)) begin valid_state = 0; expected_ratio = 8.0; display_bad_clock; end + 5'b1_10_10 : if ((frequency_ratio < 3.2) || (frequency_ratio > 4.8)) begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 5'b1_10_11 : if ((frequency_ratio < 1.6) || (frequency_ratio > 2.4)) begin valid_state = 0; expected_ratio = 2.0; display_bad_clock; end + 5'b1_11_0? : if ((frequency_ratio < 3.2) || (frequency_ratio > 4.8)) begin valid_state = 0; expected_ratio = 4.0; display_bad_clock; end + 5'b1_11_10 : if ((frequency_ratio < 1.6) || (frequency_ratio > 2.4)) begin valid_state = 0; expected_ratio = 2.0; display_bad_clock; end + 5'b1_11_11 : if ((frequency_ratio < 0.8) || (frequency_ratio > 1.2)) begin valid_state = 0; expected_ratio = 1.0; display_bad_clock; end + endcase + end + +task display_good_clock; +begin + $display("\nIO_12_LANE Message, The clock ratio of phy_clk_lane/phy_clk_phs is good, the expected ratio is %f, the actual ratio is %f", expected_ratio, frequency_ratio ); + $display("Time = %t,\n %m\n",$time); +end +endtask + +task display_bad_clock; +begin + $display("\nIO_12_LANE Message, The clock ratio of phy_clk_lane/phy_clk_phs is bad, the expected ratio is %f, the actual ratio is %f", expected_ratio, frequency_ratio ); + $display("Time = %t,\n %m\n",$time); +end +endtask + +`endif + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/io_12_lane_bcm__nf5es_abphy.sv b/ase/rtl/device_models/dcp_emif_model/io_12_lane_bcm__nf5es_abphy.sv new file mode 100644 index 000000000000..a65a59ef4709 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/io_12_lane_bcm__nf5es_abphy.sv @@ -0,0 +1,32355 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +module io_12_lane_bcm__nf5es_abphy ( + ac_hmc, + afi_rlat_core, + afi_wlat_core, + atbi_0, + atbi_1, + atpg_en_n, + avl_address_in, + avl_address_out, + avl_clk_in, + avl_clk_out, + avl_read_in, + avl_read_out, + avl_readdata_in, + avl_readdata_out, + avl_write_in, + avl_write_out, + avl_writedata_in, + avl_writedata_out, + bhniotri, + broadcast_in_bot, + broadcast_in_top, + broadcast_out_bot, + broadcast_out_top, + cas_csrdin, + cas_csrdout, + cfg_cmd_rate, + cfg_dbc_ctrl_sel, + cfg_dbc_dualport_en, + cfg_dbc_in_protocol, + cfg_dbc_pipe_lat, + cfg_dbc_rc_en, + cfg_dbc_slot_offset, + cfg_dbc_slot_rotate_en, + cfg_output_regd, + cfg_reorder_rdata, + cfg_rmw_en, + clk_pll, + codin_n, + codin_nb, + codin_p, + codin_pb, + core2dbc_rd_data_rdy, + core2dbc_wr_data_vld0, + core2dbc_wr_data_vld1, + core2dbc_wr_ecc_info, + core_dll, + crnt_clk, + csr_clk, + csr_clk_left, + csr_en, + csr_en_left, + csr_in, + csr_out, + csr_shift_n, + ctl2dbc_cs0, + ctl2dbc_cs1, + ctl2dbc_mask_entry0, + ctl2dbc_mask_entry1, + ctl2dbc_misc0, + ctl2dbc_misc1, + ctl2dbc_mrnk_read0, + ctl2dbc_mrnk_read1, + ctl2dbc_nop0, + ctl2dbc_nop1, + ctl2dbc_rb_rdptr0, + ctl2dbc_rb_rdptr1, + ctl2dbc_rb_rdptr_vld0, + ctl2dbc_rb_rdptr_vld1, + ctl2dbc_rb_wrptr0, + ctl2dbc_rb_wrptr1, + ctl2dbc_rb_wrptr_vld0, + ctl2dbc_rb_wrptr_vld1, + ctl2dbc_rd_type0, + ctl2dbc_rd_type1, + ctl2dbc_rdata_en_full0, + ctl2dbc_rdata_en_full1, + ctl2dbc_seq_en0, + ctl2dbc_seq_en1, + ctl2dbc_wb_rdptr0, + ctl2dbc_wb_rdptr1, + ctl2dbc_wb_rdptr_vld0, + ctl2dbc_wb_rdptr_vld1, + ctl2dbc_wrdata_vld0, + ctl2dbc_wrdata_vld1, + data_from_core, + data_to_core, + dbc2core_rd_data_vld0, + dbc2core_rd_data_vld1, + dbc2core_rd_type, + dbc2core_wb_pointer, + dbc2core_wr_data_rdy, + dbc2ctl_all_rd_done, + dbc2ctl_rb_retire_ptr, + dbc2ctl_rb_retire_ptr_vld, + dbc2ctl_rd_data_vld, + dbc2ctl_wb_retire_ptr, + dbc2ctl_wb_retire_ptr_vld, + dbc2db_wb_wrptr, + dbc2db_wb_wrptr_vld, + dft_core2db, + dft_db2core, + dft_phy_clk, + dft_prbs_done, + dft_prbs_ena_n, + dft_prbs_pass, + dll_core, + dq_diff_in, + dq_sstl_in, + dqs_diff_in_0, + dqs_diff_in_1, + dqs_diff_in_2, + dqs_diff_in_3, + dqs_sstl_n_0, + dqs_sstl_n_1, + dqs_sstl_n_2, + dqs_sstl_n_3, + dqs_sstl_p_0, + dqs_sstl_p_1, + dqs_sstl_p_2, + dqs_sstl_p_3, + dzoutx, + early_bhniotri, + early_csren, + early_enrnsl, + early_frzreg, + early_nfrzdrv, + early_niotri, + early_plniotri, + early_usrmode, + enrnsl, + entest, + fb_clkout, + fr_in_clk, + fr_out_clk, + frzreg, + hps_to_core_ctrl_en, + hr_in_clk, + hr_out_clk, + i50u_ref, + ibp50u, + ibp50u_cal, + ioereg_locked, + jtag_clk, + jtag_highz, + jtag_mode, + jtag_sdin, + jtag_sdout, + jtag_shftdr, + jtag_updtdr, + lane_cal_done, + local_bhniotri, + local_enrnsl, + local_frzreg, + local_nfrzdrv, + local_niotri, + local_plniotri, + local_usrmode, + local_wkpullup, + lvds_rx_clk_chnl0, + lvds_rx_clk_chnl1, + lvds_rx_clk_chnl2, + lvds_rx_clk_chnl3, + lvds_rx_clk_chnl4, + lvds_rx_clk_chnl5, + lvds_tx_clk_chnl0, + lvds_tx_clk_chnl1, + lvds_tx_clk_chnl2, + lvds_tx_clk_chnl3, + lvds_tx_clk_chnl4, + lvds_tx_clk_chnl5, + mrnk_read_core, + mrnk_write_core, + n_crnt_clk, + n_next_clk, + naclr, + ncein, + nceout, + next_clk, + nfrzdrv, + niotri, + nsclr, + oct_enable, + oeb_from_core, + osc_en_n, + osc_enable_in, + osc_mode_in, + osc_rocount_to_core, + osc_sel_n, + phy_clk, + phy_clk_phs, + pipeline_global_en_n, + pll_clk, + pll_locked, + plniotri, + progctl, + progoe, + progout, + rdata_en_full_core, + rdata_valid_core, + regulator_clk, + reinit, + reset_n, + scan_shift_n, + scanin, + scanout, + switch_dn, + switch_up, + sync_clk_bot_in, + sync_clk_bot_out, + sync_clk_top_in, + sync_clk_top_out, + sync_data_bot_in, + sync_data_bot_out, + sync_data_top_in, + sync_data_top_out, + test_avl_clk_in_en_n, + test_clk, + test_clk_ph_buf_en_n, + test_clk_pll_en_n, + test_clr_n, + test_datovr_en_n, + test_db_csr_in, + test_dbg_in, + test_dbg_out, + test_dqs_csr_in, + test_dqs_enable_en_n, + test_fr_clk_en_n, + test_hr_clk_en_n, + test_int_clk_en_n, + test_interp_clk_en_n, + test_ioereg2_csr_out, + test_phy_clk_en_n, + test_phy_clk_lane_en_n, + test_pst_clk_en_n, + test_pst_dll_i, + test_pst_dll_o, + test_tdf_select_n, + test_vref_csr_out, + test_xor_clk, + tpctl, + tpdata, + tpin, + up_ph, + usrmode, + vref_ext, + vref_int, + weak_pullup_enable, + wkpullup, + x1024_osc_out, + xor_vref, + xprio_clk, + xprio_sync, + xprio_xbus +); + + timeunit 1ps; + timeprecision 1ps; + + + input [95:0] ac_hmc; + output [5:0] afi_rlat_core; + output [5:0] afi_wlat_core; + output atbi_0; + output atbi_1; + input atpg_en_n; + input [19:0] avl_address_in; + output [19:0] avl_address_out; + input avl_clk_in; + output avl_clk_out; + input avl_read_in; + output avl_read_out; + input [31:0] avl_readdata_in; + output [31:0] avl_readdata_out; + input avl_write_in; + output avl_write_out; + input [31:0] avl_writedata_in; + output [31:0] avl_writedata_out; + input bhniotri; + input broadcast_in_bot; + input broadcast_in_top; + output broadcast_out_bot; + output broadcast_out_top; + input [4:0] cas_csrdin; + output [4:0] cas_csrdout; + input [2:0] cfg_cmd_rate; + input cfg_dbc_ctrl_sel; + input cfg_dbc_dualport_en; + input cfg_dbc_in_protocol; + input [2:0] cfg_dbc_pipe_lat; + input cfg_dbc_rc_en; + input [1:0] cfg_dbc_slot_offset; + input [2:0] cfg_dbc_slot_rotate_en; + input cfg_output_regd; + input cfg_reorder_rdata; + input cfg_rmw_en; + input clk_pll; + output [11:0] codin_n; + output [11:0] codin_nb; + output [11:0] codin_p; + output [11:0] codin_pb; + input core2dbc_rd_data_rdy; + input core2dbc_wr_data_vld0; + input core2dbc_wr_data_vld1; + input [12:0] core2dbc_wr_ecc_info; + input [2:0] core_dll; + output [5:0] crnt_clk; + input csr_clk; + output csr_clk_left; + input csr_en; + output csr_en_left; + input csr_in; + output csr_out; + input csr_shift_n; + input [1:0] ctl2dbc_cs0; + input [1:0] ctl2dbc_cs1; + input ctl2dbc_mask_entry0; + input ctl2dbc_mask_entry1; + input [3:0] ctl2dbc_misc0; + input [3:0] ctl2dbc_misc1; + input [7:0] ctl2dbc_mrnk_read0; + input [7:0] ctl2dbc_mrnk_read1; + input ctl2dbc_nop0; + input ctl2dbc_nop1; + input [11:0] ctl2dbc_rb_rdptr0; + input [11:0] ctl2dbc_rb_rdptr1; + input [1:0] ctl2dbc_rb_rdptr_vld0; + input [1:0] ctl2dbc_rb_rdptr_vld1; + input [5:0] ctl2dbc_rb_wrptr0; + input [5:0] ctl2dbc_rb_wrptr1; + input ctl2dbc_rb_wrptr_vld0; + input ctl2dbc_rb_wrptr_vld1; + input ctl2dbc_rd_type0; + input ctl2dbc_rd_type1; + input [3:0] ctl2dbc_rdata_en_full0; + input [3:0] ctl2dbc_rdata_en_full1; + input ctl2dbc_seq_en0; + input ctl2dbc_seq_en1; + input [5:0] ctl2dbc_wb_rdptr0; + input [5:0] ctl2dbc_wb_rdptr1; + input ctl2dbc_wb_rdptr_vld0; + input ctl2dbc_wb_rdptr_vld1; + input ctl2dbc_wrdata_vld0; + input ctl2dbc_wrdata_vld1; + input [95:0] data_from_core; + output [95:0] data_to_core; + output dbc2core_rd_data_vld0; + output dbc2core_rd_data_vld1; + output dbc2core_rd_type; + output [11:0] dbc2core_wb_pointer; + output dbc2core_wr_data_rdy; + output dbc2ctl_all_rd_done; + output [5:0] dbc2ctl_rb_retire_ptr; + output dbc2ctl_rb_retire_ptr_vld; + output dbc2ctl_rd_data_vld; + output [5:0] dbc2ctl_wb_retire_ptr; + output dbc2ctl_wb_retire_ptr_vld; + output [5:0] dbc2db_wb_wrptr; + output dbc2db_wb_wrptr_vld; + input [7:0] dft_core2db; + output [7:0] dft_db2core; + output [1:0] dft_phy_clk; + output dft_prbs_done; + input dft_prbs_ena_n; + output dft_prbs_pass; + output [12:0] dll_core; + input [23:0] dq_diff_in; + input [23:0] dq_sstl_in; + input [1:0] dqs_diff_in_0; + input [1:0] dqs_diff_in_1; + input [1:0] dqs_diff_in_2; + input [1:0] dqs_diff_in_3; + input [1:0] dqs_sstl_n_0; + input [1:0] dqs_sstl_n_1; + input [1:0] dqs_sstl_n_2; + input [1:0] dqs_sstl_n_3; + input [1:0] dqs_sstl_p_0; + input [1:0] dqs_sstl_p_1; + input [1:0] dqs_sstl_p_2; + input [1:0] dqs_sstl_p_3; + input [5:0] dzoutx; + input early_bhniotri; + input early_csren; + input early_enrnsl; + input early_frzreg; + input early_nfrzdrv; + input early_niotri; + input early_plniotri; + input early_usrmode; + input enrnsl; + input entest; + output [2:0] fb_clkout; + input [12*1-1:0] fr_in_clk; + input [12*1-1:0] fr_out_clk; + input frzreg; + output hps_to_core_ctrl_en; + input [12*1-1:0] hr_in_clk; + input [12*1-1:0] hr_out_clk; + input i50u_ref; + input ibp50u; + input ibp50u_cal; + output [5:0] ioereg_locked; + input jtag_clk; + input jtag_highz; + input jtag_mode; + input jtag_sdin; + output jtag_sdout; + input jtag_shftdr; + input jtag_updtdr; + output lane_cal_done; + output local_bhniotri; + output local_enrnsl; + output local_frzreg; + output local_nfrzdrv; + output local_niotri; + output local_plniotri; + output local_usrmode; + output local_wkpullup; + output [1:0] lvds_rx_clk_chnl0; + output [1:0] lvds_rx_clk_chnl1; + output [1:0] lvds_rx_clk_chnl2; + output [1:0] lvds_rx_clk_chnl3; + output [1:0] lvds_rx_clk_chnl4; + output [1:0] lvds_rx_clk_chnl5; + output [1:0] lvds_tx_clk_chnl0; + output [1:0] lvds_tx_clk_chnl1; + output [1:0] lvds_tx_clk_chnl2; + output [1:0] lvds_tx_clk_chnl3; + output [1:0] lvds_tx_clk_chnl4; + output [1:0] lvds_tx_clk_chnl5; + input [15:0] mrnk_read_core; + input [15:0] mrnk_write_core; + output [5:0] n_crnt_clk; + output [5:0] n_next_clk; + input [12*1-1:0] naclr; + input [12*1-1:0] ncein; + input [12*1-1:0] nceout; + output [5:0] next_clk; + input nfrzdrv; + input niotri; + input [12*1-1:0] nsclr; + output [11:0] oct_enable; + input [47:0] oeb_from_core; + input osc_en_n; + input osc_enable_in; + input osc_mode_in; + output osc_rocount_to_core; + input osc_sel_n; + input [4:0] phy_clk; + input [7:0] phy_clk_phs; + input pipeline_global_en_n; + input pll_clk; + input pll_locked; + input plniotri; + input [12*1-1:0] progctl; + input [12*1-1:0] progoe; + input [12*1-1:0] progout; + input [3:0] rdata_en_full_core; + output [3:0] rdata_valid_core; + input regulator_clk; + input reinit; + input reset_n; + input scan_shift_n; + input [5:0] scanin; + output [5:0] scanout; + input [5:0] switch_dn; + input [5:0] switch_up; + input sync_clk_bot_in; + output sync_clk_bot_out; + input sync_clk_top_in; + output sync_clk_top_out; + input sync_data_bot_in; + output sync_data_bot_out; + input sync_data_top_in; + output sync_data_top_out; + input test_avl_clk_in_en_n; + input test_clk; + input test_clk_ph_buf_en_n; + input test_clk_pll_en_n; + input test_clr_n; + input test_datovr_en_n; + input test_db_csr_in; + output [11:0] test_dbg_in; + input [11:0] test_dbg_out; + input test_dqs_csr_in; + input test_dqs_enable_en_n; + input test_fr_clk_en_n; + input test_hr_clk_en_n; + input test_int_clk_en_n; + input test_interp_clk_en_n; + output test_ioereg2_csr_out; + input test_phy_clk_en_n; + input test_phy_clk_lane_en_n; + input test_pst_clk_en_n; + input test_pst_dll_i; + output test_pst_dll_o; + input test_tdf_select_n; + output test_vref_csr_out; + output test_xor_clk; + input [12*1-1:0] tpctl; + output [12*1-1:0] tpdata; + input [12*1-1:0] tpin; + input [5:0] up_ph; + input usrmode; + input vref_ext; + output vref_int; + output [11:0] weak_pullup_enable; + input wkpullup; + output x1024_osc_out; + output xor_vref; + input xprio_clk; + input xprio_sync; + input [7:0] xprio_xbus; + +parameter data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_ac_dqs_dm_dq = ""; +parameter data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_data_buffer_ctrl = ""; +parameter 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data_buffer__rdwr_buffer_inst_4__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_4__a_wr_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_5__a_wr_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_6__a_wr_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_7__a_wr_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_8__a_wr_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_data_buffer_ctrl = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_db_in_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_dbc_sel = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_oe_datapath_mod = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_pipeline = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_prbs = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_wdb_bypass = ""; +parameter data_buffer__rdwr_buffer_inst_9__a_wr_datapath_mod = ""; +parameter data_buffer__HIERARCHY = ""; +parameter data_buffer__a_calibration = ""; +parameter data_buffer__a_data_buffer_ctrl = ""; +parameter data_buffer__a_dft_mode = ""; +parameter data_buffer__a_memory_standard = ""; +parameter data_buffer__a_mode_rate_in = ""; +parameter data_buffer__a_mode_rate_out = ""; +parameter [8-1:0] data_buffer__a_phy_wlat = 8'h00; +parameter [8-1:0] data_buffer__a_pipe_latency = 8'h00; +parameter [6-1:0] data_buffer__a_rb_afi_rlat_vlu = 6'b0; +parameter [6-1:0] data_buffer__a_rb_afi_wlat_vlu = 6'b0; +parameter data_buffer__a_rb_avl_ena = ""; +parameter data_buffer__a_rb_bc_id_ena = ""; +parameter data_buffer__a_rb_burst_length_mode = ""; +parameter data_buffer__a_rb_crc_dq0 = ""; +parameter data_buffer__a_rb_crc_dq1 = ""; +parameter data_buffer__a_rb_crc_dq2 = ""; +parameter data_buffer__a_rb_crc_dq3 = ""; +parameter data_buffer__a_rb_crc_dq4 = ""; +parameter data_buffer__a_rb_crc_dq5 = ""; +parameter data_buffer__a_rb_crc_dq6 = ""; +parameter data_buffer__a_rb_crc_dq7 = ""; +parameter data_buffer__a_rb_crc_dq8 = ""; +parameter data_buffer__a_rb_crc_en = ""; +parameter data_buffer__a_rb_data_alignment_mode = ""; +parameter data_buffer__a_rb_db2core_registered = ""; +parameter [4-1:0] data_buffer__a_rb_db_feature = 4'h0; +parameter [7-1:0] data_buffer__a_rb_dbc_wb_reserved_entry = 7'h04; +parameter data_buffer__a_rb_dbi_rd_en = ""; +parameter data_buffer__a_rb_dbi_sel = ""; +parameter data_buffer__a_rb_dbi_wr_en = ""; +parameter data_buffer__a_rb_dft_hmc_phy = ""; +parameter data_buffer__a_rb_dft_lbk_phy = ""; +parameter data_buffer__a_rb_dft_mux_speed_in = ""; +parameter data_buffer__a_rb_dft_mux_speed_out = ""; +parameter data_buffer__a_rb_dft_prbs_mode = ""; +parameter data_buffer__a_rb_dft_speed_test = ""; +parameter data_buffer__a_rb_gpio_0 = ""; +parameter data_buffer__a_rb_gpio_1 = ""; +parameter data_buffer__a_rb_gpio_10 = ""; +parameter data_buffer__a_rb_gpio_11 = ""; +parameter data_buffer__a_rb_gpio_2 = ""; +parameter data_buffer__a_rb_gpio_3 = ""; +parameter data_buffer__a_rb_gpio_4 = ""; +parameter data_buffer__a_rb_gpio_5 = ""; +parameter data_buffer__a_rb_gpio_6 = ""; +parameter data_buffer__a_rb_gpio_7 = ""; +parameter data_buffer__a_rb_gpio_8 = ""; +parameter data_buffer__a_rb_gpio_9 = ""; +parameter data_buffer__a_rb_hmc_or_core = ""; +parameter data_buffer__a_rb_mrnk_read_registered = ""; +parameter data_buffer__a_rb_mrnk_write_registered = ""; +parameter data_buffer__a_rb_phy_clk0_ena = ""; +parameter data_buffer__a_rb_phy_clk1_ena = ""; +parameter data_buffer__a_rb_preamble_mode = ""; +parameter data_buffer__a_rb_ptr_pipeline = ""; +parameter data_buffer__a_rb_qr_or_hr = ""; +parameter data_buffer__a_rb_rdata_en_full_registered = ""; +parameter data_buffer__a_rb_reset_auto_release = ""; +parameter data_buffer__a_rb_rwlat_mode = ""; +parameter data_buffer__a_rb_sel_core_clk = ""; +parameter [3-1:0] data_buffer__a_rb_seq_rd_en_full_pipeline = 3'h0; +parameter [9-1:0] data_buffer__a_rb_tile_id = 9'h00; +parameter data_buffer__a_rb_x4_or_x8_or_x9 = ""; +parameter [8-1:0] data_buffer__a_wl_latency = 8'h00; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_0___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_0___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_0___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_0___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_0___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_0___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_0___HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_1___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_1___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_1___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_1___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_1___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_1___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_1___HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_2___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_2___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_2___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_2___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_2___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_2___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_2___HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_3___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_3___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_3___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_3___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_3___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_3___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_3___HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_4___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_4___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_4___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_4___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_4___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_4___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_4___HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_0__gpio_reg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_0__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__HIERARCHY = ""; +parameter ioereg_top_5___gpio_wrapper_1__gpio_reg__mode = ""; +parameter ioereg_top_5___gpio_wrapper_1__HIERARCHY = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_ck_cmd = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dqss = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_mode_output = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_in = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_mode_rate_out = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_octrt = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_wl_latency = 10'h000; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_ck_cmd = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dqss = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_mode_output = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_in = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_mode_rate_out = ""; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_octrt = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase = 12'h000; +parameter ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_pin_usage = ""; +parameter [12-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_struct_gate_delay = 12'h000; +parameter [13-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_time_core_to_codin = 12'h000; +parameter [10-1:0] ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_wl_latency = 10'h000; +parameter ioereg_top_5___ioereg_pnr_x2__HIERARCHY = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_ddr2_oeb = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_dpa_enable = ""; +parameter [3-1:0] ioereg_top_5___ioereg_pnr_x2__a_lock_speed = 3'h7; +parameter ioereg_top_5___ioereg_pnr_x2__a_power_down = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_power_down_0 = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_power_down_1 = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_power_down_2 = ""; +parameter ioereg_top_5___ioereg_pnr_x2__a_sync_control = ""; +parameter ioereg_top_5___HIERARCHY = ""; +parameter vref__a_vref_cal = ""; +parameter vref__a_vref_enable = ""; +parameter vref__a_vref_offset = ""; +parameter vref__a_vref_offsetmode = ""; +parameter vref__a_vref_range = ""; +parameter vref__a_vref_sel = ""; +parameter vref__a_vref_val = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_core_dn_prgmnvrt = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_core_up_prgmnvrt = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_core_updnen = ""; +parameter [10-1:0] xio_dll_top__xio_dll_pnr__a_rb_ctl_static = 10'h000; +parameter xio_dll_top__xio_dll_pnr__a_rb_ctlsel = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel0 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel1 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel2 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel3 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel4 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel5 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel6 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel7 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel8 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel9 = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dll_en = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_dll_rst_en = ""; +parameter [10-1:0] xio_dll_top__xio_dll_pnr__a_rb_dly_pst = 10'h000; +parameter xio_dll_top__xio_dll_pnr__a_rb_dly_pst_en = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_hps_ctrl_en = ""; +parameter xio_dll_top__xio_dll_pnr__a_rb_ndllrst_prgmnvrt = ""; +parameter [3-1:0] xio_dll_top__xio_dll_pnr__a_rb_new_dll = 3'b000; +parameter xio_dll_top__xio_dll_pnr__powerdown_mode = ""; +parameter xio_dll_top__HIERARCHY = ""; +parameter xio_dll_top__dll_func_mode = ""; +parameter xio_dll_top__powerdown_mode = ""; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_board_delay = 16'h0000; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_broadcast_enable = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_burst_length = ""; +parameter [8-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_cas_latency = 8'h00; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_cmd_latency = 16'h0000; +parameter [7-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold = 7'h00; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_ddr4_search = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_en = ""; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_en_latency = 16'h0000; +parameter [6-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay = 6'h00; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_a = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_b = ""; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_shrink_delay = 16'h0000; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_shrink_gate_delay = 16'h0000; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_enable_b_rank = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_enable_toggler = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_filter_code = ""; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_io_in_delay = 16'h0000; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_io_out_delay = 16'h0000; +parameter [2-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_kicker_size = 2'h0; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_lock_edge = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_memory_burst_length = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_memory_dqs_type = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_memory_rank_size = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_memory_standard = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_memory_width = ""; +parameter [7-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_min_rd_valid_delay = 7'h00; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_in = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_out = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_mrnk_delay = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_multi_rank_enable = ""; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay = 9'h000; +parameter [9-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay = 9'h000; +parameter [10-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay = 10'h000; +parameter [3-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_oct_size = 3'h1; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_output_phase = 16'h0000; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_pack_mode = ""; +parameter [13-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a = 13'h000; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_adjust = 16'h0000; +parameter [13-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b = 13'h000; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_phy_clk_mode = ""; +parameter [8-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_pipe_latency = 8'h00; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_0 = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_1 = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_2 = ""; +parameter [4-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel = 4'h0; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_en_shrink = ""; +parameter xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_preamble_mode = ""; +parameter [10-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a = 10'h000; +parameter [10-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b = 10'h000; +parameter [7-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay = 7'h00; +parameter [8-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay_adjust = 8'h00; +parameter [8-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_rlat = 8'h00; +parameter [7-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_rlat_rd_valid_delay = 7'h00; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_time_en_full_to_shrunk_a = 16'h0000; +parameter [16-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_time_en_full_to_shrunk_b = 16'h0000; +parameter [4-1:0] xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed = 4'h0; +parameter xio_dqs_lgc_top__HIERARCHY = ""; +parameter [16-1:0] xio_dqs_lgc_top__a_clock_period = 16'h000; +parameter xio_regulator__a_cr_atbsel0 = ""; +parameter xio_regulator__a_cr_atbsel1 = ""; +parameter xio_regulator__a_cr_atbsel2 = ""; +parameter xio_regulator__a_cr_pd = ""; +parameter xio_regulator__a_powerdown_mode = ""; +parameter HIERARCHY = ""; +parameter [16-1:0] a_board_delay = 16'h0000; +parameter a_calibration = ""; +parameter [8-1:0] a_cas_latency = 8'h00; +parameter [12-1:0] a_ck_cmd = 12'h000; +parameter [16-1:0] a_clock_period = 16'h000; +parameter [13-1:0] a_cmd_core_to_codin = 13'h000; +parameter [13-1:0] a_cmd_pipe_latency = 13'h000; +parameter [13-1:0] a_dq_read_latency = 13'h000; +parameter [12-1:0] a_dqss = 12'h040; +parameter a_filter_code = ""; +parameter [16-1:0] a_io_in_delay = 16'h0000; +parameter [16-1:0] a_io_out_delay = 16'h0000; +parameter a_lane_usage = ""; +parameter a_memory_burst_length = ""; +parameter a_memory_controller = ""; +parameter a_memory_rank_size = ""; +parameter a_memory_standard = ""; +parameter a_memory_width = ""; +parameter a_mode_rate_in = ""; +parameter a_mode_rate_out = ""; +parameter [16-1:0] a_output_phase = 16'h0000; +parameter a_phy_clk_mode = ""; +parameter [8-1:0] a_pipe_latency = 8'h00; +parameter [13-1:0] a_struct_gate_delay = 13'h000; +parameter [8-1:0] a_wl_latency = 8'h00; +parameter powerdown_mode = ""; + +`ifndef USE_CSR +initial +begin + + i0.xio_dqs_lgc_top.dqs_lgc_pnr.avl_toggler = 1'b0; + + force csr_en = 1'b0; + force csr_shift_n = 1'b0; + +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[213].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[213].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[213].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[132].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[132].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[132].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[108].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[108].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[108].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[252].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[252].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[252].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_0__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[214].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[214].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[214].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[133].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[133].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[133].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[109].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[109].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[109].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[253].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[253].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[253].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_1__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[142].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[142].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[142].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[118].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[118].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[118].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[262].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[262].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[262].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_10__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[143].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[143].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[143].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[119].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[119].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[119].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[263].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[263].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[263].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_11__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[215].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[215].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[215].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[134].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[134].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[134].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[110].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[110].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[110].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[254].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[254].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[254].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_2__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[216].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[216].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[216].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[135].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[135].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[135].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[111].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[111].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[111].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[255].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[255].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[255].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_3__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[217].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[217].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[217].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[136].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[136].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[136].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[112].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[112].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[112].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[256].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[256].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[256].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_4__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[218].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[218].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[218].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[137].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[137].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[137].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[113].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[113].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[113].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[257].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[257].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[257].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_5__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[219].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[219].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[219].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[138].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[138].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[138].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[114].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[114].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[114].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[258].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[258].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[258].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_6__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[220].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[220].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[220].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[139].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[139].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[139].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[115].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[115].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[115].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[259].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[259].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[259].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_7__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[221].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[221].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[221].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[140].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[140].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[140].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[116].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[116].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[116].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[260].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[260].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[260].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_8__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_ac_dqs_dm_dq) + "dq_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + "dm_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + "ac_type" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_db_oe_bypass) + "db_oe_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[222].csr_reg_bit.csr_reg = 1'b0; + end + "db_oe_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[222].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[222].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_db_out_bypass) + "db_out_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[141].csr_reg_bit.csr_reg = 1'b0; + end + "db_out_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[141].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[141].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_oe_datapath_prgmnvrt) + "oe_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[117].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[117].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[117].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_rb_sel_ac_hmc_ena) + "sel_ac_hmc_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[261].csr_reg_bit.csr_reg = 1'b1; + end + "sel_ac_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[261].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[261].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__data_buffer_out_if_inst__io_data_buffer_out_mux_inst_9__a_wr_datapath_prgmnvrt) + "wr_datapath_non_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_invert" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[120].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[120].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[120].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[201].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[201].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[201].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_0__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[121].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[121].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[121].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[202].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[202].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[202].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_1__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[130].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[130].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[130].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[104].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[105].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[104].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[105].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[104].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[105].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[211].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[211].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[211].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_10__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[131].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[131].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[131].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[106].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[107].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[106].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[107].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[106].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[107].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[212].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[212].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[212].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_11__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[122].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[122].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[122].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[203].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[203].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[203].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_2__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[123].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[123].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[123].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[204].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[204].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[204].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_3__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[124].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[124].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[124].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[205].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[205].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[205].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_4__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[125].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[125].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[125].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[206].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[206].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[206].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_5__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[126].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[126].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[126].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[207].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[207].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[207].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_6__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[127].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[127].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[127].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[208].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[208].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[208].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_7__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[128].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[128].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[128].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[209].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[209].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[209].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_8__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_db_in_bypass) + "db_in_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[129].csr_reg_bit.csr_reg = 1'b0; + end + "db_in_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[129].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[129].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_dbc_sel) + "sel_core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "sel_dbc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_oe_datapath_mod) + "oe_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[102].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[103].csr_reg_bit.csr_reg = 1'b0; + end + "oe_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[102].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[103].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[102].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[103].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_prbs) + "sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[210].csr_reg_bit.csr_reg = 1'b1; + end + "not_sel_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[210].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[210].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_wdb_bypass) + "wdb_not_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + "wdb_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__rdwr_buffer_inst_9__a_wr_datapath_mod) + "wr_datapath_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "wr_datapath_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[237].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[238].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[239].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[240].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[3]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[241].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[4]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[242].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_rlat_vlu[5]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[231].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[232].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[233].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[234].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[3]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[235].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[4]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[236].csr_reg_bit.csr_reg = data_buffer__a_rb_afi_wlat_vlu[5]; +case (data_buffer__a_rb_avl_ena) + "avl_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[200].csr_reg_bit.csr_reg = 1'b0; + end + "avl_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[200].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[200].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_bc_id_ena) + "bc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[162].csr_reg_bit.csr_reg = 1'b0; + end + "bc_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[162].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[162].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_burst_length_mode) + "bl8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[276].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[277].csr_reg_bit.csr_reg = 1'b0; + end + "bl4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[276].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[277].csr_reg_bit.csr_reg = 1'b0; + end + "bl2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[276].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[277].csr_reg_bit.csr_reg = 1'b1; + end + "bl_reserved" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[276].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[277].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[276].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[277].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq0) + "crc_dq0_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq0_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq0_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq0_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq0_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq1) + "crc_dq1_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq1_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq1_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq1_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq1_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq2) + "crc_dq2_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq2_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq2_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq2_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq2_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq3) + "crc_dq3_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq3_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq3_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq3_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq3_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq4) + "crc_dq4_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq4_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq4_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq4_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq4_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq5) + "crc_dq5_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq5_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq5_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq5_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq5_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq6) + "crc_dq6_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq6_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq6_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq6_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq6_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq7) + "crc_dq7_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq7_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq7_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq7_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq7_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_dq8) + "crc_dq8_pin0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + "crc_dq8_pin8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq8_pin9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq8_pin10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b1; + end + "crc_dq8_pin11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_crc_en) + "crc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[152].csr_reg_bit.csr_reg = 1'b0; + end + "crc_en" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[152].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[152].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_data_alignment_mode) + "align_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[248].csr_reg_bit.csr_reg = 1'b0; + end + "align_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[248].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[248].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__a_rb_db2core_registered) + "not_registered" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[251].csr_reg_bit.csr_reg = 1'b0; + end + "registered" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[251].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[251].csr_reg_bit.csr_reg = 1'b1; + end + endcase + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[296].csr_reg_bit.csr_reg = data_buffer__a_rb_db_feature[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[297].csr_reg_bit.csr_reg = data_buffer__a_rb_db_feature[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[298].csr_reg_bit.csr_reg = data_buffer__a_rb_db_feature[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[299].csr_reg_bit.csr_reg = data_buffer__a_rb_db_feature[3]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[269].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[270].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[271].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[272].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[3]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[273].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[4]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[274].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[5]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[275].csr_reg_bit.csr_reg = data_buffer__a_rb_dbc_wb_reserved_entry[6]; +case (data_buffer__a_rb_dbi_rd_en) + "dbi_rd_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[268].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_rd_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[268].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[268].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dbi_sel) + "dbi_dq7" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq8" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b1; + end + "dbi_dq9" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b1; + end + "dbi_dq10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b1; + end + "dbi_dq11" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b1; + end + "dbi_dq0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq2" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq3" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq4" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq5" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_dq6" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dbi_wr_en) + "dbi_wr_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[149].csr_reg_bit.csr_reg = 1'b0; + end + "dbi_wr_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[149].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[149].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_hmc_phy) + "lbk_hmc_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b0; + end + "lbk_hmc_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_lbk_phy) + "lbk_phy_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b0; + end + "lbk_phy_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_mux_speed_in) + "sel_speed_in0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[265].csr_reg_bit.csr_reg = 1'b0; + end + "sel_speed_in1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[265].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[265].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_mux_speed_out) + "sel_speed_out0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[266].csr_reg_bit.csr_reg = 1'b0; + end + "sel_speed_out1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[266].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[266].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_prbs_mode) + "oe_0_dq_0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + "oe_0_dq_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + "oe_1_dq_0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + "oe_1_dq_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + "oe_prbs_dq_0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b1; + end + "oe_prbs_dq_prbs" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b1; + end + "oe_0_dq_01" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b1; + end + "oe_0_dq_10" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_dft_speed_test) + "sel_speed_test_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[267].csr_reg_bit.csr_reg = 1'b0; + end + "sel_speed_test_enable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[267].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[267].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_0) + "gpio_0_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[281].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_0_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[281].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[281].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_1) + "gpio_1_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[282].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_1_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[282].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[282].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_10) + "gpio_10_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[291].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_10_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[291].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[291].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_11) + "gpio_11_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[292].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_11_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[292].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[292].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_2) + "gpio_2_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[283].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_2_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[283].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[283].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_3) + "gpio_3_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[284].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_3_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[284].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[284].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_4) + "gpio_4_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[285].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_4_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[285].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[285].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_5) + "gpio_5_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[286].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_5_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[286].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[286].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_6) + "gpio_6_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[287].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_6_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[287].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[287].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_7) + "gpio_7_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[288].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_7_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[288].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[288].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_8) + "gpio_8_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[289].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_8_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[289].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[289].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_gpio_9) + "gpio_9_false" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[290].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_9_true" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[290].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[290].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_hmc_or_core) + "core" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[144].csr_reg_bit.csr_reg = 1'b0; + end + "hmc" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[144].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[144].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_mrnk_read_registered) + "mrnk_read_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[279].csr_reg_bit.csr_reg = 1'b0; + end + "mrnk_read_registered" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[279].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[279].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_mrnk_write_registered) + "mrnk_write_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[280].csr_reg_bit.csr_reg = 1'b0; + end + "mrnk_write_registered" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[280].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[280].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_phy_clk0_ena) + "phy_clk0_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[249].csr_reg_bit.csr_reg = 1'b0; + end + "phy_clk0_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[249].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[249].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__a_rb_phy_clk1_ena) + "phy_clk1_disable" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[250].csr_reg_bit.csr_reg = 1'b0; + end + "phy_clk1_ena" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[250].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[250].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__a_rb_preamble_mode) + "preamble_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[246].csr_reg_bit.csr_reg = 1'b0; + end + "preamble_two_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[246].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[246].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_ptr_pipeline) + "ptr_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b0; + end + "ptr_one_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b0; + end + "ptr_two_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b0; + end + "ptr_three_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b0; + end + "ptr_four_cycle" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[243].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[244].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[245].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_qr_or_hr) + "hr" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[199].csr_reg_bit.csr_reg = 1'b0; + end + "qr" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[199].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[199].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_rdata_en_full_registered) + "rdata_en_full_bypass" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[278].csr_reg_bit.csr_reg = 1'b0; + end + "rdata_en_full_registered" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[278].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[278].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_reset_auto_release) + "avl_release" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[247].csr_reg_bit.csr_reg = 1'b0; + end + "auto_release" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[247].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[247].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (data_buffer__a_rb_rwlat_mode) + "csr_vlu" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[230].csr_reg_bit.csr_reg = 1'b0; + end + "avl_vlu" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[230].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[230].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (data_buffer__a_rb_sel_core_clk) + "phy_clk0" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[264].csr_reg_bit.csr_reg = 1'b0; + end + "phy_clk1" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[264].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[264].csr_reg_bit.csr_reg = 1'b1; + end + endcase + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[293].csr_reg_bit.csr_reg = data_buffer__a_rb_seq_rd_en_full_pipeline[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[294].csr_reg_bit.csr_reg = data_buffer__a_rb_seq_rd_en_full_pipeline[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[295].csr_reg_bit.csr_reg = data_buffer__a_rb_seq_rd_en_full_pipeline[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[153].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[0]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[154].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[1]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[155].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[2]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[156].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[3]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[157].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[4]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[158].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[5]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[159].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[6]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[160].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[7]; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[161].csr_reg_bit.csr_reg = data_buffer__a_rb_tile_id[8]; +case (data_buffer__a_rb_x4_or_x8_or_x9) + "x9_mode" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = 1'b0; + end + "x8_mode" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = 1'b0; + end + "x4_mode" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = 1'b0; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = 1'b1; + end + "reserved" : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = 1'b1; + force i0.data_buffer.data_buffer_cnfg_inst.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_0___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_0___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_0___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_0___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_0_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_1___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_1___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_1___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_1___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_1_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_2___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_2___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_2___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_2___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_2_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_3___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_3___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_3___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_3___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_3_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_4___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_4___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_4___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_4___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_4_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xin_dlychn0__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xin_dlychn1__a_rb_ireg_dlychn_sel) + "dly_setting_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_16" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_17" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_18" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_19" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_20" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_21" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_22" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_23" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_24" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_25" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_26" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_27" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_28" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_29" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_30" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_31" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_32" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_33" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_34" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_35" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_36" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_37" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_38" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_39" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_40" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_41" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_42" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_43" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_44" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_45" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_46" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_47" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_48" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_49" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_50" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_51" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_52" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_53" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_54" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_55" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_56" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_57" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_58" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_59" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_60" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_61" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_62" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_63" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b1; + end + "dly_setting_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + "dly_setting_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_fr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_fr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_hr_in_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_hr_out_clk__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout2__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_iodout3__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_naclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_ncein__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_nceout__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_noe0__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_noe1__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xinv_nsclr__a_rb_sel) + "in_buf" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "in_inv" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_dfm__a_rb_ireg_or_oreg_sel) + "outreg_input" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + end + "buffer_input" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_halfrate_oreg_ereg__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_fr_out_clk_ereg_ena) + "fr_out_clk_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + "fr_out_clk_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_hr_out_clk_ereg_ena) + "hr_out_clk_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b1; + end + "hr_out_clk_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_ena) + "naclr_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_naclr_ereg_sel) + "ereg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nceout_ereg_ena) + "nceout_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_clk_rst_gen__a_rb_nsclr_ereg_ena) + "nsclr_ereg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ereg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__xio_gpio_oe_reg__a_rb_ereg_sclr_val) + "ereg_sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ereg__a_rb_ereg_tieoff_val) + "ereg_tieoff_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + "ereg_tieoff_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux0__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux1__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux2__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_4to1_mux3__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_ddio_in__a_rb_sclr_val) + "sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + "sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_fr_in_clk_ena) + "fr_in_clk_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + "fr_in_clk_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_hr_in_clk_ena) + "hr_in_clk_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b1; + end + "hr_in_clk_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_ena) + "naclr_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_naclr_ireg_sel) + "ireg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + "ireg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_ncein_ireg_ena) + "ncein_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + "ncein_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_ireg__xio_gpio_in_clk_rst_gen__a_rb_nsclr_ireg_ena) + "nsclr_ireg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_ireg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oe_dly_chn__a_rb_ereg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_4to1_mux__a_rb_mux_sel) + "sel0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + "sel2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + "sel3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_ddr_ena) + "oreg_ddr_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_ddr_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_ddio_out__a_rb_oreg_sclr_val) + "oreg_sclr_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_sclr_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_0__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_halfrate_oreg_ereg_1__a_rb_hr_reg_byp) + "hr_reg_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "hr_reg_bypass_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_fr_out_clk_oreg_ena) + "fr_out_clk_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + end + "fr_out_clk_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_hr_out_clk_oreg_ena) + "hr_out_clk_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "hr_out_clk_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_ena) + "naclr_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + "naclr_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_naclr_oreg_sel) + "oreg_nclr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_npre_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nceout_oreg_ena) + "nceout_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "nceout_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__xio_gpio_out_clk_rst_gen__a_rb_nsclr_oreg_ena) + "nsclr_oreg_dis" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "nsclr_oreg_ena" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_oreg__a_rb_oreg_tieoff_val) + "oreg_tieoff_val_low" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "oreg_tieoff_val_high" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_gpio_out_dly_chn__a_rb_oreg_dlychn_sel) + "outdly_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_9" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_10" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_11" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_12" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_13" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_14" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_15" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "outdly_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_3" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_4" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_5" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_6" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_7" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "outdly_8" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_debug) + "jtag_debug_off" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_debug_on" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_din_or_pll_sel) + "jtag_din_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_pll_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel) + "jtag_gpio_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "jtag_ddr_sel" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[0]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[1]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[10]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[11]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[2]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[3]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[4]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[5]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[6]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[7]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[8]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_0.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_0__a_output_phase[9]; +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dfx_mode) + "dfx_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_mcu_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + "dfx_dqs_gate_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + "dfx_dq_dqs_probe" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dq_select) + "dq_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_sstl_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_loopback_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_xor_loopback_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + "dq_differential_in" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_x12_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + "dq_differential_in_avl_x12_out" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dqs_select) + "dqs_sampler_b_a_rise" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_fall" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_a" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_sampler_b_a_over" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_over" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_b_a_rank" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + "dqs_sampler_a_b_rank" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_dynoct) + "oct_enabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + "oct_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_gpio_differential) + "gpio_single_ended" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + "gpio_differential" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_initial_out) + "initial_out_z" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + "initial_out_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + "initial_out_x" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b1; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = 1'b0; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_mode_ddr) + "mode_sdr" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b0; + end + "mode_ddr" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_octrt) + "static_oct_off" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + "static_oct_on" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[0]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[1]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[10]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[11]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[2]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[3]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[4]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[5]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[6]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[7]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[8]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_pnr_1.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__ioereg_pnr_1__a_output_phase[9]; +case (ioereg_top_5___ioereg_pnr_x2__a_ddr2_oeb) + "ddr3_preamble" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + "ddr2_preamble" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__a_dpa_enable) + "dpa_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "dpa_enabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__a_lock_speed[0]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__a_lock_speed[1]; + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = ioereg_top_5___ioereg_pnr_x2__a_lock_speed[2]; +case (ioereg_top_5___ioereg_pnr_x2__a_power_down) + "power_on" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__a_power_down_0) + "power_on_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__a_power_down_1) + "power_on_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__a_power_down_2) + "power_on_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (ioereg_top_5___ioereg_pnr_x2__a_sync_control) + "sync_disabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "sync_enabled" : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.ioereg_top_5_.ioereg_pnr_x2.ioereg_misc.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_cal) + "a_vref_cal_enable" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_cal_disable" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (vref__a_vref_enable) + "a_vref_disable" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_enable" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_offset) + "a_vref_offset_0" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_offset_1" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_offset_2" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_offset_3" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_offset_4" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_offset_5" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_offset_6" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_offset_7" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_offsetmode) + "a_vref_offsetmode_add" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_offsetmode_minus" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_range) + "a_vref_range1" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_range2" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_sel) + "a_vref_sel_ext" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_sel_int" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_sel_loop1" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_sel_byp" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_sel_loop2" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (vref__a_vref_val) + "a_vref_val_0" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_1" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_2" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_3" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_4" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_5" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_6" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_7" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_8" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_9" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_10" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_11" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_12" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_13" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_14" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_15" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_16" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_17" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_18" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_19" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_20" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_21" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_22" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_23" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_24" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_25" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_26" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_27" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_28" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_29" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_30" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_31" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + "a_vref_val_32" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_33" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_34" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_35" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_36" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_37" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_38" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_39" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_40" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_41" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_42" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_43" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_44" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_45" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_46" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_47" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_48" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_49" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "a_vref_val_50" : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.vref.xcsr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_core_dn_prgmnvrt) + "off" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + "on" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_core_up_prgmnvrt) + "on" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + "off" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_core_updnen) + "core_updn_dis" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + "core_updn_en" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[0]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[1]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[2]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[3]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[4]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[5]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[6]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[7]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[8]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_ctl_static[9]; +case (xio_dll_top__xio_dll_pnr__a_rb_ctlsel) + "ctl_dynamic" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + end + "ctl_static" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel0) + "pvt_gry_0" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_0" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_0" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + "dft_dll_reset" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel1) + "pvt_gry_1" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_1" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_1" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + "dft_overflow" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel2) + "pvt_gry_2" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_2" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_2" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "gate_state_0" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel3) + "pvt_gry_3" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_3" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_3" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + end + "gate_state_1" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel4) + "pvt_gry_4" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_4" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_4" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + "gate_state_2" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel5) + "pvt_gry_5" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_5" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_5" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + "gate_state_3" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel6) + "pvt_gry_6" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_6" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_6" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + "gate_state_4" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel7) + "pvt_gry_7" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_7" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_7" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + "dft_unused1" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel8) + "pvt_gry_8" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_8" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_8" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + end + "dft_unused2" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dftmuxsel9) + "pvt_gry_9" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + end + "pvt_binary_9" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + end + "int_binary_9" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + end + "dft_ctrl_to_core" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dll_en) + "dll_dis" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "dll_en" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_dll_rst_en) + "dll_rst_dis" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "dll_rst_en" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[0]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[1]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[2]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[3]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[4]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[5]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[6]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[7]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[8]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_dly_pst[9]; +case (xio_dll_top__xio_dll_pnr__a_rb_dly_pst_en) + "dly_adj_dis" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + "dly_adj_en" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_hps_ctrl_en) + "hps_ctrl_dis" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs_2.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "hps_ctrl_en" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs_2.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs_2.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dll_top__xio_dll_pnr__a_rb_ndllrst_prgmnvrt) + "off" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "on" : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_new_dll[0]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_new_dll[1]; + force i0.xio_dll_top.xio_dll_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = xio_dll_top__xio_dll_pnr__a_rb_new_dll[2]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_broadcast_enable) + "disable_broadcast" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "generate_broadcast" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + "top_in_broadcast" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + "bottom_in_broadcast" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[28].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[29].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_burst_length) + "burst_length_10" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + "burst_length_8" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b1; + end + "burst_length_4" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + "burst_length_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[13].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[14].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[4].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[5].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[6].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[7].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_count_threshold[6]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_ddr4_search) + "ddr3_search" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + "ddr4_search" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[8].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_en) + "dqs_gated" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b0; + end + "dqs_pass" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[223].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[15].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[16].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[17].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[18].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[19].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[20].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay[5]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_a) + "a_dqs_diff_in_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_diff_in_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_diff_in_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_diff_in_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_sstl_p_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_sstl_p_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_sstl_p_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_sstl_p_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + "a_dqs_sstl_n_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_sstl_n_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_sstl_n_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_sstl_n_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_loop_back0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_loop_back1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_constant" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + "a_dqs_interpolator" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[72].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[73].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[74].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[75].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_b) + "b_dqs_diff_in_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_diff_in_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_diff_in_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_diff_in_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_sstl_p_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_sstl_p_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_sstl_p_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_sstl_p_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + "b_dqs_sstl_n_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_sstl_n_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_sstl_n_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_sstl_n_3" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_loop_back0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_loop_back1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_constant" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + "b_dqs_interpolator" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[76].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[77].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[78].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[79].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_enable_b_rank) + "disable_b_rank" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b0; + end + "enable_b_rank" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[224].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_enable_toggler) + "preamble_track_dqs_enable" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b0; + end + "preamble_track_toggler" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[80].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_filter_code) + "freq_08ghz" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + "freq_10ghz" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b1; + end + "freq_12ghz" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + "freq_16ghz" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[30].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[31].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[39].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_kicker_size[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[40].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_kicker_size[1]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_lock_edge) + "preamble_lock_rising_edge" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + "preamble_lock_falling_edge" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_in) + "in_rate_full" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "in_rate_1_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b1; + end + "in_rate_1_4" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[9].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[10].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_out) + "out_rate_full" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + "out_rate_1_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + "out_rate_1_4" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + "out_rate_1_8" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[11].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[12].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_mrnk_delay) + "mrnk_short" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b0; + end + "mrnk_long" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[229].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[201].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[202].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[203].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[204].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[205].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[206].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[207].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[208].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[209].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[120].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[121].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[122].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[123].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[124].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[125].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[126].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[127].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[128].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[111].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[112].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[113].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[114].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[115].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[116].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[117].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[118].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[119].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[210].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[211].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[212].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[213].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[214].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[215].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[216].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[217].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[218].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[192].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[193].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[194].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[195].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[196].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[197].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[198].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[199].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[200].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[183].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[184].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[185].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[186].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[187].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[188].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[189].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[190].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[191].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[174].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[175].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[176].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[177].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[178].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[179].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[180].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[181].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[182].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[165].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[166].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[167].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[168].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[169].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[170].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[171].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[172].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[173].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[156].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[157].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[158].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[159].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[160].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[161].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[162].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[163].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[164].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[147].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[148].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[149].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[150].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[151].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[152].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[153].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[154].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[155].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[138].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[139].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[140].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[141].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[142].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[143].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[144].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[145].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[146].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[129].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[130].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[131].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[132].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[133].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[134].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[135].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[136].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[137].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[101].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[102].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[103].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[104].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[105].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[106].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[107].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[108].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[109].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[110].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay[9]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[42].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_oct_size[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[43].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_oct_size[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[44].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_oct_size[2]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_pack_mode) + "packed" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + "not_packed" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[41].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[46].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[47].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[56].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[10]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[57].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[11]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[58].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[12]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[48].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[49].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[50].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[51].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[52].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[53].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[54].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[55].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a[9]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[59].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[60].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[69].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[10]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[70].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[11]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[71].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[12]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[61].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[62].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[63].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[64].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[65].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[66].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[67].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[68].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b[9]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_phy_clk_mode) + "phy_clk_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + "phy_clk_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[45].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down) + "power_on" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b0; + end + "power_off" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[228].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_0) + "power_on_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[225].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_1) + "power_on_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[226].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_power_down_2) + "power_on_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + "power_off_2" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[227].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[219].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[220].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[221].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[222].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel[3]; +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_en_shrink) + "shrink_0_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "shrink_0_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b0; + end + "shrink_1_0" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + "shrink_1_1" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b1; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[32].csr_reg_bit.csr_reg = 1'b0; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[33].csr_reg_bit.csr_reg = 1'b1; + end + endcase +case (xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_preamble_mode) + "ddr3_preamble" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + "ddr4_preamble" : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[34].csr_reg_bit.csr_reg = 1'b0; + end + endcase + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[91].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[92].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[93].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[94].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[95].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[96].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[97].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[98].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[99].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[100].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a[9]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[81].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[82].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[83].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[84].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[85].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[86].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[87].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[88].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[7]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[89].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[8]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[90].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b[9]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[21].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[22].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[23].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[24].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[3]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[25].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[4]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[26].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[5]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[27].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay[6]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[35].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed[0]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[36].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed[1]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[37].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed[2]; + force i0.xio_dqs_lgc_top.dqs_lgc_pnr.csr_reg_nregs.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[38].csr_reg_bit.csr_reg = xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed[3]; +case (xio_regulator__a_cr_atbsel0) + "cr_atbsel0_dis" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + "cr_atbsel0_en" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[1].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_regulator__a_cr_atbsel1) + "cr_atbsel1_dis" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + "cr_atbsel1_en" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[2].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_regulator__a_cr_atbsel2) + "cr_atbsel2_en" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b1; + end + "cr_atbsel2_dis" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + default : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[3].csr_reg_bit.csr_reg = 1'b0; + end + endcase +case (xio_regulator__a_cr_pd) + "cr_pd_dis" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + "cr_pd_en" : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b1; + end + default : begin + force i0.xio_regulator.xio_vreg_cnfg.csr_reg_nregs[0].csr_reg_nbits.csr_reg_bit[0].csr_reg_bit.csr_reg = 1'b0; + end + endcase + + #111 + force csr_en = 1'b1; + force csr_shift_n = 1'b1; +end +`endif + +io_12_lane__nf5es_abphy i0 ( + .ac_hmc( ac_hmc), + .afi_rlat_core( afi_rlat_core), + .afi_wlat_core( afi_wlat_core), + .atbi_0( atbi_0), + .atbi_1( atbi_1), + .atpg_en_n( atpg_en_n), + .avl_address_in( avl_address_in), + .avl_address_out( avl_address_out), + .avl_clk_in( avl_clk_in), + .avl_clk_out( avl_clk_out), + .avl_read_in( avl_read_in), + .avl_read_out( avl_read_out), + .avl_readdata_in( avl_readdata_in), + .avl_readdata_out( avl_readdata_out), + .avl_write_in( avl_write_in), + .avl_write_out( avl_write_out), + .avl_writedata_in( avl_writedata_in), + .avl_writedata_out( avl_writedata_out), + .bhniotri( bhniotri), + .broadcast_in_bot( broadcast_in_bot), + .broadcast_in_top( broadcast_in_top), + .broadcast_out_bot( broadcast_out_bot), + .broadcast_out_top( broadcast_out_top), + .cas_csrdin( cas_csrdin), + .cas_csrdout( cas_csrdout), + .cfg_cmd_rate( cfg_cmd_rate), + .cfg_dbc_ctrl_sel( cfg_dbc_ctrl_sel), + .cfg_dbc_dualport_en( cfg_dbc_dualport_en), + .cfg_dbc_in_protocol( cfg_dbc_in_protocol), + .cfg_dbc_pipe_lat( cfg_dbc_pipe_lat), + .cfg_dbc_rc_en( cfg_dbc_rc_en), + .cfg_dbc_slot_offset( cfg_dbc_slot_offset), + .cfg_dbc_slot_rotate_en( cfg_dbc_slot_rotate_en), + .cfg_output_regd( cfg_output_regd), + .cfg_reorder_rdata( cfg_reorder_rdata), + .cfg_rmw_en( cfg_rmw_en), + .clk_pll( clk_pll), + .codin_n( codin_n), + .codin_nb( codin_nb), + .codin_p( codin_p), + .codin_pb( codin_pb), + .core2dbc_rd_data_rdy( core2dbc_rd_data_rdy), + .core2dbc_wr_data_vld0( core2dbc_wr_data_vld0), + .core2dbc_wr_data_vld1( core2dbc_wr_data_vld1), + .core2dbc_wr_ecc_info( core2dbc_wr_ecc_info), + .core_dll( core_dll), + .crnt_clk( crnt_clk), + .csr_clk( csr_clk), + .csr_clk_left( csr_clk_left), + .csr_en( csr_en), + .csr_en_left( csr_en_left), + .csr_in( csr_in), + .csr_out( csr_out), + .csr_shift_n( csr_shift_n), + .ctl2dbc_cs0( ctl2dbc_cs0), + .ctl2dbc_cs1( ctl2dbc_cs1), + .ctl2dbc_mask_entry0( ctl2dbc_mask_entry0), + .ctl2dbc_mask_entry1( ctl2dbc_mask_entry1), + .ctl2dbc_misc0( ctl2dbc_misc0), + .ctl2dbc_misc1( ctl2dbc_misc1), + .ctl2dbc_mrnk_read0( ctl2dbc_mrnk_read0), + .ctl2dbc_mrnk_read1( ctl2dbc_mrnk_read1), + .ctl2dbc_nop0( ctl2dbc_nop0), + .ctl2dbc_nop1( ctl2dbc_nop1), + .ctl2dbc_rb_rdptr0( ctl2dbc_rb_rdptr0), + .ctl2dbc_rb_rdptr1( ctl2dbc_rb_rdptr1), + .ctl2dbc_rb_rdptr_vld0( ctl2dbc_rb_rdptr_vld0), + .ctl2dbc_rb_rdptr_vld1( ctl2dbc_rb_rdptr_vld1), + .ctl2dbc_rb_wrptr0( ctl2dbc_rb_wrptr0), + .ctl2dbc_rb_wrptr1( ctl2dbc_rb_wrptr1), + .ctl2dbc_rb_wrptr_vld0( ctl2dbc_rb_wrptr_vld0), + .ctl2dbc_rb_wrptr_vld1( ctl2dbc_rb_wrptr_vld1), + .ctl2dbc_rd_type0( ctl2dbc_rd_type0), + .ctl2dbc_rd_type1( ctl2dbc_rd_type1), + .ctl2dbc_rdata_en_full0( ctl2dbc_rdata_en_full0), + .ctl2dbc_rdata_en_full1( ctl2dbc_rdata_en_full1), + .ctl2dbc_seq_en0( ctl2dbc_seq_en0), + .ctl2dbc_seq_en1( ctl2dbc_seq_en1), + .ctl2dbc_wb_rdptr0( ctl2dbc_wb_rdptr0), + .ctl2dbc_wb_rdptr1( ctl2dbc_wb_rdptr1), + .ctl2dbc_wb_rdptr_vld0( ctl2dbc_wb_rdptr_vld0), + .ctl2dbc_wb_rdptr_vld1( ctl2dbc_wb_rdptr_vld1), + .ctl2dbc_wrdata_vld0( ctl2dbc_wrdata_vld0), + .ctl2dbc_wrdata_vld1( ctl2dbc_wrdata_vld1), + .data_from_core( data_from_core), + .data_to_core( data_to_core), + .dbc2core_rd_data_vld0( dbc2core_rd_data_vld0), + .dbc2core_rd_data_vld1( dbc2core_rd_data_vld1), + .dbc2core_rd_type( dbc2core_rd_type), + .dbc2core_wb_pointer( dbc2core_wb_pointer), + .dbc2core_wr_data_rdy( dbc2core_wr_data_rdy), + .dbc2ctl_all_rd_done( dbc2ctl_all_rd_done), + .dbc2ctl_rb_retire_ptr( dbc2ctl_rb_retire_ptr), + .dbc2ctl_rb_retire_ptr_vld( dbc2ctl_rb_retire_ptr_vld), + .dbc2ctl_rd_data_vld( dbc2ctl_rd_data_vld), + .dbc2ctl_wb_retire_ptr( dbc2ctl_wb_retire_ptr), + .dbc2ctl_wb_retire_ptr_vld( dbc2ctl_wb_retire_ptr_vld), + .dbc2db_wb_wrptr( dbc2db_wb_wrptr), + .dbc2db_wb_wrptr_vld( dbc2db_wb_wrptr_vld), + .dft_core2db( dft_core2db), + .dft_db2core( dft_db2core), + .dft_phy_clk( dft_phy_clk), + .dft_prbs_done( dft_prbs_done), + .dft_prbs_ena_n( dft_prbs_ena_n), + .dft_prbs_pass( dft_prbs_pass), + .dll_core( dll_core), + .dq_diff_in( dq_diff_in), + .dq_sstl_in( dq_sstl_in), + .dqs_diff_in_0( dqs_diff_in_0), + .dqs_diff_in_1( dqs_diff_in_1), + .dqs_diff_in_2( dqs_diff_in_2), + .dqs_diff_in_3( dqs_diff_in_3), + .dqs_sstl_n_0( dqs_sstl_n_0), + .dqs_sstl_n_1( dqs_sstl_n_1), + .dqs_sstl_n_2( dqs_sstl_n_2), + .dqs_sstl_n_3( dqs_sstl_n_3), + .dqs_sstl_p_0( dqs_sstl_p_0), + .dqs_sstl_p_1( dqs_sstl_p_1), + .dqs_sstl_p_2( dqs_sstl_p_2), + .dqs_sstl_p_3( dqs_sstl_p_3), + .dzoutx( dzoutx), + .early_bhniotri( early_bhniotri), + .early_csren( early_csren), + .early_enrnsl( early_enrnsl), + .early_frzreg( early_frzreg), + .early_nfrzdrv( early_nfrzdrv), + .early_niotri( early_niotri), + .early_plniotri( early_plniotri), + .early_usrmode( early_usrmode), + .enrnsl( enrnsl), + .entest( entest), + .fb_clkout( fb_clkout), + .fr_in_clk( fr_in_clk), + .fr_out_clk( fr_out_clk), + .frzreg( frzreg), + .hps_to_core_ctrl_en( hps_to_core_ctrl_en), + .hr_in_clk( hr_in_clk), + .hr_out_clk( hr_out_clk), + .i50u_ref( i50u_ref), + .ibp50u( ibp50u), + .ibp50u_cal( ibp50u_cal), + .ioereg_locked( ioereg_locked), + .jtag_clk( jtag_clk), + .jtag_highz( jtag_highz), + .jtag_mode( jtag_mode), + .jtag_sdin( jtag_sdin), + .jtag_sdout( jtag_sdout), + .jtag_shftdr( jtag_shftdr), + .jtag_updtdr( jtag_updtdr), + .lane_cal_done( lane_cal_done), + .local_bhniotri( local_bhniotri), + .local_enrnsl( local_enrnsl), + .local_frzreg( local_frzreg), + .local_nfrzdrv( local_nfrzdrv), + .local_niotri( local_niotri), + .local_plniotri( local_plniotri), + .local_usrmode( local_usrmode), + .local_wkpullup( local_wkpullup), + .lvds_rx_clk_chnl0( lvds_rx_clk_chnl0), + .lvds_rx_clk_chnl1( lvds_rx_clk_chnl1), + .lvds_rx_clk_chnl2( lvds_rx_clk_chnl2), + .lvds_rx_clk_chnl3( lvds_rx_clk_chnl3), + .lvds_rx_clk_chnl4( lvds_rx_clk_chnl4), + .lvds_rx_clk_chnl5( lvds_rx_clk_chnl5), + .lvds_tx_clk_chnl0( lvds_tx_clk_chnl0), + .lvds_tx_clk_chnl1( lvds_tx_clk_chnl1), + .lvds_tx_clk_chnl2( lvds_tx_clk_chnl2), + .lvds_tx_clk_chnl3( lvds_tx_clk_chnl3), + .lvds_tx_clk_chnl4( lvds_tx_clk_chnl4), + .lvds_tx_clk_chnl5( lvds_tx_clk_chnl5), + .mrnk_read_core( mrnk_read_core), + .mrnk_write_core( mrnk_write_core), + .n_crnt_clk( n_crnt_clk), + .n_next_clk( n_next_clk), + .naclr( naclr), + .ncein( ncein), + .nceout( nceout), + .next_clk( next_clk), + .nfrzdrv( nfrzdrv), + .niotri( niotri), + .nsclr( nsclr), + .oct_enable( oct_enable), + .oeb_from_core( oeb_from_core), + .osc_en_n( osc_en_n), + .osc_enable_in( osc_enable_in), + .osc_mode_in( osc_mode_in), + .osc_rocount_to_core( osc_rocount_to_core), + .osc_sel_n( osc_sel_n), + .phy_clk( phy_clk), + .phy_clk_phs( phy_clk_phs), + .pipeline_global_en_n( pipeline_global_en_n), + .pll_clk( pll_clk), + .pll_locked( pll_locked), + .plniotri( plniotri), + .progctl( progctl), + .progoe( progoe), + .progout( progout), + .rdata_en_full_core( rdata_en_full_core), + .rdata_valid_core( rdata_valid_core), + .regulator_clk( regulator_clk), + .reinit( reinit), + .reset_n( reset_n), + .scan_shift_n( scan_shift_n), + .scanin( scanin), + .scanout( scanout), + .switch_dn( switch_dn), + .switch_up( switch_up), + .sync_clk_bot_in( sync_clk_bot_in), + .sync_clk_bot_out( sync_clk_bot_out), + .sync_clk_top_in( sync_clk_top_in), + .sync_clk_top_out( sync_clk_top_out), + .sync_data_bot_in( sync_data_bot_in), + .sync_data_bot_out( sync_data_bot_out), + .sync_data_top_in( sync_data_top_in), + .sync_data_top_out( sync_data_top_out), + .test_avl_clk_in_en_n( test_avl_clk_in_en_n), + .test_clk( test_clk), + .test_clk_ph_buf_en_n( test_clk_ph_buf_en_n), + .test_clk_pll_en_n( test_clk_pll_en_n), + .test_clr_n( test_clr_n), + .test_datovr_en_n( test_datovr_en_n), + .test_db_csr_in( test_db_csr_in), + .test_dbg_in( test_dbg_in), + .test_dbg_out( test_dbg_out), + .test_dqs_csr_in( test_dqs_csr_in), + .test_dqs_enable_en_n( test_dqs_enable_en_n), + .test_fr_clk_en_n( test_fr_clk_en_n), + .test_hr_clk_en_n( test_hr_clk_en_n), + .test_int_clk_en_n( test_int_clk_en_n), + .test_interp_clk_en_n( test_interp_clk_en_n), + .test_ioereg2_csr_out( test_ioereg2_csr_out), + .test_phy_clk_en_n( test_phy_clk_en_n), + .test_phy_clk_lane_en_n( test_phy_clk_lane_en_n), + .test_pst_clk_en_n( test_pst_clk_en_n), + .test_pst_dll_i( test_pst_dll_i), + .test_pst_dll_o( test_pst_dll_o), + .test_tdf_select_n( test_tdf_select_n), + .test_vref_csr_out( test_vref_csr_out), + .test_xor_clk( test_xor_clk), + .tpctl( tpctl), + .tpdata( tpdata), + .tpin( tpin), + .up_ph( up_ph), + .usrmode( usrmode), + .vref_ext( vref_ext), + .vref_int( vref_int), + .weak_pullup_enable( weak_pullup_enable), + .wkpullup( wkpullup), + .x1024_osc_out( x1024_osc_out), + .xor_vref( xor_vref), + .xprio_clk( xprio_clk), + .xprio_sync( xprio_sync), + .xprio_xbus( xprio_xbus) +); + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/mem_array_abphy.sv b/ase/rtl/device_models/dcp_emif_model/mem_array_abphy.sv new file mode 100644 index 000000000000..50adee866240 --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/mem_array_abphy.sv @@ -0,0 +1,1578 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +`define _abphy_get_pin_count(_loc) ( _loc[ 9 : 0 ] ) +`define _abphy_get_pin_index(_loc, _port_i) ( _loc[ (_port_i + 1) * 10 +: 10 ] ) + +`define _abphy_get_tile(_loc, _port_i) ( `_abphy_get_pin_index(_loc, _port_i) / (PINS_PER_LANE * LANES_PER_TILE) ) +`define _abphy_get_lane(_loc, _port_i) ( (`_abphy_get_pin_index(_loc, _port_i) / PINS_PER_LANE) % LANES_PER_TILE ) +`define _abphy_get_pin(_loc, _port_i) ( `_abphy_get_pin_index(_loc, _port_i) % PINS_PER_LANE ) + +`define _abphy_sel_hmc_val(_tile_i, _pri, _sec) ( PHY_PING_PONG_EN ? (_tile_i <= SEC_AC_TILE_INDEX ? _sec : _pri) : _pri ) + + +`define _abphy_connect_to_abphy(_loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : aa \ + for (phase_i = 0; phase_i < _num_of_phases; ++phase_i) begin : bb \ + assign _abphy_port[phase_i][port_i] = _tile_data_port[ (`_abphy_get_pin_index(_loc, port_i)*8)+phase_i]; \ + end \ + end + + +`define _abphy_connect_to_abphy_oe(_loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port ) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : a \ + for (phase_i = 0; phase_i < _num_of_phases; ++phase_i) begin : b \ + assign _abphy_port[phase_i][port_i] = _tile_data_port[ (`_abphy_get_pin_index(_loc, port_i)*4)+phase_i]; \ + end \ + end + +`define _abphy_connect_to_abphy_oe2(_loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port ) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : c \ + for (phase_i = 0; phase_i < _num_of_phases; ++phase_i) begin : d \ + assign _abphy_port[phase_i][port_i] = _tile_data_port[ (`_abphy_get_pin_index(_loc, port_i)*4)+phase_i]; \ + end \ + end + +`define _abphy_connect_from_abphy(_loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : e \ + for (phase_i = 0; phase_i < _num_of_phases; ++phase_i) begin : f \ + assign _tile_data_port[ (`_abphy_get_pin_index(_loc, port_i)*8)+phase_i] = _abphy_port[phase_i][port_i]; \ + end \ + end +`define _abphy_connect_from_abphy2(_loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port) \ + for (port_i = 0; port_i < _mem_port_width; ++port_i) begin : g \ + for (phase_i = 0; phase_i < _num_of_phases; ++phase_i) begin : h \ + assign _tile_data_port[ (`_abphy_get_pin_index(_loc, port_i)*8)+phase_i] = _abphy_port[phase_i][port_i]; \ + end \ + end + +`define _abphy_connect_to_abphy_debug( _loc, _mem_port_width, _num_of_phases, _abphy_port, _tile_data_port) \ + initial begin \ + for (i = 0; i < _mem_port_width; ++i) begin \ + for (j = 0; j < _num_of_phases; ++j) begin \ + if ( DIAG_VERBOSE_IOAUX!=0 ) $display( "abphy %d/%d connected to tile=%-d,pin=%-d",i,j,`_abphy_get_tile(_loc,i),`_abphy_get_pin_index(_loc,i)%48); \ + end \ + end \ + end + +`define _get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) ( PINS_RATE[_tile_i * LANES_PER_TILE * PINS_PER_LANE + _lane_i * PINS_PER_LANE + _pin_i] ) +`define _get_pin_ddr_str(_tile_i, _lane_i, _pin_i) ( `_get_pin_ddr_raw(_tile_i, _lane_i, _pin_i) == PIN_RATE_DDR ? "mode_ddr" : "mode_sdr" ) +`define _get_pin_ddr_str_wrap(_loc, _port_i) (`_get_pin_ddr_str(`_abphy_get_tile(_loc,_port_i), `_abphy_get_lane(_loc,_port_i), `_abphy_get_pin(_loc,_port_i))) + +module mem_array_abphy # ( + parameter DIAG_VERBOSE_IOAUX = 0, + parameter NUM_OF_RTL_TILES = 1, + parameter LANES_PER_TILE = 4, + parameter PINS_PER_LANE = 12, + parameter PINS_RATE = 1'b0, + parameter MEM_DATA_MASK_EN = 1, + parameter USER_CLK_RATIO = 1, + parameter PHY_HMC_CLK_RATIO = 1, + parameter NUM_OF_HMC_PORTS = 0, + parameter PORT_MEM_A_PINLOC = 0, + parameter PORT_MEM_BA_PINLOC = 0, + parameter PORT_MEM_BG_PINLOC = 0, + parameter PORT_MEM_CS_N_PINLOC = 0, + parameter PORT_MEM_ACT_N_PINLOC = 0, + parameter PORT_MEM_DQ_PINLOC = 0, + parameter PORT_MEM_DM_PINLOC = 0, + parameter PORT_MEM_DBI_N_PINLOC = 0, + parameter PORT_MEM_RAS_N_PINLOC = 0, + parameter PORT_MEM_CAS_N_PINLOC = 0, + parameter PORT_MEM_WE_N_PINLOC = 0, + parameter PORT_MEM_REF_N_PINLOC = 0, + parameter PORT_MEM_WPS_N_PINLOC = 0, + parameter PORT_MEM_RPS_N_PINLOC = 0, + parameter PORT_MEM_BWS_N_PINLOC = 0, + parameter PORT_MEM_DQA_PINLOC = 0, + parameter PORT_MEM_DQB_PINLOC = 0, + parameter PORT_MEM_Q_PINLOC = 0, + parameter PORT_MEM_D_PINLOC = 0, + parameter PORT_MEM_RWA_N_PINLOC = 0, + parameter PORT_MEM_RWB_N_PINLOC = 0, + parameter PORT_MEM_QKA_PINLOC = 0, + parameter PORT_MEM_QKB_PINLOC = 0, + parameter PORT_MEM_LDA_N_PINLOC = 0, + parameter PORT_MEM_LDB_N_PINLOC = 0, + parameter PORT_MEM_CK_PINLOC = 0, + parameter PORT_MEM_DINVA_PINLOC = 0, + parameter PORT_MEM_DINVB_PINLOC = 0, + parameter PORT_MEM_AINV_PINLOC = 0, + parameter PORT_MEM_DQ_WIDTH = 0, + parameter PORT_MEM_A_WIDTH = 0, + parameter PORT_MEM_BA_WIDTH = 0, + parameter PORT_MEM_BG_WIDTH = 0, + parameter PORT_MEM_CS_N_WIDTH = 0, + parameter PORT_MEM_ACT_N_WIDTH = 0, + parameter PORT_MEM_DBI_N_WIDTH = 0, + parameter PORT_MEM_RAS_N_WIDTH = 0, + parameter PORT_MEM_CAS_N_WIDTH = 0, + parameter PORT_MEM_WE_N_WIDTH = 0, + parameter PORT_MEM_DM_WIDTH = 0, + parameter PORT_MEM_REF_N_WIDTH = 0, + parameter PORT_MEM_WPS_N_WIDTH = 0, + parameter PORT_MEM_RPS_N_WIDTH = 0, + parameter PORT_MEM_BWS_N_WIDTH = 0, + parameter PORT_MEM_DQA_WIDTH = 0, + parameter PORT_MEM_DQB_WIDTH = 0, + parameter PORT_MEM_Q_WIDTH = 0, + parameter PORT_MEM_D_WIDTH = 0, + parameter PORT_MEM_RWA_N_WIDTH = 0, + parameter PORT_MEM_RWB_N_WIDTH = 0, + parameter PORT_MEM_QKA_WIDTH = 0, + parameter PORT_MEM_QKB_WIDTH = 0, + parameter PORT_MEM_LDA_N_WIDTH = 0, + parameter PORT_MEM_LDB_N_WIDTH = 0, + parameter PORT_MEM_CK_WIDTH = 0, + parameter PORT_MEM_DINVA_WIDTH = 0, + parameter PORT_MEM_DINVB_WIDTH = 0, + parameter PORT_MEM_AINV_WIDTH = 0, + parameter PHY_PING_PONG_EN = 0, + parameter PROTOCOL_ENUM = "", + parameter DBI_WR_ENABLE = "", + parameter DBI_RD_ENABLE = "", + parameter PRI_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter PRI_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_COLADDR_WIDTH = "", + parameter SEC_HMC_CFG_MEM_IF_ROWADDR_WIDTH = "", + parameter MEM_BURST_LENGTH = 8, + parameter ABPHY_WRITE_PROTOCOL = 1 + +) ( + input phy_clk, + input reset_n, + input [12*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] select_ac_hmc, + input [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] ac_hmc, + input [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_data_to_mem, + input [48*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_oe, + input afi_cal_success, + input mem_rd_req, + input [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] afi_wlat, + input [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0][5:0] afi_rlat, + output reg [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] dq_data_from_mem, + output reg [3:0] rdata_valid_local [NUM_OF_RTL_TILES-1:0][LANES_PER_TILE-1:0], + input runAbstractPhySim +); + + timeunit 1ns; + timeprecision 1ps; + + typedef enum bit [0:0] { + PIN_RATE_DDR = 1'b0, + PIN_RATE_SDR = 1'b1 + } PIN_RATE; + + parameter [4:0] + pCMD_ACTIVE = (PROTOCOL_ENUM == "PROTOCOL_DDR4") ? 5'b00xxx : + ((PROTOCOL_ENUM == "PROTOCOL_DDR3") ? 5'b00110 : + ((PROTOCOL_ENUM == "PROTOCOL_LPDDR3") ? 5'b001x0 : + 5'b00011 )), + + pCMD_WRITE = (PROTOCOL_ENUM == "PROTOCOL_DDR4") ? 5'b01100 : + ((PROTOCOL_ENUM == "PROTOCOL_DDR3"|| PROTOCOL_ENUM == "PROTOCOL_LPDDR3") ? 5'b01000 : + ((PROTOCOL_ENUM == "PROTOCOL_RLD3" ) ? 5'b00100 : + ((PROTOCOL_ENUM == "PROTOCOL_QDR2") ? 5'b01000 : + ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? 5'b00000 : + 5'd0 )))), + + pCMD_READ = (PROTOCOL_ENUM == "PROTOCOL_DDR4") ? 5'b01101 : + ((PROTOCOL_ENUM == "PROTOCOL_DDR3" || PROTOCOL_ENUM == "PROTOCOL_LPDDR3") ? 5'b01010 : + ((PROTOCOL_ENUM == "PROTOCOL_RLD3") ? 5'b01100 : + ((PROTOCOL_ENUM == "PROTOCOL_QDR2") ? 5'b10000 : + ((PROTOCOL_ENUM == "PROTOCOL_QDR4") ? 5'b01000 : + 5'd0 )))), + pCMD_WRITE_N_READ = PROTOCOL_ENUM == "PROTOCOL_QDR2" ? 5'b00000 : 5'b10101; + + + parameter + pNO_RD_DATA = 'd0, + pCURRENT_RD_DATA = 'd1, + pDELAY_1_RD_DATA = 'd2, + pDELAY_2_RD_DATA = 'd3; + + parameter + pWS_IDLE = 'd0, + pWS_WR_N_CHECK_DATA = 'd1, + pWS_BUILD_DATA = 'd2; + + parameter + pRS_IDLE = 'd0, + pRS_READING = 'd1, + pRS_READ_UPPER = 'd2, + pRS_READ_BOTH = 'd3; + + localparam pLOCAL_DM_WIDTH = PROTOCOL_ENUM == "PROTOCOL_DDR4" ? PORT_MEM_DBI_N_WIDTH : + PROTOCOL_ENUM == "PROTOCOL_QDR2" ? PORT_MEM_BWS_N_WIDTH : + PORT_MEM_DM_WIDTH; + localparam pLOCAL_D_WIDTH = PROTOCOL_ENUM == "PROTOCOL_QDR2" ? PORT_MEM_D_WIDTH : + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? (PORT_MEM_DQA_WIDTH+PORT_MEM_DQB_WIDTH) : + PORT_MEM_DQ_WIDTH; + localparam pLOCAL_Q_WIDTH = PROTOCOL_ENUM == "PROTOCOL_QDR2" ? PORT_MEM_Q_WIDTH : + PROTOCOL_ENUM == "PROTOCOL_QDR4" ? (PORT_MEM_DQA_WIDTH+PORT_MEM_DQB_WIDTH) : + PORT_MEM_DQ_WIDTH; + + localparam LOCAL_ADDR_WIDTH = PROTOCOL_ENUM == "PROTOCOL_LPDDR3" ? 16 : PORT_MEM_A_WIDTH; + + + localparam pWRITE_PATH_LAT = 7; + localparam pWRITE_PATH_LAT_INDEX = pWRITE_PATH_LAT-1; + localparam pNUM_OF_INTF = PROTOCOL_ENUM == "PROTOCOL_QDR4" ? 2 : PHY_PING_PONG_EN+1; + localparam pNUM_OF_CHANS = PROTOCOL_ENUM == "PROTOCOL_QDR4" ? 2 : PORT_MEM_CS_N_WIDTH; + localparam PORT_MEM_DQ_WIDTH_PER_INTF = pLOCAL_D_WIDTH/pNUM_OF_INTF; + localparam PORT_MEM_DBI_N_WIDTH_PER_INTF = (pLOCAL_DM_WIDTH/pNUM_OF_INTF)>=1 ? pLOCAL_DM_WIDTH/pNUM_OF_INTF : 1; + + + localparam pDM_MASK_LEN = PROTOCOL_ENUM == "PROTOCOL_RLD3" ? 9 : PORT_MEM_DQ_WIDTH_PER_INTF/PORT_MEM_DBI_N_WIDTH_PER_INTF; + localparam pBANK_WIDTH = 4; + localparam pCMD_WIDTH = 5; + localparam pAC_PIPE_ADDR_WIDTH = (2*LOCAL_ADDR_WIDTH) + pBANK_WIDTH; + localparam pAC_PIPE_WIDTH = pAC_PIPE_ADDR_WIDTH + 2; + localparam pWR_MEM_PIPE_WIDTH = pAC_PIPE_ADDR_WIDTH + 1 +(PORT_MEM_DQ_WIDTH_PER_INTF*8)+(PORT_MEM_DBI_N_WIDTH_PER_INTF*8); + localparam pADDR_PIN_RATE = `_get_pin_ddr_str_wrap(PORT_MEM_A_PINLOC, (PORT_MEM_A_WIDTH/2)); + localparam pADDR_NUM_OF_PHASES = (`_get_pin_ddr_str_wrap(PORT_MEM_A_PINLOC, (PORT_MEM_A_WIDTH/2))=="mode_ddr"? 8:4); + + + reg [pCMD_WIDTH-1:0] cmd_d [pNUM_OF_CHANS-1:0][3:0]; + reg [PORT_MEM_A_WIDTH-1:0] addr_d [7:0]; + reg [pBANK_WIDTH-1:0] bank_d [3:0]; + reg [pLOCAL_D_WIDTH-1:0] data_d [7:0]; + reg [pLOCAL_DM_WIDTH-1:0] data_dm_d [7:0]; + reg [pLOCAL_DM_WIDTH-1:0] rd_dbi_d [7:0]; + reg [PORT_MEM_DINVA_WIDTH-1:0] rd_dinva_d [7:0]; + reg [PORT_MEM_DINVB_WIDTH-1:0] rd_dinvb_d [7:0]; + reg [pLOCAL_D_WIDTH-1:0] oe_d [3:0]; + reg [pLOCAL_D_WIDTH-1:0] oe_a_d [3:0]; + reg [pLOCAL_D_WIDTH-1:0] oe_b_d [3:0]; + reg [PORT_MEM_BA_WIDTH-1:0] bank_a_d [3:0]; + reg [PORT_MEM_BG_WIDTH-1:0] bank_g_d [3:0]; + reg [PORT_MEM_CS_N_WIDTH-1:0] cs_n_d [3:0]; + reg [PORT_MEM_ACT_N_WIDTH-1:0] act_n_d [3:0]; + reg [PORT_MEM_RAS_N_WIDTH-1:0] ras_n_d [3:0]; + reg [PORT_MEM_CAS_N_WIDTH-1:0] cas_n_d [3:0]; + reg [PORT_MEM_WE_N_WIDTH-1:0] we_n_d [3:0]; + reg [PORT_MEM_REF_N_WIDTH-1:0] ref_n_d [3:0]; + reg [PORT_MEM_WPS_N_WIDTH-1:0] wps_n_d [3:0]; + reg [PORT_MEM_RPS_N_WIDTH-1:0] rps_n_d [3:0]; + reg [PORT_MEM_DQA_WIDTH-1:0] dqa_d [7:0]; + reg [PORT_MEM_DQB_WIDTH-1:0] dqb_d [7:0]; + reg [PORT_MEM_RWA_N_WIDTH-1:0] rwa_n_d [7:0]; + reg [PORT_MEM_RWB_N_WIDTH-1:0] rwb_n_d [7:0]; + reg [PORT_MEM_LDA_N_WIDTH-1:0] lda_n_d [7:0]; + reg [PORT_MEM_LDB_N_WIDTH-1:0] ldb_n_d [7:0]; + reg [PORT_MEM_CK_WIDTH-1:0] ck_d [7:0]; + reg [PORT_MEM_DINVA_WIDTH-1:0] dinva_d [7:0]; + reg [PORT_MEM_DINVB_WIDTH-1:0] dinvb_d [7:0]; + reg [PORT_MEM_AINV_WIDTH-1:0] ainv_d [7:0]; + + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] data_muxd_d [pNUM_OF_INTF-1:0][7:0]; + reg [PORT_MEM_DBI_N_WIDTH_PER_INTF-1:0] data_dm_muxd_d [pNUM_OF_INTF-1:0][7:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] oe_muxd_d [pNUM_OF_INTF-1:0][3:0]; + reg [LOCAL_ADDR_WIDTH-1:0] col_addr_d [pADDR_NUM_OF_PHASES-1:0]; + + + reg [LOCAL_ADDR_WIDTH-1:0] row_addr [15:0][pNUM_OF_CHANS-1:0]; + reg [LOCAL_ADDR_WIDTH-1:0] row_addr_d [pNUM_OF_CHANS-1:0]; + reg [LOCAL_ADDR_WIDTH-1:0] lpddr3_row_addr_d [3:0]; + + + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] mem [*]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] mem_temp; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_temp_array [7:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_temp_array_mask; + + reg wr_WRITE_en [pNUM_OF_CHANS-1:0][3:0]; + reg wr_READ_en [pNUM_OF_CHANS-1:0][3:0]; + reg rd_en; + reg [(2*LOCAL_ADDR_WIDTH)+pBANK_WIDTH-1:0] wr_ac_data [pNUM_OF_CHANS-1:0][3:0]; + reg [LOCAL_ADDR_WIDTH-1:0] wr_ac_data_col_addr [pNUM_OF_CHANS-1:0][3:0]; + reg [LOCAL_ADDR_WIDTH-1:0] wr_ac_data_row_addr [pNUM_OF_CHANS-1:0][3:0]; + reg [pBANK_WIDTH-1:0] wr_ac_data_bank [pNUM_OF_CHANS-1:0][3:0]; + + reg [pAC_PIPE_WIDTH-1:0] ac_cmd_pipeline [63:0][pNUM_OF_CHANS-1:0][3:0]; + reg mem_wr_d [pNUM_OF_INTF-1:0]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] mem_data_d [pNUM_OF_INTF-1:0]; + reg [(PORT_MEM_DBI_N_WIDTH_PER_INTF*8)-1:0] mem_data_dm_d [pNUM_OF_INTF-1:0]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] rd_mem_data_d [pNUM_OF_CHANS-1:0][3:0]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] rd_mem_data [pNUM_OF_CHANS-1:0][3:0]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] rd_mem_data_r [pNUM_OF_CHANS-1:0][3:0]; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] rd_mem_data_shifted_d [pNUM_OF_CHANS-1:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] rd_mem_data_shifted_debug_d [pNUM_OF_CHANS-1:0][7:0]; + reg [1:0] rd_mem_shifted_en_d [pNUM_OF_CHANS-1:0][3:0][7:0]; + reg [3:0] rd_mem_shifted_element_d [pNUM_OF_CHANS-1:0][3:0][7:0]; + reg [3:0] mem_rd_amt_sent_d [pNUM_OF_CHANS-1:0][3:0]; + reg [3:0] mem_rd_amt_sent [pNUM_OF_CHANS-1:0][3:0]; + reg [1:0] mem_rd_delay_d [pNUM_OF_CHANS-1:0][3:0]; + reg [1:0] mem_rd_delay [pNUM_OF_CHANS-1:0][3:0]; + reg [3:0] mem_rd_amt_prev_to_send_d [pNUM_OF_CHANS-1:0][3:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_data [pNUM_OF_INTF-1:0][7:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_data_r1 [pNUM_OF_INTF-1:0][7:0]; + reg [PORT_MEM_DBI_N_WIDTH_PER_INTF-1:0] mem_data_dm [pNUM_OF_INTF-1:0][7:0]; + reg [PORT_MEM_DBI_N_WIDTH_PER_INTF-1:0] mem_data_dm_r1 [pNUM_OF_INTF-1:0][7:0]; + reg active_detected; + reg row_addr_d_en [pNUM_OF_CHANS-1:0]; + reg [3:0] active_bank; + reg [pWR_MEM_PIPE_WIDTH-1:0] WR_mem_pipeline [15:0][pNUM_OF_CHANS-1:0][3:0]; + reg [1:0] mem_rd_state_d [pNUM_OF_CHANS-1:0][3:0]; + reg [1:0] mem_rd_state [pNUM_OF_CHANS-1:0][3:0]; + reg [pAC_PIPE_ADDR_WIDTH-1:0] RD_mem_addr_d [pNUM_OF_CHANS-1:0][3:0]; + reg RD_req_d [pNUM_OF_CHANS-1:0][3:0]; + reg WR_req_d [pNUM_OF_CHANS-1:0][3:0]; + reg [pAC_PIPE_ADDR_WIDTH-1:0] WR_mem_addr_d [pNUM_OF_CHANS-1:0][3:0]; + reg mem_wr_pipe [pNUM_OF_CHANS-1:0][3:0]; + reg [pAC_PIPE_ADDR_WIDTH-1:0] mem_addr_pipe [pNUM_OF_CHANS-1:0][3:0]; + reg [pAC_PIPE_ADDR_WIDTH-1:0] temp_addr; + reg [(PORT_MEM_DQ_WIDTH_PER_INTF*8)-1:0] mem_data_pipe [pNUM_OF_CHANS-1:0][3:0]; + reg [(PORT_MEM_DBI_N_WIDTH_PER_INTF*8)-1:0] mem_data_dm_pipe [pNUM_OF_CHANS-1:0][3:0]; + reg [pLOCAL_Q_WIDTH-1:0] rd_data_d [7:0]; + reg [PORT_MEM_DQA_WIDTH-1:0] rd_data_a_d [7:0]; + reg [PORT_MEM_DQB_WIDTH-1:0] rd_data_b_d [7:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] rd_data_debug_d [pNUM_OF_CHANS-1:0][3:0][7:0]; + reg [5:0] afi_rlat_sel [pNUM_OF_CHANS-1:0]; + reg [5:0] afi_wlat_sel [pNUM_OF_CHANS-1:0]; + reg [5:0] afi_wlat_sel_tmp; + reg [5:0] afi_rlat_sel_tmp; + reg [5:0] afi_wlat_sel_phase [pNUM_OF_CHANS-1:0][3:0]; + reg [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_data_ph_d [pNUM_OF_CHANS-1:0][3:0][7:0]; + reg [PORT_MEM_DBI_N_WIDTH_PER_INTF-1:0] mem_data_dm_ph_d [pNUM_OF_CHANS-1:0][3:0][7:0]; + reg [3:0] rdata_valid_local_per_chan [pNUM_OF_CHANS-1:0]; + + reg first_wr; + + + wire [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] wr_data_d [7:0][pNUM_OF_CHANS-1:0][3:0]; + wire [PORT_MEM_DQ_WIDTH_PER_INTF-1:0] mem_data_pipe_array [pNUM_OF_CHANS-1:0][3:0][7:0]; + wire [PORT_MEM_DBI_N_WIDTH_PER_INTF-1:0] mem_data_dm_pipe_array [pNUM_OF_CHANS-1:0][3:0][7:0]; + wire [96*NUM_OF_RTL_TILES*LANES_PER_TILE-1:0] ac_data_to_mem; + wire [31:0] banks_per_write; + + integer i,j,k,ii,jj,aa,bb,phase_num,cs_num,beat_num; + integer interface_num; + integer high_addr; + + assign ac_data_to_mem = ( NUM_OF_HMC_PORTS==0 ) ? dq_data_to_mem : ac_hmc; + + assign banks_per_write = PROTOCOL_ENUM != "PROTOCOL_RLD3" || ABPHY_WRITE_PROTOCOL==0 ? 1 : ABPHY_WRITE_PROTOCOL*2; + + generate + genvar port_i; + genvar phase_i; + genvar cs_i; + + + if (`_abphy_get_pin_count(PORT_MEM_A_PINLOC) != 0) begin : mem_a + `_abphy_connect_to_abphy(PORT_MEM_A_PINLOC, PORT_MEM_A_WIDTH, pADDR_NUM_OF_PHASES, addr_d, ac_data_to_mem ) + end + + if (`_abphy_get_pin_count(PORT_MEM_BA_PINLOC) != 0) begin : mem_ba + `_abphy_connect_to_abphy(PORT_MEM_BA_PINLOC, PORT_MEM_BA_WIDTH, 4, bank_a_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_BG_PINLOC) != 0) begin : mem_bg + `_abphy_connect_to_abphy(PORT_MEM_BG_PINLOC, PORT_MEM_BG_WIDTH, 4, bank_g_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_CS_N_PINLOC) != 0) begin : mem_cs_n + `_abphy_connect_to_abphy(PORT_MEM_CS_N_PINLOC, PORT_MEM_CS_N_WIDTH, 4, cs_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_ACT_N_PINLOC) != 0) begin : mem_act_n + `_abphy_connect_to_abphy(PORT_MEM_ACT_N_PINLOC, PORT_MEM_ACT_N_WIDTH, 4, act_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_RAS_N_PINLOC) != 0) begin : mem_ras + `_abphy_connect_to_abphy(PORT_MEM_RAS_N_PINLOC, PORT_MEM_RAS_N_WIDTH, 4, ras_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_CAS_N_PINLOC) != 0) begin : mem_cas + `_abphy_connect_to_abphy(PORT_MEM_CAS_N_PINLOC, PORT_MEM_CAS_N_WIDTH, 4, cas_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_WE_N_PINLOC) != 0) begin : mem_we_n + `_abphy_connect_to_abphy(PORT_MEM_WE_N_PINLOC, PORT_MEM_WE_N_WIDTH, 4, we_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_REF_N_PINLOC) != 0) begin : mem_ref_n + `_abphy_connect_to_abphy(PORT_MEM_REF_N_PINLOC, PORT_MEM_REF_N_WIDTH, 4, ref_n_d, ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_WPS_N_PINLOC) != 0) begin : mem_wps_n + `_abphy_connect_to_abphy(PORT_MEM_WPS_N_PINLOC,PORT_MEM_WPS_N_WIDTH , 4, wps_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_RPS_N_PINLOC) != 0) begin : mem_rps_n + `_abphy_connect_to_abphy(PORT_MEM_RPS_N_PINLOC,PORT_MEM_RPS_N_WIDTH , 4, rps_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_DINVA_PINLOC) != 0) begin : mem_dinva + `_abphy_connect_to_abphy(PORT_MEM_DINVA_PINLOC,PORT_MEM_DINVA_WIDTH , 8, dinva_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_DINVB_PINLOC) != 0) begin : mem_dinvb + `_abphy_connect_to_abphy(PORT_MEM_DINVB_PINLOC,PORT_MEM_DINVB_WIDTH , 8, dinvb_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_AINV_PINLOC) != 0) begin : mem_ainv + `_abphy_connect_to_abphy(PORT_MEM_AINV_PINLOC,PORT_MEM_AINV_WIDTH , 8, ainv_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_DQA_PINLOC) != 0) begin : mem_dqa + `_abphy_connect_to_abphy(PORT_MEM_DQA_PINLOC,PORT_MEM_DQA_WIDTH , 8, dqa_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_DQB_PINLOC) != 0) begin : mem_dqb + `_abphy_connect_to_abphy(PORT_MEM_DQB_PINLOC,PORT_MEM_DQB_WIDTH , 8, dqb_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_RWA_N_PINLOC) != 0) begin : mem_rwa_n + `_abphy_connect_to_abphy(PORT_MEM_RWA_N_PINLOC,PORT_MEM_RWA_N_WIDTH , 8, rwa_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_RWB_N_PINLOC) != 0) begin : mem_rwb_n + `_abphy_connect_to_abphy(PORT_MEM_RWB_N_PINLOC,PORT_MEM_RWB_N_WIDTH , 8, rwb_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_LDA_N_PINLOC) != 0) begin : mem_lda_n + `_abphy_connect_to_abphy(PORT_MEM_LDA_N_PINLOC,PORT_MEM_LDA_N_WIDTH , 8, lda_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_LDB_N_PINLOC) != 0) begin : mem_ldb_n + `_abphy_connect_to_abphy(PORT_MEM_LDB_N_PINLOC,PORT_MEM_LDB_N_WIDTH , 8, ldb_n_d , ac_data_to_mem) + end + + if (`_abphy_get_pin_count(PORT_MEM_CK_PINLOC) != 0) begin : mem_ck + `_abphy_connect_to_abphy(PORT_MEM_CK_PINLOC,PORT_MEM_CK_WIDTH , 8, ck_d , ac_data_to_mem) + end + + + if ( PROTOCOL_ENUM == "PROTOCOL_QDR2" ) begin : mem_d_qdr2 + `_abphy_connect_to_abphy (PORT_MEM_D_PINLOC, pLOCAL_D_WIDTH , 8, data_d, dq_data_to_mem) + `_abphy_connect_to_abphy_oe(PORT_MEM_D_PINLOC, pLOCAL_D_WIDTH, 4, oe_d, dq_oe) + `_abphy_connect_from_abphy (PORT_MEM_Q_PINLOC, pLOCAL_Q_WIDTH, 8, rd_data_d, dq_data_from_mem) + end + else if ( PROTOCOL_ENUM == "PROTOCOL_QDR4" ) begin : mem_d_qdr4 + `_abphy_connect_to_abphy_oe(PORT_MEM_DQA_PINLOC,PORT_MEM_DQA_WIDTH, 4, oe_a_d, dq_oe) + `_abphy_connect_to_abphy_oe2(PORT_MEM_DQB_PINLOC,PORT_MEM_DQB_WIDTH, 4, oe_b_d, dq_oe) + for (port_i = 0; port_i < pLOCAL_D_WIDTH; ++port_i) begin : cc + for (phase_i = 0; phase_i < 4; ++phase_i) begin : dd + if ( port_i=(pNUM_OF_CHANS/2) ) begin + if ( PHY_HMC_CLK_RATIO==4 ) begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))] - 2; + end + else begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))] - 1; + end + afi_rlat_sel[j] = afi_rlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, (PORT_MEM_DQ_WIDTH/2))] - 4; + end + else begin + if ( PHY_HMC_CLK_RATIO==4 ) begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)]; + end + else begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] + 1; + end + afi_rlat_sel[j] = afi_rlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] - 2; + end + end + else begin + if ( PHY_HMC_CLK_RATIO==4 ) begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)]; + end + else begin + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] + 1; + end + afi_rlat_sel[j] = afi_rlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] - 2; + end + end + else if ( PROTOCOL_ENUM == "PROTOCOL_QDR4" ) begin + afi_wlat_sel_tmp = j==0 ? afi_wlat[`_abphy_get_tile(PORT_MEM_DQA_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQA_PINLOC, 0)] : + afi_wlat[`_abphy_get_tile(PORT_MEM_DQB_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQB_PINLOC, 0)]; + afi_rlat_sel_tmp = j==0 ? afi_rlat[`_abphy_get_tile(PORT_MEM_DQA_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQA_PINLOC, 0)] : + afi_rlat[`_abphy_get_tile(PORT_MEM_DQB_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQB_PINLOC, 0)]; + if ( PHY_HMC_CLK_RATIO==2 && MEM_BURST_LENGTH==8 ) + + afi_wlat_sel[j] = afi_wlat_sel_tmp + 1; + else if ( MEM_BURST_LENGTH==2 ) + afi_wlat_sel[j] = afi_wlat_sel_tmp - 1; + else + afi_wlat_sel[j] = afi_wlat_sel_tmp; + + if ( NUM_OF_HMC_PORTS==0 ) begin + afi_wlat_sel[j] = afi_wlat_sel[j]-1; + end + afi_rlat_sel[j] = afi_rlat_sel_tmp - 2; + end + else begin + if ( PHY_HMC_CLK_RATIO==2 && MEM_BURST_LENGTH==8 ) + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] + 1; + else if ( MEM_BURST_LENGTH==2 ) + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] - 1; + else + afi_wlat_sel[j] = afi_wlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)]; + + if ( NUM_OF_HMC_PORTS==0 ) begin + afi_wlat_sel[j] = afi_wlat_sel[j]-1; + end + afi_rlat_sel[j] = afi_rlat[`_abphy_get_tile(PORT_MEM_DQ_PINLOC, 0)][`_abphy_get_lane(PORT_MEM_DQ_PINLOC, 0)] - 2; + end + end + end + + integer mod_phase,rounded_num_of_cycles,max_num_of_cycles; + always @ ( negedge phy_clk ) begin + for ( j=0; j1 && cs_num>=(pNUM_OF_CHANS/pNUM_OF_INTF))? 1 : 0; + for ( phase_num=0; phase_num<4; phase_num++ ) begin + if ( WR_req_d[cs_num][phase_num] ) begin + curr_element = ((phase_num+(MEM_BURST_LENGTH/2)-1)*2)%(PHY_HMC_CLK_RATIO*2)+1; + reverse_cnt = (PHY_HMC_CLK_RATIO*2)-curr_element-1; + for ( beat_num=MEM_BURST_LENGTH-1; beat_num>=0; beat_num-- ) begin + if ( reverse_cnt<(2*PHY_HMC_CLK_RATIO) ) begin + mem_data_ph_d[cs_num][phase_num][beat_num] = data_muxd_d[interface_num][curr_element]; + mem_data_dm_ph_d[cs_num][phase_num][beat_num] = data_dm_muxd_d[interface_num][curr_element]; + end + else if ( reverse_cnt<(4*PHY_HMC_CLK_RATIO) ) begin + mem_data_ph_d[cs_num][phase_num][beat_num] = mem_data[interface_num][curr_element]; + mem_data_dm_ph_d[cs_num][phase_num][beat_num] = mem_data_dm[interface_num][curr_element]; + end + else begin + mem_data_ph_d[cs_num][phase_num][beat_num] = mem_data_r1[interface_num][curr_element]; + mem_data_dm_ph_d[cs_num][phase_num][beat_num] = mem_data_dm_r1[interface_num][curr_element]; + end + reverse_cnt++; + curr_element = curr_element==0 ? (PHY_HMC_CLK_RATIO*2)-1 : (curr_element-1); + end + end + end + end + end + + always @ ( posedge phy_clk or negedge reset_n ) begin + if ( ~reset_n ) begin + for ( i=0; iMEM_BURST_LENGTH ? MEM_BURST_LENGTH : ((PHY_HMC_CLK_RATIO-phase_to_put_data_too)*2); + mem_rd_delay_d[j][k] = 'd0; + for ( i=0; i<8; i++ ) begin + if ( i>=(2*phase_to_put_data_too) && i<((2*phase_to_put_data_too)+mem_rd_amt_sent_d[j][k]) ) begin + rd_mem_shifted_en_d[j][k][i] = pCURRENT_RD_DATA; + rd_mem_shifted_element_d[j][k][i] = i-(2*phase_to_put_data_too); + end + end + end + else begin + mem_rd_state_d[j][k] = pRS_IDLE; + mem_rd_amt_sent_d[j][k] = 'd0; + mem_rd_delay_d[j][k] = 'd0; + end + end + + pRS_READING: begin + + for ( i=0; i<8; i++ ) begin + rd_mem_shifted_en_d[j][k][i] = pNO_RD_DATA; + rd_mem_shifted_element_d[j][k][i] = 'd0; + mem_rd_amt_prev_to_send_d[j][k] = 'd0; + end + + if ( RD_req_d[j][k] ) begin + mem_rd_state_d[j][k] = pRS_READING; + mem_rd_amt_sent_d[j][k] = ((PHY_HMC_CLK_RATIO-phase_to_put_data_too)*2)>MEM_BURST_LENGTH ? MEM_BURST_LENGTH : ((PHY_HMC_CLK_RATIO-phase_to_put_data_too)*2); + mem_rd_delay_d[j][k] = 'd0; + for ( i=0; i<8; i++ ) begin + if ( i>=(2*phase_to_put_data_too) && i<((2*phase_to_put_data_too)+mem_rd_amt_sent_d[j][k]) ) begin + rd_mem_shifted_en_d[j][k][i] = pCURRENT_RD_DATA; + rd_mem_shifted_element_d[j][k][i] = i-(2*phase_to_put_data_too); + end + end + end + else begin + if ( mem_rd_amt_sent[j][k]MEM_BURST_LENGTH ? MEM_BURST_LENGTH : + mem_rd_amt_sent[j][k] + (2*PHY_HMC_CLK_RATIO); + mem_rd_delay_d[j][k] = mem_rd_delay[j][k]+'d1; + end + else begin + mem_rd_state_d[j][k] = pRS_IDLE; + mem_rd_amt_sent_d[j][k] = 'd0; + mem_rd_delay_d[j][k] = 'd0; + end + end + + if ( mem_rd_amt_sent[j][k]0 ) begin + if ( (mem_rd_amt_sent[j][k]+(2*PHY_HMC_CLK_RATIO))>MEM_BURST_LENGTH ) begin + mem_rd_amt_prev_to_send_d[j][k] = MEM_BURST_LENGTH-mem_rd_amt_sent[j][k]; + end + else begin + mem_rd_amt_prev_to_send_d[j][k] = mem_rd_amt_sent[j][k] + (2*PHY_HMC_CLK_RATIO); + end + for ( i=0; i'd0 ? pDELAY_2_RD_DATA : pDELAY_1_RD_DATA; + rd_mem_shifted_element_d[j][k][i] = mem_rd_amt_sent[j][k]+i; + end + end + else begin + mem_rd_amt_prev_to_send_d[j][k] = 'd0; + end + + end + endcase + end + end + end + + + + always @ ( posedge phy_clk or negedge reset_n ) begin + if ( ~reset_n ) begin + for ( j=0; j 0) ? 1 : 0); +localparam dqs_shrink_delay_phase_adj = (dqs_shrink_delay_full_dram_cycles * out_rate_fact * 128) - dqs_shrink_delay; + +localparam dqs_enable_gate_delay = 128 * (195 / ((1.0 / phy_clk_phs_freq) * (10**6))); +localparam output_gate_delay = 128 * ( 56 / ((1.0 / phy_clk_phs_freq) * (10**6))); +localparam [12:0] net_gate_delays = output_gate_delay - dqs_enable_gate_delay; + +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_enable_delay = (mode_rate_out == "out_rate_full" ) ? ((mode_rate_in == "in_rate_1_4") ? dqs_enable_delay - (pipe_latency * 4) - 6'd04 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + (mode_rate_in == "in_rate_1_2") ? dqs_enable_delay - (pipe_latency * 2) - 6'd02 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + dqs_enable_delay - (pipe_latency * 1) - 6'd01 - 6'd01 - dqs_shrink_delay_full_dram_cycles ) : + (mode_rate_out == "out_rate_1_2" ) ? ((mode_rate_in == "in_rate_1_4") ? dqs_enable_delay - (pipe_latency * 4) - 6'd04 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + (mode_rate_in == "in_rate_1_2") ? dqs_enable_delay - (pipe_latency * 2) - 6'd02 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + dqs_enable_delay - (pipe_latency * 1) - 6'd01 - 6'd01 - dqs_shrink_delay_full_dram_cycles ) : + (mode_rate_out == "out_rate_1_4" ) ? ((mode_rate_in == "in_rate_1_4") ? dqs_enable_delay - (pipe_latency * 4) - 6'd04 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + (mode_rate_in == "in_rate_1_2") ? dqs_enable_delay - (pipe_latency * 2) - 6'd02 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + dqs_enable_delay - (pipe_latency * 1) - 6'd01 - 6'd01 - dqs_shrink_delay_full_dram_cycles ) : + ((mode_rate_in == "in_rate_1_4") ? dqs_enable_delay - (pipe_latency * 4) - 6'd04 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + (mode_rate_in == "in_rate_1_2") ? dqs_enable_delay - (pipe_latency * 2) - 6'd02 - 6'd01 - dqs_shrink_delay_full_dram_cycles : + dqs_enable_delay - (pipe_latency * 1) - 6'd01 - 6'd01 - dqs_shrink_delay_full_dram_cycles ) ; + +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_a = dqs_lgc_phase_shift_a + net_gate_delays + dqs_shrink_delay_phase_adj; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_phase_shift_b = dqs_lgc_phase_shift_b + net_gate_delays + dqs_shrink_delay_phase_adj; + +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_a = (dqs_lgc_dqs_a_interp_en == "true") ? "a_dqs_interpolator" : + (dqs_lgc_swap_dqs_a_b == "true") ? "a_dqs_sstl_n_0" : + (db_crc_x4_or_x8_or_x9 == "x4_mode") ? "a_dqs_diff_in_1" : + "a_dqs_sstl_p_0" ; + +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_dqs_select_b = (dqs_lgc_dqs_b_interp_en == "true") ? "b_dqs_interpolator" : + (dqs_lgc_swap_dqs_a_b == "true") ? "b_dqs_sstl_p_0" : + (db_crc_x4_or_x8_or_x9 == "x4_mode") ? "b_dqs_diff_in_0" : + "b_dqs_sstl_n_0" ; + +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_enable_toggler = dqs_lgc_enable_toggler; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_filter_code = (phy_clk_phs_freq >= 500 && phy_clk_phs_freq < 600) ? "freq_08ghz" : + (phy_clk_phs_freq >= 600 && phy_clk_phs_freq < 750) ? "freq_10ghz" : + (phy_clk_phs_freq >= 750 && phy_clk_phs_freq < 950) ? "freq_12ghz" : + "freq_16ghz"; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_kicker_size = 2'h1; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_lock_edge = "preamble_lock_rising_edge"; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_in = mode_rate_in; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_mode_rate_out = mode_rate_out; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_0_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_1_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_2_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_3_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_4_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_5_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_6_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_7_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_8_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_9_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_10_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dq_11_delay = 9'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_non_pvt_dqs_delay = 10'd0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_oct_size = 3'h1; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_pack_mode = dqs_lgc_pack_mode; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_phy_clk_mode = (phy_clk_sel == 0) ? "phy_clk_0" : "phy_clk_1"; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_probe_sel = 4'h0; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_en_shrink = dqs_lgc_pst_en_shrink; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_pst_preamble_mode = dqs_lgc_pst_preamble_mode; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_a = dqs_lgc_pvt_input_delay_a; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_pvt_input_delay_b = dqs_lgc_pvt_input_delay_b; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_rd_valid_delay = rd_valid_delay; +defparam u_io_12_lane_bcm.xio_dqs_lgc_top__dqs_lgc_pnr__a_track_speed = 4'hc; + +defparam u_io_12_lane_bcm.xio_regulator__a_cr_atbsel0 = "cr_atbsel0_dis"; +defparam u_io_12_lane_bcm.xio_regulator__a_cr_atbsel1 = "cr_atbsel1_dis"; +defparam u_io_12_lane_bcm.xio_regulator__a_cr_atbsel2 = "cr_atbsel2_dis"; +defparam u_io_12_lane_bcm.xio_regulator__a_cr_pd = "cr_pd_dis"; + + + +defparam u_io_12_lane_bcm.ioereg_top_0___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_0___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_1___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_1___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_2___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_2___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_3___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_3___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_4___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_4___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_5___gpio_wrapper_0__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; +defparam u_io_12_lane_bcm.ioereg_top_5___gpio_wrapper_1__gpio_reg__xio_jtag__a_rb_gpio_or_ddr_sel = "jtag_ddr_sel"; + +defparam u_io_12_lane_bcm.i0.ioereg_top_0_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_0_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_1_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_1_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_2_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_2_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_3_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_3_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_4_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_4_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_5_.interpolator_0.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.ioereg_top_5_.interpolator_1.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.xio_dqs_lgc_top.interpolator_a.fast_interpolator_sim = fast_interpolator_sim; +defparam u_io_12_lane_bcm.i0.xio_dqs_lgc_top.interpolator_b.fast_interpolator_sim = fast_interpolator_sim; + +endmodule diff --git a/ase/rtl/device_models/dcp_emif_model/verbosity_pkg.sv b/ase/rtl/device_models/dcp_emif_model/verbosity_pkg.sv new file mode 100644 index 000000000000..9b0e5834894d --- /dev/null +++ b/ase/rtl/device_models/dcp_emif_model/verbosity_pkg.sv @@ -0,0 +1,199 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + +// $Id: //acds/rel/17.0/ip/sopc/components/verification/lib/verbosity_pkg.sv#1 $ +// $Revision: #1 $ +// $Date: 2017/02/12 $ +//----------------------------------------------------------------------------- +// =head1 NAME +// verbosity_pkg +// =head1 SYNOPSIS +// Package for controlling verbosity of messages sent to the console +//----------------------------------------------------------------------------- +// =head1 DESCRIPTION +// This module will dump diagnostic messages to the console during +// simulation. The level of verbosity can be controlled in the test +// bench by using the *set_verbosity* method in the imported package +// verbosity_pkg. For a given setting, message at that level and all +// lower levels are dumped. For example, setting VERBOSITY_DEBUG level +// causes all messages to be dumped, while VERBOSITY_FAILURE restricts +// only failure messages and those tagged as VERBOSITY_NONE to be +// dumped. +// The different levels are: +// =over 4 +// =item 1 VERBOSITY_NONE +// Messages tagged with this level are always dumped to the console. +// =item 2 VERBOSITY_FAILURE +// A fatal simulation error has occurred and the simulator will exit. +// =item 3 VERBOSITY_ERROR +// A non-fatal error has occured. An example is a data comparison mismatch. +// =item 4 VERBOSITY_WARNING +// Warn the user that a potential error has occurred. +// =item 5 VERBOSITY_INFO +// Informational message. +// =item 6 VERBOSITY_DEBUG +// Dump enough state to diagnose problem scenarios. +// =back + + +`ifndef _AVALON_VERBOSITY_PKG_ +`define _AVALON_VERBOSITY_PKG_ + +package verbosity_pkg; + + timeunit 1ps; + timeprecision 1ps; + + typedef enum int {VERBOSITY_NONE, + VERBOSITY_FAILURE, + VERBOSITY_ERROR, + VERBOSITY_WARNING, + VERBOSITY_INFO, + VERBOSITY_DEBUG} Verbosity_t; + + Verbosity_t verbosity = VERBOSITY_INFO; + string message = ""; + int dump_file; + int dump = 0; + + //-------------------------------------------------------------------------- + // =head1 Public Methods API + // =pod + // This section describes the public methods in the application programming + // interface (API). In this case the application program is the test bench + // or component which imports this package. + // =cut + //-------------------------------------------------------------------------- + + function automatic Verbosity_t get_verbosity(); // public + // Returns the global verbosity setting. + return verbosity; + endfunction + + function automatic void set_verbosity ( // public + Verbosity_t v + ); + // Sets the global verbosity setting. + + string verbosity_str; + verbosity = v; + + case(verbosity) + VERBOSITY_NONE: verbosity_str = "VERBOSITY_"; + VERBOSITY_FAILURE: verbosity_str = "VERBOSITY_FAILURE"; + VERBOSITY_ERROR: verbosity_str = "VERBOSITY_ERROR"; + VERBOSITY_WARNING: verbosity_str = "VERBOSITY_WARNING"; + VERBOSITY_INFO: verbosity_str = "VERBOSITY_INFO"; + VERBOSITY_DEBUG: verbosity_str = "VERBOSITY_DEBUG"; + default: verbosity_str = "UNKNOWN"; + endcase + $sformat(message, "%m: Setting Verbosity level=%0d (%s)", + verbosity, verbosity_str); + print(VERBOSITY_NONE, message); + endfunction + + function automatic void print( // public + Verbosity_t level, + string message + ); + // Print a message to the console if the verbosity argument + // is less than or equal to the global verbosity setting. + string level_str; + + if (level <= verbosity) begin + case(level) + VERBOSITY_NONE: level_str = ""; + VERBOSITY_FAILURE: level_str = "FAILURE:"; + VERBOSITY_ERROR: level_str = "ERROR:"; + VERBOSITY_WARNING: level_str = "WARNING:"; + VERBOSITY_INFO: level_str = "INFO:"; + VERBOSITY_DEBUG: level_str = "DEBUG:"; + default: level_str = "UNKNOWN:"; + endcase + + $display("%t: %s %s",$time, level_str, message); + if (dump) begin + $fdisplay(dump_file, "%t: %s %s",$time, level_str, message); + end + end + endfunction + + function automatic void print_divider( // public + Verbosity_t level + ); + // Prints a divider line to the console to make a block of related text + // easier to identify and read. + string message; + $sformat(message, + "------------------------------------------------------------"); + print(level, message); + endfunction + + function automatic void open_dump_file ( // public + string dump_file_name = "avalon_bfm_sim.log" + ); + // Opens a dump file which collects console messages. + + if (dump) begin + $sformat(message, "%m: Dump file already open - ignoring open."); + print(VERBOSITY_ERROR, message); + end else begin + dump_file = $fopen(dump_file_name, "w"); + $fdisplay(dump_file, "testing dump file"); + $sformat(message, "%m: Opening dump file: %s", dump_file_name); + print(VERBOSITY_INFO, message); + dump = 1; + end + endfunction + + function automatic void close_dump_file(); // public + // Close the console message dump file. + if (!dump) begin + $sformat(message, "%m: No open dump file - ignoring close."); + print(VERBOSITY_ERROR, message); + end else begin + dump = 0; + $fclose(dump_file); + $sformat(message, "%m: Closing dump file"); + print(VERBOSITY_INFO, message); + end + endfunction + + function automatic void abort_simulation(); + string message; + $sformat(message, "%m: Abort the simulation due to fatal error incident."); + print(VERBOSITY_FAILURE, message); + $stop; + endfunction + +endpackage + +// =cut + +`endif + diff --git a/ase/rtl/inorder_wrf_channel.sv b/ase/rtl/inorder_wrf_channel.sv new file mode 100644 index 000000000000..24107b8221d5 --- /dev/null +++ b/ase/rtl/inorder_wrf_channel.sv @@ -0,0 +1,443 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: In-order transaction channel + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * ********************************************************************************* + * SR 4.1.x - SR 5.0.0-prealpha implementation + * --------------------------------------------------------------------------------- + * - Transactions are stored when request comes from AFU + * - This is a normal DPI-C call to C functions + * - When a response is received, the response is queued in normal format + * + * THIS COMPONENT + * - simply re-orders requests and sends them out + * - May not necessarily be synthesizable + * + * OPERATION: + * - {meta_in, data_in} is validated with write_en signal + * - An empty slot is found, a random delay is computed based on pre-known parameters + * - The state machine is kicked off. + * + * GENERICS: + * - NUM_WAIT_STATIONS : Number of transactions in latency buffer + * - FIFO_FULL_THRESH : FIFO full threshold + * - FIFO_DEPTH_BASE2 : FIFO depth radix + * + */ + +import ase_pkg::*; + +`include "platform.vh" + +module inorder_wrf_channel + #( + parameter string DEBUG_LOGNAME = "channel.log", + parameter int NUM_WAIT_STATIONS = 8, + parameter int NUM_STATIONS_FULL_THRESH = 3, + parameter int COUNT_WIDTH = 8, + parameter int VISIBLE_DEPTH_BASE2 = 8, + parameter int VISIBLE_FULL_THRESH = 220, + parameter int LATBUF_MAX_TXN = 4, + parameter int WRITE_CHANNEL = 0 + ) + ( + input logic clk, + input logic rst, + input logic finish_trigger, + // Transaction in + input TxHdr_t hdr_in, + input logic [CCIP_DATA_WIDTH-1:0] data_in, + input logic write_en, + // Transaction out + output TxHdr_t txhdr_out, + output RxHdr_t rxhdr_out, + output logic [CCIP_DATA_WIDTH-1:0] data_out, + output logic valid_out, + input logic read_en, + // Status signals + output logic empty, + output logic almfull, + output logic full, + output logic overflow_error, + // Status inputs to hazard detector logic (dummy ports, never used --- since everything is in-order) + output ase_haz_pkt hazpkt_in, + output ase_haz_pkt hazpkt_out + ); + + // Logger function +`ifdef ASE_DEBUG + // Internal logger fd + int log_fd; + initial begin + log_fd = $fopen( DEBUG_LOGNAME, "w"); + $fwrite(log_fd, "Logger for %m transactions\n"); + end +`endif + + + // Visible depth + localparam VISIBLE_DEPTH = 2**VISIBLE_DEPTH_BASE2; + + // Internal signals + logic [LATBUF_TID_WIDTH-1:0] tid_in; + logic [LATBUF_TID_WIDTH-1:0] tid_out; + + logic outfifo_almfull; + + // FIFO widths + localparam INFIFO_WIDTH = LATBUF_TID_WIDTH + CCIP_TX_HDR_WIDTH + CCIP_DATA_WIDTH; + localparam OUTFIFO_WIDTH = LATBUF_TID_WIDTH + CCIP_RX_HDR_WIDTH + CCIP_TX_HDR_WIDTH + CCIP_DATA_WIDTH; + + // Internal channel management + logic [INFIFO_WIDTH-1:0] infifo[$:VISIBLE_DEPTH-1]; + logic [OUTFIFO_WIDTH-1:0] outfifo[$:VISIBLE_DEPTH-1]; + + // FIFO counts + int infifo_cnt; + int outfifo_cnt; + + always @(posedge clk) begin : cnt_proc + infifo_cnt <= infifo.size(); + outfifo_cnt <= outfifo.size(); + end + + /* + * Tracking ID generator + */ + always @(posedge clk) begin : tid_proc + if (rst) + tid_in <= {LATBUF_TID_WIDTH{1'b0}}; + else if (write_en) + tid_in <= tid_in + 1; + end + + // Full signal + always @(posedge clk) begin : full_proc + if (rst) begin + full <= 0; + end + else if (infifo_cnt == VISIBLE_DEPTH-1) begin + full <= 1; + end + else begin + full <= 0; + end + end + + // Overflow check + always @(posedge clk) begin + if (rst) begin + overflow_error <= 0; + end + else if ((infifo_cnt == VISIBLE_DEPTH-1) && write_en) begin + overflow_error <= 1; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | ** Overflow Error detected **\n", $time); +`endif + end + end + + + /* + * Infifo, request staging + */ + always @(posedge clk) begin : infifo_push + if (write_en) begin +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | ENTER : %s assigned tid=%x\n", $time, return_txhdr(hdr_in), tid_in); + if (hdr_in.reqtype == ASE_WRFENCE) begin + $fwrite (log_fd, "%d | WrFence inserted in channel\n", $time); + end +`endif + infifo.push_back({ tid_in, data_in, logic_cast_TxHdr_t'(hdr_in) }); + end + end + + + // Almfull signal + always @(posedge clk) begin : almfull_proc + if (rst) begin + almfull <= 1; + end + else if (infifo_cnt > VISIBLE_FULL_THRESH ) begin + almfull <= 1; + end + else begin + almfull <= 0; + end + end + + // Almfull tracking + logic almfull_q; + always @(posedge clk) begin + almfull_q <= almfull; + end + + // If Full toggles, log the event +`ifdef ASE_DEBUG + always @(posedge clk) begin + if (almfull_q != almfull) begin + $fwrite(log_fd, "%d | Module full toggled from %b to %b\n", $time, almfull_q, almfull); + end + end +`endif + + + /* + * Processing logic + */ + logic [CCIP_DATA_WIDTH-1:0] infifo_data_out; + logic [LATBUF_TID_WIDTH-1:0] infifo_tid_out; + logic [CCIP_TX_HDR_WIDTH-1:0] infifo_hdr_out_vec; + TxHdr_t infifo_hdr_out; + logic infifo_vld_out; + + ccip_vc_t vc_arb; + logic [1:0] curr_vc_index = 2'b0; + ccip_vc_t [0:3] sel_vc_array = {VC_VL0, VC_VH0, VC_VL0, VC_VH1}; + + logic outfifo_empty; + logic [CCIP_TX_HDR_WIDTH-1:0] txhdr_out_vec; + logic [CCIP_RX_HDR_WIDTH-1:0] rxhdr_out_vec; + ccip_vc_t last_vc; + ccip_len_t base_len; + ccip_vc_t base_vc; + + // Function: infifo_to_outfifo + // function automatic void infifo_to_outfifo(int init); + task automatic infifo_to_outfifo(int init); + // int mcl_txn_iter; + RxHdr_t infifo_rxhdr; + logic [41:0] base_addr; + begin + if (init) begin + vc_arb = ccip_vc_t'(VC_VL0); + curr_vc_index = 2'b00; + end + else if ((infifo.size() != 0) && ~outfifo_almfull) begin + // ----- Read from infifo ---- // + {infifo_tid_out, infifo_data_out, infifo_hdr_out_vec} = infifo.pop_front(); + infifo_hdr_out = TxHdr_t'(infifo_hdr_out_vec); + // ----- If VA is set, select a channel ----- // + if ((infifo_hdr_out.vc == VC_VA) && (isReadRequest(infifo_hdr_out) || (isWriteRequest(infifo_hdr_out) && infifo_hdr_out.sop))) begin + infifo_hdr_out.vc = sel_vc_array[curr_vc_index]; + curr_vc_index = curr_vc_index + 1; + last_vc = infifo_hdr_out.vc; + end + else if (isWriteRequest(infifo_hdr_out) && ~infifo_hdr_out.sop) begin + infifo_hdr_out.vc = last_vc; + end + // ---- Address capture ---- // + base_addr = infifo_hdr_out.addr; + // ---- MCL packet management --- // + if (isWriteRequest(infifo_hdr_out)) begin + if (infifo_hdr_out.sop) begin + base_vc = infifo_hdr_out.vc; + base_len = infifo_hdr_out.len; + end + else begin + infifo_hdr_out.vc = base_vc; + infifo_hdr_out.len = base_len; + end + end + /////////////// Prepare RxHdr //////////////////// + infifo_rxhdr = RxHdr_t'(0); + infifo_rxhdr.vc_used = infifo_hdr_out.vc; + infifo_rxhdr.hitmiss = 0; + infifo_rxhdr.mdata = infifo_hdr_out.mdata; + if (isReadRequest(infifo_hdr_out)) begin + infifo_rxhdr.resptype = ASE_RD_RSP; + end + else if (isWriteRequest(infifo_hdr_out)) begin + infifo_rxhdr.resptype = ASE_WR_RSP; + end + else if (isWrFenceRequest(infifo_hdr_out)) begin + infifo_rxhdr.resptype = ASE_WRFENCE_RSP; + end +`ifdef ASE_ENABLE_INTR_FEATURE + else if (isIntrRequest(infifo_hdr_out)) begin + infifo_rxhdr.resptype = ASE_INTR_RSP; + end +`endif + if (isWriteRequest(infifo_hdr_out)) begin + if (isVHxRequest(infifo_hdr_out)) begin + infifo_rxhdr.format = 1; + infifo_rxhdr.clnum = base_len; + // mcl_txn_iter = mcl_txn_iter + 1; + end + else begin + infifo_rxhdr.format = 0; + infifo_rxhdr.clnum = infifo_hdr_out.len; + end + end +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | tid=%x assigned to channel %s, %s %s\n", $time, infifo_tid_out, ase_channel_type(infifo_hdr_out.vc), return_txhdr(infifo_hdr_out), return_rxhdr(infifo_rxhdr)); +`endif + ///////////// Packing & CLNUM control /////////// + if (isReadRequest(infifo_hdr_out)) begin + infifo_rxhdr.format = 0; + for (int cl_i = 0; cl_i <= int'(infifo_hdr_out.len); cl_i = cl_i + 1) begin + infifo_rxhdr.clnum = ccip_len_t'(cl_i); + infifo_hdr_out.addr = base_addr + cl_i[1:0]; + outfifo.push_back({infifo_tid_out, infifo_data_out, logic_cast_RxHdr_t'(infifo_rxhdr), logic_cast_TxHdr_t'(infifo_hdr_out)} ); + end + end + else begin + outfifo.push_back({infifo_tid_out, infifo_data_out, logic_cast_RxHdr_t'(infifo_rxhdr), logic_cast_TxHdr_t'(infifo_hdr_out)}); + end + + end // else: !if(init) + end + // endfunction // infifo_to_outfifo + endtask // infifo_to_outfifo + + // Glue process + always @(posedge clk) begin + if (rst) begin + infifo_to_outfifo(1); + end + else if (infifo_cnt != 0) begin + infifo_to_outfifo(0); + end + end + + + /* + * Output Staging + */ + // Outfifo Full/Empty + assign outfifo_almfull = (outfifo_cnt > VISIBLE_FULL_THRESH) ? 1 : 0; + + always @(*) begin + if (outfifo_cnt == 0) + outfifo_empty <= 1; + else + outfifo_empty <= 0; + end + + assign empty = outfifo_empty; + + // HDR out + assign txhdr_out = TxHdr_t'(txhdr_out_vec); + assign rxhdr_out = RxHdr_t'(rxhdr_out_vec); + + // Output pop process + always @(posedge clk) begin : read_out_proc + if (rst) begin + valid_out <= 0; + end + else if (read_en && (outfifo.size() != 0)) begin + { tid_out, data_out, rxhdr_out_vec, txhdr_out_vec } <= outfifo.pop_front(); + valid_out <= 1; + end + else begin + valid_out <= 0; + end + end + + // Log output pop +`ifdef ASE_DEBUG + always @(posedge clk) begin + if (valid_out) begin + $fwrite(log_fd, "%d | EXIT => tid=%x with %s %s \n", $time, tid_out, return_txhdr(txhdr_out), return_rxhdr(rxhdr_out) ); + end + end +`endif + + + /* + * Transaction IN-OUT checker + * Sniffs dropped transactions, unexpected mdata, vc or mcl responses + */ +`ifdef ASE_DEBUG + TxHdr_t check_hdr_array[*]; + int check_vld_array[*]; + + // Check and delete from array + function automatic void check_delete_from_array(longint key); + begin + if (check_hdr_array.exists(key)) begin + check_hdr_array.delete(key); + check_vld_array.delete(key); + end + else begin + `BEGIN_RED_FONTCOLOR; + $display(" ** HASH ERROR ** %x key was not found ", key); + $fwrite(log_fd, " ** HASH ERROR ** %x key was not found ", key); + `END_RED_FONTCOLOR; + end + end + endfunction + + // Update & self-ccheck process + always @(posedge clk) begin + // Push to channel + if (write_en) begin + if (WRITE_CHANNEL == 0) begin + for (int ii = 0; ii <= hdr_in.len ; ii = ii + 1) begin + check_hdr_array [tid_in] <= hdr_in; + check_vld_array [tid_in] <= hdr_in.len + 1; + end + end + else if (WRITE_CHANNEL == 1) begin + check_hdr_array [tid_in] <= hdr_in; + check_vld_array [tid_in] <= 1; + end + end + // Pop from channel + if (valid_out) begin + check_vld_array[tid_out] = check_vld_array[tid_out] - 1; + if (check_vld_array[tid_out] == 0) begin + check_delete_from_array( tid_out ); + end + // *** VC checks here *** + if ((check_hdr_array[tid_out].vc != VC_VA) && (rxhdr_out.vc_used != check_hdr_array[tid_out].vc)) begin + `BEGIN_RED_FONTCOLOR; + $display("** ERROR **: VC was assigned incorrectly"); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + // ** MDATA checks here *** + if (rxhdr_out.mdata != check_hdr_array[tid_out].mdata) begin + `BEGIN_RED_FONTCOLOR; + $display("** ERROR **: MDATA was assigned incorrectly"); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + end + end +`endif + + +endmodule // inorder_wrf_channel diff --git a/ase/rtl/latency_pipe.sv b/ase/rtl/latency_pipe.sv new file mode 100644 index 000000000000..1927e0bc6473 --- /dev/null +++ b/ase/rtl/latency_pipe.sv @@ -0,0 +1,110 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: Generic register block & Latency pipe + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + +module register + #( + parameter REG_WIDTH = 1 + ) + ( + input logic clk, + input logic rst, + input logic [REG_WIDTH-1:0] d, + output logic [REG_WIDTH-1:0] q + ); + + + // DFF behaviour + always @( posedge clk or posedge rst ) begin + if (rst) + q <= 0; + else + q <= d; + end + +endmodule + + +/* + * latency_pipe : A generic N-stage, W-width pipeline that delays + * input by a known number of clocks + */ +module latency_pipe + #( + parameter NUM_DELAY = 5, + parameter PIPE_WIDTH = 1 + ) + ( + input logic clk, + input logic rst, + input logic [PIPE_WIDTH-1:0] pipe_in, + output logic [PIPE_WIDTH-1:0] pipe_out + ); + + logic [PIPE_WIDTH-1:0] pipe_in_tmp [0:NUM_DELAY-1]; + logic [PIPE_WIDTH-1:0] pipe_out_tmp [0:NUM_DELAY-1]; + + + // Register stages (instantiated here, not connected) + genvar ii; + generate + for(ii = 0; ii < NUM_DELAY; ii = ii + 1) begin : reg_array_gen + register + #( + .REG_WIDTH (PIPE_WIDTH) + ) + reg_i + ( + .clk (clk), + .rst (rst), + .d (pipe_in_tmp[ii]), + .q (pipe_out_tmp[ii]) + ); + end + endgenerate + + // Pipeline stages connected here + genvar jj; + generate + for(jj = 1; jj < NUM_DELAY; jj = jj + 1) begin : connect_gen + assign pipe_in_tmp[jj] = pipe_out_tmp[jj - 1]; + end + endgenerate + + assign pipe_in_tmp[0] = pipe_in; + assign pipe_out = pipe_out_tmp[NUM_DELAY-1]; + +endmodule diff --git a/ase/rtl/outoforder_wrf_channel.sv b/ase/rtl/outoforder_wrf_channel.sv new file mode 100644 index 000000000000..f9412031a1a0 --- /dev/null +++ b/ase/rtl/outoforder_wrf_channel.sv @@ -0,0 +1,1845 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: Latency modeling scoreboard system + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * ********************************************************************************* + * SR-5.0.0-alpha onwards implementation + * --------------------------------------------------------------------------------- + * + * TBD cachesim link + * || + * /---------------------------------\ + * |-->vl0-->| | | | + * | | assign | wait | multi-CL | + * -->infifo-->|-->vh0-->| delayed | stattions | breakout |-->outfifo--> + * | | action | | | + * |-->vh1-->| | | | + * \---------------------------------/ + * + * - Input FIFO stages requests and asserts AlmostFull signal | + * -- Feeds 2 high-lat and 1 low-lat lanes | + * - If VA | Request + * -- Round robin between VH and VL lanes | Order + * -- Response channels (VC_USED) is assigned here | Maintain + * - Assignment of waits is done and pushed to wait stations | + * - When ready to pop from wait stations |--------- + * -- If multi-CL is observed, request is broken out to multiple-single | + * -- If single line is observed, it is passed through | + * -- Unit generates RxHdr output to send response back to AFU | Request + * - If fence is observed with: | order + * -- VA : All channels fenced | changed + * -- VL0/VHx : Requested channel is fenced | + * + * ********************************************************************************* + * SR 4.1.x - SR 5.0.0-prealpha implementation + * --------------------------------------------------------------------------------- + * - Transactions are stored when request comes from AFU + * - Random number generator chooses a delay component between MIN_DELAY & MAX_DELAY + * - When a request's "time has come", it gets called by cci_emulator + * - This is a normal DPI-C call to C functions + * - When a response is received, the response is queued in normal format + * + * THIS COMPONENT + * - simply re-orders requests and sends them out + * - May not necessarily be synthesizable + * + * OPERATION: + * - {meta_in, data_in} is validated with write_en signal + * - An empty slot is found, a random delay is computed based on pre-known parameters + * - The state machine is kicked off. + * + * GENERICS: + * - NUM_WAIT_STATIONS : Number of transactions in latency buffer + * - FIFO_FULL_THRESH : FIFO full threshold + * - FIFO_DEPTH_BASE2 : FIFO depth radix + * + */ + +import ase_pkg::*; + +`include "platform.vh" + +module outoforder_wrf_channel + #( + parameter string DEBUG_LOGNAME = "channel.log", + parameter int NUM_WAIT_STATIONS = 8, + parameter int NUM_STATIONS_FULL_THRESH = 3, + parameter int COUNT_WIDTH = 8, + parameter int VISIBLE_DEPTH_BASE2 = 8, + parameter int VISIBLE_FULL_THRESH = 220, + parameter int LATBUF_MAX_TXN = 4, + parameter int WRITE_CHANNEL = 0 + ) + ( + input logic clk, + input logic rst, + input logic finish_trigger, + // Transaction in + input TxHdr_t hdr_in, + input logic [CCIP_DATA_WIDTH-1:0] data_in, + input logic write_en, + // Transaction out + output TxHdr_t txhdr_out, + output RxHdr_t rxhdr_out, + output logic [CCIP_DATA_WIDTH-1:0] data_out, + output logic valid_out, + input logic read_en, + // Status signals + output logic empty, + output logic almfull, + output logic full, + output logic overflow_error, + // Status inputs to hazard detector logic + output ase_haz_pkt hazpkt_in, + output ase_haz_pkt hazpkt_out + ); + + + // Read/Write macro + generate + if (WRITE_CHANNEL == 0) begin +`define WRITE_LATBUF_CHANNEL + end + else if (WRITE_CHANNEL == 1) begin +`define READ_LATBUF_CHANNEL + end + endgenerate + + + /* + * FUNCTION: get_random_from_range + */ + function int get_random_from_range(int low, + int high); + int rand_out; + begin + // rand_out = abs_val($random() % (high + 1 - low) + low); + rand_out = $urandom_range(low, high); + return rand_out; + end + endfunction + + + /* + * Optional tracking log - enabled by ASE_DEBUG + */ +`ifdef ASE_PROFILE + // Distribution histogram counters + int histogram_stats[`ASE_MAX_LATENCY]; + initial begin + // Initialize histogram counters + for(int ii=0; ii<`ASE_MAX_LATENCY; ii = ii + 1) begin + histogram_stats[ii] = 0; + end + end +`endif + +`ifdef ASE_DEBUG + // Internal logger fd + int log_fd; + initial begin + log_fd = $fopen( DEBUG_LOGNAME, "w"); + $fwrite(log_fd, "Logger for %m transactions\n"); + end +`endif + + // Set random seed + // initial begin + // // $srandom(cfg.ase_seed); + // // $urandom(cfg.ase_seed); + // end + + localparam FIFO_WIDTH = LATBUF_TID_WIDTH + CCIP_TX_HDR_WIDTH + CCIP_DATA_WIDTH; + localparam OUTFIFO_WIDTH = LATBUF_TID_WIDTH + CCIP_RX_HDR_WIDTH + CCIP_TX_HDR_WIDTH + CCIP_DATA_WIDTH; + + localparam LATBUF_SLOT_INVALID = 255; + + // Visible depth + localparam VISIBLE_DEPTH = 2**VISIBLE_DEPTH_BASE2; + + // Internal FIFOs are invisible FIFOs inside channel + localparam INTERNAL_FIFO_DEPTH_RADIX = 6; + localparam INTERNAL_FIFO_DEPTH = 2**INTERNAL_FIFO_DEPTH_RADIX; + localparam INTERNAL_FIFO_ALMFULL_THRESH = INTERNAL_FIFO_DEPTH - 10; + + // Internal signals + logic [LATBUF_TID_WIDTH-1:0] tid_in; + logic [LATBUF_TID_WIDTH-1:0] tid_out; + + // Infifo + logic [FIFO_WIDTH-1:0] infifo[$:VISIBLE_DEPTH-1]; + + // Lanes + logic [FIFO_WIDTH-1:0] vl0_array[$:INTERNAL_FIFO_DEPTH-1]; + logic [FIFO_WIDTH-1:0] vh0_array[$:INTERNAL_FIFO_DEPTH-1]; + logic [FIFO_WIDTH-1:0] vh1_array[$:INTERNAL_FIFO_DEPTH-1]; + + + /* + * Wrfence response mechanism + * -------------------------- + * + * - When Wrfence is observed on infifo, it is applied to + * required channel + * - A response packet is formed and staged + * THIS ENSURES WRFENCE RESPONSES ARE RETURNED IN ORDER RECEIVED + * - A compare-wait engine waits pops wrfence_rsp_array, and + * waits until wrfence_flag is seen on records_t:interface + * - Then response is placed on outfifo + * + */ +`ifdef WRITE_LATBUF_CHANNEL + // Wrfence response staging + logic [(LATBUF_TID_WIDTH+CCIP_RX_HDR_WIDTH+CCIP_TX_HDR_WIDTH-1):0] wrfence_rsp_array[$]; + + // Wrfence assert/deassert/status/compare + logic wrfence_rspvalid; + logic [LATBUF_TID_WIDTH-1:0] wrfence_rsptid; + RxHdr_t wrfence_rsphdr; + TxHdr_t wrfence_reqhdr; + logic vl0_wrfence_deassert; + logic vh0_wrfence_deassert; + logic vh1_wrfence_deassert; +`endif + + // Outfifo + logic [OUTFIFO_WIDTH-1:0] outfifo[$:VISIBLE_DEPTH-1]; + + // FIFO counts + int infifo_cnt; + int vl0_array_cnt; + int vh0_array_cnt; + int vh1_array_cnt; + int outfifo_cnt; + int wrfence_rsp_cnt; + + logic vl0_array_full; + logic vh0_array_full; + logic vh1_array_full; + + logic vl0_array_empty; + logic vh0_array_empty; + logic vh1_array_empty; + + logic outfifo_empty; + logic outfifo_almfull; + + logic [2:0] vc_push; + + logic some_lane_full; + + always @(*) begin : lane_fullcheck_comb + some_lane_full <= vl0_array_full | vh0_array_full | vh1_array_full; + end + + /* + * Tracking ID generator + */ + always @(posedge clk) begin : tid_proc + if (rst) + tid_in <= {LATBUF_TID_WIDTH{1'b0}}; + else if (write_en) + tid_in <= tid_in + 1; + end + + // Counts/fill level + always @(posedge clk) begin : cnt_proc + infifo_cnt <= infifo.size(); + vl0_array_cnt <= vl0_array.size(); + vh0_array_cnt <= vh0_array.size(); + vh1_array_cnt <= vh1_array.size(); + outfifo_cnt <= outfifo.size(); + wrfence_rsp_cnt <= wrfence_rsp_array.size(); + end + + assign vl0_array_full = (vl0_array_cnt > INTERNAL_FIFO_ALMFULL_THRESH) ? 1 : 0; + assign vh0_array_full = (vh0_array_cnt > INTERNAL_FIFO_ALMFULL_THRESH) ? 1 : 0; + assign vh1_array_full = (vh1_array_cnt > INTERNAL_FIFO_ALMFULL_THRESH) ? 1 : 0; + + assign vl0_array_empty = (vl0_array_cnt == 0) ? 1 : 0; + assign vh0_array_empty = (vh0_array_cnt == 0) ? 1 : 0; + assign vh1_array_empty = (vh1_array_cnt == 0) ? 1 : 0; + + // Almfull signal + always @(posedge clk) begin : almfull_proc + if (rst) begin + almfull <= 1; + end + else if (infifo_cnt > VISIBLE_FULL_THRESH ) begin + almfull <= 1; + end + else begin + almfull <= 0; + end + end + + // Almfull tracking + logic almfull_q; + always @(posedge clk) begin + almfull_q <= almfull; + end + + // If Full toggles, log the event +`ifdef ASE_DEBUG + always @(posedge clk) begin + if (almfull_q != almfull) begin + $fwrite(log_fd, "%d | Module full toggled from %b to %b\n", $time, almfull_q, almfull); + end + end +`endif + + // Full signal + always @(posedge clk) begin : full_proc + if (rst) begin + full <= 0; + end + else if (infifo_cnt == VISIBLE_DEPTH-1) begin + full <= 1; + end + else begin + full <= 0; + end + end + + // Overflow check + always @(posedge clk) begin + if (rst) begin + overflow_error <= 0; + end + else if ((infifo_cnt == VISIBLE_DEPTH-1) && write_en) begin + overflow_error <= 1; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | ** Overflow Error detected **\n", $time); +`endif + end + end + + /* + * Scoreboard logic + */ + // Enumerate states + typedef enum {LatSc_Disabled, + LatSc_Countdown, + LatSc_DoneReady, + LatSc_RecordPopped} latsc_fsmState; + + // Transaction storage + typedef struct + { + TxHdr_t hdr [0:LATBUF_MAX_TXN-1]; // in + logic [CCIP_DATA_WIDTH-1:0] data [0:LATBUF_MAX_TXN-1]; // in + logic [LATBUF_TID_WIDTH-1:0] tid [0:LATBUF_MAX_TXN-1]; // in + logic [LATBUF_TIMER_WIDTH-1:0] ctr_out; // out + int num_items; // in + // logic record_valid; // out + logic record_ready; // out + // logic record_push; // in + logic record_pop; // in + latsc_fsmState state; // out + } transact_t; + + // Array of stored transactions + transact_t records[NUM_WAIT_STATIONS] ; + + logic [0:NUM_WAIT_STATIONS-1] record_vl0_flag_arr; + logic [0:NUM_WAIT_STATIONS-1] record_vh0_flag_arr; + logic [0:NUM_WAIT_STATIONS-1] record_vh1_flag_arr; + + // logic [0:NUM_WAIT_STATIONS-1] record_pop_arr; + // logic [0:NUM_WAIT_STATIONS-1] record_push_arr; + + /* + * Busy state management + */ + logic [0:NUM_WAIT_STATIONS-1] latbuf_busy_state; + + // Set Record as busy + function void set_latbuf_busy(int slot); + begin + latbuf_busy_state[slot] = 1; + end + endfunction + + // Unset record as available + function void unset_latbuf_available(int slot); + begin + latbuf_busy_state[slot] = 0; + end + endfunction + + + /* + * Infifo, request staging + */ + always @(posedge clk) begin : infifo_push + if (write_en) begin +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | ENTER : %s assigned tid=%x\n", $time, return_txhdr(hdr_in), tid_in); + if (hdr_in.reqtype == ASE_WRFENCE) begin + $fwrite (log_fd, "%d | WrFence inserted in channel\n", $time); + end +`endif + infifo.push_back({ tid_in, data_in, logic_cast_TxHdr_t'(hdr_in) }); + end + end + + + // Pop infifo, arbitrate between lanes + logic [CCIP_DATA_WIDTH-1:0] infifo_data_out; + logic [LATBUF_TID_WIDTH-1:0] infifo_tid_out; + logic [CCIP_TX_HDR_WIDTH-1:0] infifo_hdr_out_vec; + TxHdr_t infifo_hdr_out; + logic infifo_vld_out; + + ccip_vc_t vc_rd_arb; + ccip_vc_t vc_wr_arb; + + ccip_vc_t [0:3] sel_vc_array = {VC_VL0, VC_VH0, VC_VL0, VC_VH1}; + logic [1:0] curr_vc_index = 2'b0; + + + /* + * Read MCL select VC + */ +`ifdef READ_LATBUF_CHANNEL + function automatic void select_vc_read(int init, ref TxHdr_t hdr); + begin + if (init) begin + vc_rd_arb = ccip_vc_t'(VC_VL0); + end + else begin + if (hdr.vc == VC_VA) begin + case ({vl0_array_full, vh0_array_full, vh1_array_full}) + 3'b000: + begin + hdr.vc = sel_vc_array[curr_vc_index]; + curr_vc_index = curr_vc_index + 1; + end + 3'b001: hdr.vc = VC_VL0; + 3'b010: hdr.vc = VC_VH1; + 3'b011: hdr.vc = VC_VL0; + 3'b100: hdr.vc = VC_VH0; + 3'b101: hdr.vc = VC_VH0; + 3'b110: hdr.vc = VC_VH1; + endcase + vc_rd_arb = ccip_vc_t'(hdr.vc); + end + end + end + endfunction +`endif + + /* + * Write MCL select VC + */ +`ifdef WRITE_LATBUF_CHANNEL + function automatic void select_vc_write(int init, ref TxHdr_t hdr); + begin + if (init) begin + vc_wr_arb = ccip_vc_t'(VC_VL0); + end + else if (hdr.sop && (hdr.vc == VC_VA) && isWriteRequest(hdr)) begin + case ({vl0_array_full, vh0_array_full, vh1_array_full}) + 3'b000: + begin + hdr.vc = sel_vc_array[curr_vc_index]; + curr_vc_index = curr_vc_index + 1; + end + 3'b001: hdr.vc = VC_VL0; + 3'b010: hdr.vc = VC_VH1; + 3'b011: hdr.vc = VC_VL0; + 3'b100: hdr.vc = VC_VH0; + 3'b101: hdr.vc = VC_VH0; + 3'b110: hdr.vc = VC_VH1; + endcase + vc_wr_arb = ccip_vc_t'(hdr.vc); + end // if (hdr.sop && (hdr.vc == VC_VA)) + else if (hdr.sop && (hdr.vc != VC_VA)) begin + vc_wr_arb = ccip_vc_t'(hdr.vc); + end + else if (~hdr.sop) begin + hdr.vc = vc_wr_arb; + end + end + endfunction +`endif + + // Write fence response generator +`ifdef WRITE_LATBUF_CHANNEL + function automatic logic [CCIP_RX_HDR_WIDTH-1:0] prepare_wrfence_response(TxHdr_t wrfence); + RxHdr_t wrfence_rsp; + logic [CCIP_RX_HDR_WIDTH-1:0] wrfence_rsp_vec; + begin + // Precast + wrfence_rsp = RxHdr_t'(0); + // response + wrfence_rsp.vc_used = wrfence.vc; + wrfence_rsp.resptype = ASE_WRFENCE_RSP; + wrfence_rsp.mdata = wrfence.mdata; + // Cast back and return + wrfence_rsp_vec = logic_cast_RxHdr_t'(wrfence_rsp); + return wrfence_rsp_vec; + end + endfunction +`endif // `ifdef WRITE_LATBUF_CHANNEL + + + /* + * INFIFO->VC_sel + * ----------------------------------------- + * - Read infifo contents + * - If WrFence (either channel) + * = Block required channel(s) + * = Stage WrFence response in wrfence_rsp_array + * - Else !wrfence + * = Select VC + * = Stage into response array + */ + // ================================================================== // + // Read CHANNEL infifo_to_vc_put + // ================================================================== // +`ifdef READ_LATBUF_CHANNEL + task automatic READ_infifo_to_vc_push (); + logic [PHYSCLADDR_WIDTH-1:0] c0tx_vl0_addr_base; + TxHdr_t vl0_hdr; + begin + {infifo_tid_out, infifo_data_out, infifo_hdr_out_vec} = infifo.pop_front(); + infifo_hdr_out = TxHdr_t'(infifo_hdr_out_vec); + select_vc_read (0, infifo_hdr_out); + case (infifo_hdr_out.vc) + VC_VL0: + begin + vc_push = 3'b100; + if (WRITE_CHANNEL == 0) begin + for(int ii = 0; ii <= infifo_hdr_out.len; ii = ii + 1) begin + vl0_hdr = infifo_hdr_out; + if (ii == 0) begin + c0tx_vl0_addr_base = infifo_hdr_out.addr; + end + vl0_hdr.addr = infifo_hdr_out.addr + ii; + vl0_hdr.len = ccip_len_t'(ii); + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(vl0_hdr)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VL0) : tid=%x %s sent to VL0\n", $time, infifo_tid_out, return_txhdr(vl0_hdr) ); + `endif + end // for (int ii = 0; ii <= infifo_hdr_out.len; ii = ii + 1) + end // if (WRITE_CHANNEL == 0) + else begin + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VL0) : tid=%x %s sent to VL0\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out) ); + `endif + end + end + + VC_VH0: + begin + vc_push = 3'b010; + vh0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VH0) : tid=%x %s sent to VH0\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out)); + `endif + end + + VC_VH1: + begin + vc_push = 3'b001; + vh1_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VH1) : tid=%x %s sent to VH1\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out)); + `endif + end + endcase + // ----------------------------------------------------------------------- // + @(posedge clk); + // vc_push = 3'b000; + end + endtask +`endif + + // ================================================================== // + // Write CHANNEL infifo_to_vc_put + // ================================================================== // +`ifdef WRITE_LATBUF_CHANNEL + task automatic WRITE_infifo_to_vc_push (); + logic [PHYSCLADDR_WIDTH-1:0] c0tx_vl0_addr_base; + TxHdr_t vl0_hdr; + begin + {infifo_tid_out, infifo_data_out, infifo_hdr_out_vec} = infifo.pop_front(); + infifo_hdr_out = TxHdr_t'(infifo_hdr_out_vec); + // ----------------------------------------------------------------------- // + // If Write fence is observed + // ----------------------------------------------------------------------- // + if (infifo_hdr_out.reqtype == ASE_WRFENCE) begin + vc_push = 3'b111; + case (infifo_hdr_out.vc) + // If VA, fence all channels, and stage one coalesced response + VC_VA: + begin + // Fence activatd + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + vh0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + vh1_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + // Wrfence response + wrfence_rsp_array.push_back( {infifo_tid_out, prepare_wrfence_response(infifo_hdr_out), logic_cast_TxHdr_t'(infifo_hdr_out) } ); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc: WrFence of tid=%x inserted into VA\n", $time, infifo_tid_out); + `endif + end + + // If single channel fence, stage requisite response + VC_VL0: + begin + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + wrfence_rsp_array.push_back( {infifo_tid_out, prepare_wrfence_response(infifo_hdr_out), logic_cast_TxHdr_t'(infifo_hdr_out) } ); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc: WrFence of tid=%x inserted into VL0\n", $time, infifo_tid_out); + `endif + end + + VC_VH0: + begin + vh0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + wrfence_rsp_array.push_back( {infifo_tid_out, prepare_wrfence_response(infifo_hdr_out), logic_cast_TxHdr_t'(infifo_hdr_out) } ); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc: WrFence of tid=%x inserted into VH0\n", $time, infifo_tid_out); + `endif + end + + VC_VH1: + begin + vh1_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + wrfence_rsp_array.push_back( {infifo_tid_out, prepare_wrfence_response(infifo_hdr_out), logic_cast_TxHdr_t'(infifo_hdr_out) } ); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc: WrFence of tid=%x inserted into VH1\n", $time, infifo_tid_out); + `endif + end + + endcase + end // if (infifo_hdr_out.reqtype == ASE_WRFENCE) + // ----------------------------------------------------------------------- // + // Any non-WRFence transaction + // ----------------------------------------------------------------------- // + else begin + select_vc_write (0, infifo_hdr_out); + // No fence + case (infifo_hdr_out.vc) + VC_VL0: + begin + vc_push = 3'b100; + if (WRITE_CHANNEL == 0) begin + for(int ii = 0; ii <= infifo_hdr_out.len; ii = ii + 1) begin + vl0_hdr = infifo_hdr_out; + if (ii == 0) begin + c0tx_vl0_addr_base = infifo_hdr_out.addr; + end + vl0_hdr.addr = infifo_hdr_out.addr + ii; + vl0_hdr.len = ccip_len_t'(ii); + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(vl0_hdr)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VL0) : tid=%x %s sent to VL0\n", $time, infifo_tid_out, return_txhdr(vl0_hdr) ); + `endif + end // for (int ii = 0; ii <= infifo_hdr_out.len; ii = ii + 1) + end // if (WRITE_CHANNEL == 0) + else begin + vl0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VL0) : tid=%x %s sent to VL0\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out) ); + `endif + end + end + + VC_VH0: + begin + vc_push = 3'b010; + vh0_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VH0) : tid=%x %s sent to VH0\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out)); + `endif + end + + VC_VH1: + begin + vc_push = 3'b001; + vh1_array.push_back({infifo_tid_out, infifo_data_out, logic_cast_TxHdr_t'(infifo_hdr_out)}); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | infifo_to_vc(VH1) : tid=%x %s sent to VH1\n", $time, infifo_tid_out, return_txhdr(infifo_hdr_out)); + `endif + end + endcase + end // else: !if(infifo_hdr_out.reqtype == ASE_WRFENCE) + // ----------------------------------------------------------------------- // + @(posedge clk); + // vc_push = 3'b000; + end + endtask +`endif + + + /* + * Virtual channel select and push + */ + generate + // ================================================================== // + // Read CHANNEL infifo_to_vc_put + // ================================================================== // + if (WRITE_CHANNEL == 0) begin + always @(posedge clk) begin : vc_selector_proc + if (rst) begin + vc_push <= 3'b000; + select_vc_read (1, infifo_hdr_out); + infifo_tid_out <= {LATBUF_TID_WIDTH{1'b0}}; + infifo_data_out <= {CCIP_DATA_WIDTH{1'b0}}; + infifo_hdr_out <= TxHdr_t'({CCIP_TX_HDR_WIDTH{1'b0}}); + infifo_vld_out <= 0; + end + else if (~some_lane_full && (infifo.size() != 0)) begin + READ_infifo_to_vc_push(); + infifo_vld_out <= 1; + end + else begin + vc_push <= 3'b000; + infifo_tid_out <= {LATBUF_TID_WIDTH{1'b0}}; + infifo_data_out <= {CCIP_DATA_WIDTH{1'b0}}; + infifo_hdr_out <= TxHdr_t'({CCIP_TX_HDR_WIDTH{1'b0}}); + infifo_vld_out <= 0; + end + end + end + // ================================================================== // + // Write CHANNEL infifo_to_vc_put + // ================================================================== // + else if (WRITE_CHANNEL == 1) begin + always @(posedge clk) begin : vc_selector_proc + if (rst) begin + vc_push <= 3'b000; + select_vc_write (1, infifo_hdr_out); + infifo_tid_out <= {LATBUF_TID_WIDTH{1'b0}}; + infifo_data_out <= {CCIP_DATA_WIDTH{1'b0}}; + infifo_hdr_out <= TxHdr_t'({CCIP_TX_HDR_WIDTH{1'b0}}); + infifo_vld_out <= 0; + end + else if (~some_lane_full && (infifo.size() != 0)) begin + WRITE_infifo_to_vc_push(); + infifo_vld_out <= 1; + end + else begin + vc_push <= 3'b000; + infifo_tid_out <= {LATBUF_TID_WIDTH{1'b0}}; + infifo_data_out <= {CCIP_DATA_WIDTH{1'b0}}; + infifo_hdr_out <= TxHdr_t'({CCIP_TX_HDR_WIDTH{1'b0}}); + infifo_vld_out <= 0; + end + end + end + endgenerate + + + // Lane pop and latency scoreboard push + logic vl0_wrfence_flag; + logic vh0_wrfence_flag; + logic vh1_wrfence_flag; + + logic glbl_wrfence_pop_status; + + logic [LATBUF_TID_WIDTH-1:0] vl0_wrfence_tid; + logic [LATBUF_TID_WIDTH-1:0] vh0_wrfence_tid; + logic [LATBUF_TID_WIDTH-1:0] vh1_wrfence_tid; + + int latbuf_push_ptr; + int latbuf_pop_ptr; + + int vl0_records_cnt ; + int vh0_records_cnt ; + int vh1_records_cnt; + + int latbuf_cnt; + logic latbuf_full; + logic latbuf_almfull; + logic latbuf_empty; + + // Count used latbuf + assign vl0_records_cnt = $countones(record_vl0_flag_arr); + assign vh0_records_cnt = $countones(record_vh0_flag_arr); + assign vh1_records_cnt = $countones(record_vh1_flag_arr); + + // Total count + always @(posedge clk) begin : latbuf_cnt_proc + latbuf_cnt <= vl0_records_cnt + vh0_records_cnt + vh1_records_cnt; + end + + // Latbuf status signals + always @(*) begin : latbuf_empty_comb + if (latbuf_cnt == 0) + latbuf_empty <= 1; + else + latbuf_empty <= 0; + end + + always @(*) begin : latbuf_full_comb + if (latbuf_cnt == NUM_WAIT_STATIONS) + latbuf_full <= 1; + else + latbuf_full <= 0; + end + + assign latbuf_almfull = (latbuf_cnt > NUM_STATIONS_FULL_THRESH) ? 1 : 0; + + // Initial assertion + initial begin + if (NUM_WAIT_STATIONS-5 <= 0 ) begin + $display("** ERROR ** => (NUM_WAIT_STATIONS-5) must not be less than 0... operation cannot continue -- EXIT !"); + start_simkill_countdown(); + end + end + + // push_ptr selector + function automatic integer find_next_push_slot(); + int find_iter; + int ret_free_slot; + begin + for(find_iter = latbuf_push_ptr; + find_iter < latbuf_push_ptr + NUM_WAIT_STATIONS; + find_iter = find_iter + 1) begin + ret_free_slot = find_iter % NUM_WAIT_STATIONS; + // if ( (records[ret_free_slot].state == LatSc_Disabled) && ~records[ret_free_slot].record_valid ) begin + if ( (records[ret_free_slot].state == LatSc_Disabled) && ~latbuf_busy_state[ret_free_slot] ) begin + return ret_free_slot; + end + end + return LATBUF_SLOT_INVALID; + end + endfunction + + // MCL Write in progress + logic mcl_write_in_progress; + int mcl_txn_iter; + int record_len; + + + /* + * Latbuf assignment process + * - Read and update record in latency scoreboard + */ + // Read channel VC->LATBUF glue +`ifdef READ_LATBUF_CHANNEL + function automatic void READ_get_vc_put_latbuf (ref logic [FIFO_WIDTH-1:0] array[$:INTERNAL_FIFO_DEPTH-1]); + logic [CCIP_TX_HDR_WIDTH-1:0] array_hdr; + logic [CCIP_DATA_WIDTH-1:0] array_data; + logic [LATBUF_TID_WIDTH-1:0] array_tid; + TxHdr_t hdr; + int ptr; + begin + hazpkt_in.valid = 0; + // Find a pointer to use + ptr = find_next_push_slot(); + latbuf_push_ptr = ptr; + // ------------------------------------------------------ // + // If slot is legal only then proceed + // ------------------------------------------------------ // + if (ptr != LATBUF_SLOT_INVALID) begin + set_latbuf_busy(ptr); + {array_tid, array_data, array_hdr} = array.pop_front(); + hdr = TxHdr_t'(array_hdr); + record_len = int'(hdr.len); + records[ptr].hdr[0] = hdr; + records[ptr].data[0] = array_data; + records[ptr].tid[0] = array_tid; + // records[ptr].record_push = 1; + // records[ptr].record_valid = 1; + records[ptr].num_items = int'(ASE_1CL); + mcl_write_in_progress = 0; + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | latbuf_push : tid=%x %s sent to record[%02d][0]\n", $time, array_tid, return_txhdr(hdr), ptr); + `endif + hazpkt_in.hdr = hdr; + hazpkt_in.tid = array_tid; + hazpkt_in.valid = 1; + end // if (ptr != LATBUF_SLOT_INVALID) + `ifdef ASE_DEBUG + else begin + $fwrite(log_fd, "%d | latbuf_push : Returned slot_num = %d .. UNUSED\n", $time, LATBUF_SLOT_INVALID); + end + `endif + end + endfunction +`endif + + + // Write channel VC->LATBUF glue +`ifdef WRITE_LATBUF_CHANNEL + function automatic void WRITE_get_vc_put_latbuf (ref logic [FIFO_WIDTH-1:0] array[$:INTERNAL_FIFO_DEPTH-1], + ref logic wrfence_flag, + ref logic [LATBUF_TID_WIDTH-1:0] wrfence_tid + ); + logic [CCIP_TX_HDR_WIDTH-1:0] array_hdr; + logic [CCIP_DATA_WIDTH-1:0] array_data; + logic [LATBUF_TID_WIDTH-1:0] array_tid; + TxHdr_t hdr; + int ptr; + begin + hazpkt_in.valid = 0; + // Find a pointer to use + if (~mcl_write_in_progress) begin + ptr = find_next_push_slot(); + latbuf_push_ptr = ptr; + end + else begin + ptr = latbuf_push_ptr; + end + // ------------------------------------------------------ // + // If slot is legal only then proceed + // ------------------------------------------------------ // + if (ptr != LATBUF_SLOT_INVALID) begin + {array_tid, array_data, array_hdr} = array.pop_front(); + hdr = TxHdr_t'(array_hdr); + // Record base length + if (hdr.sop) begin + mcl_txn_iter = 0; + record_len = int'(hdr.len); + end + // ------------------------------------------------------ // + // If Transaction is a Wrfence + // ------------------------------------------------------ // + if (hdr.reqtype == ASE_WRFENCE) begin + hazpkt_in.valid = 0; + wrfence_flag = 1; + wrfence_tid = array_tid; + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | latbuf_push : saw Wrfence on tid=%x on channel %s\n", $time, array_tid, ase_channel_type(hdr.vc)); + `endif + end + // ------------------------------------------------------ // + // If Transaction is a WRITE + // ------------------------------------------------------ // + else if (isWriteRequest(hdr)) begin + // ------------------------------------------------------ // + // If a VHx transaction + // ------------------------------------------------------ // + if (isVHxRequest(hdr)) begin + set_latbuf_busy(ptr); + records[ptr].hdr[mcl_txn_iter] = hdr; + records[ptr].data[mcl_txn_iter] = array_data; + records[ptr].tid[mcl_txn_iter] = array_tid; + // records[ptr].record_push = 1; + // records[ptr].record_valid = 1; + records[ptr].num_items = record_len; + if (mcl_txn_iter != record_len) + mcl_write_in_progress = 1; + else + mcl_write_in_progress = 0; + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | latbuf_push : tid=%x %s sent to record[%02d][%02d]\n", $time, array_tid, return_txhdr(hdr), ptr, mcl_txn_iter); + `endif + mcl_txn_iter = mcl_txn_iter + 1; + hazpkt_in.hdr = hdr; + hazpkt_in.tid = array_tid; + hazpkt_in.valid = 1; + end // if (isVHxRequest(hdr)) + // ------------------------------------------------------ // + // If a VL0 transaction + // ------------------------------------------------------ // + else begin + set_latbuf_busy(ptr); + records[ptr].hdr[0] = hdr; + records[ptr].data[0] = array_data; + records[ptr].tid[0] = array_tid; + // records[ptr].record_push = 1; + // records[ptr].record_valid = 1; + records[ptr].num_items = int'(ASE_1CL); + mcl_write_in_progress = 0; + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | latbuf_push : tid=%x sent to record[%02d][0]\n", $time, array_tid, ptr); + `endif + hazpkt_in.hdr = hdr; + hazpkt_in.tid = array_tid; + hazpkt_in.valid = 1; + end // else: !if(isVHxRequest(hdr)) + end // if (isWriteRequest(hdr)) + end // if (ptr != LATBUF_SLOT_INVALID) + `ifdef ASE_DEBUG + else begin + $fwrite(log_fd, "%d | latbuf_push : Returned slot_num = %d .. UNUSED\n", $time, LATBUF_SLOT_INVALID); + end // else: !if(ptr != LATBUF_SLOT_INVALID) + `endif + end + endfunction +`endif // `ifdef WRITE_LATBUF_CHANNEL + + + // --------------------------------------------------------- // + // States + // --------------------------------------------------------- // + typedef enum {Select_VL0, Select_VH0, Select_VH1} lssel_state; + lssel_state vc_pop; + + generate + // ====================================================================== // + // READ CHANNEL + // ====================================================================== // + if (WRITE_CHANNEL == 0) begin + always @(posedge clk) begin : READ_latbuf_push_proc + if (rst) begin + vc_pop <= Select_VL0; + vl0_wrfence_flag <= 0; + vh0_wrfence_flag <= 0; + vh1_wrfence_flag <= 0; + hazpkt_in.valid <= 0; + mcl_write_in_progress <= 0; + for(int ii = 0 ; ii < NUM_WAIT_STATIONS ; ii = ii + 1) begin + unset_latbuf_available(ii); + // records[ii].record_push <= 0; + // records[ii].record_valid <= 0; + end + end + else begin + // If input arrays are available + case (vc_pop) + Select_VL0: + begin + if (~vl0_array_empty && ~latbuf_almfull) begin + hazpkt_in.valid <= 1; + READ_get_vc_put_latbuf(vl0_array); + end + else begin + hazpkt_in.valid <= 0; + end + vc_pop <= Select_VH0; + end + + Select_VH0: + begin + if (~vh0_array_empty && ~latbuf_almfull) begin + hazpkt_in.valid <= 1; + READ_get_vc_put_latbuf(vh0_array); + end + else begin + hazpkt_in.valid <= 0; + end + vc_pop <= Select_VH1; + end + + Select_VH1: + begin + if (~vh1_array_empty && ~latbuf_almfull) begin + hazpkt_in.valid <= 1; + READ_get_vc_put_latbuf(vh1_array); + end + else begin + hazpkt_in.valid <= 0; + end + vc_pop <= Select_VL0; + end + + default: + begin + hazpkt_in.valid <= 0; + vc_pop <= Select_VL0; + end + + endcase // case (vc_pop) + // -------------------------------------------------- // + // Release latbuf_used & record_push + // -------------------------------------------------- // + for(int ii = 0 ; ii < NUM_WAIT_STATIONS ; ii = ii + 1) begin + if (records[ii].state == LatSc_Countdown) begin + unset_latbuf_available(ii); + // records[ii].record_push <= 0; + // records[ii].record_valid <= 0; + end + end + end + end + end + // ====================================================================== // + // WRITE CHANNEL + // ====================================================================== // + else if (WRITE_CHANNEL == 1) begin + always @(posedge clk) begin : WRITE_latbuf_push_proc + if (rst) begin + hazpkt_in.valid <= 0; + vc_pop <= Select_VL0; + vl0_wrfence_flag <= 0; + vh0_wrfence_flag <= 0; + vh1_wrfence_flag <= 0; + mcl_write_in_progress <= 0; + for(int ii = 0 ; ii < NUM_WAIT_STATIONS ; ii = ii + 1) begin + unset_latbuf_available(ii); + // records[ii].record_push <= 0; + // records[ii].record_valid <= 0; + end + end + else begin + // hazpkt_in.valid <= 0; + // If input arrays are available + case (vc_pop) + Select_VL0: + begin + // hazpkt_in.valid <= 0; + if (~vl0_wrfence_flag && ~vl0_array_empty && ~latbuf_almfull) begin + // hazpkt_in.valid <= 1; + WRITE_get_vc_put_latbuf(vl0_array, vl0_wrfence_flag, vl0_wrfence_tid ); + end + else begin + hazpkt_in.valid <= 0; + end + if (~mcl_write_in_progress) begin + vc_pop <= Select_VH0; + end + end + + Select_VH0: + begin + // hazpkt_in.valid <= 0; + if (~vh0_wrfence_flag && ~vh0_array_empty && ~latbuf_almfull) begin + // hazpkt_in.valid <= 1; + WRITE_get_vc_put_latbuf(vh0_array, vh0_wrfence_flag, vh0_wrfence_tid ); + end + else begin + hazpkt_in.valid <= 0; + end + if (~mcl_write_in_progress) begin + vc_pop <= Select_VH1; + end + end + + Select_VH1: + begin + // hazpkt_in.valid <= 0; + if (~vh1_wrfence_flag && ~vh1_array_empty && ~latbuf_almfull) begin + // hazpkt_in.valid <= 1; + WRITE_get_vc_put_latbuf(vh1_array, vh1_wrfence_flag, vh1_wrfence_tid ); + end + else begin + hazpkt_in.valid <= 0; + end + if (~mcl_write_in_progress) begin + vc_pop <= Select_VL0; + end + end + + default: + begin + // hazpkt_in.valid <= 0; + vc_pop <= Select_VL0; + end + + endcase // case (vc_pop) + // ------------------------------------------------------------- // + // WrFence assertion logic (assertions in WRITE mode only) + // ------------------------------------------------------------- // + // If a VL0 fence is set, wait till downstream gets cleared + if (vl0_wrfence_flag && (vl0_records_cnt == 0) && vl0_wrfence_deassert) begin + hazpkt_in.valid <= 0; + vl0_wrfence_flag <= 0; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | VL0 write fence popped\n", $time); +`endif + end + // If a VH0 fence is set, wait till downstream gets cleared + if (vh0_wrfence_flag && (vh0_records_cnt == 0) && vh0_wrfence_deassert) begin + hazpkt_in.valid <= 0; + vh0_wrfence_flag <= 0; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | VH0 write fence popped\n", $time); +`endif + end + // If a VH0 fence is set, wait till downstream gets cleared + if (vh1_wrfence_flag && (vh1_records_cnt == 0) && vh1_wrfence_deassert) begin + hazpkt_in.valid <= 0; + vh1_wrfence_flag <= 0; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | VH1 write fence popped\n", $time); +`endif + end + // -------------------------------------------------- // + // Release latbuf_used & record_push + // -------------------------------------------------- // + for(int ii = 0 ; ii < NUM_WAIT_STATIONS ; ii = ii + 1) begin + if (records[ii].state == LatSc_Countdown) begin + unset_latbuf_available(ii); + // records[ii].record_push <= 0; + // records[ii].record_valid <= 0; + end + end + end // else: !if(rst) + end // block: latbuf_push_proc + end + endgenerate + + // Print process (DEBUG ONLY) +`ifdef ASE_DEBUG + always @(posedge clk) begin + if (hazpkt_in.valid) begin + $fwrite(log_fd, "%d | hazpkt_in => tid = %x, hdr=%s\n", $time, hazpkt_in.tid, return_txhdr(hazpkt_in.hdr)); + end + end +`endif + + /* + * Latency scoreboard + */ + // Get delay function + function int get_delay(input TxHdr_t hdr); + int delay; + begin + case (hdr.vc) + VC_VL0: + begin + delay = get_random_from_range(`RDWR_VL_LATRANGE); + end + VC_VH0: + begin + delay = get_random_from_range(`RDWR_VH_LATRANGE); + end + VC_VH1: + begin + delay = get_random_from_range(`RDWR_VH_LATRANGE); + end + VC_VA: + begin + delay = 100; +`ifdef ASE_DEBUG + $fwrite(log_fd, "%d | *ERROR* => get_delay() must not get VC_VA", $time); +`endif + end + endcase // case (hdr.vc) +`ifdef ASE_PROFILE + histogram_stats[delay] = histogram_stats[delay] + 1; +`endif + return delay; + end + endfunction + + + // Wait station logic + genvar ii; + generate + for ( ii = 0; ii < NUM_WAIT_STATIONS; ii = ii + 1) begin : gen_latsc + // Record process + always @(posedge clk) begin : record_proc + if (rst) begin + records[ii].ctr_out <= 0; + records[ii].record_ready <= 0; + record_vl0_flag_arr[ii] <= 0; + record_vh0_flag_arr[ii] <= 0; + record_vh1_flag_arr[ii] <= 0; + end + else begin + case (records[ii].state) + LatSc_Disabled: + begin + records[ii].record_ready <= 0; + //if (records[ii].record_push) begin + // if (records[ii].record_valid) begin + if (latbuf_busy_state[ii]) begin + records[ii].ctr_out <= get_delay(records[ii].hdr[0]); + records[ii].state <= LatSc_Countdown; + if (records[ii].hdr[0].vc == VC_VL0) begin + record_vl0_flag_arr[ii] <= 1; + end + else if (records[ii].hdr[0].vc == VC_VH0) begin + record_vh0_flag_arr[ii] <= 1; + end + else if (records[ii].hdr[0].vc == VC_VH1) begin + record_vh1_flag_arr[ii] <= 1; + end + end + else begin + records[ii].ctr_out <= 0; + records[ii].state <= LatSc_Disabled; + end + end + + LatSc_Countdown: + begin + records[ii].ctr_out <= records[ii].ctr_out - 1; + if (records[ii].ctr_out == 0) begin + records[ii].record_ready <= 1; + records[ii].state <= LatSc_DoneReady; + end + else begin + records[ii].record_ready <= 0; + records[ii].state <= LatSc_Countdown; + end + end + + LatSc_DoneReady: + begin + records[ii].ctr_out <= 0; + if (records[ii].record_pop) begin + records[ii].record_ready <= 0; + records[ii].state <= LatSc_RecordPopped; + end + else begin + records[ii].record_ready <= 1; + records[ii].state <= LatSc_DoneReady; + end + end + + LatSc_RecordPopped: + begin + record_vl0_flag_arr[ii] <= 0; + record_vh0_flag_arr[ii] <= 0; + record_vh1_flag_arr[ii] <= 0; + records[ii].record_ready <= 0; + records[ii].ctr_out <= 0; + if (~records[ii].record_pop) begin + records[ii].state <= LatSc_Disabled; + end + else begin + records[ii].state <= LatSc_RecordPopped; + end + end + + default: + begin + records[ii].record_ready <= 0; + records[ii].ctr_out <= 0; + records[ii].state <= LatSc_Disabled; + end + endcase + end + end + + end + endgenerate + + + // Find a transaction to release to output stage + function integer find_next_pop_slot(); + int ret_pop_slot; + int pop_iter; + int sel_slot; + begin + for(pop_iter = latbuf_pop_ptr; pop_iter < latbuf_pop_ptr + NUM_WAIT_STATIONS ; pop_iter = pop_iter + 1) begin + sel_slot = pop_iter % NUM_WAIT_STATIONS; + if (records[sel_slot].record_ready) begin + return sel_slot; + end + end + return LATBUF_SLOT_INVALID; + end + endfunction + + + // Status of unroll (readouts) + logic [CCIP_RX_HDR_WIDTH-1:0] rxhdr_out_vec; + logic [CCIP_TX_HDR_WIDTH-1:0] txhdr_out_vec; + // logic // unroll_active; + + + /* + * get_latbuf_unroll_put_outfifo : Get a record from latbuf, unroll and stage in outfifo + * -------------------------------------------------------------------------------------- + * VirtChannel Read/Write MCL Action + * ------------------------------------------------------------- + * VL0 Read 0 Passthru + * VL0 Read 1 Passthru + * VL0 Write 0 Passthru + * VL0 Write 1 Passthru + * VHx Read 0 Unroll, outfifo + * VHx Read 1 Unroll, outfifo + * VHx Write 0 iterate, outfifo + * VHx Write 1 iterate, outfifo + * + */ +`ifdef READ_LATBUF_CHANNEL + // Read channel latbuf -> outfifo + task automatic READ_get_latbuf_unroll_put_outfifo(ref logic [OUTFIFO_WIDTH-1:0] array[$:VISIBLE_DEPTH-1] ); + TxHdr_t base_hdr; + logic [CCIP_DATA_WIDTH-1:0] data; + int ptr; + TxHdr_t txhdr; + RxHdr_t rxhdr; + logic [LATBUF_TID_WIDTH-1:0] tid; + int line_i; + logic [41:0] base_addr; + logic [15:0] base_mdata; + ccip_vc_t base_vc; + ccip_len_t base_len; + int loop_max; + begin + // unroll_active = 0; + ptr = find_next_pop_slot(); + latbuf_pop_ptr = ptr; + if (ptr != LATBUF_SLOT_INVALID) begin + // unroll_active = 1; + base_hdr = records[ptr].hdr[0]; + base_addr = records[ptr].hdr[0].addr; + base_mdata = records[ptr].hdr[0].mdata; + base_vc = records[ptr].hdr[0].vc; + base_len = records[ptr].hdr[0].len; + loop_max = records[ptr].num_items + 1; + // --------------------------------------------------------- // + // VL0 request (broken out by infifo_to_vc) + // --------------------------------------------------------- // + if (isVL0Request(base_hdr)) begin + txhdr = records[ptr].hdr[0]; + tid = records[ptr].tid[0]; + data = records[ptr].data[0]; + // --------------- RxHdr ------------------ // + rxhdr = RxHdr_t'(0); + rxhdr.vc_used = txhdr.vc; + rxhdr.hitmiss = 0; + rxhdr.mdata = base_mdata; + rxhdr.clnum = txhdr.len; + rxhdr.format = 0; + rxhdr.resptype = ASE_RD_RSP; + array.push_back({ tid, data, logic_cast_RxHdr_t'(rxhdr), logic_cast_TxHdr_t'(txhdr) }); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | record[%02d][0] size %1d with tid=%x unrolled %s %s \n", $time, ptr, loop_max, tid, return_txhdr(txhdr), return_rxhdr(rxhdr) ); + `endif + end + // ---------------------------------------------- // + // VHx MCL Read Request, unroll the request + // ---------------------------------------------- // + else if (isVHxRequest(base_hdr)) begin // && isReadRequest(base_hdr)) begin + txhdr = base_hdr; + tid = records[ptr].tid[0]; + data = {CCIP_DATA_WIDTH{1'b0}}; + for(int jj = 0; jj <= txhdr.len; jj = jj + 1) begin + txhdr.addr = base_addr + jj; + // --------------- RxHdr ------------------ // + rxhdr = RxHdr_t'(0); + rxhdr.hitmiss = 0; + rxhdr.mdata = base_mdata; + rxhdr.clnum = ccip_len_t'(jj); + rxhdr.vc_used = base_vc; + rxhdr.resptype = ASE_RD_RSP; + array.push_back({ tid, data, logic_cast_RxHdr_t'(rxhdr), logic_cast_TxHdr_t'(txhdr) }); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | record[%02d][%02d] size %1d with tid=%x unrolled %s %s \n", $time, ptr, jj, loop_max, tid, return_txhdr(txhdr), return_rxhdr(rxhdr) ); + `endif + end // for (int jj = 0; jj <= txhdr.len; jj = jj + 1) + end // if (isVHxRequest(base_hdr)) + // ----------------------------------------------------- // + // Pop record and deactivate unroll + // ----------------------------------------------------- // + // unroll_active = 0; + records[ptr].record_pop = 1; + @(posedge clk); + end // if (ptr != LATBUF_SLOT_INVALID) + end + endtask +`endif + + +`ifdef WRITE_LATBUF_CHANNEL + // Write channel latbuf -> outfifo + task automatic WRITE_get_latbuf_unroll_put_outfifo(ref logic [OUTFIFO_WIDTH-1:0] array[$:VISIBLE_DEPTH-1] ); + TxHdr_t base_hdr; + logic [CCIP_DATA_WIDTH-1:0] data; + int ptr; + TxHdr_t txhdr; + RxHdr_t rxhdr; + logic [LATBUF_TID_WIDTH-1:0] tid; + int line_i; + logic [41:0] base_addr; + logic [15:0] base_mdata; + ccip_vc_t base_vc; + ccip_len_t base_len; + int loop_max; + begin + // unroll_active = 0; + ptr = find_next_pop_slot(); + latbuf_pop_ptr = ptr; + if (ptr != LATBUF_SLOT_INVALID) begin + // unroll_active = 1; + base_hdr = records[ptr].hdr[0]; + base_addr = records[ptr].hdr[0].addr; + base_mdata = records[ptr].hdr[0].mdata; + base_vc = records[ptr].hdr[0].vc; + base_len = records[ptr].hdr[0].len; + loop_max = records[ptr].num_items + 1; + // --------------------------------------------------------- // + // VL0 request (broken out by infifo_to_vc) + // --------------------------------------------------------- // + if (isVL0Request(base_hdr)) begin + txhdr = records[ptr].hdr[0]; + tid = records[ptr].tid[0]; + data = records[ptr].data[0]; + // --------------- RxHdr ------------------ // + rxhdr = RxHdr_t'(0); + rxhdr.vc_used = txhdr.vc; + rxhdr.hitmiss = 0; + rxhdr.mdata = base_mdata; + rxhdr.clnum = txhdr.len; + rxhdr.format = 0; + rxhdr.resptype = ASE_WR_RSP; + array.push_back({ tid, data, logic_cast_RxHdr_t'(rxhdr), logic_cast_TxHdr_t'(txhdr) }); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | record[%02d][0] size %1d with tid=%x unrolled %s %s \n", $time, ptr, loop_max, tid, return_txhdr(txhdr), return_rxhdr(rxhdr) ); + `endif + end + // ---------------------------------------------- // + // VHx Write request + // ---------------------------------------------- // + else if (isVHxRequest(base_hdr)) begin + for (int rec_i = 0; rec_i < loop_max ; rec_i = rec_i + 1) begin + txhdr = records[ptr].hdr[rec_i]; + tid = records[ptr].tid[rec_i]; + data = records[ptr].data[rec_i]; + // --------------- RxHdr ------------------ // + rxhdr = RxHdr_t'(0); + rxhdr.clnum = base_len; + rxhdr.mdata = base_mdata; + rxhdr.vc_used = base_vc; + rxhdr.format = 1; + rxhdr.resptype = ASE_WR_RSP; + array.push_back({ tid, data, logic_cast_RxHdr_t'(rxhdr), logic_cast_TxHdr_t'(txhdr) }); + `ifdef ASE_DEBUG + $fwrite(log_fd, "%d | record[%02d][0] size %1d with tid=%x unrolled %s %s \n", $time, ptr, loop_max, tid, return_txhdr(txhdr), return_rxhdr(rxhdr) ); + `endif + end + end + // ----------------------------------------------------- // + // Pop record and deactivate unroll + // ----------------------------------------------------- // + // unroll_active = 0; + records[ptr].record_pop = 1; + @(posedge clk); + end // if (ptr != LATBUF_SLOT_INVALID) + end + endtask +`endif // `ifdef WRITE_LATBUF_CHANNE + + + // Wrfence response monitor +`ifdef WRITE_LATBUF_CHANNEL + always @(posedge clk) begin : wrfence_rsp_monitor + if (rst) begin + wrfence_rspvalid <= 0; + end + else if (~wrfence_rspvalid & (wrfence_rsp_cnt != 0)) begin + wrfence_rspvalid <= 1; + {wrfence_rsptid, wrfence_rsphdr, wrfence_reqhdr } = wrfence_rsp_array.pop_front(); + end + else if (wrfence_rspvalid & (vl0_wrfence_deassert|vh0_wrfence_deassert|vh1_wrfence_deassert) ) begin + wrfence_rspvalid <= 0; + end + end +`endif + + logic [2:0] latbuf_pop_proc_status; + + + /* + * Latbuf -> outfifo process + */ + generate + // ====================================================================== // + // READ CHANNEL + // ====================================================================== // + if (WRITE_CHANNEL == 0) begin + always @(posedge clk) begin : READ_latbuf_pop_proc + if (rst) begin + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b000; + glbl_wrfence_pop_status <= 0; + // unroll_active <= 0; + end + // empty outfifo on normal transactions + else if (~outfifo_almfull && ~latbuf_empty ) begin + READ_get_latbuf_unroll_put_outfifo(outfifo); + latbuf_pop_proc_status <= 3'b110; + end + // Else + else begin + latbuf_pop_proc_status <= 3'b000; + end + // ------------------------------------------------------------------- //- + // Book keeping + // -------------------------------------------------------------------- // + for(int ready_i = 0; ready_i < NUM_WAIT_STATIONS ; ready_i = ready_i + 1) begin + if (rst) begin + records[ready_i].record_pop <= 0; + end + else if ( (records[ready_i].state == LatSc_RecordPopped) || + (records[ready_i].state == LatSc_Disabled) ) begin + records[ready_i].record_pop <= 0; + end + end + end + end + // ====================================================================== // + // Write CHANNEL + // ====================================================================== // + else if (WRITE_CHANNEL == 1) begin + always @(posedge clk) begin : WRITE_latbuf_pop_proc + if (rst) begin + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b000; + glbl_wrfence_pop_status <= 0; + // unroll_active <= 0; + end + // empty outfifo on normal transactions + else if (~outfifo_almfull && ~latbuf_empty ) begin + WRITE_get_latbuf_unroll_put_outfifo(outfifo); + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b110; + glbl_wrfence_pop_status <= 0; + end + // Pop write fence + else if (wrfence_rspvalid && (vl0_wrfence_flag|vh0_wrfence_flag|vh1_wrfence_flag) && ~glbl_wrfence_pop_status) begin + case (wrfence_rsphdr.vc_used) + VC_VA : + begin + if ( (wrfence_rsptid == vl0_wrfence_tid) && + (wrfence_rsptid == vh0_wrfence_tid) && + (wrfence_rsptid == vh1_wrfence_tid) && + vl0_wrfence_flag && + vh0_wrfence_flag && + vh1_wrfence_flag ) begin + vl0_wrfence_deassert <= 1; + vh0_wrfence_deassert <= 1; + vh1_wrfence_deassert <= 1; + latbuf_pop_proc_status <= 3'b100; + glbl_wrfence_pop_status <= 1; + outfifo.push_back({wrfence_rsptid, {CCIP_DATA_WIDTH{1'b0}}, logic_cast_RxHdr_t'(wrfence_rsphdr), logic_cast_TxHdr_t'(wrfence_reqhdr) }); + end + end + + VC_VL0: + begin + if ((wrfence_rsptid == vl0_wrfence_tid) && vl0_wrfence_flag) begin + vl0_wrfence_deassert <= 1; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b101; + glbl_wrfence_pop_status <= 1; + outfifo.push_back({wrfence_rsptid, {CCIP_DATA_WIDTH{1'b0}}, logic_cast_RxHdr_t'(wrfence_rsphdr), logic_cast_TxHdr_t'(wrfence_reqhdr) }); + end + end + + VC_VH0: + begin + if ((wrfence_rsptid == vh0_wrfence_tid) && vh0_wrfence_flag ) begin + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 1; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b110; + glbl_wrfence_pop_status <= 1; + outfifo.push_back({wrfence_rsptid, {CCIP_DATA_WIDTH{1'b0}}, logic_cast_RxHdr_t'(wrfence_rsphdr), logic_cast_TxHdr_t'(wrfence_reqhdr) }); + end + end + + VC_VH1: + begin + if ((wrfence_rsptid == vh1_wrfence_tid) && vh1_wrfence_flag ) begin + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 1; + latbuf_pop_proc_status <= 3'b111; + glbl_wrfence_pop_status <= 1; + outfifo.push_back({wrfence_rsptid, {CCIP_DATA_WIDTH{1'b0}}, logic_cast_RxHdr_t'(wrfence_rsphdr), logic_cast_TxHdr_t'(wrfence_reqhdr) }); + end + end + endcase + end + else begin + vl0_wrfence_deassert <= 0; + vh0_wrfence_deassert <= 0; + vh1_wrfence_deassert <= 0; + latbuf_pop_proc_status <= 3'b000; + glbl_wrfence_pop_status <= 0; + // unroll_active <= 0; + end + // ------------------------------------------------------------------- //- + // Book keeping + // -------------------------------------------------------------------- // + for(int ready_i = 0; ready_i < NUM_WAIT_STATIONS ; ready_i = ready_i + 1) begin + if (rst) begin + records[ready_i].record_pop <= 0; + end + else if ( (records[ready_i].state == LatSc_RecordPopped) || + (records[ready_i].state == LatSc_Disabled) ) begin + records[ready_i].record_pop <= 0; + end + end + end // block: latbuf_pop_proc + // ====================================================================== // + end + endgenerate + + // Outfifo Full/Empty + assign outfifo_almfull = (outfifo_cnt > VISIBLE_FULL_THRESH) ? 1 : 0; + + always @(*) begin + if (outfifo_cnt == 0) + outfifo_empty <= 1; + else + outfifo_empty <= 0; + end + + assign empty = outfifo_empty; + + assign txhdr_out = TxHdr_t'(txhdr_out_vec); + assign rxhdr_out = RxHdr_t'(rxhdr_out_vec); + + + ////////////////////////////////////////////////////////////////////// + // Read guard + always @(posedge clk) begin : read_out_proc + if (rst) begin + valid_out <= 0; + end + else if (read_en && (outfifo.size() != 0)) begin + { tid_out, data_out, rxhdr_out_vec, txhdr_out_vec } <= outfifo.pop_front(); + valid_out <= 1; + end + else begin + valid_out <= 0; + end + end + + + /* + * Hazard-OUT interface assignment + */ + generate + // -------------------------------------- // + // Read channel configuration + // -------------------------------------- // + if (WRITE_CHANNEL == 0) begin + always @(posedge clk) begin + if (valid_out) begin + hazpkt_out.valid <= valid_out; + hazpkt_out.hdr <= txhdr_out; + hazpkt_out.tid <= tid_out; + end + else begin + hazpkt_out.valid <= 0; + end + end + end + // -------------------------------------- // + // Write channel configuration + // -------------------------------------- // + else if (WRITE_CHANNEL == 1) begin + always @(posedge clk) begin + if (valid_out && isWriteRequest(txhdr_out)) begin + hazpkt_out.valid <= valid_out; + hazpkt_out.hdr <= txhdr_out; + hazpkt_out.tid <= tid_out; + end + else begin + hazpkt_out.valid <= 0; + end + end + end + endgenerate + + + // Log output pop +`ifdef ASE_DEBUG + always @(posedge clk) begin + if (valid_out) begin + $fwrite(log_fd, "%d | EXIT => tid=%x with %s %s \n", $time, tid_out, return_txhdr(txhdr_out), return_rxhdr(rxhdr_out) ); + end + end +`endif + + + /* + * Transaction IN-OUT checker + * Sniffs dropped transactions, unexpected mdata, vc or mcl responses + */ +`ifdef ASE_DEBUG + TxHdr_t check_hdr_array[*]; + int check_vld_array[*]; + + // Check and delete from array + function automatic void check_delete_from_array(longint key); + begin + if (check_hdr_array.exists(key)) begin + check_hdr_array.delete(key); + check_vld_array.delete(key); + end + else begin + `BEGIN_RED_FONTCOLOR; + $display(" ** HASH ERROR ** %x key was not found ", key); + $fwrite(log_fd, " ** HASH ERROR ** %x key was not found ", key); + `END_RED_FONTCOLOR; + end + end + endfunction + + // Update & self-ccheck process + always @(posedge clk) begin + // Push to channel + if (write_en) begin + if (WRITE_CHANNEL == 0) begin + for (int ii = 0; ii <= hdr_in.len ; ii = ii + 1) begin + check_hdr_array [tid_in] <= hdr_in; + check_vld_array [tid_in] <= hdr_in.len + 1; + end + end + else if (WRITE_CHANNEL == 1) begin + check_hdr_array [tid_in] <= hdr_in; + check_vld_array [tid_in] <= 1; + end + end + // Pop from channel + if (valid_out) begin + check_vld_array[tid_out] = check_vld_array[tid_out] - 1; + if (check_vld_array[tid_out] == 0) begin + check_delete_from_array( tid_out ); + end + // *** VC checks here *** + if ((check_hdr_array[tid_out].vc != VC_VA) && (rxhdr_out.vc_used != check_hdr_array[tid_out].vc)) begin + `BEGIN_RED_FONTCOLOR; + $display("** ERROR **: VC was assigned incorrectly"); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + // ** MDATA checks here *** + if (rxhdr_out.mdata != check_hdr_array[tid_out].mdata) begin + `BEGIN_RED_FONTCOLOR; + $display("** ERROR **: MDATA was assigned incorrectly"); + `END_RED_FONTCOLOR; + start_simkill_countdown(); + end + end + end + +`endif + +endmodule // outoforder_wrf_channel diff --git a/ase/rtl/platform.vh b/ase/rtl/platform.vh new file mode 100644 index 000000000000..64915264a032 --- /dev/null +++ b/ase/rtl/platform.vh @@ -0,0 +1,163 @@ +/* **************************************************************************** + * Copyright(c) 2011-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ************************************************************************** + * + * Module Info: + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * ASE platform generics + * Control specific ASE behavior such as: + * - Latency range + * - Error/Warning colors + * + */ + +`ifndef _PLATFORM_VH_ + `define _PLATFORM_VH_ + + /* + * SIMKILL_ON_UNDEFINED: A switch to kill simulation if on a valid + * signal, 'X' or 'Z' is not allowed, gracious closedown on same + */ + `define VLOG_UNDEF 1'bx + `define VLOG_HIIMP 1'bz + + /* + * Print in Color + */ + // Error in RED color + `define BEGIN_RED_FONTCOLOR $display("\033[1;31m"); + `define END_RED_FONTCOLOR $display("\033[1;m"); + + // Info in GREEN color + `define BEGIN_GREEN_FONTCOLOR $display("\033[32;1m"); + `define END_GREEN_FONTCOLOR $display("\033[0m"); + + // Warnings/ASEDBGDUMP in YELLOW color + `define BEGIN_YELLOW_FONTCOLOR $display("\033[0;33m"); + `define END_YELLOW_FONTCOLOR $display("\033[0m"); + +/* + * Platform Specific parameters + * ----------------------------- + * INITIAL_SYSTEM_RESET_DURATION = Duration of initial system reset before system is up and running + * CLK_TIME = Clock cycle timescale + * LP_INITDONE_READINESS_LATENCY = Amount of time LP takes to be ready after reset is released + */ + + `define UMSG_DELAY_TIMER_LOG2 8 + + `define SOFT_RESET_DURATION 16 + `define RESET_TIMEOUT_DURATION 1024 + +/* + * CCI-P Clock, reset, and links + */ + `define INITIAL_SYSTEM_RESET_DURATION 20 + `define CLK_64UI_TIME 10000 + `define CLK_32UI_TIME 5000 + `define CLK_16UI_TIME 2500 + `define CLK_8UI_TIME 1250 + `define LP_INITDONE_READINESS_LATENCY 5 + `define NUM_VL_LINKS 1 + `define NUM_VH_LINKS 2 + + +/* + * MMIO Specifications + */ +`define MMIO_RESPONSE_TIMEOUT 512 +`define MMIO_RESPONSE_TIMEOUT_RADIX $clog2(`MMIO_RESPONSE_TIMEOUT) + 1 +`define MMIO_MAX_OUTSTANDING 64 + + +/* + * Latency model + * Coded as a Min,Max tuple + * ------------------------------------------------------- + * RDLINE_LATRANGE : ReadLine turnaround time + * WRLINE_LATRANGE : WriteLine turnaround time + * UMSG_LATRANGE : UMsg latency + * INTR_LATRANGE : Interrupt turnaround time + * + * LAT_UNDEFINED : Undefined latency + * + */ +`define MMIO_LATENCY 15 +`define RDLINE_S_LATRANGE 20,118 +`define RDLINE_I_LATRANGE 20,118 +`define WRLINE_M_LATRANGE 20,118 +`define WRLINE_I_LATRANGE 20,118 +`define UMSG_START2HINT_LATRANGE 39,41 // 200 ns +`define UMSG_HINT2DATA_LATRANGE 41,45 // 220 ns +`define UMSG_START2DATA_LATRANGE 82,85 // 420 ns +`define INTR_LATRANGE 10,15 + +`define LAT_UNDEFINED 300 + +`define RDWR_VL_LATRANGE 20,118 +`define RDWR_VH_LATRANGE 240,270 + +`define ASE_MAX_LATENCY 300 + + +/* + * Disable Transaction shuffling + * - In integrated mode, OutOfOrder channel control is used + * - In discrete mode, InOrder channel control is used + * + * Infinite bandwidth test mode (independent of platform selection) + * `define INFINITE_BANDWIDTH_MODE + * + * Specific platform features like interrupts and UMsgs are explicitly + * selected based on platform type + */ +// ------------------------------------------------------ // +`ifdef FPGA_PLATFORM_INTG_XEON + `ifdef INFINITE_BANDWIDTH_MODE + `define FORWARDING_CHANNEL inorder_wrf_channel + `else + `define FORWARDING_CHANNEL outoforder_wrf_channel + `endif + `define ASE_ENABLE_UMSG_FEATURE + `undef ASE_ENABLE_INTR_FEATURE +// ------------------------------------------------------ // +`elsif FPGA_PLATFORM_DISCRETE + `define FORWARDING_CHANNEL inorder_wrf_channel + `undef ASE_ENABLE_UMSG_FEATURE + `define ASE_ENABLE_INTR_FEATURE +// ------------------------------------------------------ // +`else +*** ASE will run only in 'FPGA_PLATFORM_INTG_XEON' or 'FPGA_PLATFORM_DISCRETE' modes, set ASE_PLATFORM *** +`endif +// ------------------------------------------------------ // + +`endif diff --git a/ase/rtl/sources.txt b/ase/rtl/sources.txt new file mode 100644 index 000000000000..eaab0e169d39 --- /dev/null +++ b/ase/rtl/sources.txt @@ -0,0 +1,12 @@ ++incdir+. + +ccip_if_pkg.sv +ase_pkg.sv +outoforder_wrf_channel.sv +inorder_wrf_channel.sv +latency_pipe.sv +ccip_emulator.sv +ase_svfifo.sv +ccip_logger.sv +ccip_checker.sv +ase_top.sv diff --git a/ase/sample_config/intg_xeon_nlb/config_mode0/ase_sources.mk b/ase/sample_config/intg_xeon_nlb/config_mode0/ase_sources.mk new file mode 100644 index 000000000000..36ab189a9b72 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode0/ase_sources.mk @@ -0,0 +1,18 @@ +############################################################## +# # +# Xeon(R) + FPGA AFU Simulation Environment # +# File generated by ase/scripts/generate_ase_environment.py # +# # +############################################################## + +DUT_VLOG_SRC_LIST = $(PATH_TO_VLOG_LIST)/vlog_files.list + +DUT_INCDIR = $(PATH_TO_NLB_RTL)/+$(PATH_TO_NLB_RTL)/QSYS_IPs+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/include_files+$(PATH_TO_NLB_RTL)/include_files/common+ + +SIMULATOR = VCS + +ASE_PLATFORM = FPGA_PLATFORM_INTG_XEON + +SNPS_VLOGAN_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_0 + +MENT_VLOG_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_0 diff --git a/ase/sample_config/intg_xeon_nlb/config_mode0/synopsys_sim.setup b/ase/sample_config/intg_xeon_nlb/config_mode0/synopsys_sim.setup new file mode 100644 index 000000000000..04f7ed5cc0ce --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode0/synopsys_sim.setup @@ -0,0 +1,2 @@ +WORK > DEFAULT +DEFAULT : ./work diff --git a/ase/sample_config/intg_xeon_nlb/config_mode0/vcs_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode0/vcs_run.tcl new file mode 100644 index 000000000000..3967d77b3cfe --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode0/vcs_run.tcl @@ -0,0 +1,4 @@ +dump -depth 0 +dump -aggregates -add / +run +quit diff --git a/ase/sample_config/intg_xeon_nlb/config_mode0/vlog_files.list b/ase/sample_config/intg_xeon_nlb/config_mode0/vlog_files.list new file mode 100644 index 000000000000..65a26e571bbb --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode0/vlog_files.list @@ -0,0 +1,26 @@ +$PATH_TO_NLB_RTL/include_files/common/sys_cfg_pkg.svh + + + + + +$PATH_TO_NLB_RTL/nlb_lpbk.sv +$PATH_TO_NLB_RTL/nlb_csr.sv +$PATH_TO_NLB_RTL/ccip_std_afu.sv +$PATH_TO_NLB_RTL/nlb_C1Tx_fifo.sv +$PATH_TO_NLB_RTL/ccip_debug.sv +$PATH_TO_NLB_RTL/arbiter.sv +$PATH_TO_NLB_RTL/requestor.sv +$PATH_TO_NLB_RTL/test_lpbk1.sv +$PATH_TO_NLB_RTL/ccip_interface_reg.sv +$PATH_TO_NLB_RTL/green_ccip_if_reg.sv +$PATH_TO_NLB_RTL/test_rdwr.sv +$PATH_TO_NLB_RTL/test_sw1.sv + + +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v +$PATH_TO_NLB_RTL/nlb_gram_sdp.v + diff --git a/ase/sample_config/intg_xeon_nlb/config_mode0/vsim_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode0/vsim_run.tcl new file mode 100644 index 000000000000..9ea592104632 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode0/vsim_run.tcl @@ -0,0 +1,2 @@ +add wave -r /* +run -all diff --git a/ase/sample_config/intg_xeon_nlb/config_mode3/ase_sources.mk b/ase/sample_config/intg_xeon_nlb/config_mode3/ase_sources.mk new file mode 100644 index 000000000000..546bd3448e4b --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode3/ase_sources.mk @@ -0,0 +1,18 @@ +############################################################## +# # +# Xeon(R) + FPGA AFU Simulation Environment # +# File generated by ase/scripts/generate_ase_environment.py # +# # +############################################################## + +DUT_VLOG_SRC_LIST = $(PATH_TO_VLOG_LIST)/vlog_files.list + +DUT_INCDIR = $(PATH_TO_NLB_RTL)/+$(PATH_TO_NLB_RTL)/QSYS_IPs+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/include_files+$(PATH_TO_NLB_RTL)/include_files/common+ + +SIMULATOR = VCS + +ASE_PLATFORM = FPGA_PLATFORM_INTG_XEON + +SNPS_VLOGAN_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_3 + +MENT_VLOG_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_3 diff --git a/ase/sample_config/intg_xeon_nlb/config_mode3/synopsys_sim.setup b/ase/sample_config/intg_xeon_nlb/config_mode3/synopsys_sim.setup new file mode 100644 index 000000000000..04f7ed5cc0ce --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode3/synopsys_sim.setup @@ -0,0 +1,2 @@ +WORK > DEFAULT +DEFAULT : ./work diff --git a/ase/sample_config/intg_xeon_nlb/config_mode3/vcs_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode3/vcs_run.tcl new file mode 100644 index 000000000000..3967d77b3cfe --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode3/vcs_run.tcl @@ -0,0 +1,4 @@ +dump -depth 0 +dump -aggregates -add / +run +quit diff --git a/ase/sample_config/intg_xeon_nlb/config_mode3/vlog_files.list b/ase/sample_config/intg_xeon_nlb/config_mode3/vlog_files.list new file mode 100644 index 000000000000..65a26e571bbb --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode3/vlog_files.list @@ -0,0 +1,26 @@ +$PATH_TO_NLB_RTL/include_files/common/sys_cfg_pkg.svh + + + + + +$PATH_TO_NLB_RTL/nlb_lpbk.sv +$PATH_TO_NLB_RTL/nlb_csr.sv +$PATH_TO_NLB_RTL/ccip_std_afu.sv +$PATH_TO_NLB_RTL/nlb_C1Tx_fifo.sv +$PATH_TO_NLB_RTL/ccip_debug.sv +$PATH_TO_NLB_RTL/arbiter.sv +$PATH_TO_NLB_RTL/requestor.sv +$PATH_TO_NLB_RTL/test_lpbk1.sv +$PATH_TO_NLB_RTL/ccip_interface_reg.sv +$PATH_TO_NLB_RTL/green_ccip_if_reg.sv +$PATH_TO_NLB_RTL/test_rdwr.sv +$PATH_TO_NLB_RTL/test_sw1.sv + + +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v +$PATH_TO_NLB_RTL/nlb_gram_sdp.v + diff --git a/ase/sample_config/intg_xeon_nlb/config_mode3/vsim_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode3/vsim_run.tcl new file mode 100644 index 000000000000..9ea592104632 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode3/vsim_run.tcl @@ -0,0 +1,2 @@ +add wave -r /* +run -all diff --git a/ase/sample_config/intg_xeon_nlb/config_mode7/ase_sources.mk b/ase/sample_config/intg_xeon_nlb/config_mode7/ase_sources.mk new file mode 100644 index 000000000000..578992d0c8b5 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode7/ase_sources.mk @@ -0,0 +1,18 @@ +############################################################## +# # +# Xeon(R) + FPGA AFU Simulation Environment # +# File generated by ase/scripts/generate_ase_environment.py # +# # +############################################################## + +DUT_VLOG_SRC_LIST = $(PATH_TO_VLOG_LIST)/vlog_files.list + +DUT_INCDIR = $(PATH_TO_NLB_RTL)/+$(PATH_TO_NLB_RTL)/QSYS_IPs+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160+$(PATH_TO_NLB_RTL)/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth+$(PATH_TO_NLB_RTL)/include_files+$(PATH_TO_NLB_RTL)/include_files/common+ + +SIMULATOR = VCS + +ASE_PLATFORM = FPGA_PLATFORM_INTG_XEON + +SNPS_VLOGAN_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_7 + +MENT_VLOG_OPT = +define+VENDOR_ALTERA +define+TOOL_QUARTUS +define+NUM_AFUS=1 +define+NLB400_MODE_7 diff --git a/ase/sample_config/intg_xeon_nlb/config_mode7/synopsys_sim.setup b/ase/sample_config/intg_xeon_nlb/config_mode7/synopsys_sim.setup new file mode 100644 index 000000000000..04f7ed5cc0ce --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode7/synopsys_sim.setup @@ -0,0 +1,2 @@ +WORK > DEFAULT +DEFAULT : ./work diff --git a/ase/sample_config/intg_xeon_nlb/config_mode7/vcs_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode7/vcs_run.tcl new file mode 100644 index 000000000000..3967d77b3cfe --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode7/vcs_run.tcl @@ -0,0 +1,4 @@ +dump -depth 0 +dump -aggregates -add / +run +quit diff --git a/ase/sample_config/intg_xeon_nlb/config_mode7/vlog_files.list b/ase/sample_config/intg_xeon_nlb/config_mode7/vlog_files.list new file mode 100644 index 000000000000..65a26e571bbb --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode7/vlog_files.list @@ -0,0 +1,26 @@ +$PATH_TO_NLB_RTL/include_files/common/sys_cfg_pkg.svh + + + + + +$PATH_TO_NLB_RTL/nlb_lpbk.sv +$PATH_TO_NLB_RTL/nlb_csr.sv +$PATH_TO_NLB_RTL/ccip_std_afu.sv +$PATH_TO_NLB_RTL/nlb_C1Tx_fifo.sv +$PATH_TO_NLB_RTL/ccip_debug.sv +$PATH_TO_NLB_RTL/arbiter.sv +$PATH_TO_NLB_RTL/requestor.sv +$PATH_TO_NLB_RTL/test_lpbk1.sv +$PATH_TO_NLB_RTL/ccip_interface_reg.sv +$PATH_TO_NLB_RTL/green_ccip_if_reg.sv +$PATH_TO_NLB_RTL/test_rdwr.sv +$PATH_TO_NLB_RTL/test_sw1.sv + + +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v +$PATH_TO_NLB_RTL/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v +$PATH_TO_NLB_RTL/nlb_gram_sdp.v + diff --git a/ase/sample_config/intg_xeon_nlb/config_mode7/vsim_run.tcl b/ase/sample_config/intg_xeon_nlb/config_mode7/vsim_run.tcl new file mode 100644 index 000000000000..9ea592104632 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/config_mode7/vsim_run.tcl @@ -0,0 +1,2 @@ +add wave -r /* +run -all diff --git a/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v new file mode 100644 index 000000000000..d4817e66617c --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/ram_2port_160/synth/lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a.v @@ -0,0 +1,114 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a ( + clock, + data, + rdaddress, + wraddress, + wren, + q); + + input clock; + input [533:0] data; + input [8:0] rdaddress; + input [8:0] wraddress; + input wren; + output [533:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [533:0] sub_wire0; + wire [533:0] q = sub_wire0[533:0]; + + altera_syncram altera_syncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address2_a (1'b1), + .address2_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({534{1'b1}}), + .eccencbypass (1'b0), + .eccencparity (8'b0), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .sclr (1'b0), + .wren_b (1'b0)); + defparam + altera_syncram_component.address_aclr_b = "NONE", + altera_syncram_component.address_reg_b = "CLOCK0", + altera_syncram_component.clock_enable_input_a = "BYPASS", + altera_syncram_component.clock_enable_input_b = "BYPASS", + altera_syncram_component.clock_enable_output_b = "BYPASS", + altera_syncram_component.intended_device_family = "Arria 10", + altera_syncram_component.lpm_type = "altera_syncram", + altera_syncram_component.maximum_depth = 512, + altera_syncram_component.numwords_a = 512, + altera_syncram_component.numwords_b = 512, + altera_syncram_component.operation_mode = "DUAL_PORT", + altera_syncram_component.outdata_aclr_b = "NONE", + altera_syncram_component.outdata_sclr_b = "NONE", + altera_syncram_component.outdata_reg_b = "CLOCK0", + altera_syncram_component.power_up_uninitialized = "FALSE", + altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altera_syncram_component.widthad_a = 9, + altera_syncram_component.widthad_b = 9, + altera_syncram_component.width_a = 534, + altera_syncram_component.width_b = 534, + altera_syncram_component.width_byteena_a = 1; + + +endmodule + + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v new file mode 100644 index 000000000000..2ba43c5fc7ed --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/lpbk1_RdRspRAM2PORT/synth/lpbk1_RdRspRAM2PORT.v @@ -0,0 +1,24 @@ +// lpbk1_RdRspRAM2PORT.v + +// Generated using ACDS version 16.0.1 218 + +`timescale 1 ps / 1 ps +module lpbk1_RdRspRAM2PORT ( + input wire [533:0] data, // ram_input.datain + input wire [8:0] wraddress, // .wraddress + input wire [8:0] rdaddress, // .rdaddress + input wire wren, // .wren + input wire clock, // .clock + output wire [533:0] q // ram_output.dataout + ); + + lpbk1_RdRspRAM2PORT_ram_2port_160_5m77a5a ram_2port_0 ( + .data (data), // ram_input.datain + .wraddress (wraddress), // .wraddress + .rdaddress (rdaddress), // .rdaddress + .wren (wren), // .wren + .clock (clock), // .clock + .q (q) // ram_output.dataout + ); + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v new file mode 100644 index 000000000000..4de64bf99e3f --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/ram_2port_160/synth/req_C1TxRAM2PORT_ram_2port_160_nfprwsy.v @@ -0,0 +1,114 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + + + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module req_C1TxRAM2PORT_ram_2port_160_nfprwsy ( + clock, + data, + rdaddress, + wraddress, + wren, + q); + + input clock; + input [555:0] data; + input [8:0] rdaddress; + input [8:0] wraddress; + input wren; + output [555:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; + tri0 wren; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [555:0] sub_wire0; + wire [555:0] q = sub_wire0[555:0]; + + altera_syncram altera_syncram_component ( + .address_a (wraddress), + .address_b (rdaddress), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_b (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address2_a (1'b1), + .address2_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b ({556{1'b1}}), + .eccencbypass (1'b0), + .eccencparity (8'b0), + .eccstatus (), + .q_a (), + .rden_a (1'b1), + .rden_b (1'b1), + .sclr (1'b0), + .wren_b (1'b0)); + defparam + altera_syncram_component.address_aclr_b = "NONE", + altera_syncram_component.address_reg_b = "CLOCK0", + altera_syncram_component.clock_enable_input_a = "BYPASS", + altera_syncram_component.clock_enable_input_b = "BYPASS", + altera_syncram_component.clock_enable_output_b = "BYPASS", + altera_syncram_component.intended_device_family = "Arria 10", + altera_syncram_component.lpm_type = "altera_syncram", + altera_syncram_component.maximum_depth = 512, + altera_syncram_component.numwords_a = 512, + altera_syncram_component.numwords_b = 512, + altera_syncram_component.operation_mode = "DUAL_PORT", + altera_syncram_component.outdata_aclr_b = "NONE", + altera_syncram_component.outdata_sclr_b = "NONE", + altera_syncram_component.outdata_reg_b = "CLOCK0", + altera_syncram_component.power_up_uninitialized = "FALSE", + altera_syncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", + altera_syncram_component.widthad_a = 9, + altera_syncram_component.widthad_b = 9, + altera_syncram_component.width_a = 556, + altera_syncram_component.width_b = 556, + altera_syncram_component.width_byteena_a = 1; + + +endmodule + + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v new file mode 100644 index 000000000000..0e73fe67503f --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/QSYS_IPs/RAM/req_C1TxRAM2PORT/synth/req_C1TxRAM2PORT.v @@ -0,0 +1,24 @@ +// req_C1TxRAM2PORT.v + +// Generated using ACDS version 16.0.1 218 + +`timescale 1 ps / 1 ps +module req_C1TxRAM2PORT ( + input wire [555:0] data, // ram_input.datain + input wire [8:0] wraddress, // .wraddress + input wire [8:0] rdaddress, // .rdaddress + input wire wren, // .wren + input wire clock, // .clock + output wire [555:0] q // ram_output.dataout + ); + + req_C1TxRAM2PORT_ram_2port_160_nfprwsy ram_2port_0 ( + .data (data), // ram_input.datain + .wraddress (wraddress), // .wraddress + .rdaddress (rdaddress), // .rdaddress + .wren (wren), // .wren + .clock (clock), // .clock + .q (q) // ram_output.dataout + ); + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/README_NLB_V1.1 b/ase/sample_config/intg_xeon_nlb/rtl/README_NLB_V1.1 new file mode 100644 index 000000000000..eed892a958c3 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/README_NLB_V1.1 @@ -0,0 +1,51 @@ +// *************************************************************************** +// +// Copyright (C) 2008-2013 Intel Corporation All Rights Reserved. +// +// Engineer: Pratik Marolia +// Create Date: 10/19/2011 +// Modified: 07/24/2014 +// +// *************************************************************************** +// NLB updated to run at 400MHz in A10. +// Removed arbitration logic, only support LPBK1 mode +// +// +// NLB v1.1 is a reference CCI attached Accelerator Function Unit (CAFU) designed for CCI v2.0 +// +// NLB Revision and feature tracking +//------------------------------------------------------------------------------------------- +// Rev CCI spec Comments +//------------------------------------------------------------------------------------------- +// 1.0 0.9 Uses proprietary memory mapped CSR read mapping +// 1.1 2.0 Device Status Memory Compliant -- Current +// 1.3 2.0 Portability across CCI and SPL -- Planned +//------------------------------------------------------------------------------------------- +// +// File structure- +// . +// |-- README_NLB_V1.1 // That is me +// |-- include_files // all include packages are under here +// | |-- altr // For Altera project- Add this dir to library path +// | | |-- nlb_cfg_pkg.vh +// | | `-- vendor_defines.vh +// | |-- common +// | | |-- nlb_cfg_pkg_altr.vh +// | | |-- nlb_cfg_pkg_xlnx.vh +// | | `-- vendor_defines.vh +// | `-- xlnx // For Xilinx project- Add this dir to library path +// | |-- nlb_cfg_pkg.vh +// | `-- vendor_defines.vh +// |-- arbiter.v // All the test modules +// |-- nlb_gfifo.v +// |-- nlb_gram_sdp.v +// |-- nlb_lpbk.v // -Micro Architecture Spec is contained in this file- +// |-- nlb_sb_gfifo.v +// |-- nlb_top.sv +// |-- requestor.v +// |-- test_lpbk1.v +// |-- test_lpbk2.v +// |-- test_lpbk3.v +// |-- test_rdwr.v +// `-- test_sw1.v +// diff --git a/ase/sample_config/intg_xeon_nlb/rtl/arbiter.sv b/ase/sample_config/intg_xeon_nlb/rtl/arbiter.sv new file mode 100755 index 000000000000..d8aeb7a02000 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/arbiter.sv @@ -0,0 +1,823 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: arbiter.v +// Project: NLB AFU +// Description: +// +// *************************************************************************** +// +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// Arbiter +// ------------------------------------------------------------------------------------------------------------------------------------------------ +// +// This module instantiates different test AFUs, and connect them up to the arbiter. + +`default_nettype none +module arbiter #(parameter PEND_THRESH=1, ADDR_LMT=20, MDATA=14) +( + + // ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + + ab2re_WrAddr, // [ADDR_LMT-1:0] app_cnt: write address + ab2re_WrTID, // [15:0] app_cnt: meta data + ab2re_WrDin, // [511:0] app_cnt: Cache line data + ab2re_WrFence, // app_cnt: write fence + ab2re_WrEn, // app_cnt: write enable + re2ab_WrSent, // app_cnt: write issued + re2ab_WrAlmFull, // app_cnt: write fifo almost full + + ab2re_RdAddr, // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + ab2re_RdTID, // [15:0] app_cnt: meta data + ab2re_RdEn, // app_cnt: read enable + re2ab_RdSent, // app_cnt: read issued + + re2ab_RdRspValid, // app_cnt: read response valid + re2ab_UMsgValid, // arbiter: UMsg valid + re2ab_CfgValid, // arbiter: Cfg valid + re2ab_RdRsp, // [15:0] app_cnt: read response header + re2ab_RdData, // [511:0] app_cnt: read data + re2ab_stallRd, // app_cnt: stall read requests FOR LPBK1 + + re2ab_WrRspValid, // app_cnt: write response valid + re2ab_WrRsp, // [ADDR_LMT-1:0] app_cnt: write response header + re2xy_go, // requestor: start the test + re2xy_src_addr, // [31:0] requestor: src address + re2xy_dst_addr, // [31:0] requestor: destination address + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_stride, // [31:0] requestor: stride value + re2xy_Cont, // requestor: continuous mode + re2xy_wrdin_msb, // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + re2xy_test_cfg, // [7:0] requestor: 8-bit test cfg register. + re2ab_Mode, // [2:0] requestor: test mode + ab2re_TestCmp, // arbiter: Test completion flag + ab2re_ErrorInfo, // [255:0] arbiter: error information + ab2re_ErrorValid, // arbiter: test has detected an error + cr2s1_csr_write, + test_Resetb, // requestor: rest the app + + ab2re_RdLen, + ab2re_RdSop, + ab2re_WrLen, + ab2re_WrSop, + + re2ab_RdRspFormat, + re2ab_RdRspCLnum, + re2ab_WrRspFormat, + re2ab_WrRspCLnum, + re2xy_multiCL_len // Default is 0 which implies single CL +); + + input logic Clk_400; // ccip_intf: Clk_400 + + output logic [ADDR_LMT-1:0] ab2re_WrAddr; // [ADDR_LMT-1:0] app_cnt: Writes are guaranteed to be accepted + output logic [15:0] ab2re_WrTID; // [15:0] app_cnt: meta data + output logic [511:0] ab2re_WrDin; // [511:0] app_cnt: Cache line data + output logic ab2re_WrFence; // app_cnt: write fence. + output logic ab2re_WrEn; // app_cnt: write enable + input logic re2ab_WrSent; // app_cnt: write issued + input logic re2ab_WrAlmFull; // app_cnt: write fifo almost full + + output logic [ADDR_LMT-1:0] ab2re_RdAddr; // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + output logic [15:0] ab2re_RdTID; // [15:0] app_cnt: meta data + output logic ab2re_RdEn; // app_cnt: read enable + input logic re2ab_RdSent; // app_cnt: read issued + + input logic re2ab_RdRspValid; // app_cnt: read response valid + input logic re2ab_UMsgValid; // arbiter: UMsg valid + input logic re2ab_CfgValid; // arbiter: Cfg valid + input logic [15:0] re2ab_RdRsp; // [15:0] app_cnt: read response header + input logic [511:0] re2ab_RdData; // [511:0] app_cnt: read data + input logic re2ab_stallRd; // app_cnt: stall read requests FOR LPBK1 + + input logic re2ab_WrRspValid; // app_cnt: write response valid + input logic [15:0] re2ab_WrRsp; // [15:0] app_cnt: write response header + + input logic re2xy_go; // requestor: start of frame recvd + input logic [31:0] re2xy_src_addr; // [31:0] requestor: src address + input logic [31:0] re2xy_dst_addr; // [31:0] requestor: destination address + input logic [31:0] re2xy_NumLines; // [31:0] requestor: number of cache lines + input logic [31:0] re2xy_stride; // [31:0] requestor: stride value + input logic re2xy_Cont; // requestor: continuous mode + input logic [7:0] re2xy_test_cfg; // [7:0] requestor: 8-bit test cfg register. + input logic [2:0] re2ab_Mode; // [2:0] requestor: test mode + input logic re2xy_wrdin_msb; // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + + output logic ab2re_TestCmp; // arbiter: Test completion flag + output logic [255:0] ab2re_ErrorInfo; // [255:0] arbiter: error information + output logic ab2re_ErrorValid; // arbiter: test has detected an error + + input logic cr2s1_csr_write; + input logic test_Resetb; + + output logic [1:0] ab2re_RdLen; + output logic ab2re_RdSop; + output logic [1:0] ab2re_WrLen; + output logic ab2re_WrSop; + + input logic re2ab_RdRspFormat; // TODO: This is not applicable. Even Multi CL Rds return individual unpacked response always + input logic [1:0] re2ab_RdRspCLnum; // For unpacked rd rsp, OoO + input logic re2ab_WrRspFormat; // Packed or unpacked response for multi CL Writes. + input logic [1:0] re2ab_WrRspCLnum; // for unpacked wr rsp, could be OoO + input logic [1:0] re2xy_multiCL_len; + + //------------------------------------------------------------------------------------------------------------------------ + + // Test Modes + //-------------------------------------------------------- + localparam M_LPBK1 = 3'b000; + localparam M_READ = 3'b001; + localparam M_WRITE = 3'b010; + localparam M_TRPUT = 3'b011; + localparam M_SW1 = 3'b111; + //-------------------------------------------------------- + + + //------------------------------------------------------------------------------------------------------------------------ + // test_lpbk1 signal declarations + //------------------------------------------------------------------------------------------------------------------------ + + wire [ADDR_LMT-1:0] l12ab_WrAddr; // [ADDR_LMT-1:0] app_cnt: write address + wire [15:0] l12ab_WrTID; // [15:0] app_cnt: meta data + wire [511:0] l12ab_WrDin; // [511:0] app_cnt: Cache line data + wire l12ab_WrEn; // app_cnt: write enable + reg ab2l1_WrSent; // app_cnt: write issued + reg ab2l1_WrAlmFull; // app_cnt: write fifo almost full + + wire [ADDR_LMT-1:0] l12ab_RdAddr; // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + wire [15:0] l12ab_RdTID; // [15:0] app_cnt: meta data + wire l12ab_RdEn; // app_cnt: read enable + reg ab2l1_RdSent; // app_cnt: read issued + + reg ab2l1_RdRspValid; // app_cnt: read response valid + reg ab2l1_UMsgValid; // app_cnt: UMsg valid + reg ab2l1_CfgValid; // app_cnt: Cfg valid + reg [15:0] ab2l1_RdRsp; // [15:0] app_cnt: read response header + reg [ADDR_LMT-1:0] ab2l1_RdRspAddr; // [ADDR_LMT-1:0] app_cnt: read response address + reg [511:0] ab2l1_RdData; // [511:0] app_cnt: read data + reg ab2l1_stallRd; // app_cnt: read stall + + reg ab2l1_WrRspValid; // app_cnt: write response valid + reg [15:0] ab2l1_WrRsp; // [15:0] app_cnt: write response header + reg [ADDR_LMT-1:0] ab2l1_WrRspAddr; // [Addr_LMT-1:0] app_cnt: write response address + + wire l12ab_TestCmp; // arbiter: Test completion flag + wire [255:0] l12ab_ErrorInfo; // [255:0] arbiter: error information + wire l12ab_ErrorValid; // arbiter: test has detected an error + + logic ab2l1_RdRspFormat; + logic [1:0] ab2l1_RdRspCLnum; + logic ab2l1_WrRspFormat; + logic [1:0] ab2l1_WrRspCLnum; + + logic [1:0] l12ab_RdLen; + logic l12ab_RdSop; + logic [1:0] l12ab_WrLen; + logic l12ab_WrSop; + + //------------------------------------------------------------------------------------------------------------------------ + // test_trput signal declarations + //------------------------------------------------------------------------------------------------------------------------ + reg [1:0] ab2rw_Mode; // arb: 1- reads only test, 0- writes only test + wire [ADDR_LMT-1:0] rw2ab_WrAddr; // [ADDR_LMT-1:0] app_cnt: write address + wire [15:0] rw2ab_WrTID; // [15:0] app_cnt: meta data + wire [511:0] rw2ab_WrDin; // [511:0] app_cnt: Cache line data + wire rw2ab_WrEn; // app_cnt: write enable + reg ab2rw_WrSent; // app_cnt: write issued + reg ab2rw_WrAlmFull; // app_cnt: write fifo almost full + + wire [ADDR_LMT-1:0] rw2ab_RdAddr; // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + wire [15:0] rw2ab_RdTID; // [15:0] app_cnt: meta data + wire rw2ab_RdEn; // app_cnt: read enable + reg ab2rw_RdSent; // app_cnt: read issued + + reg ab2rw_RdRspValid; // app_cnt: read response valid + reg ab2rw_UMsgValid; // app_cnt: UMsg valid + reg ab2rw_CfgValid; // app_cnt: Cfg valid + reg [15:0] ab2rw_RdRsp; // [15:0] app_cnt: read response header + reg [ADDR_LMT-1:0] ab2rw_RdRspAddr; // [ADDR_LMT-1:0] app_cnt: read response address + reg [511:0] ab2rw_RdData; // [511:0] app_cnt: read data + + reg ab2rw_WrRspValid; // app_cnt: write response valid + reg [15:0] ab2rw_WrRsp; // [15:0] app_cnt: write response header + reg [ADDR_LMT-1:0] ab2rw_WrRspAddr; // [Addr_LMT-1:0] app_cnt: write response address + + wire rw2ab_TestCmp; // arbiter: Test completion flag + wire [255:0] rw2ab_ErrorInfo; // [255:0] arbiter: error information + wire rw2ab_ErrorValid; // arbiter: test has detected an error + + logic ab2rw_RdRspFormat; + logic [1:0] ab2rw_RdRspCLnum; + logic ab2rw_WrRspFormat; + logic [1:0] ab2rw_WrRspCLnum; + + logic [1:0] rw2ab_RdLen; + logic rw2ab_RdSop; + logic [1:0] rw2ab_WrLen; + logic rw2ab_WrSop; + + //------------------------------------------------------------------------------------------------------------------------ + // test_sw1 signal declarations + //------------------------------------------------------------------------------------------------------------------------ + + wire [ADDR_LMT-1:0] s12ab_WrAddr; // [ADDR_LMT-1:0] app_cnt: write address + wire [15:0] s12ab_WrTID; // [15:0] app_cnt: meta data + wire [511:0] s12ab_WrDin; // [511:0] app_cnt: Cache line data + wire s12ab_WrEn; // app_cnt: write enable + wire s12ab_WrFence; // app_cnt: write fence + reg ab2s1_WrSent; // app_cnt: write issued + reg ab2s1_WrAlmFull; // app_cnt: write fifo almost full + + wire [ADDR_LMT-1:0] s12ab_RdAddr; // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + wire [15:0] s12ab_RdTID; // [15:0] app_cnt: meta data + wire s12ab_RdEn; // app_cnt: read enable + reg ab2s1_RdSent; // app_cnt: read issued + + reg ab2s1_RdRspValid; // app_cnt: read response valid + reg ab2s1_UMsgValid; // app_cnt: UMsg valid + reg ab2s1_CfgValid; // app_cnt: Cfg valid + reg [15:0] ab2s1_RdRsp; // [15:0] app_cnt: read response header + reg [ADDR_LMT-1:0] ab2s1_RdRspAddr; // [ADDR_LMT-1:0] app_cnt: read response address + reg [511:0] ab2s1_RdData; // [511:0] app_cnt: read data + + reg ab2s1_WrRspValid; // app_cnt: write response valid + reg [15:0] ab2s1_WrRsp; // [15:0] app_cnt: write response header + reg [ADDR_LMT-1:0] ab2s1_WrRspAddr; // [Addr_LMT-1:0] app_cnt: write response address + + wire s12ab_TestCmp; // arbiter: Test completion flag + wire [255:0] s12ab_ErrorInfo; // [255:0] arbiter: error information + wire s12ab_ErrorValid; // arbiter: test has detected an error + + // local variables + reg re2ab_RdRspValid_q, re2ab_RdRspValid_qq; + reg re2ab_WrRspValid_q, re2ab_WrRspValid_qq; + reg re2ab_UMsgValid_q, re2ab_UMsgValid_qq; + reg re2ab_CfgValid_q, re2ab_CfgValid_qq; + reg [15:0] re2ab_RdRsp_q, re2ab_RdRsp_qq; + reg [15:0] re2ab_WrRsp_q, re2ab_WrRsp_qq; + reg [511:0] re2ab_RdData_q, re2ab_RdData_qq; + + logic re2ab_RdRspFormat_q, re2ab_RdRspFormat_qq; + logic [1:0] re2ab_RdRspCLnum_q, re2ab_RdRspCLnum_qq; + logic re2ab_WrRspFormat_q, re2ab_WrRspFormat_qq; + logic [1:0] re2ab_WrRspCLnum_q, re2ab_WrRspCLnum_qq; + + //------------------------------------------------------------------------------------------------------------------------ + // Arbitrataion Memory instantiation + //------------------------------------------------------------------------------------------------------------------------ + wire [ADDR_LMT-1:0] arbmem_rd_dout; + wire [ADDR_LMT-1:0] arbmem_wr_dout; + + nlb_gram_sdp #(.BUS_SIZE_ADDR(MDATA), + .BUS_SIZE_DATA(ADDR_LMT), + .GRAM_MODE(2'd3) + )arb_rd_mem + ( + .clk (Clk_400), + .we (ab2re_RdEn), + .waddr(ab2re_RdTID[MDATA-1:0]), + .din (ab2re_RdAddr), + .raddr(re2ab_RdRsp[MDATA-1:0]), + .dout (arbmem_rd_dout ) + ); + + nlb_gram_sdp #(.BUS_SIZE_ADDR(MDATA), + .BUS_SIZE_DATA(ADDR_LMT), + .GRAM_MODE(2'd3) + )arb_wr_mem + ( + .clk (Clk_400), + .we (ab2re_WrEn), + .waddr(ab2re_WrTID[MDATA-1:0]), + .din (ab2re_WrAddr), + .raddr(re2ab_WrRsp[MDATA-1:0]), + .dout (arbmem_wr_dout ) + ); + + //------------------------------------------------------------------------------------------------------------------------ + always @(posedge Clk_400) + begin + re2ab_RdData_q <= re2ab_RdData; + re2ab_RdRsp_q <= re2ab_RdRsp; + re2ab_WrRsp_q <= re2ab_WrRsp; + re2ab_RdData_qq <= re2ab_RdData_q; + re2ab_RdRsp_qq <= re2ab_RdRsp_q; + re2ab_WrRsp_qq <= re2ab_WrRsp_q; + if(~test_Resetb) + begin + re2ab_RdRspValid_q <= 0; + re2ab_UMsgValid_q <= 0; + re2ab_CfgValid_q <= 0; + re2ab_WrRspValid_q <= 0; + re2ab_RdRspValid_qq <= 0; + re2ab_UMsgValid_qq <= 0; + re2ab_CfgValid_qq <= 0; + re2ab_WrRspValid_qq <= 0; + re2ab_RdRspFormat_q <= 0; + re2ab_RdRspFormat_qq <= 0; + re2ab_RdRspCLnum_q <= 0; + re2ab_RdRspCLnum_qq <= 0; + re2ab_WrRspFormat_q <= 0; + re2ab_WrRspFormat_qq <= 0; + re2ab_WrRspCLnum_q <= 0; + re2ab_WrRspCLnum_qq <= 0; + end + else + begin + re2ab_RdRspValid_q <= re2ab_RdRspValid; + re2ab_UMsgValid_q <= re2ab_UMsgValid; + re2ab_CfgValid_q <= re2ab_CfgValid; + re2ab_WrRspValid_q <= re2ab_WrRspValid; + re2ab_RdRspValid_qq <= re2ab_RdRspValid_q; + re2ab_UMsgValid_qq <= re2ab_UMsgValid_q; + re2ab_CfgValid_qq <= re2ab_CfgValid_q; + re2ab_WrRspValid_qq <= re2ab_WrRspValid_q; + re2ab_RdRspFormat_q <= re2ab_RdRspFormat; + re2ab_RdRspFormat_qq <= re2ab_RdRspFormat_q; + re2ab_RdRspCLnum_q <= re2ab_RdRspCLnum; + re2ab_RdRspCLnum_qq <= re2ab_RdRspCLnum_q; + re2ab_WrRspFormat_q <= re2ab_WrRspFormat; + re2ab_WrRspFormat_qq <= re2ab_WrRspFormat_q; + re2ab_WrRspCLnum_q <= re2ab_WrRspCLnum; + re2ab_WrRspCLnum_qq <= re2ab_WrRspCLnum_q; + end + end + + always @(*) + begin + // OUTPUTs + ab2re_WrAddr = 0; + ab2re_WrTID = 0; + ab2re_WrDin = 'hx; + ab2re_WrFence = 0; + ab2re_WrEn = 0; + ab2re_RdAddr = 0; + ab2re_RdTID = 0; + ab2re_RdEn = 0; + ab2re_TestCmp = 0; + ab2re_ErrorInfo = 'h0; + ab2re_ErrorValid= 0; + + ab2re_RdLen = 0; + ab2re_RdSop = 0; + ab2re_WrLen = 0; + ab2re_WrSop = 0; + + // M_LPBK1 + ab2l1_WrSent = 0; + ab2l1_WrAlmFull = 0; + ab2l1_RdSent = 0; + ab2l1_RdRspValid= 0; + ab2l1_RdRsp = 0; + ab2l1_RdRspAddr = 0; + ab2l1_RdData = 'hx; + ab2l1_stallRd = 0; + ab2l1_WrRspValid= 0; + ab2l1_WrRsp = 0; + ab2l1_WrRspAddr = 0; + + ab2l1_RdRspFormat = 0; + ab2l1_RdRspCLnum = 0; + ab2l1_WrRspFormat = 0; + ab2l1_WrRspCLnum = 0; + + // M_TRPUT + ab2rw_Mode = 0; + ab2rw_WrSent = 0; + ab2rw_WrAlmFull = 0; + ab2rw_RdSent = 0; + ab2rw_RdRspValid= 0; + ab2rw_RdRsp = 0; + ab2rw_RdRspAddr = 0; + ab2rw_RdData = 'hx; + ab2rw_WrRspValid= 0; + ab2rw_WrRsp = 0; + ab2rw_WrRspAddr = 0; + + ab2rw_RdRspFormat = 0; + ab2rw_RdRspCLnum = 0; + ab2rw_WrRspFormat = 0; + ab2rw_WrRspCLnum = 0; + + // M_SW1 + ab2s1_WrSent = 0; + ab2s1_WrAlmFull = 0; + ab2s1_RdSent = 0; + ab2s1_RdRspValid= 0; + ab2s1_CfgValid = 0; + ab2s1_UMsgValid = 0; + ab2s1_RdRsp = 0; + ab2s1_RdRspAddr = 0; + ab2s1_RdData = 'hx; + ab2s1_WrRspValid= 0; + ab2s1_WrRsp = 0; + ab2s1_WrRspAddr = 0; + + // --------------------------------------------------------------------------------------------------------------------- + // Input to tests + // --------------------------------------------------------------------------------------------------------------------- + `ifdef SIM_MODE + if(re2ab_Mode==M_LPBK1) + begin + // Input + ab2l1_WrSent = re2ab_WrSent; + ab2l1_WrAlmFull = re2ab_WrAlmFull; + ab2l1_RdSent = re2ab_RdSent; + ab2l1_RdRspValid = re2ab_RdRspValid_qq; + ab2l1_UMsgValid = re2ab_UMsgValid_qq; + ab2l1_CfgValid = re2ab_CfgValid_qq; + ab2l1_RdRsp = re2ab_RdRsp_qq; + ab2l1_RdRspAddr = arbmem_rd_dout; + ab2l1_RdData = re2ab_RdData_qq; + ab2l1_stallRd = re2ab_stallRd; + ab2l1_WrRspValid = re2ab_WrRspValid_qq; + ab2l1_WrRsp = re2ab_WrRsp_qq; + ab2l1_WrRspAddr = arbmem_wr_dout; + + ab2l1_RdRspFormat = re2ab_RdRspFormat_qq; + ab2l1_RdRspCLnum = re2ab_RdRspCLnum_qq; + ab2l1_WrRspFormat = re2ab_WrRspFormat_qq; + ab2l1_WrRspCLnum = re2ab_WrRspCLnum_qq; + // Output + ab2re_WrAddr = l12ab_WrAddr; + ab2re_WrTID = l12ab_WrTID; + ab2re_WrDin = l12ab_WrDin; + ab2re_WrFence = 1'b0; + ab2re_WrEn = l12ab_WrEn; + ab2re_RdAddr = l12ab_RdAddr; + ab2re_RdTID = l12ab_RdTID; + ab2re_RdEn = l12ab_RdEn; + ab2re_TestCmp = l12ab_TestCmp; + ab2re_ErrorInfo = l12ab_ErrorInfo; + ab2re_ErrorValid = l12ab_ErrorValid; + + ab2re_RdLen = l12ab_RdLen; + ab2re_RdSop = l12ab_RdSop; + ab2re_WrLen = l12ab_WrLen; + ab2re_WrSop = l12ab_WrSop; + + end + if(re2ab_Mode==M_TRPUT || re2ab_Mode==M_READ || re2ab_Mode==M_WRITE) + begin + // Input + ab2rw_Mode = re2ab_Mode[1:0]; + ab2rw_WrSent = re2ab_WrSent; + ab2rw_WrAlmFull = re2ab_WrAlmFull; + ab2rw_RdSent = re2ab_RdSent; + ab2rw_RdRspValid = re2ab_RdRspValid_qq; + ab2rw_UMsgValid = re2ab_UMsgValid_qq; + ab2rw_CfgValid = re2ab_CfgValid_qq; + ab2rw_RdRsp = re2ab_RdRsp_qq; + ab2rw_RdRspAddr = arbmem_rd_dout; + ab2rw_RdData = re2ab_RdData_qq; + ab2rw_WrRspValid = re2ab_WrRspValid_qq; + ab2rw_WrRsp = re2ab_WrRsp_q; + ab2rw_WrRspAddr = arbmem_wr_dout; + + ab2rw_RdRspFormat = re2ab_RdRspFormat_qq; + ab2rw_RdRspCLnum = re2ab_RdRspCLnum_qq; + ab2rw_WrRspFormat = re2ab_WrRspFormat_qq; + ab2rw_WrRspCLnum = re2ab_WrRspCLnum_qq; + // Output + ab2re_WrAddr = rw2ab_WrAddr; + ab2re_WrTID = rw2ab_WrTID; + ab2re_WrDin = rw2ab_WrDin; + ab2re_WrFence = 1'b0; + ab2re_WrEn = rw2ab_WrEn; + ab2re_RdAddr = rw2ab_RdAddr; + ab2re_RdTID = rw2ab_RdTID; + ab2re_RdEn = rw2ab_RdEn; + ab2re_TestCmp = rw2ab_TestCmp; + ab2re_ErrorInfo = rw2ab_ErrorInfo; + ab2re_ErrorValid = rw2ab_ErrorValid; + + ab2re_RdLen = rw2ab_RdLen; + ab2re_RdSop = rw2ab_RdSop; + ab2re_WrLen = rw2ab_WrLen; + ab2re_WrSop = rw2ab_WrSop; + end + if(re2ab_Mode==M_SW1) + begin + // Input + ab2s1_WrSent = re2ab_WrSent; + ab2s1_WrAlmFull = re2ab_WrAlmFull; + ab2s1_RdSent = re2ab_RdSent; + ab2s1_RdRspValid = re2ab_RdRspValid_qq; + ab2s1_UMsgValid = re2ab_UMsgValid_qq; + ab2s1_CfgValid = re2ab_CfgValid_qq; + ab2s1_RdRsp = re2ab_RdRsp_qq; + ab2s1_RdRspAddr = arbmem_rd_dout; + ab2s1_RdData = re2ab_RdData_qq; + ab2s1_WrRspValid = re2ab_WrRspValid_qq; + ab2s1_WrRsp = re2ab_WrRsp_qq; + ab2s1_WrRspAddr = arbmem_wr_dout; + // Output + ab2re_WrAddr = s12ab_WrAddr; + ab2re_WrTID = s12ab_WrTID; + ab2re_WrDin = s12ab_WrDin; + ab2re_WrFence = s12ab_WrFence; + ab2re_WrEn = s12ab_WrEn; + ab2re_RdAddr = s12ab_RdAddr; + ab2re_RdTID = s12ab_RdTID; + ab2re_RdEn = s12ab_RdEn; + ab2re_TestCmp = s12ab_TestCmp; + ab2re_ErrorInfo = s12ab_ErrorInfo; + ab2re_ErrorValid = s12ab_ErrorValid; + + ab2re_RdLen = 0; + ab2re_RdSop = 1; + ab2re_WrLen = 0; + ab2re_WrSop = 1; + end + + `else // NOT SIM_MODE + // PAR MODE + `ifdef NLB400_MODE_0 + // Input + ab2l1_WrSent = re2ab_WrSent; + ab2l1_WrAlmFull = re2ab_WrAlmFull; + ab2l1_RdSent = re2ab_RdSent; + ab2l1_RdRspValid = re2ab_RdRspValid_qq; + ab2l1_UMsgValid = re2ab_UMsgValid_qq; + ab2l1_CfgValid = re2ab_CfgValid_qq; + ab2l1_RdRsp = re2ab_RdRsp_qq; + ab2l1_RdRspAddr = arbmem_rd_dout; + ab2l1_RdData = re2ab_RdData_qq; + ab2l1_stallRd = re2ab_stallRd; + ab2l1_WrRspValid = re2ab_WrRspValid_qq; + ab2l1_WrRsp = re2ab_WrRsp_qq; + ab2l1_WrRspAddr = arbmem_wr_dout; + + ab2l1_RdRspFormat = re2ab_RdRspFormat_qq; + ab2l1_RdRspCLnum = re2ab_RdRspCLnum_qq; + ab2l1_WrRspFormat = re2ab_WrRspFormat_qq; + ab2l1_WrRspCLnum = re2ab_WrRspCLnum_qq; + + // Output + ab2re_WrAddr = l12ab_WrAddr; + ab2re_WrTID = l12ab_WrTID; + ab2re_WrDin = l12ab_WrDin; + ab2re_WrFence = 1'b0; + ab2re_WrEn = l12ab_WrEn; + ab2re_RdAddr = l12ab_RdAddr; + ab2re_RdTID = l12ab_RdTID; + ab2re_RdEn = l12ab_RdEn; + ab2re_TestCmp = l12ab_TestCmp; + ab2re_ErrorInfo = l12ab_ErrorInfo; + ab2re_ErrorValid = l12ab_ErrorValid; + + ab2re_RdLen = l12ab_RdLen; + ab2re_RdSop = l12ab_RdSop; + ab2re_WrLen = l12ab_WrLen; + ab2re_WrSop = l12ab_WrSop; + + `elsif NLB400_MODE_3 + // Input + ab2rw_Mode = re2ab_Mode[1:0]; + ab2rw_WrSent = re2ab_WrSent; + ab2rw_WrAlmFull = re2ab_WrAlmFull; + ab2rw_RdSent = re2ab_RdSent; + ab2rw_RdRspValid = re2ab_RdRspValid_qq; + ab2rw_UMsgValid = re2ab_UMsgValid_qq; + ab2rw_CfgValid = re2ab_CfgValid_qq; + ab2rw_RdRsp = re2ab_RdRsp_qq; + ab2rw_RdRspAddr = arbmem_rd_dout; + ab2rw_RdData = re2ab_RdData_qq; + ab2rw_WrRspValid = re2ab_WrRspValid_qq; + ab2rw_WrRsp = re2ab_WrRsp_qq; + ab2rw_WrRspAddr = arbmem_wr_dout; + + ab2rw_RdRspFormat = re2ab_RdRspFormat_qq; + ab2rw_RdRspCLnum = re2ab_RdRspCLnum_qq; + ab2rw_WrRspFormat = re2ab_WrRspFormat_qq; + ab2rw_WrRspCLnum = re2ab_WrRspCLnum_qq; + + // Output + ab2re_WrAddr = rw2ab_WrAddr; + ab2re_WrTID = rw2ab_WrTID; + ab2re_WrDin = rw2ab_WrDin; + ab2re_WrFence = 1'b0; + ab2re_WrEn = rw2ab_WrEn; + ab2re_RdAddr = rw2ab_RdAddr; + ab2re_RdTID = rw2ab_RdTID; + ab2re_RdEn = rw2ab_RdEn; + ab2re_TestCmp = rw2ab_TestCmp; + ab2re_ErrorInfo = rw2ab_ErrorInfo; + ab2re_ErrorValid = rw2ab_ErrorValid; + + ab2re_RdLen = rw2ab_RdLen; + ab2re_RdSop = rw2ab_RdSop; + ab2re_WrLen = rw2ab_WrLen; + ab2re_WrSop = rw2ab_WrSop; + + `elsif NLB400_MODE_7 + // Input + ab2s1_WrSent = re2ab_WrSent; + ab2s1_WrAlmFull = re2ab_WrAlmFull; + ab2s1_RdSent = re2ab_RdSent; + ab2s1_RdRspValid = re2ab_RdRspValid_qq; + ab2s1_UMsgValid = re2ab_UMsgValid_qq; + ab2s1_CfgValid = re2ab_CfgValid_qq; + ab2s1_RdRsp = re2ab_RdRsp_qq; + ab2s1_RdRspAddr = arbmem_rd_dout; + ab2s1_RdData = re2ab_RdData_qq; + ab2s1_WrRspValid = re2ab_WrRspValid_qq; + ab2s1_WrRsp = re2ab_WrRsp_qq; + ab2s1_WrRspAddr = arbmem_wr_dout; + // Output + ab2re_WrAddr = s12ab_WrAddr; + ab2re_WrTID = s12ab_WrTID; + ab2re_WrDin = s12ab_WrDin; + ab2re_WrFence = s12ab_WrFence; + ab2re_WrEn = s12ab_WrEn; + ab2re_RdAddr = s12ab_RdAddr; + ab2re_RdTID = s12ab_RdTID; + ab2re_RdEn = s12ab_RdEn; + ab2re_TestCmp = s12ab_TestCmp; + ab2re_ErrorInfo = s12ab_ErrorInfo; + ab2re_ErrorValid = s12ab_ErrorValid; + + ab2re_RdLen = 0; + ab2re_RdSop = 1; + ab2re_WrLen = 0; + ab2re_WrSop = 1; + `else + *** In PAR Mode, Select a valid NBL400_MODE: 0, 3, 7 + `endif +`endif + end + + test_lpbk1 #(.PEND_THRESH(PEND_THRESH), + .ADDR_LMT (ADDR_LMT), + .MDATA (MDATA) + ) + test_lpbk1( + Clk_400 , // in std_logic; -- Core clock + + l12ab_WrAddr, // [ADDR_LMT-1:0] app_cnt: write address + l12ab_WrTID, // [ADDR_LMT-1:0] app_cnt: meta data + l12ab_WrDin, // [511:0] app_cnt: Cache line data + l12ab_WrEn, // app_cnt: write enable + ab2l1_WrSent, // app_cnt: write issued + ab2l1_WrAlmFull, // app_cnt: write fifo almost full + + l12ab_RdAddr, // [ADDR_LMT-1:0] app_cnt: Reads may yield to writes + l12ab_RdTID, // [15:0] app_cnt: meta data + l12ab_RdEn, // app_cnt: read enable + ab2l1_RdSent, // app_cnt: read issued + + ab2l1_RdRspValid, // app_cnt: read response valid + ab2l1_RdRsp, // [15:0] app_cnt: read response header + ab2l1_RdRspAddr, // [ADDR_LMT-1:0] app_cnt: read response address + ab2l1_RdData, // [511:0] app_cnt: read data + ab2l1_stallRd, // app_cnt: stall read requests FOR LPBK1 + + ab2l1_WrRspValid, // app_cnt: write response valid + ab2l1_WrRsp, // [15:0] app_cnt: write response header + ab2l1_WrRspAddr, // [ADDR_LMT-1:0] app_cnt: write response address + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_Cont, // requestor: continuous mode + + l12ab_TestCmp, // arbiter: Test completion flag + l12ab_ErrorInfo, // [255:0] arbiter: error information + l12ab_ErrorValid, // arbiter: test has detected an error + test_Resetb, // requestor: rest the app + + l12ab_RdLen, + l12ab_RdSop, + l12ab_WrLen, + l12ab_WrSop, + + ab2l1_RdRspFormat, + ab2l1_RdRspCLnum, + ab2l1_WrRspFormat, + ab2l1_WrRspCLnum, + re2xy_multiCL_len + ); + + test_rdwr #(.PEND_THRESH(PEND_THRESH), + .ADDR_LMT (ADDR_LMT), + .MDATA (MDATA) + ) + + test_rdwr( + + // ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + ab2rw_Mode , // arb: 1- reads only test, 0- writes only test + + rw2ab_WrAddr, // [ADDR_LMT-1:0] arb: write address + rw2ab_WrTID, // [ADDR_LMT-1:0] arb: meta data + rw2ab_WrDin, // [511:0] arb: Cache line data + rw2ab_WrEn, // arb: write enable + ab2rw_WrSent, // arb: write issued + ab2rw_WrAlmFull, // arb: write fifo almost full + re2xy_wrdin_msb, // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + + rw2ab_RdAddr, // [ADDR_LMT-1:0] arb: Reads may yield to writes + rw2ab_RdTID, // [15:0] arb: meta data + rw2ab_RdEn, // arb: read enable + ab2rw_RdSent, // arb: read issued + + ab2rw_RdRspValid, // arb: read response valid + ab2rw_RdRsp, // [15:0] arb: read response header + ab2rw_RdRspAddr, // [ADDR_LMT-1:0] arb: read response address + ab2rw_RdData, // [511:0] arb: read data + + ab2rw_WrRspValid, // arb: write response valid + ab2rw_WrRsp, // [15:0] arb: write response header + ab2rw_WrRspAddr, // [ADDR_LMT-1:0] arb: write response address + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_Cont, // requestor: continuous mode + re2xy_stride, // [31:0] requestor: stride value + + + rw2ab_TestCmp, // arb: Test completion flag + rw2ab_ErrorInfo, // [255:0] arb: error information + rw2ab_ErrorValid, // arb: test has detected an error + test_Resetb, // requestor: rest the app + + rw2ab_RdLen, + rw2ab_RdSop, + rw2ab_WrLen, + rw2ab_WrSop, + + ab2rw_RdRspFormat, + ab2rw_RdRspCLnum, + ab2rw_WrRspFormat, + ab2rw_WrRspCLnum, + re2xy_multiCL_len + ); + + test_sw1 #(.PEND_THRESH(PEND_THRESH), + .ADDR_LMT (ADDR_LMT), + .MDATA (MDATA) + ) + + test_sw1 ( + + // ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + + s12ab_WrAddr, // [ADDR_LMT-1:0] arb: write address + s12ab_WrTID, // [ADDR_LMT-1:0] arb: meta data + s12ab_WrDin, // [511:0] arb: Cache line data + s12ab_WrFence, // arb: write fence + s12ab_WrEn, // arb: write enable + ab2s1_WrSent, // arb: write issued + ab2s1_WrAlmFull, // arb: write fifo almost full + + s12ab_RdAddr, // [ADDR_LMT-1:0] arb: Reads may yield to writes + s12ab_RdTID, // [15:0] arb: meta data + s12ab_RdEn, // arb: read enable + ab2s1_RdSent, // arb: read issued + + ab2s1_RdRspValid, // arb: read response valid + ab2s1_UMsgValid, // arb: UMsg valid + ab2s1_CfgValid, // arb: Cfg valid + ab2s1_RdRsp, // [15:0] arb: read response header + ab2s1_RdRspAddr, // [ADDR_LMT-1:0] arb: read response address + ab2s1_RdData, // [511:0] arb: read data + + ab2s1_WrRspValid, // arb: write response valid + ab2s1_WrRsp, // [15:0] arb: write response header + ab2s1_WrRspAddr, // [ADDR_LMT-1:0] arb: write response address + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_Cont, // requestor: continuous mode + re2xy_test_cfg, // [7:0] requestor: 8-bit test cfg register. + + s12ab_TestCmp, // arb: Test completion flag + s12ab_ErrorInfo, // [255:0] arb: error information + s12ab_ErrorValid, // arb: test has detected an error + cr2s1_csr_write, + test_Resetb // requestor: rest the app + ); +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/ccip_debug.sv b/ase/sample_config/intg_xeon_nlb/rtl/ccip_debug.sv new file mode 100755 index 000000000000..11ff1febda19 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/ccip_debug.sv @@ -0,0 +1,75 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// Module Name : ccip_std_afu +// Project : ccip afu top (work in progress) +// Description : This module instantiates CCI-P compliant AFU + +// *************************************************************************** +import ccip_if_pkg::*; +module ccip_debug( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx // CCI-P Tx Port +); + +// Register the signals +// Use these registered signals in Signal Tap +(* noprune *) logic [1:0] dbg_pwrState; +(* noprune *) logic dbg_error; +(* noprune *) t_if_ccip_Rx dbg_sRx; +(* noprune *) t_if_ccip_Tx dbg_sTx; + +always_ff @ (posedge pClk) +begin + dbg_pwrState <= pck_cp2af_pwrState; + dbg_error <= pck_cp2af_error; + + // Rx signals + dbg_sRx.c0.hdr <= pck_cp2af_sRx.c0.hdr; + dbg_sRx.c0.rspValid <= pck_cp2af_sRx.c0.rspValid; + dbg_sRx.c0.mmioRdValid <= pck_cp2af_sRx.c0.mmioRdValid; + dbg_sRx.c0.mmioWrValid <= pck_cp2af_sRx.c0.mmioWrValid; + // Data 8b only + dbg_sRx.c0.data[7:0] <= pck_cp2af_sRx.c0.data[7:0]; + + dbg_sRx.c1 <= pck_cp2af_sRx.c1; + + // Tx signals + dbg_sTx.c0 <= pck_af2cp_sTx; + dbg_sTx.c1.hdr <= pck_af2cp_sTx.c1.hdr; + dbg_sTx.c1.valid <= pck_af2cp_sTx.c1.valid; + // Data 8b only + dbg_sTx.c1.data[7:0] <= pck_af2cp_sTx.c1.data[7:0]; + dbg_sTx.c2 <= pck_af2cp_sTx.c2; +end + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/ccip_interface_reg.sv b/ase/sample_config/intg_xeon_nlb/rtl/ccip_interface_reg.sv new file mode 100755 index 000000000000..684aba03d024 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/ccip_interface_reg.sv @@ -0,0 +1,60 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// ====================================== +// Module to Register IF signals +// ====================================== + +import ccip_if_pkg::*; +module ccip_interface_reg( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CC-P clock domain. Primary Clock + input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State + input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port + input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port + + output logic pck_cp2af_softReset_T1, + output logic [1:0] pck_cp2af_pwrState_T1, + output logic pck_cp2af_error_T1, + + output t_if_ccip_Rx pck_cp2af_sRx_T1, + output t_if_ccip_Tx pck_af2cp_sTx_T1 +); + +always@(posedge pClk) +begin + pck_cp2af_softReset_T1 <= pck_cp2af_softReset_T0; + pck_cp2af_pwrState_T1 <= pck_cp2af_pwrState_T0; + pck_cp2af_error_T1 <= pck_cp2af_error_T0; + pck_cp2af_sRx_T1 <= pck_cp2af_sRx_T0; + pck_af2cp_sTx_T1 <= pck_af2cp_sTx_T0; +end + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/ccip_std_afu.sv b/ase/sample_config/intg_xeon_nlb/rtl/ccip_std_afu.sv new file mode 100755 index 000000000000..9835de1cf52a --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/ccip_std_afu.sv @@ -0,0 +1,119 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name : ccip_std_afu +// Project : ccip afu top +// Description : This module instantiates CCI-P compliant AFU + +// *************************************************************************** +`default_nettype none +import ccip_if_pkg::*; +module ccip_std_afu( + // CCI-P Clocks and Resets + pClk, // 400MHz - CCI-P clock domain. Primary interface clock + pClkDiv2, // 200MHz - CCI-P clock domain. + pClkDiv4, // 100MHz - CCI-P clock domain. + uClk_usr, // User clock domain. ** + uClk_usrDiv2, // User clock domain. + pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + pck_cp2af_pwrState, // CCI-P AFU Power State + pck_cp2af_error, // CCI-P Protocol Error Detected + + // Interface structures + pck_cp2af_sRx, // CCI-P Rx Port + pck_af2cp_sTx // CCI-P Tx Port +); + input wire pClk; // 400MHz - CCI-P clock domain. Primary interface clock + input wire pClkDiv2; // 200MHz - CCI-P clock domain. + input wire pClkDiv4; // 100MHz - CCI-P clock domain. + input wire uClk_usr; // User clock domain. + input wire uClk_usrDiv2; // User clock domain. + input wire pck_cp2af_softReset; // CCI-P ACTIVE HIGH Soft Reset + input wire [1:0] pck_cp2af_pwrState; // CCI-P AFU Power State + input wire pck_cp2af_error; // CCI-P Protocol Error Detected + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx; // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx; // CCI-P Tx Port + +// ============================================================= +// Register SR <--> PR signals at interface before consuming it +// ============================================================= + +(* noprune *) logic [1:0] pck_cp2af_pwrState_T1; +(* noprune *) logic pck_cp2af_error_T1; + +logic pck_cp2af_softReset_T1; +t_if_ccip_Rx pck_cp2af_sRx_T1; +t_if_ccip_Tx pck_af2cp_sTx_T0; + +ccip_interface_reg inst_green_ccip_interface_reg ( + .pClk (pClk), + .pck_cp2af_softReset_T0 (pck_cp2af_softReset), + .pck_cp2af_pwrState_T0 (pck_cp2af_pwrState), + .pck_cp2af_error_T0 (pck_cp2af_error), + .pck_cp2af_sRx_T0 (pck_cp2af_sRx), + .pck_af2cp_sTx_T0 (pck_af2cp_sTx_T0), + + .pck_cp2af_softReset_T1 (pck_cp2af_softReset_T1), + .pck_cp2af_pwrState_T1 (pck_cp2af_pwrState_T1), + .pck_cp2af_error_T1 (pck_cp2af_error_T1), + .pck_cp2af_sRx_T1 (pck_cp2af_sRx_T1), + .pck_af2cp_sTx_T1 (pck_af2cp_sTx) +); + +// ================================================================= +// NLB AFU- provides validation, performance characterization modes. +// It also serves as a reference design +// ================================================================= + +nlb_lpbk nlb_lpbk( + .Clk_400 (pClk), + .SoftReset (pck_cp2af_softReset_T1), + .cp2af_sRxPort (pck_cp2af_sRx_T1), + .af2cp_sTxPort (pck_af2cp_sTx_T0) +); + +// ================================================================= +// ccip_debug is a reference debug module for tapping cci-p signals +// ================================================================= +/* +ccip_debug inst_ccip_debug( + .pClk (pClk), + .pck_cp2af_pwrState (pck_cp2af_pwrState), + .pck_cp2af_error (pck_cp2af_error), + + .pck_cp2af_sRx (pck_cp2af_sRx), + .pck_af2cp_sTx (pck_af2cp_sTx) +); +*/ + +`ifdef FPGA_PLATFORM_DISCRETE + ** This version of NLB cannot be built on FPGA_PLATFORM_DISCRETE mode ** +`endif + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/green_ccip_if_reg.sv b/ase/sample_config/intg_xeon_nlb/rtl/green_ccip_if_reg.sv new file mode 100755 index 000000000000..7d699928e092 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/green_ccip_if_reg.sv @@ -0,0 +1,56 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// Module Name : +// Project : +// Description : + +// *************************************************************************** + +import ccip_if_pkg::*; +module green_ccip_if_reg( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock + + input logic pck_cp2af_softReset_d, + output logic pck_cp2af_softReset_q, + + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx_d, + output t_if_ccip_Rx pck_cp2af_sRx_q, + + input t_if_ccip_Tx pck_af2cp_sTx_d, + output t_if_ccip_Tx pck_af2cp_sTx_q +); + +always_ff @ (posedge pClk) +begin + pck_cp2af_sRx_q <= pck_cp2af_sRx_d; + pck_af2cp_sTx_q <= pck_af2cp_sTx_d; + pck_cp2af_softReset_q <= pck_cp2af_softReset_d; +end + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/nlb_cfg_pkg.vh b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/nlb_cfg_pkg.vh new file mode 100644 index 000000000000..39e9ffb7d6f9 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/nlb_cfg_pkg.vh @@ -0,0 +1,33 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +`ifndef NLB_CFG_PKG_VH +`define NLB_CFG_PKG_VH + `define VENDOR_ALTERA + `define TOOL_QUARTUS + `include "vendor_defines.vh" +`endif diff --git a/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/sys_cfg_pkg.svh b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/sys_cfg_pkg.svh new file mode 100755 index 000000000000..e4237791b201 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/sys_cfg_pkg.svh @@ -0,0 +1,35 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +`ifndef SYS_CFG_PKG_SV + `define SYS_CFG_PKG_SV +// `define CCIP_DEBUG // Add ccip_debug_module + `define VENDOR_ALTERA // Use Altera FPGA + `define TOOL_QUARTUS // Use Altera Quartus Tools +`endif + + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/vendor_defines.vh b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/vendor_defines.vh new file mode 100644 index 000000000000..06d5b8179753 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/include_files/common/vendor_defines.vh @@ -0,0 +1,114 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// ------------------------------------------------------------------------ +// TOOL and VENDOR Specific configurations +// ------------------------------------------------------------------------ +// The TOOL and VENDOR definition necessary to correctly configure PAR project +// package currently supports +// Vendors : Xilinx & Altera +// Tools : Synplify & Quartus II & Vivado +`include "sys_cfg_pkg.svh" +`ifndef VENDOR_DEFINES_VH +`define VENDOR_DEFINES_VH + + // Generate error if Vendor not defined + `ifdef VENDOR_XILINX + `ifdef VENDOR_ALTERA + ***Select only one VENDOR option*** + `endif + `else + `ifndef VENDOR_ALTERA + ***Select atleast one VENDOR option*** + `endif + `endif + + `ifdef VENDOR_ALTERA + `define GRAM_AUTO "no_rw_check" // defaults to auto + `define GRAM_BLCK "no_rw_check, M20K" + `define GRAM_DIST "no_rw_check, MLAB" + `endif + + //------------------------------------------- + // Generate error if TOOL not defined + `ifdef TOOL_QUARTUS + `ifdef TOOL_SYNPLIFY + ***Select only one TOOL option*** + `endif + `ifdef TOOL_VIVADO + ***Select only one TOOL option*** + `endif + + `elsif TOOL_SYNPLIFY + `ifdef TOOL_QUARTUS + ***Select atleast one TOOL option*** + `endif + `ifdef TOOL_VIVADO + ***Select atleast one TOOL option*** + `endif + `else + `ifndef TOOL_VIVADO + ***Select atleast one TOOL option*** + `endif + `endif + + `ifdef TOOL_QUARTUS + `define GRAM_STYLE ramstyle + `define NO_RETIMING dont_retime + `define NO_MERGE dont_merge + `define KEEP_WIRE syn_keep = 1 + `endif + + `ifdef TOOL_SYNPLIFY + `define GRAM_STYLE syn_ramstyle + `define NO_RETIMING syn_allow_retiming=0 + `define NO_MERGE syn_preserve=1 + `define KEEP_WIRE syn_keep=1 + + `ifdef VENDOR_XILINX + `define GRAM_AUTO "no_rw_check" + `define GRAM_BLCK "block_ram" + `define GRAM_DIST "select_ram" + `endif + + `endif + + `ifdef TOOL_VIVADO + `define GRAM_STYLE ram_style + `define NO_RETIMING dont_touch="true" + `define NO_MERGE dont_touch="true" + `define KEEP_WIRE keep="true" + + `ifdef VENDOR_XILINX + `define GRAM_AUTO "auto_gram" + `define GRAM_BLCK "block" + `define GRAM_DIST "distributed" + `endif + `endif + + +`endif diff --git a/ase/sample_config/intg_xeon_nlb/rtl/nlb_C1Tx_fifo.sv b/ase/sample_config/intg_xeon_nlb/rtl/nlb_C1Tx_fifo.sv new file mode 100755 index 000000000000..2529f8390561 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/nlb_C1Tx_fifo.sv @@ -0,0 +1,266 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: sbv_gfifo.v +// Project: NLB AFU +// Description: +// +// *************************************************************************** + +//----------------------------------------------------------------- +// (C) Copyright Intel Corporation, 2008. All Rights Reserved. +//----------------------------------------------------------------- +// +// +//--------------------------------------------------------------------------------------------------------------------------------------------------- +// sbv_gfifo with Read Store & Read-Write forwarding +//--------------------------------------------------------------------------------------------------------------------------------------------------- +// 22-4-2010 : Renamed cci_hdr_fifo into sb_gfifo +// 26-4-2011 : Derived sbv_gfifo from sb_gfifo. +// The read engine in the fifo presents valid data on output ports. When data out is used, rdack should be asserted. +// This is different from a traditional fifo where the fifo pops out a new data in response to a rden in the previous Clk. +// Instead this fifo presents the valid data on output port & expects a rdack in the same Clk when data is consumed. +// 27-6-2012 : Redesigned the sbv_gfifo to have registered outputs. The design consists of BRAM based fifo with 2 register stages in front +// of it. The second register stage is required to hide the BRAM write to read latency of 1. +// 10-10-2014: Edited the fifo with output register stage. Validated in JKT environment. Stratix 5 max frequency = 579MHz +// 10-13-2014: Mapped to Distributed memory with registered output. Fifo dout 1 clk delayed after fifo_dout_v +// Write to Read latency = 1, i.e. fifo_wen t0 fifo_dout_v latency = 1clk +// fifo_dout 1 cycle after fifo_dout_v +// 04-09-2015: derived from gfifo_2d +// Control will be 2clks ahead of Data +// Write to Read Control latency = 1clk +// Write to Read Data latency = 3clks +// +// |Write 1|T0 | |T2 | +// | |Dout_v1| |Dout | +// | |(ctl) | |(data) | +// | | | | | +// +// Full thresh - value should be less than/ euqual to 2**DEPTH_BASE2. If # entries more than threshold than fifo_almFull is set +// +// +// + +`include "vendor_defines.vh" +module nlb_C1Tx_fifo #(parameter DATA_WIDTH =51, + CTL_WIDTH =1, // control data width + DEPTH_BASE2 =3, + GRAM_STYLE =`GRAM_AUTO, + GRAM_MODE =3, // Uses registered RAM outputs. Write to Read Data out Lantecy = 2clks + FULL_THRESH =0 // fifo_almFull will be asserted if there are more entries than FULL_THRESH + ) + ( + Resetb, //Active low reset + Clk, //global clock + fifo_din, //Data input to the FIFO tail + fifo_ctlin, //control input + fifo_wen, //Write to the tail + fifo_rdack, //Read ack, pop the next entry + //--------------------- Output ------------------ + T2_fifo_dout, //FIFO read data out + T0_fifo_ctlout, //FIFO control output + T0_fifo_dout_v, //FIFO data out is valid + T0_fifo_empty, //FIFO is empty + T0_fifo_full, //FIFO is full + T0_fifo_count, //Number of entries in the FIFO + T0_fifo_almFull, //fifo_count > FULL_THRESH + T0_fifo_underflow, // fifo underflow + T0_fifo_overflow // fifo overflow + )/* synthesis maxfan=128 */; + +input Resetb; // Active low reset +input Clk; // global clock +input [DATA_WIDTH-1:0] fifo_din; // FIFO write data in +input [CTL_WIDTH-1:0] fifo_ctlin; +input fifo_wen; // FIFO write enable +input fifo_rdack; // Read ack, pop the next entry + +output [DATA_WIDTH-1:0] T2_fifo_dout; // FIFO read data out +output [CTL_WIDTH-1:0] T0_fifo_ctlout; +output T0_fifo_dout_v; // FIFO data out is valid +output T0_fifo_empty; // set when FIFO is empty +output T0_fifo_full; // set if Fifo full +output [DEPTH_BASE2-1:0] T0_fifo_count; // Number of entries in the fifo +output T0_fifo_almFull; +output T0_fifo_underflow; +output T0_fifo_overflow; +//------------------------------------------------------------------------------------ + +reg T0_fifo_underflow; +reg T0_fifo_overflow; +(* `NO_RETIMING *) reg dram_v; +(* ramstyle = "logic" *) reg [CTL_WIDTH-1:0] ctl_reg [2**DEPTH_BASE2]; +reg bram_wen, bram_full, bram_empty; +reg [DATA_WIDTH-1:0] bram_wdin; +wire [DATA_WIDTH-1:0] bram_rdout; +(* maxfan=150 *) reg [DEPTH_BASE2-1:0] bram_waddr, bram_raddr; +reg [DEPTH_BASE2-1:0] bram_raddr_next; +reg [DEPTH_BASE2-1:0] bram_raddr_d; +(* `NO_RETIMING, maxfan=7 *) reg [DEPTH_BASE2:0] bram_count; +(* `NO_RETIMING, `NO_MERGE *) reg bram_rena; +(* `NO_RETIMING, `NO_MERGE *) reg bram_renb; + + + +wire T0_fifo_dout_v = dram_v; +wire [DATA_WIDTH-1:0] T2_fifo_dout = bram_rdout; +wire T0_fifo_full = bram_count[DEPTH_BASE2]; +reg T0_fifo_almFull; +reg [CTL_WIDTH-1:0] T0_fifo_ctlout; +wire [DEPTH_BASE2-1:0] T0_fifo_count = bram_count[DEPTH_BASE2-1:0]; +wire T0_fifo_empty = bram_empty; + +// Data out shift register +// Shifts in data from either fifo_din or gram_rdata +always @(posedge Clk) +begin + if(fifo_wen) + ctl_reg[bram_waddr] <= fifo_ctlin; + + case(dram_v) + 1'b0:begin + if(fifo_wen) + begin + T0_fifo_ctlout <= fifo_ctlin; + dram_v <= 1'b1; + end + end + 1'b1:begin + if(bram_rena && ~fifo_wen && bram_count==1'b1) + dram_v <= 1'b0; + if(bram_rena && fifo_wen && bram_count==1'b1) + T0_fifo_ctlout <= fifo_ctlin; + else if(bram_rena) + T0_fifo_ctlout <= ctl_reg[bram_raddr_next]; + end + endcase + + if(CTL_WIDTH==0) + T0_fifo_ctlout <= 0; + + if(T0_fifo_empty & fifo_rdack ) + T0_fifo_underflow <= 1'b1; + if(T0_fifo_full & fifo_wen) + T0_fifo_overflow <= 1'b1; + + if(!Resetb) + begin + dram_v <= 0; + T0_fifo_underflow <= 0; + T0_fifo_overflow <= 0; + end +end + +always @(*) +begin + bram_wen = fifo_wen; + bram_rena = fifo_rdack; + bram_renb = fifo_rdack; + bram_wdin = fifo_din; + bram_full = bram_count[DEPTH_BASE2]; +end + +always @(posedge Clk) +begin + if(bram_wen & ~bram_full) + bram_waddr <= bram_waddr + 1'b1; + if(bram_renb & ~bram_empty) + begin + bram_raddr <= bram_raddr + 1'b1; + bram_raddr_next <= bram_raddr+2'h2; + end + + bram_count <= bram_count + (~bram_full & bram_wen) - (~bram_empty & bram_renb); + + case(bram_empty) + 1'b0: if(bram_count==1'b1 && ~bram_wen && bram_renb) + bram_empty <= 1'b1; + 1'b1: if(bram_wen) + bram_empty <= 1'b0; + endcase + + + if(!Resetb) + begin + bram_waddr <= 0; + bram_raddr <= 0; + bram_raddr_next <= 1'b1; + bram_count <= 0; + bram_empty <= 1'b1; + end +end + +// generate programmable full only when required +generate if (FULL_THRESH>0) +begin : GEN_ENABLE_fifo_almFull + always @(posedge Clk) + begin + if (!Resetb) + T0_fifo_almFull <= 0; + else + begin + casex ({(bram_rena && ~T0_fifo_empty), (fifo_wen && ~T0_fifo_full)}) + 2'b10: T0_fifo_almFull <= (bram_count-1'b1) >= FULL_THRESH; + 2'b01: T0_fifo_almFull <= (bram_count+1'b1) >= FULL_THRESH; + default: T0_fifo_almFull <= T0_fifo_almFull; + endcase + end + end +end +endgenerate + +//------------------------------------------------------------------------------------ +// instantiate gram with mode 3. Uses output register stage +// read to data out latency = 2clks +// we on critical path. Optimization- always write to the ram, when we==1, the wraddr is incremented +// this preserves the last write data to ram +// When fifo_full, it will corrupt the 0th data, current raddr. Therefore drop wren when fifo_full. + + // NOTE: RAM is currently sized to handle 556 bits (din/dout) and 512 deep + // Regenerate the RAM with additional bits if you increase the width/depth of this FIFO +req_C1TxRAM2PORT C1Tx_mem ( + .data (bram_wdin), // ram_input.datain + .wraddress (bram_waddr), // .wraddress + .rdaddress (bram_raddr), // .rdaddress + .wren (~bram_full), // .wren + .clock (Clk), // .clock + .q (bram_rdout) // ram_output.dataout + ); + +//--------------------------------------------------------------------------------------------------------------------- +// Error Logic +//--------------------------------------------------------------------------------------------------------------------- +/*synthesis translate_off */ +always @(*) +begin + assert(T0_fifo_underflow==0) else $fatal("ERROR: fifo underflow detected. \n Module Name: %m"); + assert(T0_fifo_overflow==0) else $fatal("ERROR: fifo overflow detected. \n Module Name: %m"); +end +/*synthesis translate_on */ +endmodule + + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/nlb_csr.sv b/ase/sample_config/intg_xeon_nlb/rtl/nlb_csr.sv new file mode 100755 index 000000000000..4d5bcbcffddd --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/nlb_csr.sv @@ -0,0 +1,539 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name : nlb_csr.v +// Project : NLB AFU update for CCI-P +// Description: Implements 64-bits read/write port a CSR file +// capable of doing 32 and 64 bit rd/wr the register file. +// +// *************************************************************************** +`default_nettype none +`include "vendor_defines.vh" +import ccip_if_pkg::*; +module nlb_csr #(parameter CCIP_VERSION_NUMBER=0) +( + Clk_400, // clk_pll: 16UI clock + SoftReset, // rst: ACTIVE HIGH soft reset + re2cr_wrlock_n, + // MMIO Requests from CCI-P + cp2cr_MmioHdr, // [31:0] CSR Request Hdr + cp2cr_MmioDin, // [63:0] CSR read data + cp2cr_MmioWrEn, // CSR write strobe + cp2cr_MmioRdEn, // CSR read strobe + // MMIO Responses to CCI-P + cr2cp_MmioHdr, // [11:0] CSR Response Hdr + cr2cp_MmioDout, // [63:0] CSR read data + cr2cp_MmioDout_v, // CSR read data valid + // connections to requestor + cr2re_src_address, + cr2re_dst_address, + cr2re_num_lines, + cr2re_inact_thresh, + cr2re_interrupt0, + cr2re_cfg, + cr2re_ctl, + cr2re_stride, + cr2re_dsm_base, + cr2re_dsm_base_valid, + cr2s1_csr_write, + + re2cr_num_reads, + re2cr_num_writes, + re2cr_num_Rdpend, + re2cr_num_Wrpend, + re2cr_error +); +input wire Clk_400; // 400MHz clock +input wire SoftReset; +input wire re2cr_wrlock_n; +// MMIO Requests +input t_ccip_c0_ReqMmioHdr cp2cr_MmioHdr; // CSR Request Hdr +input t_ccip_mmioData cp2cr_MmioDin; // CSR read data +input logic cp2cr_MmioWrEn; // CSR write enable +input logic cp2cr_MmioRdEn; // CSR read enable +// MMIO Response +output t_ccip_c2_RspMmioHdr cr2cp_MmioHdr; // CSR Response Hdr +output t_ccip_mmioData cr2cp_MmioDout; // CSR read data +output logic cr2cp_MmioDout_v; // CSR read data valid +// Connections to requestor +(* `KEEP_WIRE *) output wire [63:0] cr2re_src_address; +(* `KEEP_WIRE *) output wire [63:0] cr2re_dst_address; +(* `KEEP_WIRE *) output wire [31:0] cr2re_num_lines; +(* `KEEP_WIRE *) output wire [31:0] cr2re_inact_thresh; +(* `KEEP_WIRE *) output wire [31:0] cr2re_interrupt0; +(* `KEEP_WIRE *) output wire [63:0] cr2re_cfg; +(* `KEEP_WIRE *) output wire [31:0] cr2re_ctl; +(* `KEEP_WIRE *) output wire [31:0] cr2re_stride; +(* `KEEP_WIRE *) output wire [63:0] cr2re_dsm_base; +(* `KEEP_WIRE *) output reg cr2re_dsm_base_valid; +(* `KEEP_WIRE *) output reg cr2s1_csr_write; + +(* `KEEP_WIRE *) input wire [31:0] re2cr_num_reads; +(* `KEEP_WIRE *) input wire [31:0] re2cr_num_writes; +(* `KEEP_WIRE *) input wire [31:0] re2cr_num_Rdpend; +(* `KEEP_WIRE *) input wire [31:0] re2cr_num_Wrpend; +(* `KEEP_WIRE *) input wire [31:0] re2cr_error; + +// -------------------------------------------------------------------------- +// BBB Attributes +// -------------------------------------------------------------------------- +localparam END_OF_LIST = 1'h0; // Set this to 0 if there is another DFH beyond this +localparam NEXT_DFH_BYTE_OFFSET = 24'h1000; // Next DFH Byte offset + +//---------------------------------------------------------------------------- +// CSR Attributes +//---------------------------------------------------------------------------- +localparam RO = 3'h0; +localparam RW = 3'h1; +localparam RsvdP = 3'h6; +localparam RsvdZ = 3'h6; + +//--------------------------------------------------------- +// CSR Address Map ***** DO NOT MODIFY ***** +//--------------------------------------------------------- +localparam CSR_AFH_DFH_BASE = 16'h000; // RO - Start for the DFH info for this AFU +localparam CSR_AFH_ID_L = 16'h008; // RO - Lower 64 bits of the AFU ID +localparam CSR_AFH_ID_H = 16'h010; // RO - Upper 64 bits of the AFU ID +localparam CSR_DFH_RSVD0 = 16'h018; // RO - Offset to next AFU +localparam CSR_DFH_RSVD1 = 16'h020; // RO - Reserved space for DFH managment(?) + +localparam CSR_SCRATCHPAD0 = 16'h100; // 32b +localparam CSR_SCRATCHPAD1 = 16'h104; // 32b +localparam CSR_SCRATCHPAD2 = 16'h108; // 64b + +localparam CSR_AFU_DSM_BASEL = 16'h110; // 32b // RW - Lower 32-bits of AFU DSM base address. The lower 6-bbits are 4x00 since the address is cache aligned. +localparam CSR_AFU_DSM_BASEH = 16'h114; // 32b // RW - Upper 32-bits of AFU DSM base address. + +localparam CSR_SRC_ADDR = 16'h120; // 64b // RW Reads are targetted to this region +localparam CSR_DST_ADDR = 16'h128; // 64b // RW Writes are targetted to this region +localparam CSR_NUM_LINES = 16'h130; // 32b // RW Numbers of cache lines to be read/write +localparam CSR_CTL = 16'h138; // 32b // RW Control CSR to start n stop the test +localparam CSR_CFG = 16'h140; // 32b // RW Configures test mode, wrthru, cont and delay mode +localparam CSR_INACT_THRESH = 16'h148; // 32b // RW set the threshold limit for inactivity trigger + +localparam CSR_SWTEST_MSG = 16'h158; // 32b // RW Write to this serves as a notification to SW test +localparam CSR_STATUS0 = 16'h160; // 32b RO num_read, num_writes +localparam CSR_STATUS1 = 16'h168; // 32b RO num_Rdpend, num_Wrpend +localparam CSR_ERROR = 16'h170; // 32b RO error +localparam CSR_STRIDE = 16'h178; // 32b // stride value +//--------------------------------------------------------- +localparam NO_STAGED_CSR = 16'hXXX; // used for NON late action CSRs +localparam CFG_SEG_SIZE = 16'h180>>3; // Range specified in number of 8B CSRs +localparam[15:0]CFG_SEG_BEG = 16'h0000; +localparam CFG_SEG_END = CFG_SEG_BEG+(CFG_SEG_SIZE<<3); +localparam L_CFG_SEG_SIZE = $clog2(CFG_SEG_SIZE) == 0?1:$clog2(CFG_SEG_SIZE); + +localparam FEATURE_0_BEG = 18'h0000; +//localparam FEATURE_1_BEG = 18'h1000; + +//WARNING: The next localparam must match what is currently in the +// requestor.v file. This should be moved to a global package/file +// that can be used, rather than in two files. Future Work. PKB +// PAR Mode +// Each Test implements a different functionality +// Therefore it should really be treated like a different AFU +// For ease of maintainability they are implemented in a single source tree +// At compile time, user can decide which test mode is synthesized. +`ifndef SIM_MODE // PAR_MODE + `ifdef NLB400_MODE_0 + localparam NLB_AFU_ID_H = 64'hD842_4DC4_A4A3_C413; + localparam NLB_AFU_ID_L = 64'hF89E_4336_83F9_040B; + + `elsif NLB400_MODE_3 + localparam NLB_AFU_ID_H = 64'hF7DF_405C_BD7A_CF72; + localparam NLB_AFU_ID_L = 64'h22F1_44B0_B93A_CD18; + `elsif NLB400_MODE_7 + localparam NLB_AFU_ID_H = 64'h7BAF_4DEA_A57C_E91E; + localparam NLB_AFU_ID_L = 64'h168A_455D_9BDA_88A3; + `elsif NLB400_MODE_5 + localparam NLB_AFU_ID_H = 64'hA0B8_4916_A8A2_12A1; + localparam NLB_AFU_ID_L = 64'hA2EC_457C_84E7_47BC; + `else + ** Select a valid NLB Test Mode + `endif +`else // SIM_MODE + // Temporary Workaround + // Simulation tests are always expecting same AFU ID + // ** To be Fixed ** + localparam NLB_AFU_ID_H = 64'hC000_C966_0D82_4272; + localparam NLB_AFU_ID_L = 64'h9AEF_FE5F_8457_0612; +`endif + +//---------------------------------------------------------------------------------------------------------------------------------------------- +reg rw1c_pulse, rw1s_pulse; +reg [63:0] csr_reg [2**L_CFG_SEG_SIZE-1:0]; // register file +wire [15:0] afu_csr_addr_4B = cp2cr_MmioHdr.address; +wire [14:0] afu_csr_addr_8B = afu_csr_addr_4B[15:1]; +wire [1:0] afu_csr_length = cp2cr_MmioHdr.length; +wire ip_select = afu_csr_addr_8B[14:L_CFG_SEG_SIZE]==CFG_SEG_BEG[15:L_CFG_SEG_SIZE+3]; +reg afu_csr_length_4B_T1, afu_csr_length_8B_T1; +reg afu_csr_length_4B_T2, afu_csr_length_8B_T2; +reg afu_csr_length_8B_T3; +t_ccip_mmioData afu_csr_wrdin_T1, afu_csr_dout_T3; +t_ccip_mmioData afu_csr_dout_T2 [1:0]; +reg [1:0] afu_csr_dw_enable_T1, afu_csr_dw_enable_T2, afu_csr_dw_enable_T3; +reg afu_csr_wren_T1, afu_csr_rden_T1, afu_csr_dout_v_T2, afu_csr_dout_v_T3; +t_ccip_tid afu_csr_tid_T1, afu_csr_tid_T2, afu_csr_tid_T3; +(* maxfan=1 *) reg [14:0] afu_csr_offset_8B_T1; +reg range_valid; +integer i; +assign cr2re_interrupt0 = 0; + +initial begin + for (i=0;i<2**L_CFG_SEG_SIZE;i=i+1) + csr_reg[i] = 64'h0; +end + +assign cr2re_ctl = func_csr_connect_4B(CSR_CTL,csr_reg[CSR_CTL>>3]); +assign cr2re_stride = func_csr_connect_4B(CSR_STRIDE,csr_reg[CSR_STRIDE>>3]); +assign cr2re_dsm_base[31:0] = func_csr_connect_4B(CSR_AFU_DSM_BASEL,csr_reg[CSR_AFU_DSM_BASEL>>3]); +assign cr2re_dsm_base[63:32] = func_csr_connect_4B(CSR_AFU_DSM_BASEH,csr_reg[CSR_AFU_DSM_BASEH>>3]); +assign cr2re_src_address = csr_reg[CSR_SRC_ADDR>>3]; +assign cr2re_dst_address = csr_reg[CSR_DST_ADDR>>3]; +assign cr2re_num_lines = func_csr_connect_4B(CSR_NUM_LINES, csr_reg[CSR_NUM_LINES>>3]); +assign cr2re_inact_thresh = func_csr_connect_4B(CSR_INACT_THRESH,csr_reg[CSR_INACT_THRESH>>3]); +assign cr2re_cfg = csr_reg[CSR_CFG>>3]; + +function automatic [31:0] func_csr_connect_4B; + input [15:0] address; + input [63:0] data_8B; + begin + if(address[2]) + func_csr_connect_4B = data_8B[63:32]; + else + func_csr_connect_4B = data_8B[31:0]; + end +endfunction +// [14:9] , [8:0] +wire [14:0] feature_0_addr_offset_8B_T1 = {FEATURE_0_BEG[17:12], 3'h0, afu_csr_offset_8B_T1[5:0]}; +//wire [14:0] feature_1_addr_offset_8B_T1 = {FEATURE_1_BEG[17:12], afu_csr_offset_8B_T1[8:0]}; +reg [1:0] feature_id_T2; +always @(posedge Clk_400) +begin + // -Stage T1- + afu_csr_tid_T1 <= cp2cr_MmioHdr.tid; + afu_csr_offset_8B_T1 <= afu_csr_addr_4B[15:1]; + + if(cp2cr_MmioWrEn | cp2cr_MmioRdEn) + begin + afu_csr_length_4B_T1 <= afu_csr_length==2'b00; + afu_csr_length_8B_T1 <= afu_csr_length==2'b01; + end + // DW enable is used when doing a 4B write + case({afu_csr_length, afu_csr_addr_4B[0]}) + 3'b000: begin afu_csr_dw_enable_T1 <= 2'b01; + afu_csr_wrdin_T1 <= cp2cr_MmioDin; + end + 3'b001: begin afu_csr_dw_enable_T1 <= 2'b10; + afu_csr_wrdin_T1 <= {cp2cr_MmioDin[31:0], cp2cr_MmioDin[31:0]}; + end + default:begin afu_csr_dw_enable_T1 <= 2'b11; + afu_csr_wrdin_T1 <= cp2cr_MmioDin; + end + endcase + + afu_csr_wren_T1 <= 1'b0; + afu_csr_rden_T1 <= 1'b0; + if(ip_select) + begin + afu_csr_wren_T1 <= cp2cr_MmioWrEn; + afu_csr_rden_T1 <= cp2cr_MmioRdEn; + end + + // -Stage T2- + afu_csr_dout_v_T2 <= afu_csr_rden_T1; + afu_csr_dw_enable_T2 <= afu_csr_dw_enable_T1; + afu_csr_length_4B_T2 <= afu_csr_length_4B_T1; + afu_csr_length_8B_T2 <= afu_csr_length_8B_T1; + afu_csr_tid_T2 <= afu_csr_tid_T1; + + // Read Feature 0 + addr offset + afu_csr_dout_T2[0] <= csr_reg[feature_0_addr_offset_8B_T1]; + // Read Feature 1 + addr offset +// afu_csr_dout_T2[1] <= csr_reg[feature_1_addr_offset_8B_T1]; + + feature_id_T2 <= afu_csr_offset_8B_T1[10:9]; + + // -Stage T3- + afu_csr_dout_v_T3 <= afu_csr_dout_v_T2; + afu_csr_dw_enable_T3 <= afu_csr_dw_enable_T2; + afu_csr_length_8B_T3 <= afu_csr_length_8B_T2; + afu_csr_tid_T3 <= afu_csr_tid_T2; + + case(feature_id_T2) + 2'h0 : afu_csr_dout_T3 <= afu_csr_dout_T2[0]; +// 2'h1 : afu_csr_dout_T3 <= afu_csr_dout_T2[1]; + default : afu_csr_dout_T3 <= afu_csr_dout_T2[0]; + endcase + + // -Stage T4- + case(afu_csr_dw_enable_T3) + 2'b10: cr2cp_MmioDout <= afu_csr_dout_T3[63:32]; + default:cr2cp_MmioDout <= afu_csr_dout_T3; + endcase + cr2cp_MmioDout_v <= afu_csr_dout_v_T3; + cr2cp_MmioHdr <= afu_csr_tid_T3; + + if(SoftReset) + begin + cr2cp_MmioDout_v <= 1'b0; + end + + // AFH DFH Declarations: + // The AFU-DFH must have the following mapping + // [63:60] 4'b0001 + // [59:52] Rsvd + // [51:48] 4b User defined AFU mimor version # + // [47:41] Rsvd + // [40] End of List + // [39:16] 24'h0 because no other DFHs + // [15:12] 4b User defined AFU major version # + // [11:0] 12'h001 CCI-P version # + set_attr(CSR_AFH_DFH_BASE, + NO_STAGED_CSR, + 1'b1, + {64{RW}}, + {4'b0001, // Type=AFU + 8'h0, + 4'h0, // AFU minor version # + 7'h0, + END_OF_LIST, + NEXT_DFH_BYTE_OFFSET, + 4'h1, // AFU major version # + CCIP_VERSION_NUMBER}); // CCI-P version # + + // The AFU ID + set_attr(CSR_AFH_ID_L, + NO_STAGED_CSR, + 1'b1, + {64{RO}}, + NLB_AFU_ID_L); + + set_attr(CSR_AFH_ID_H, + NO_STAGED_CSR, + 1'b1, + {64{RO}}, + NLB_AFU_ID_H); + + + set_attr(CSR_DFH_RSVD0, + NO_STAGED_CSR, + 1'b1, + {64{RsvdP}}, + 64'h0); + + // And set the Reserved AFU DFH 0x020 block to Reserved + set_attr(CSR_DFH_RSVD1, + NO_STAGED_CSR, + 1'b1, + {64{RsvdP}}, + 64'h0); + + // CSR Declarations + // These are the parts of the CSR Register that are unique + // for the NLB AFU. They are not required for the FIU. + // The are used by the SW that accesses this AFU. + set_attr(CSR_SCRATCHPAD0, // + CSR_SCRATCHPAD1 + NO_STAGED_CSR, + 1'b1, + {64{RW}}, + 64'h0 + ); + + set_attr(CSR_SCRATCHPAD2, + NO_STAGED_CSR, + 1'b1, + {64{RW}}, + 64'h0 + ); + + + set_attr(CSR_AFU_DSM_BASEL, // + CSR_AFU_DSM_BASEH + NO_STAGED_CSR, + 1'b1, + {64{RW}}, + 64'h0 + ); + + if(SoftReset) + cr2re_dsm_base_valid <= 1'b0; + else if(afu_csr_wren_T1 + && afu_csr_offset_8B_T1==CSR_AFU_DSM_BASEL[3+:L_CFG_SEG_SIZE] + && afu_csr_dw_enable_T1==2'b01 + ) + cr2re_dsm_base_valid <= 1'b1; + + set_attr(CSR_SRC_ADDR, + NO_STAGED_CSR, + re2cr_wrlock_n, + {64{RW}}, + 64'h0 + ); + + set_attr(CSR_DST_ADDR, + NO_STAGED_CSR, + re2cr_wrlock_n, + {64{RW}}, + 64'h0 + ); + + set_attr(CSR_NUM_LINES, + NO_STAGED_CSR, + 1'b1, + { + {44{RsvdP}}, + {20{RW}} + }, + 64'h0 + ); + + set_attr(CSR_CTL, + NO_STAGED_CSR, + 1'b1, + {{32{RW}}, + {16{RsvdP}}, + {16{RW}} + }, + 64'h0 + ); + + set_attr(CSR_STRIDE, + NO_STAGED_CSR, + 1'b1, + {{58{RsvdP}}, + {6{RW}} + }, + 64'h0 + ); + + set_attr(CSR_CFG, + NO_STAGED_CSR, + re2cr_wrlock_n, + {64{RW}}, + 64'h0 + ); + + set_attr(CSR_INACT_THRESH, + NO_STAGED_CSR, + re2cr_wrlock_n, + {64{RW}}, + 64'h0 + ); + + + set_attr(CSR_SWTEST_MSG, + NO_STAGED_CSR, + 1'b1, + {64{RW}}, + 64'h0 + ); + + set_attr(CSR_STATUS0, + NO_STAGED_CSR, + 1'b1, + {64{RO}}, + {re2cr_num_reads, re2cr_num_writes} + ); + + set_attr(CSR_STATUS1, + NO_STAGED_CSR, + 1'b1, + {64{RO}}, + {re2cr_num_Rdpend, re2cr_num_Wrpend} + ); + + set_attr(CSR_ERROR, + NO_STAGED_CSR, + 1'b1, + {64{RO}}, + {32'h0, re2cr_error} + ); + + if(SoftReset) + cr2s1_csr_write <= 0; + else + begin + if( afu_csr_wren_T1 + && afu_csr_offset_8B_T1==CSR_SWTEST_MSG[3+:L_CFG_SEG_SIZE] + ) + cr2s1_csr_write <= 1'b1; + else + cr2s1_csr_write <= 1'b0; + end +end + + +//---------------------------------------------------------------------------------------------------------------------------------------------- +task automatic set_attr; + input [15:0] csr_id; // byte aligned CSR address + input [15:0] staged_csr_id; // byte aligned CSR address for late action staged register + input conditional_wr; // write condition for RW, RWS, RWDL attributes + input [3*64-1:0] attr; // Attribute for each bit in the CSR + input [63:0] default_val; // Initial value on Reset + reg [12:0] csr_offset_8B; + reg [12:0] staged_csr_offset_8B; + reg [1:0] this_write; + integer i,j; + begin + + csr_offset_8B = csr_id[3+:L_CFG_SEG_SIZE]; + staged_csr_offset_8B = staged_csr_id[3+:L_CFG_SEG_SIZE]; + this_write[0] = afu_csr_wren_T1 && (csr_offset_8B==afu_csr_offset_8B_T1) && conditional_wr && afu_csr_dw_enable_T1[0]; + this_write[1] = afu_csr_wren_T1 && (csr_offset_8B==afu_csr_offset_8B_T1) && conditional_wr && afu_csr_dw_enable_T1[1]; + + for(i=0; i<64; i=i+1) + begin: foo + if(i>31) + j = 1'b1; + else + j = 1'b0; + + casex ({attr[i*3+:3]}) + RW: begin // - Read Write + if(SoftReset) + csr_reg[csr_offset_8B][i] <= default_val[i]; + else if(this_write[j]) + begin + csr_reg[csr_offset_8B][i] <= afu_csr_wrdin_T1[i]; + end + end + + RO: begin // - Read Only + csr_reg[csr_offset_8B][i] <= default_val[i]; // update status + end + + /*RsvdZ*/ RsvdP: begin // - Software must preserve these bits + csr_reg[csr_offset_8B][i] <= default_val[i]; // set default value + end + + endcase + end + end +endtask + +endmodule + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/nlb_gram_sdp.v b/ase/sample_config/intg_xeon_nlb/rtl/nlb_gram_sdp.v new file mode 100755 index 000000000000..7ac302bf077a --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/nlb_gram_sdp.v @@ -0,0 +1,169 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: gram_sdp.v +// Project: NLB AFU +// Description: +// +// *************************************************************************** +// gram_sdp.v: Generic simple dual port RAM with one write port and one read port +// qigang.wang@intel.com Copyright Intel 2008 +// edited by pratik marolia on 3/15/2010 +// Created 2008Oct16 +// referenced Arthur's VHDL version +// +// Generic dual port RAM. This module helps to keep your HDL code architecture +// independent. +// +// Four modes are supported. All of them use synchronous write and differ only +// in read. +// Mode Read Latency write-to-read latency Read behavior +// 0 0 1 asynchronous read +// 1 1 1 Unknown data on simultaneous access +// 2 1 2 Old data on simultaneous access +// 3 2 2 Unknown data on simultaneous access +// +// This module makes use of synthesis tool's automatic RAM recognition feature. +// It can infer distributed as well as block RAM. The type of inferred RAM +// depends on GRAM_STYLE and mode. Mode 0 can only be mapped to +// distributed RAM. Mode 1/2/3 can be mapped to either distributed or block +// RAM. There are three supported values for GRAM_STYLE. +// GRAM_AUTO : Let the tool to decide +// GRAM_BLCK : Use block RAM +// GRAM_DIST : Use distributed RAM +// +// Diagram of GRAM: +// +// +---+ +------------+ +------+ +// raddr --|1/3|______| | | 2/3 | +// |> | | |-----| |-- dout +// +---+ | | |> | +// din __________| RAM | +------+ +// waddr __________| | +// we __________| | +// clk __________|\ | +// |/ | +// +------------+ +// +// You can override parameters to customize RAM. +// + +`include "nlb_cfg_pkg.vh" + +module nlb_gram_sdp (clk, // input clock + we, // input write enable + waddr, // input write address with configurable width + din, // input write data with configurable width + raddr, // input read address with configurable width + dout); // output write data with configurable width + + parameter BUS_SIZE_ADDR =4; // number of bits of address bus + parameter BUS_SIZE_DATA =32; // number of bits of data bus + parameter GRAM_MODE =2'd3; // GRAM read mode + parameter GRAM_STYLE =`GRAM_AUTO; // GRAM_AUTO, GRAM_BLCK, GRAM_DIST + + input clk; + input we; + input [BUS_SIZE_ADDR-1:0] waddr; + input [BUS_SIZE_DATA-1:0] din; + input [BUS_SIZE_ADDR-1:0] raddr; + output [BUS_SIZE_DATA-1:0] dout; + + (* `GRAM_STYLE = GRAM_STYLE *) + reg [BUS_SIZE_DATA-1:0] ram [(2**BUS_SIZE_ADDR)-1:0]; + + reg [BUS_SIZE_ADDR-1:0] raddr_q; + reg [BUS_SIZE_DATA-1:0] dout; + reg [BUS_SIZE_DATA-1:0] ram_dout; + /*synthesis translate_off */ + reg driveX; // simultaneous access detected. Drive X on output + /*synthesis translate_on */ + + always @(posedge clk) + begin + if (we) + ram[waddr]<=din; // synchronous write the RAM + end + generate + case (GRAM_MODE) + 0: begin : GEN_ASYN_READ // asynchronous read + //----------------------------------------------------------------------- + always @(*) dout = ram[raddr]; + end + 1: begin : GEN_SYN_READ // synchronous read + //----------------------------------------------------------------------- + always @(posedge clk) + begin /* synthesis translate_off */ + if(driveX) + dout <= 'hx; + else /* synthesis translate_on */ + dout <= ram[raddr]; + end + /*synthesis translate_off */ + always @(*) + begin + driveX = 0; + + if(raddr==waddr && we) + driveX = 1; + else driveX = 0; + + end /*synthesis translate_on */ + + end + 2: begin : GEN_FALSE_SYN_READ // False synchronous read, buffer output + //----------------------------------------------------------------------- + always @(*) + begin + ram_dout = ram[raddr]; + /*synthesis translate_off */ + if(raddr==waddr && we) + ram_dout = 'hx; /*synthesis translate_on */ + end + always @(posedge clk) + begin + dout <= ram_dout; + end + end + 3: begin : GEN_SYN_READ_BUF_OUTPUT // synchronous read, buffer output + //----------------------------------------------------------------------- + always @(posedge clk) + begin + ram_dout<= ram[raddr]; + dout <= ram_dout; + /*synthesis translate_off */ + if(driveX) + dout <= 'hx; + if(raddr==waddr && we) + driveX <= 1; + else driveX <= 0; /*synthesis translate_on */ + end + end + endcase + endgenerate + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/nlb_lpbk.sv b/ase/sample_config/intg_xeon_nlb/rtl/nlb_lpbk.sv new file mode 100755 index 000000000000..d5b367e1aec4 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/nlb_lpbk.sv @@ -0,0 +1,545 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: nlb_lpbk.v +// Project: NLB_400 AFU +// Compliant with CCI-P spec v0.58 +// Description: top level wrapper for NLB, it instantiates requestor +// & arbiter +// *************************************************************************** +// +// Change Log +// Date Comments +// 7/2/2014 Supports extended 64KB CSR space. Remapped all NLB CSRs +// +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// NLB - Native Loopback test +// ------------------------------------------------------------------------------------------------------------------------------------------------ +// +// This is a reference CCI-S AFU implementation compatible with CCI specification v2.10 +// The purpose of this design is to generate different memory access patterns for validation. +// The test can also be used to measure following performance metrics: +// Bandwidth: 100% Read, 100% Write, 50% Read + 50% Write +// Latency: Read, Write +// +// Block Diagram: +// +// +------------------------------------------------------------------+ +// | +----------+ +---------+ +------------+ | +// | | | Wr | |<---->| Test_lpbk1 | | +// CCI-P |Requestor |<--------->| Arbiter |<--+ +------------+ | +// <----->| | Rd |/Selector|<+ | +------------+ | +// | | |<--------->| | | +->|Test_rdwr | | +// | +----------+ +---------+ | +------------+ | +// | /\ | +------------+ | +// | +--->| Test_SW1 | | +// | +------------+ | +// | | +// | nlb_lpbk | +// +------------------------------------------------------------------+ +// +// +// NLB Revision and feature tracking +//------------------------------------------------------------------------------------------- +// Rev CCI spec Comments +//------------------------------------------------------------------------------------------- +// 1.0 0.9 Uses proprietary memory mapped CSR read mapping +// 1.1 2.0 Device Status Memory Compliant +// 1.2 CCI-P v0.58 Updates to CCI-P spec +// +// CSR Address Map +//------------------------------------------------------------------------------------------ +// Byte Address Attribute Name Width Comments +// 'h0000 RO DFH 64b AFU Device Feature Header +// 'h0008 RO AFU_ID_L 64b AFU ID low 64b +// 'h0010 RO AFU_ID_H 64b AFU ID high 64b +// 'h0018 RsvdZ CSR_DFH_RSVD0 64b Mandatory Reserved 0 +// 'h0020 RO CSR_DFH_RSVD1 64b Mandatory Reserved 1 +// 'h0100 RW CSR_SCRATCHPAD0 64b Scratchpad register 0 +// 'h0108 RW CSR_SCRATCHPAD0 64b Scratchpad register 2 +// 'h0110 RW CSR_AFU_DSM_BASEL 32b Lower 32-bits of AFU DSM base address. The lower 6-bbits are 4x00 since the address is cache aligned. +// 'h0114 RW CSR_AFU_DSM_BASEH 32b Upper 32-bits of AFU DSM base address. +// 'h0120: RW CSR_SRC_ADDR 64b Start physical address for source buffer. All read requests are targetted to this region. +// 'h0128: RW CSR_DST_ADDR 64b Start physical address for destination buffer. All write requests are targetted to this region. +// 'h0130: RW CSR_NUM_LINES 32b Number of cache lines +// 'h0138: RW CSR_CTL 32b Controls test flow, start, stop, force completion +// 'h0140: RW CSR_CFG 32b Configures test parameters +// 'h0148: RW CSR_INACT_THRESH 32b inactivity threshold limit +// 'h0150 RW CSR_INTERRUPT0 32b SW allocates Interrupt APIC ID & Vector to device +// +// +// DSM Offeset Map +// ***CCIP v0.6*** Note DSM is NOT mandatory. User can still define a workspace and use it for DSM. +//------------------------------------------------------------------------------------------ +// Byte Offset Attribute Name Comments +// 0x40 RO DSM_STATUS test status and error register +// +// +// 1 Cacheline = 64B i.e 2^6 Bytes +// Let N be the number of cachelines in the source & destination buffers. Then select CSR_SRC_ADDR & CSR_DEST_ADDR to be 2^(N+6) aligned. +// CSR_NUM_LINES should be less than or equal to N. +// +// CSR_SRC_ADDR: +// [63:N] RW 2^(N+6)MB aligned address points to the start of read buffer +// [N-1:0] RW 'h0 +// +// CSR_DST_ADDR: +// [63:N] RW 2^(N+6)MB aligned address points to the start of write buffer +// [N-1:0] RW 'h0 +// +// CSR_NUM_LINES: +// [31:N] RW 'h0 +// [N-1:0] RW # cache lines to be read/written to. This threshold may be different for each test AFU. IMPORTANT- Ensure that source and destination buffers +// are large enough to accomodate the N cache lines. +// +// Let's assume N=14, then CSR_SRC_ADDR and CSR_DST_ADDR will accept a 2^20, i.e. 1MB aligned addresses. +// +// CSR_SRC_ADDR: +// [31:14] RW 1MB aligned address +// [13:0] RW 'h0 +// +// CSR_DST_ADDR: +// [31:14] RW 1MB aligned address +// [13:0] RW 'h0 +// +// CSR_NUM_LINES: +// [31:16] RW 'h0 +// [15:0] RW # cache lines to be read/written to. This threshold may be different for each test AFU. IMPORTANT- Ensure that source and destination buffers +// are large enough to accomodate the # cache lines. +// +// CSR_CTL: +// [31:3] RW Rsvd +// [2] RW Force test completion. Writes test completion flag and other performance counters to csr_stat. It appears to be like a normal test completion. +// [1] RW Starts test execution. +// [0] RW Active low test Reset. All configuration parameters change to reset defaults. +// +// +// CSR_CFG: +// [29] RW cr_interrupt_testmode - used to test interrupt. Generates an interrupt at end of each test. +// [28] RW cr_interrupt_on_error - send an interrupt when error detected +// [27:20] RW cr_test_cfg -may be used to configure the behavior of each test mode +// [13:12] RW cr_chsel -select virtual channel +// [10:9] RW cr_rdsel -configure read request type. 0- RdLine_S, 1- RdLine_I, 2- RdLine_O, 3- Mixed mode +// [8] RW cr_delay_en -enable random delay insertion between requests +// [6:5] RW cr_multiCL_len - Multi CL length. Valid values are 0,1,3 +// [4:2] RW cr_mode -configures test mode +// [1] RW cr_cont - 1- test rollsover to start address after it reaches the CSR_NUM_LINES count. Such a test terminates only on an error. +// 0- test terminates, updated the status csr when CSR_NUM_LINES count is reached. +// [0] RW cr_wrthru_en -switch between WrLine_I & WrLine_M request types. +// 0- WrLine_M +// 1- WrLine_I +// +// CSR_INACT_THRESHOLD: +// [31:0] RW inactivity threshold limit. The idea is to detect longer duration of stalls during a test run. Inactivity counter will count number of consecutive idle cycles, +// i.e. no requests are sent and no responses are received. If the inactivity count > CSR_INACT_THRESHOLD then it sets the inact_timeout signal. The inactivity counter +// is activated only after test is started by writing 1 to CSR_CTL[1]. +// +// CSR_INTERRUPT0: +// [23:16] RW vector - Interrupt Vector # for the device +// [15:0] RW apic id - Interrupt APIC ID for the device +// +// DSM_STATUS: +// [511:256] RO Error dump from Test Mode +// [255:224] RO end overhead +// [223:192] RO start overhead +// [191:160] RO Number of writes +// [159:128] RO Number of reads +// [127:64] RO Number of clocks +// [63:32] RO test error register +// [31:16] RO Compare and Exchange success Counter +// [15:1] RO Unique id for each dsm status write +// [0] RO test completion flag +// +// High Level Test flow: +//--------------------------------------------------------------- +// 1. SW Reads DFH at AFU offset 0x0 +// 2. SW REad AFU ID at offset 0x8 & 0x10 +// 3. SW initalizes Device Status Memory (DSM) to zero. +// 4. SW writes DSM BASE address to AFU. CSR Write(DSM_BASE_H), CSR Write(DSM_BASE_L) +// 5. SW prepares source & destination memory buffer- this is test specific. +// 4. SW CSR Write(CSR_CTL)=3'h1. This brings the test out of reset and puts it in configuration mode. Configuration is allowed only when CSR_CTL[0]=1 & CSR_CTL[1]=0. +// 5. SW configures the test parameters, i.e. src/dest address, csr_cfg, num lines etc. +// 6. SW CSR Write(CSR_CTL)=3'h3. AFU begins test execution. +// 7. Test completion: +// a. HW completes- When the test completes or detects an error, the HW AFU writes to DSM_STATUS. SW is polling on DSM_STATUS[31:0]==1. +// b. SW forced completion- The SW forces a test completion, CSR Write(CSR_CTL)=3'h7. HW AFU writes to DSM_STATUS. +// The test completion method used depends on the test mode. Some test configuration have no defined end state. When using continuous mode, you must use 7.b. +// +// Test modes: +//--------------------------------------------------------------- +// Test Mode Encoding- CSR_CFG[4:2] #cache line threshold- CSR_NUM_LINES[N-1:0] #cache line threshold for N=14 +// -------------------------------------------------------------------------------------------------------------------------------------- +// 1. LPBK1 3'b000 2^N 14'h3fff +// 2. READ 3'b001 2^N 14'h3fff +// 3. WRITE 3'b010 2^N 14'h3fff +// 4. TRPUT 3'b011 2^N 14'h3fff +// 5. SW1 3'b111 2^N 14'h3ffe +// +// 1. LPBK1: +// This is a memory copy test. AFU copies CSR_NUM_LINES from source buffer to destination buffer. On test completion, the software compares the source and destination buffers. +// +// 2. READ: +// This is a read only test with NO data checking. AFU reads CSR_NUM_LINES starting from CSR_SRC_ADDR. This test is used to stress the read path and +// measure 100% read bandwidth or latency. +// +// 3. WRITE: +// This is a write only test with NO data checking. AFU writes CSR_NUM_LINES starting from CSR_DST_ADDR location. This test is used to stress the write path and +// measure 100% write bandwidth or latency. +// +// 4. TRPUT: +// This test combines the read and write streams. There is NO data checking and no dependency between read & writes. It reads CSR_NUM_LINES starting from CSR_SRC_ADDR location and +// writes CSR_NUM_LINES to CSR_DST_ADDR. It is also used to measure 50% Read + 50% Write bandwdith. +// +// 7. SW1: +// This test measures the full round trip data movement latency between CPU & FPGA. +// The test can be configured to use different 4 different CPU to FPGA messaging methods- +// a. polling from AFU +// b. UMsg without Data +// c. UMsg with Data +// d. CSR Write +// test flow: +// 1. Wait on test_go +// 2. Start timer. Write N cache lines. WrData= {16{32'h0000_0001}} +// 3. Write Fence. +// 4. FPGA -> CPU Message. Write to address N+1. WrData = {{14{32'h0000_0000}},{64{1'b1}}} +// 5. CPU -> FPGA Message. Configure one of the following methods: +// a. Poll on Addr N+1. Expected Data [63:32]==32'hffff_ffff +// b. CSR write to Address 0xB00. Data= Dont Care +// c. UMsg Mode 0 (with data). UMsg ID = 0 +// d. UMsgH Mode 1 (without data). UMsg ID = 0 +// 7. Read N cache lines. Wait for all read completions. +// 6. Stop timer Send test completion. +// + +`default_nettype none +`include "vendor_defines.vh" +import ccip_if_pkg::*; +module nlb_lpbk #(parameter TXHDR_WIDTH=61, RXHDR_WIDTH=18, DATA_WIDTH =512) +( + + // ---------------------------global signals------------------------------------------------- + Clk_400, // in std_logic; Core clock. CCI interface is synchronous to this clock. + SoftReset, // in std_logic; CCI interface reset. The Accelerator IP must use this Reset. ACTIVE HIGH + // ---------------------------IF signals between CCI and AFU -------------------------------- + cp2af_sRxPort, + af2cp_sTxPort +); + + + input Clk_400; // in std_logic; Core clock. CCI interface is synchronous to this clock. + input SoftReset; // in std_logic; CCI interface reset. The Accelerator IP must use this Reset. ACTIVE HIGH + + input t_if_ccip_Rx cp2af_sRxPort; + output t_if_ccip_Tx af2cp_sTxPort; + + localparam PEND_THRESH = 7; + localparam ADDR_LMT = 20; + localparam MDATA = 'd11; + //-------------------------------------------------------- + // Test Modes + //-------------------------------------------------------- + localparam M_LPBK1 = 3'b000; + localparam M_READ = 3'b001; + localparam M_WRITE = 3'b010; + localparam M_TRPUT = 3'b011; + //-------------------------------------------------------- + + wire Clk_400; + wire SoftReset; + + t_if_ccip_Tx af2cp_sTxPort_c; + + + wire [ADDR_LMT-1:0] ab2re_WrAddr; + wire [15:0] ab2re_WrTID; + wire [DATA_WIDTH -1:0] ab2re_WrDin; + wire ab2re_WrFence; + wire ab2re_WrEn; + wire re2ab_WrSent; + wire re2ab_WrAlmFull; + wire [ADDR_LMT-1:0] ab2re_RdAddr; + wire [15:0] ab2re_RdTID; + wire ab2re_RdEn; + wire re2ab_RdSent; + wire re2ab_RdRspValid; + wire re2ab_UMsgValid; + wire re2ab_CfgValid; + wire [15:0] re2ab_RdRsp; + wire [DATA_WIDTH -1:0] re2ab_RdData; + wire re2ab_stallRd; + wire re2ab_WrRspValid; + wire [15:0] re2ab_WrRsp; + wire re2xy_go; + wire [31:0] re2xy_src_addr; + wire [31:0] re2xy_dst_addr; + wire [31:0] re2xy_NumLines; + wire [31:0] re2xy_stride; + wire re2xy_Cont,re2xy_wrdin_msb; + wire [7:0] re2xy_test_cfg; + wire [2:0] re2ab_Mode; + wire ab2re_TestCmp; + (* `KEEP_WIRE *) wire [255:0] ab2re_ErrorInfo; + wire ab2re_ErrorValid; + + wire test_SoftReset; + wire [63:0] cr2re_src_address; + wire [63:0] cr2re_dst_address; + wire [31:0] cr2re_num_lines; + wire [31:0] cr2re_inact_thresh; + wire [31:0] cr2re_interrupt0; + wire [63:0] cr2re_cfg; + wire [31:0] cr2re_ctl; + wire [31:0] cr2re_stride; + wire [63:0] cr2re_dsm_base; + wire cr2re_dsm_base_valid; + wire re2cr_wrlock_n; + wire cr2s1_csr_write; + + logic ab2re_RdSop; + logic [1:0] ab2re_WrLen; + logic [1:0] ab2re_RdLen; + logic ab2re_WrSop; + + logic re2ab_RdRspFormat; + logic [1:0] re2ab_RdRspCLnum; + logic re2ab_WrRspFormat; + logic [1:0] re2ab_WrRspCLnum; + logic [1:0] re2xy_multiCL_len; + + logic [31:0] re2cr_num_reads; + logic [31:0] re2cr_num_writes; + logic [31:0] re2cr_num_Rdpend; + logic [31:0] re2cr_num_Wrpend; + logic [31:0] re2cr_error; + + reg SoftReset_q=1'b1; + always @(posedge Clk_400) + begin + SoftReset_q <= SoftReset; + end + +requestor #(.PEND_THRESH(PEND_THRESH), + .ADDR_LMT (ADDR_LMT), + .TXHDR_WIDTH(TXHDR_WIDTH), + .RXHDR_WIDTH(RXHDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH ) + ) +inst_requestor( + + +// ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + SoftReset_q , // in std_logic; -- Use SPARINGLY only for control +// ---------------------------CCI IF signals between CCI and requestor --------------------- + + af2cp_sTxPort_c, + cp2af_sRxPort, + + cr2re_src_address, + cr2re_dst_address, + cr2re_num_lines, + cr2re_inact_thresh, + cr2re_interrupt0, + cr2re_cfg, + cr2re_ctl, + cr2re_stride, + cr2re_dsm_base, + cr2re_dsm_base_valid, + + ab2re_WrAddr, // [ADDR_LMT-1:0] arbiter: Writes are guaranteed to be accepted + ab2re_WrTID, // [15:0] arbiter: meta data + ab2re_WrDin, // [DATA_WIDTH -1:0] arbiter: Cache line data + ab2re_WrFence, // arbiter: write fence + ab2re_WrEn, // arbiter: write enable + re2ab_WrSent, // arbiter: write issued + re2ab_WrAlmFull, // arbiter: write fifo almost full + + ab2re_RdAddr, // [ADDR_LMT-1:0] arbiter: Reads may yield to writes + ab2re_RdTID, // [15:0] arbiter: meta data + ab2re_RdEn, // arbiter: read enable + re2ab_RdSent, // arbiter: read issued + + re2ab_RdRspValid, // arbiter: read response valid + re2ab_UMsgValid, // arbiter: UMsg valid + re2ab_CfgValid, // arbiter: Cfg Valid + re2ab_RdRsp, // [ADDR_LMT-1:0] arbiter: read response header + re2ab_RdData, // [DATA_WIDTH -1:0] arbiter: read data + re2ab_stallRd, // arbiter: stall read requests FOR LPBK1 + + re2ab_WrRspValid, // arbiter: write response valid + re2ab_WrRsp, // [ADDR_LMT-1:0] arbiter: write response header + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_stride, // [31:0] requestor: stride value + re2xy_Cont, // requestor: continuous mode + re2xy_wrdin_msb, // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + re2xy_src_addr, // [31:0] requestor: src address + re2xy_dst_addr, // [31:0] requestor: destination address + re2xy_test_cfg, // [7:0] requestor: 8-bit test cfg register. + re2ab_Mode, // [2:0] requestor: test mode + + ab2re_TestCmp, // arbiter: Test completion flag + ab2re_ErrorInfo, // [255:0] arbiter: error information + ab2re_ErrorValid, // arbiter: test has detected an error + test_SoftReset, // requestor: rest the app + re2cr_wrlock_n, // requestor: when low, block csr writes + + ab2re_RdLen, + ab2re_RdSop, + ab2re_WrLen, + ab2re_WrSop, + + re2ab_RdRspFormat, + re2ab_RdRspCLnum, + re2ab_WrRspFormat, + re2ab_WrRspCLnum, + re2xy_multiCL_len, + + re2cr_num_reads, + re2cr_num_writes, + re2cr_num_Rdpend, + re2cr_num_Wrpend, + re2cr_error +); + +arbiter #(.PEND_THRESH(PEND_THRESH), + .ADDR_LMT(ADDR_LMT), + .MDATA (MDATA) + ) +inst_arbiter ( + +// ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + + ab2re_WrAddr, // [ADDR_LMT-1:0] arbiter: write address + ab2re_WrTID, // [15:0] arbiter: meta data + ab2re_WrDin, // [DATA_WIDTH -1:0] arbiter: Cache line data + ab2re_WrFence, // arbiter: write fence + ab2re_WrEn, // arbiter: write enable + re2ab_WrSent, // arbiter: write issued + re2ab_WrAlmFull, // arbiter: write fifo almost full + + ab2re_RdAddr, // [ADDR_LMT-1:0] arbiter: Reads may yield to writes + ab2re_RdTID, // [15:0] arbiter: meta data + ab2re_RdEn, // arbiter: read enable + re2ab_RdSent, // arbiter: read issued + + re2ab_RdRspValid, // arbiter: read response valid + re2ab_UMsgValid, // arbiter: UMsg valid + re2ab_CfgValid, // arbiter: Cfg Valid + re2ab_RdRsp, // [ADDR_LMT-1:0] arbiter: read response header + re2ab_RdData, // [DATA_WIDTH -1:0] arbiter: read data + re2ab_stallRd, // arbiter: stall read requests FOR LPBK1 + + re2ab_WrRspValid, // arbiter: write response valid + re2ab_WrRsp, // [ADDR_LMT-1:0] arbiter: write response header + re2xy_go, // requestor: start the test + re2xy_src_addr, // [31:0] requestor: src address + re2xy_dst_addr, // [31:0] requestor: destination address + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_stride, // [31:0] requestor: stride value + re2xy_Cont, // requestor: continuous mode + re2xy_wrdin_msb, // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + re2xy_test_cfg, // [7:0] requestor: 8-bit test cfg register. + re2ab_Mode, // [2:0] requestor: test mode + ab2re_TestCmp, // arbiter: Test completion flag + ab2re_ErrorInfo, // [255:0] arbiter: error information + ab2re_ErrorValid, // arbiter: test has detected an error + cr2s1_csr_write, + test_SoftReset, // requestor: rest the app + + ab2re_RdLen, + ab2re_RdSop, + ab2re_WrLen, + ab2re_WrSop, + + re2ab_RdRspFormat, + re2ab_RdRspCLnum, + re2ab_WrRspFormat, + re2ab_WrRspCLnum, + re2xy_multiCL_len +); + +t_ccip_c0_ReqMmioHdr cp2cr_MmioHdr; +logic cp2cr_MmioWrEn; +logic cp2cr_MmioRdEn; +t_ccip_mmioData cp2cr_MmioDin; +t_ccip_mmioData cr2af_MmioDout; +logic cr2af_MmioDout_v; +t_ccip_c2_RspMmioHdr cr2af_MmioHdr; + +always_comb +begin + cp2cr_MmioHdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr); + cp2cr_MmioWrEn = cp2af_sRxPort.c0.mmioWrValid; + cp2cr_MmioRdEn = cp2af_sRxPort.c0.mmioRdValid; + cp2cr_MmioDin = cp2af_sRxPort.c0.data[CCIP_MMIODATA_WIDTH-1:0]; + + af2cp_sTxPort = af2cp_sTxPort_c; + // Override the C2 channel + af2cp_sTxPort.c2.hdr = cr2af_MmioHdr; + af2cp_sTxPort.c2.data = cr2af_MmioDout; + af2cp_sTxPort.c2.mmioRdValid = cr2af_MmioDout_v; +end + +nlb_csr # (.CCIP_VERSION_NUMBER(CCIP_VERSION_NUMBER)) +inst_nlb_csr ( + Clk_400, + SoftReset_q, // ACTIVE HIGH soft reset + re2cr_wrlock_n, + + // MMIO Requests + cp2cr_MmioHdr, + cp2cr_MmioDin, + cp2cr_MmioWrEn, + cp2cr_MmioRdEn, + + // MMIO Response + cr2af_MmioHdr, + cr2af_MmioDout, + cr2af_MmioDout_v, + + cr2re_src_address, + cr2re_dst_address, + cr2re_num_lines, + cr2re_inact_thresh, + cr2re_interrupt0, + cr2re_cfg, + cr2re_ctl, + cr2re_stride, + cr2re_dsm_base, + cr2re_dsm_base_valid, + cr2s1_csr_write, + + re2cr_num_reads, + re2cr_num_writes, + re2cr_num_Rdpend, + re2cr_num_Wrpend, + re2cr_error +); + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/requestor.sv b/ase/sample_config/intg_xeon_nlb/rtl/requestor.sv new file mode 100755 index 000000000000..35782b8ce05f --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/requestor.sv @@ -0,0 +1,987 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: requestor.v +// Project: NLB AFU v1.1 +// Compliant with CCI v2.1 +// Description: accepts requests from arbiter and formats it per cci +// spec. It also implements the flow control. +// *************************************************************************** +// +// The requestor accepts the address index from the arbiter, appends that to the source/destination base address and +// sends out the request to the CCI module. It arbitrates between the read and the write requests, peforms the flow control, +// implements all the CSRs for source address, destination address, status address, wrthru enable, start and stop the test. +// +// +// +`default_nettype none +import ccip_if_pkg::*; +module requestor #(parameter PEND_THRESH=1, ADDR_LMT=20, TXHDR_WIDTH=61, RXHDR_WIDTH=18, DATA_WIDTH=512) +( + + // ---------------------------global signals------------------------------------------------- + Clk_400, // in std_logic; -- Core clock + SoftReset, // in std_logic; -- Use SPARINGLY only for control. ACTIVE HIGH + // ---------------------------CCI IF signals between CCI and requestor --------------------- + af2cp_sTxPort, + cp2af_sRxPort, + + cr2re_src_address, + cr2re_dst_address, + cr2re_num_lines, + cr2re_inact_thresh, + cr2re_interrupt0, + cr2re_cfg, + cr2re_ctl, + cr2re_stride, + cr2re_dsm_base, + cr2re_dsm_base_valid, + + ab2re_WrAddr, // [ADDR_LMT-1:0] arbiter: Writes are guaranteed to be accepted + ab2re_WrTID, // [15:0] arbiter: meta data + ab2re_WrDin, // [511:0] arbiter: Cache line data + ab2re_WrFence, // arbiter: write fence. + ab2re_WrEn, // arbiter: write enable + re2ab_WrSent, // arbiter: can accept writes. Qualify with write enable + re2ab_WrAlmFull, // arbiter: write fifo almost full + + ab2re_RdAddr, // [ADDR_LMT-1:0] arbiter: Reads may yield to writes + ab2re_RdTID, // [15:0] arbiter: meta data + ab2re_RdEn, // arbiter: read enable + re2ab_RdSent, // arbiter: read issued + + re2ab_RdRspValid, // arbiter: read response valid + re2ab_UMsgValid, // arbiter: UMsg valid + re2ab_CfgValid, // arbiter: Cfg Valid + re2ab_RdRsp, // [ADDR_LMT-1:0] arbiter: read response header + re2ab_RdData, // [511:0] arbiter: read data + re2ab_stallRd, // arbiter: stall read requests FOR LPBK1 + + re2ab_WrRspValid, // arbiter: write response valid + re2ab_WrRsp, // [ADDR_LMT-1:0] arbiter: write response header + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_stride, // [31:0] requestor: stride value + re2xy_Cont, // requestor: continuous mode + re2xy_wrdin_msb, // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + re2xy_src_addr, // [31:0] requestor: src address + re2xy_dst_addr, // [31:0] requestor: destination address + re2xy_test_cfg, // [7:0] requestor: 8-bit test cfg register. + re2ab_Mode, // [2:0] requestor: test mode + + ab2re_TestCmp, // arbiter: Test completion flag + ab2re_ErrorInfo, // [255:0] arbiter: error information + ab2re_ErrorValid, // arbiter: test has detected an error + test_Reset_n, // requestor: rest the app + re2cr_wrlock_n, // requestor: when low, block csr writes + + ab2re_RdLen, + ab2re_RdSop, + ab2re_WrLen, + ab2re_WrSop, + + re2ab_RdRspFormat, + re2ab_RdRspCLnum, + re2ab_WrRspFormat, + re2ab_WrRspCLnum, + re2xy_multiCL_len, + + re2cr_num_reads, + re2cr_num_writes, + re2cr_num_Rdpend, + re2cr_num_Wrpend, + re2cr_error +); + //-------------------------------------------------------------------------------------------------------------- + input logic Clk_400; // ccip_intf: Clk_400 + input logic SoftReset; // ccip_intf: system SoftReset + + output t_if_ccip_Tx af2cp_sTxPort; + input t_if_ccip_Rx cp2af_sRxPort; + + input t_ccip_mmioData cr2re_src_address; + input t_ccip_mmioData cr2re_dst_address; + input logic [31:0] cr2re_num_lines; + input logic [31:0] cr2re_inact_thresh; + input logic [31:0] cr2re_interrupt0; + input t_ccip_mmioData cr2re_cfg; + input logic [31:0] cr2re_ctl; + input logic [31:0] cr2re_stride; + input t_ccip_mmioData cr2re_dsm_base; + input logic cr2re_dsm_base_valid; + + input logic [ADDR_LMT-1:0] ab2re_WrAddr; // [ADDR_LMT-1:0] arbiter: Writes are guaranteed to be accepted + input t_ccip_mdata ab2re_WrTID; // [15:0] arbiter: meta data + input t_ccip_clData ab2re_WrDin; // [511:0] arbiter: Cache line data + input logic ab2re_WrFence; // arbiter: write fence + input logic ab2re_WrEn; // arbiter: write enable + output logic re2ab_WrSent; // arbiter: write issued + output logic re2ab_WrAlmFull; // arbiter: write fifo almost full + + input logic [ADDR_LMT-1:0] ab2re_RdAddr; // [ADDR_LMT-1:0] arbiter: Reads may yield to writes + input t_ccip_mdata ab2re_RdTID; // [15:0] arbiter: meta data + input logic ab2re_RdEn; // arbiter: read enable + output logic re2ab_RdSent; // arbiter: read issued + + output logic re2ab_RdRspValid; // arbiter: read response valid + output logic re2ab_UMsgValid; // arbiter: UMsg valid + output logic re2ab_CfgValid; // arbiter: Cfg valid + output t_ccip_mdata re2ab_RdRsp; // [15:0] arbiter: read response header + output t_ccip_clData re2ab_RdData; // [511:0] arbiter: read data + output logic re2ab_stallRd; // arbiter: stall read requests FOR LPBK1 + + output logic re2ab_WrRspValid; // arbiter: write response valid + output t_ccip_mdata re2ab_WrRsp; // [15:0] arbiter: write response header + + (* maxfan=1 *)output logic re2xy_go; // requestor: start of frame recvd + output logic [31:0] re2xy_NumLines; // [31:0] requestor: number of cache lines + output logic [31:0] re2xy_stride; // [31:0] requestor: stride value + output logic re2xy_Cont; // requestor: continuous mode + output logic [31:0] re2xy_src_addr; // [31:0] requestor: src address + output logic [31:0] re2xy_dst_addr; // [31:0] requestor: destination address + output logic [7:0] re2xy_test_cfg; // [7:0] requestor: 8-bit test cfg register. + output logic [2:0] re2ab_Mode; // [2:0] requestor: test mode + input logic ab2re_TestCmp; // arbiter: Test completion flag + input logic [255:0] ab2re_ErrorInfo; // [255:0] arbiter: error information + input logic ab2re_ErrorValid; // arbiter: test has detected an error + output logic re2xy_wrdin_msb; // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + output logic test_Reset_n; + output logic re2cr_wrlock_n; + + input logic [1:0] ab2re_RdLen; + input logic ab2re_RdSop; + input logic [1:0] ab2re_WrLen; + input logic ab2re_WrSop; + output logic re2ab_RdRspFormat; + output logic [1:0] re2ab_RdRspCLnum; + output logic re2ab_WrRspFormat; + output logic [1:0] re2ab_WrRspCLnum; + output logic [1:0] re2xy_multiCL_len; + + output logic [31:0] re2cr_num_Rdpend; + output logic [31:0] re2cr_num_Wrpend; + output logic [31:0] re2cr_num_reads; + output logic [31:0] re2cr_num_writes; + output logic [31:0] re2cr_error; + + //---------------------------------------------------------------------------------------------------------------------- + //--------------------------------------------------------- + // Default Values ****** May be MODIFIED ******* + //--------------------------------------------------------- + localparam DEF_SRC_ADDR = 32'h0400_0000; // Read data starting from here. Cache aligned Address + localparam DEF_DST_ADDR = 32'h0500_0000; // Copy data to here. Cache aligned Address + localparam DEF_DSM_BASE = 32'h04ff_ffff; // default status address + + + //---------------------------------------------------------------------------------- + // Device Status Memory (DSM) Address Map ***** DO NOT MODIFY ***** + // This is a shared memory region where AFU writes and SW reads from. It is used for sharing status. + // Physical address = value at CSR_AFU_DSM_BASE + Byte offset + //---------------------------------------------------------------------------------- + // Byte Offset Attribute Width Comments + localparam DSM_STATUS = 32'h40; // RO 512b test status and error info + + //---------------------------------------------------------------------------------------------------------------------- + + reg [31:0] ErrorVector; + reg [31:0] Num_Reads; // Number of reads performed + reg [31:0] Num_Writes; // Number of writes performed + reg [19:0] Num_ticks_low, Num_ticks_high; + reg [31:0] Num_C0stall; // Number of clocks for which Channel0 was throttled + reg [31:0] Num_C1stall; // Number of clocks for which channel1 was throttled + reg signed [31:0] Num_RdCredits; // For LPBK1: number of read credits + reg RdHdr_valid; + reg WrHdr_valid_T1, WrHdr_valid_T2, WrHdr_valid_T3 , WrHdr_valid_T4; + reg [31:0] wrfifo_addr; + t_ccip_clData wrfifo_data; + reg txFifo_RdAck; + wire txFifo_Dout_v; + reg tx_c0_req_valid, tx_c1_req_valid; + reg rx_c0_resp_valid, rx_c1_resp_valid; + + t_if_ccip_Rx cp2af_sRxPort_T1; + + reg re2ab_CfgValid_d; + reg status_write; + reg interrupt_sent; + reg send_interrupt; + + reg [31:0] inact_cnt; + reg inact_timeout; + reg [5:0] delay_lfsr; + reg [1:0] delay_lfsr1,rnd_ch_sel; + reg [31:0] cr_inact_thresh; + reg penalty_start_f; + reg [7:0] penalty_start; + reg [7:0] penalty_end; +(* dont_merge, maxfan=256 *) reg dsm_status_wren_a; +(* dont_merge, maxfan=256 *) reg dsm_status_wren_b; +(* dont_merge, maxfan=256 *) reg dsm_status_wren_c; + t_ccip_c0_req rdreq_type; + t_ccip_c0_req rnd_rdreq_type; + reg rnd_rdreq_sel; + + integer i; + t_ccip_mmioData cr_dsm_base; // a00h, a04h - DSM base address + t_ccip_mmioData cr_src_address; // a20h - source buffer address + t_ccip_mmioData cr_dst_address; // a24h - destn buffer address + reg [31:0] cr_num_lines; // a28h - Number of cache lines + reg [31:0] cr_stride; //stride value + reg [1:0] cr_multiCL_len; + reg [31:0] cr_ctl = 0; // a2ch - control register to start and stop the test + reg cr_wrlineI_en; // a34h - [0] : test configuration- wrlineI_en + reg cr_wrpushI_en; // a34h - [16] : test configuration- wrlineI_en + reg cr_cont; // a34h - [1] : repeats the test sequence, NO end condition + reg cr_wrdin_msb; // + reg [2:0] cr_mode; // a34h - [4:2] : selects test mode + reg cr_delay_en; // a34h - [8] : use start delay + reg [1:0] cr_rdsel, cr_rdsel_q; // a34h - [10:9] : read request type + reg [7:0] cr_test_cfg; // a34h - [27:0] : configuration within a selected test mode + reg [31:0] cr_interrupt0; // a3ch - SW allocates apic id & interrupt vector + reg cr_interrupt_testmode; + reg cr_interrupt_on_error; + reg [1:0] rnd_ch_type,rnd_ch_type_q; + reg [2:0] rd_ch_type,cr_rd_chsel,cr_rd_chsel_q; + reg [2:0] wr_ch_type,cr_wr_chsel,cr_wr_chsel_q; + reg [41:0] ds_stat_address; // 040h - test status is written to this address + +(* maxfan=512 *) wire txFifo_Full; + wire txFifo_AlmFull; + wire txFifo_WrEn = (ab2re_WrEn| ab2re_WrFence) && ~txFifo_Full; + wire [15:0] txFifo_WrTID; + reg [ADDR_LMT-1:0] txFifo_WrAddr,txFifo_WrAddr_q; + wire txFifo_WrFence; + wire txFifo_WrSop; + wire [1:0] txFifo_WrLen; + + logic [41:0] RdAddr; + logic RdHdr_valid_q; + logic [1:0] ab2re_RdLen_q; + logic ab2re_RdEn_q; + logic [15:0] ab2re_RdTID_q; + logic [41:0] WrAddr; + + t_ccip_c1_req wrreq_type; + t_ccip_clData txFifo_WrDin; + t_ccip_clData WrData_dsm; + + reg test_go; + reg sop; + + wire rnd_delay = ~cr_delay_en || (delay_lfsr[0] || delay_lfsr[2] || delay_lfsr[3]); + wire tx_errorValid = ErrorVector!=0; + reg [14:0] dsm_number=0; + + logic [15:0] txFifo_WrTID_q,txFifo_WrTID_qq; + logic txFifo_WrFence_q, txFifo_WrFence_qq; + logic txFifo_WrSop_q, txFifo_WrSop_qq; + logic [1:0] txFifo_WrLen_q, txFifo_WrLen_qq; + logic txFifo_cxEn_q; + logic [2:0] txFifo_cxQword_q; + t_ccip_clData txFifo_WrDin_q , txFifo_WrDin_qq; + + logic test_stop; + logic WrFence_sent; + logic read_only_test; + logic test_cmplt; + logic [1:0] tx_rd_req_len; + logic rx_wr_resp_fmt; + logic [1:0] rx_wr_resp_cl_num; + + logic tx_c0_req_valid_q; + logic rx_c0_resp_valid_q; + logic tx_c1_req_valid_q; + logic rx_c1_resp_valid_q; + + (* noprune *) logic [2:0] num_rd_sent; + (* maxfan=1 *) logic [2:0] num_wr_recvd; + (* noprune *) logic [11:0] Num_WrPend; + (* noprune *) logic [11:0] Num_RdPend; + + // NLB supports 64MB data transfers + // RdAddr computation takes one cycle :- Delay Rd valid generation from req to upstream by 1 clk + // WrAddr computation takes two cycle :- Delay Wr valid popped from FIFO by 1 cycle before fwd'ing to upstream + always @(posedge Clk_400) + begin + RdAddr <= (cr_src_address[41:0] + ab2re_RdAddr[19:0]); + ab2re_RdLen_q <= ab2re_RdLen; + ab2re_RdTID_q <= ab2re_RdTID; + ab2re_RdEn_q <= ab2re_RdEn; + RdHdr_valid_q <= RdHdr_valid; + + txFifo_WrAddr_q <= txFifo_WrAddr; + WrAddr <= {(cr_dst_address[41:0] + txFifo_WrAddr_q[19:0])}; + txFifo_WrLen_q <= txFifo_WrLen; + txFifo_WrSop_q <= txFifo_WrSop; + txFifo_WrFence_q <= txFifo_WrFence; + txFifo_WrDin_q <= txFifo_WrDin; + txFifo_WrTID_q <= txFifo_WrTID; + txFifo_WrLen_qq <= txFifo_WrLen_q; + txFifo_WrSop_qq <= txFifo_WrSop_q; + txFifo_WrFence_qq <= txFifo_WrFence_q; + txFifo_WrDin_qq <= txFifo_WrDin_q; + txFifo_WrTID_qq <= txFifo_WrTID_q; + end + + always @(posedge Clk_400) + begin + re2cr_wrlock_n <= cr_ctl[0] & ~cr_ctl[1]; + test_Reset_n <= cr_ctl[0]; // Clears all the states. Either is one then test is out of Reset. + test_go <= cr_ctl[1]; // When 0, it allows reconfiguration of test parameters. + re2ab_Mode <= cr_mode; + re2xy_test_cfg <= cr_test_cfg; + re2xy_NumLines <= cr_num_lines; + re2xy_stride <= cr_stride; + re2xy_multiCL_len <= cr_multiCL_len; + re2xy_Cont <= cr_cont; + re2xy_wrdin_msb <= cr_wrdin_msb; + re2xy_src_addr <= cr_src_address[31:0]; + re2xy_dst_addr <= cr_dst_address[31:0]; + end + + always_comb + begin + re2ab_RdRspFormat=0; + re2ab_WrAlmFull = txFifo_AlmFull; + re2ab_WrSent = !txFifo_Full; + re2ab_RdRspValid = cp2af_sRxPort_T1.c0.rspValid && (cp2af_sRxPort_T1.c0.hdr.resp_type==eRSP_RDLINE); + re2ab_UMsgValid = cp2af_sRxPort_T1.c0.rspValid && cp2af_sRxPort_T1.c0.hdr.resp_type==eRSP_UMSG; + re2ab_RdRsp = cp2af_sRxPort_T1.c0.hdr.mdata[15:0]; + re2ab_RdRspCLnum = cp2af_sRxPort_T1.c0.hdr.cl_num[1:0]; + re2ab_RdData = cp2af_sRxPort_T1.c0.data; + re2ab_WrRspValid = cp2af_sRxPort_T1.c1.rspValid && cp2af_sRxPort_T1.c1.hdr.resp_type==eRSP_WRLINE; + re2ab_WrRsp = cp2af_sRxPort_T1.c1.hdr.mdata[15:0]; + re2ab_WrRspFormat= cp2af_sRxPort_T1.c1.hdr.format; + re2ab_WrRspCLnum = cp2af_sRxPort_T1.c1.hdr.cl_num[1:0]; + re2ab_CfgValid = re2ab_CfgValid_d; + sop = txFifo_WrFence_qq ? 0 : txFifo_WrSop_qq; + + end + + always @(*) + begin + cr_ctl = cr2re_ctl; + cr_stride = cr2re_stride; + cr_dsm_base = cr2re_dsm_base; + cr_src_address = cr2re_src_address; + cr_dst_address = cr2re_dst_address; + cr_num_lines = cr2re_num_lines; + cr_inact_thresh = cr2re_inact_thresh; + cr_interrupt0 = cr2re_interrupt0; + + cr_wrlineI_en = cr2re_cfg[0]; + cr_cont = cr2re_cfg[1]; + cr_mode = cr2re_cfg[4:2]; + cr_multiCL_len = cr2re_cfg[6:5]; + cr_delay_en = 1'b0; + cr_rdsel = cr2re_cfg[10:9]; + cr_test_cfg = cr2re_cfg[27:20]; + cr_interrupt_on_error = cr2re_cfg[28]; + cr_interrupt_testmode = cr2re_cfg[29]; + cr_rd_chsel = cr2re_cfg[14:12]; + cr_wrdin_msb = cr2re_cfg[15]; + cr_wrpushI_en = cr2re_cfg[16]; + cr_wr_chsel = cr2re_cfg[19:17]; + + + end + + always @(posedge Clk_400) + begin + re2cr_num_Rdpend <= 0; + re2cr_num_Wrpend <= 0; + + // So, Max pending write transactions that requestor needs to track = 256 + // So, there could be maximum of 256 * 4 = 1024 reqs that are tracked as Num_Wr/Rd_pend + // Num_Wr/Rd_Pend[11] indicates an underflow -- recorded as unexpected WrRsp Err + // Num_Wr/Rd_Pend[10:9] == 2'b11 indicates Test has to be stalled to prevent an overflow + + re2cr_num_Rdpend[11:0] <= Num_RdPend[11:0]; + re2cr_num_Wrpend[11:0] <= Num_WrPend[11:0]; + re2cr_num_reads <= Num_Reads; + re2cr_num_writes <= Num_Writes; + re2cr_error <= ErrorVector; + ds_stat_address <= dsm_offset2addr(DSM_STATUS,cr_dsm_base); + cr_rdsel_q <= cr_rdsel; + cr_rd_chsel_q <= cr_rd_chsel; + cr_wr_chsel_q <= cr_wr_chsel; + delay_lfsr <= {delay_lfsr[4:0], (delay_lfsr[5] ^ delay_lfsr[4]) }; + delay_lfsr1 <= {delay_lfsr1[0], (delay_lfsr1[0] ^ delay_lfsr1[1]) }; + rnd_ch_sel <= delay_lfsr1; + case(rnd_ch_sel) + 2'h1: rnd_ch_type <= eVC_VL0; + 2'h2: rnd_ch_type <= eVC_VH0; + 2'h3: rnd_ch_type <= eVC_VH1; + default: rnd_ch_type <=eVC_VL0; + endcase + + case(cr_rd_chsel_q) + 3'h0: rd_ch_type <= eVC_VA; + 3'h1: rd_ch_type <= eVC_VL0; + 3'h2: rd_ch_type <= eVC_VH0; + 3'h3: rd_ch_type <= eVC_VH1; + 3'h4: rd_ch_type <= rnd_ch_type; + default: rd_ch_type <= eVC_VA; + endcase + + case(cr_wr_chsel_q) + 3'h0: wr_ch_type <= eVC_VA; + 3'h1: wr_ch_type <= eVC_VL0; + 3'h2: wr_ch_type <= eVC_VH0; + 3'h3: wr_ch_type <= eVC_VH1; + 3'h4: wr_ch_type <= rnd_ch_type; + default: wr_ch_type <= eVC_VA; + endcase + + case(cr_rdsel_q) + 2'h0: rdreq_type <= eREQ_RDLINE_S; + 2'h1: rdreq_type <= eREQ_RDLINE_I; + 2'h2: rdreq_type <= eREQ_RDLINE_I; + 2'h3: rdreq_type <= rnd_rdreq_type; + endcase + rnd_rdreq_sel <= 0; + if(rnd_rdreq_sel) + rnd_rdreq_type <= eREQ_RDLINE_I; + else + rnd_rdreq_type <= eREQ_RDLINE_S; + + if(test_go ) + re2xy_go <= 1'b1; + if(status_write) + re2xy_go <= 1'b0; + + send_interrupt <= status_write && ((cr_interrupt_on_error & tx_errorValid) | cr_interrupt_testmode); + dsm_status_wren_a<= ab2re_TestCmp | test_stop; // Update Status upon test completion + dsm_status_wren_b<= ab2re_TestCmp | test_stop; // Update Status upon test completion + dsm_status_wren_c<= ab2re_TestCmp | test_stop; // Update Status upon test completion + + // Wait for multi CL request to complete + // If Error detected or SW forced test termination + // Make sure that multiCL request is completed before sending out DSM Write + + if (re2ab_Mode[2:0] == 3'b001) + read_only_test <= 1; + + if (cr_ctl[2] | tx_errorValid) + test_cmplt <= 1; + + if (test_stop == 0) + test_stop <= test_cmplt & (read_only_test | (!(|txFifo_WrLen_qq) & WrHdr_valid_T4)); + + WrData_dsm <={ ab2re_ErrorInfo, // [511:256] upper half cache line + 24'h00_0000,penalty_end, // [255:224] test end overhead in # clks + 24'h00_0000,penalty_start, // [223:192] test start overhead in # clks + Num_Writes, // [191:160] Total number of Writes sent / Total Num CX sent + Num_Reads, // [159:128] Total number of Reads sent + 24'h00_0000,Num_ticks_high, Num_ticks_low, // [127:64] number of clks + ErrorVector, // [63:32] errors detected + 16'h0000, dsm_number, // [15:1] unique id for each dsm status write + 1'h1 // [0] test completion flag + }; + + + //Tx Path + //-------------------------------------------------------------------------- + af2cp_sTxPort.c1.hdr <= 0; + af2cp_sTxPort.c1.valid <= 0; + af2cp_sTxPort.c0.hdr <= 0; + af2cp_sTxPort.c0.valid <= 0; + + af2cp_sTxPort.c1.data[511:256] <= dsm_status_wren_a ? WrData_dsm[511:256] : txFifo_WrDin_qq[511:256]; + af2cp_sTxPort.c1.data[255:0] <= dsm_status_wren_b ? WrData_dsm[255:0] : txFifo_WrDin_qq[255:0]; + + // Channel 1 + if ( send_interrupt + & !interrupt_sent + & !cp2af_sRxPort_T1.c1TxAlmFull + ) + begin + interrupt_sent <= 1'b1; + af2cp_sTxPort.c1.hdr.vc_sel <= t_ccip_vc'(wr_ch_type); + af2cp_sTxPort.c1.hdr.req_type <= eREQ_INTR; + af2cp_sTxPort.c1.hdr.address[31:0] <= cr_interrupt0; + af2cp_sTxPort.c1.hdr.mdata[15:0] <= 16'hfffc; + af2cp_sTxPort.c1.valid <= 1'b1; + end + + else if (re2xy_go & rnd_delay ) + begin + if( dsm_status_wren_c // Write Fence + & !cp2af_sRxPort_T1.c1TxAlmFull + & !WrFence_sent + ) + begin //----------------------------------- + if(WrFence_sent==0 ) + begin + af2cp_sTxPort.c1.valid <= 1'b1; + end + WrFence_sent <= 1'b1; + af2cp_sTxPort.c1.hdr.vc_sel <= t_ccip_vc'(wr_ch_type); + af2cp_sTxPort.c1.hdr.req_type <= eREQ_WRFENCE; + af2cp_sTxPort.c1.hdr.address[41:0] <= '0; + af2cp_sTxPort.c1.hdr.mdata[15:0] <= '0; + af2cp_sTxPort.c1.hdr.sop <= 1'b0; + af2cp_sTxPort.c1.hdr.cl_len <= eCL_LEN_1; + end + + if( // Write DSM Status + !cp2af_sRxPort_T1.c1TxAlmFull + & WrFence_sent + ) + begin //----------------------------------- + if(status_write==0) + begin + dsm_number <= dsm_number + 1'b1; + af2cp_sTxPort.c1.valid <= 1'b1; + end + status_write <= 1'b1; + af2cp_sTxPort.c1.hdr.vc_sel <= t_ccip_vc'(wr_ch_type); + af2cp_sTxPort.c1.hdr.req_type <= eREQ_WRLINE_M; + af2cp_sTxPort.c1.hdr.address[41:0] <= ds_stat_address; + af2cp_sTxPort.c1.hdr.mdata[15:0] <= 16'hffff; + af2cp_sTxPort.c1.hdr.sop <= 1'b1; // DSM Write is single CL write + af2cp_sTxPort.c1.hdr.cl_len <= eCL_LEN_1; + end + + else if( WrHdr_valid_T4 & !test_stop ) // Write to Destination Workspace + begin //------------------------------------- + af2cp_sTxPort.c1.hdr.vc_sel <= sop? t_ccip_vc'(wr_ch_type) : af2cp_sTxPort.c1.hdr.vc_sel ; //for multi-cl write dont randomise vc within a packet + af2cp_sTxPort.c1.hdr.req_type <= wrreq_type; + af2cp_sTxPort.c1.hdr.address[41:0] <= WrAddr; + af2cp_sTxPort.c1.hdr.mdata[15:0] <= txFifo_WrTID_qq; + af2cp_sTxPort.c1.hdr.sop <= sop; + af2cp_sTxPort.c1.hdr.cl_len <= t_ccip_clLen'(txFifo_WrLen_qq); + af2cp_sTxPort.c1.valid <= 1'b1; + Num_Writes <= (wrreq_type == eREQ_WRFENCE) ? Num_Writes : Num_Writes + 1'b1; + end + end // re2xy_go + + // Channel 0 + if( re2xy_go && rnd_delay + && RdHdr_valid_q) // Read from Source Workspace + begin //---------------------------------- + af2cp_sTxPort.c0.hdr.vc_sel <= t_ccip_vc'(rd_ch_type); + af2cp_sTxPort.c0.hdr.req_type <= rdreq_type; + af2cp_sTxPort.c0.hdr.address[41:0] <= RdAddr; + af2cp_sTxPort.c0.hdr.mdata[15:0] <= ab2re_RdTID_q; + af2cp_sTxPort.c0.valid <= 1'b1; + af2cp_sTxPort.c0.hdr.cl_len <= t_ccip_clLen'(ab2re_RdLen_q); + Num_Reads <= Num_Reads + re2xy_multiCL_len + 1'b1; + end + + //-------------------------------------------------------------------------- + // Rx Response Path + //-------------------------------------------------------------------------- + cp2af_sRxPort_T1 <= cp2af_sRxPort; + + // Counters + //-------------------------------------------------------------------------- + if(re2xy_go) // Count #clks after test start + begin + Num_ticks_low <= Num_ticks_low + 1'b1; + if(&Num_ticks_low) + Num_ticks_high <= Num_ticks_high + 1'b1; + end + + if(re2xy_go & cp2af_sRxPort.c0TxAlmFull ) + Num_C0stall <= Num_C0stall + 1'b1; + + if(re2xy_go & cp2af_sRxPort.c1TxAlmFull) + Num_C1stall <= Num_C1stall + 1'b1; + + // Read Request + tx_c0_req_valid <= af2cp_sTxPort.c0.valid && (af2cp_sTxPort.c0.hdr.req_type==eREQ_RDLINE_I || af2cp_sTxPort.c0.hdr.req_type==eREQ_RDLINE_S); + tx_rd_req_len <= af2cp_sTxPort.c0.hdr.cl_len[1:0]; + // Read Response + rx_c0_resp_valid <= cp2af_sRxPort_T1.c0.rspValid && cp2af_sRxPort_T1.c0.hdr.resp_type==eRSP_RDLINE; + + // Write Request + tx_c1_req_valid <= af2cp_sTxPort.c1.valid && (af2cp_sTxPort.c1.hdr.req_type==eREQ_WRLINE_I || af2cp_sTxPort.c1.hdr.req_type==eREQ_WRLINE_M || af2cp_sTxPort.c1.hdr.req_type== eREQ_WRPUSH_I ); + // Write Response + rx_c1_resp_valid <= cp2af_sRxPort_T1.c1.rspValid && cp2af_sRxPort_T1.c1.hdr.resp_type==eRSP_WRLINE; + rx_wr_resp_fmt <= cp2af_sRxPort_T1.c1.hdr.format; + rx_wr_resp_cl_num <= cp2af_sRxPort_T1.c1.hdr.cl_num[1:0]; + + num_rd_sent <= tx_rd_req_len + 1'b1; + tx_c0_req_valid_q <= tx_c0_req_valid; + rx_c0_resp_valid_q <= rx_c0_resp_valid; + tx_c1_req_valid_q <= tx_c1_req_valid; + rx_c1_resp_valid_q <= rx_c1_resp_valid; + + // Track number of pending Reads + case({rx_c0_resp_valid_q , tx_c0_req_valid_q}) + 2'b00: Num_RdPend <= Num_RdPend; + 2'b01: Num_RdPend <= Num_RdPend + num_rd_sent; + 2'b10: Num_RdPend <= Num_RdPend - 1'h1; + 2'b11: Num_RdPend <= Num_RdPend + num_rd_sent - 1'h1; + endcase + + case (rx_wr_resp_fmt) + 1'b0: num_wr_recvd <= 1'h1; + 1'b1: num_wr_recvd <= rx_wr_resp_cl_num + 1'h1; + endcase + + // Track number of pending Writes + case({rx_c1_resp_valid_q, tx_c1_req_valid_q}) + 2'b00: Num_WrPend <= Num_WrPend; + 2'b01: Num_WrPend <= Num_WrPend + 1'h1; + 2'b10: Num_WrPend <= Num_WrPend - num_wr_recvd; + 2'b11: Num_WrPend <= Num_WrPend - num_wr_recvd + 1'h1; + endcase + + // For LPBK1 (memory copy): stall reads if Num_RdCredits less than 0. Read credits are limited by the depth of Write fifo + // Wr fifo depth in requestor is 128. Therefore max num write pending should be less than 128. + + case ({af2cp_sTxPort.c0.valid,af2cp_sTxPort.c1.valid }) + 2'b01: + begin + if (af2cp_sTxPort.c1.hdr.sop) + Num_RdCredits <= Num_RdCredits + 1'b1; // 1Wr sent + end + + 2'b10: + begin + Num_RdCredits <= Num_RdCredits - 1'b1; // 1Rd sent + end + + 2'b11: + begin + if (!af2cp_sTxPort.c1.hdr.sop) + Num_RdCredits <= Num_RdCredits - 1'b1; // 1Rd + 1Wr sent + end + + default: + begin + Num_RdCredits <= Num_RdCredits; + end + endcase + re2ab_stallRd <= ($signed(Num_RdCredits)<=0); + + // Error Detection Logic + //-------------------------- + // synthesis translate_off + if(|ErrorVector) + $finish(); + // synthesis translate_on + + if(Num_RdPend[11]==1'b1) + begin + ErrorVector[0] <= 1; + /*synthesis translate_off */ + $display("nlb_lpbk: Error: unexpected RxRead response"); + /*synthesis translate_on */ + end + + if(Num_WrPend[11]==1'b1) + begin + ErrorVector[0] <= 1; + /*synthesis translate_off */ + $display("nlb_lpbk: Error: unexpected RxWrite response"); + /*synthesis translate_on */ + end + + if(txFifo_Full & txFifo_WrEn) + begin + ErrorVector[2] <= 1; + /*synthesis translate_off */ + $display("nlb_lpbk: Error: wr fifo overflow"); + /*synthesis translate_on */ + end + + if(ErrorVector[3]==0) + ErrorVector[3] <= ab2re_ErrorValid; + + /* synthesis translate_off */ + // if(af2cp_sTxPort.c1.valid ) + // $display("*Req Type: %x \t Addr: %x \n Data: %x", af2cp_sTxPort.c1.hdr.req_type, af2cp_sTxPort.c1.hdr.address, af2cp_sTxPort.c1.data); + + // if(af2cp_sTxPort.c0.valid) + // $display("*Req Type: %x \t Addr: %x", af2cp_sTxPort.c0.hdr.req_type, af2cp_sTxPort.c0.hdr.address); + + /* synthesis translate_on */ + + + // Use for Debug- if no transactions going across the CCI interface # clks > inactivity threshold + // than set the flag. You may use this as a trigger signal in logic analyzer + if(af2cp_sTxPort.c1.valid || af2cp_sTxPort.c0.valid) + inact_cnt <= cr_inact_thresh; + else if(re2xy_go) + inact_cnt <= inact_cnt - 1'b1; + + if(inact_timeout==0) + begin + if(inact_cnt==0) + inact_timeout <= 1'b1; + end + else if(af2cp_sTxPort.c1.valid || af2cp_sTxPort.c0.valid) + begin + inact_timeout <= 0; + end + + if(!test_Reset_n) + begin + Num_Reads <= 0; + Num_Writes <= 0; + Num_RdPend <= 0; + Num_WrPend <= 0; + Num_ticks_low <= 0; + Num_ticks_high <= 0; + re2xy_go <= 0; + + re2ab_CfgValid_d <= 0; + ErrorVector <= 0; + status_write <= 0; + interrupt_sent <= 0; + send_interrupt <= 0; + inact_cnt <= 0; + inact_timeout <= 0; + delay_lfsr <= 1; + delay_lfsr1 <= 1; + Num_C0stall <= 0; + Num_C1stall <= 0; + Num_RdCredits <= (2**PEND_THRESH-8); // Max num rdcredits is 128. But 128 multiCL Reads could in turn lead to 512 writes + // So, TxWriteFIFO is made 512 deep and RdCredit return is adjusted accordingly + dsm_status_wren_a <= 0; + dsm_status_wren_b <= 0; + dsm_status_wren_c <= 0; + test_stop <= 0; + WrFence_sent <= 0; + test_cmplt <= 0; + read_only_test <= 0; + end + end + + always @(posedge Clk_400) // Computes NLB start and end overheads + begin //------------------------------------- + if(!test_go) + begin + penalty_start <= 0; + penalty_start_f <= 0; + penalty_end <= 8'h2; + end + else + begin + if(!penalty_start_f & (af2cp_sTxPort.c0.valid | af2cp_sTxPort.c1.valid )) + begin + penalty_start_f <= 1'b1; + penalty_start <= Num_ticks_low[7:0]; /* synthesis translate_off */ + $display ("NLB_INFO : start penalty = %d ", Num_ticks_low); /* synthesis translate_on */ + end + + penalty_end <= penalty_end + 1'b1; + if( cp2af_sRxPort.c0.rspValid + | cp2af_sRxPort.c1.rspValid | cp2af_sRxPort.c0.mmioWrValid + ) + begin + penalty_end <= 8'h2; + end + + if(ab2re_TestCmp + && !cp2af_sRxPort.c1TxAlmFull + && !status_write) + begin /* synthesis translate_off */ + $display ("NLB_INFO : end penalty = %d ", penalty_end); /* synthesis translate_on */ + end + + end + end + + + logic rd_pend_thresh; + logic wr_pend_thresh; + always @(*) + begin + + RdHdr_valid = re2xy_go + && !status_write + && rnd_delay + && !cp2af_sRxPort.c0TxAlmFull + && ab2re_RdEn; + + re2ab_RdSent= RdHdr_valid & !rd_pend_thresh; + + txFifo_RdAck = re2xy_go && rnd_delay && !cp2af_sRxPort.c1TxAlmFull && txFifo_Dout_v && !wr_pend_thresh; + wrreq_type = txFifo_WrFence_qq ? eREQ_WRFENCE + :cr_wrlineI_en ? eREQ_WRLINE_I + : cr_wrpushI_en ? eREQ_WRPUSH_I + : eREQ_WRLINE_M; + + end + always @(posedge Clk_400) + begin + rd_pend_thresh <= Num_RdPend[10] && Num_RdPend[9]; + wr_pend_thresh <= Num_WrPend[10] && Num_WrPend[9]; + WrHdr_valid_T1 <= txFifo_RdAck; + WrHdr_valid_T2 <= WrHdr_valid_T1 & re2xy_go; + WrHdr_valid_T3 <= WrHdr_valid_T2; + WrHdr_valid_T4 <= WrHdr_valid_T3; + if(!test_Reset_n) + begin + WrHdr_valid_T1 <= 0; + WrHdr_valid_T2 <= 0; + WrHdr_valid_T3 <= 0; + WrHdr_valid_T4 <= 0; + end + end + + //---------------------------------------------------------------------------------------------------------------------------------------------- + // Instances + //---------------------------------------------------------------------------------------------------------------------------------------------- + // Tx Write request fifo. Some tests may have writes dependent on reads, i.e. a read response will generate a write request + // If the CCI-S write channel is stalled, then the write requests will be queued up in this Tx fifo. + + // NOTE: RAM inside the FIFO is currently sized to handle 556 bits (din/dout) and 512 deep + // Regenerate the RAM with additional bits if you increase the width/depth of this FIFO + + // FIFO Bitmap - 556 bits wide and 512 bits deep + + // [551:550] - ab2re_WrLen + // [549] - ab2re_WrSop + // [548] - ab2re_WrFence + // [547:36] - ab2re_WrDin + // [35:16] - ab2re_WrAddr + // [15:0] - ab2re_WrTID + wire [3+1+2+1+1+512+ADDR_LMT+15:0]txFifo_Din= { ab2re_WrLen, + ab2re_WrSop, + ab2re_WrFence, + ab2re_WrDin, + ab2re_WrAddr, + ab2re_WrTID + }; + wire [3+1+2+1+1+512+ADDR_LMT+15:0]txFifo_Dout; + assign txFifo_WrLen = txFifo_Dout[2+1+1+DATA_WIDTH+ADDR_LMT+16-1: 1+1+1+DATA_WIDTH+ADDR_LMT+16-1]; + assign txFifo_WrSop = txFifo_Dout[1+1+DATA_WIDTH+ADDR_LMT+16-1]; + assign txFifo_WrFence = txFifo_Dout[1+DATA_WIDTH+ADDR_LMT+16-1]; + assign txFifo_WrDin = txFifo_Dout[ADDR_LMT+16+:DATA_WIDTH]; + assign txFifo_WrAddr = txFifo_Dout[16+:ADDR_LMT]; + assign txFifo_WrTID = txFifo_Dout[15:0]; + + wire [9-1:0] txFifo_count; + nlb_C1Tx_fifo #(.DATA_WIDTH (3+1+2+1+1+DATA_WIDTH+ADDR_LMT+16), + .CTL_WIDTH (0), + .DEPTH_BASE2 (9), + .GRAM_MODE (3), + .FULL_THRESH (2**9-8) + )nlb_writeTx_fifo + ( //--------------------- Input ------------------ + .Resetb (test_Reset_n), + .Clk (Clk_400), + .fifo_din (txFifo_Din), + .fifo_ctlin (), + .fifo_wen (txFifo_WrEn), + .fifo_rdack (txFifo_RdAck), + //--------------------- Output ------------------ + .T2_fifo_dout (txFifo_Dout), + .T0_fifo_ctlout (), + .T0_fifo_dout_v (txFifo_Dout_v), + .T0_fifo_empty (), + .T0_fifo_full (txFifo_Full), + .T0_fifo_count (txFifo_count), + .T0_fifo_almFull (txFifo_AlmFull), + .T0_fifo_underflow (), + .T0_fifo_overflow () + ); + + // Function: Returns physical address for a DSM register + function automatic [41:0] dsm_offset2addr; + input [9:0] offset_b; + input [63:0] base_b; + begin + dsm_offset2addr = base_b[47:6] + offset_b[9:6]; + end + endfunction + + //---------------------------------------------------------------- + // For signal tap + //---------------------------------------------------------------- +/* + + (* noprune *) reg [3:0] DEBUG_nlb_error; + (* noprune *) reg [31:0] DEBUG_Num_Reads; + (* noprune *) reg [31:0] DEBUG_Num_Writes; + (* noprune *) reg DEBUG_inact_timeout; + (* noprune *) reg [9:0] DEBUG_C0TxHdrID; + (* noprune *) reg [31:0] DEBUG_C0TxHdrAddr; + (* noprune *) reg [9:0] DEBUG_C1TxHdrID; + (* noprune *) reg [31:0] DEBUG_C1TxHdrAddr; + (* noprune *) reg [16:0] DEBUG_C1TxData; + (* noprune *) reg [9:0] DEBUG_C0RxHdrID; + (* noprune *) reg [8:0] DEBUG_C0RxData; + (* noprune *) reg [9:0] DEBUG_C1RxHdrID; + (* noprune *) reg DEBUG_C0TxValid; + (* noprune *) reg DEBUG_C0RxValid; + (* noprune *) reg DEBUG_C1TxValid; + (* noprune *) reg DEBUG_C1RxValid; + (* noprune *) reg DEBUG_txFifo_Dout_v; + (* noprune *) reg DEBUG_txFifo_RdAck; + (* noprune *) reg DEBUG_txFifo_WrEn; + (* noprune *) reg DEBUG_txFifo_Full; + (* noprune *) reg [4:0] DEBUG_txFifo_Din, DEBUG_txFifo_Dout; + (* noprune *) reg [15:0] DEBUG_txFifo_WrCount, DEBUG_txFifo_RdCount; + (* noprune *) reg [9-1:0] DEBUG_txFifo_count; // TODO: was PEND_THRESH (7) + + + always @(posedge Clk_400) + begin + DEBUG_nlb_error[3:0] <= ErrorVector[3:0]; + DEBUG_Num_Reads <= Num_Reads; + DEBUG_Num_Writes <= Num_Writes; + DEBUG_inact_timeout <= inact_timeout; + DEBUG_C0TxHdrID <= af2cp_sTxPort.c0.hdr.mdata[9:0]; + DEBUG_C0TxHdrAddr <= af2cp_sTxPort.c0.hdr.address[31:0]; + DEBUG_C1TxHdrID <= af2cp_sTxPort.c1.hdr.mdata[9:0]; + DEBUG_C1TxHdrAddr <= af2cp_sTxPort.c1.hdr.address[31:0]; + DEBUG_C1TxData <= af2cp_sTxPort.c1.data[16:0]; + DEBUG_C0RxHdrID <= cp2af_sRxPort.c0.hdr.mdata[9:0]; + DEBUG_C0RxData <= cp2af_sRxPort.c0.data[8:0]; + DEBUG_C1RxHdrID <= cp2af_sRxPort.c1.hdr.mdata[9:0]; + DEBUG_C0TxValid <= af2cp_sTxPort.c0.valid; + DEBUG_C1TxValid <= af2cp_sTxPort.c1.valid; + DEBUG_C0RxValid <= cp2af_sRxPort.c0.rspValid; + DEBUG_C1RxValid <= cp2af_sRxPort.c1.rspValid; + + DEBUG_txFifo_Dout_v <= txFifo_Dout_v; + DEBUG_txFifo_RdAck <= txFifo_RdAck; + DEBUG_txFifo_WrEn <= txFifo_WrEn; + DEBUG_txFifo_Full <= txFifo_Full; + DEBUG_txFifo_Din <= txFifo_Din[4:0]; + DEBUG_txFifo_Dout <= txFifo_Dout[4:0]; + DEBUG_txFifo_count <= txFifo_count; + if(txFifo_WrEn) + DEBUG_txFifo_WrCount <= DEBUG_txFifo_WrCount+1'b1; + if(txFifo_RdAck) + DEBUG_txFifo_RdCount <= DEBUG_txFifo_RdCount+1'b1; + + if(!test_Reset_n) + begin + DEBUG_txFifo_WrCount<= 0; + DEBUG_txFifo_RdCount<= 0; + end + end +*/ + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/test_lpbk1.sv b/ase/sample_config/intg_xeon_nlb/rtl/test_lpbk1.sv new file mode 100755 index 000000000000..76cb7c2f7139 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/test_lpbk1.sv @@ -0,0 +1,748 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: test_lpbk1.v +// Project: NLB AFU +// Description: memory copy test +// +// *************************************************************************** +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// Loopback 1- memory copy test +// ------------------------------------------------------------------------------------------------------------------------------------------------ +// +// This is a memory copy test. It copies cache lines from source to destination buffer. +// +`default_nettype none +module test_lpbk1 #(parameter PEND_THRESH=1, ADDR_LMT=20, MDATA=14) +( + +// ---------------------------global signals------------------------------------------------- + Clk_400 , // in std_logic; -- Core clock + + l12ab_WrAddr, // [ADDR_LMT-1:0] arb: write address + l12ab_WrTID, // [ADDR_LMT-1:0] arb: meta data + l12ab_WrDin, // [511:0] arb: Cache line data + l12ab_WrEn, // arb: write enable + ab2l1_WrSent, // arb: write issued + ab2l1_WrAlmFull, // arb: write fifo almost full + + l12ab_RdAddr, // [ADDR_LMT-1:0] arb: Reads may yield to writes + l12ab_RdTID, // [15:0] arb: meta data + l12ab_RdEn, // arb: read enable + ab2l1_RdSent, // arb: read issued + + ab2l1_RdRspValid_T0, // arb: read response valid + ab2l1_RdRsp_T0, // [15:0] arb: read response header + ab2l1_RdRspAddr_T0, // [ADDR_LMT-1:0] arb: read response address + ab2l1_RdData_T0, // [511:0] arb: read data + ab2l1_stallRd, // arb: stall read requests FOR LPBK1 + + ab2l1_WrRspValid_T0, // arb: write response valid + ab2l1_WrRsp_T0, // [15:0] arb: write response header + ab2l1_WrRspAddr_T0, // [ADDR_LMT-1:0] arb: write response address + re2xy_go, // requestor: start the test + re2xy_NumLines, // [31:0] requestor: number of cache lines + re2xy_Cont, // requestor: continuous mode + + l12ab_TestCmp, // arb: Test completion flag + l12ab_ErrorInfo, // [255:0] arb: error information + l12ab_ErrorValid, // arb: test has detected an error + test_Resetb, // requestor: rest the app + + l12ab_RdLen, + l12ab_RdSop, + l12ab_WrLen, + l12ab_WrSop, + + ab2l1_RdRspFormat, + ab2l1_RdRspCLnum_T0, + ab2l1_WrRspFormat_T0, + ab2l1_WrRspCLnum_T0, + re2xy_multiCL_len +); + //------------------------------------------------------------------------------------------------------------------------ + + input logic Clk_400; // Clk_400 + + output logic [ADDR_LMT-1:0] l12ab_WrAddr; // [ADDR_LMT-1:0] arb: write address + output logic [15:0] l12ab_WrTID; // [15:0] arb: meta data + output logic [511:0] l12ab_WrDin; // [511:0] arb: Cache line data + output logic l12ab_WrEn; // arb: write enable + input logic ab2l1_WrSent; // arb: write issued + input logic ab2l1_WrAlmFull; // arb: write fifo almost full + + output logic [ADDR_LMT-1:0] l12ab_RdAddr; // [ADDR_LMT-1:0] arb: Reads may yield to writes + output logic [15:0] l12ab_RdTID; // [15:0] arb: meta data + output logic l12ab_RdEn; // arb: read enable + input logic ab2l1_RdSent; // arb: read issued + + input logic ab2l1_RdRspValid_T0; // arb: read response valid + input logic [15:0] ab2l1_RdRsp_T0; // [15:0] arb: read response header + input logic [ADDR_LMT-1:0] ab2l1_RdRspAddr_T0; // [ADDR_LMT-1:0] arb: read response address + input logic [511:0] ab2l1_RdData_T0; // [511:0] arb: read data + input logic ab2l1_stallRd; // arb: stall read requests FOR LPBK1 + + input logic ab2l1_WrRspValid_T0; // arb: write response valid + input logic [15:0] ab2l1_WrRsp_T0; // [15:0] arb: write response header + input logic [ADDR_LMT-1:0] ab2l1_WrRspAddr_T0; // [Addr_LMT-1:0] arb: write response address + + input logic re2xy_go; // requestor: start of frame recvd + input logic [31:0] re2xy_NumLines; // [31:0] requestor: number of cache lines + input logic re2xy_Cont; // requestor: continuous mode + + output logic l12ab_TestCmp; // arb: Test completion flag + output logic [255:0] l12ab_ErrorInfo; // [255:0] arb: error information + output logic l12ab_ErrorValid; // arb: test has detected an error + input logic test_Resetb; + + output logic [1:0] l12ab_RdLen; + output logic l12ab_RdSop; + output logic [1:0] l12ab_WrLen; + output logic l12ab_WrSop; + + input logic ab2l1_RdRspFormat; + input logic [1:0] ab2l1_RdRspCLnum_T0; + input logic ab2l1_WrRspFormat_T0; + input logic [1:0] ab2l1_WrRspCLnum_T0; + + input logic [1:0] re2xy_multiCL_len; + + //------------------------------------------------------------------------------------------------------------------------ + + logic [MDATA-1:0] wr_mdata; + logic [1:0] read_fsm; + logic write_fsm, write_fsm_q; + logic [19:0] Num_Read_req; + logic [19:0] Num_Write_req; + logic [19:0] Num_Write_rsp; + logic Wr_go; + logic ab2l1_WrAlmFull_q, ab2l1_WrAlmFull_qq; + logic [1:0] wrCLnum, wrCLnum_q, wrCLnum_qq, wrCLnum_qqq; + logic ram_rdValid, ram_rdValid_q, ram_rdValid_qq, ram_rdValid_qqq; + logic wrsop, wrsop_q, wrsop_qq, wrsop_qqq; + logic [6:0] WrReq_tid, WrReq_tid_q; + logic [6:0] WrReq_tid_mCL; + logic [6:0] i; + logic [2:0] multiCL_num; + logic rd_done; + logic finite_test; + logic [4:0] ram_max_index; + logic [7:0] Num_ram_reads; + logic [20:0] Total_ram_reads; + logic [15:0] ab2l1_WrRsp; + logic [1:0] ab2l1_WrRspCLnum; + logic [2:0] pckd_num_wr_rsp; + logic [ADDR_LMT-1:0] ab2l1_WrRspAddr; + logic ab2l1_WrRspFormat; + logic ab2l1_WrRspValid; + logic [15:0] ab2l1_RdRsp; + logic [1:0] ab2l1_RdRspCLnum; + logic [ADDR_LMT-1:0] ab2l1_RdRspAddr; + logic [511:0] ab2l1_RdData; + logic ab2l1_RdRspValid; + logic memwr_en_ram0, memwr_en_ram1; + logic [533:0] rdrsp_mem_in; + logic [8:0] memrd_addr; + logic [8:0] memwr_addr; + logic [533:0] wrreq_mem0_out; + logic [533:0] wrreq_mem0_out_q; + logic [533:0] wrreq_mem1_out; + logic [533:0] wrreq_mem1_out_q; + logic [1:0] FSM_Rd_throttle; + logic [7:0] Num_buff_RdReq; + logic [1:0] fsm_read_ctrl; + logic [1:0] fsm_write_ctrl; + logic [1:0] buff0_status; + logic [1:0] buff1_status; + logic [1:0] buff1_status_T1; + logic [1:0] buff1_status_T2; + logic ram1_sel_T3; + logic buff0_rd_cmplt; + logic buff1_rd_cmplt; + logic buff0_wr_cmplt; + logic buff1_wr_cmplt; + logic [20:0] Total_Num_RdRsp; + logic [9:0] Num_RdRsp_buff0; + logic [9:0] Num_RdRsp_buff1; + logic trigger_rds_done; + logic Wr_cmplt; + logic Wr_cmplt_q; + logic rd_cmplt; + logic Read_Buffer_ID; + logic buff0_serviced; + logic buff1_serviced; + + (* maxfan=32 *) logic ram1_sel_T4; + (* maxfan=1 *) logic [1:0] CL_ID; + + localparam mCL1_depth_base2 = 7; + localparam mCL2_depth_base2 = 8; + localparam mCL4_depth_base2 = 9; + localparam READ = 2'b00; + localparam READ_DONE = 2'b01; + localparam WRITE = 2'b10; + localparam WRITE_DONE = 2'b11; + + // ---------------------------------------------------------------------------- + // Registering Rsp inputs - Adds 1 additional cycle bw last Rsp to completion + // ---------------------------------------------------------------------------- + always@(posedge Clk_400) + begin + ab2l1_WrRsp <= ab2l1_WrRsp_T0; + ab2l1_WrRspCLnum <= ab2l1_WrRspCLnum_T0; + ab2l1_WrRspAddr <= ab2l1_WrRspAddr_T0; + ab2l1_WrRspFormat <= ab2l1_WrRspFormat_T0; + ab2l1_WrRspValid <= ab2l1_WrRspValid_T0; + ab2l1_RdRsp <= ab2l1_RdRsp_T0; + ab2l1_RdRspCLnum <= ab2l1_RdRspCLnum_T0; + ab2l1_RdRspAddr <= ab2l1_RdRspAddr_T0; + ab2l1_RdData <= ab2l1_RdData_T0; + ab2l1_RdRspValid <= ab2l1_RdRspValid_T0; + end + + // ---------------------------------------------------------------------------- + // Static Update based on multi CL length + // ---------------------------------------------------------------------------- + always@(posedge Clk_400) + begin + finite_test <= re2xy_go && !re2xy_Cont; + if (!test_Resetb) + begin + ram_max_index <= mCL1_depth_base2; + finite_test <= 0; + end + + else + begin + case (re2xy_multiCL_len) + 2'b00 : ram_max_index <= mCL1_depth_base2; + 2'b01 : ram_max_index <= mCL2_depth_base2; + 2'b11 : ram_max_index <= mCL4_depth_base2; + default: ram_max_index <= mCL1_depth_base2; + endcase + end + end + + // ------------------------------------------------------ + // Read FSM + // ------------------------------------------------------ + always @(posedge Clk_400) + begin + case(read_fsm) /* synthesis parallel_case */ + 2'h0: + begin // Wait for re2xy_go + l12ab_RdAddr <= 0; + l12ab_RdLen <= re2xy_multiCL_len; + l12ab_RdSop <= 1'b1; + Num_Read_req <= 20'h0 + re2xy_multiCL_len + 1'b1; // Default is 1 req; implies single CL + + if(re2xy_go) + if(re2xy_NumLines!=0) + read_fsm <= 2'h1; + else + read_fsm <= 2'h2; + end + + 2'h1: + begin // Send read requests + if(ab2l1_RdSent) + begin + l12ab_RdAddr <= l12ab_RdAddr + re2xy_multiCL_len + 1'b1; // multiCL_len = {0/1/2/3} + l12ab_RdLen <= l12ab_RdLen; // All reqs are uniform. Based on test cfg + l12ab_RdSop <= 1'b1; // All reqs are uniform. Based on test cfg + Num_Read_req <= Num_Read_req + re2xy_multiCL_len + 1'b1; // final count will be same as re2xy_NumLines + + if(Num_Read_req == re2xy_NumLines) + if(re2xy_Cont) read_fsm <= 2'h0; + else read_fsm <= 2'h2; + end // ab2l1_RdSent + end + + default: read_fsm <= read_fsm; + endcase + + if(read_fsm==2'h2 && Num_Write_rsp==re2xy_NumLines) + begin + l12ab_TestCmp <= 1'b1; + end + + // Error logic + if(l12ab_WrEn && ab2l1_WrSent==0) + begin + // WrFSM assumption is broken + $display ("%m LPBK1 test WrEn asserted, but request Not accepted by requestor"); + l12ab_ErrorValid <= 1'b1; + l12ab_ErrorInfo <= 1'b1; + end + + if(!test_Resetb) + begin + l12ab_TestCmp <= 0; + l12ab_ErrorInfo <= 0; + l12ab_ErrorValid <= 0; + read_fsm <= 0; + Num_Read_req <= 20'h1; + l12ab_RdLen <= 0; + l12ab_RdSop <= 1; + end + end + + always @(*) + begin + l12ab_RdTID = 0; + l12ab_RdTID[MDATA-1:0] = {Read_Buffer_ID, Num_buff_RdReq[7:0]}; + l12ab_RdEn = (read_fsm ==2'h1) & !Num_buff_RdReq[7]; + end + + // ------------------------------------------------------ + // RAM to store RdRsp Data and Address + // 2 cycle Read latency + // 2 cycle Rd2Wr latency + // Unknown data returned if same address is read, written + // ------------------------------------------------------ + + // RAM0 Instance + lpbk1_RdRspRAM2PORT rdrsp_mem0 ( + .data (rdrsp_mem_in), // ram_input.datain + .wraddress (memwr_addr), // .wraddress + .rdaddress (memrd_addr), // .rdaddress + .wren (memwr_en_ram0), // .wren + .clock (Clk_400), // .clock + .q (wrreq_mem0_out) // ram_output.dataout + ); + + // RAM1 Instance + lpbk1_RdRspRAM2PORT rdrsp_mem1 ( + .data (rdrsp_mem_in), // ram_input.datain + .wraddress (memwr_addr), // .wraddress + .rdaddress (memrd_addr), // .rdaddress + .wren (memwr_en_ram1), // .wren + .clock (Clk_400), // .clock + .q (wrreq_mem1_out) // ram_output.dataout + ); + + // ---------------------------------------------------------------------------- + // Collect RdRsp in RAM0/1 + // Initiate Write Requests + // Collect Write Responses + // ---------------------------------------------------------------------------- + always @(posedge Clk_400) + begin + case (FSM_Rd_throttle) + 2'h0: + begin + if (ab2l1_RdSent) + Num_buff_RdReq <= Num_buff_RdReq + 1'b1; + + if (Num_buff_RdReq[7] && Read_Buffer_ID == 0) + FSM_Rd_throttle <= 2'h1; + + if (Num_buff_RdReq[7] && Read_Buffer_ID == 1) + FSM_Rd_throttle <= 2'h2; + end + + 2'h1: + begin + if (buff1_serviced && buff1_status == READ) + begin + FSM_Rd_throttle <= 2'h0; + Read_Buffer_ID <= 1; + Num_buff_RdReq <= 0; + buff1_serviced <= 0; + end + end + + 2'h2: + begin + if (buff0_serviced && buff0_status == READ) + begin + FSM_Rd_throttle <= 2'h0; + Read_Buffer_ID <= 0; + Num_buff_RdReq <= 0; + buff0_serviced <= 0; + end + end + + default: + FSM_Rd_throttle <= FSM_Rd_throttle; + endcase + + case(fsm_read_ctrl) /* synthesis parallel_case */ + 2'h0: + begin + if (buff0_status == WRITE_DONE || buff0_status == READ) // all buffer 0 writes complete + begin + fsm_read_ctrl <= 2'h1; + buff0_status <= READ; + end + end + + 2'h1: + begin + if (buff0_rd_cmplt) // all buffer 0 reads received + begin + buff0_status <= READ_DONE; + fsm_read_ctrl <= 2'h2; + buff0_rd_cmplt <= 0; + end + + if (buff1_status == WRITE_DONE) // all buffer 1 writes complete + begin + buff1_status <= READ; + end + end + + 2'h2: + begin + if (buff1_status == WRITE_DONE || buff1_status == READ) // all buffer 1 writes complete + begin + fsm_read_ctrl <= 2'h3; + buff1_status <= READ; + end + end + + 2'h3: + begin + if (buff1_rd_cmplt) // all buffer 1 reads received + begin + buff1_status <= READ_DONE; + fsm_read_ctrl <= 2'h0; + buff1_rd_cmplt <= 0; + end + + if (buff0_status == WRITE_DONE) // all buffer 0 writes complete + begin + buff0_status <= READ; + end + end + endcase + + case(fsm_write_ctrl) /* synthesis parallel_case */ + 2'h0: + begin + if (buff0_status == READ_DONE) // buffer 0 data ready + begin + fsm_write_ctrl <= 2'h1; + end + end + + 2'h1: + begin + buff0_status <= WRITE; + if (buff0_wr_cmplt) // all buffer 0 writes complete + begin + buff0_status <= WRITE_DONE; + buff0_serviced <= 1; + fsm_write_ctrl <= 2'h2; + end + end + + 2'h2: + begin + if (buff1_status == READ_DONE) // buffer 1 data ready + begin + fsm_write_ctrl <= 2'h3; + end + end + + 2'h3: + begin + buff1_status <= WRITE; + if (buff1_wr_cmplt) // all buffer 1 writes complete + begin + buff1_status <= WRITE_DONE; + buff1_serviced <= 1; + fsm_write_ctrl <= 2'h0; + end + end + endcase + + // Store RdResponses in RAM0 and RAM1 + memwr_en_ram0 <= 0; + memwr_en_ram1 <= 0; + memwr_addr <= {ab2l1_RdRsp[6:0],ab2l1_RdRspCLnum[1:0]}; + rdrsp_mem_in <= {ab2l1_RdData[511:0],ab2l1_RdRspAddr[19:0],ab2l1_RdRspCLnum[1:0]}; + + // Count Total Rd Responses + if (ab2l1_RdRspValid) + begin + Total_Num_RdRsp <= Total_Num_RdRsp + 1'b1; + end + + // Compute RdDone for non-cont test + trigger_rds_done <= 0; + if ((Total_Num_RdRsp == re2xy_NumLines) & finite_test & !rd_cmplt) + begin + trigger_rds_done <= 1; + rd_cmplt <= 1; + end + + // Count RdRsps to buffer0 + if(ab2l1_RdRspValid && !ab2l1_RdRsp[8]) + begin + memwr_en_ram0 <= 1; + Num_RdRsp_buff0 <= Num_RdRsp_buff0 + 1'b1; + end + + // Count RdRsps to buffer1 + if(ab2l1_RdRspValid && ab2l1_RdRsp[8]) + begin + memwr_en_ram1 <= 1; + Num_RdRsp_buff1 <= Num_RdRsp_buff1 + 1'b1; + end + + // Buffer0 has all data ready + if (trigger_rds_done || Num_RdRsp_buff0[ram_max_index]) + begin + buff0_rd_cmplt <= 1; + Num_RdRsp_buff0 <= 0; + end + + // Buffer1 has all data ready + if (trigger_rds_done || Num_RdRsp_buff1[ram_max_index]) + begin + buff1_rd_cmplt <= 1; + Num_RdRsp_buff1 <= 0; + end + + // Track Reads from RAM + if (!write_fsm & Wr_go & !ab2l1_WrAlmFull_qq) + begin + Num_ram_reads <= Num_ram_reads + 1'b1; + end + + // If all reads done: stop WrFSM, trigger write complete + Wr_cmplt <= 0; + Wr_cmplt_q <= Wr_cmplt; + if ( Num_ram_reads[7] || ((Total_ram_reads > re2xy_NumLines) && finite_test) ) + begin + Wr_go <= 0; + Wr_cmplt <= 1; + end + + else if (buff1_status == WRITE || buff0_status == WRITE) + begin + Wr_go <= 1; + end + + buff0_wr_cmplt <= 0; + if (Wr_cmplt && buff0_status == WRITE) + begin + buff0_wr_cmplt <= 1; + end + + buff1_wr_cmplt <= 0; + if (Wr_cmplt && buff1_status == WRITE) + begin + buff1_wr_cmplt <= 1; + end + + if (Wr_cmplt_q) + Num_ram_reads <= 0; + + // ---------------------------------------------------------------------------- + // WrFSM: Requestor Stores Tx Writes in a FIFO + // TxFIFO is sized in such a way that writes are guaranteed to be accepted + // So, ab2l1_WrSent = 0 when WrEn=1 is an error condition + // ---------------------------------------------------------------------------- + ab2l1_WrAlmFull_q <= ab2l1_WrAlmFull; + ab2l1_WrAlmFull_qq <= ab2l1_WrAlmFull_q; + case (write_fsm) /* synthesis parallel_case */ + 1'h0: + begin + if (Wr_go & !ab2l1_WrAlmFull_qq) + begin + // Read first CL of 'num_multi_CL' memWrite requests from RAM + write_fsm <= 1'h1; + CL_ID <= CL_ID + 1'b1; + memrd_addr <= {WrReq_tid[6:0], CL_ID}; + ram_rdValid <= 1; + Total_ram_reads <= Total_ram_reads + 1'b1; + wrsop <= 1; + wrCLnum <= re2xy_multiCL_len[1:0]; + end + end + + 1'h1: + begin + if (|wrCLnum[1:0]) + begin + // Read remaining CLs of 're2xy_multiCL_len' memWrite requests from RAM + write_fsm <= 1'h1; + CL_ID <= CL_ID + 1'b1; + memrd_addr <= {WrReq_tid[6:0], CL_ID}; + ram_rdValid <= 1; + Total_ram_reads <= Total_ram_reads + 1'b1; + wrsop <= 0; + wrCLnum <= wrCLnum - 1'b1; + end + + else + begin + // Goto next set of multiCL requests; One cycle bubble between each set of multi CL writes. + write_fsm <= 1'h0; + CL_ID <= 0; + ram_rdValid <= 0; + wrsop <= 1; + wrCLnum <= re2xy_multiCL_len[1:0]; + WrReq_tid <= WrReq_tid + 1'b1; + end + end + + default: + begin + write_fsm <= write_fsm; + end + endcase + + // ---------------------------------------------------------------------------- + // Pipeline WrReq parameters till RAM output is valid + // ---------------------------------------------------------------------------- + ram_rdValid_q <= ram_rdValid; + ram_rdValid_qq <= ram_rdValid_q; + ram_rdValid_qqq <= ram_rdValid_qq; + wrsop_q <= wrsop; + wrsop_qq <= wrsop_q; + wrsop_qqq <= wrsop_qq; + wrCLnum_q <= wrCLnum; + wrCLnum_qq <= wrCLnum_q; + wrCLnum_qqq <= wrCLnum_qq; + wrreq_mem0_out_q <= wrreq_mem0_out; + wrreq_mem1_out_q <= wrreq_mem1_out; + buff1_status_T1 <= buff1_status; + buff1_status_T2 <= buff1_status_T1; + + if (buff1_status_T2 == WRITE) + ram1_sel_T3 <= 1; + else + ram1_sel_T3 <= 0; + ram1_sel_T4 <= ram1_sel_T3; + + // ---------------------------------------------------------------------------- + // send Multi CL Write Requests + // ---------------------------------------------------------------------------- + l12ab_WrEn <= (ram_rdValid_qqq == 1'b1); + l12ab_WrSop <= wrsop_qqq; + l12ab_WrLen <= wrCLnum_qqq; + l12ab_WrAddr <= wrreq_mem0_out_q[21:2] + wrreq_mem0_out_q[1:0] ; + l12ab_WrDin <= wrreq_mem0_out_q[533:22]; + l12ab_WrTID[15:0] <= wrreq_mem0_out_q[17:2]; + + if(ram1_sel_T4) + begin + l12ab_WrAddr <= wrreq_mem1_out_q[21:2] + wrreq_mem1_out_q[1:0] ; + l12ab_WrDin <= wrreq_mem1_out_q[533:22]; + l12ab_WrTID[15:0] <= wrreq_mem1_out_q[17:2]; + end + + // ---------------------------------------------------------------------------- + // Track Num Write requests + // ---------------------------------------------------------------------------- + if (l12ab_WrEn) + begin + Num_Write_req <= Num_Write_req + 1'b1; + end + + // ---------------------------------------------------------------------------- + // Track Num Write responses + // ---------------------------------------------------------------------------- + pckd_num_wr_rsp <= ab2l1_WrRspCLnum_T0 + 1'b1; + if(ab2l1_WrRspValid && ab2l1_WrRspFormat) // Packed write response + begin + Num_Write_rsp <= Num_Write_rsp + pckd_num_wr_rsp; + end + + if (ab2l1_WrRspValid && !ab2l1_WrRspFormat) // unpacked write response + begin + Num_Write_rsp <= Num_Write_rsp + 1'b1; + end + + if (!test_Resetb) + begin + Wr_go <= 0; + memwr_en_ram0 <= 0; + memwr_en_ram1 <= 0; + multiCL_num <= 1; + write_fsm <= 1'h0; + WrReq_tid <= 0; + WrReq_tid_mCL <= 0; + CL_ID <= 0; + ram_rdValid <= 0; + wrsop <= 1; + wrCLnum <= 0; + l12ab_WrEn <= 0; + l12ab_WrSop <= 1; + l12ab_WrLen <= 0; + Num_Write_req <= 20'h1; + Num_Write_rsp <= 0; + pckd_num_wr_rsp <= 0; + Total_ram_reads <= 20'h1; + Num_ram_reads <= 0; + rd_done <= 0; + Total_Num_RdRsp <= 0; + trigger_rds_done <= 0; + Num_RdRsp_buff0 <= 0; + Num_RdRsp_buff1 <= 0; + Wr_cmplt <= 0; + Wr_cmplt_q <= 0; + rd_cmplt <= 0; + buff1_status_T1 <= 0; + buff1_status_T2 <= 0; + ram1_sel_T3 <= 0; + ab2l1_WrAlmFull_q <= 0; + ab2l1_WrAlmFull_qq <= 0; + Read_Buffer_ID <= 0; + Num_buff_RdReq <= 0; + FSM_Rd_throttle <= 0; + fsm_read_ctrl <= 0; + fsm_write_ctrl <= 0; + buff0_status <= WRITE_DONE; + buff1_status <= WRITE_DONE; + buff0_serviced <= 0; + buff1_serviced <= 1; + buff1_rd_cmplt <= 0; + buff0_rd_cmplt <= 0; + end + end + + // synthesis translate_off + logic numCL_error = 0; + always @(posedge Clk_400) + begin + if( re2xy_go && ((re2xy_NumLines)%(re2xy_multiCL_len + 1) != 0) ) + begin + $display("%m \m ERROR: Total Num Lines should be exactly divisible by multiCL length"); + $display("\m re2xy_NumLines = %d and re2xy_multiCL_len = %d",re2xy_NumLines,re2xy_multiCL_len); + numCL_error <= 1'b1; + end + + if(numCL_error) + $finish(); + end + // synthesis translate_on +endmodule + diff --git a/ase/sample_config/intg_xeon_nlb/rtl/test_rdwr.sv b/ase/sample_config/intg_xeon_nlb/rtl/test_rdwr.sv new file mode 100755 index 000000000000..2f744e009539 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/test_rdwr.sv @@ -0,0 +1,375 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: test_rdwr.v +// Project: NLB AFU +// Description: streaming read/write test +// +// *************************************************************************** +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// Read Write test +// ------------------------------------------------------------------------------------------------------------------------------------------------ +// Test bandwidth for read and write + +`default_nettype none +module test_rdwr #(parameter PEND_THRESH=1, ADDR_LMT=20, MDATA=14) +( + //---------------------------global signals------------------------------------------------- + Clk_400, // input -- Core clock + + ab2rw_Mode, // input [1:0] + + rw2ab_WrAddr, // output [ADDR_LMT-1:0] + rw2ab_WrTID, // output [ADDR_LMT-1:0] + rw2ab_WrDin, // output [511:0] + rw2ab_WrEn, // output + ab2rw_WrSent, // input + ab2rw_WrAlmFull, // input + re2xy_wrdin_msb, // input + + rw2ab_RdAddr, // output [ADDR_LMT-1:0] + rw2ab_RdTID, // output [15:0] + rw2ab_RdEn, // output + ab2rw_RdSent, // input + + ab2rw_RdRspValid, // input + ab2rw_RdRsp, // input [15:0] + ab2rw_RdRspAddr, // input [ADDR_LMT-1:0] + ab2rw_RdData, // input [511:0] + + ab2rw_WrRspValid, // input + ab2rw_WrRsp, // input [15:0] + ab2rw_WrRspAddr, // input [ADDR_LMT-1:0] + + re2xy_go, // input + re2xy_NumLines, // input [31:0] + re2xy_Cont, // input + re2xy_stride, // input [7:0] + + rw2ab_TestCmp, // output + rw2ab_ErrorInfo, // output [255:0] + rw2ab_ErrorValid, // output + test_Resetb, // input + + rw2ab_RdLen, + rw2ab_RdSop, + rw2ab_WrLen, + rw2ab_WrSop, + + ab2rw_RdRspFormat, + ab2rw_RdRspCLnum, + ab2rw_WrRspFormat, + ab2rw_WrRspCLnum, + re2xy_multiCL_len +); + + input logic Clk_400; // csi_top: Clk_400 + + input logic [1:0] ab2rw_Mode; // arb: 01 - reads only test, 10 - writes only test, 11 - read/write + + output logic [ADDR_LMT-1:0] rw2ab_WrAddr; // arb: write address + output logic [15:0] rw2ab_WrTID; // arb: meta data + output logic [511:0] rw2ab_WrDin; // arb: Cache line data + output logic rw2ab_WrEn; // arb: write enable + input logic ab2rw_WrSent; // arb: write issued + input logic ab2rw_WrAlmFull; // arb: write fifo almost full + input logic re2xy_wrdin_msb; // requestor: modifies msb(1) of wrdata to differntiate b/n different multiple afu write patterns + + + output logic [ADDR_LMT-1:0] rw2ab_RdAddr; // arb: Reads may yield to writes + output logic [15:0] rw2ab_RdTID; // arb: meta data + output logic rw2ab_RdEn; // arb: read enable + input logic ab2rw_RdSent; // arb: read issued + + input logic ab2rw_RdRspValid; // arb: read response valid + input logic [15:0] ab2rw_RdRsp; // arb: read response header + input logic [ADDR_LMT-1:0] ab2rw_RdRspAddr; // arb: read response address + input logic [511:0] ab2rw_RdData; // arb: read data + + input logic ab2rw_WrRspValid; // arb: write response valid + input logic [15:0] ab2rw_WrRsp; // arb: write response header + input logic [ADDR_LMT-1:0] ab2rw_WrRspAddr; // arb: write response address + + input logic re2xy_go; // requestor: start of frame recvd + input logic [31:0] re2xy_NumLines; // requestor: number of cache lines + input logic re2xy_Cont; // requestor: continuous mode + input logic [31:0] re2xy_stride; // requestor: 8-bit test cfg register + + output logic rw2ab_TestCmp; // arb: Test completion flag + output logic [255:0] rw2ab_ErrorInfo; // arb: error information + output logic rw2ab_ErrorValid; // arb: test has detected an error + input logic test_Resetb; + + output logic [1:0] rw2ab_RdLen; + output logic rw2ab_RdSop; + output logic [1:0] rw2ab_WrLen; + output logic rw2ab_WrSop; + + input logic ab2rw_RdRspFormat; + input logic [1:0] ab2rw_RdRspCLnum; + input logic ab2rw_WrRspFormat; + input logic [1:0] ab2rw_WrRspCLnum; + input logic [1:0] re2xy_multiCL_len; + + //------------------------------------------------------------------------------------------------------------------------ + + + reg [19:0] Num_RdReqs; + reg [10:0] Num_RdPend; + reg [1:0] RdFSM; + reg [MDATA-2:0] Rdmdata; + + reg [19:0] Num_WrReqs; + reg [10:0] Num_WrPend; + reg [1:0] WrFSM; + reg [MDATA-2:0] Wrmdata; + + + logic rw2ab_RdEn_q; + logic ab2rw_RdSent_q; + logic ab2rw_RdRspValid_q; + logic [1:0] RdFSM_q; + + logic rw2ab_WrEn_q; + logic ab2rw_WrSent_q; + logic ab2rw_WrRspValid_q; + logic ab2rw_WrRspFormat_q; + logic [1:0] ab2rw_WrRspCLnum_q; + logic [1:0] WrFSM_q; + + assign rw2ab_RdTID = {Rdmdata, 1'b1}; + assign rw2ab_WrTID = {Wrmdata, 1'b0}; + + assign rw2ab_RdEn = (RdFSM == 2'h1); + assign rw2ab_WrEn = (WrFSM == 2'h1); + + logic [6:0] stride; + assign stride = re2xy_stride[6:0]; + + always @(posedge Clk_400) + begin + rw2ab_ErrorInfo <= 'hx; + if (!test_Resetb) + begin + rw2ab_ErrorValid <= 0; + rw2ab_TestCmp <= 0; + end + else + begin + rw2ab_ErrorValid <= 0; + rw2ab_TestCmp <= (((WrFSM_q == 2'h2 && Num_WrPend == 0) && (RdFSM_q == 2'h2 && Num_RdPend == 0))); + end + end + + always @(posedge Clk_400) + begin + RdFSM_q <= RdFSM; + case(RdFSM) /* synthesis parallel_case */ + 2'h0: + begin + rw2ab_RdAddr <= 0; + rw2ab_RdLen <= re2xy_multiCL_len; + rw2ab_RdSop <= 1'b1; + Num_RdReqs <= 20'h0 + re2xy_multiCL_len + 1'b1; // Default is 1 req; implies single CL + + if(re2xy_go) + begin + if ((re2xy_NumLines!=0)&&(ab2rw_Mode[0]==1'b1)) + RdFSM <= 2'h1; + else + RdFSM <= 2'h2; + end + end + + 2'h1: + begin + if(ab2rw_RdSent) + begin + rw2ab_RdAddr <= rw2ab_RdAddr + re2xy_multiCL_len + 16'b1 + stride; + rw2ab_RdLen <= rw2ab_RdLen; + rw2ab_RdSop <= 1'b1; + Num_RdReqs <= Num_RdReqs + re2xy_multiCL_len + 1'b1; + + if(Num_RdReqs == re2xy_NumLines) + if(re2xy_Cont) + RdFSM <= 2'h0; + else + RdFSM <= 2'h2; + end + end + + default: + begin + RdFSM <= RdFSM; + end + endcase + + if ((rw2ab_RdEn && ab2rw_RdSent)) + Rdmdata <= Rdmdata + 1'b1; + + // Track read responses + // Timing Fix: Update Num_RdPend - one cycle delayed + // Delays Test completion by 1 cycle in non-cont mode + rw2ab_RdEn_q <= rw2ab_RdEn; + ab2rw_RdSent_q <= ab2rw_RdSent; + ab2rw_RdRspValid_q <= ab2rw_RdRspValid; + + if ((rw2ab_RdEn_q && ab2rw_RdSent_q) && !ab2rw_RdRspValid_q) + Num_RdPend <= Num_RdPend + 1'b1 + re2xy_multiCL_len; + else if ((rw2ab_RdEn_q && ab2rw_RdSent_q) && ab2rw_RdRspValid_q) + Num_RdPend <= Num_RdPend + re2xy_multiCL_len; + else if(!(rw2ab_RdEn_q && ab2rw_RdSent_q) && ab2rw_RdRspValid_q && ((rw2ab_TestCmp == 1'b0))) + Num_RdPend <= Num_RdPend - 1'b1; + + + if (!test_Resetb) + begin + rw2ab_RdAddr <= 0; + Rdmdata <= 0; + Num_RdReqs <= 20'h1; + Num_RdPend <= 0; + RdFSM <= 0; + rw2ab_RdLen <= 0; + rw2ab_RdSop <= 0; + end + + end + + always @(posedge Clk_400) + begin + WrFSM_q <= WrFSM; + case(WrFSM) /* synthesis parallel_case */ + 2'h0: + begin + rw2ab_WrAddr <= 0; + rw2ab_WrLen <= re2xy_multiCL_len; + rw2ab_WrSop <= 1; + Num_WrReqs <= 20'h1; + + if(re2xy_go) + begin + if((re2xy_NumLines != 0) && (ab2rw_Mode[1] == 1'b1)) + begin + WrFSM <= 2'h1; + end + + else + begin + WrFSM <= 2'h2; + end + end + end + + 2'h1: + begin + if(ab2rw_WrSent) + begin + if ((re2xy_multiCL_len == 0) || (rw2ab_WrLen == 2'b0)) + + begin + // Next request starts a new packet. Use the stride. + rw2ab_WrAddr <= rw2ab_WrAddr + 16'b1 + stride; + end + else + begin + // In the middle of a multi-line packet + rw2ab_WrAddr <= rw2ab_WrAddr + 16'b1; + end + Num_WrReqs <= Num_WrReqs + 1'b1; + + if (rw2ab_WrLen == 2'b00) + begin + rw2ab_WrLen <= re2xy_multiCL_len; + rw2ab_WrSop <= 1; + end + + else + begin + rw2ab_WrLen <= rw2ab_WrLen - 1'b1; + rw2ab_WrSop <= 0; + end + + if(Num_WrReqs == re2xy_NumLines) + if(re2xy_Cont) + WrFSM <= 2'h0; + else + WrFSM <= 2'h2; + end + end + + default: + begin + WrFSM <= WrFSM; + end + endcase + + rw2ab_WrDin <= {re2xy_wrdin_msb,31'h0,{13{32'h0000_0000}},~rw2ab_WrAddr,rw2ab_WrAddr}; + + if ((rw2ab_WrEn && ab2rw_WrSent)) + Wrmdata <= Wrmdata + 1'b1; + + rw2ab_WrEn_q <= rw2ab_WrEn; + ab2rw_WrSent_q <= ab2rw_WrSent; + ab2rw_WrRspValid_q <= ab2rw_WrRspValid; + ab2rw_WrRspFormat_q <= ab2rw_WrRspFormat; + ab2rw_WrRspCLnum_q <= ab2rw_WrRspCLnum; + + // Track write responses + if (rw2ab_WrEn_q && ab2rw_WrSent_q) // One write sent + begin + if(!ab2rw_WrRspValid_q) // No write response + Num_WrPend <= Num_WrPend + 1'b1; + else if (ab2rw_WrRspValid_q && ab2rw_WrRspFormat_q) + Num_WrPend <= Num_WrPend - ab2rw_WrRspCLnum_q; // Packed write response + //else + //Num_WrPend <= Num_WrPend; // Unpacked write response + end + + else if( (rw2ab_TestCmp == 1'b0) ) // no write sent and test is live + begin + if (ab2rw_WrRspValid_q && ab2rw_WrRspFormat_q) // Packed write response + Num_WrPend <= Num_WrPend - (ab2rw_WrRspCLnum_q + 1'b1); + else if (ab2rw_WrRspValid_q) // unpacked write response + Num_WrPend <= Num_WrPend - 1'b1; + //else + //Num_WrPend <= Num_WrPend; // No write response + end + + if (!test_Resetb) + begin +// rw2ab_WrAddr <= 0; + // rw2ab_WrDin <= 0; + Wrmdata <= 0; + Num_WrReqs <= 20'h1; + Num_WrPend <= 0; + WrFSM <= 0; + rw2ab_WrLen <= 0; + rw2ab_WrSop <= 0; + end + end + +endmodule diff --git a/ase/sample_config/intg_xeon_nlb/rtl/test_sw1.sv b/ase/sample_config/intg_xeon_nlb/rtl/test_sw1.sv new file mode 100755 index 000000000000..4a966ffc59f1 --- /dev/null +++ b/ase/sample_config/intg_xeon_nlb/rtl/test_sw1.sv @@ -0,0 +1,406 @@ +// *************************************************************************** +// Copyright (c) 2013-2016, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +// Module Name: test_sw1.v +// Project: NLB AFU +// Description: hw + sw ping pong test. FPGA initializes a location X, +// flag the SW. The SW in turn copies the data to location +// Y and flag the FPGA. FPGA reads the data from location Y. +// *************************************************************************** +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// SW test 1 +// --------------------------------------------------------------------------------------------------------------------------------------------------- +// Goal: +// Characterize 3 methods of notification from CPU to FPGA: +// 1. polling from AFU +// 2. UMsg without Data +// 3. UMsg with Data +// 3. CSR Write +// +// Test flow: +// 1. Wait on test_goErrorValid +// 2. Start timer. Write N cache lines. WrData= {16{32'h0000_0001}} +// 3. Write Fence. +// 4. FPGA -> CPU Message. Write to address N+1. WrData = {{14{32'h0000_0000}},{64{1'b1}}} +// 5. CPU -> FPGA Message. Configure one of the following methods: +// a. Poll on Addr N+1. Expected Data [63:32]==32'hffff_ffff +// b. CSR write to Address 0xB00. Data= Dont Care +// c. UMsg Mode 0 (with data). UMsg ID = 0 +// d. UMsgH Mode 1 (without data). UMsg ID = 0 +// 7. Read N cache lines. Wait for all read completions. +// 6. Stop timer Send test completion. +// +// test mode selection: +// re2xy_test_cfg[7:6] Description +// ---------------------------------------- +// 2'h0 Polling method +// 2'h1 CSR Write +// 2'h2 UMsg Mode 0 with data +// 2'h3 UMsgH Mode 1, i.e. hint without data. +// +// Determine test overheads for latency measurements + +`default_nettype none +module test_sw1 #(parameter PEND_THRESH=1, ADDR_LMT=20, MDATA=14) +( + //---------------------------global signals------------------------------------------------- + Clk_400, // input -- Core clock + + s12ab_WrAddr, // output [ADDR_LMT-1:0] + s12ab_WrTID, // output [ADDR_LMT-1:0] + s12ab_WrDin, // output [511:0] + s12ab_WrFence, // output write fence. + s12ab_WrEn, // output write enable + ab2s1_WrSent, // input + ab2s1_WrAlmFull, // input + + s12ab_RdAddr, // output [ADDR_LMT-1:0] + s12ab_RdTID, // output [15:0] + s12ab_RdEn, // output + ab2s1_RdSent, // input + + ab2s1_RdRspValid, // input + ab2s1_UMsgValid, // input + ab2s1_CfgValid, // input arb: Cfg valid + ab2s1_RdRsp, // input [15:0] + ab2s1_RdRspAddr, // input [ADDR_LMT-1:0] + ab2s1_RdData, // input [511:0] + + ab2s1_WrRspValid, // input + ab2s1_WrRsp, // input [15:0] + ab2s1_WrRspAddr, // input [ADDR_LMT-1:0] + + re2xy_go, // input + re2xy_NumLines, // input [31:0] + re2xy_Cont, // input + re2xy_test_cfg, // input [7:0] + + s12ab_TestCmp, // output + s12ab_ErrorInfo, // output [255:0] + s12ab_ErrorValid, // output + cr2s1_csr_write, + test_Resetb // input +); + + input logic Clk_400; // csi_top: Clk_400 + + output logic [ADDR_LMT-1:0] s12ab_WrAddr; // arb: write address + output logic [15:0] s12ab_WrTID; // arb: meta data + output logic [511:0] s12ab_WrDin; // arb: Cache line data + output logic s12ab_WrFence; // arb: write fence + output logic s12ab_WrEn; // arb: write enable. + input logic ab2s1_WrSent; // arb: write issued + input logic ab2s1_WrAlmFull; // arb: write fifo almost full + + output logic [ADDR_LMT-1:0] s12ab_RdAddr; // arb: Reads may yield to writes + output logic [15:0] s12ab_RdTID; // arb: meta data + output logic s12ab_RdEn; // arb: read enable + input logic ab2s1_RdSent; // arb: read issued + + input logic ab2s1_RdRspValid; // arb: read response valid + input logic ab2s1_UMsgValid; // arb: UMsg valid + input logic ab2s1_CfgValid; // arb: Cfg valid + input logic [15:0] ab2s1_RdRsp; // arb: read response header + input logic [ADDR_LMT-1:0] ab2s1_RdRspAddr; // arb: read response address + input logic [511:0] ab2s1_RdData; // arb: read data + + input logic ab2s1_WrRspValid; // arb: write response valid + input logic [15:0] ab2s1_WrRsp; // arb: write response header + input logic [ADDR_LMT-1:0] ab2s1_WrRspAddr; // arb: write response address + + input logic re2xy_go; // requestor: start of frame recvd + input logic [31:0] re2xy_NumLines; // requestor: number of cache lines + input logic re2xy_Cont; // requestor: continuous mode + input logic [7:0] re2xy_test_cfg; // requestor: 8-bit test cfg register. + + output logic s12ab_TestCmp; // arb: Test completion flag + output logic [255:0] s12ab_ErrorInfo; // arb: error information + output logic s12ab_ErrorValid; // arb: test has detected an error + input logic cr2s1_csr_write; + input logic test_Resetb; + + //------------------------------------------------------------------------------------------------------------------------ + // Rd FSM states + localparam Vrdfsm_WAIT = 2'h0; + localparam Vrdfsm_RESP = 2'h1; + localparam Vrdfsm_READ = 2'h2; + localparam Vrdfsm_DONE = 2'h3; + // Wr FSM states + localparam Vwrfsm_WAIT = 3'h0; + localparam Vwrfsm_WRITE = 3'h1; + localparam Vwrfsm_WRFENCE = 3'h2; + localparam Vwrfsm_UPDTFLAG = 3'h3; + localparam Vwrfsm_DONE = 3'h4; + + // Rd Poll FSM + localparam Vpollfsm_WAIT = 2'h0; + localparam Vpollfsm_READ = 2'h1; + localparam Vpollfsm_RESP = 2'h2; + localparam Vpollfsm_DONE = 2'h3; + + + reg [511:0] wrDin; // arb: Cache line data + reg s12ab_TestCmp_c; // arb: Test completion flag + + reg [20:0] Num_RdReqs; + reg [20:0] Num_RdRsp; + reg [1:0] RdFSM; + reg [1:0] PollFSM; + + reg [20:0] Num_WrReqs; + reg [2:0] WrFSM; + reg rd_go; + reg ErrorValid; + + logic ab2s1_RdRspValid_q; + logic [15:0] ab2s1_RdRspAddr_q; + logic [15:0] ab2s1_RdData_q; + logic [15:0] ab2s1_RdRsp_q; + logic [20:0] Num_RdRsp_q; + + wire [MDATA-2:0] Wrmdata = s12ab_WrAddr[MDATA-2:0]; + wire [MDATA-2:0] Rdmdata = s12ab_RdAddr[MDATA-2:0]; + assign s12ab_WrDin = (WrFSM == Vwrfsm_UPDTFLAG) ? {wrDin[511:0]} : {wrDin[511:17],s12ab_WrAddr[16:0]}; + + assign s12ab_RdTID = {1'b1, Rdmdata}; + assign s12ab_WrTID = {1'b0, Wrmdata}; + + always @(*) + begin + s12ab_ErrorValid = 1'b0; + if (ErrorValid ==1) s12ab_ErrorValid = 1'b1; + + s12ab_TestCmp_c = WrFSM==Vwrfsm_DONE + && RdFSM==Vrdfsm_DONE; + s12ab_RdEn = ( RdFSM == Vrdfsm_READ + ||PollFSM == Vpollfsm_READ ); + s12ab_WrEn = ( WrFSM == Vwrfsm_WRITE + ||WrFSM == Vwrfsm_UPDTFLAG ); + s12ab_WrFence = WrFSM == Vwrfsm_WRFENCE; + end + +// Write FSM + always @(posedge Clk_400) + begin + s12ab_TestCmp <= s12ab_TestCmp_c; + + case(WrFSM) /* synthesis parallel_case */ + Vwrfsm_WAIT: // Wait for CPU to start the test + begin + s12ab_WrAddr <= 0; + Num_WrReqs <= 1'b1; + wrDin <= {16{32'h0000_0001}}; + + if(re2xy_go) + begin + if(re2xy_NumLines != 0) + WrFSM <= Vwrfsm_WRITE; + else + begin + WrFSM <= Vwrfsm_UPDTFLAG; + wrDin <= {{14{32'h0000_0000}},{64{1'b1}}}; + end + end + end + + Vwrfsm_WRITE: // Move data from FPGA to CPU + begin + if(ab2s1_WrSent) + begin + s12ab_WrAddr <= s12ab_WrAddr + 1'b1; + Num_WrReqs <= Num_WrReqs + 1'b1; + + if(Num_WrReqs == re2xy_NumLines) + begin + WrFSM <= Vwrfsm_WRFENCE; + end + end + end + + Vwrfsm_WRFENCE: // Fence- guarantees data is written + begin + wrDin <= {{14{32'h0000_0000}},{64{1'b1}}}; + if(ab2s1_WrSent) + begin + WrFSM <= Vwrfsm_UPDTFLAG; + end + end + + Vwrfsm_UPDTFLAG: // FPGA -> CPU Message saying data is available + begin + if(ab2s1_WrSent) + begin + WrFSM <= Vwrfsm_DONE; + end + end + + default: + begin + WrFSM <= WrFSM; + end + endcase + + + + if (!test_Resetb) + begin + WrFSM <= Vwrfsm_WAIT; + s12ab_TestCmp <= 0; + end + + end + +// Read FSM + always @(posedge Clk_400) + begin + + case(re2xy_test_cfg[7:6]) + 2'h0: // polling method + begin + case(PollFSM) + Vpollfsm_WAIT: + begin + s12ab_RdAddr <= re2xy_NumLines[ADDR_LMT-1:0]; + if(WrFSM==Vwrfsm_DONE) + PollFSM <= Vpollfsm_READ; + end + Vpollfsm_READ: + begin + if(ab2s1_RdSent) + PollFSM <= Vpollfsm_RESP; + end + Vpollfsm_RESP: + begin + if(ab2s1_RdRspValid) + begin + if(ab2s1_RdData[63:32]==32'hffff_ffff) + begin + rd_go <= 1; + PollFSM <= Vpollfsm_DONE; + end + else + PollFSM <= Vpollfsm_READ; + end + end + default: //Vpollfsm_DONE + begin + PollFSM <= PollFSM; + end + endcase + end + 2'h1: // CSR Write + rd_go <= cr2s1_csr_write; + 2'h2: // UMsg Mode 0 (with Data) + rd_go <= ab2s1_UMsgValid && ab2s1_RdRsp[15]==1'b0 && ab2s1_RdRsp[2:0]=='b0; + 2'h3: // UMsg Mode 1 (with Hint+Data) + rd_go <= ab2s1_UMsgValid && ab2s1_RdRsp[15]==1'b1 && ab2s1_RdRsp[2:0]=='b0; + endcase + + case(RdFSM) /* synthesis parallel_case */ + Vrdfsm_WAIT: // Read Data payload + begin + Num_RdReqs <= 1'b1; + Num_RdRsp <= 0; + if(rd_go) + begin + s12ab_RdAddr <= 0; + if(re2xy_NumLines!=0) + RdFSM <= Vrdfsm_READ; + else + RdFSM <= Vrdfsm_DONE; + end + end + + Vrdfsm_READ: // Read N cache lines + begin + if(ab2s1_RdSent) + begin + s12ab_RdAddr <= s12ab_RdAddr + 1'b1; + Num_RdReqs <= Num_RdReqs + 1'b1; + + if(Num_RdReqs == re2xy_NumLines) + RdFSM <= Vrdfsm_RESP; + end + end + Vrdfsm_RESP: // Wait untill all reads complete + begin + if(Num_RdRsp==re2xy_NumLines) + RdFSM <= Vrdfsm_DONE; + end + + default: + begin + RdFSM <= RdFSM; + end + endcase + + if(ab2s1_RdRspValid) + Num_RdRsp <= Num_RdRsp + 1'b1; + + // Data check logic + // FPGA wrote N data lines with Addr = Data + // SW thread copied it to read buffer + // While FPGA Reading back N lines, check if Addr = Data + // Trigger Error if Addr != Data (Delayed 1 cycle : Timing) + ab2s1_RdRspValid_q <= ab2s1_RdRspValid; + ab2s1_RdRspAddr_q <= ab2s1_RdRspAddr[15:0]; + ab2s1_RdData_q <= ab2s1_RdData[15:0]; + ab2s1_RdRsp_q <= ab2s1_RdRsp; + Num_RdRsp_q <= Num_RdRsp; + + s12ab_ErrorInfo[31:0] <= ab2s1_RdData_q[15:0]; + s12ab_ErrorInfo[63:32] <= ab2s1_RdRspAddr_q[15:0]; + s12ab_ErrorInfo[95:64] <= ab2s1_RdRsp_q; + s12ab_ErrorInfo[127:96] <= Num_RdRsp_q; + + if(ab2s1_RdRspValid_q && (RdFSM == Vrdfsm_READ || RdFSM == Vrdfsm_RESP)) + begin + if (ab2s1_RdData_q[15:0] != ab2s1_RdRspAddr_q[15:0]) + begin + ErrorValid <= 1'b1; + end + + else + begin + ErrorValid <= 0; + end + end + + + + if (!test_Resetb) + begin + ErrorValid <= 0; + s12ab_RdAddr <= 0; + RdFSM <= Vrdfsm_WAIT; + PollFSM <= Vpollfsm_WAIT; + rd_go <= 0; + end + + end + +endmodule diff --git a/ase/scripts/ase_functions.py b/ase/scripts/ase_functions.py new file mode 100755 index 000000000000..ec6e658af33f --- /dev/null +++ b/ase/scripts/ase_functions.py @@ -0,0 +1,47 @@ +## Copyright(c) 2013-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +from __future__ import print_function +import os, re, sys + +################## FONT COLORS ################## +# Begin Red color +def begin_red_fontcolor(): + print("\033[1;31m") + +# End Red color +def end_red_fontcolor(): + print("\033[1;m") + +# Begin Green color +def begin_green_fontcolor(): + print("\033[32;1m") + +# End green color +def end_green_fontcolor(): + print("\033[0m") + + diff --git a/ase/scripts/ase_setup.sh b/ase/scripts/ase_setup.sh new file mode 100755 index 000000000000..22171dbabf9a --- /dev/null +++ b/ase/scripts/ase_setup.sh @@ -0,0 +1,114 @@ +#!/bin/bash +## Copyright(c) 2013-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +########################################################## +# +# ASE Setup file +# Author: Rahul R Sharma +# +# INSTRUCTIONS: +# * This file is a one-time per site setup +# * Before starting, it is a good idea to backup the file +# +########################################################## + +# Step 1: Setup License Server +# Contact your EDA Admin and set this to required values +# Modify following line +export LM_LICENSE_FILE=".." +if ! [ $LM_LICENSE_FILE ] ; then + echo "License variable not set, set this in line 43. Please check with your EDA admin" + exit +elif [ $LM_LICENSE_FILE == "" ] ; then + echo "License variable not set, set this in line 43. Please check with your EDA admin" + exit +fi + +# Step 2: Select one of the following tools +# - VCS +# - QuestaSim +# Uncomment setenv line with correct tool string +# +export MY_SIM_TOOL="VCS" +if ! [ $MY_SIM_TOOL ] ; then + echo "MY_SIM_TOOL has not been set up, please set this in line 57" + exit +fi + + +# +# Step 3: Set up the correct Tool strings +# Follow your sub-case closely and fill in the details +# Contact your EDA admin for more details +# +if [ $MY_SIM_TOOL == "VCS" ] ; then + # VCS setup + echo "VCS Tool setup" + # Modify this line + export VCS_HOME="" + export PATH="${VCS_HOME}/bin:${PATH}" + if ! [ $VCS_HOME ] ; then + echo "A) VCS_HOME has not been set up. Contact EDA Admin" + exit + elif [ $VCS_HOME == "" ] ; then + echo "B) VCS_HOME is empty. Contact EDA Admin" + exit + fi +elif [ $MY_SIM_TOOL == "QuestaSim" ] ; then + # QuestaSim setup + echo "QuestaSim tool setup" + # Modify this line. Contact EDA Admin + export QUESTA_HOME="" + if ! [ $QUESTA_HOME ] ; then + echo "A) QUESTA_HOME has not been set up. Contact EDA Admin" + exit + elif [ $QUESTA_HOME == "" ] ; then + echo "B) QUESTA_HOME is empty. Contact EDA Admin" + exit + fi + # Modify this line. Contact EDA Admin + export MGLS_LICENSE_FILE="" + if ! [ $MGLS_LICENSE_FILE ] ; then + echo "A) MGLS_LICENSE_FILE has not been set up. Contact EDA Admin" + exit + elif [ $MGLS_LICENSE_FILE == "" ] ; then + echo "B) MGLS_LICENSE_FILE is empty. Contact EDA Admin" + exit + fi + # LM_PROJECT env + export LM_PROJECT="PutMyLM_PROJECThere" + export MENTOR_TOP=$QUESTA_HOME + export MDLTECH=$QUESTA_HOME + export MTI_VCO_MODE=64 + export COMP64=1 +else + echo "The Simulation toolname supplied is not supported" + echo "ASE mode is supported in VCS and QuestaSim tools only" +fi + + + diff --git a/ase/scripts/create_ase_simbuild_env.sh b/ase/scripts/create_ase_simbuild_env.sh new file mode 100755 index 000000000000..753941c5ca62 --- /dev/null +++ b/ase/scripts/create_ase_simbuild_env.sh @@ -0,0 +1,111 @@ +#!/bin/bash +## Copyright(c) 2014-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +set -e + +################################## +# # +# Usage notes: # +# $ ./create_ase_simbuild_env.sh # +# # +################################## + +## Pseudocode +## ---------------------------------------------------------------------------------- +## * Check if 'ase' directory exists in current directory +## * FALSE: +## * Create references +## * $ASE_SRCDIR - Find running directory +## * Check if $ASE_SRCDIR/rtl/platform.vh and $ASE_SRCDIR/sw/ase_common.h exist +## * TRUE +## * Create 'ase' directory +## * Copy ase/Makefile script, then ase_regress.sh, and ase.cfg +## * grep/sed ASE_SRCDIR to point to retrieved source directory +## * FALSE +## * Error exit here +## * Copy 'ase' directory from +## * TRUE: +## * Error exit here +## + +echo "#################################################################" +echo "# #" +echo "# OPAE Intel(R) Xeon(R) + FPGA Library #" +echo "# AFU Simulation Environment (ASE) #" +echo "# #" +echo "#################################################################" + +## Check if 'ase' directory exists, else EXIT +if [ -d ${PWD}/ase ] ; +then + echo "ERROR: 'ase' already exists in this location.. Script will EXIT here.\n" + echo " Please run the script in another location.\n" + exit 1 +fi + +## Check for ASE script origin location +run_from_dir=$(dirname `readlink -e $0`)/ +echo "Script running from: $run_from_dir" + +## Check ASE source paths +check_rtlpath=${run_from_dir}/../rtl/platform.vh +check_swpath=${run_from_dir}/../sw/ase_common.h + +## Check SW and RTL paths +if [ -f ${check_rtlpath} ] && [ -f ${check_swpath} ] ; +then + echo "ASE Sources found... will proceed to create directory" + ase_srcdir=$(dirname $run_from_dir/) + ## Print ASE location + echo "ASE Source directory: $ase_srcdir" +else + echo "ERROR: ASE Sources could not be found\n" + echo " Check the Package Distribution documentation, and that the script hasn't been modified" + exit 1 +fi + + +## Create ASE Directory +mkdir ase +cp $ase_srcdir/Makefile ./ase/ +cp $ase_srcdir/ase.cfg ./ase/ +cp $ase_srcdir/ase_regress.sh ./ase/ + +## Change permission of 'ase' directory +chmod 644 ase/Makefile ase/ase.cfg +chmod 744 ase/ase_regress.sh + +## Modify ASE_SRCDIR location +## grep/sed and replace only the first instance of ASE_SRCDIR +sed -i 's#^ASE_SRCDIR.*#ASE_SRCDIR = '$ase_srcdir'#g' ase/Makefile + +## Print information about ase_sources.mk +echo "" +echo "ASE simulator build environment created" +echo "Next steps: This simulation environment must be configured for an AFU" +echo " See ASE Documentation on usage steps" +echo "" diff --git a/ase/scripts/env_check.sh b/ase/scripts/env_check.sh new file mode 100755 index 000000000000..c5cb7bfe3c85 --- /dev/null +++ b/ase/scripts/env_check.sh @@ -0,0 +1,188 @@ +#!/bin/bash +## Copyright(c) 2016-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +os=$(uname -s | tr '\[A-Z\]' '\[a-z\]') +kernel_rel=$(uname -r) +arch=$(uname -p) +dist_id=$(lsb_release -i -s | tr '\[A-Z\]' '\[a-z\]') +dist_ver=$(lsb_release -r -s | tr '\[A-Z\]' '\[a-z\]') +dist_code=$(lsb_release -c -s | tr '\[A-Z\]' '\[a-z\]') +shm_testfile="/dev/shm/$USER.ase_envcheck" + +## Version greater than tester function +function version_check() +{ + test "$(echo "$@" | tr " " "\n" | sort -V | head -n 1)" != "$1"; +} + +## Print header, and basic info +echo "#################################################################" +echo "# #" +echo "# Intel(R) Xeon(R) + FPGA OPAE Library #" +echo "# AFU Simulation Environment (ASE) #" +echo "# #" +echo "#################################################################" +echo " Checking Machine... " +echo " Operating System = ${os} " +echo " Kernel Release = ${kernel_rel}" +echo " Machine = ${arch}" +echo " Distro ID = ${dist_id}" +echo " Distro Version = ${dist_ver}" +echo " Distro Code = ${dist_code}" +echo "-----------------------------------------------------------" + +## If Machine is not 64-bit, flash message +if [ "$os" == "linux" ]; then + if [ "$arch" == "x86_64" ]; then + echo " [INFO] 64-bit Linux found" + else + echo " [WARN] 32-bit Linux found --- ASE works best on 64-bit Linux !" + fi + # Check distro + if [ "$dist_id" == "ubuntu" ] ; then + if version_check "$dist_ver" "12.04"; then + echo " [INFO] Ubuntu $dist_ver found" + else + echo " [WARN] ASE behavior on Ubuntu $dist_ver is unknown !" + fi + elif [ "$dist_id" == "suse linux" ] ; then + echo " [INFO] SLES found" + if version_check "$dist_ver" "10"; then + echo " [INFO] SLES version seems to be OK" + else + echo " [WARN] ASE behaviour on SLES < 11 is unknown !" + fi + else + echo " [WARN] Machine is running an unknown Distro --- ASE compatibility unknown !" + fi +else + echo " [WARN] Non-Linux distro found --- ASE is not supported on non-Linux platforms !" +fi + + +echo "-----------------------------------------------------------" + +## Check shell environment +shell=$(basename "$SHELL") +echo " [INFO] SHELL identified as ${shell} (located \"$SHELL\")" +if [ "$shell" == "bash" ] ; then + echo " [INFO] SHELL ${shell} version : \"$BASH_VERSION\"" +elif [ "$shell" == "zsh" ] ; then + echo " [INFO] SHELL ${shell} version : $(zsh --version)" +elif [ "$shell" == "tcsh" ] ; then + echo " [INFO] SHELL ${shell} version : $(tcsh --version)" +elif [ "$shell" == "csh" ] ; then + echo " [INFO] SHELL ${shell} version : $(csh --version)" +else + echo " [WARN] SHELL ${shell} is unknown !" +fi +echo "-----------------------------------------------------------" + +## Check if /dev/shm is mounted, try writing then deleting a file for access check +if [ -d /dev/shm/ ]; then + echo " [INFO] /dev/shm is accessible ... testing further" + echo " [INFO] Testing with file \"$shm_testfile\"" + touch "$shm_testfile" + echo "$USER" >> "$shm_testfile" + readback_shmfile=$(cat "$shm_testfile") + if [ "$readback_shmfile" == "$USER" ] ; then + echo " [INFO] SHM self-check completed successfully." + else + echo " [WARN] SHM self-check failed !" + fi + rm "$shm_testfile" +else + echo " [WARN] /dev/shm seems to be inaccessible ! " + echo " [WARN] ASE uses this location for data sharing between SW and simulator" + echo " [WARN] Please mount this location before proceeding... see 'man shm_overview'" +fi + +echo "-----------------------------------------------------------" + +## GCC version check +# GCCVERSION=$(gcc --version | grep ^gcc | sed 's/^.* //g') +GCCVERSION=$(gcc -dumpversion) +echo " [INFO] GCC version found : $GCCVERSION" +if version_check "$GCCVERSION" "4.4"; then + echo " [INFO] GCC version seems to be OK" +else + echo " [WARN] Possible incompatible GCC found in path" + echo " [INFO] ASE recommends using GCC version > 4.4" +fi +echo "-----------------------------------------------------------" + +## Python version check +PYTHONVER=$(python -c 'import sys; print(".".join(map(str, sys.version_info[:3])))') +echo " [INFO] Python version found : $PYTHONVER" +if version_check "$PYTHONVER" "2.7"; then + echo " [INFO] Python version seems to be OK" +else + echo " [WARN] Possible incompatible Python found in path" + echo " [INFO] ASE recommends using Python version > 2.7" +fi +echo "-----------------------------------------------------------" + +## RTL tool check +if [ "$VCS_HOME" ] ; then + echo " [INFO] env(VCS_HOME) is set." + if [ -x "$(command -v vcs)" ] && [ -x "$(command -v vlogan)" ] && [ -x "$(command -v vhdlan)" ] ; then + echo " [INFO] $(type vhdlan)" + echo " [INFO] $(type vlogan)" + echo " [INFO] $(type vcs)" + else + echo " [WARN] VCS commands (vcs, vlogan, vhdlan) was not found !" + echo " [WARN] Check VCS settings !" + fi +elif [ "$QUESTA_HOME" ] ; then + echo " [INFO] env(QUESTA_HOME) is set." + if [ -x "$(command -v vlog)" ] && [ -x "$(command -v vlib)" ] && [ -x "$(command -v vsim)" ] ; then + echo " [INFO] $(type vlib)" + echo " [INFO] $(type vlog)" + echo " [INFO] $(type vsim)" + else + echo " [WARN] VCS commands (vcs, vlogan, vhdlan) was not found !" + echo " [WARN] Check VCS settings !" + fi +else + echo " [WARN] No Compatible RTL tool seems to be available !" +fi + +echo "-----------------------------------------------------------" +## Quartus version not available +if [ "$QUARTUS_HOME" ] ; then + echo " [INFO] env(QUARTUS_HOME) is set." + if [ -x "$(command -v quartus)" ] ; then + echo " [INFO] $(type quartus)" + else + echo " [WARN] quartus command not found !" + echo " [WARN] Check Quartus settings !" + fi +else + echo " [WARN] Quartus not found, ASE won't run Altera eda_lib library simulation !" + echo " [INFO] Alternately, if you have a non-standard Quartus install, the Makefile may need editing" +fi +echo "-----------------------------------------------------------" diff --git a/ase/scripts/generate_ase_environment.py b/ase/scripts/generate_ase_environment.py new file mode 100755 index 000000000000..276e0aa65ebe --- /dev/null +++ b/ase/scripts/generate_ase_environment.py @@ -0,0 +1,346 @@ +#!/usr/bin/env python +## Copyright(c) 2013-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +####################################################################### +# generate_ase_environment.py : Generate AFU paths, include directories as a +# Makefile snippet for ASE builds +# +# Author: Rahul R Sharma +# +# After running script, you will see: +# * A list of VHDL files +# * A list of {System}Verilog files +# * ase_common.mk: Prepares variables pointing to the file lists and +# gueses include directories. The ASE files' absolute paths are also +# calculated +# * A synopsys_sim.setup file, applicable to VCS builds, QUESTA will +# ignore this +# +# Mar 2014 RRS Original version +# Oct 2014 RRS Python 3.3 compatibility +# Version check added +# May 2017 RRS Platform type support added +# +####################################################################### + +# Future-proofing against Python 3 syntax changes in 'print' +from __future__ import print_function +import argparse +import ase_functions +import os, re, sys +from collections import defaultdict +from fnmatch import fnmatch + +reload(sys) +sys.setdefaultencoding('utf8') + +if sys.version_info < (2, 7): + import commands +else: + import subprocess + +### Supported file extensions +# USERs may modify this if needed +VLOG_EXTENSIONS = [ ".svh", ".sv", ".vs", ".v" ] +VHD_EXTENSIONS = [ ".vhd", ".vhdl" ] + +VHDL_FILE_LIST = os.environ['PWD'] + "/vhdl_files.list" +VLOG_FILE_LIST = os.environ['PWD'] + "/vlog_files.list" +TOOL_BRAND = "VCS" + +# Forbidden characters +SPECIAL_CHARS='\[]~!@#$%^&*(){}:;+$\'' + +########################################################## +### ### +### DO NOT MODIFY BELOW THIS COMMENT BLOCK ### +### ### +########################################################## +# Global variables +arg_list = [] +tolowarg_list = [] +valid_dirlist = [] + +special_chars_in_path = 0 + +def remove_dups(filepath, exclude=None): + import hashlib + include = lambda f : exclude is None or not fnmatch(f, exclude) + files = [] + hashes = dict() + with open(filepath, 'r') as fd: + files = filter(lambda l : l.strip() != '', fd.readlines()) + files = [f.strip() for f in files] + for f in files: + with open(f, 'r') as fd: + m = hashlib.md5() + m.update(fd.read()) + h = m.digest() + if h not in hashes and include(f): + hashes[h] = f + text = '\n'.join(sorted(hashes.values(), key=os.path.basename)) + with open(filepath, 'w') as fd: + fd.write(text) + return text + + + +#################### Run command and get string output ####################### +def commands_getoutput(cmd): + if sys.version_info < (2,7): + return commands.getoutput(cmd) + else: + byte_out = subprocess.check_output(cmd.split()) + str_out = byte_out.decode("utf-8") + return str_out + +############################# Print Help ##################################### +def show_help(): + ase_functions.begin_red_fontcolor() + print("INCORRECT command, CORRECT (required) usage is:") + print("python generate_ase_environment.py [dir 2] ... [dir n] [-t ] [-p ]") + print("") + print("Required switches => ") + print(" => Atleast one sources directory is required") + print(" [dir2]...[dir n] => Other optional directories with sources") + print("") + print("Optional switches => ") + print(" -h,--help => Show this help message") + print(" -t,--tool => Enter tool type as 'VCS' or 'QUESTA'") + print(" -p,--plat => Enter platform type as 'intg_xeon' or 'discrete'") + print("") + ase_functions.end_red_fontcolor() + +########################### Has duplicates ################################### +def has_duplicates(word_dict): + dups = filter(lambda (k,v) : len(v) > 1, word_dict.items()) + if dups: + print("Duplicates found -") + for k,v in dups: + print(k) + print('\n'.join(['\t{}'.format(l) for l in v])) + return True + return False + +######################## Close file and exit ################################# +def print_instructions(): + print("") + ase_functions.begin_green_fontcolor() + print("NOTES TO USER => ") + print("* This script assumes File Extensions: ") + print(" * VHDL : .vhd") + print(" * V/SV : .sv .vs .v") + print(" * If you use arbitrary extensions, please edit this script to reflect them, and re-run the script") + print("* See ase_sources.mk and check for correctness") + print("* See if DUT_INCDIR has all the locations mentioned") + print(" * If a directory is missing, append it separated by '+' symbol") + ase_functions.end_green_fontcolor() + print("") + +############################################################################# +## Script begins here ## +############################################################################# +print("#################################################################") +print("# #") +print("# OPAE Intel(R) Xeon(R) + FPGA Library #") +print("# AFU Simulation Environment (ASE) #") +print("# #") +print("#################################################################") +parser = argparse.ArgumentParser() +parser.add_argument('dirlist', nargs='+', + help='list of directories to scan') +parser.add_argument('-t', '--tool', choices=['VCS', 'QUESTA'], default='VCS', + help='simulator tool to use, default is VCS') +parser.add_argument('-p', '--plat', choices=['intg_xeon', 'discrete'], default='intg_xeon', + help='FPGA Platform to simulate') +parser.add_argument('-x', '--exclude', default=None, + help='file name pattern to exclude') +args = parser.parse_args() +tool_type = args.tool +TOOL_BRAND = args.tool +PLAT_TYPE = {'intg_xeon': 'FPGA_PLATFORM_INTG_XEON', + 'discrete' : 'FPGA_PLATFORM_DISCRETE'}.get(args.plat) +print("\nTool Brand : ", TOOL_BRAND) +print("\nPlatform Type : ", PLAT_TYPE) +####################################################################### +# Prepare list of candidate directories +print ("Valid directories supplied => "); +valid_dirlist = filter(lambda p : os.path.exists(p), args.dirlist) +str_dirlist = " ".join(valid_dirlist) +if len(valid_dirlist) == 0: + ase_functions.begin_red_fontcolor() + print("No Valid source directories were specified ... please re-run script with legal directory name") + show_help() + ase_functions.end_red_fontcolor() + sys.exit(0) + +######################################################## +### Write Makefile snippet ### +######################################################## +fd = open("ase_sources.mk", "w") +# Print Information in ase_sources.mk +fd.write("##############################################################\n") +fd.write("# #\n") +fd.write("# Xeon(R) + FPGA AFU Simulation Environment #\n") +fd.write("# File generated by ase/scripts/generate_ase_environment.py #\n") +fd.write("# #\n") +fd.write("##############################################################\n") +fd.write("\n") + +######################################################## +# Check if VHDL files exist, populate if any +######################################################## +print("") +print("Finding VHDL files ... ") +str = "" +vhdl_filepaths = "" +for extn in VHD_EXTENSIONS: + str = str + commands_getoutput("find -L " + str_dirlist + " -type f -name *" + extn) + if len(str) != 0: + str = str + "\n" +if len(str.strip()) != 0: + open(VHDL_FILE_LIST, "w").write(str) + vhdl_filepaths = str + print("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST) + fd.write("DUT_VHD_SRC_LIST = " + VHDL_FILE_LIST + " \n\n") +else: + print("No VHDL files were found !") + +######################################################## +# Check if V/SV files exist, populate if any +######################################################## +print("") +print("Finding {System}Verilog files ... ") +str = "" +vlog_filepaths = "" +cmd = "" +for extn in VLOG_EXTENSIONS: + cmd = "find -L " + str_dirlist + " -type f -name *pkg*" + extn + str = str + commands_getoutput(cmd) + if len(str) != 0: + str = str + "\n" +for extn in VLOG_EXTENSIONS: + cmd = "find -L " + str_dirlist + " -type f -name *" + extn + " -not -name *pkg*" + extn + str = str + commands_getoutput(cmd) + if len(str) != 0: + str = str + "\n" +if len(str) != 0: + open(VLOG_FILE_LIST, "w").write(str) + vlog_filepaths = str + print("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST) + fd.write("DUT_VLOG_SRC_LIST = " + VLOG_FILE_LIST + " \n\n") +else: + print("No {System}Verilog files were found !") + +vlog_filepaths = remove_dups(VLOG_FILE_LIST, args.exclude) + +######################################################## +# Recursively find and add directory locations for VH +######################################################## +print("") +print("Finding include directories ... ") +str = commands_getoutput("find -L " + str_dirlist + " -type d") +str = str.replace("\n", "+") +if len(str) != 0: + print("DUT_INCDIR = " + str) + fd.write("DUT_INCDIR = " + str + "\n\n") + +############################################# +# Find ASE HW files ### +############################################# +pwd = commands_getoutput("pwd").strip() + +############################################# +# Update SIMULATOR +############################################# +fd.write("SIMULATOR ?= ") +fd.write(TOOL_BRAND) +fd.write("\n\n") + +############################################# +# Update ASE_PLATFORM +############################################# +fd.write("ASE_PLATFORM ?= ") +fd.write(PLAT_TYPE) +fd.write("\n\n") + +fd.close() + +############################################# +# Write tool specific scripts +############################################# +if tool_type == "VCS": + print ("Generating VCS specific Runtime TCL scripts") + ### Write Synopsys Setup file& TCL script ### + open("synopsys_sim.setup", "w").write("WORK > DEFAULT\nDEFAULT : ./work\n") + open("vcs_run.tcl", "w").write("dump -depth 0 \ndump -aggregates -add / \nrun \nquit\n") +elif tool_type == "QUESTA": + ### Generate .DO file ### + print ("Generating Modelsim specific scripts") + open("vsim_run.tcl", "w").write("add wave -r /* \nrun -all\n") + +############################################# +# Print special character message +############################################# +if (special_chars_in_path == 1): + ase_functions.begin_red_fontcolor() + print("Special characters found in path name --- RTL simulator tools may have trouble deciphering paths") + ase_functions.end_red_fontcolor() + +############################################# +# Module repetition check +############################################# +vhdl_filepaths = vhdl_filepaths.replace("\n", " ").split() +vlog_filepaths = vlog_filepaths.replace("\n", " ").split() + +all_filepaths = vhdl_filepaths + vlog_filepaths +module_namelist = [] +module_files = defaultdict(list) + +for filepath in all_filepaths: + file_content = open(filepath).readlines() + for line in file_content: + strip_line = line.strip() + if strip_line.startswith("//"): + continue + elif strip_line.startswith("module"): + words = strip_line.split() + modname = words[1] + module_files[modname].append(filepath) + module_namelist.append(modname) + +ase_functions.begin_red_fontcolor() +if (has_duplicates(module_files) == True): + print("\n") + print("Duplicate module names were found in the RTL file lists.") + print("Please remove them manually as RTL compilation is expected to FAIL !") +ase_functions.end_red_fontcolor() + +############################################# +# Print instructions +############################################# +print_instructions() diff --git a/ase/scripts/ipc_clean.py b/ase/scripts/ipc_clean.py new file mode 100755 index 000000000000..6bc15587aa78 --- /dev/null +++ b/ase/scripts/ipc_clean.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python +## Copyright(c) 2013-2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +from __future__ import print_function +import ase_functions +import os, re, sys, signal + +if sys.version_info < (2, 7): + import commands +else: + import subprocess + +from subprocess import call + +#################### Run command and get string output ####################### +def commands_getoutput(cmd): + if sys.version_info < (2,7): + return commands.getoutput(cmd) + else: + byte_out = subprocess.check_output(cmd.split()) + str_out = byte_out.decode("utf-8") + return str_out + +MQUEUE_MOUNT = "./work/" +SHM_MOUNT = "/dev/shm/" +GLOBAL_LIST = MQUEUE_MOUNT + "/.ase_ipc_global" +USER = os.getenv("USER") + +print("############################################################") +print("# #") +print("# ASE IPC Cleanup script #") +print("# #") +print("############################################################") + +## Check if locations are mounted correctly +print_admin = 0 +if (os.path.isdir(SHM_MOUNT) == False): + print("** WARNING: ", SHM_MOUNT, " location is not mounted in this system. **") + print_admin = 1 + +## Ask Admin to mount /dev/shm +if print_admin == 1: + print("Please contact your Linux administrator for help.") + print("PLEASE NOTE: ASE will continue to function, but should IPC constructs misbehave, some of the constructs listed in ", GLOBAL_LIST, " will need to be removed manually.") + +## Straightforward delete operation ## +if print_admin == 0: + print("IPC mounts seem to be readable... will attempt cleaning up IPC constructs by user '", USER,"'") + problem_ipc = commands_getoutput("find " + SHM_MOUNT + " -type f -user " + USER ).split("\n") + for ipc in problem_ipc: + if (os.path.isfile(ipc) == True): + print("Removing ", ipc) + os.unlink(ipc) + +## Remove ready file ## +print("Removing .ase_ready file ... ") +ready_list = commands_getoutput("find . -name .ase_ready.pid").split("\n") +for rfile in ready_list: + rfile = rfile.replace("\n", "") + if (os.path.isfile(rfile) == True): + print(rfile) + os.unlink(rfile) + +## Kill all ase_simv processes started by by $USER +cleanme_input = raw_input("Type 'y' to clean up all zombie ase_simv processes : ") +if cleanme_input == "y": + print("Going ahead with cleaning up ASE processes opened by ", USER) + os.system("pgrep ase_simv -u " + USER + " | xargs kill -9 ") +else: + print("Skipping process removal") + diff --git a/ase/sw/app_backend.c b/ase/sw/app_backend.c new file mode 100644 index 000000000000..048d191df5e7 --- /dev/null +++ b/ase/sw/app_backend.c @@ -0,0 +1,1499 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: ASE native SW application interface (bare-bones ASE access) + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + */ + +#define _GNU_SOURCE + +#include "ase_common.h" + +// Log-level +int glbl_loglevel = ASE_LOG_MESSAGE; + +// MMIO Mutex Lock, initilize it here +pthread_mutex_t mmio_port_lock = PTHREAD_MUTEX_INITIALIZER; + +// CSR map storage +struct buffer_t *mmio_region; + +// UMAS region +struct buffer_t *umas_region; + +// Workspace metadata table +struct wsmeta_t *wsmeta_head = (struct wsmeta_t *) NULL; +struct wsmeta_t *wsmeta_end = (struct wsmeta_t *) NULL; + +// Buffer index count +int asebuf_index_count; // global count/index +int userbuf_index_count; // User count/index + +// Timestamp char array +char *tstamp_string; + +// Application lock file path +char app_ready_lockpath[ASE_FILEPATH_LEN]; + +// MMIO Scoreboard (used in APP-side only) +struct mmio_scoreboard_line_t { + uint64_t data; + int tid; + bool tx_flag; + bool rx_flag; +}; +volatile struct mmio_scoreboard_line_t mmio_table[MMIO_MAX_OUTSTANDING]; + +// Debug logs +#ifdef ASE_DEBUG +FILE *fp_pagetable_log = (FILE *) NULL; +FILE *fp_mmioaccess_log = (FILE *) NULL; +#endif + +/* + * MMIO Read response watcher + */ +// MMIO Tid +int glbl_mmio_tid; + +// Tracker thread Id +pthread_t mmio_watch_tid; + +// MMIO Response packet handoff control +mmio_t *mmio_rsp_pkt; + +/* + * UMsg listener/packet + */ +// UMsg Watch TID +pthread_t umsg_watch_tid; + +// UMsg byte offset +const int umsg_byteindex_arr[] = { + 0x0, 0x1040, 0x2080, 0x30C0, 0x4100, 0x5140, 0x6180, 0x71C0 +}; + +// UMsg address array +char *umsg_addr_array[NUM_UMSG_PER_AFU]; + +// UMAS initialized flag +volatile int umas_init_flag; + +// Time taken calc +struct timespec start_time_snapshot, end_time_snapshot; +unsigned long long runtime_nsec; + +// Exist status flags +static uint32_t session_exist_status; +static uint32_t mq_exist_status; +static uint32_t mmio_exist_status; +static uint32_t umas_exist_status; + + +/* + * MMIO Generate TID + * - Creation of TID must be atomic + */ +uint32_t generate_mmio_tid(void) +{ + // Return value + uint32_t ret_mmio_tid; + + while (count_mmio_tid_used() == MMIO_MAX_OUTSTANDING) { +#ifdef ASE_DEBUG + ASE_INFO("MMIO TIDs have run out --- waiting !\n"); +#endif + usleep(10000); + } + + // Increment and mask + ret_mmio_tid = glbl_mmio_tid & MMIO_TID_BITMASK; + glbl_mmio_tid++; + + // Return ID + return ret_mmio_tid; +} + + +/* + * THREAD: MMIO Read thread watcher + */ +void *mmio_response_watcher(void *arg) +{ + // Mark as thread that can be cancelled anytime + pthread_setcanceltype(PTHREAD_CANCEL_ENABLE, NULL); + + mmio_rsp_pkt = (struct mmio_t *) ase_malloc(sizeof(struct mmio_t)); + int ret; + int slot_idx; + +#ifdef ASE_DEBUG + char mmio_type[3]; +#endif + + // start watching for messages + while (mmio_exist_status == ESTABLISHED) { + memset((void *) mmio_rsp_pkt, 0xbc, sizeof(mmio_t)); + + // If received, update global message + ret = + mqueue_recv(sim2app_mmiorsp_rx, (char *) mmio_rsp_pkt, + sizeof(mmio_t)); + if (ret == ASE_MSG_PRESENT) { +#ifdef ASE_DEBUG + // Logging event + print_mmiopkt(fp_mmioaccess_log, "Got ", + mmio_rsp_pkt); + if (mmio_rsp_pkt->write_en == MMIO_WRITE_REQ) { + ase_string_copy(mmio_type, "WR\0", 3); + } else if (mmio_rsp_pkt->write_en == MMIO_READ_REQ) { + ase_string_copy(mmio_type, "RD\0", 3); + } + + ASE_DBG + ("mmio_watcher => %03x, %s, %d, %x, %016llx\n", + mmio_rsp_pkt->tid, mmio_type, + mmio_rsp_pkt->width, mmio_rsp_pkt->addr, + mmio_rsp_pkt->qword[0]); + +#endif + + // Find scoreboard slot number to update + slot_idx = + get_scoreboard_slot_by_tid(mmio_rsp_pkt->tid); + + if (slot_idx == 0xFFFF) { + ASE_ERR + ("get_scoreboard_slot_by_tid() found a bad slot !"); + raise(SIGABRT); + } else { + // MMIO Read response (for credit count only) + if (mmio_rsp_pkt->write_en == + MMIO_READ_REQ) { + mmio_table[slot_idx].tid = + mmio_rsp_pkt->tid; + mmio_table[slot_idx].data = + mmio_rsp_pkt->qword[0]; + mmio_table[slot_idx].tx_flag = + true; + mmio_table[slot_idx].rx_flag = + true; + } + // MMIO Write response (for credit count only) + else if (mmio_rsp_pkt->write_en == + MMIO_WRITE_REQ) { + mmio_table[slot_idx].tx_flag = + false; + mmio_table[slot_idx].rx_flag = + false; + } +#ifdef ASE_DEBUG + else { + ASE_ERR + ("Illegal MMIO request found -- must not happen !\n"); + } +#endif + } + } + } + + return 0; +} + + +/* + * Interrupt request (FPGA->CPU) watcher + */ +// void *intr_request_watcher() +// { + +// } + + +/* + * Send SW Reset + */ +void send_swreset(void) +{ + ASE_MSG("\n"); + ASE_MSG("Issuing Soft Reset... \n"); + while (count_mmio_tid_used() != 0) { + sleep(1); + } + + // Sending reset trigger + char ase_reset_msg[ASE_MQ_MSGSIZE]; + snprintf(ase_reset_msg, ASE_MQ_MSGSIZE, "AFU_RESET 1"); + ase_portctrl(ase_reset_msg); + + usleep(1); + snprintf(ase_reset_msg, ASE_MQ_MSGSIZE, "AFU_RESET 0"); + ase_portctrl(ase_reset_msg); +} + + +/* + * Send SIMKILL + */ +void send_simkill(int n) +{ + ASE_ERR("User Interrupt was seen... SW application will exit\n"); + + // Simkill + char ase_simkill_msg[ASE_MQ_MSGSIZE]; + memset(ase_simkill_msg, 0, ASE_MQ_MSGSIZE); + snprintf(ase_simkill_msg, ASE_MQ_MSGSIZE, "ASE_SIMKILL 0"); + ase_portctrl(ase_simkill_msg); + + // Deinitialize session + session_exist_status = NOT_ESTABLISHED; + session_deinit(); + + exit(0); +} + + +/* + * Session Initialize + * Open the message queues to ASE simulator + */ +void session_init(void) +{ + FUNC_CALL_ENTRY; + + // Start clock + clock_gettime(CLOCK_MONOTONIC, &start_time_snapshot); + + // Current APP PID + pid_t lockread_app_pid; + FILE *fp_app_lockfile; + + // Session setup + if (session_exist_status != ESTABLISHED) { + + // Set loglevel + glbl_loglevel = ase_calc_loglevel(); + + setvbuf(stdout, NULL, (int) _IONBF, (size_t) 0); + + ipc_init(); + + // Initialize ase_workdir_path + ASE_MSG("ASE Session Directory located at =>\n"); + ASE_MSG("%s\n", ase_workdir_path); + + // Craft a .app_lock.pid lock filepath string + memset(app_ready_lockpath, 0, ASE_FILEPATH_LEN); + snprintf(app_ready_lockpath, ASE_FILEPATH_LEN, "%s/%s", + ase_workdir_path, APP_LOCK_FILENAME); + + // Read ready file and check sanity + ase_read_lock_file(ase_workdir_path); + + // If .app_lock.pid exists, then exit immediately (there is another session using simulator) + if (access(app_ready_lockpath, F_OK) == 0) { + // Read the PID of the running application + fp_app_lockfile = fopen(app_ready_lockpath, "r"); + if (fp_app_lockfile == NULL) { + ASE_ERR + ("Error opening Application lock file path, EXITING\n"); + exit(1); + } else { + if (fscanf + (fp_app_lockfile, "%d\n", + &lockread_app_pid) != 0) { + ASE_ERR + ("ASE session in env(ASE_WORKDIR) is currently used by PID=%d\n", + lockread_app_pid); + } else { + ASE_ERR + ("Error reading PID of application using ASE, EXITING\n"); + } + } + + // Issue error message and exit + fclose(fp_app_lockfile); + ASE_ERR + ("ASE was found to be running with another application !\n"); + ASE_ERR + ("This will cause an unstable simulation - Application WILL EXIT now !\n"); + ASE_ERR("\n"); + ASE_ERR("If you think this is in error:\n"); + ASE_ERR + (" - Manually delete $ASE_WORKDIR/.app_lock.pid file\n"); + ASE_ERR + (" - Close any ASE simulator is running from the $ASE_WORKDIR directory\n"); + exit(1); + } else { + // Open lock file for writing + fp_app_lockfile = fopen(app_ready_lockpath, "w"); + if (fp_app_lockfile == NULL) { + ASE_ERR + ("Application lockfile could not opened for writing in env(ASE_WORKDIR) !"); + exit(1); + } else { + // Write PID into lockfile + fprintf(fp_app_lockfile, "%d\n", getpid()); + } + + // close lockfile + fclose(fp_app_lockfile); + } + + // Register kill signals to issue simkill + signal(SIGTERM, send_simkill); + signal(SIGINT, send_simkill); + signal(SIGQUIT, send_simkill); + signal(SIGHUP, send_simkill); + + // When bad stuff happens, print backtrace + signal(SIGSEGV, backtrace_handler); + signal(SIGBUS, backtrace_handler); + signal(SIGABRT, backtrace_handler); + + // Ignore SIGPIPE + signal(SIGPIPE, SIG_IGN); + + + ASE_INFO("Initializing simulation session ... \n"); + + + app2sim_alloc_tx = + mqueue_open(mq_array[0].name, mq_array[0].perm_flag); + app2sim_mmioreq_tx = + mqueue_open(mq_array[1].name, mq_array[1].perm_flag); + app2sim_umsg_tx = + mqueue_open(mq_array[2].name, mq_array[2].perm_flag); + sim2app_alloc_rx = + mqueue_open(mq_array[3].name, mq_array[3].perm_flag); + sim2app_mmiorsp_rx = + mqueue_open(mq_array[4].name, mq_array[4].perm_flag); + app2sim_portctrl_req_tx = + mqueue_open(mq_array[5].name, mq_array[5].perm_flag); + app2sim_dealloc_tx = + mqueue_open(mq_array[6].name, mq_array[6].perm_flag); + sim2app_dealloc_rx = + mqueue_open(mq_array[7].name, mq_array[7].perm_flag); + sim2app_portctrl_rsp_rx = + mqueue_open(mq_array[8].name, mq_array[8].perm_flag); + sim2app_intr_request_rx = + mqueue_open(mq_array[9].name, mq_array[9].perm_flag); + + // Message queues have been established + mq_exist_status = ESTABLISHED; + + // Issue soft reset + send_swreset(); + + // Page table tracker (optional logger) +#ifdef ASE_DEBUG + // Create debug log of page table + fp_pagetable_log = fopen("app_pagetable.log", "w"); + if (fp_pagetable_log == NULL) { + ASE_ERR + ("APP pagetable logger initialization failed !\n"); + } else { + ASE_MSG("APP pagetable logger initialized\n"); + } + + // Debug log of MMIO + fp_mmioaccess_log = fopen("app_mmioaccess.log", "w"); + if (fp_mmioaccess_log == NULL) { + ASE_ERR + ("APP MMIO access logger initialization failed !\n"); + } else { + ASE_MSG("APP MMIO access logger initialized\n"); + } +#endif + + + // Set MMIO Tid to 0 + glbl_mmio_tid = 0; + + // Thread error integer + int thr_err; + + // Start MSI-X watcher thread + // ASE_MSG("Starting Interrupt watcher ... "); + + // Session start + ASE_MSG("Session started\n"); + + // Send portctrl command to start a session + char session_ctrlcmd[ASE_MQ_MSGSIZE]; + memset(session_ctrlcmd, 0, ASE_MQ_MSGSIZE); + snprintf(session_ctrlcmd, ASE_MQ_MSGSIZE, "ASE_INIT %d", + getpid()); + ase_portctrl(session_ctrlcmd); + + // Wait till session file is created + poll_for_session_id(); + tstamp_string = (char *) ase_malloc(20); + // tstamp_string = get_timestamp(0); + get_timestamp(tstamp_string); + + // Creating CSR map + + ASE_MSG("Creating MMIO ...\n"); + + mmio_region = (struct buffer_t *) + ase_malloc(sizeof(struct buffer_t)); + mmio_region->memsize = MMIO_LENGTH; + mmio_region->is_mmiomap = 1; + allocate_buffer(mmio_region, NULL); + mmio_afu_vbase = + (uint64_t *) ((uint64_t) mmio_region->vbase + + MMIO_AFU_OFFSET); + mmio_exist_status = ESTABLISHED; + + ASE_MSG("AFU MMIO Virtual Base Address = %p\n", + (void *) mmio_afu_vbase); + + + // Create UMSG region + + umas_init_flag = 0; + ASE_MSG("Creating UMAS ... \n"); + + umas_region = (struct buffer_t *) + ase_malloc(sizeof(struct buffer_t)); + umas_region->memsize = UMAS_REGION_MEMSIZE; //UMAS_LENGTH; + umas_region->is_umas = 1; + allocate_buffer(umas_region, NULL); + umsg_umas_vbase = + (uint64_t *) ((uint64_t) umas_region->vbase); + umas_exist_status = ESTABLISHED; + umsg_set_attribute(0x0); + ASE_MSG("UMAS Virtual Base address = %p\n", + (void *) umsg_umas_vbase); + + // Start MMIO read response watcher watcher thread + ASE_MSG("Starting MMIO Read Response watcher ... \n"); + thr_err = + pthread_create(&mmio_watch_tid, NULL, + &mmio_response_watcher, NULL); + if (thr_err != 0) { + ASE_ERR("FAILED\n"); + BEGIN_RED_FONTCOLOR; + perror("pthread_create"); + END_RED_FONTCOLOR; + exit(1); + } else { + ASE_MSG("SUCCESS\n"); + } + + ASE_MSG("Starting UMsg watcher ... \n"); + + // Initiate UMsg watcher + thr_err = pthread_create(&umsg_watch_tid, NULL, &umsg_watcher, + NULL); + if (thr_err != 0) { + ASE_ERR("FAILED\n"); + BEGIN_RED_FONTCOLOR; + perror("pthread_create"); + END_RED_FONTCOLOR; + exit(1); + } else { + ASE_MSG("SUCCESS\n"); + } + + while (umas_init_flag != 1) + ; + + // MMIO Scoreboard setup + int ii; + for (ii = 0; ii < MMIO_MAX_OUTSTANDING; ii = ii + 1) { + mmio_table[ii].tid = 0; + mmio_table[ii].data = 0; + mmio_table[ii].tx_flag = false; + mmio_table[ii].rx_flag = false; + } + + // Session status + session_exist_status = ESTABLISHED; + + } else { +#ifdef ASE_DEBUG + ASE_DBG("Session already exists\n"); +#endif + } + + FUNC_CALL_EXIT; +} + + +/* + * Session deninitialize + * Close down message queues to ASE simulator + */ +void session_deinit(void) +{ + FUNC_CALL_ENTRY; + + if (session_exist_status == ESTABLISHED) { + + ASE_INFO("Deinitializing simulation session \n"); + + // Mark session as destroyed + session_exist_status = NOT_ESTABLISHED; + + // Unmap UMAS region + if (umas_exist_status == ESTABLISHED) { + + ASE_MSG("Closing Watcher threads\n"); + + // Update status + umas_exist_status = NOT_ESTABLISHED; + + // Close UMsg thread + pthread_cancel(umsg_watch_tid); + + // Deallocate the region + ASE_MSG("Deallocating UMAS\n"); + deallocate_buffer(umas_region); + } +#ifdef ASE_DEBUG + else { + ASE_MSG("No UMAS established\n"); + } +#endif + + // Um-mapping CSR region + ASE_MSG("Deallocating MMIO map\n"); + if (mmio_exist_status == ESTABLISHED) { + + deallocate_buffer(mmio_region); + mmio_exist_status = NOT_ESTABLISHED; + + // Close MMIO Response tracker thread + pthread_cancel(mmio_watch_tid); + } + // Send SIMKILL + char session_ctrlcmd[ASE_MQ_MSGSIZE]; + memset(session_ctrlcmd, 0, ASE_MQ_MSGSIZE); + snprintf(session_ctrlcmd, ASE_MQ_MSGSIZE, "ASE_SIMKILL 0"); + ase_portctrl(session_ctrlcmd); + +#ifdef ASE_DEBUG + fclose(fp_pagetable_log); + fclose(fp_mmioaccess_log); +#endif + } else { + ASE_MSG("Session already deinitialized, call ignored !\n"); + } + + // close message queue + mqueue_close(app2sim_mmioreq_tx); + mqueue_close(sim2app_mmiorsp_rx); + mqueue_close(app2sim_alloc_tx); + mqueue_close(sim2app_alloc_rx); + mqueue_close(app2sim_umsg_tx); + mqueue_close(app2sim_portctrl_req_tx); + mqueue_close(app2sim_dealloc_tx); + mqueue_close(sim2app_dealloc_rx); + mqueue_close(sim2app_portctrl_rsp_rx); + + // Lock deinit + if (pthread_mutex_unlock(&mmio_port_lock) != 0) { + ASE_MSG("Trying to shutdown mutex unlock\n"); + } + // Stop running threads + pthread_cancel(umsg_watch_tid); + pthread_cancel(mmio_watch_tid); + + // End Clock snapshot + clock_gettime(CLOCK_MONOTONIC, &end_time_snapshot); + runtime_nsec = + 1e9 * (end_time_snapshot.tv_sec - + start_time_snapshot.tv_sec) + + (end_time_snapshot.tv_nsec - start_time_snapshot.tv_nsec); + + // Set locale, inherit locale, and reset back + char *oldLocale = setlocale(LC_NUMERIC, NULL); + setlocale(LC_NUMERIC, ""); + ASE_INFO("\tTook %'llu nsec \n", runtime_nsec); + setlocale(LC_NUMERIC, oldLocale); + + // Delete the .app_lock.pid file + if (access(app_ready_lockpath, F_OK) == 0) { + if (unlink(app_ready_lockpath) == 0) { + // Session end, set locale + ASE_INFO("Session ended \n"); + } + } + + FUNC_CALL_EXIT; +} + + +/* + * Get a scoreboard slot + */ +int find_empty_mmio_scoreboard_slot(void) +{ + int ii; + int idx; + for (ii = 0; ii < MMIO_MAX_OUTSTANDING; ii = ii + 1) { + idx = ii % MMIO_MAX_OUTSTANDING; + if ((mmio_table[idx].tx_flag == false) + && (mmio_table[idx].rx_flag == false)) + return idx; + } + return 0xFFFF; +} + + +/* + * Get MMIO Slot by TID + */ +int get_scoreboard_slot_by_tid(int in_tid) +{ + int ii; + for (ii = 0; ii < MMIO_MAX_OUTSTANDING; ii = ii + 1) { + if ((mmio_table[ii].tx_flag == true) + && (mmio_table[ii].tid == in_tid)) + return ii; + } + return 0xFFFF; +} + + +/* + * Count MMIO TIDs in use + */ +int count_mmio_tid_used(void) +{ + int ii; + int cnt = 0; + + for (ii = 0; ii < MMIO_MAX_OUTSTANDING; ii = ii + 1) + if (mmio_table[ii].tx_flag == true) + cnt++; + + return cnt; +} + + +/* + * MMIO Request call + * - Return index value + */ +int mmio_request_put(struct mmio_t *pkt) +{ + FUNC_CALL_ENTRY; + +#ifdef ASE_DEBUG + print_mmiopkt(fp_mmioaccess_log, "Sent", pkt); +#endif + + // Update scoreboard + int mmiotable_idx; + mmiotable_idx = find_empty_mmio_scoreboard_slot(); + if (mmiotable_idx != 0xFFFF) { + mmio_table[mmiotable_idx].tx_flag = true; + mmio_table[mmiotable_idx].rx_flag = false; + mmio_table[mmiotable_idx].tid = pkt->tid; + mmio_table[mmiotable_idx].data = pkt->qword[0]; + } + /* #ifdef ASE_DEBUG */ + else { + ASE_ERR + ("ASE Error generating MMIO TID, simulation cannot proceed !\n"); + raise(SIGABRT); + } + /* #endif */ + + // Send packet + mqueue_send(app2sim_mmioreq_tx, (char *) pkt, sizeof(mmio_t)); + + FUNC_CALL_EXIT; + +#ifdef ASE_DEBUG + if (pkt->write_en == MMIO_READ_REQ) { + ASE_DBG("mmiotable_idx = %d\n", mmiotable_idx); + } +#endif + + return mmiotable_idx; +} + + +/* + * MMIO Write 32-bit + */ +void mmio_write32(int offset, uint32_t data) +{ + FUNC_CALL_ENTRY; + +#ifdef ASE_DEBUG + int slot_idx; +#endif + + if (offset < 0) { + ASE_ERR("Requested offset is not in AFU MMIO region\n"); + ASE_ERR("MMIO Write Error\n"); + raise(SIGABRT); + } else { + mmio_t *mmio_pkt; + mmio_pkt = + (struct mmio_t *) ase_malloc(sizeof(struct mmio_t)); + + mmio_pkt->write_en = MMIO_WRITE_REQ; + mmio_pkt->width = MMIO_WIDTH_32; + mmio_pkt->addr = offset; + ase_memcpy(mmio_pkt->qword, &data, sizeof(uint32_t)); + mmio_pkt->resp_en = 0; + + // Critical Section + { + if (pthread_mutex_lock(&mmio_port_lock) != 0) { + ASE_ERR + ("pthread_mutex_lock could not attain lock !\n"); + exit(1); + } + + mmio_pkt->tid = generate_mmio_tid(); +#ifdef ASE_DEBUG + slot_idx = mmio_request_put(mmio_pkt); +#else + mmio_request_put(mmio_pkt); +#endif + + if (pthread_mutex_unlock(&mmio_port_lock) != 0) { + ASE_ERR + ("Mutex unlock failure ... Application Exit here\n"); + exit(1); + } + } + + // Write to MMIO map + uint32_t *mmio_vaddr; + mmio_vaddr = + (uint32_t *) ((uint64_t) mmio_afu_vbase + offset); + ase_memcpy(mmio_vaddr, (char *) &data, sizeof(uint32_t)); + + // Display + + ASE_MSG + ("MMIO Write : tid = 0x%03x, offset = 0x%x, data = 0x%08x\n", + mmio_pkt->tid, mmio_pkt->addr, data); + + free(mmio_pkt); + } + + FUNC_CALL_EXIT; +} + + +/* + * MMIO Write 64-bit + */ +void mmio_write64(int offset, uint64_t data) +{ + FUNC_CALL_ENTRY; + +#ifdef ASE_DEBUG + int slot_idx; +#endif + + if (offset < 0) { + ASE_ERR("Requested offset is not in AFU MMIO region\n"); + ASE_ERR("MMIO Write Error\n"); + raise(SIGABRT); + } else { + mmio_t *mmio_pkt; + mmio_pkt = + (struct mmio_t *) ase_malloc(sizeof(struct mmio_t)); + + mmio_pkt->write_en = MMIO_WRITE_REQ; + mmio_pkt->width = MMIO_WIDTH_64; + mmio_pkt->addr = offset; + ase_memcpy(mmio_pkt->qword, &data, sizeof(uint64_t)); + mmio_pkt->resp_en = 0; + + // Critical section + { + if (pthread_mutex_lock(&mmio_port_lock) != 0) { + ASE_ERR + ("pthread_mutex_lock could not attain lock !\n"); + exit(1); + } + + mmio_pkt->tid = generate_mmio_tid(); +#ifdef ASE_DEBUG + slot_idx = mmio_request_put(mmio_pkt); +#else + mmio_request_put(mmio_pkt); +#endif + + if (pthread_mutex_unlock(&mmio_port_lock) != 0) { + ASE_ERR + ("Mutex unlock failure ... Application Exit here\n"); + exit(1); + } + } + + // Write to MMIO Map + uint64_t *mmio_vaddr; + mmio_vaddr = + (uint64_t *) ((uint64_t) mmio_afu_vbase + offset); + *mmio_vaddr = data; + + + ASE_MSG + ("MMIO Write : tid = 0x%03x, offset = 0x%x, data = 0x%llx\n", + mmio_pkt->tid, mmio_pkt->addr, + (unsigned long long) data); + + + free(mmio_pkt); + } + + FUNC_CALL_EXIT; +} + + + +/* ********************************************************************* + * MMIO Read + * ********************************************************************* + * + * Request packet + * --------------------------------------- + * | MMIO_READ_REQ | MMIO_WIDTH | Offset | + * --------------------------------------- + * + * Response packet + * ------------------------------------- + * | MMIO_READ_RSP | MMIO_WIDTH | Data | + * ------------------------------------- + * + */ +/* + * MMIO Read 32-bit + */ +void mmio_read32(int offset, uint32_t *data32) +{ + FUNC_CALL_ENTRY; + int slot_idx; + + if (offset < 0) { + ASE_ERR("Requested offset is not in AFU MMIO region\n"); + ASE_ERR("MMIO Read Error\n"); + raise(SIGABRT); + } else { + mmio_t *mmio_pkt; + mmio_pkt = + (struct mmio_t *) ase_malloc(sizeof(struct mmio_t)); + + mmio_pkt->write_en = MMIO_READ_REQ; + mmio_pkt->width = MMIO_WIDTH_32; + mmio_pkt->addr = offset; + mmio_pkt->resp_en = 0; + + // Critical section + { + if (pthread_mutex_lock(&mmio_port_lock) != 0) { + ASE_ERR + ("pthread_mutex_lock could not attain lock !\n"); + exit(1); + } + + mmio_pkt->tid = generate_mmio_tid(); + slot_idx = mmio_request_put(mmio_pkt); + + if (pthread_mutex_unlock(&mmio_port_lock) != 0) { + ASE_ERR + ("Mutex unlock failure ... Application Exit here\n"); + exit(1); + } + } + + ASE_MSG("MMIO Read : tid = 0x%03x, offset = 0x%x\n", + mmio_pkt->tid, mmio_pkt->addr); + +#ifdef ASE_DEBUG + ASE_DBG("slot_idx = %d\n", slot_idx); +#endif + + // Wait until correct response found + while (mmio_table[slot_idx].rx_flag != true) { + usleep(1); + } + + // Write data + *data32 = (uint32_t) mmio_table[slot_idx].data; + + // Display + + ASE_MSG("MMIO Read Resp : tid = 0x%03x, %08x\n", + mmio_table[slot_idx].tid, (uint32_t) *data32); + + + // Reset scoreboard flags + mmio_table[slot_idx].tx_flag = false; + mmio_table[slot_idx].rx_flag = false; + + free(mmio_pkt); + } + + FUNC_CALL_EXIT; +} + + +/* + * MMIO Read 64-bit + */ +void mmio_read64(int offset, uint64_t *data64) +{ + FUNC_CALL_ENTRY; + int slot_idx; + +#ifdef ASE_DEBUG + void *retptr; +#endif + + if (offset < 0) { + ASE_ERR("Requested offset is not in AFU MMIO region\n"); + ASE_ERR("MMIO Read Error\n"); + raise(SIGABRT); + } else { + mmio_t *mmio_pkt; + mmio_pkt = + (struct mmio_t *) ase_malloc(sizeof(struct mmio_t)); + + mmio_pkt->write_en = MMIO_READ_REQ; + mmio_pkt->width = MMIO_WIDTH_64; + mmio_pkt->addr = offset; + mmio_pkt->resp_en = 0; + + // Critical section + { + if (pthread_mutex_lock(&mmio_port_lock) != 0) { + ASE_ERR + ("pthread_mutex_lock could not attain lock !\n"); + exit(1); + } + + mmio_pkt->tid = generate_mmio_tid(); + slot_idx = mmio_request_put(mmio_pkt); + + if (pthread_mutex_unlock(&mmio_port_lock) != 0) { + ASE_ERR + ("Mutex unlock failure ... Application Exit here\n"); + exit(1); + } + } + + ASE_MSG + ("MMIO Read : tid = 0x%03x, offset = 0x%x\n", + mmio_pkt->tid, mmio_pkt->addr); + +#ifdef ASE_DEBUG + ASE_DBG("slot_idx = %d\n", slot_idx); +#endif + + // Wait for correct response to be back + while (mmio_table[slot_idx].rx_flag != true) { + usleep(1); + }; + + // Write data + *data64 = mmio_table[slot_idx].data; + + // Display + ASE_MSG + ("MMIO Read Resp : tid = 0x%03x, data = %llx\n", + mmio_table[slot_idx].tid, + (unsigned long long) *data64); + + // Reset scoreboard flags + mmio_table[slot_idx].tx_flag = false; + mmio_table[slot_idx].rx_flag = false; + + free(mmio_pkt); + } + + FUNC_CALL_EXIT; +} + + +/* + * allocate_buffer: Shared memory allocation and vbase exchange + * Instantiate a buffer_t structure with given parameters + * Must be called by ASE_APP + */ +void allocate_buffer(struct buffer_t *mem, uint64_t *suggested_vaddr) +{ + FUNC_CALL_ENTRY; + + // pthread_mutex_trylock (&app_lock); + int fd_alloc; + char tmp_msg[ASE_MQ_MSGSIZE] = { 0, }; + + + ASE_MSG("Attempting to open a shared memory... \n"); + + + // Buffer is invalid until successfully allocated + mem->valid = ASE_BUFFER_INVALID; + + // If memory size is not set, then exit !! + if (mem->memsize <= 0) { + ASE_ERR + ("Memory requested must be larger than 0 bytes... exiting...\n"); + exit(1); + } + // Autogenerate a memname, by defualt the first region id=0 will be + // called "/mmio", subsequent regions will be called strcat("/buf", id) + // Initially set all characters to NULL + memset(mem->memname, 0, sizeof(mem->memname)); + if (mem->is_mmiomap == 1) { + snprintf(mem->memname, ASE_FILENAME_LEN, "/mmio.%s", + tstamp_string); + } else if (mem->is_umas == 1) { + snprintf(mem->memname, ASE_FILENAME_LEN, "/umas.%s", + tstamp_string); + } else { + snprintf(mem->memname, ASE_FILENAME_LEN, "/buf%d.%s", + userbuf_index_count, tstamp_string); + userbuf_index_count++; + } + + // Disable private memory flag + mem->is_privmem = 0; + + // Obtain a file descriptor for the shared memory region + // Tue May 5 19:24:21 PDT 2015 + // https://www.gnu.org/software/libc/manual/html_node/Permission-Bits.html + // S_IREAD | S_IWRITE are obselete + fd_alloc = + shm_open(mem->memname, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR); + if (fd_alloc < 0) { + BEGIN_RED_FONTCOLOR; + perror("shm_open"); + END_RED_FONTCOLOR; + exit(1); + } + // Mmap shared memory region + if (suggested_vaddr == (uint64_t *) NULL) { + mem->vbase = + (uint64_t) mmap(NULL, mem->memsize, + PROT_READ | PROT_WRITE, MAP_SHARED, + fd_alloc, 0); + } else { + mem->vbase = + (uint64_t) mmap(suggested_vaddr, mem->memsize, + PROT_READ | PROT_WRITE, + MAP_SHARED, fd_alloc, 0); + } + + // Check + if (mem->vbase == (uint64_t) MAP_FAILED) { + BEGIN_RED_FONTCOLOR; + perror("mmap"); + END_RED_FONTCOLOR; + ASE_ERR("error string %s", strerror(errno)); + exit(1); + } + // Extend memory to required size + int ret; + ret = ftruncate(fd_alloc, (off_t) mem->memsize); +#ifdef ASE_DEBUG + if (ret != 0) { + ASE_DBG("ftruncate failed"); + BEGIN_RED_FONTCOLOR; + perror("ftruncate"); + END_RED_FONTCOLOR; + + } +#endif + + // Autogenerate buffer index + mem->index = asebuf_index_count; + asebuf_index_count++; + ASE_MSG("SUCCESS\n"); + + // Set buffer as valid + mem->valid = ASE_BUFFER_VALID; + + // Send an allocate command to DPI, metadata = ASE_MEM_ALLOC + // mem->metadata = HDR_MEM_ALLOC_REQ; + mem->next = NULL; + + // Message queue must be enabled when using DPI (else debug purposes only) + if (mq_exist_status == NOT_ESTABLISHED) { + + ASE_MSG("Session not started --- STARTING now\n"); + + session_init(); + } + // Form message and transmit to DPI + ase_buffer_t_to_str(mem, tmp_msg); + mqueue_send(app2sim_alloc_tx, tmp_msg, ASE_MQ_MSGSIZE); + + // Receive message from DPI with pbase populated + while (mqueue_recv(sim2app_alloc_rx, tmp_msg, ASE_MQ_MSGSIZE) == 0) { /* wait */ + } + ase_str_to_buffer_t(tmp_msg, mem); + + // Print out the buffer +#ifdef ASE_DEBUG + ase_buffer_info(mem); +#endif + + // book-keeping WSmeta // used by ASEALIAFU + struct wsmeta_t *ws; + ws = (struct wsmeta_t *) ase_malloc(sizeof(struct wsmeta_t)); + ws->index = mem->index; + ws->buf_structaddr = (uint64_t *) mem; + append_wsmeta(ws); + +#ifdef ASE_DEBUG + if (fp_pagetable_log != NULL) { + if (mem->index % 20 == 0) { + fprintf(fp_pagetable_log, + "Index\tAppVBase\tASEVBase\tBufsize\tBufname\t\tPhysBase\n"); + } + fprintf(fp_pagetable_log, + "%d\t%p\t%p\t%x\t%s\t\t%p\n", + mem->index, + (void *) mem->vbase, + (void *) mem->pbase, + mem->memsize, + mem->memname, (void *) mem->fake_paddr); + } +#endif + + close(fd_alloc); + + FUNC_CALL_EXIT; +} + + +/* + * deallocate_buffer : Deallocate a memory region + * Destroy shared memory regions + * Called by ASE APP only + */ +void deallocate_buffer(struct buffer_t *mem) +{ + FUNC_CALL_ENTRY; + + int ret; + char tmp_msg[ASE_MQ_MSGSIZE] = { 0, }; + + ASE_MSG("Deallocating memory %s ... \n", mem->memname); + + // Send a one way message to request a deallocate + ase_buffer_t_to_str(mem, tmp_msg); + mqueue_send(app2sim_dealloc_tx, tmp_msg, ASE_MQ_MSGSIZE); + // Wait for response to deallocate + mqueue_recv(sim2app_dealloc_rx, tmp_msg, ASE_MQ_MSGSIZE); + ase_str_to_buffer_t(tmp_msg, mem); + + // Unmap the memory accordingly + ret = munmap((void *) mem->vbase, (size_t) mem->memsize); + if (0 != ret) { + BEGIN_RED_FONTCOLOR; + perror("munmap"); + END_RED_FONTCOLOR; + exit(1); + } + // Print if successful + ASE_MSG("SUCCESS\n"); + + FUNC_CALL_EXIT; +} + + +/* + * Appends and maintains a Workspace Meta Linked List (wsmeta_t) + * > linkedlist + */ +void append_wsmeta(struct wsmeta_t *new) +{ + FUNC_CALL_ENTRY; + + if (wsmeta_head == NULL) { + wsmeta_head = new; + wsmeta_end = new; + } + + wsmeta_end->next = new; + new->next = NULL; + wsmeta_end = new; + wsmeta_end->valid = 1; + +#ifdef ASE_DEBUG + + struct wsmeta_t *wsptr; + ASE_DBG("WSMeta traversal START =>\n"); + wsptr = wsmeta_head; + while (wsptr != NULL) { + ASE_DBG("\t%d %p %d\n", wsptr->index, + wsptr->buf_structaddr, wsptr->valid); + wsptr = wsptr->next; + } + ASE_DBG("WSMeta traversal END\n"); + +#endif + + FUNC_CALL_EXIT; +} + + +/* + * deallocate_buffer_by_index: + * Find a workspace by ID and then call deallocate_buffer + */ +bool deallocate_buffer_by_index(int search_index) +{ + FUNC_CALL_ENTRY; + bool value; + uint64_t *bufptr = (uint64_t *) NULL; + struct wsmeta_t *wsptr; + + ASE_MSG("Deallocate request index = %d ... \n", search_index); + + // Traverse wsmeta_t + wsptr = wsmeta_head; + while (wsptr != NULL) { + if (wsptr->index == search_index) { + bufptr = wsptr->buf_structaddr; + ASE_DBG("FOUND\n"); + break; + } else { + wsptr = wsptr->next; + } + } + + + // Call deallocate + if ((bufptr != NULL) && (wsptr->valid == 1)) { + deallocate_buffer((struct buffer_t *) bufptr); + wsptr->valid = 0; + value = true; + } else { + ASE_MSG("Buffer pointer was returned as NULL\n"); + value = false; + } + + FUNC_CALL_EXIT; + return value; +} + + +/* + * Traverse WSmeta array and find buffer by WSID + */ +struct buffer_t *find_buffer_by_index(uint64_t wsid) +{ + struct buffer_t *bufptr = (struct buffer_t *) NULL; + struct wsmeta_t *trav_ptr; + + trav_ptr = wsmeta_head; + while (trav_ptr != NULL) { + if (trav_ptr->index == wsid) { + bufptr = + (struct buffer_t *) trav_ptr->buf_structaddr; + break; + } else { + trav_ptr = trav_ptr->next; + } + } + + if (bufptr == (struct buffer_t *) NULL) { + ASE_ERR + ("find_buffer_by_index: Couldn't find buffer by WSID\n"); + } + + return bufptr; +} + + +/* + * UMSG Get Address + * umsg_get_address: Takes in umsg_id, and returns App virtual address + */ +uint64_t *umsg_get_address(int umsg_id) +{ + uint64_t *ret_vaddr; + if ((umsg_id >= 0) && (umsg_id < NUM_UMSG_PER_AFU)) { + ret_vaddr = + (uint64_t *) ((uint64_t) umsg_umas_vbase + + (uint64_t) ((uint64_t) umsg_id * + (ASE_PAGESIZE + 64))); + } else { + ret_vaddr = NULL; + ASE_ERR + ("**ERROR** Requested umsg_id out of range... EXITING\n"); + exit(1); + } + return ret_vaddr; +} + + +/* + * umsg_send: Write data to umsg region + */ +void umsg_send(int umsg_id, uint64_t *umsg_data) +{ + ase_memcpy((char *) umsg_addr_array[umsg_id], (char *) umsg_data, + sizeof(uint64_t)); +} + + +/* + * umsg_set_attribute: Set UMSG Hint setting + */ +void umsg_set_attribute(uint32_t hint_mask) +{ + char *umsg_attrib_cmd; + + // Cast message + umsg_attrib_cmd = ase_malloc(ASE_MQ_MSGSIZE); + snprintf(umsg_attrib_cmd, ASE_MQ_MSGSIZE, "UMSG_MODE %d", + hint_mask); + + // Send transaction + ase_portctrl(umsg_attrib_cmd); + + // Free memory + ase_free_buffer(umsg_attrib_cmd); +} + + +/* + * Umsg watcher thread + * Setup UMSG tracker addresses, and watch for activity + */ +void *umsg_watcher(void *arg) +{ + // Mark as thread that can be cancelled anytime + pthread_setcanceltype(PTHREAD_CANCEL_ENABLE, NULL); + + // Generic index + int cl_index; + + // UMsg old data + char umsg_old_data[NUM_UMSG_PER_AFU][CL_BYTE_WIDTH]; + + // Declare and Allocate umsgcmd_t packet + umsgcmd_t *umsg_pkt; + umsg_pkt = + (struct umsgcmd_t *) ase_malloc(sizeof(struct umsgcmd_t)); + + // Patrol each UMSG line + for (cl_index = 0; cl_index < NUM_UMSG_PER_AFU; cl_index++) { + // Original copy + ase_memcpy((char *) umsg_old_data[cl_index], + (char *) ((uint64_t) umas_region->vbase + + umsg_byteindex_arr[cl_index]), + CL_BYTE_WIDTH); + + // Calculate addres + umsg_addr_array[cl_index] = + (char *) ((uint64_t) umas_region->vbase + + umsg_byteindex_arr[cl_index]); +#ifdef ASE_DEBUG + + ASE_DBG("umsg_addr_array[%d] = %p\n", cl_index, + umsg_addr_array[cl_index]); + +#endif + } + + // Set UMsg initialized flag + umas_init_flag = 1; + + // While application is running + while (umas_exist_status == ESTABLISHED) { + // Walk through each line + for (cl_index = 0; cl_index < NUM_UMSG_PER_AFU; cl_index++) { + if (memcmp + (umsg_addr_array[cl_index], + umsg_old_data[cl_index], + CL_BYTE_WIDTH) != 0) { + // Construct UMsg packet + umsg_pkt->id = cl_index; + ase_memcpy((char *) umsg_pkt->qword, + (char *) + umsg_addr_array[cl_index], + CL_BYTE_WIDTH); + + // Send UMsg + mqueue_send(app2sim_umsg_tx, + (char *) umsg_pkt, + sizeof(struct umsgcmd_t)); + + // Update local mirror + ase_memcpy((char *) + umsg_old_data[cl_index], + (char *) umsg_pkt->qword, + CL_BYTE_WIDTH); + } + } + usleep(1); + } + + // Free memory + ase_free_buffer((char *) umsg_pkt); + + return 0; +} + + +/* + * ase_portctrl: Send port control message to simulator + * + * AFU_RESET | (0,1) + * UMSG_MODE [31:0] | (0xF0FF0FF0) + * ASE_INIT | (X) + * ASE_SIMKILL | (X) + * + */ +void __attribute__ ((optimize("O0"))) ase_portctrl(const char *ctrl_msg) +// void ase_portctrl(const char *ctrl_msg) +{ + // char dummy_rxstr[ASE_MQ_MSGSIZE]; + // memset(dummy_rxstr, 0, ASE_MQ_MSGSIZE); + char *dummy_rxstr; + dummy_rxstr = (char *) ase_malloc(ASE_MQ_MSGSIZE); + + // Send message + mqueue_send(app2sim_portctrl_req_tx, ctrl_msg, ASE_MQ_MSGSIZE); + + // Receive message + mqueue_recv(sim2app_portctrl_rsp_rx, dummy_rxstr, ASE_MQ_MSGSIZE); + + // Release memory + free(dummy_rxstr); +} diff --git a/ase/sw/ase_common.h b/ase/sw/ase_common.h new file mode 100644 index 000000000000..5ec62808f1da --- /dev/null +++ b/ase/sw/ase_common.h @@ -0,0 +1,854 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: ASE common (C header file) + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + + +#ifndef _ASE_COMMON_H_ +#define _ASE_COMMON_H_ + +#define _GNU_SOURCE + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef SIM_SIDE +#include +#endif + +#ifdef SIM_SIDE +#include "svdpi.h" +#endif + +#ifndef SIM_SIDE +#define APP_SIDE +#endif + +/* + * ASE Unique ID Check + */ +#define ASE_UNIQUE_ID "SR-6.4.0-7325e31" + + +/* + * Return integers + */ +#define OK 0 +#define NOT_OK -1 + +/* ******************************************************************************* + * + * SYSTEM FACTS + * + * *******************************************************************************/ +/* #define FPGA_ADDR_WIDTH 48 */ +/* #define PHYS_ADDR_PREFIX_MASK 0x0000FFFFFFE00000 */ +#define CL_ALIGN 6 +#define MEMBUF_2MB_ALIGN 21 + +// Width of a cache line in bytes +#define CL_BYTE_WIDTH 64 +#define SIZEOF_1GB_BYTES ((uint64_t)pow(1024, 3)) + +// Size of page +#define ASE_PAGESIZE 0x1000 // 4096 bytes +#define CCI_CHUNK_SIZE (2*1024*1024) // CCI 2 MB physical chunks + +//MMIO memory map size +#define MMIO_LENGTH (512*1024) // 512 KB MMIO size +#define MMIO_AFU_OFFSET (256*1024) + +// MMIO Tid width +#define MMIO_TID_BITWIDTH 9 +#define MMIO_TID_BITMASK (uint32_t)(pow((uint32_t)2, MMIO_TID_BITWIDTH)-1) +#define MMIO_MAX_OUTSTANDING 64 + +// Number of UMsgs per AFU +#define NUM_UMSG_PER_AFU 8 + +// UMAS region +#define UMAS_LENGTH (NUM_UMSG_PER_AFU * ASE_PAGESIZE) +#define UMAS_REGION_MEMSIZE (2*1024*1024) + +// User clock default +#define DEFAULT_USR_CLK_MHZ 312.500 +#define DEFAULT_USR_CLK_TPS (int)(1E+12/(DEFAULT_USR_CLK_MHZ*pow(1000, 2))); + + +/* + * ASE Debug log-level + * ------------------- + * Two log levels are supported in ASE, controlled by env(ASE_LOG) + * - ASE_LOG=0 | ASE_LOG_SILENT : Only INFO, ERR messages are posted + * - ASE_LOG!=0 | ASE_LOG_MESSAGE : All MSG, INFO, ERR messages are posted + */ +enum ase_loglevel { + ASE_LOG_ERROR = -3, + ASE_LOG_INFO_2 = -2, + ASE_LOG_INFO = -1, + ASE_LOG_SILENT = 0, + ASE_LOG_MESSAGE, + ASE_LOG_DEBUG +}; + +extern int glbl_loglevel; + +int ase_calc_loglevel(void); +void ase_print(int loglevel, char *fmt, ...); + +#ifdef SIM_SIDE + #define LOG_PREFIX " [SIM] " +#else + #define LOG_PREFIX " [APP] " +#endif + +// Shorten filename +#ifdef __SHORTEN_FILE__ +#undef __SHORTEN_FILE__ +#endif // __SHORT_FILE__ +#define __SHORTEN_FILE__ \ +({ const char *file = __FILE__; \ + const char *p = file; \ + while (*p) \ + ++p; \ + while ((p > file) && \ + ('/' != *p) && \ + ('\\' != *p)) \ + --p; \ + if (p > file) \ + ++p; \ + p; \ +}) + +#ifdef ASE_ERR +#undef ASE_ERR +#endif +#ifdef ASE_DEBUG +#define ASE_ERR(format, ...) \ + ase_print(ASE_LOG_ERROR, LOG_PREFIX "%s:%u:%s()\t" format, __SHORTEN_FILE__, __LINE__, __FUNCTION__, ## __VA_ARGS__) +#else +#define ASE_ERR(format, ...) \ + ase_print(ASE_LOG_ERROR, LOG_PREFIX format, ## __VA_ARGS__) +#endif + + +#ifdef ASE_INFO +#undef ASE_INFO +#endif +#ifdef ASE_DEBUG +#define ASE_INFO(format, ...) \ + ase_print(ASE_LOG_INFO, LOG_PREFIX "%s:%u:%s()\t" format, __SHORTEN_FILE__, __LINE__, __FUNCTION__, ## __VA_ARGS__) +#else +#define ASE_INFO(format, ...) \ + ase_print(ASE_LOG_INFO, LOG_PREFIX format, ## __VA_ARGS__) +#endif + + +#ifdef ASE_INFO_2 +#undef ASE_INFO_2 +#endif +#ifdef ASE_DEBUG +#define ASE_INFO_2(format, ...) \ + ase_print(ASE_LOG_INFO_2, LOG_PREFIX "%s:%u:%s()\t" format, __SHORTEN_FILE__, __LINE__, __FUNCTION__, ## __VA_ARGS__) +#else +#define ASE_INFO_2(format, ...) \ + ase_print(ASE_LOG_INFO_2, LOG_PREFIX format, ## __VA_ARGS__) +#endif + + +#ifdef ASE_MSG +#undef ASE_MSG +#endif +#ifdef ASE_DEBUG +#define ASE_MSG(format, ...) \ + ase_print(ASE_LOG_MESSAGE, LOG_PREFIX "%s:%u:%s()\t" format, __SHORTEN_FILE__, __LINE__, __FUNCTION__, ## __VA_ARGS__) +#else +#define ASE_MSG(format, ...) \ + ase_print(ASE_LOG_MESSAGE, LOG_PREFIX format, ## __VA_ARGS__) +#endif + + +#ifdef ASE_DBG +#undef ASE_DBG +#endif +#define ASE_DBG(format, ...) \ + ase_print(ASE_LOG_DEBUG, LOG_PREFIX "%s:%u:%s()\t" format, __SHORTEN_FILE__, __LINE__, __FUNCTION__, ## __VA_ARGS__) + + +/* + * ASE INTERNAL MACROS + * ------------------- + * Controls file, path lengths + * + */ +// SHM memory name length +#define ASE_FILENAME_LEN 40 + +// ASE filepath length +#define ASE_FILEPATH_LEN 256 + +// ASE logger len +#define ASE_LOGGER_LEN 1024 + +// Timestamp session code length +#define ASE_SESSION_CODE_LEN 20 + +// work Directory location +char *ase_workdir_path; + +// Timestamp IPC file +#define TSTAMP_FILENAME ".ase_timestamp" +char tstamp_filepath[ASE_FILEPATH_LEN]; +char *glbl_session_id; + +// CCIP Warnings and Error stat location +char *ccip_sniffer_file_statpath; + +// READY file name +#define ASE_READY_FILENAME ".ase_ready.pid" +#define APP_LOCK_FILENAME ".app_lock.pid" + +// IPC control list +char *ipclist_filepath; + +// CONFIG,SCRIPT parameter paths received from SV (initial) +char *sv2c_config_filepath; +char *sv2c_script_filepath; + +// ASE-APP run command +char *app_run_cmd; + +// ASE Mode macros +#define ASE_MODE_DAEMON_NO_SIMKILL 1 +#define ASE_MODE_DAEMON_SIMKILL 2 +#define ASE_MODE_DAEMON_SW_SIMKILL 3 +#define ASE_MODE_REGRESSION 4 + +// UMAS establishment status +#define NOT_ESTABLISHED 0xC0C0 +#define ESTABLISHED 0xBEEF + + +/* + * Console colors + */ +// ERROR codes are in RED color +#define BEGIN_RED_FONTCOLOR printf("\033[1;31m"); +#define END_RED_FONTCOLOR printf("\033[0m"); + +// INFO or INSTRUCTIONS are in GREEN color +#define BEGIN_GREEN_FONTCOLOR printf("\033[32;1m"); +#define END_GREEN_FONTCOLOR printf("\033[0m"); + +// WARNING codes in YELLOW color +#define BEGIN_YELLOW_FONTCOLOR printf("\033[0;33m"); +#define END_YELLOW_FONTCOLOR printf("\033[0m"); + +// Wipeout current line in printf +#define WIPEOUT_LINE printf("]\n\033[F\033[J"); + + +/* + * ASE Error codes + */ +#define ASE_USR_CAPCM_NOINIT 0x1 // CAPCM not initialized +#define ASE_OS_MQUEUE_ERR 0x2 // MQ open error +#define ASE_OS_SHM_ERR 0x3 // SHM open error +#define ASE_OS_FOPEN_ERR 0x4 // Normal fopen failure +#define ASE_OS_MEMMAP_ERR 0x5 // Memory map/unmap errors +#define ASE_OS_MQTXRX_ERR 0x6 // MQ send receive error +#define ASE_OS_MALLOC_ERR 0x7 // Malloc error +#define ASE_OS_STRING_ERR 0x8 // String operations error +#define ASE_IPCKILL_CATERR 0xA // Catastropic error when cleaning + // IPCs, manual intervention required +#define ASE_UNDEF_ERROR 0xFF // Undefined error, pls report + +// Simkill message +#define ASE_SIMKILL_MSG 0xDEADDEAD + +// Test complete separator +#define TEST_SEPARATOR "#####################################################" + +// Completed String +char *completed_str_msg; + + +/* ******************************************************************************* + * + * Shared buffer structure + * Fri Mar 11 09:02:18 PST 2016 : Converted to dual-ended linked list + * + * ******************************************************************************/ +// Buffer information structure -- +// Be careful of alignment within this structure! The layout must be +// identical on both 64 bit and 32 bit compilations. +struct buffer_t // Descriptiion Computed by +{ // -------------------------------------------- + int32_t index; // Tracking id | INTERNAL + int32_t valid; // Valid buffer indicator | INTERNAL + uint64_t vbase; // SW virtual address | APP + uint64_t pbase; // SIM virtual address | SIM + uint64_t fake_paddr; // unique low FPGA_ADDR_WIDTH addr | SIM + uint64_t fake_paddr_hi; // unique hi FPGA_ADDR_WIDTH addr | SIM + int32_t is_privmem; // Flag memory as a private memory | + int32_t is_mmiomap; // Flag memory as CSR map | + int32_t is_umas; // Flag memory as UMAS region | + uint32_t memsize; // Memory size | APP + char memname[ASE_FILENAME_LEN]; // Shared memory name | INTERNAL + struct buffer_t *next; +}; + + +/* + * Workspace meta list + */ +struct wsmeta_t { + int index; + int valid; + uint64_t *buf_structaddr; + struct wsmeta_t *next; +}; + + +/* + * MMIO transaction packet -- + * Be careful of alignment within this structure! The layout must be + * identical on both 64 bit and 32 bit compilations. + */ +typedef struct mmio_t { + int32_t tid; + int32_t write_en; + int32_t width; + int32_t addr; + uint64_t qword[8]; + int32_t resp_en; + int32_t dummy; // For 64 bit alignment +} mmio_t; + + +/* + * Umsg transaction packet + */ +typedef struct umsgcmd_t { + int32_t id; + int32_t hint; + uint64_t qword[8]; +} umsgcmd_t; + + +// Incoming UMSG packet (allocated in ase_init, deallocated in start_simkill_countdown) +struct umsgcmd_t *incoming_umsg_pkt; + +// Incoming MMIO packet (allocated in ase_init, deallocated in start_simkill_countdown) +struct mmio_t *incoming_mmio_pkt; + +// Compute buffer_t size +#define BUFSIZE sizeof(struct buffer_t) + + +// Head and tail pointers of DPI side Linked list +extern struct buffer_t *head; // Head pointer +extern struct buffer_t *end; // Tail pointer + +// DPI side CSR base, offsets updated on CSR writes +uint64_t *mmio_afu_vbase; +// UMAS Base Address +uint64_t *umsg_umas_vbase; + + +// ASE buffer valid/invalid indicator +// When a buffer is 'allocated' successfully, it will be valid, when +// it is deallocated, it will become invalid. +#define ASE_BUFFER_VALID 0xFFFF +#define ASE_BUFFER_INVALID 0x0 + +// Buffer allocate/deallocate message headers +#define HDR_MEM_ALLOC_REQ 0x7F7F +#define HDR_MEM_ALLOC_REPLY 0x77FF +#define HDR_MEM_DEALLOC_REQ 0x00FF +#define HDR_MEM_DEALLOC_REPLY 0x7700 + +// MMIO widths +#define MMIO_WRITE_REQ 0xAA88 +#define MMIO_READ_REQ 0xBB88 + +#define MMIO_WIDTH_32 32 +#define MMIO_WIDTH_64 64 + +// UMSG info structure +typedef struct { + int id; + int hint; + char data[CL_BYTE_WIDTH]; +} umsg_pack_t; + +// Size map +#define SIZEOF_UMSG_PACK_T sizeof(umsg_pack_t) + + +/* ******************************************************************** + * + * FUNCTION PROTOTYPES + * + * ********************************************************************/ +// Linked list functions +void ll_print_info(struct buffer_t *); +void ll_traverse_print(void); +void ll_append_buffer(struct buffer_t *); +void ll_remove_buffer(struct buffer_t *); +uint32_t check_if_physaddr_used(uint64_t); +struct buffer_t *ll_search_buffer(int); + +// Mem-ops functions +int ase_recv_msg(struct buffer_t *); +void ase_alloc_action(struct buffer_t *); +void ase_dealloc_action(struct buffer_t *, int); +void ase_destroy(void); +uint64_t *ase_fakeaddr_to_vaddr(uint64_t); +void ase_dbg_memtest(struct buffer_t *); +void ase_perror_teardown(void); +void ase_empty_buffer(struct buffer_t *); +uint64_t get_range_checked_physaddr(uint32_t); +void ase_memory_barrier(void); +#ifdef ASE_DEBUG +void print_mmiopkt(FILE *, char *, struct mmio_t *); +#endif +void ase_free_buffer(char *); + +uint32_t generate_ase_seed(void); +void ase_write_seed(uint32_t); +uint32_t ase_read_seed(void); + + +// ASE operations +#ifdef ASE_DEBUG +void ase_buffer_info(struct buffer_t *); +#endif +void ase_buffer_oneline(struct buffer_t *); +void ase_buffer_t_to_str(struct buffer_t *, char *); +void ase_str_to_buffer_t(char *, struct buffer_t *); +int ase_dump_to_file(struct buffer_t *, char *); +uint64_t ase_rand64(void); +void ase_eval_session_directory(void); +int ase_instance_running(void); +void remove_spaces(char *); +void remove_tabs(char *); +void remove_newline(char *); +uint32_t ret_random_in_range(int, int); +void ase_string_copy(char *, const char *, size_t); +char *ase_getenv(const char *); +void ase_memcpy(void *, const void *, size_t); +int ase_strncmp(const char *, const char *, size_t); + +// Message queue operations +void ipc_init(void); +void mqueue_create(char *); +int mqueue_open(char *, int); +void mqueue_close(int); +void mqueue_destroy(char *); +void mqueue_send(int, const char *, int); +int mqueue_recv(int, char *, int); + +// Timestamp functions +void put_timestamp(void); +// char* get_timestamp(int); +void get_timestamp(char *); +char *generate_tstamp_path(char *); + +// Error report functions +void ase_error_report(char *, int, int); +void backtrace_handler(int); + +// IPC management functions +void final_ipc_cleanup(void); +void add_to_ipc_list(char *, char *); +void create_ipc_listfile(void); + +// BBS DFH specifics +void initialize_fme_dfh(struct buffer_t *); +void update_fme_dfh(struct buffer_t *); + + +/* + * These functions are called by C++ Applications + */ +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +// Session control +void session_init(void); +void session_deinit(void); +void poll_for_session_id(void); +int ase_read_lock_file(const char *); +void send_simkill(int); +void send_swreset(void); +// Shared memory alloc/dealloc operations +void allocate_buffer(struct buffer_t *, uint64_t *); +void deallocate_buffer(struct buffer_t *); +bool deallocate_buffer_by_index(int); +void append_wsmeta(struct wsmeta_t *); +// MMIO activity +int find_empty_mmio_scoreboard_slot(void); +int get_scoreboard_slot_by_tid(int); +int count_mmio_tid_used(void); +uint32_t generate_mmio_tid(void); +int mmio_request_put(struct mmio_t *); +void mmio_response_get(struct mmio_t *); +void mmio_write32(int, uint32_t); +void mmio_write64(int, uint64_t); +void mmio_read32(int, uint32_t *); +void mmio_read64(int, uint64_t *); +// GET IOVA +struct buffer_t *find_buffer_by_index(uint64_t); + +// UMSG functions +uint64_t *umsg_get_address(int); +void umsg_send(int, uint64_t *); +void umsg_set_attribute(uint32_t); +// Driver activity +void ase_portctrl(const char *); +// Threaded watch processes +void *mmio_response_watcher(void *); +// ASE-special malloc +char *ase_malloc(size_t); +void *umsg_watcher(void *); + +#ifdef __cplusplus +} +#endif // __cplusplus +#define DUMPSTRVAR(varname) fprintf(DUMPSTRVAR_str, "%s", #varname); +/* ******************************************************************** + * + * MESSAGING IPC + * + * ********************************************************************/// Message queue parameters +#define ASE_MQ_MAXMSG 8 +#define ASE_MQ_MSGSIZE 1024 +#define ASE_MQ_NAME_LEN 64 +#define ASE_MQ_INSTANCES 10 +// Message presence setting +#define ASE_MSG_PRESENT 0xD33D +#define ASE_MSG_ABSENT 0xDEAD +// Message queue controls +struct ipc_t { + char name[ASE_MQ_NAME_LEN]; + char path[ASE_FILEPATH_LEN]; + int perm_flag; +}; +struct ipc_t mq_array[ASE_MQ_INSTANCES]; +//struct ipc_t *mq_array; + + +/* ******************************************************************** + * + * DEBUG STRUCTURES + * + * ********************************************************************/ +// Enable function call entry/exit +// Extremely noisy debug feature to watch function entry/exit +// #define ENABLE_ENTRY_EXIT_WATCH +#ifdef ENABLE_ENTRY_EXIT_WATCH +#define FUNC_CALL_ENTRY printf("--- ENTER: %s ---\n", __FUNCTION__); +#define FUNC_CALL_EXIT printf("--- EXIT : %s ---\n", __FUNCTION__); +#else +#define FUNC_CALL_ENTRY +#define FUNC_CALL_EXIT +#endif + +// --------------------------------------------------------------------- +// Enable memory test function +// --------------------------------------------------------------------- +// Basic Memory Read/Write test feature (runs on allocate_buffer) +// Leaving this setting ON automatically scrubs memory (sets 0s) +// Read shm_dbg_memtest() and ase_dbg_memtest() +// #define ASE_MEMTEST_ENABLE + + +// ------------------------------------------------------------------ +// Triggers, safety catches and debug information used in the AFU +// simulator environment. +// ------------------------------------------------------------------ +// ASE message view #define - Print messages as they go around +// #define ASE_MSG_VIEW + +// Enable debug info from linked lists +// #define ASE_LL_VIEW + +// Print buffers as they are being alloc/dealloc +// #define ASE_BUFFER_VIEW + +// Backtrace data +int bt_j, bt_nptrs; +void *bt_buffer[4096]; +char **bt_strings; + + +/* ********************************************************************* + * + * SIMULATION-ONLY (SIM_SIDE) declarations + * - This is available only in simulation side + * - This compiled in when SIM_SIDE is set to 1 + * + * *********************************************************************/ +#ifdef SIM_SIDE + +/* + * ASE config structure + * This will reflect ase.cfg + */ +struct ase_cfg_t { + int ase_mode; + int ase_timeout; + int ase_num_tests; + int enable_reuse_seed; + int ase_seed; + int enable_cl_view; + int usr_tps; + int phys_memory_available_gb; +}; +struct ase_cfg_t *cfg; + +// ASE config file +// #define ASE_CONFIG_FILE "ase.cfg" + +// ASE seed file +#define ASE_SEED_FILE "ase_seed.txt" + +/* + * Data-exchange functions and structures + */ +// CCI transaction packet +typedef struct { + int mode; + int qw_start; + long mdata; + long long cl_addr; + long long qword[8]; + int resp_channel; + int intr_id; + int success; +} cci_pkt; + +#define CCIPKT_WRITE_MODE 0x1010 +#define CCIPKT_READ_MODE 0x2020 +#define CCIPKT_WRFENCE_MODE 0xFFFF +#define CCIPKT_ATOMIC_MODE 0x8080 +#define CCIPKT_INTR_MODE 0x4040 + + +/* + * Function prototypes + */ +// DPI-C export(C to SV) calls +extern void simkill(void); +extern void sw_simkill_request(void); +extern void buffer_messages(char *); +extern void ase_config_dex(struct ase_cfg_t *); + +// DPI-C import(SV to C) calls +int ase_init(void); +int ase_ready(void); +void ase_write_lock_file(void); +int ase_listener(void); +void ase_config_parse(char *); + +// Simulation control function +void register_signal(int, void *); +void start_simkill_countdown(void); +void run_clocks(int num_clocks); +void afu_softreset_trig(int init, int value); +void ase_reset_trig(void); +void sw_reset_response(void); + +// Read system memory line +void rd_memline_dex(cci_pkt *pkt); + +// Write system memory line +void wr_memline_dex(cci_pkt *pkt); + +// Seed Dex +uint32_t get_ase_seed(void); + +// MMIO request +void mmio_dispatch(int init, struct mmio_t *mmio_pkt); + +// MMIO Read response +void mmio_response(struct mmio_t *mmio_pkt); + +// UMSG functions +void umsg_dispatch(int init, struct umsgcmd_t *umsg_pkt); + +// Interrupt generator function +void ase_interrupt_generator(int id); + +// Buffer message injection +void buffer_msg_inject(int, char *); + +// Count error flag dex +extern int count_error_flag_ping(void); +void count_error_flag_pong(int); +void update_glbl_dealloc(int); + +// Redeclaring ase_malloc, following maintainer-check issues !!! Do Not Edit !!! +char *ase_malloc(size_t); + + +/* + * ASE Ready session control files, for wrapping with autorun script + */ +// File pointer +FILE *fp_ase_ready; +// Ready filepath +char *ase_ready_filepath; + +// ASE seed +uint64_t ase_seed; + +// ASE error file +FILE *error_fp; // = (FILE *)NULL; + + +/* + * IPC cleanup on catastrophic errors + */ +#define IPC_LOCAL_FILENAME ".ase_ipc_local" +FILE *local_ipc_fp; // = (FILE *)NULL; + +/* + * Physical Memory ranges for PrivMem & SysMem + */ +// System Memory +uint64_t sysmem_size; +uint64_t sysmem_phys_lo; +uint64_t sysmem_phys_hi; + +// ASE PID +int ase_pid; + +// ASE hostname +char *ase_hostname; + +// Workspace information log (information dump of +FILE *fp_workspace_log; // = (FILE *)NULL; + +// Memory access debug log +#ifdef ASE_DEBUG +FILE *fp_memaccess_log; // = (FILE *)NULL; +FILE *fp_pagetable_log; // = (FILE *)NULL; +#endif + +// Physical address mask - used to constrain generated addresses +uint64_t PHYS_ADDR_PREFIX_MASK; + +// '1' indicates that teardown is in progress +int self_destruct_in_progress; + +#endif + + +/* + * IPC MQ fd names + */ +#ifdef SIM_SIDE +int app2sim_alloc_rx; // app2sim mesaage queue in RX mode +int sim2app_alloc_tx; // sim2app mesaage queue in TX mode +int app2sim_mmioreq_rx; // MMIO Request path +int sim2app_mmiorsp_tx; // MMIO Response path +int app2sim_umsg_rx; // UMSG message queue in RX mode +int app2sim_portctrl_req_rx; // Port Control messages in Rx mode +int app2sim_dealloc_rx; +int sim2app_dealloc_tx; +int sim2app_portctrl_rsp_tx; +int sim2app_intr_request_tx; +#else +int app2sim_alloc_tx; // app2sim mesaage queue in RX mode +int sim2app_alloc_rx; // sim2app mesaage queue in TX mode +int app2sim_mmioreq_tx; // MMIO Request path +int sim2app_mmiorsp_rx; // MMIO Response path +int app2sim_umsg_tx; // UMSG message queue in RX mode +int app2sim_portctrl_req_tx; // Port Control message in TX mode +int app2sim_dealloc_tx; +int sim2app_dealloc_rx; +int sim2app_portctrl_rsp_rx; +int sim2app_intr_request_rx; +#endif // End SIM_SIDE + +// There is no global fixes for this +#define DEFEATURE_ATOMICS + + +/* + * Platform specific switches are enabled here + */ +// ------------------------------------------ // +#ifdef FPGA_PLATFORM_INTG_XEON +#define ASE_ENABLE_UMSG_FEATURE +#undef ASE_ENABLE_INTR_FEATURE +// ------------------------------------------ // +#elif FPGA_PLATFORM_DISCRETE +#undef ASE_ENABLE_UMSG_FEATURE +#define ASE_ENABLE_INTR_FEATURE +#endif +// ------------------------------------------ // + + +#endif // End _ASE_COMMON_H_ diff --git a/ase/sw/ase_ops.c b/ase/sw/ase_ops.c new file mode 100644 index 000000000000..cc5a4d2bfda1 --- /dev/null +++ b/ase/sw/ase_ops.c @@ -0,0 +1,816 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: ASE operations functions + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + +#include "ase_common.h" + +struct buffer_t *head; +struct buffer_t *end; + + +/* + * Parse strings and remove unnecessary characters + */ +// Remove spaces +void remove_spaces(char *in_str) +{ + if (in_str == NULL) { + ASE_ERR("remove_spaces : Input string is NULL\n"); + } else { + char *i; + char *j; + i = in_str; + j = in_str; + while (*j != 0) { + *i = *j++; + if (*i != ' ') + i++; + } + *i = 0; + } +} + + +// Remove tabs +void remove_tabs(char *in_str) +{ + if (in_str == NULL) { + ASE_ERR("remove_tabs : Input string is NULL\n"); + } else { + char *i = in_str; + char *j = in_str; + while (*j != 0) { + *i = *j++; + if (*i != '\t') + i++; + } + *i = 0; + } +} + +// Remove newline +void remove_newline(char *in_str) +{ + if (in_str == NULL) { + ASE_ERR("remove_newline : Input string is NULL\n"); + } else { + char *i = in_str; + char *j = in_str; + while (*j != 0) { + *i = *j++; + if (*i != '\n') + i++; + } + *i = 0; + } +} + + +// ------------------------------------------------------------- +// ase_buffer_info : Print out information about the buffer +// ------------------------------------------------------------- +#ifdef ASE_DEBUG +void ase_buffer_info(struct buffer_t *mem) +{ + FUNC_CALL_ENTRY; + + ASE_MSG("\tindex = %d \n", mem->index); + ASE_MSG("\tvalid = %s \n", + (mem->valid == 0xffff) ? "VALID" : "INVALID"); + ASE_MSG("\tAPPVirtBase = 0x%" PRIx64 "\n", mem->vbase); + ASE_MSG("\tSIMVirtBase = 0x%" PRIx64 "\n", mem->pbase); + ASE_MSG("\tBufferSize = 0x%" PRIx32 " \n", mem->memsize); + ASE_MSG("\tBufferName = \"%s\"\n", mem->memname); + ASE_MSG("\tPhysAddr LO = 0x%" PRIx64 "\n", mem->fake_paddr); + ASE_MSG("\tPhysAddr HI = 0x%" PRIx64 "\n", mem->fake_paddr_hi); + ASE_MSG("\tisMMIOMap = %s\n", + (mem->is_mmiomap == 1) ? "YES" : "NO"); + ASE_MSG("\tisUMAS = %s\n", + (mem->is_umas == 1) ? "YES" : "NO"); + + FUNC_CALL_EXIT; +} +#endif + + +/* + * ase_buffer_oneline : Print one line info about buffer + */ +void ase_buffer_oneline(struct buffer_t *mem) +{ + if (mem->valid == ASE_BUFFER_VALID) { + ASE_MSG("%d\tADDED \t%5s\n", mem->index, mem->memname); + } else { + ASE_MSG("%d\tREMOVED \t%5s\n", mem->index, mem->memname); + } +} + + +// ------------------------------------------------------------------- +// buffer_t_to_str : buffer_t to string conversion +// Converts buffer_t to string +// ------------------------------------------------------------------- +void ase_buffer_t_to_str(struct buffer_t *buf, char *str) +{ + FUNC_CALL_ENTRY; + + ase_memcpy(str, (char *) buf, sizeof(struct buffer_t)); + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------- +// ase_str_to_buffer_t : string to buffer_t conversion +// All fields are space separated, use strtok to decode +// -------------------------------------------------------------- +void ase_str_to_buffer_t(char *str, struct buffer_t *buf) +{ + FUNC_CALL_ENTRY; + + ase_memcpy((char *) buf, str, sizeof(struct buffer_t)); + + FUNC_CALL_EXIT; +} + + +/* + * ASE memory barrier + */ +void ase_memory_barrier(void) +{ + // asm volatile("" ::: "memory"); + __asm__ __volatile__("":::"memory"); +} + + +/* + * Evaluate Session directory + * If SIM_SIDE is set, Return "$ASE_WORKDIR/work/" + * else, Return "$PWD/work/" + * Both must be the same location + * + * PROCEDURE: + * - Check if PWD/ASE_WORKDIR exists: + * - Most cases, it will exist, created by Makefile + * - Check if "work" directory already exists, if not create one + * - If not Error out + */ +void ase_eval_session_directory(void) +{ + FUNC_CALL_ENTRY; + + // ase_workdir_path = ase_malloc (ASE_FILEPATH_LEN); + + // Evaluate location of simulator or own location +#ifdef SIM_SIDE + ase_workdir_path = getenv("PWD"); +#else + ase_workdir_path = getenv("ASE_WORKDIR"); + +#ifdef ASE_DEBUG + ASE_DBG("env(ASE_WORKDIR) = %s\n", ase_workdir_path); +#endif + + if (ase_workdir_path == NULL) { + ASE_ERR + ("**ERROR** Environment variable ASE_WORKDIR could not be evaluated !!\n"); + ASE_ERR("**ERROR** ASE will exit now !!\n"); + perror("getenv"); + exit(1); + } else { + // Check if directory exists here + DIR *ase_dir; + ase_dir = opendir(ase_workdir_path); + if (!ase_dir) { + ASE_ERR + ("ASE workdir path pointed by env(ASE_WORKDIR) does not exist !\n"); + ASE_ERR("Cannot continue execution... exiting !"); + perror("opendir"); + exit(1); + } else { + closedir(ase_dir); + } + } +#endif +} + + +/* + * ASE malloc + * Malloc wrapped with ASE closedown if failure accures + */ +char *ase_malloc(size_t size) +{ + FUNC_CALL_ENTRY; + + char *buffer; + + buffer = malloc(size); + // posix_memalign((void**)&buffer, (size_t)getpagesize(), size); + if (buffer == NULL) { + ase_error_report("malloc", errno, ASE_OS_MALLOC_ERR); + + ASE_ERR("Malloc failed\n"); + ase_free_buffer(buffer); + FUNC_CALL_EXIT; +#ifdef SIM_SIDE + start_simkill_countdown(); + exit(1); // Klocwork fix +#else + exit(1); +#endif + } else { + memset(buffer, 0, size); + FUNC_CALL_EXIT; + return buffer; + } +} + + +/* + * ase_write_lock_file : Write ASE Lock file + * To be used only by simulator, NOT application + * + * Writes a lock file about session specific items like this + * ------------------------------ + * | pid = + * | host = + * | dir = <$PWD> + * | uid = + * ------------------------------ + * + */ +#ifdef SIM_SIDE +void ase_write_lock_file(void) +{ + FUNC_CALL_ENTRY; + + int ret_err; + + // Create a filepath string + ase_ready_filepath = ase_malloc(ASE_FILEPATH_LEN); + snprintf(ase_ready_filepath, ASE_FILEPATH_LEN, "%s/%s", + ase_workdir_path, ASE_READY_FILENAME); + + // Line 2 + ase_hostname = ase_malloc(ASE_FILENAME_LEN); + + // Open file + fp_ase_ready = fopen(ase_ready_filepath, "w"); + if (fp_ase_ready == (FILE *) NULL) { + ASE_ERR + ("**ERROR** => ASE lock file could not be written, Exiting\n"); + start_simkill_countdown(); + } else { + // ///////// Write specifics //////////////// + // Line 1 + fprintf(fp_ase_ready, "pid = %d\n", ase_pid); + + // Get hostname for comparison + ret_err = gethostname(ase_hostname, ASE_FILENAME_LEN); + if (ret_err != 0) { + ASE_ERR + ("**ERROR** => Hostname could not be calculated, Exiting\n"); + + // Close file + fclose(fp_ase_ready); + + // Remove buffers + free(ase_hostname); + + // Issue Simkill + start_simkill_countdown(); + } else { + fprintf(fp_ase_ready, "host = %s\n", ase_hostname); + + // Line 3 + fprintf(fp_ase_ready, "dir = %s\n", + ase_workdir_path); + + // Line 4 + fprintf(fp_ase_ready, "uid = %s\n", + ASE_UNIQUE_ID); + + //////////////////////////////////////////// + // Close file + fclose(fp_ase_ready); + free(ase_hostname); + + // Notice on stdout + ASE_MSG + ("ASE lock file .ase_ready.pid written in work directory\n"); + } + } + + + FUNC_CALL_EXIT; +} +#endif + + +/* + * ase_read_lock_file() : Read an existing lock file and decipher contents + */ +int ase_read_lock_file(const char *workdir) +{ + // Allocate string + FILE *fp_exp_ready; + char *exp_ready_filepath; + char *line; + size_t len; + + char *parameter; + char *value; + + char *readback_workdir_path; + char *readback_hostname; + char *curr_hostname; + char *readback_uid; + char *curr_uid; + int readback_pid = 0; + int ret_err; + + // Null check and exit + if (workdir == NULL) { + ASE_ERR + ("ase_read_lock_file : Input ASE workdir path is NULL \n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // Calculate ready file path + exp_ready_filepath = ase_malloc(ASE_FILEPATH_LEN); + snprintf(exp_ready_filepath, ASE_FILEPATH_LEN, "%s/%s", + workdir, ASE_READY_FILENAME); + + // Check if file exists + if (access(exp_ready_filepath, F_OK) != -1) { // File exists + // Malloc/memset + line = ase_malloc(256); + readback_hostname = ase_malloc(ASE_FILENAME_LEN); + readback_uid = ase_malloc(ASE_FILEPATH_LEN); + readback_workdir_path = + ase_malloc(ASE_FILEPATH_LEN); + curr_hostname = ase_malloc(ASE_FILENAME_LEN); + + // Open file + fp_exp_ready = fopen(exp_ready_filepath, "r"); + if (fp_exp_ready == NULL) { + ASE_ERR + ("Ready file couldn't be opened for reading, Exiting !\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + + // Read file line by line + while (getline(&line, &len, fp_exp_ready) + != -1) { + // LHS/RHS tokenizing + parameter = strtok(line, "="); + value = strtok(NULL, ""); + // Check for parameter being recorded as NULL + if ((parameter == NULL) + || (value == NULL)) { + ASE_ERR + ("** Error tokenizing paramter in lock file, EXIT !\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // Trim contents + remove_spaces(parameter); + remove_tabs(parameter); + remove_newline(parameter); + remove_spaces(value); + remove_tabs(value); + remove_newline(value); + // Line 1/2/3/4 check + if (ase_strncmp + (parameter, "pid", + 3) == 0) { + readback_pid = + atoi(value); + } else + if (ase_strncmp + (parameter, "host", + 4) == 0) { + ase_string_copy + (readback_hostname, + value, + ASE_FILENAME_LEN); + } else + if (ase_strncmp + (parameter, "dir", + 3) == 0) { + ase_string_copy + (readback_workdir_path, + value, + ASE_FILEPATH_LEN); + } else + if (ase_strncmp + (parameter, "uid", + 3) == 0) { + ase_string_copy + (readback_uid, + value, + ASE_FILEPATH_LEN); + } else { + ASE_ERR + ("** ERROR **: Session parameter could not be deciphered !\n"); + } + } + } + fclose(fp_exp_ready); + } + + ////////////////// Error checks ////////////////// + // If hostname does not match + ret_err = + gethostname(curr_hostname, ASE_FILENAME_LEN); + if (ret_err != 0) { + ASE_ERR + ("**ERROR** => Hostname could not be calculated, Exiting\n"); + exit(1); + } else { + // Check here + if (ase_strncmp + (curr_hostname, readback_hostname, + ASE_FILENAME_LEN) != 0) { + ASE_ERR + ("** ERROR ** => Hostname specified in ASE lock file (%s) is different as current hostname (%s)\n", + readback_hostname, + curr_hostname); + ASE_ERR + ("** ERROR ** => Ensure that Simulator process and OPAE SW application are running on the same host !\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // If readback_uid (Readback unique ID from lock file) doesnt match ase_common.h + curr_uid = + ase_malloc(ASE_FILENAME_LEN); + ase_string_copy(curr_uid, + ASE_UNIQUE_ID, + ASE_FILENAME_LEN); + + // Check + if (ase_strncmp + (curr_uid, readback_uid, + ASE_FILENAME_LEN) != 0) { + ASE_ERR + ("** ERROR ** => Application UID does not match known release UID\n"); + ASE_ERR + ("** ERROR ** => Simulator built with UID=%s, Application built with UID=%s\n", + readback_uid, + curr_uid); + ASE_ERR + ("** ERROR ** => Ensure that Simulator process and OPAE SW application are compiled from the same System Release version !\n"); + ASE_ERR + ("** ERROR ** => Also, check if env(LD_LIBRARY_PATH) is set to appropriate or library paths \n"); + ASE_ERR + ("** ERROR ** => Simulation cannot proceed ... EXITING\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + // Free curr_uid + free(curr_uid); + } + } + + // Free all buffers + ase_free_buffer(line); + ase_free_buffer(readback_hostname); + ase_free_buffer(curr_hostname); + ase_free_buffer(readback_workdir_path); + ase_free_buffer(readback_uid); + } else { // File does not exist + ASE_ERR + ("ASE Ready file was not found at env(ASE_WORKDIR) !\n"); + ASE_ERR + ("This could be for one of two reasons =>\n"); + ASE_ERR(" - Simualtor is not running yet \n"); + ASE_ERR + (" - env(ASE_WORKDIR) is set to the wrong location \n"); + // Shutdown process +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + + // Free expected filepath buffer + free(exp_ready_filepath); + } + + // Return PID of Simulator instance + return readback_pid; +} + + +/* + * Pretty print function - print_mmiopkt + */ +#ifdef ASE_DEBUG +void print_mmiopkt(FILE *fp, char *activity, struct mmio_t *pkt) +{ + FUNC_CALL_ENTRY; + + char mmio_action_type[20]; + memset(mmio_action_type, 0, 20); + + snprintf(mmio_action_type, 20, + "MMIO-%s-%d-%s", + (pkt->write_en == MMIO_WRITE_REQ ? "Write" : "Read"), + pkt->width, (pkt->resp_en == 0 ? "Req " : "Resp")); + + fprintf(fp, "%s\t%03x\t%s\t%x\t%" PRIx64 "\n", activity, + pkt->tid, mmio_action_type, pkt->addr, pkt->qword[0]); + + FUNC_CALL_EXIT; +} +#endif + + +/* + * ase_free_buffer : Free memory if not NULL + */ +void ase_free_buffer(char *ptr) +{ + if (ptr != (char *) NULL) { + free(ptr); + } +} + + +/* + * register_signal : Register Signal Handler + */ +void register_signal(int sig, void *handler) +{ + FUNC_CALL_ENTRY; + + struct sigaction cfg; + + // Configure signal handler + cfg.sa_handler = handler; + sigemptyset(&cfg.sa_mask); + cfg.sa_flags = SA_RESTART; + + // Declare signal action + sigaction(sig, &cfg, 0); + + FUNC_CALL_EXIT; +} + + +/* + * ret_random_in_range : Return random number in a range + */ +uint32_t ret_random_in_range(int low, int high) +{ + return (rand() % (high + 1 - low) + low); +} + + +/* + * ase_string_copy + * ASE's own safe string copy insures a null-termination + * NOTE: dest must be malloc'ed before use (use ase_malloc) + */ +void ase_string_copy(char *dest, const char *src, size_t num_bytes) +{ + FUNC_CALL_ENTRY; + + int dest_strlen; + + // Allocate memory if not already done + if (dest == NULL) { + ASE_ERR + ("** ERROR ** => String copy destination not allocated.. Exiting\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // Use snprintf as a copy mechanism + snprintf(dest, num_bytes, "%s", src); + + // Find length + dest_strlen = strlen(dest); + + // Terminate length, or kill + if (dest_strlen < num_bytes) { + dest[dest_strlen] = '\0'; + } else { + ASE_ERR + ("** Internal Error ** => Invalid null termination during string copy [%d]\n", + dest_strlen); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + } + + FUNC_CALL_EXIT; +} + + +/* + * ase_getenv : Secure getenv abstraction + */ +char *ase_getenv(const char *name) +{ + char *env; + + if (name == NULL) { + ASE_ERR + ("** ERROR **: Input Environment variable is NULL... EXITING"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // GLIBC check before getenv call (check if GLIBC >= 2.17) +#if __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 17) + env = secure_getenv(name); +#else + env = getenv(name); +#endif + + if (env == NULL) { + ASE_ERR + ("** ERROR **: Environment variable env(%s) could not be evaluated... EXITING", + name); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + return env; + } + } + + return NULL; +} + + +/* + * ase_memcpy - Secure memcpy abstraction + */ +void ase_memcpy(void *dest, const void *src, size_t n) +{ + // Insecure implementation + // memcpy(dest, src, n); + + // Secure implementation + memcpy_s(dest, n, src, n); +} + + +/* + * Print messages + */ +int ase_calc_loglevel(void) +{ + int ret_loglevel; + + // Evaluate env(ASE_LOG) + char *str_env; + str_env = getenv("ASE_LOG"); + if (str_env) { + ret_loglevel = atoi(str_env); + } else { + ret_loglevel = ASE_LOG_MESSAGE; + } + + // Clean up if illegal (can be 0 or higher only + if (ret_loglevel < ASE_LOG_SILENT) { + ret_loglevel = ASE_LOG_MESSAGE; + } + // If ASE_DEBUG is set, return ASE_LOG_DEBUG +#ifdef ASE_DEBUG + ASE_MSG("Started in DEBUG mode\n"); + ret_loglevel = ASE_LOG_DEBUG; +#endif + + return ret_loglevel; +} + + +/* + * Print level function + */ +void ase_print(int loglevel, char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + + // glbl_loglevel is sanitized to Either 0, 1, or 2 + + if (loglevel == ASE_LOG_ERROR) { + BEGIN_RED_FONTCOLOR; + vprintf(fmt, args); + END_RED_FONTCOLOR; + } else if (loglevel == ASE_LOG_INFO) { +#ifdef SIM_SIDE + BEGIN_GREEN_FONTCOLOR; + vprintf(fmt, args); + END_GREEN_FONTCOLOR; +#else + BEGIN_YELLOW_FONTCOLOR; + vprintf(fmt, args); + END_YELLOW_FONTCOLOR; +#endif + } +#ifdef SIM_SIDE + else if (loglevel == ASE_LOG_INFO_2) { + BEGIN_YELLOW_FONTCOLOR; + vprintf(fmt, args); + END_YELLOW_FONTCOLOR; + } +#endif + else if (loglevel == ASE_LOG_DEBUG) { +#ifdef ASE_DEBUG + BEGIN_YELLOW_FONTCOLOR; + vprintf(fmt, args); + END_YELLOW_FONTCOLOR; +#endif + } else { + if (glbl_loglevel != ASE_LOG_SILENT) { + BEGIN_YELLOW_FONTCOLOR; + vprintf(fmt, args); + END_YELLOW_FONTCOLOR; + } + } + + va_end(args); +} + + +/* + * ASE String Compare + */ +int ase_strncmp(const char *s1, const char *s2, size_t n) +{ + errno_t ret; + int indicator; + + // Run secure compare + ret = strcmp_s(s2, n, s1, &indicator); + if (ret != EOK) { + ASE_DBG("Problem with ase_strncmp - code %d\n", ret); + return -1; + } else { + return indicator; + } +} diff --git a/ase/sw/error_report.c b/ase/sw/error_report.c new file mode 100644 index 000000000000..4a9c643768fd --- /dev/null +++ b/ase/sw/error_report.c @@ -0,0 +1,178 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: ASE Error reporting functions + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + */ + +#include "ase_common.h" + +// ----------------------------------------------------------------------- +// ASE error report : Prints a verbose report on catastrophic errors +// ----------------------------------------------------------------------- +void ase_error_report(char *err_func, int err_num, int err_code) +{ + // Report error + ASE_ERR("@ERROR in %s CODE %d | %s\n", err_func, err_num, + strerror(err_num)); + + // Corrective actions + switch (err_code) { + // CAPCM not initialized + case ASE_USR_CAPCM_NOINIT: + ASE_ERR + ("QPI-CA private memory has not been initialized.\n"); + break; + + // Message queue error + case ASE_OS_MQUEUE_ERR: + ASE_ERR + ("There was an error in the POSIX Message Queue subsystem.\n"); + ASE_ERR + ("Please look up 'man mq_overview' for more information.\n"); + break; + + // Message queue error + case ASE_OS_SHM_ERR: + ASE_ERR + ("There was an error in the POSIX Shared Memory subsystem.\n"); + break; + + // File open error + case ASE_OS_FOPEN_ERR: + ASE_ERR + ("File opening failed. This could be due to several reasons: \n"); + ASE_ERR + ("1. ASE is being run from the wrong relative paths, and causing fstat to fail.\n"); + ASE_ERR("2. File system permissions are not optimal\n"); + break; + + // Memory map/unmap failed + case ASE_OS_MEMMAP_ERR: + ASE_ERR + ("A problem occured when mapping or unmapping a memory region to a virtual base pointer.\n"); + break; + + // MQ send/receive error + case ASE_OS_MQTXRX_ERR: + ASE_ERR + ("There was a problem when sending/receiving messages using the POSIX message queues.\n"); + ASE_ERR + ("This may be due to sub-optimal message queue attributes.\n"); + break; + + // Malloc error + case ASE_OS_MALLOC_ERR: + ASE_ERR + ("There was a problem with memory allocation system, NULL was returned.\n"); + ASE_ERR("Simulator will attempt to close down.\n"); + break; + + // IPCkill catastrophic error + case ASE_IPCKILL_CATERR: + ASE_ERR + ("There was an ERROR when trying to open IPC local listfile for cleaning.\n"); + ASE_ERR + ("fopen failed, see .ase_ipc_local file, and clean them manually.\n"); + break; + + // Default or unknown error + default: + ASE_ERR + ("ERROR code is not defined, or cause is unknown.\n"); + ASE_ERR + ("If your agreement allows this, please report detailed steps to recreate the error to the developer.\n"); + } + + END_RED_FONTCOLOR; +} + + +/* + * Wrapper for backtrace handler + * Useful for debugging broken symbols + */ +extern const char *__progname; + +void backtrace_handler(int sig) +{ + void *bt_addr[16]; + char **bt_messages = (char **) NULL; + int ii, trace_depth = 0; + char sys_cmd[256]; + char app_or_sim[16]; + int cmd_ret; + + memset(app_or_sim, 0, sizeof(app_or_sim)); + +#ifdef SIM_SIDE + snprintf(app_or_sim, 16, "Simulator "); +#else + snprintf(app_or_sim, 16, "Application "); +#endif + + // Identify SIG received + ASE_ERR("%s received a ", app_or_sim); + switch (sig) { + case SIGSEGV: + ASE_ERR("SIGSEGV\n"); + break; + + case SIGBUS: + ASE_ERR("SIGBUS\n"); + break; + + case SIGABRT: + ASE_ERR("SIGABRT\n"); + break; + + default: + ASE_ERR("Unidentified signal %d\n", sig); + break; + } + + trace_depth = backtrace(bt_addr, 16); + bt_messages = backtrace_symbols(bt_addr, trace_depth); + ASE_ERR("\n[bt] Execution Backtrace:\n"); + for (ii = 1; ii < trace_depth; ii++) { + ASE_ERR("[bt] #%d %s\n", ii, bt_messages[ii]); + snprintf(sys_cmd, 256, "addr2line %p -e %s", bt_addr[ii], + __progname); + cmd_ret = system(sys_cmd); + // man page for system asks users to check for SIGINT/SIGQUIT + if (WIFSIGNALED(cmd_ret) + && ((WTERMSIG(cmd_ret) == SIGINT) + || (WTERMSIG(cmd_ret) == SIGQUIT))) { + break; + } + } + + exit(1); +} diff --git a/ase/sw/ipc_mgmt_ops.c b/ase/sw/ipc_mgmt_ops.c new file mode 100644 index 000000000000..0a5a55768d79 --- /dev/null +++ b/ase/sw/ipc_mgmt_ops.c @@ -0,0 +1,157 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: IPC management functions + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + */ + + +#include "ase_common.h" + +// ----------------------------------------------------------------------- +// create_ipc_listfile : Creates a log of IPC structures opened by +// this ASE session. This will be looked up so a +// civilized cleaning can be done +// ----------------------------------------------------------------------- +void create_ipc_listfile(void) +{ + FUNC_CALL_ENTRY; + + // Allocate memory, fail if not possible + ipclist_filepath = ase_malloc(ASE_FILEPATH_LEN); + + // Create IPC file path length + snprintf(ipclist_filepath, ASE_FILEPATH_LEN, "%s/%s", + ase_workdir_path, IPC_LOCAL_FILENAME); + + // Open IPC log in write mode + local_ipc_fp = fopen(ipclist_filepath, "w"); + if (local_ipc_fp == NULL) { + // Error out gracefully on problem + ase_error_report("fopen", errno, ASE_OS_FOPEN_ERR); + ASE_ERR("Local IPC file cannot be opened\n"); + start_simkill_countdown(); // RRS: exit(1); + } +#ifdef ASE_DEBUG + else { + ASE_DBG("IPC Watchdog file %s opened\n", + IPC_LOCAL_FILENAME); + } +#endif + + FUNC_CALL_EXIT; +} + + +// ----------------------------------------------------------------------- +// add_to_ipc_list : Add record to IPC list +// ----------------------------------------------------------------------- +void add_to_ipc_list(char *ipc_type, char *ipc_name) +{ + FUNC_CALL_ENTRY; + int ret; + + // Add name to local IPC list + ret = fprintf(local_ipc_fp, "%s\t%s\n", ipc_type, ipc_name); + + if (ret < 0) { + ASE_ERR + ("add_to_ipc_list: Failed to update IPC management file, cleanup may be incomplete\n"); + ASE_ERR(" Simulation will continue\n"); + } + + FUNC_CALL_EXIT; +} + +// ----------------------------------------------------------------------- +// final_ipc_cleanup : A second level check to see all the blocks are +// removed +// ----------------------------------------------------------------------- +void final_ipc_cleanup(void) +{ + FUNC_CALL_ENTRY; + + char *ipc_type; + char *ipc_name; + + char *ipc_line; + size_t ipc_line_len = 0; + + ipc_line = ase_malloc(ASE_FILEPATH_LEN + 16); + + // Close global/local files + fclose(local_ipc_fp); + + // Reopen local IPC listfile + local_ipc_fp = fopen(ipclist_filepath, "r"); + if (local_ipc_fp == NULL) { + ase_error_report("fopen", errno, ASE_IPCKILL_CATERR); + start_simkill_countdown(); // RRS: exit(1); + } else { + // Parse through list + ASE_MSG + ("Removing message queues and buffer handles ... \n"); + while (getline(&ipc_line, &ipc_line_len, local_ipc_fp) != + -1) { + ipc_type = strtok(ipc_line, " \t"); + ipc_name = strtok(NULL, " \t"); + if ((ipc_type == NULL) || (ipc_name == NULL)) { + ASE_DBG("Ignoring ipc_line_len\n"); + } else { + // Compare type of ipc_type + if (ase_strncmp(ipc_type, "MQ", 2) == 0) { + ASE_DBG(" Removing MQ %s ", + ipc_name); + if (unlink(ipc_name) == -1) { + ASE_DBG("\n"); + } else { + ASE_DBG("DONE\n"); + } + } else if (ase_strncmp(ipc_type, "SHM", 3) + == 0) { + ASE_DBG(" Removing SHM %s ", + ipc_name); + if (shm_unlink(ipc_name) == -1) { + ASE_DBG("\n"); + } else { + ASE_DBG("DONE\n"); + } + } + } + } + + // Close both files + fclose(local_ipc_fp); + } + + ase_free_buffer(ipc_line); + + FUNC_CALL_EXIT; +} diff --git a/ase/sw/linked_list_ops.c b/ase/sw/linked_list_ops.c new file mode 100644 index 000000000000..fb2d72b86ba4 --- /dev/null +++ b/ase/sw/linked_list_ops.c @@ -0,0 +1,197 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: Linked List memory buffer controls + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + +#include "ase_common.h" + +/* + * ll_print_info: Print linked list node info + * Thu Oct 2 15:50:06 PDT 2014 : Modified for cleanliness + * Prints buffer info + */ +void ll_print_info(struct buffer_t *print_ptr) +{ + FUNC_CALL_ENTRY; + + ASE_MSG("%d ", print_ptr->index); + ASE_MSG("%5s \t", print_ptr->memname); + ASE_MSG("%5s ", + (print_ptr->valid == + ASE_BUFFER_VALID) ? "VALID" : "INVLD"); + ASE_MSG("0x%" PRIx64 " ", print_ptr->vbase); + ASE_MSG("0x%" PRIx64 " ", print_ptr->pbase); + ASE_MSG("0x%" PRIx64 " ", print_ptr->fake_paddr); + ASE_MSG("0x%" PRIx32 " ", print_ptr->memsize); + ASE_MSG("\n"); + + FUNC_CALL_EXIT; +} + + +// --------------------------------------------------------------- +// ll_traverse_print: Traverse and print linked list data +// --------------------------------------------------------------- +void ll_traverse_print(void) +{ + FUNC_CALL_ENTRY; + struct buffer_t *traverse_ptr; + + ASE_MSG("Starting linked list traversal from 'head'..\n"); + traverse_ptr = head; + while (traverse_ptr != NULL) { + ll_print_info(traverse_ptr); + traverse_ptr = traverse_ptr->next; + } + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------------- +// ll_append_buffer : Append a buffer to linked list +// A buffer must be allocated before this function is called +// -------------------------------------------------------------------- +void ll_append_buffer(struct buffer_t *new) +{ + FUNC_CALL_ENTRY; + + // If there are no nodes in the list, set the new buffer as head + if (head == NULL) { + head = new; + end = new; + } + // Link the new new node to the end of the list + end->next = new; + // Set the next field as NULL + new->next = NULL; + // Adjust end to point to last node + end = new; + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------------- +// ll_remove_buffer : Remove a buffer (relink remaining) +// Use ll_search_buffer() to pin-point the deletion target first. +// -------------------------------------------------------------------- +void ll_remove_buffer(struct buffer_t *ptr) +{ + FUNC_CALL_ENTRY; + + struct buffer_t *temp, *prev; + // node to be deleted + temp = ptr; + + // Reset linked list traversal + prev = head; + + // If first node is to be deleted + if (temp == head) { + // Move head to next node + head = head->next; + // If there is only one node in the linked list + if (end == temp) + end = end->next; + } else { // If not the first node + // Traverse until node is found + while (prev->next != temp) { + prev = prev->next; + } + // Link previous node to next node + prev->next = temp->next; + // If this is the end node, reset the end pointer + if (end == temp) + end = prev; + } + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------------- +// search_buffer_ll : Search buffer by ID +// Pass the head of the linked list along when calling +// -------------------------------------------------------------------- +struct buffer_t *ll_search_buffer(int search_index) +{ + FUNC_CALL_ENTRY; + + struct buffer_t *search_ptr; + + // Start searching from the head + search_ptr = head; + + // Traverse linked list starting from head + if (search_ptr != NULL) { + while (search_ptr->index != search_index) { + search_ptr = search_ptr->next; + if (search_ptr == NULL) + break; + } + } + // When found, return pointer to buffer + if (search_ptr != NULL) { + if (search_index == (int) search_ptr->index) + return search_ptr; + else + return (struct buffer_t *) NULL; + } else + return (struct buffer_t *) NULL; + + FUNC_CALL_EXIT; +} + + +/* + * Check if physical address is used + * RETURN 0 if not found, 1 if found + */ +uint32_t check_if_physaddr_used(uint64_t paddr) +{ + struct buffer_t *search_ptr; + int flag = 0; + + search_ptr = head; + while (search_ptr != NULL) { + if ((paddr >= search_ptr->fake_paddr) + && (paddr < search_ptr->fake_paddr_hi)) { + flag = 1; + break; + } else { + search_ptr = search_ptr->next; + } + } + return flag; +} diff --git a/ase/sw/mem_model.c b/ase/sw/mem_model.c new file mode 100644 index 000000000000..4c4dc6901752 --- /dev/null +++ b/ase/sw/mem_model.c @@ -0,0 +1,420 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: Memory Model operations (C module) + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + * Purpose: Keeping cci_to_mem_translator.c clutter free and modular + * test and debug. Includes message queue management by DPI. + * NOTE: These functions must be called by DPI side ONLY. + */ + +#include "ase_common.h" + + +// --------------------------------------------------------------- +// ASE graceful shutdown - Called if: error() occurs +// Deallocate & Unlink all shared memories and message queues +// --------------------------------------------------------------- +void ase_perror_teardown(void) +{ + FUNC_CALL_ENTRY; + + self_destruct_in_progress = 1; + + ase_destroy(); + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------------- +// DPI ALLOC buffer action - Allocate buffer action inside DPI +// Receive buffer_t pointer with memsize, memname and index populated +// Calculate fd, pbase and fake_paddr +// -------------------------------------------------------------------- +void ase_alloc_action(struct buffer_t *mem) +{ + FUNC_CALL_ENTRY; + + struct buffer_t *new_buf; + int fd_alloc; + + ASE_DBG("SIM-C : Adding a new buffer \"%s\"...\n", mem->memname); + + // Obtain a file descriptor + fd_alloc = shm_open(mem->memname, O_RDWR, S_IRUSR | S_IWUSR); + if (fd_alloc < 0) { + ase_error_report("shm_open", errno, ASE_OS_SHM_ERR); + ase_perror_teardown(); + start_simkill_countdown(); + } else { + // Add to IPC list + add_to_ipc_list("SHM", mem->memname); + + // Mmap to pbase, find one with unique low 38 bit + mem->pbase = + (uintptr_t) mmap(NULL, mem->memsize, + PROT_READ | PROT_WRITE, MAP_SHARED, + fd_alloc, 0); + if (mem->pbase == 0) { + ase_error_report("mmap", errno, ASE_OS_MEMMAP_ERR); + ase_perror_teardown(); + start_simkill_countdown(); + } + if (ftruncate(fd_alloc, (off_t) mem->memsize) != 0) { + ase_error_report("ftruncate", errno, + ASE_OS_SHM_ERR); + ASE_MSG("Running ftruncate to %d bytes\n", + (off_t) mem->memsize); + } + close(fd_alloc); + + // Record fake address + mem->fake_paddr = get_range_checked_physaddr(mem->memsize); + mem->fake_paddr_hi = + mem->fake_paddr + (uint64_t) mem->memsize; + + // Received buffer is valid + mem->valid = ASE_BUFFER_VALID; + + // Create a buffer and store the information + new_buf = (struct buffer_t *) ase_malloc(BUFSIZE); + ase_memcpy(new_buf, mem, BUFSIZE); + + // Append to linked list + ll_append_buffer(new_buf); +#ifdef ASE_LL_VIEW + ll_traverse_print(); +#endif + + // Convert buffer_t to string + mqueue_send(sim2app_alloc_tx, (char *) mem, + sizeof(struct buffer_t)); + + // If memtest is enabled +#ifdef ASE_MEMTEST_ENABLE + ase_dbg_memtest(mem); +#endif + + if (mem->is_mmiomap == 1) { + // Pin CSR address + mmio_afu_vbase = + (uint64_t *) (uintptr_t) (mem->pbase + + MMIO_AFU_OFFSET); + ASE_DBG("Global CSR Base address = %p\n", + (void *) mmio_afu_vbase); + } +#ifdef ASE_DEBUG + if (fp_pagetable_log != NULL) { + if (mem->index % 20 == 0) { + fprintf(fp_pagetable_log, + "Index\tAppVBase\tASEVBase\tBufsize\tBufname\t\tPhysBase\n"); + } + + fprintf(fp_pagetable_log, + "%d\t0x%" PRIx64 "\t0x%" PRIx64 + "\t%x\t%s\t\t0x%" PRIx64 "\n", mem->index, + mem->vbase, mem->pbase, mem->memsize, + mem->memname, mem->fake_paddr); + } +#endif + } + + FUNC_CALL_EXIT; +} + + +// -------------------------------------------------------------------- +// DPI dealloc buffer action - Deallocate buffer action inside DPI +// Receive index and invalidates buffer +// -------------------------------------------------------------------- +void ase_dealloc_action(struct buffer_t *buf, int mq_enable) +{ + FUNC_CALL_ENTRY; + + char buf_str[ASE_MQ_MSGSIZE]; + memset(buf_str, 0, ASE_MQ_MSGSIZE); + + // Traversal pointer + struct buffer_t *dealloc_ptr; + // dealloc_ptr = (struct buffer_t *) ase_malloc(sizeof(struct buffer_t)); + + // Search buffer and Invalidate + dealloc_ptr = ll_search_buffer(buf->index); + + // If deallocate returns a NULL, dont get hosed + if (dealloc_ptr == NULL) { + ASE_INFO_2 + ("NULL deallocation request received ... ignoring.\n"); + } else { + ASE_INFO_2("Request to deallocate \"%s\" ...\n", + dealloc_ptr->memname); + // Mark buffer as invalid & deallocate + dealloc_ptr->valid = ASE_BUFFER_INVALID; + munmap((void *) (uintptr_t) dealloc_ptr->pbase, + (size_t) dealloc_ptr->memsize); + shm_unlink(dealloc_ptr->memname); + // Respond back + ll_remove_buffer(dealloc_ptr); + ase_memcpy(buf_str, dealloc_ptr, sizeof(struct buffer_t)); + // If Buffer removal is requested by APP, send back notice, else no response + if (mq_enable == 1) { + mqueue_send(sim2app_dealloc_tx, buf_str, + ASE_MQ_MSGSIZE); + } +#ifdef ASE_LL_VIEW + ll_traverse_print(); +#endif + } + + // Free dealloc_ptr + // free(dealloc_ptr); + + FUNC_CALL_EXIT; +} + +// -------------------------------------------------------------------- +// ase_empty_buffer: create an empty buffer_t object +// Create a buffer with all parameters set to 0 +// -------------------------------------------------------------------- +void ase_empty_buffer(struct buffer_t *buf) +{ + buf->index = 0; + buf->valid = ASE_BUFFER_INVALID; + memset(buf->memname, 0, ASE_FILENAME_LEN); + buf->memsize = 0; + buf->vbase = 0; + buf->pbase = 0; + buf->fake_paddr = 0; + buf->next = NULL; +} + + +// -------------------------------------------------------------------- +// ase_destroy : Destroy everything, called before exiting OR to +// reset simulation environment +// +// OPERATION: +// Traverse trough linked list +// - Remove each shared memory region +// - Remove each buffer_t +// -------------------------------------------------------------------- +void ase_destroy(void) +{ + FUNC_CALL_ENTRY; + +#ifdef ASE_DEBUG + char str[256]; + snprintf(str, 256, "ASE destroy called"); + buffer_msg_inject(1, str); +#endif + + struct buffer_t *ptr; + + ptr = head; + if (head != NULL) { + while (ptr != (struct buffer_t *) NULL) { + ase_dealloc_action(ptr, 0); + ptr = ptr->next; + } + } + + FUNC_CALL_EXIT; +} + + +/* + * Range check a Physical address to check if used + * Created to integrate Sysmem & CAPCM and prevent corner case overwrite + * issues (Mon Oct 13 13:33:59 PDT 2014) + * Operation: When allocating a fake physical address, this function + * will return an unused physical address range + * This will be used by SW allocate buffer funtion ONLY + */ +uint64_t get_range_checked_physaddr(uint32_t size) +{ + int unique_physaddr_needed = 1; + uint64_t ret_fake_paddr; + uint32_t search_flag; + uint32_t opposite_flag; + uint32_t zero_pbase_flag; +#ifdef ASE_DEBUG + int tries = 0; +#endif + + // Generate a new address + while (unique_physaddr_needed) { + // Generate a random physical address for system memory + ret_fake_paddr = + sysmem_phys_lo + ase_rand64() % sysmem_size; + // 2MB align and sanitize + // ret_fake_paddr = ret_fake_paddr & 0x00003FFFE00000 ; + ret_fake_paddr = ret_fake_paddr & PHYS_ADDR_PREFIX_MASK; + + // Check for conditions + // Is address in sysmem range, go back + search_flag = check_if_physaddr_used(ret_fake_paddr); + + // Is HI smaller than LO, go back + opposite_flag = 0; + if ((ret_fake_paddr + (uint64_t) size) < ret_fake_paddr) + opposite_flag = 1; + + // Zero base flag + zero_pbase_flag = 0; + if (ret_fake_paddr == 0) + zero_pbase_flag = 1; + + // If all OK + unique_physaddr_needed = + search_flag | opposite_flag | zero_pbase_flag; +#ifdef ASE_DEBUG + tries++; +#endif + } + +#ifdef ASE_DEBUG + if (fp_memaccess_log != NULL) { + fprintf(fp_memaccess_log, + " [DEBUG] ASE took %d tries to generate phyaddr\n", + tries); + } +#endif + + return ret_fake_paddr; +} + + +/* + * ASE Physical address to virtual address converter + * Takes in a simulated physical address from AFU, converts it + * to virtual address + */ +uint64_t *ase_fakeaddr_to_vaddr(uint64_t req_paddr) +{ + FUNC_CALL_ENTRY; + + // Traversal ptr + struct buffer_t *trav_ptr = (struct buffer_t *) NULL; + // int buffer_found = 0; + + if (req_paddr != 0) { + // Clean up address of signed-ness (limit to CCI-P 42 bits) + req_paddr = req_paddr & (((uint64_t) 1 << 42) - 1); + + // DPI pbase address + uint64_t *ase_pbase; + + // This is the real offset to perform read/write + uint64_t real_offset, calc_pbase; + + // For debug only +#ifdef ASE_DEBUG + if (fp_memaccess_log != NULL) { + fprintf(fp_memaccess_log, + "req_paddr = 0x%" PRIx64 " | ", req_paddr); + } +#endif + + // Search which buffer offset_from_pin lies in + trav_ptr = head; + while (trav_ptr != NULL) { + if ((req_paddr >= trav_ptr->fake_paddr) + && (req_paddr < trav_ptr->fake_paddr_hi)) { + real_offset = + (uint64_t) req_paddr - + (uint64_t) trav_ptr->fake_paddr; + calc_pbase = trav_ptr->pbase; + ase_pbase = + (uint64_t *) (uintptr_t) (calc_pbase + + real_offset); + + // Debug only +#ifdef ASE_DEBUG + if (fp_memaccess_log != NULL) { + fprintf(fp_memaccess_log, + "offset=0x%016" PRIx64 + " | pbase=%p\n", + real_offset, ase_pbase); + } +#endif + return ase_pbase; + } else { + trav_ptr = trav_ptr->next; + } + } + } else { + // buffer_found = 0; + trav_ptr = NULL; + } + + // If accesses are correct, ASE should not reach this point + if (trav_ptr == NULL) { + ASE_ERR + ("@ERROR: ASE has detected a memory operation to an unallocated memory region.\n"); + ASE_ERR + (" Simulation cannot continue, please check the code.\n"); + ASE_ERR(" Failure @ phys_addr = 0x%" PRIx64 "\n", + req_paddr); + ASE_ERR + (" See ERROR log file => ase_memory_error.log\n"); + ASE_ERR + ("@ERROR: Check that previously requested memories have not been deallocated before an AFU transaction could access them\n"); + ASE_ERR + (" NOTE: If your application polls for an AFU completion message, and you deallocate after that, consider using a WriteFence before AFU status message\n"); + ASE_ERR + (" The simulator may be committing AFU transactions out of order\n"); + + // Write error to file + error_fp = (FILE *) NULL; + error_fp = fopen("ase_memory_error.log", "w"); + if (error_fp != NULL) { + fprintf(error_fp, + "*** ASE stopped on an illegal memory access ERROR ***\n" + " AFU requested access @ physical memory 0x%" + PRIx64 "\n" + " Address not found in requested workspaces\n" + " Timestamped transaction to this address is listed in ccip_transactions.tsv\n" + " Check that previously requested memories have not been deallocated before an AFU transaction could access them" + " NOTE: If your application polls for an AFU completion message, and you deallocate after that, consider using a WriteFence before AFU status message\n" + " The simulator may be committing AFU transactions out of order\n", + req_paddr); + + fclose(error_fp); + } + // Request SIMKILL + start_simkill_countdown(); + } + + return (uint64_t *) NOT_OK; + + FUNC_CALL_EXIT; +} diff --git a/ase/sw/mqueue_ops.c b/ase/sw/mqueue_ops.c new file mode 100644 index 000000000000..e89d6a9e6dd3 --- /dev/null +++ b/ase/sw/mqueue_ops.c @@ -0,0 +1,344 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: Message queue functions + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + */ + +#include "ase_common.h" + +/* + * Named pipe string array + */ +const char *mq_name_arr[] = { + "app2sim_alloc_ping_smq\0", + "app2sim_mmioreq_smq\0", + "app2sim_umsg_smq\0", + "sim2app_alloc_pong_smq\0", + "sim2app_mmiorsp_smq\0", + "app2sim_portctrl_req_smq\0", + "app2sim_dealloc_ping_smq\0", + "sim2app_dealloc_pong_smq\0", + "sim2app_portctrl_rsp_smq\0", + "sim2app_intr_request_smq\0" +}; + + +/* + * get_smq_perm_flag : Calculate perm_flag based on string name + * Automates the assignment of MQ flags + * + */ +int get_smq_perm_flag(const char *mq_name_str) +{ + char *mq_str; + int ret = -1; + + // Length controlled string copy + mq_str = ase_malloc(ASE_MQ_NAME_LEN); + + // Length terminated string copy + ase_string_copy(mq_str, mq_name_str, ASE_MQ_NAME_LEN); + + // Tokenize string and get first phrase --- "app2sim" OR "sim2app" + char *token; + token = strtok(mq_str, "_"); + + // If name looks weird, throw an error, crash gracefully + if (token == NULL) { + ase_free_buffer(mq_str); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + if ((ase_strncmp(token, "sim2app", 7) != 0) + && (ase_strncmp(token, "app2sim", 7) != 0)) { + ASE_ERR + (" ** ERROR **: Named pipe name is neither app2sim nor sim2app!\n"); + ase_free_buffer(mq_str); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { +#ifdef SIM_SIDE + if (ase_strncmp(token, "sim2app", 7) == 0) { + ret = O_WRONLY; + } else if (ase_strncmp(token, "app2sim", 7) == 0) { + ret = O_RDONLY | O_NONBLOCK; + } +#else + if (ase_strncmp(token, "sim2app", 7) == 0) { + ret = O_RDONLY; + } else if (ase_strncmp(token, "app2sim", 7) == 0) { + ret = O_WRONLY; + } +#endif + + // Free memory + ase_free_buffer(mq_str); + } + } + + return ret; +} + + +/* + * ipc_init: Initialize IPC messaging structure + * DOES not create or open the IPC, simply initializes the structures + */ +void ipc_init(void) +{ + FUNC_CALL_ENTRY; + + int ipc_iter; + + // Evaluate ase_workdir_path + ase_workdir_path = (char *) ase_malloc(ASE_FILEPATH_LEN); + ase_eval_session_directory(); + + // Initialize named pipe array + for (ipc_iter = 0; ipc_iter < ASE_MQ_INSTANCES; ipc_iter++) { + // Set name + ase_string_copy(mq_array[ipc_iter].name, + mq_name_arr[ipc_iter], ASE_MQ_NAME_LEN); + + // Compute path + snprintf(mq_array[ipc_iter].path, ASE_FILEPATH_LEN, + "%s/%s", ase_workdir_path, + mq_array[ipc_iter].name); + // Set permission flag + mq_array[ipc_iter].perm_flag = + get_smq_perm_flag(mq_name_arr[ipc_iter]); + if (mq_array[ipc_iter].perm_flag == -1) { + ASE_ERR + ("Message pipes opened up with wrong permissions --- unexpected error"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + } + + // Remove IPCs if already there +#ifdef SIM_SIDE + for (ipc_iter = 0; ipc_iter < ASE_MQ_INSTANCES; ipc_iter++) + unlink(mq_array[ipc_iter].path); +#endif + + FUNC_CALL_EXIT; +} + + +/* + * mqueue_create: Create a simplex mesaage queue by passing a name + */ +void mqueue_create(char *mq_name_suffix) +{ + FUNC_CALL_ENTRY; + + char *mq_path; + int ret; + + mq_path = ase_malloc(ASE_FILEPATH_LEN); + snprintf(mq_path, ASE_FILEPATH_LEN, "%s/%s", ase_workdir_path, + mq_name_suffix); + + ret = mkfifo(mq_path, S_IRUSR | S_IWUSR); + if (ret == -1) { + ASE_ERR("Error creating IPC %s\n", mq_path); + ASE_ERR("Consider re-compiling OPAE libraries !\n"); + } + // Add IPC to list +#ifdef SIM_SIDE + add_to_ipc_list("MQ", mq_path); + fflush(local_ipc_fp); +#endif + + // Free memories + free(mq_path); + + FUNC_CALL_EXIT; +} + + +/* + * mqueue_open : Open IPC messaging device + * + * NOTES: + * - Named pipes require reader to be ready for non-blocking open to + * proceed. This may not be possible in an ASE environment. + * - This may be solved by having a dummy reader the WRONLY fifo, then + * close it after ASE's real fd is created successfully. + * + */ +int mqueue_open(char *mq_name, int perm_flag) +{ + FUNC_CALL_ENTRY; + + int mq; + char *mq_path; + + mq_path = ase_malloc(ASE_FILEPATH_LEN); + snprintf(mq_path, ASE_FILEPATH_LEN, "%s/%s", ase_workdir_path, + mq_name); + + // Dummy function to open WRITE only MQs + // Named pipe requires non-blocking write-only move on from here + // only when reader is ready. +#ifdef SIM_SIDE + int dummy_fd; + if (perm_flag == O_WRONLY) { + ASE_DBG("Opening IPC in write-only mode with dummy fd\n"); + dummy_fd = open(mq_path, O_RDONLY | O_NONBLOCK); + } +#endif + + mq = open(mq_path, perm_flag); + if (mq == -1) { + ASE_ERR("Error opening IPC %s\n", mq_path); +#ifdef SIM_SIDE + ase_error_report("open", errno, ASE_OS_FOPEN_ERR); + start_simkill_countdown(); +#else + perror("open"); + exit(1); +#endif + } +#ifdef SIM_SIDE + if (perm_flag == O_WRONLY) { + close(dummy_fd); + } +#endif + + FUNC_CALL_EXIT; + + // Free temp variables + free(mq_path); + + return mq; +} + + +// ------------------------------------------------------- +// mqueue_close(int): close MQ by descriptor +// ------------------------------------------------------- +void mqueue_close(int mq) +{ + FUNC_CALL_ENTRY; + + int ret; + ret = close(mq); + if (ret == -1) { +#ifdef SIM_SIDE + ASE_DBG("Error closing IPC\n"); +#endif + } + + FUNC_CALL_EXIT; +} + + +// ----------------------------------------------------------- +// mqueue_destroy(): Unlink message queue, must be called from API +// ----------------------------------------------------------- +void mqueue_destroy(char *mq_name_suffix) +{ + FUNC_CALL_ENTRY; + + char *mq_path; + int ret; + + // ASE malloc will allocate buffer, mq_path will be set correctly + mq_path = ase_malloc(ASE_FILEPATH_LEN); + + // Generate mq_path variable from given and $ASE_WORKDIR + snprintf(mq_path, ASE_FILEPATH_LEN, "%s/%s", ase_workdir_path, + mq_name_suffix); + + // Attempt to unlink the pipe + ret = unlink(mq_path); + if (ret == -1) { + ASE_ERR + ("Message queue %s could not be removed, please remove manually\n", + mq_name_suffix); + } + // Free memory + free(mq_path); + + FUNC_CALL_EXIT; +} + + +// ------------------------------------------------------------ +// mqueue_send(): Easy send function +// - Typecast any message as a character array and ram it in. +// ------------------------------------------------------------ +void mqueue_send(int mq, const char *str, int size) +{ + FUNC_CALL_ENTRY; + + int ret_tx; + ret_tx = write(mq, (void *) str, size); + + if ((ret_tx == 0) || (ret_tx != size)) { +#ifdef ASE_DEBUG + perror("write"); + ASE_DBG("write() returned wrong data size."); +#endif + } + + FUNC_CALL_EXIT; +} + + +// ------------------------------------------------------------------ +// mqueue_recv(): Easy receive function +// - Typecast message back to a required type +// ------------------------------------------------------------------ +int mqueue_recv(int mq, char *str, int size) +{ + FUNC_CALL_ENTRY; + + int ret; + + ret = read(mq, str, size); + FUNC_CALL_EXIT; + if (ret > 0) { + return ASE_MSG_PRESENT; + } else { + return ASE_MSG_ABSENT; + } +} diff --git a/ase/sw/protocol_backend.c b/ase/sw/protocol_backend.c new file mode 100644 index 000000000000..11a3792801e1 --- /dev/null +++ b/ase/sw/protocol_backend.c @@ -0,0 +1,1495 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: + * - Protocol backend for keeping IPCs alive + * - Interfacing with DPI-C, messaging + * - Interface to page table + * + * Language : C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + * + */ + +#include "ase_common.h" + +// Log-level +int glbl_loglevel = ASE_LOG_MESSAGE; + +// Global test complete counter +// Keeps tabs of how many session_deinits were received +int glbl_test_cmplt_cnt; + +// Global umsg mode, lookup before issuing UMSG +int glbl_umsgmode; +char umsg_mode_msg[ASE_LOGGER_LEN]; + +// Session status +int session_empty; + +// MMIO Respons lock +// pthread_mutex_t mmio_resp_lock; + +// User clock frequency +float f_usrclk; + +/* + * Generate scope data + */ +svScope scope; +void scope_function(void) +{ + scope = svGetScope(); +} + + +/* + * ASE instance already running + * - If instance is found, return its process ID, else return 0 + */ +int ase_instance_running(void) +{ + FUNC_CALL_ENTRY; + + int ase_simv_pid; + + // If Ready file does not exist + if (access(ASE_READY_FILENAME, F_OK) == -1) { + ase_simv_pid = 0; + } + // If ready file exists + else { + char *pwd_str; + pwd_str = ase_malloc(ASE_FILEPATH_LEN); + ase_simv_pid = + ase_read_lock_file(getcwd(pwd_str, ASE_FILEPATH_LEN)); + free(pwd_str); + } + + FUNC_CALL_EXIT; + return ase_simv_pid; +} + + +/* + * DPI: CONFIG path data exchange + */ +void sv2c_config_dex(const char *str) +{ + // Allocate memory + sv2c_config_filepath = ase_malloc(ASE_FILEPATH_LEN); + + // Check that input string is not NULL + if (str == NULL) { + ASE_MSG("sv2c_config_dex => Input string is unusable\n"); + ase_free_buffer(sv2c_config_filepath); + } else { + // If Malloc fails + if (sv2c_config_filepath != NULL) { + // Attempt string copy and keep safe + ase_string_copy(sv2c_config_filepath, str, + ASE_FILEPATH_LEN); +#ifdef ASE_DEBUG + ASE_DBG("sv2c_config_filepath = %s\n", + sv2c_config_filepath); +#endif + + // Check if file exists + if (access(sv2c_config_filepath, F_OK) == 0) { + ASE_MSG("+CONFIG %s file found !\n", + sv2c_config_filepath); + } else { + ASE_ERR + ("** WARNING ** +CONFIG file was not found, will revert to DEFAULTS\n"); + memset(sv2c_config_filepath, 0, + ASE_FILEPATH_LEN); + } + } + } +} + + +/* + * DPI: SCRIPT path data exchange + */ +void sv2c_script_dex(const char *str) +{ + if (str == NULL) { + ASE_MSG("sv2c_script_dex => Input string is unusable\n"); + } else { + sv2c_script_filepath = ase_malloc(ASE_FILEPATH_LEN); + if (sv2c_script_filepath != NULL) { + ase_string_copy(sv2c_script_filepath, str, + ASE_FILEPATH_LEN); +#ifdef ASE_DEBUG + ASE_DBG("sv2c_script_filepath = %s\n", + sv2c_script_filepath); +#endif + + // Check for existance of file + if (access(sv2c_script_filepath, F_OK) == 0) { + ASE_MSG("+SCRIPT %s file found !\n", + sv2c_script_filepath); + } else { + ASE_MSG + ("** WARNING ** +SCRIPT file was not found, will revert to DEFAULTS\n"); + memset(sv2c_script_filepath, 0, + ASE_FILEPATH_LEN); + } + } + } +} + + +/* + * DPI: Return ASE seed + */ +uint32_t get_ase_seed(void) +{ + // return ase_seed; + return 0xFF; +} + + +/* + * DPI: WriteLine Data exchange + */ +void wr_memline_dex(cci_pkt *pkt) +{ + FUNC_CALL_ENTRY; + + uint64_t phys_addr; + uint64_t *wr_target_vaddr = (uint64_t *) NULL; + int intr_id; + //int ret_fd; +/* #ifndef DEFEATURE_ATOMICS */ +/* uint64_t *rd_target_vaddr = (uint64_t*)NULL; */ +/* long long cmp_qword; // Data to be compared */ +/* long long new_qword; // Data to be writen if compare passes */ +/* #endif */ + + if (pkt->mode == CCIPKT_WRITE_MODE) { + /* + * Normal write operation + * Takes Write request and performs verbatim + */ + // Get cl_addr, deduce wr_target_vaddr + phys_addr = (uint64_t) pkt->cl_addr << 6; + wr_target_vaddr = + ase_fakeaddr_to_vaddr((uint64_t) phys_addr); + + // Write to memory + ase_memcpy(wr_target_vaddr, (char *) pkt->qword, + CL_BYTE_WIDTH); + + // Success + pkt->success = 1; + } else if (pkt->mode == CCIPKT_INTR_MODE) { + /* + * Interrupt operation + */ + // Trigger interrupt action + intr_id = pkt->intr_id; + ase_interrupt_generator(intr_id); + + // Success + pkt->success = 1; + } +/* #ifndef DEFEATURE_ATOMICS */ +/* else if (pkt->mode == CCIPKT_ATOMIC_MODE) */ +/* { */ +/* /\* */ +/* * This is a special mode in which read response goes back */ +/* * WRITE request is responded with a READ response */ +/* *\/ */ +/* // Specifics of the requested compare operation */ +/* cmp_qword = pkt->qword[0]; */ +/* new_qword = pkt->qword[4]; */ + +/* // Get cl_addr, deduce rd_target_vaddr */ +/* phys_addr = (uint64_t)pkt->cl_addr << 6; */ +/* rd_target_vaddr = ase_fakeaddr_to_vaddr((uint64_t)phys_addr); */ + +/* // Perform read first and set response packet accordingly */ +/* ase_memcpy((char*)pkt->qword, rd_target_vaddr, CL_BYTE_WIDTH); */ + +/* // Get cl_addr, deduct wr_target, use qw_start to determine exact qword */ +/* wr_target_vaddr = (uint64_t*)( (uint64_t)rd_target_vaddr + pkt->qw_start*8 ); */ + +/* // CmpXchg output */ +/* pkt->success = (int)__sync_bool_compare_and_swap (wr_target_vaddr, cmp_qword, new_qword); */ + +/* // Debug output */ +/* #ifdef ASE_DEBUG */ +/* */ +/* ASE_DBG("CmpXchg_op=%d\n", pkt->success); */ +/* */ +/* #endif */ +/* } */ +/* #endif */ + + FUNC_CALL_EXIT; +} + + +/* + * DPI: ReadLine Data exchange + */ +void rd_memline_dex(cci_pkt *pkt) +{ + FUNC_CALL_ENTRY; + + uint64_t phys_addr; + uint64_t *rd_target_vaddr = (uint64_t *) NULL; + + // Get cl_addr, deduce rd_target_vaddr + phys_addr = (uint64_t) pkt->cl_addr << 6; + rd_target_vaddr = ase_fakeaddr_to_vaddr((uint64_t) phys_addr); + + // Read from memory + ase_memcpy((char *) pkt->qword, rd_target_vaddr, CL_BYTE_WIDTH); + + FUNC_CALL_EXIT; +} + + +/* + * DPI: MMIO response + */ +void mmio_response(struct mmio_t *mmio_pkt) +{ + FUNC_CALL_ENTRY; + + // Lock channel + // pthread_mutex_lock (&mmio_resp_lock); + +#ifdef ASE_DEBUG + print_mmiopkt(fp_memaccess_log, "MMIO Got ", mmio_pkt); +#endif + + // Send MMIO Response + mqueue_send(sim2app_mmiorsp_tx, (char *) mmio_pkt, sizeof(mmio_t)); + + // Unlock channel + // pthread_mutex_unlock (&mmio_resp_lock); + + FUNC_CALL_EXIT; +} + + +/* + * ASE Interrupt generator handle + */ +void ase_interrupt_generator(int id) +{ + ASE_ERR("*FIXME* Nothing happening here !\n"); +} + + +/* + * DPI: Reset response + */ +void sw_reset_response(void) +{ + FUNC_CALL_ENTRY; + + // Send portctrl_rsp message + mqueue_send(sim2app_portctrl_rsp_tx, completed_str_msg, + ASE_MQ_MSGSIZE); + + FUNC_CALL_EXIT; +} + + +/* + * Count error flag ping/pong + */ +volatile int count_error_flag; +void count_error_flag_pong(int flag) +{ + count_error_flag = flag; +} + + +/* + * Update global disable/enable + */ +int glbl_dealloc_allowed; +void update_glbl_dealloc(int flag) +{ + glbl_dealloc_allowed = flag; +} + + +/* + * Populating required DFH in BBS + */ + +// Capability CSRs +uint64_t *csr_port_capability; +uint64_t *csr_port_umsg; + +// UMSG CSRs +uint64_t *csr_umsg_capability; +uint64_t *csr_umsg_base_address; +uint64_t *csr_umsg_mode; + +/* + * Initialize: Populate FME DFH block + * When initialized, this is called + * update*function is called when UMSG is to be set up + */ +void initialize_fme_dfh(struct buffer_t *buf) +{ + FUNC_CALL_ENTRY; + + uint8_t *port_vbase = (uint8_t *) (uintptr_t) buf->pbase; + + /* + * PORT CSRs + */ + // PORT_CAPABILITY + csr_port_capability = (uint64_t *) (port_vbase + 0x0030); + *csr_port_capability = (0x100 << 23) + (0x0 << 0); + + // PORT_UMSG DFH + csr_port_umsg = (uint64_t *) (port_vbase + 0x2000); + *csr_port_umsg = + ((uint64_t) 0x3 << 60) | ((uint64_t) 0x1000 << 39) | (0x11 << + 0); + + /* + * UMSG settings + */ + // UMSG_CAPABILITY + csr_umsg_capability = (uint64_t *) (port_vbase + 0x2008); + *csr_umsg_capability = (0x0 << 9) + (0x0 << 8) + (0x8 << 0); + + // UMSG_BASE_ADDRESS (only initalize address, update function will update CSR) + csr_umsg_base_address = (uint64_t *) (port_vbase + 0x2010); + + // UMSG_MODE + csr_umsg_mode = (uint64_t *) (port_vbase + 0x2018); + *csr_umsg_mode = 0x0; + + FUNC_CALL_EXIT; +} + + +// Update FME DFH after UMAS becomes known +void update_fme_dfh(struct buffer_t *umas) +{ + // Write UMAS address + *csr_umsg_base_address = (uint64_t) umas->pbase; +} + + +/* ******************************************************************** + * ASE Listener thread + * -------------------------------------------------------------------- + * vbase/pbase exchange THREAD + * when an allocate request is received, the buffer is copied into a + * linked list. The reply consists of the pbase, fakeaddr and fd_ase. + * When a deallocate message is received, the buffer is invalidated. + * + * MMIO Request + * Calls MMIO Dispatch task in ccip_emulator + * + * *******************************************************************/ +int ase_listener(void) +{ + // FUNC_CALL_ENTRY; + + // ---------------------------------------------------------------------- // + /* + * Port Control message + * Format: + * ----------------------------------------------------------------- + * Supported commands | + * ASE_INIT | Session control - sends PID to + * | + * AFU_RESET <0,1> | AFU reset handle + * UMSG_MODE <8-bit mask> | UMSG mode control + * + * ASE responds with "COMPLETED" as a string, there is no + * expectation of a string check + * + */ + char portctrl_msgstr[ASE_MQ_MSGSIZE]; + char portctrl_cmd[ASE_MQ_MSGSIZE]; + int portctrl_value; + memset(portctrl_msgstr, 0, ASE_MQ_MSGSIZE); + memset(portctrl_cmd, 0, ASE_MQ_MSGSIZE); + + // Allocate a completed string + completed_str_msg = (char *) ase_malloc(ASE_MQ_MSGSIZE); + snprintf(completed_str_msg, 10, "COMPLETED"); + + // Simulator is not in lockdown mode (simkill not in progress) + if (self_destruct_in_progress == 0) { + if (mqueue_recv + (app2sim_portctrl_req_rx, (char *) portctrl_msgstr, + ASE_MQ_MSGSIZE) == ASE_MSG_PRESENT) { + sscanf(portctrl_msgstr, "%s %d", portctrl_cmd, + &portctrl_value); + if (ase_strncmp(portctrl_cmd, "AFU_RESET", 9) == 0) { + // AFU Reset control + portctrl_value = + (portctrl_value != 0) ? 1 : 0; + + // Wait until transactions clear + // AFU Reset trigger function will wait until channels clear up + afu_softreset_trig(0, portctrl_value); + + // Reset response is returned from simulator once queues are cleared + // Simulator cannot be held up here. + } else + if (ase_strncmp(portctrl_cmd, "UMSG_MODE", 9) + == 0) { + // Umsg mode setting here + glbl_umsgmode = + portctrl_value & 0xFFFFFFFF; + snprintf(umsg_mode_msg, ASE_LOGGER_LEN, + "UMSG Mode mask set to 0x%x", + glbl_umsgmode); + buffer_msg_inject(1, umsg_mode_msg); + + // Send portctrl_rsp message + mqueue_send(sim2app_portctrl_rsp_tx, + completed_str_msg, + ASE_MQ_MSGSIZE); + } else if (ase_strncmp(portctrl_cmd, "ASE_INIT", 8) + == 0) { + ASE_INFO("Session requested by PID = %d\n", + portctrl_value); + // Generate new timestamp + put_timestamp(); + + // Generate session ID path + snprintf(tstamp_filepath, ASE_FILEPATH_LEN, + "%s/%s", ase_workdir_path, + TSTAMP_FILENAME); + // Print timestamp + glbl_session_id = ase_malloc(20); + get_timestamp(glbl_session_id); + ASE_MSG("Session ID => %s\n", + glbl_session_id); + + session_empty = 0; + + // Send portctrl_rsp message + mqueue_send(sim2app_portctrl_rsp_tx, + completed_str_msg, + ASE_MQ_MSGSIZE); + } else + if (ase_strncmp + (portctrl_cmd, "ASE_SIMKILL", 11) == 0) { +#ifdef ASE_DEBUG + ASE_MSG + ("ASE_SIMKILL requested, processing options... \n"); +#endif + // ------------------------------------------------------------- // + // Update regression counter + glbl_test_cmplt_cnt = + glbl_test_cmplt_cnt + 1; + // Mode specific exit behaviour + if ((cfg->ase_mode == + ASE_MODE_DAEMON_NO_SIMKILL) + && (session_empty == 0)) { + ASE_MSG + ("ASE running in daemon mode (see ase.cfg)\n"); + ASE_MSG + ("Reseting buffers ... Simulator RUNNING\n"); + ase_reset_trig(); + ase_destroy(); + ASE_INFO + ("Ready to run next test\n"); + session_empty = 1; + buffer_msg_inject(0, + TEST_SEPARATOR); + } else if (cfg->ase_mode == + ASE_MODE_DAEMON_SIMKILL) { + ASE_INFO + ("ASE Timeout SIMKILL will happen soon\n"); + } else if (cfg->ase_mode == + ASE_MODE_DAEMON_SW_SIMKILL) { + ASE_INFO + ("ASE recognized a SW simkill (see ase.cfg)... Simulator will EXIT\n"); + run_clocks(500); + ase_perror_teardown(); + start_simkill_countdown(); + } else if (cfg->ase_mode == + ASE_MODE_REGRESSION) { + if (cfg->ase_num_tests == + glbl_test_cmplt_cnt) { + ASE_INFO + ("ASE completed %d tests (see supplied ASE config file)... Simulator will EXIT\n", + cfg->ase_num_tests); + run_clocks(500); + ase_perror_teardown(); + start_simkill_countdown(); + } else { + ase_reset_trig(); + } + } + // Check for simulator sanity -- if transaction counts dont match + // Kill the simulation ASAP -- DEBUG feature only +#ifdef ASE_DEBUG + count_error_flag_ping(); + if (count_error_flag != 0) { + ASE_ERR + ("** ERROR ** Transaction counts do not match, something got lost\n"); + run_clocks(500); + ase_perror_teardown(); + start_simkill_countdown(); + } +#endif + + // Send portctrl_rsp message + mqueue_send(sim2app_portctrl_rsp_tx, + completed_str_msg, + ASE_MQ_MSGSIZE); + + // Clean up session OD + ase_free_buffer(glbl_session_id); + } else { + ASE_ERR + ("Undefined Port Control function ... IGNORING\n"); + + // Send portctrl_rsp message + mqueue_send(sim2app_portctrl_rsp_tx, + completed_str_msg, + ASE_MQ_MSGSIZE); + } + } + // ------------------------------------------------------------------------------- // + + /* + * Buffer Allocation Replicator + */ + struct buffer_t ase_buffer; + char logger_str[ASE_LOGGER_LEN]; + char incoming_alloc_msgstr[ASE_MQ_MSGSIZE]; + memset(incoming_alloc_msgstr, 0, ASE_MQ_MSGSIZE); + + // Receive a DPI message and get information from replicated buffer + ase_empty_buffer(&ase_buffer); + if (mqueue_recv + (app2sim_alloc_rx, (char *) incoming_alloc_msgstr, + ASE_MQ_MSGSIZE) == ASE_MSG_PRESENT) { + // Typecast string to buffer_t + ase_memcpy((char *) &ase_buffer, + incoming_alloc_msgstr, + sizeof(struct buffer_t)); + + // Allocate action + ase_alloc_action(&ase_buffer); + ase_buffer.is_privmem = 0; + if (ase_buffer.index == 0) { + ase_buffer.is_mmiomap = 1; + } else { + ase_buffer.is_mmiomap = 0; + } + + // Format workspace info string + memset(logger_str, 0, ASE_LOGGER_LEN); + if (ase_buffer.is_mmiomap) { + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "MMIO map Allocated "); + initialize_fme_dfh(&ase_buffer); + } else if (ase_buffer.is_umas) { + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "UMAS Allocated "); + update_fme_dfh(&ase_buffer); + } else { + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "Buffer %d Allocated ", + ase_buffer.index); + } + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + " (located /dev/shm/%s) =>\n", + ase_buffer.memname); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "\t\tHost App Virtual Addr = 0x%" PRIx64 + "\n", ase_buffer.vbase); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "\t\tHW Physical Addr = 0x%" PRIx64 + "\n", ase_buffer.fake_paddr); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "\t\tHW CacheAligned Addr = 0x%" PRIx64 + "\n", ase_buffer.fake_paddr >> 6); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "\t\tWorkspace Size (bytes) = %" PRId32 + "\n", ase_buffer.memsize); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, "\n"); + + // Inject buffer message + buffer_msg_inject(1, logger_str); + + // Standard oneline message ---> Hides internal info + ase_buffer_oneline(&ase_buffer); + + // Write buffer information to file + if ((ase_buffer.is_mmiomap == 0) + || (ase_buffer.is_privmem == 0)) { + // Flush info to file + if (fp_workspace_log != NULL) { + fprintf(fp_workspace_log, "%s", + logger_str); + fflush(fp_workspace_log); + } + } + // Debug only +#ifdef ASE_DEBUG + ase_buffer_info(&ase_buffer); +#endif + } + // ------------------------------------------------------------------------------- // + char incoming_dealloc_msgstr[ASE_MQ_MSGSIZE]; + memset(incoming_dealloc_msgstr, 0, ASE_MQ_MSGSIZE); + + ase_empty_buffer(&ase_buffer); + if (mqueue_recv + (app2sim_dealloc_rx, (char *) incoming_dealloc_msgstr, + ASE_MQ_MSGSIZE) == ASE_MSG_PRESENT) { + // Typecast string to buffer_t + ase_memcpy((char *) &ase_buffer, + incoming_dealloc_msgstr, + sizeof(struct buffer_t)); + + // Format workspace info string + memset(logger_str, 0, ASE_LOGGER_LEN); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, + "\nBuffer %d Deallocated =>\n", + ase_buffer.index); + snprintf(logger_str + strlen(logger_str), + ASE_LOGGER_LEN, "\n"); + + // Deallocate action + ase_dealloc_action(&ase_buffer, 1); + + // Inject buffer message + buffer_msg_inject(1, logger_str); + + // Standard oneline message ---> Hides internal info + ase_buffer.valid = ASE_BUFFER_INVALID; + ase_buffer_oneline(&ase_buffer); + + // Debug only +#ifdef ASE_DEBUG + ase_buffer_info(&ase_buffer); +#endif + } + // ------------------------------------------------------------------------------- // + /* + * MMIO request listener + */ + // char mmio_mapstr[ASE_MQ_MSGSIZE]; + // Message string + // struct mmio_t *mmio_pkt; + + // Receive csr_write packet + if (mqueue_recv + (app2sim_mmioreq_rx, (char *) incoming_mmio_pkt, + sizeof(struct mmio_t)) == ASE_MSG_PRESENT) { + // ase_memcpy(incoming_mmio_pkt, (mmio_t *)mmio_mapstr, sizeof(struct mmio_t)); + +#ifdef ASE_DEBUG + print_mmiopkt(fp_memaccess_log, "MMIO Sent", + incoming_mmio_pkt); +#endif + mmio_dispatch(0, incoming_mmio_pkt); + } + // ------------------------------------------------------------------------------- // + /* + * UMSG engine + */ + char umsg_mapstr[ASE_MQ_MSGSIZE]; + + // cleanse string before reading + if (mqueue_recv + (app2sim_umsg_rx, (char *) umsg_mapstr, + sizeof(struct umsgcmd_t)) == ASE_MSG_PRESENT) { + ase_memcpy(incoming_umsg_pkt, + (umsgcmd_t *) umsg_mapstr, + sizeof(struct umsgcmd_t)); + + // Hint trigger + incoming_umsg_pkt->hint = + (glbl_umsgmode >> (4 * incoming_umsg_pkt->id)) + & 0xF; + + // dispatch to event processing +#ifdef ASE_ENABLE_UMSG_FEATURE + umsg_dispatch(0, incoming_umsg_pkt); +#else + ASE_ERR + ("UMsg is only supported in the integrated configuration!\n"); + ASE_ERR + (" Simulator will shut down now.\n"); + start_simkill_countdown(); +#endif + } + // ------------------------------------------------------------------------------- // + } else { +#ifdef ASE_DEBUG + ASE_DBG + ("Simulator is in Lockdown mode, Simkill in progress\n"); + sleep(1); +#endif + } + + + // FUNC_CALL_EXIT; + return 0; +} + + +/* + * Calculate Sysmem & CAPCM ranges to be used by ASE + */ +void calc_phys_memory_ranges(void) +{ + sysmem_size = cfg->phys_memory_available_gb * pow(1024, 3); + sysmem_phys_lo = 0; + sysmem_phys_hi = sysmem_size - 1; + + // Calculate address mask + PHYS_ADDR_PREFIX_MASK = + ((sysmem_phys_hi >> MEMBUF_2MB_ALIGN) << MEMBUF_2MB_ALIGN); +#ifdef ASE_DEBUG + ASE_DBG("PHYS_ADDR_PREFIX_MASK = 0x%" PRIx64 "\n", + (uint64_t) PHYS_ADDR_PREFIX_MASK); +#endif + + ASE_MSG(" System memory range => 0x%016" PRIx64 "-0x%016" + PRIx64 " | %" PRId64 "~%" PRId64 " GB \n", sysmem_phys_lo, + sysmem_phys_hi, sysmem_phys_lo / (uint64_t) pow(1024, 3), + (uint64_t) (sysmem_phys_hi + 1) / (uint64_t) pow(1024, 3)); +} + + +// ----------------------------------------------------------------------- +// DPI Initialize routine +// - Setup message queues +// - Start buffer replicator, csr_write listener thread +// ----------------------------------------------------------------------- +int ase_init(void) +{ + FUNC_CALL_ENTRY; + + // Set loglevel + glbl_loglevel = ase_calc_loglevel(); + + // Set stdout bufsize to empty immediately + // setvbuf(stdout, NULL, _IONBF, 0); + setbuf(stdout, NULL); + + // Set self_destruct flag = 0, SIMulator is not in lockdown + self_destruct_in_progress = 0; + + // Graceful kill handlers + register_signal(SIGTERM, start_simkill_countdown); + register_signal(SIGINT, start_simkill_countdown); + register_signal(SIGQUIT, start_simkill_countdown); + register_signal(SIGHUP, start_simkill_countdown); + + // Runtime error handler (print backtrace) + register_signal(SIGSEGV, backtrace_handler); + register_signal(SIGBUS, backtrace_handler); + register_signal(SIGABRT, backtrace_handler); + + // Ignore SIGPIPE + signal(SIGPIPE, SIG_IGN); + + // Get PID + ase_pid = getpid(); + ASE_MSG("PID of simulator is %d\n", ase_pid); + + // Allocate incoming_mmio_pkt + incoming_mmio_pkt = (struct mmio_t *) ase_malloc(sizeof(mmio_t)); + + // Allocate incoming_umsg_pkt + incoming_umsg_pkt = + (struct umsgcmd_t *) ase_malloc(sizeof(struct umsgcmd_t)); + + // ASE configuration management + // ase_config_parse(ASE_CONFIG_FILE); + ase_config_parse(sv2c_config_filepath); + + // Evaluate IPCs + ipc_init(); + + ASE_MSG("Current Directory located at =>\n"); + ASE_MSG("%s\n", ase_workdir_path); + + // Create IPC cleanup setup + create_ipc_listfile(); + + // Sniffer file stat path + ccip_sniffer_file_statpath = ase_malloc(ASE_FILEPATH_LEN); + snprintf(ccip_sniffer_file_statpath, ASE_FILEPATH_LEN, + "%s/ccip_warning_and_errors.txt", ase_workdir_path); + + // Remove existing error log files from previous run + if (access(ccip_sniffer_file_statpath, F_OK) == 0) { + if (unlink(ccip_sniffer_file_statpath) == 0) { + ASE_MSG + ("Removed sniffer log file from previous run\n"); + } + } + + /* + * Debug logs + */ +#ifdef ASE_DEBUG + // Create a memory access log + fp_memaccess_log = fopen("aseafu_access.log", "w"); + if (fp_memaccess_log == NULL) { + ASE_ERR + (" [DEBUG] Memory access debug logger initialization failed !\n"); + } else { + ASE_DBG("Memory access debug logger initialized\n"); + } + + // Page table tracker + fp_pagetable_log = fopen("ase_pagetable.log", "w"); + if (fp_pagetable_log == NULL) { + ASE_ERR + (" [DEBUG] ASE pagetable logger initialization failed !\n"); + } else { + ASE_DBG("ASE pagetable logger initialized\n"); + } +#endif + + // Set up message queues + ASE_MSG("Creating Messaging IPCs...\n"); + int ipc_iter; + for (ipc_iter = 0; ipc_iter < ASE_MQ_INSTANCES; ipc_iter++) + mqueue_create(mq_array[ipc_iter].name); + + // Open message queues + app2sim_alloc_rx = + mqueue_open(mq_array[0].name, mq_array[0].perm_flag); + app2sim_mmioreq_rx = + mqueue_open(mq_array[1].name, mq_array[1].perm_flag); + app2sim_umsg_rx = + mqueue_open(mq_array[2].name, mq_array[2].perm_flag); + sim2app_alloc_tx = + mqueue_open(mq_array[3].name, mq_array[3].perm_flag); + sim2app_mmiorsp_tx = + mqueue_open(mq_array[4].name, mq_array[4].perm_flag); + app2sim_portctrl_req_rx = + mqueue_open(mq_array[5].name, mq_array[5].perm_flag); + app2sim_dealloc_rx = + mqueue_open(mq_array[6].name, mq_array[6].perm_flag); + sim2app_dealloc_tx = + mqueue_open(mq_array[7].name, mq_array[7].perm_flag); + sim2app_portctrl_rsp_tx = + mqueue_open(mq_array[8].name, mq_array[8].perm_flag); + sim2app_intr_request_tx = + mqueue_open(mq_array[9].name, mq_array[9].perm_flag); + + // Calculate memory map regions + ASE_MSG("Calculating memory map...\n"); + calc_phys_memory_ranges(); + + // Random number for csr_pinned_addr + /* if (cfg->enable_reuse_seed) */ + /* { */ + /* ase_seed = ase_read_seed (); */ + /* } */ + /* else */ + /* { */ + /* ase_seed = generate_ase_seed(); */ + /* ase_write_seed ( ase_seed ); */ + /* } */ + ase_write_seed(cfg->ase_seed); + srand(cfg->ase_seed); + + // Open Buffer info log + fp_workspace_log = fopen("workspace_info.log", "wb"); + if (fp_workspace_log == (FILE *) NULL) { + ase_error_report("fopen", errno, ASE_OS_FOPEN_ERR); + } else { + ASE_INFO_2 + ("Information about allocated buffers => workspace_info.log \n"); + } + + fflush(stdout); + + FUNC_CALL_EXIT; + return 0; +} + + +// ----------------------------------------------------------------------- +// ASE ready indicator: Print a message that ASE is ready to go. +// Controls run-modes +// ----------------------------------------------------------------------- +int ase_ready(void) +{ + FUNC_CALL_ENTRY; + + // App run command + app_run_cmd = ase_malloc(ASE_FILEPATH_LEN); + + // Set test_cnt to 0 + glbl_test_cmplt_cnt = 0; + + // Write lock file + ase_write_lock_file(); + + // Display "Ready for simulation" + ASE_INFO + ("** ATTENTION : BEFORE running the software application **\n"); + ASE_INFO + ("Set env(ASE_WORKDIR) in terminal where application will run (copy-and-paste) =>\n"); + ASE_INFO("$SHELL | Run:\n"); + ASE_INFO + ("---------+---------------------------------------------------\n"); + ASE_INFO("bash/zsh | export ASE_WORKDIR=%s\n", ase_workdir_path); + ASE_INFO("tcsh/csh | setenv ASE_WORKDIR %s\n", ase_workdir_path); + ASE_INFO + ("For any other $SHELL, consult your Linux administrator\n"); + ASE_INFO("\n"); + + // Run ase_regress.sh here + if (cfg->ase_mode == ASE_MODE_REGRESSION) { + ASE_INFO("Starting ase_regress.sh script...\n"); + if ((sv2c_script_filepath != NULL) + && (strlen(sv2c_script_filepath) != 0)) { + snprintf(app_run_cmd, ASE_FILEPATH_LEN, "%s &", + sv2c_script_filepath); + } else { + ase_string_copy(app_run_cmd, "./ase_regress.sh &", + ASE_FILEPATH_LEN); + } + + // Run the regress application + if (system(app_run_cmd) == -1) { + ASE_INFO_2 + ("ASE had some problem starting script pointed by ASE_SCRIPT\n"); + ASE_INFO_2("Tests may be run manually instead\n"); + } + } else { + ASE_INFO("Ready for simulation...\n"); + ASE_INFO("Press CTRL-C to close simulator...\n"); + } + + fflush(stdout); + + FUNC_CALL_EXIT; + return 0; +} + + +/* + * DPI simulation timeout counter + * - When CTRL-C is pressed, start teardown sequence + * - TEARDOWN SEQUENCE: + * - Close and unlink message queues + * - Close and unlink shared memories + * - Destroy linked list + * - Delete .ase_ready + * - Send $finish to VCS + */ +void start_simkill_countdown(void) +{ + FUNC_CALL_ENTRY; + +#ifdef ASE_DEBUG + ASE_DBG("Caught a SIG\n"); +#endif + + // Close and unlink message queue + ASE_MSG("Closing message queue and unlinking...\n"); + + // Close message queues + mqueue_close(app2sim_alloc_rx); + mqueue_close(sim2app_alloc_tx); + mqueue_close(app2sim_mmioreq_rx); + mqueue_close(sim2app_mmiorsp_tx); + mqueue_close(app2sim_umsg_rx); + mqueue_close(app2sim_portctrl_req_rx); + mqueue_close(app2sim_dealloc_rx); + mqueue_close(sim2app_dealloc_tx); + mqueue_close(sim2app_portctrl_rsp_tx); + mqueue_close(sim2app_intr_request_tx); + + int ipc_iter; + for (ipc_iter = 0; ipc_iter < ASE_MQ_INSTANCES; ipc_iter++) + mqueue_destroy(mq_array[ipc_iter].name); + + // Destroy all open shared memory regions + ASE_MSG("Unlinking Shared memory regions.... \n"); + // ase_destroy(); + + if (unlink(tstamp_filepath) == -1) { + ASE_MSG + ("$ASE_WORKDIR/.ase_ready could not be deleted, please delete manually... \n"); + } else { + ASE_MSG("Session code file removed\n"); + } + + // Final clean of IPC + final_ipc_cleanup(); + + // Close workspace log + if (fp_workspace_log != NULL) { + fclose(fp_workspace_log); + } +#ifdef ASE_DEBUG + if (fp_memaccess_log != NULL) { + fclose(fp_memaccess_log); + } + if (fp_pagetable_log != NULL) { + fclose(fp_pagetable_log); + } +#endif + + // Remove session files + ASE_MSG("Cleaning session files...\n"); + if (unlink(ase_ready_filepath) == -1) { + ASE_ERR + ("Session file %s could not be removed, please remove manually !!\n", + ASE_READY_FILENAME); + } + // Print location of log files + ASE_INFO("Simulation generated log files\n"); + ASE_INFO + (" Transactions file | $ASE_WORKDIR/ccip_transactions.tsv\n"); + ASE_INFO + (" Workspaces info | $ASE_WORKDIR/workspace_info.log\n"); + if (access(ccip_sniffer_file_statpath, F_OK) != -1) { + ASE_INFO + (" Protocol warning/errors | $ASE_WORKDIR/ccip_warning_and_errors.txt\n"); + } + ASE_INFO + (" ASE seed | $ASE_WORKDIR/ase_seed.txt\n"); + + // Display test count + ASE_INFO("\n"); + ASE_INFO("Tests run => %d\n", glbl_test_cmplt_cnt); + ASE_INFO("\n"); + + // Send a simulation kill command + ASE_INFO_2("Sending kill command...\n"); + usleep(1000); + + // Set scope + svSetScope(scope); + + // Free memories + free(cfg); + free(ase_ready_filepath); + ase_free_buffer((char *) incoming_mmio_pkt); + ase_free_buffer((char *) incoming_umsg_pkt); + // ase_free_buffer (ase_workdir_path); + + // Issue Simulation kill + simkill(); + + FUNC_CALL_EXIT; +} + + +/* + * ASE config parsing + * - Set default values for ASE configuration + * - See if a ase.cfg is available for overriding global values + * - If YES, parse and configure the cfg (ase_cfg_t) structure + */ +void ase_config_parse(char *filename) +{ + FUNC_CALL_ENTRY; + + FILE *fp = (FILE *) NULL; + char *line; + size_t len = 0; + char *parameter; + int value; + char *pch; + + + // Allocate space to store ASE config + cfg = (struct ase_cfg_t *) ase_malloc(sizeof(struct ase_cfg_t)); + + // Allocate memory to store a line + line = ase_malloc(sizeof(char) * 80); + + // Default values + cfg->ase_mode = ASE_MODE_DAEMON_NO_SIMKILL; + cfg->ase_timeout = 50000; + cfg->ase_num_tests = 1; + cfg->enable_reuse_seed = 0; + cfg->ase_seed = 9876; + cfg->enable_cl_view = 1; + cfg->usr_tps = DEFAULT_USR_CLK_TPS; + cfg->phys_memory_available_gb = 256; + + // Fclk Mhz + f_usrclk = DEFAULT_USR_CLK_MHZ; + + // Find ase.cfg OR not + if (access(filename, F_OK) != -1) { + // FILE exists, overwrite + fp = fopen(filename, "r"); + if (fp == NULL) { + ASE_ERR + ("%s supplied by +CONFIG could not be opened, IGNORED\n", + filename); + } else { + ASE_INFO_2("Reading %s configuration file \n", + filename); + // Parse file line by line + while (getline(&line, &len, fp) != -1) { + // Remove all invalid characters + remove_spaces(line); + remove_tabs(line); + remove_newline(line); + // Ignore strings begining with '#' OR NULL (compound NOR) + if ((line[0] != '#') && (line[0] != '\0')) { + parameter = strtok(line, "=\n"); + if (parameter != NULL) { + if (ase_strncmp + (parameter, "ASE_MODE", + 8) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + ase_mode + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "ASE_TIMEOUT", + 11) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + ase_timeout + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "ASE_NUM_TESTS", + 13) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + ase_num_tests + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "ENABLE_REUSE_SEED", + 17) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + enable_reuse_seed + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "ASE_SEED", + 8) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + ase_seed + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "ENABLE_CL_VIEW", + 14) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + cfg-> + enable_cl_view + = + atoi + (pch); + } + } else + if (ase_strncmp + (parameter, + "USR_CLK_MHZ", + 11) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + f_usrclk = + atof + (pch); + if (f_usrclk == 0.000000) { + ASE_ERR + ("User Clock Frequency cannot be 0.000 MHz\n"); + ASE_ERR + (" Reverting to %f MHz\n", + DEFAULT_USR_CLK_MHZ); + f_usrclk + = + DEFAULT_USR_CLK_MHZ; + cfg-> + usr_tps + = + DEFAULT_USR_CLK_TPS; + } else + if + (f_usrclk + == + DEFAULT_USR_CLK_MHZ) + { + cfg-> + usr_tps + = + DEFAULT_USR_CLK_TPS; + } else { + cfg-> + usr_tps + = + (int) + (1E+12 + / + (f_usrclk + * + pow + (1000, + 2))); +#ifdef ASE_DEBUG + ASE_DBG + ("usr_tps = %d\n", + cfg-> + usr_tps); +#endif + if (f_usrclk != DEFAULT_USR_CLK_MHZ) { + ASE_INFO_2 + ("User clock Frequency was modified from %f to %f MHz\n", + DEFAULT_USR_CLK_MHZ, + f_usrclk); + } + } + } + } else + if (ase_strncmp + (parameter, + "PHYS_MEMORY_AVAILABLE_GB", + 24) == 0) { + pch = + strtok(NULL, + ""); + if (pch != NULL) { + value = + atoi + (pch); + if (value < + 0) { + ASE_ERR + ("Physical memory size is negative in %s\n", + filename); + ASE_ERR + (" Reverting to default 256 GB\n"); + } else { + cfg-> + phys_memory_available_gb + = + value; + } + } + } else { + ASE_INFO_2 + ("In config file %s, Parameter type %s is unidentified \n", + filename, + parameter); + } + } + } + } + } + + /* + * ASE mode control + */ + switch (cfg->ase_mode) { + // Classic Server client mode + case ASE_MODE_DAEMON_NO_SIMKILL: + ASE_INFO_2 + ("ASE was started in Mode 1 (Server-Client without SIMKILL)\n"); + cfg->ase_timeout = 0; + cfg->ase_num_tests = 0; + break; + + // Server Client mode with SIMKILL + case ASE_MODE_DAEMON_SIMKILL: + ASE_INFO_2 + ("ASE was started in Mode 2 (Server-Client with SIMKILL)\n"); + cfg->ase_num_tests = 0; + break; + + // Long runtime mode (SW kills SIM) + case ASE_MODE_DAEMON_SW_SIMKILL: + ASE_INFO_2 + ("ASE was started in Mode 3 (Server-Client with Sw SIMKILL (long runs)\n"); + cfg->ase_timeout = 0; + cfg->ase_num_tests = 0; + break; + + // Regression mode (lets an SH file with + case ASE_MODE_REGRESSION: + ASE_INFO_2 + ("ASE was started in Mode 4 (Regression mode)\n"); + cfg->ase_timeout = 0; + break; + + // Illegal modes + default: + ASE_INFO_2 + ("ASE mode could not be identified, will revert to ASE_MODE = 1 (Server client w/o SIMKILL)\n"); + cfg->ase_mode = ASE_MODE_DAEMON_NO_SIMKILL; + cfg->ase_timeout = 0; + cfg->ase_num_tests = 0; + } + + // Close file + if (fp != NULL) { + fclose(fp); + } + + } else { + // FILE does not exist + ASE_INFO_2("%s not found, using default values\n", + filename); + } + + // Mode configuration + switch (cfg->ase_mode) { + case ASE_MODE_DAEMON_NO_SIMKILL: + ASE_INFO_2 + ("ASE Mode: Server-Client mode without SIMKILL\n"); + break; + case ASE_MODE_DAEMON_SIMKILL: + ASE_INFO_2("ASE Mode: Server-Client mode with SIMKILL\n"); + break; + case ASE_MODE_DAEMON_SW_SIMKILL: + ASE_INFO_2 + ("ASE Mode: Server-Client mode with SW SIMKILL (long runs)\n"); + break; + case ASE_MODE_REGRESSION: + ASE_INFO_2("ASE Mode: ASE Regression mode\n"); + break; + } + + // Inactivity + if (cfg->ase_mode == ASE_MODE_DAEMON_SIMKILL) + ASE_INFO_2 + ("Inactivity kill-switch ... ENABLED after %d clocks \n", + cfg->ase_timeout); + else + ASE_INFO_2("Inactivity kill-switch ... DISABLED \n"); + + // Reuse seed + if (cfg->enable_reuse_seed != 0) + ASE_INFO_2("Reuse simulation seed ... ENABLED \n"); + else { + ASE_INFO_2 + ("Reuse simulation seed ... DISABLED (will create one at $ASE_WORKDIR/ase_seed.txt) \n"); + cfg->ase_seed = generate_ase_seed(); + } + + // ASE will be run with this seed + ASE_INFO_2("ASE Seed ... %d \n", cfg->ase_seed); + + // CL view + if (cfg->enable_cl_view != 0) + ASE_INFO_2("ASE Transaction view ... ENABLED\n"); + else + ASE_INFO_2("ASE Transaction view ... DISABLED\n"); + + // User clock frequency + ASE_INFO_2 + ("User Clock Frequency ... %.6f MHz, T_uclk = %d ps \n", + f_usrclk, cfg->usr_tps); + if (f_usrclk != DEFAULT_USR_CLK_MHZ) { + ASE_INFO_2 + ("** NOTE **: User Clock Frequency was changed from default %f MHz !\n", + DEFAULT_USR_CLK_MHZ); + } + // GBs of physical memory available + ASE_INFO_2("Amount of physical memory ... %d GB\n", + cfg->phys_memory_available_gb); + + // Transfer data to hardware (for simulation only) + ase_config_dex(cfg); + + // free memory + free(line); + + FUNC_CALL_EXIT; +} diff --git a/ase/sw/randomness_control.c b/ase/sw/randomness_control.c new file mode 100644 index 000000000000..bc760e610c69 --- /dev/null +++ b/ase/sw/randomness_control.c @@ -0,0 +1,153 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** + +#include "ase_common.h" + + +/* + * Generate seed + */ +uint32_t generate_ase_seed(void) +{ + uint32_t seed; + + seed = (uint32_t) time(NULL); + seed = seed & 0x0000FFFF; + + return seed; +} + + +/* + * Write simulation seed to file + */ +void ase_write_seed(uint32_t seed) +{ + FILE *fp_seed = (FILE *) NULL; + + // Open seed file + fp_seed = fopen(ASE_SEED_FILE, "w"); + + // Use no more than 31-bits of seed + seed = seed & 0x0000FFFF; + + // Write to file + if (fp_seed == NULL) { + ASE_ERR("ASE Seed file could not be written\n"); + ase_error_report("fopen", errno, ASE_OS_FOPEN_ERR); + } else { + fprintf(fp_seed, "%u", seed); + fclose(fp_seed); + } +} + + +/* + * Readback simulation seed - used if ENABLE_REUSE_SEED is enabled + */ +uint32_t ase_read_seed(void) +{ + FILE *fp_seed = (FILE *) NULL; + uint32_t new_seed; + uint32_t readback_seed; + + // Check if file already exists (FALSE) + if (access(ASE_SEED_FILE, F_OK) == -1) { + ASE_ERR("ASE Seed file could not be read\n"); + ASE_ERR("Old seed unusable --- creating a new seed\n"); + + // Generate seed + new_seed = generate_ase_seed(); + + // Write seed to file + ase_write_seed(new_seed); + + // Return seed + return new_seed; + } + // If TRUE, read seed file + else { + // Open file (known to exist) + fp_seed = fopen(ASE_SEED_FILE, "r"); + if (fp_seed == NULL) { + ASE_ERR + ("ASE Seed file could not be read (NULL seed fileptr) \n"); + ASE_ERR + ("Old seed unusable --- creating a new seed\n"); + + // Generate seed + new_seed = generate_ase_seed(); + + // Write seed to file + ase_write_seed(new_seed); + + // Return seed + return new_seed; + } else { + // Read conents, post on log, close, return + if (fscanf(fp_seed, "%u", &readback_seed) <= 0) { + ASE_ERR("Seed readback failed !\n"); + } + // Close seed file + fclose(fp_seed); + + // Return seed + return readback_seed; + } + } +} + + +/* + * Generate 64-bit random number + */ +uint64_t ase_rand64(void) +{ + uint64_t random; + random = rand(); + random = (random << 32) | rand(); + return random; +} + +/* + * Shuffle an array of numbers + * USAGE: For setting up latency_scoreboard + */ +void shuffle_int_array(int *array, int num_items) +{ + int i, j; + int tmp; + + if (num_items > 1) { + for (i = 0; i < num_items - 1; i++) { + j = i + rand() / (RAND_MAX / (num_items - i) + 1); + tmp = array[j]; + array[j] = array[i]; + array[i] = tmp; + } + } +} diff --git a/ase/sw/tstamp_ops.c b/ase/sw/tstamp_ops.c new file mode 100644 index 000000000000..ccdbab5c8b0c --- /dev/null +++ b/ase/sw/tstamp_ops.c @@ -0,0 +1,189 @@ +// Copyright(c) 2014-2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// ************************************************************************** +/* + * Module Info: Timestamp based session control functions + * Language : System{Verilog} | C/C++ + * Owner : Rahul R Sharma + * rahul.r.sharma@intel.com + * Intel Corporation + */ + +#include "ase_common.h" + + +// ----------------------------------------------------------------------- +// Timestamp based isolation +// ----------------------------------------------------------------------- +#if defined(__i386__) +static __inline__ unsigned long long rdtsc(void) +{ + unsigned long long int x; + __asm__ volatile (".byte 0x0f, 0x31":"=A" (x)); + return x; +} +#elif defined(__x86_64__) +static __inline__ unsigned long long rdtsc(void) +{ + unsigned hi, lo; + __asm__ __volatile__("rdtsc":"=a"(lo), "=d"(hi)); + return ((unsigned long long) lo) | (((unsigned long long) hi) << + 32); +} +#else +#error "Host Architecture unidentified, timestamp wont work" +#endif + + +// ----------------------------------------------------------------------- +// Write timestamp +// ----------------------------------------------------------------------- +void put_timestamp(void) +{ + FUNC_CALL_ENTRY; + + FILE *fp = (FILE *) NULL; + char *tstamp_path; + unsigned long long rdtsc_out; + + tstamp_path = (char *) ase_malloc(ASE_FILEPATH_LEN); + + snprintf(tstamp_path, ASE_FILEPATH_LEN, "%s/%s", ase_workdir_path, + TSTAMP_FILENAME); + + fp = fopen(tstamp_path, "wb"); + if (fp == NULL) { +#ifdef SIM_SIDE + ase_error_report("fopen", errno, ASE_OS_FOPEN_ERR); + start_simkill_countdown(); +#else + perror("fopen"); + exit(1); +#endif + } else { + // rdtsc call + rdtsc_out = rdtsc(); + ASE_DBG(" rdtsc_out = %lld\n", rdtsc_out); + + // Write session code + fprintf(fp, "%lld\n", rdtsc_out); + + // Close file + fclose(fp); + } + + free(tstamp_path); + + FUNC_CALL_EXIT; +} + + +// ----------------------------------------------------------------------- +// Read timestamp +// ----------------------------------------------------------------------- +void get_timestamp(char *session_str) +{ + FUNC_CALL_ENTRY; + + FILE *fp = (FILE *) NULL; + + // Form session code path + snprintf(tstamp_filepath, ASE_FILEPATH_LEN, "%s/%s", + ase_workdir_path, TSTAMP_FILENAME); + + ASE_DBG("tstamp_filepath = %s\n", tstamp_filepath); + + if (session_str != NULL) { + // Check if file exists + if (access(tstamp_filepath, F_OK) != -1) { // File exists + fp = fopen(tstamp_filepath, "r"); + // fopen failed + if (fp == NULL) { + ase_error_report("fopen", errno, + ASE_OS_FOPEN_ERR); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } else { + // Read timestamp file + if (fgets(session_str, 20, fp) == NULL) { + ase_error_report("fgets", errno, + ASE_OS_MALLOC_ERR); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + // Close fp + fclose(fp); + } + + // Remove newline char + remove_newline(session_str); + } else { +#ifdef SIM_SIDE + ase_error_report("access", errno, + ASE_OS_FOPEN_ERR); + start_simkill_countdown(); +#else + perror("access"); + exit(1); +#endif + } + } else { + ASE_ERR + ("** ASE ERROR: Session ID was calculated as NULL **\n"); +#ifdef SIM_SIDE + start_simkill_countdown(); +#else + exit(1); +#endif + } + + FUNC_CALL_EXIT; +} + + +// ----------------------------------------------------------------------- +// Check for session file to be created +// Used by session_init() to wait until .ase_timestamp existance is confirm +// ----------------------------------------------------------------------- +void poll_for_session_id(void) +{ + // char tstamp_filepath[ASE_FILEPATH_LEN]; + snprintf(tstamp_filepath, ASE_FILEPATH_LEN, "%s/%s", + ase_workdir_path, TSTAMP_FILENAME); + + ASE_MSG("Waiting till session ID is created by ASE ... "); + + while (access(tstamp_filepath, F_OK) == -1) { + usleep(1000); + } + ASE_MSG("DONE\n"); +} diff --git a/cmake/config/config.h.in b/cmake/config/config.h.in new file mode 100644 index 000000000000..1ecea104b644 --- /dev/null +++ b/cmake/config/config.h.in @@ -0,0 +1,220 @@ +/* config.h.in */ + +/* 1234 = LIL_ENDIAN, 4231 = BIG_ENDIAN */ +#cmakedefine BYTEORDER @BYTEORDER@ + +/* Define to 1 if you have the bcopy function. */ +#cmakedefine HAVE_BCOPY 1 + +/* Define to 1 if you have the strlcat function. */ +#cmakedefine HAVE_STRLCAT 1 + +/* Define to 1 if you have the strlcpy function. */ +#cmakedefine HAVE_STRLCPY 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_CTYPE_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_DLFCN_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_ERRNO_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_FCNTL_H 1 + +/* Define to 1 if you have the `getpagesize' function. */ +#cmakedefine HAVE_GETPAGESIZE 1 + +/* Define to 1 if you have the `gettimeofday' function. */ +#cmakedefine HAVE_GETTIMEOFDAY 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `ltdl' library (-lltdl). */ +#cmakedefine HAVE_LIBLTDL 1 + +/* Define to 1 if you have the `pthread' library (-lpthread). */ +#cmakedefine HAVE_LIBPTHREAD 1 + +/* Define to 1 if you have the `rt' library (-lrt). */ +#cmakedefine HAVE_LIBRT 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_LTDL_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_MEMORY_H 1 + +/* Define to 1 if you have the `memset' function. */ +#cmakedefine HAVE_MEMSET 1 + +/* Define to 1 if you have a working `mmap' system call. */ +#cmakedefine HAVE_MMAP 1 + +/* Define to 1 if you have the `munmap' function. */ +#cmakedefine HAVE_MUNMAP 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_PTHREAD_H 1 + +/* Define to 1 if stdbool.h conforms to C99. */ +#cmakedefine HAVE_STDBOOL_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STDDEF_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STDLIB_H 1 + +/* Define to 1 if you have the `strchr' function. */ +#cmakedefine HAVE_STRCHR 1 + +/* Define to 1 if you have the `strerror' function. */ +#cmakedefine HAVE_STRERROR 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_STRING_H 1 + +/* Define to 1 if you have the `strncpy' function. */ +#cmakedefine HAVE_STRNCPY 1 + +/* Define to 1 if the system has the type `struct timespec'. */ +#cmakedefine HAVE_STRUCT_TIMESPEC 1 + +/* Define to 1 if the system has the type `struct timeval'. */ +#cmakedefine HAVE_STRUCT_TIMEVAL 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_IOCTL_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_MMAN_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_PARAM_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_RESOURCE_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_TIME_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_TIME_H 1 + +/* Define to 1 if the system has the type `uintptr_t'. */ +#cmakedefine HAVE_UINTPTR_T 1 + +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_UNISTD_H 1 + +/* Define to 1 if the system has the type `_Bool'. */ +#cmakedefine HAVE__BOOL 1 + +/* Define to 1 if your C compiler doesn't accept -c and -o together. */ +#cmakedefine NO_MINUS_C_MINUS_O 1 + +/* Name of package */ +#cmakedefine PACKAGE @PACKAGE@ + +/* Define to the address where bug reports for this package should be sent. */ +#cmakedefine PACKAGE_BUGREPORT @PACKAGE_BUGREPORT@ + +/* Define to the full name of this package. */ +#cmakedefine PACKAGE_NAME @PACKAGE_NAME@ + +/* Define to the full name and version of this package. */ +#cmakedefine PACKAGE_STRING @PACKAGE_STRING@ + +/* Define to the one symbol short name of this package. */ +#cmakedefine PACKAGE_TARNAME @PACKAGE_TARNAME@ + +/* Define to the home page for this package. */ +#cmakedefine PACKAGE_URL @PACKAGE_URL@ + +/* Define to the version of this package. */ +#cmakedefine PACKAGE_VERSION "@PACKAGE_VERSION@" + +/* Define to the version of this package. */ +#cmakedefine VERSION "@PACKAGE_VERSION@" + +/* Define to 1 if you have the ANSI C header files. */ +#cmakedefine STDC_HEADERS 1 + +/* Define for Solaris 2.5.1 so the uint32_t typedef from , + , or is not used. If the typedef were allowed, the + #define below would cause a syntax error. */ +#cmakedefine _UINT32_T + +/* Define for Solaris 2.5.1 so the uint64_t typedef from , + , or is not used. If the typedef were allowed, the + #define below would cause a syntax error. */ +#cmakedefine _UINT64_T + +/* Define for Solaris 2.5.1 so the uint8_t typedef from , + , or is not used. If the typedef were allowed, the + #define below would cause a syntax error. */ +#cmakedefine _UINT8_T + +/* Define to `__inline__' or `__inline' if that's what the C compiler + calls it, or to nothing if 'inline' is not supported under any name. */ +#ifndef __cplusplus +#cmakedefine inline +#endif + +/* Define to the type of a signed integer type of width exactly 16 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine int16_t + +/* Define to the type of a signed integer type of width exactly 32 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine int32_t + +/* Define to the type of a signed integer type of width exactly 64 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine int64_t + +/* Define to the type of a signed integer type of width exactly 8 bits if such + a type exists and the standard includes do not define it. */ +#cmakedefine int8_t + +/* Define to `long int' if does not define. */ +#cmakedefine off_t @OFF_T@ + +/* Define to `unsigned int' if does not define. */ +#cmakedefine size_t @SIZE_T@ + +/* Define to the type of an unsigned integer type of width exactly 16 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine uint16_t + +/* Define to the type of an unsigned integer type of width exactly 32 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine uint32_t + +/* Define to the type of an unsigned integer type of width exactly 64 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine uint64_t + +/* Define to the type of an unsigned integer type of width exactly 8 bits if + such a type exists and the standard includes do not define it. */ +#cmakedefine uint8_t + +/* Define to the type of an unsigned integer type wide enough to hold a + pointer, if such a type exists, and if the system does not define it. */ +#cmakedefine uintptr_t diff --git a/cmake/config/libopae-all.spec.in b/cmake/config/libopae-all.spec.in new file mode 100644 index 000000000000..2e232d8b980b --- /dev/null +++ b/cmake/config/libopae-all.spec.in @@ -0,0 +1,73 @@ +%{?!packager: %define packager @PACKAGE_PACKAGER_NAME@ <@PACKAGE_PACKAGER_EMAIL@>} + +@DEFINE_RPM_NAME@ + +%define module @MODULE_NAME@ +Name: @PACKAGE_NAME@ + +Version: @PACKAGE_VERSION@ +Release: @CPACK_PACKAGE_RELEASE@ +Summary: @PACKAGE_SUMMARY@ +Vendor: @PACKAGE_VENDOR@ +URL: @PACKAGE_URL@ +License: GPL-2.0+ +Group: unknown + +BuildArch: x86_64 +BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n) + +Requires: opae-devel = @PACKAGE_VERSION@ +Requires: opae-tools = @PACKAGE_VERSION@ +Requires: opae-ase = @PACKAGE_VERSION@ + +# Put the RPM in the current directory +%define _rpmdir . + +# Find the tarball in the current directory +%define _sourcedir %(echo $PWD) + +# Disable redundant stuff rpm distros include in the build process by +# default: +# Disable any prep shell actions. replace them with simply 'true' +%define __spec_prep_pre true +%define __spec_prep_post true +# Disable any build shell actions. replace them with simply 'true' +%define __spec_build_pre cd %{_builddir} +%define __spec_build_post true +# Disable any install shell actions. replace them with simply 'true' +%define __spec_install_pre cd %{_builddir} +%define __spec_install_post true +# Disable any clean shell actions. replace them with simply 'true' +%define __spec_clean_pre cd %{_builddir} +%define __spec_clean_post true + +%description +@PACKAGE_DESCRIPTION@ + +%global debug_package %{nil} + +%prep + +%build +# nothing to do + +%install +# nothing to do + +%clean +# nothing to do + +%files + +%pre +# nothing to do + +%post +# nothing to do + +%preun +# nothing to do + +%changelog +* %(date "+%a %b %d %Y") %packager %{version}-%{release} +- OPAE meta package @GIT_COMMIT_HASH@ diff --git a/cmake/config/run_coverage_test.sh.in b/cmake/config/run_coverage_test.sh.in new file mode 100755 index 000000000000..c9bcd6edc5db --- /dev/null +++ b/cmake/config/run_coverage_test.sh.in @@ -0,0 +1,33 @@ +#!/bin/bash +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +rm -rf coverage_${target_name} +mkdir -p coverage_${target_name} +${test_command} ${ARGV2} +find */**/${target_name}.dir -iname "*.gcda" | xargs -i cp {} ${CMAKE_BINARY_DIR}/coverage_${target_name} +find */**/${target_name}.dir -iname "*.gcno" | xargs -i cp {} ${CMAKE_BINARY_DIR}/coverage_${target_name} +echo "Finished running test." diff --git a/cmake/modules/FindRT.cmake b/cmake/modules/FindRT.cmake new file mode 100644 index 000000000000..00c4d3333a4c --- /dev/null +++ b/cmake/modules/FindRT.cmake @@ -0,0 +1,34 @@ +# - Try to find librt +# Once done, this will define +# +# librt_FOUND - system has librt +# librt_INCLUDE_DIRS - the librt include directories +# librt_LIBRARIES - link these to use librt + +# Use pkg-config to get hints about paths +execute_process(COMMAND pkg-config --cflags rt --silence-errors + COMMAND cut -d I -f 2 + OUTPUT_VARIABLE RT_PKG_CONFIG_INCLUDE_DIRS) +set(RT_PKG_CONFIG_INCLUDE_DIRS "${RT_PKG_CONFIG_INCLUDE_DIRS}" CACHE STRING "Compiler flags for RT library") + +# Include dir +find_path(librt_INCLUDE_DIRS + NAMES time.h + PATHS ${LIBRT_ROOT}/include + ${RT_PKG_CONFIG_INCLUDE_DIRS} + /usr/local/include + /usr/include + ${CMAKE_EXTRA_INCLUDES}) + +# The library itself +find_library(librt_LIBRARIES + NAMES rt + PATHS ${LIBRT_ROOT}/lib + /usr/local/lib + /usr/lib + /lib + ${CMAKE_EXTRA_LIBS}) + +if(librt_LIBRARIES AND librt_INCLUDE_DIRS) + set(librt_FOUND true) +endif(librt_LIBRARIES AND librt_INCLUDE_DIRS) diff --git a/cmake/modules/FindUUID.cmake b/cmake/modules/FindUUID.cmake new file mode 100644 index 000000000000..1764c306d95c --- /dev/null +++ b/cmake/modules/FindUUID.cmake @@ -0,0 +1,34 @@ +# - Try to find uuid +# Once done, this will define +# +# libuuid_FOUND - system has libuuid +# libuuid_INCLUDE_DIRS - the libuuid include directories +# libuuid_LIBRARIES - link these to use libuuid + +# Use pkg-config to get hints about paths +execute_process(COMMAND pkg-config --cflags uuid --silence-errors + COMMAND cut -d I -f 2 + OUTPUT_VARIABLE UUID_PKG_CONFIG_INCLUDE_DIRS) +set(UUID_PKG_CONFIG_INCLUDE_DIRS "${UUID_PKG_CONFIG_INCLUDE_DIRS}" CACHE STRING "Compiler flags for UUID library") + +# Include dir +find_path(libuuid_INCLUDE_DIRS + NAMES uuid/uuid.h + PATHS ${LIBUUID_ROOT}/include + ${UUID_PKG_CONFIG_INCLUDE_DIRS} + /usr/local/include + /usr/include + ${CMAKE_EXTRA_INCLUDES}) + +# The library itself +find_library(libuuid_LIBRARIES + NAMES uuid + PATHS ${LIBUUID_ROOT}/lib + /usr/local/lib + /usr/lib + /lib + ${CMAKE_EXTRA_LIBS}) + +if(libuuid_LIBRARIES AND libuuid_INCLUDE_DIRS) + set(libuuid_FOUND true) +endif(libuuid_LIBRARIES AND libuuid_INCLUDE_DIRS) diff --git a/cmake/modules/Findjson-c.cmake b/cmake/modules/Findjson-c.cmake new file mode 100644 index 000000000000..e2edfec39988 --- /dev/null +++ b/cmake/modules/Findjson-c.cmake @@ -0,0 +1,34 @@ +# - Try to find libjson-c +# Once done, this will define +# +# libjson-c_FOUND - system has libjson-c +# libjson-c_INCLUDE_DIRS - the libjson-c include directories +# libjson-c_LIBRARIES - link these to use libjson-c + +# Use pkg-config to get hints about paths +execute_process(COMMAND pkg-config --cflags json-c --silence-errors + COMMAND cut -d I -f 2 + OUTPUT_VARIABLE JSON-C_PKG_CONFIG_INCLUDE_DIRS) +set(JSON-C_PKG_CONFIG_INCLUDE_DIRS "${JSON-C_PKG_CONFIG_INCLUDE_DIRS}" CACHE STRING "Compiler flags for JSON-C library") + +# Include dir +find_path(libjson-c_INCLUDE_DIRS + NAMES json-c/json.h + PATHS ${LIBJSON-C_ROOT}/include + ${JSON-C_PKG_CONFIG_INCLUDE_DIRS} + /usr/local/include + /usr/include + ${CMAKE_EXTRA_INCLUDES}) + +# The library itself +find_library(libjson-c_LIBRARIES + NAMES json-c + PATHS ${LIBJSON-C_ROOT}/lib + /usr/local/lib + /usr/lib + /lib + ${CMAKE_EXTRA_LIBS}) + +if(libjson-c_LIBRARIES AND libjson-c_INCLUDE_DIRS) + set(libjson-c_FOUND true) +endif(libjson-c_LIBRARIES AND libjson-c_INCLUDE_DIRS) diff --git a/cmake/modules/compiler_config.cmake b/cmake/modules/compiler_config.cmake new file mode 100644 index 000000000000..790bbe38c7c6 --- /dev/null +++ b/cmake/modules/compiler_config.cmake @@ -0,0 +1,165 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +# Enable checking compiler flags +include(CheckCCompilerFlag) +include(CheckCXXCompilerFlag) + +# Export compile commands +set(CMAKE_EXPORT_COMPILE_COMMANDS 1) + +# Set the default build type to release with debug info +if (NOT DEFINED CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE RelWithDebInfo + CACHE STRING + "Choose the type of build, options are: None Debug Release RelWithDebInfo MinSizeRel Coverage.") +endif (NOT DEFINED CMAKE_BUILD_TYPE) + +############################################################################ +## GCC specific options #################################################### +############################################################################ + +if(CMAKE_COMPILER_IS_GNUCC) + # Default flags to compiler when build user-space programs. + # Should come before enabling language. + set(CMAKE_C_FLAGS_DEBUG "-g -O0 -Wall -Wextra" + CACHE STRING "Compiler flags for debug builds.") + set(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -Wall -Wextra" + CACHE STRING "Compiler flags for Release With Debug Info builds.") + set(CMAKE_C_FLAGS_RELEASE "-Wall" + CACHE STRING "Compiler flags for release builds.") + set(CMAKE_CXX_FLAGS_DEBUG "-g -O0 -Wall -Wextra" + CACHE STRING "C++ compiler flags for debug builds.") + set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -Wall -Wextra" + CACHE STRING "C++ compiler flags for Release with Debug Info builds.") + set(CMAKE_CXX_FLAGS_RELEASE "-Wall" + CACHE STRING "C++ compiler flags for release builds.") +endif(CMAKE_COMPILER_IS_GNUCC) + +# Check if support for C++ 11 is available +check_cxx_compiler_flag("-std=c++14" COMPILER_SUPPORTS_CXX14) +check_cxx_compiler_flag("-std=c++11" COMPILER_SUPPORTS_CXX11) +check_cxx_compiler_flag("-std=c++0x" COMPILER_SUPPORTS_CXX0X) +if(COMPILER_SUPPORTS_CXX14) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++14") + set(CMAKE_CXX_STANDARD 14) +elseif(COMPILER_SUPPORTS_CXX11) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11") + set(CMAKE_CXX_STANDARD 11) +elseif(COMPILER_SUPPORTS_CXX0X) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++0x") +endif() + +# Disable GCC warnings +check_cxx_compiler_flag("-Wno-format" + CXX_SUPPORTS_NO_FORMAT) +if (CXX_SUPPORTS_NO_FORMAT) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-format") +endif() + +check_cxx_compiler_flag("-Wno-write-strings" + CXX_SUPPORTS_NO_WRITE_STRINGS) +if (CXX_SUPPORTS_NO_WRITE_STRINGS) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-write-strings") +endif() + +check_cxx_compiler_flag("-Wno-deprecated-declarations" + CXX_SUPPORTS_NO_DEPRECATED_DECLARATIONS) +if (CXX_SUPPORTS_NO_DEPRECATED_DECLARATIONS) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-deprecated-declarations") +endif() + +check_cxx_compiler_flag("-Wno-unknown-pragmas" + CXX_SUPPORTS_NO_UNKNOWN_PRAGMAS) +if (CXX_SUPPORTS_NO_UNKNOWN_PRAGMAS) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-unknown-pragmas") +endif() + +check_cxx_compiler_flag("-Wno-strict-aliasing" + CXX_SUPPORTS_NO_STRICT_ALIASING) +if (CXX_SUPPORTS_NO_STRICT_ALIASING) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-strict-aliasing") +endif() + +check_cxx_compiler_flag("-Wno-nonnull" + CXX_SUPPORTS_NO_NONNULL_EXTENSION) +if (CXX_SUPPORTS_NO_NONNULL_EXTENSION) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-nonnull") +endif() + +# If building on a 32-bit system, make sure off_t can store offsets > 2GB +if(CMAKE_COMPILER_IS_GNUCC) + if(CMAKE_SIZEOF_VOID_P EQUAL 4) + add_definitions(-D_LARGEFILE_SOURCE) + add_definitions(-D_FILE_OFFSET_BITS=64) + endif() +endif(CMAKE_COMPILER_IS_GNUCC) + +############################################################################ +## Clang specific options ################################################## +############################################################################ + +# Disable Clang warnings +check_cxx_compiler_flag("-Wno-deprecated-register" + CXX_SUPPORTS_NO_DEPRECATED_REGISTER) +if (CXX_SUPPORTS_NO_DEPRECATED_REGISTER) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-deprecated-register") +endif() + +check_cxx_compiler_flag("-Wno-vla-extension" + CXX_SUPPORTS_NO_VLA_EXTENSION) +if (CXX_SUPPORTS_NO_VLA_EXTENSION) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-vla-extension") +endif() + +############################################################################ +## Defensive compilation for Release ####################################### +####################################################################### +if(CMAKE_BUILD_TYPE STREQUAL "Release") + ## C options + set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wformat -Wformat-security") + set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fPIC -O2 -D_FORTIFY_SOURCE=2") + if (GCC_VERSION VERSION_GREATER 4.9 OR GCC_VERSION VERSION_EQUAL 4.9) + set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fstack-protector-strong") + set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -z noexecstack -z relro -z now") + else() + set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fstack-protector-all") + endif() + + ## C++ options + set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wformat -Wformat-security") + set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fPIC -O2 -D_FORTIFY_SOURCE=2") + if (GCC_VERSION VERSION_GREATER 4.9 OR GCC_VERSION VERSION_EQUAL 4.9) + set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fstack-protector-strong") + set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -z noexecstack -z relro -z now") + else() + set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fstack-protector-all") + endif() + + set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -pie") + + set (CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -pie") +endif(CMAKE_BUILD_TYPE STREQUAL "Release") \ No newline at end of file diff --git a/cmake/modules/coverage.cmake b/cmake/modules/coverage.cmake new file mode 100644 index 000000000000..abb42f0df8cb --- /dev/null +++ b/cmake/modules/coverage.cmake @@ -0,0 +1,110 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +# Check prereqs +find_program(GCOV_EXECUTABLE gcov) +find_program(LCOV_EXECUTABLE lcov) +find_program(GENHTML_EXECUTABLE genhtml) + +if(NOT GCOV_EXECUTABLE) + message(FATAL_ERROR "gcov not found! Aborting...") +endif() + +set(GCOV_COMPILE_FLAGS "-g -O0 --coverage -fprofile-arcs -ftest-coverage") +set(GCOV_LINK_FLAGS "-lgcov") + +set(CMAKE_CXX_FLAGS_COVERAGE + ${GCOV_COMPILE_FLAGS} + CACHE STRING "Flags used by the C++ compiler during coverage builds." + FORCE) +set(CMAKE_C_FLAGS_COVERAGE + ${GCOV_COMPILE_FLAGS} + CACHE STRING "Flags used by the C compiler during coverage builds." + FORCE) +set(CMAKE_EXE_LINKER_FLAGS_COVERAGE + ${GCOV_LINK_FLAGS} + CACHE STRING "Flags used for linking binaries during coverage builds." + FORCE) +set(CMAKE_SHARED_LINKER_FLAGS_COVERAGE + ${GCOV_LINK_FLAGS} + CACHE STRING "Flags used by the shared libraries linker during coverage builds." + FORCE) +mark_as_advanced( + CMAKE_C_FLAGS_COVERAGE + CMAKE_CXX_FLAGS_COVERAGE + CMAKE_EXE_LINKER_FLAGS_COVERAGE + CMAKE_SHARED_LINKER_FLAGS_COVERAGE) + +# targetname The name of original target from which the current target depends on +# testrunner The name of the target which runs the tests. +# Optional third parameter is passed as arguments to testrunner +# Pass them in list form, e.g.: "-k;1" for -k 1 +function(set_target_for_coverage target_name testrunner) + + if(NOT LCOV_EXECUTABLE) + message(FATAL_ERROR "lcov not found! Aborting...") + endif() + + if(NOT GENHTML_EXECUTABLE) + message(FATAL_ERROR "genhtml not found! Aborting...") + endif() + + message("-- Setting ${target_name} for coverage run.") + set(outputfile ${target_name}) + set(coverage_info "${CMAKE_BINARY_DIR}/coverage_${target_name}/${outputfile}.info") + set(coverage_cleaned "${coverage_info}.cleaned") + set(coverage_runtest_script "coverage_${target_name}.sh") + + separate_arguments(test_command UNIX_COMMAND "${testrunner}") + configure_file(${CMAKE_SOURCE_DIR}/cmake/config/run_coverage_test.sh.in + ${CMAKE_BINARY_DIR}/${coverage_runtest_script}) + + # Setup target + set(name "coverage_${target_name}") + add_custom_target(${name} + + # Cleanup lcov + COMMAND ${LCOV_EXECUTABLE} --directory . --zerocounters + + # Wrap test on script, so coverage files generate even if tests return 1 + # CMake will stop if this step returns 1 + COMMAND chmod 755 ${coverage_runtest_script} + COMMAND ${CMAKE_BINARY_DIR}/${coverage_runtest_script} + + # Capturing lcov counters and generating report + COMMAND ${LCOV_EXECUTABLE} -t ${target_name} -o ${coverage_info} -c -d ${CMAKE_BINARY_DIR}/coverage_${target_name} + + # Clean coverage file + COMMAND ${LCOV_EXECUTABLE} --remove ${coverage_info} '/usr/**' 'tests/**' '*/**/*CMakefiles*' ${LCOV_REMOVE_EXTRA} --output-file ${coverage_cleaned} + COMMAND ${GENHTML_EXECUTABLE} --branch-coverage --function-coverage ${coverage_info} -o coverage_${target_name} ${coverage_cleaned} + COMMAND ${CMAKE_COMMAND} -E remove ${coverage_info} ${coverage_cleaned} + + # Add dependencies + DEPENDS ${target_name} + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + COMMENT "Run coverage tests.") + +endfunction() diff --git a/cmake/modules/doxygen.cmake b/cmake/modules/doxygen.cmake new file mode 100644 index 000000000000..a6514bd062ac --- /dev/null +++ b/cmake/modules/doxygen.cmake @@ -0,0 +1,86 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +find_package(Perl) +set(PACKAGE_VERSION "${CMAKE_VERSION_MAJOR}.${CMAKE_VERSION_MINOR}.${CMAKE_VERSION_PATCH}") +set(PACKAGE ${CMAKE_PROJECT}) +set(ABS_SRCDIR ${CMAKE_SOURCE_DIR}) +set(DOX_EXTRACT_ALL YES) +set(DOX_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/doc) +set(DOX_STRIP_FROM_PATH ${CMAKE_SOURCE_DIR}) +set(DOX_STRIP_FROM_INC_PATH ${FPGA_INCLUDE_DIR}) +set(DOX_GENERATETODOLIST NO) +set(DOX_GENERATETESTLIST YES) +set(DOX_GENERATEBUGLIST NO) +set(DOX_GENERATEDEPRECATEDLIST YES) +set(DOX_LAYOUT_FILE ${CMAKE_SOURCE_DIR}/doc/DoxygenLayout.xml ) +set(DOX_WARNINGS YES) +set(DOX_GENERATE_HTML YES) +set(DOX_GENERATE_LATEX YES) +set(DOX_USE_PDFLATEX YES) +set(DOX_GENERATE_RTF NO) +set(DOX_GENERATE_MAN YES) +set(DOX_GENERATE_XML YES) +set(DOX_GENERATE_TAGFILE ${CMAKE_BINARY_DIR}/doc/doxygen_sdk.tag) + +if(PERL_FOUND) + set(PERL ${PERL_EXECUTABLE}) +endif(PERL_FOUND) + +if(DOXYGEN_DOT_FOUND) + set(HAVE_DOT YES) +else(DOXYGEN_DOT_FOUND) + set(HAVE_DOT NO) +endif(DOXYGEN_DOT_FOUND) + +configure_file(${CMAKE_SOURCE_DIR}/doc/Doxyfile.in + ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile @ONLY) +add_custom_target(doc + ${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMENT "Generating API docs" VERBATIM + SOURCES ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile + ) +if(DOX_GENERATE_HTML) + file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/doc/html) + install(DIRECTORY ${CMAKE_BINARY_DIR}/doc/html DESTINATION doc/opae COMPONENT dochtml) +endif() +if(DOX_GENERATE_LATEX) + file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/doc/latex) + install(DIRECTORY ${CMAKE_BINARY_DIR}/doc/latex DESTINATION doc/opae COMPONENT doclatex) +endif() +if(DOX_GENERATE_RTF) + file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/doc/rtf) + install(DIRECTORY ${CMAKE_BINARY_DIR}/doc/rtf DESTINATION doc/opae COMPONENT docrtf) +endif() +if(DOX_GENERATE_MAN) + file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/doc/man) + install(DIRECTORY ${CMAKE_BINARY_DIR}/doc/man DESTINATION doc/opae COMPONENT docman) +endif() +if(DOX_GENERATE_XML) + file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/doc/xml) + install(DIRECTORY ${CMAKE_BINARY_DIR}/doc/xml DESTINATION doc/opae COMPONENT docxml) +endif() diff --git a/cmake/modules/fpga_functions.cmake b/cmake/modules/fpga_functions.cmake new file mode 100644 index 000000000000..956909ad9fd8 --- /dev/null +++ b/cmake/modules/fpga_functions.cmake @@ -0,0 +1,83 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +set(ASE_LIBRARIES "" CACHE INTERNAL "ase libraries") + +function(add_fpga_executable) + list(GET ARGV 0 target_name) + if (BUILD_LIBFPGA) + add_executable(${ARGV}) + target_link_libraries(${target_name} fpga) + endif(BUILD_LIBFPGA) + if (BUILD_ASE) + list(REMOVE_AT ARGV 0) + add_executable(${target_name}-ASE ${ARGV}) + endif(BUILD_ASE) +endfunction(add_fpga_executable) + +function(add_fpga_library) + list(GET ARGV 0 target_name) + if (BUILD_LIBFPGA) + add_library(${ARGV}) + target_link_libraries(${target_name} fpga) + endif(BUILD_LIBFPGA) + if (BUILD_ASE) + list(REMOVE_AT ARGV 0) + add_library(${target_name}-ASE ${ARGV}) + endif(BUILD_ASE) +endfunction(add_fpga_library) + +function(fpga_target_link_libraries) + list(GET ARGV 0 target_name) + list(REMOVE_AT ARGV 0) + list(LENGTH ARGV length) + list(FIND ARGV "FPGA_LIBS" fpga_libs_index) + set(fpga_libs "") + set(ase_libs "") + if (fpga_libs_index GREATER -1) + math(EXPR start "${fpga_libs_index}+1") + math(EXPR end "${length}-1") + foreach(idx RANGE ${start} ${end}) + list(GET ARGV ${idx} item) + list(APPEND fpga_libs ${item}) + list(APPEND ase_libs ${item}-ASE) + endforeach() + list(REMOVE_ITEM ARGV FPGA_LIBS ${fpga_libs}) + endif() + if (BUILD_LIBFPGA) + target_link_libraries(${target_name} ${ARGV} ${fpga_libs}) + endif(BUILD_LIBFPGA) + if (BUILD_ASE) + target_link_libraries(${target_name}-ASE ${ARGV} ${ase_libs}) + endif(BUILD_ASE) +endfunction(fpga_target_link_libraries) + +macro(set_install_rpath target_name) + set_target_properties(${target_name} PROPERTIES INSTALL_RPATH "\$ORIGIN/../lib" + INSTALL_RPATH_USE_LINK_PATH TRUE + SKIP_BUILD_RPATH FALSE + BUILD_WITH_INSTALL_RPATH FALSE) +endmacro(set_install_rpath target_name) diff --git a/cmake/modules/libraries_config.cmake b/cmake/modules/libraries_config.cmake new file mode 100644 index 000000000000..ab318b315ffc --- /dev/null +++ b/cmake/modules/libraries_config.cmake @@ -0,0 +1,81 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +include(CheckCCompilerFlag) +include(CheckCXXCompilerFlag) +include(CheckCSourceCompiles) +include(CheckTypeSize) +include(CheckIncludeFile) +include(CheckFunctionExists) +include(CheckSymbolExists) +include(CheckLibraryExists) + +set(PROJECT_LIBS "${CMAKE_BINARY_DIR}/libs") + +# Threads library: CMAKE_THREAD_LIBS_INIT CMAKE_USE_PTHREADS_INIT CMAKE_USE_WIN32_THREADS_INIT +find_package(Threads) +if (CMAKE_USE_PTHREADS_INIT) + set(HAVE_PTHREAD_H 1) + set(CMAKE_THREAD_PREFER_PTHREAD ON) + list(APPEND PROJECT_LIBS ${CMAKE_THREAD_LIBS_INIT}) +endif() + +check_library_exists(pthread pthread_create "" HAVE_LIBPTHREAD) +if (HAVE_LIBPTHREAD) + check_library_exists(pthread pthread_getspecific "" HAVE_PTHREAD_GETSPECIFIC) + check_library_exists(pthread pthread_rwlock_init "" HAVE_PTHREAD_RWLOCK_INIT) + check_library_exists(pthread pthread_mutex_lock "" HAVE_PTHREAD_MUTEX_LOCK) +else() + check_library_exists(c pthread_create "" PTHREAD_IN_LIBC) + if (PTHREAD_IN_LIBC) + check_library_exists(c pthread_getspecific "" HAVE_PTHREAD_GETSPECIFIC) + check_library_exists(c pthread_rwlock_init "" HAVE_PTHREAD_RWLOCK_INIT) + check_library_exists(c pthread_mutex_lock "" HAVE_PTHREAD_MUTEX_LOCK) + endif() +endif(HAVE_LIBPTHREAD) + +# dlopen support: CMAKE_DL_LIBS (built-in cmake variable) +check_library_exists(dl dlopen "" HAVE_LIBDL) +if (HAVE_LIBDL) + list(APPEND PROJECT_LIBS ${CMAKE_DL_LIBS}) +endif() + +# rt check +find_package(RT) +check_library_exists(rt clock_gettime "" HAVE_LIBRT) + +# uuid check +find_package(UUID) + +#json-c check +find_package(json-c) + +# ncurses check: CURSES_FOUND CURSES_INCLUDE_DIRS CURSES_LIBRARIES +find_package(Curses) +if (CURSES_FOUND) + include_directories(${CURSES_INCLUDE_DIRS}) + list(APPEND PROJECT_LIBS ${CURSES_LIBRARIES}) +endif() diff --git a/common/include/opae/access.h b/common/include/opae/access.h new file mode 100644 index 000000000000..b28e14daa37c --- /dev/null +++ b/common/include/opae/access.h @@ -0,0 +1,104 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file access.h + * @brief Functions to acquire, release, and reset OPAE FPGA resources + */ + +#ifndef __FPGA_ACCESS_H__ +#define __FPGA_ACCESS_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Open an FPGA object + * + * Acquires ownership of the FPGA resource referred to by 'token'. + * + * Most often this will be used to open an accelerator object to directly interact + * with an accelerator function, or to open an FPGA object to perform + * management functions. + * + * @param[in] token Pointer to token identifying resource to acquire + * ownership of + * @param[out] handle Pointer to preallocated memory to place a handle in. + * This handle will be used in subsequent API calls. + * @param[in] flags One of the following flags: + * * FPGA_OPEN_SHARED allows the resource to be opened + * multiple times (not supported in ASE) + * @returns FPGA_OK on success. FPGA_NOT_FOUND if the resource for + * 'token' could not be found. FPGA_INVALID_PARAM if + * 'token' does not refer to a resource that can be + * opened, or if either argument is NULL or invalid. + * FPGA_EXCEPTION if an internal exception occurred while + * creating the handle. FPGA_NO_DRIVER if the driver is + * not loaded. FPGA_BUSY if trying to open a resource that + * has already been opened in exclusive mode. + * FPGA_NO_ACCESS if the current process' privileges are + * not sufficient to open the resource. + */ +fpga_result fpgaOpen(fpga_token token, fpga_handle *handle, + int flags); + +/** + * Close a previously opened FPGA object + * + * Relinquishes ownership of a previously fpgaOpen()ed resource. This enables + * others to acquire ownership if the resource was opened exclusively. + * Also deallocates / unmaps MMIO and UMsg memory areas. + * + * @param[in] handle Handle to previously opened FPGA object + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does + * not refer to an acquired resource, or if handle is NULL. + * FPGA_EXCEPTION if an internal error occurred while + * accessing the handle. + */ +fpga_result fpgaClose(fpga_handle handle); + +/** + * Reset an FPGA object + * + * Performs an accelerator reset. + * + * @param[in] handle Handle to previously opened FPGA object + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does + * not refer to an acquired resource or to a resoure that + * cannot be reset. FPGA_EXCEPTION if an internal error + * occurred while trying to access the handle or resetting + * the resource. + */ +fpga_result fpgaReset(fpga_handle handle); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_ACCESS_H__ diff --git a/common/include/opae/buffer.h b/common/include/opae/buffer.h new file mode 100644 index 000000000000..22b3fbc75bc9 --- /dev/null +++ b/common/include/opae/buffer.h @@ -0,0 +1,136 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file buffer.h + * @brief Functions for allocating and sharing system memory with an FPGA + * accelerator + * + * To share memory between a software application and an FPGA accelerator, + * these functions set up system components (e.g. an IOMMU) to allow + * accelerator access to a provided memory region. + * + * There are a number of restrictions on what memory can be shared, depending + * on platform capabilities. Usually, FPGA accelerators to not have access to + * virtual address mappings of the CPU, so they can only access physical + * addresses. To support this, the OPAE C library on Linux uses hugepages to + * allocate large, contiguous pages of physical memory that can be shared with + * an accalerator. It also supports sharing memory that has already been + * allocated by an application, as long as that memory satisfies the + * requirements of being physically contigous and page-aligned. + */ + +#ifndef __FPGA_BUFFER_H__ +#define __FPGA_BUFFER_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Prepare a shared memory buffer + * + * Prepares a memory buffer for shared access between an accelerator and the calling + * process. This may either include allocation of physcial memory, or + * preparation of already allocated memory for sharing. The latter case is + * indicated by supplying the FPGA_BUF_PREALLOCATED flag. + * + * This function will ask the driver to pin the indicated memory (make it + * non-swappable), and program the IOMMU to allow access from the accelerator. If the + * buffer was not pre-allocated (flag FPGA_BUF_PREALLOCATED), the function + * will also allocate physical memory of the requested size and map the + * memory into the caller's process' virtual address space. It returns in + * 'wsid' an fpga_buffer object that can be used to program address registers + * in the accelerator for shared access to the memory. + * + * When using FPGA_BUF_PREALLOCATED, the input len must be a non-zero multiple + * of the page size, else the function returns FPGA_INVALID_PARAM. When not + * using FPGA_BUF_PREALLOCATED, the input len is rounded up to the nearest + * multiple of page size. + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] len Length of the buffer to allocate/prepare in bytes + * @param[inout] buf_addr Virtual address of buffer. Contents may be NULL (OS + * will choose mapping) or non-NULL (OS will take + * contents as a hint for the virtual address). + * @param[out] wsid Handle to the allocated/prepared buffer to be used + * with other functions + * @param[in] flags Flags. FPGA_BUF_PREALLOCATED indicates that memory + * pointed at in '*buf_addr' is already allocated an + * mapped into virtual memory. + * @returns FPGA_OK on success. FPGA_NO_MEMORY if the requested memory could + * not be allocated. FPGA_INVALID_PARAM if invalid parameters were provided, or + * if the parameter combination is not valid. FPGA_EXCEPTION if an internal + * exception occurred while trying to access the handle. + */ +fpga_result fpgaPrepareBuffer(fpga_handle handle, + uint64_t len, + void **buf_addr, uint64_t *wsid, int flags); + +/** + * Release a shared memory buffer + * + * Releases a previously prepared shared buffer. If the buffer was allocated + * using fpgaPrepareBuffer (FPGA_BUF_PREALLOCATED was not specified), this call + * will deallocate/free that memory. Otherwise, it will only be returned to + * it's previous state (pinned/unpinned, cached/non-cached). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] wsid Handle to the allocated/prepared buffer + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were + * provided, or if the parameter combination is not valid. FPGA_EXCEPTION if an + * internal exception occurred while trying to access the handle. + */ +fpga_result fpgaReleaseBuffer(fpga_handle handle, uint64_t wsid); + +/** + * Retrieve base IO address for buffer + * + * This function is used to acquire the physical base address (on some platforms + * called IO Virtual Address or IOVA) for a shared buffer identified by wsid. + * + * @note This function will disappear once the APIs for secure sharing of + * buffer addresses is implemented. + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] wsid Buffer handle / workspace ID referring to the buffer for + * which the IO address is requested + * @param[out] ioaddr Pointer to memory where the IO address will be returned + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if invalid parameters were + * provided, or if the parameter combination is not valid. FPGA_EXCEPTION if an + * internal exception occurred while trying to access the handle. + * FPGA_NOT_FOUND if `wsid` does not refer to a previously shared buffer. + */ +fpga_result fpgaGetIOAddress(fpga_handle handle, uint64_t wsid, + uint64_t *ioaddr); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_BUFFER_H__ diff --git a/common/include/opae/enum.h b/common/include/opae/enum.h new file mode 100644 index 000000000000..e55224cb297d --- /dev/null +++ b/common/include/opae/enum.h @@ -0,0 +1,133 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file enum.h + * @brief APIs for resource enumeration and managing tokens + * + * These APIs are the first step for any application using OPAE to discover + * resources that are present on the system. They allow selective enumeration + * (i.e. getting a list of resources that match a given list of criteria) and + * methods to manage the lifecycle of tokens generated by fpgaEnumerate(). + */ + +#ifndef __FPGA_ENUM_H__ +#define __FPGA_ENUM_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Enumerate FPGA resources present in the system + * + * This call allows the user to query the system for FPGA resources that match + * a certain set of criteria, e.g. all accelerators that are assigned to a host + * interface and available, all FPGAs of a specific type, etc. + * + * fpgaEnumerate() will create a number of `fpga_token`s to represent the + * matching resources and populate the array `tokens` with these tokens. The + * `max_tokens` argument can be used to limit the number of tokens + * allocated/returned by fpgaEnumerate(); i.e., the number of tokens in the + * returned `tokens` array will be either `max_tokens` or `num_matches` (the + * number of resources matching the filter), whichever is smaller. Use + * fpgaDestroyToken() to destroy tokens that are no longer needed. + * + * To query the number of matches for a particular set of filters (e.g. to + * allocate a `tokens` array of the appropriate size), call fpgaEnumerate() + * with the parameter `tokens` set to NULL; this will only return the number of + * matches in `num_matches`. + * + * @note fpgaEnumerate() will allocate memory for the created tokens returned + * in `tokens`. It is the responsibility of the using application to free this + * memory after use by calling fpgaDestroyToken() for each of the returned + * tokens. + * + * @param[in] filters Array of `fpga_properties` objects describing the + * properties of the objects that should be returned. A + * resource is considered matching if its properties + * match any one of the supplied filters. Passing NULL + * will match all FPGA resources present in the system. + * @param[in] num_filters Number of entries in the `filters` array. + * @param[out] tokens Pointer to an array of fpga_token variables to be + * populated. If NULL is supplied, fpgaEnumerate() will + * not create any tokens, but it will return the + * number of possible matches in `num_match`. + * @param[in] max_tokens Maximum number of tokens that fpgaEnumerate() shall + * return (length of `tokens` array). There may be more + * or fewer matches than this number; `num_matches` is + * set to the number of actual matches. + * @param[out] num_matches Number of resources matching the `filter` criteria. + * This number can be higher than the number of tokens + * returned in the `tokens` array (depending on the + * value of `max_tokens`). + * @returns FPGA_OK on success. + * FPGA_INVALID_PARAM if invalid pointers or objects + * are passed into the function. + * FPGA_NO_DRIVER if OPAE can't find the respective + * enumeration data structures usually provided by the + * driver. + * FPGA_NO_MEMORY if there was not enough memory to + * create tokens. + */ +fpga_result fpgaEnumerate(const fpga_properties *filters, + uint32_t num_filters, fpga_token *tokens, + uint32_t max_tokens, uint32_t *num_matches); + +/** + * Clone a fpga_token object + * + * Creates a copy of an fpga_token object. + * + * @note This call creates a new token object and allocates memory for it. It + * is the responsibility of the using application to free this memory after use + * by calling fpgaDestroyToken() for the cloned token. + * + * @param[in] src fpga_token object to copy + * @param[out] dst New fpga_token object cloned from 'src' + * @returns FPGA_OK on success + */ +fpga_result fpgaCloneToken(fpga_token src, fpga_token *dst); + +/** + * Destroy a Token + * + * This function destroys a token created by fpgaEnumerate() and frees the + * associated memory. + * + * @param[in] token fpga_token to destroy + * @returns FPGA_OK on success + */ +fpga_result fpgaDestroyToken(fpga_token *token); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_ENUM_H__ + diff --git a/common/include/opae/event.h b/common/include/opae/event.h new file mode 100644 index 000000000000..68be27ef86fc --- /dev/null +++ b/common/include/opae/event.h @@ -0,0 +1,137 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file event.h + * @brief Functions for registering events and managing the lifecycle for + * `fpga_event_handle`s. + * + * OPAE provides an interface to asynchronous events that can be generated by + * different FPGA resources. The event API provides functions to register for + * these events; associated with every event a process has registered for is an + * fpga_event_handle, which encapsulates the OS-specific data structure for + * event objects. On Linux, an fpga_event_handle can be used as a file + * descriptor and passed to select(), poll(), epoll() and similar functions to + * wait for asynchronous events. + */ + +#ifndef __FPGA_EVENT_H__ +#define __FPGA_EVENT_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize an event_handle + * + * Platform independent way to initialize an event_handle used for + * notifications from the driver to application. For Linux, this function + * creates an eventfd and returns the eventfd file descriptor in + * `*event_handle`. + * + * @param[out] event_handle Pointer to event handle variable. + * + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `event_handle` is NULL. + * FPGA_NOT_SUPPORTED if platform does not support events. + */ +fpga_result fpgaCreateEventHandle(fpga_event_handle *event_handle); + +/** + * Destroy an event_handle + * + * Destroy handle and free resources. On Linux this corresponds + * to closing the file descriptor pointed to by handle + * + * @param[in] event_handle Pointer to handle to be destroyed + * + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `event_handle` is NULL. + */ +fpga_result fpgaDestroyEventHandle(fpga_event_handle *event_handle); + +/** + * Register an FPGA event + * + * This function tells the driver that the caller is interested in notification + * for the event specified by the type and flags pair. + * + * The event_handle points to an OS specific mechanism for event notification. + * An event_handle is associated with only a single event. + * + * @todo define if calling fpgaRegisterEvent multiple times with the + * same event_handle is an error condition or if it is silently ignored. + * + * @note This function is currently not supported. + * + * @param[in] handle Handle to previously opened FPGA resource. + * @param[in] event_type Type of event + * @param[in] event_handle Handle to previously opened resource for event + * notification. + * @param[in] flags Optional argument for specifying additional + * information about event. For example irq number + * for interrupt events. + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does not refer to + * a resource supporting the requested event, or if event_handle is not valid. + * FPGA_EXCEPTION if an internal exception occurred while accessing the handle + * or the event_handle. On Linux: FPGA_NO_DAEMON if the driver does not support + * the requested event and there is no FPGA Daemon (fpgad) running to proxy it. + */ +fpga_result fpgaRegisterEvent(fpga_handle handle, + fpga_event_type event_type, + fpga_event_handle event_handle, + uint32_t flags); + +/** + * Unregister an FPGA event + * + * This function tells the driver that the caller is no longer interested in + * notification for the event associated with the event_handle + * + * The event_handle points to an OS specific mechanism for event notification. + * An event_handle is associated with only a single event. + * + * @todo define if calling fpgaUnregisterEvent multiple times with the + * same event_handle is an error condition or if it is silently ignored. + * + * @note This function is currently not supported. + * + * @param[in] handle Handle to previously opened FPGA resource. + * @param[in] event_type Type of previously registered event. + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if handle does + * not refer to a resource supporting the requested event, + * or if event_handle is not valid. FPGA_EXCEPTION if an + * internal error occurred accessing the handle or the + * event_handle. + */ +fpga_result fpgaUnregisterEvent(fpga_handle handle, fpga_event_type event_type); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_EVENT_H__ diff --git a/common/include/opae/fpga.h b/common/include/opae/fpga.h new file mode 100644 index 000000000000..9f95a3010bc4 --- /dev/null +++ b/common/include/opae/fpga.h @@ -0,0 +1,53 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * \file fpga.h + * \brief FPGA API + * + * This conveniently includes all APIs that a part of the OPAE release (base and + * extensions). + */ + +#ifndef __FPGA_FPGA_H__ +#define __FPGA_FPGA_H__ + +#define FPGA_API_VERSION_MAJOR 0 +#define FPGA_API_VERSION_MINOR 1 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // __FPGA_FPGA_H__ + diff --git a/common/include/opae/manage.h b/common/include/opae/manage.h new file mode 100644 index 000000000000..fe5640d7d347 --- /dev/null +++ b/common/include/opae/manage.h @@ -0,0 +1,139 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file manage.h + * @brief Functions for managing FPGA configurations + * + * FPGA accelerators can be reprogrammed at run time by providing new partial + * bitstreams ("green bitstreams"). This file defines API functions for + * programming green bitstreams as well as for assigning accelerators to host + * interfaces for more complex deployment setups, such as virtualized systems. + */ + +#ifndef __FPGA_MANAGE_H__ +#define __FPGA_MANAGE_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* Assign Port to a host interface. +* +* This function assign Port to a host interface for subsequent use. Only +* Port that have been assigned to a host interface can be opened by +* fpgaOpen(). +* +* @param[in] fpga Handle to an FPGA object previously opened that +* both the host interface and the slot belong to +* @param[in] interface_num Host interface number +* @param[in] slot_num Slot number +* @param[in] flags Flags (to be defined) +* @returns FPGA_OK on success +* FPGA_INVALID_PARAM if input parameter combination +* is not valid. +* FPGA_EXCEPTION if an exception occcurred accessing +* the `fpga` handle. +* FPGA_NOT_SUPPORTED if driver does not support +* assignment. +*/ +fpga_result fpgaAssignPortToInterface(fpga_handle fpga, + uint32_t interface_num, + uint32_t slot_num, + int flags); + +/** + * Assign an accelerator to a host interface + * + * This function assigns an accelerator to a host interface for subsequent use. Only + * accelerators that have been assigned to a host interface can be opened by + * fpgaOpen(). + * + * @note This function is currently not supported. + * + * @param[in] fpga Handle to an FPGA object previously opened that + * both the host interface and the accelerator belong to + * @param[in] accelerator accelerator to assign + * @param[in] host_interface Host interface to assign accelerator to + * @param[in] flags Flags (to be defined) + * @returns FPGA_OK on success + */ +fpga_result fpgaAssignToInterface(fpga_handle fpga, + fpga_token accelerator, + uint32_t host_interface, + int flags); + +/** + * Unassign a previously assigned accelerator + * + * This function removes the assignment of an accelerator to an host interface (e.g. to + * be later assigned to a different host interface). As a consequence, the accelerator + * referred to by token 'accelerator' will be reset during the course of this function. + * + * @note This function is currently not supported. + * + * @param[in] fpga Handle to an FPGA object previously opened that + * both the host interface and the accelerator belong to + * @param[in] accelerator accelerator to unassign/release + * @returns FPGA_OK on success + */ +fpga_result fpgaReleaseFromInterface(fpga_handle fpga, + fpga_token accelerator); + +/** + * Reconfigure a slot + * + * Sends a green bitstream file to an FPGA to reconfigure a specific slot. This + * call, if successful, will overwrite the currently programmed AFU in that + * slot with the AFU in the provided bitstream. + * + * As part of the reconfiguration flow, all accelerators associated with this slot will + * be unassigned and reset. + * + * @param[in] fpga Handle to an FPGA object previously opened + * @param[in] slot Token identifying the slot to reconfigure + * @param[in] bitstream Pointer to memory holding the bitstream + * @param[in] bitstream_len Length of the bitstream in bytes + * @param[in] flags Flags (to be defined) + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if the provided parameters + * are not valid. FPGA_EXCEPTION if an internal error occurred accessing the + * handle or while sending the bitstream data to the driver. FPGA_RECONF_ERROR + * on errors reported by the driver (such as CRC or protocol errors). + */ +fpga_result fpgaReconfigureSlot(fpga_handle fpga, + uint32_t slot, + const uint8_t *bitstream, + size_t bitstream_len, int flags); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_MANAGE_H__ + diff --git a/common/include/opae/mmio.h b/common/include/opae/mmio.h new file mode 100644 index 000000000000..1d071cfd5e0b --- /dev/null +++ b/common/include/opae/mmio.h @@ -0,0 +1,198 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file mmio.h + * @brief Functions for mapping and accessing MMIO space + * + * Most FPGA accelerators provide access to control registers through + * memory-mappable address spaces, commonly referred to as "MMIO spaces". This + * file provides functions to map, unmap, read, and write MMIO spaces. + * + * Note that an accelerator may have multiple MMIO spaces, denoted by the + * `mmio_num` argument of the APIs below. The meaning and properties of each + * MMIO space are up to the accelerator designer. + */ + +#ifndef __FPGA_MMIO_H__ +#define __FPGA_MMIO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Write 64 bit value to MMIO space + * + * This function will write to MMIO space of the target object at a specified + * offset. + * + * In order to access a resource's MMIO space using this function, it has to be + * mapped to the application's address space using fpgaMapMMIO(). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] mmio_num Number of MMIO space to access + * @param[in] offset Byte offset into MMIO space + * @param[in] value Value to write (64 bit) + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. FPGA_NOT_FOUND if the MMIO space + * `mmio_num` was not mapped using fpgaMapMMIO() before calling this function. + */ +fpga_result fpgaWriteMMIO64(fpga_handle handle, + uint32_t mmio_num, uint64_t offset, + uint64_t value); + +/** + * Read 64 bit value from MMIO space + * + * This function will read from MMIO space of the target object at a specified + * offset. + * + * In order to access a resource's MMIO space using this function, it has to be + * mapped to the application's address space using fpgaMapMMIO(). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] mmio_num Number of MMIO space to access + * @param[in] offset Byte offset into MMIO space + * @param[out] value Pointer to memory where read value is returned (64 bit) + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. FPGA_NOT_FOUND if the MMIO space + * `mmio_num` was not mapped using fpgaMapMMIO() before calling this function. + */ +fpga_result fpgaReadMMIO64(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, uint64_t *value); + +/** + * Write 32 bit value to MMIO space + * + * This function will write to MMIO space of the target object at a specified + * offset. + * + * In order to access a resource's MMIO space using this function, it has to be + * mapped to the application's address space using fpgaMapMMIO(). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] mmio_num Number of MMIO space to access + * @param[in] offset Byte offset into MMIO space + * @param[in] value Value to write (32 bit) + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. FPGA_NOT_FOUND if the MMIO space + * `mmio_num` was not mapped using fpgaMapMMIO() before calling this function. + */ +fpga_result fpgaWriteMMIO32(fpga_handle handle, + uint32_t mmio_num, uint64_t offset, + uint32_t value); + +/** + * Read 32 bit value from MMIO space + * + * This function will read from MMIO space of the target object at a specified + * offset. + * + * In order to access a resource's MMIO space using this function, it has to be + * mapped to the application's address space using fpgaMapMMIO(). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] mmio_num Number of MMIO space to access + * @param[in] offset Byte offset into MMIO space + * @param[out] value Pointer to memory where read value is returned (32 bit) + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. FPGA_NOT_FOUND if the MMIO space + * `mmio_num` was not mapped using fpgaMapMMIO() before calling this function. + */ +fpga_result fpgaReadMMIO32(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, uint32_t *value); + +/** + * Map MMIO space + * + * This function will return a pointer to the specified MMIO space of the + * target object in process virtual memory. Some MMIO spaces may be restricted + * to privileged processes, depending on the used handle and type. + * + * After mapping the respective MMIO space, you can access it either through + * direct pointer operations (observing supported access sizes and alignments + * of the target platform and accelerator), or by using fpgaReadMMIO32(), + * fpgaWriteMMIO32(), fpgeReadMMIO64(), and fpgaWriteMMIO64(). + * + * @note This call only supports returning an actual mmio_ptr for hardware + * targets, not for ASE simulation. Use fpgaReadMMIO32(), fpgaWriteMMIO32(), + * fpgeReadMMIO64(), and fpgaWriteMMIO64() if you need ASE simulation + * capabilities. You will still need to call fpgaMapMMIO() before using these + * functions, though. + * + * If the caller passes in NULL for mmio_ptr, no virtual address will be + * returned. This implies that all accesses will be performed through + * fpgaReadMMIO32(), fpgaWriteMMIO32(), fpgeReadMMIO64(), and + * fpgaWriteMMIO64(). This is the only supported case for ASE. + * + * The number of available MMIO spaces can be retrieved through the num_mmio + * property (fpgaPropertyGetNumMMIO()). + * + * @param[in] handle Handle to previously opened resource + * @param[in] mmio_num Number of MMIO space to access + * @param[out] mmio_ptr Pointer to memory where a pointer to the MMIO space + * will be returned. May be NULL, in which case no pointer + * is returned. + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. FPGA_NO_ACCESS if the process' + * permissions are not sufficient to map the requested MMIO space. + */ +fpga_result fpgaMapMMIO(fpga_handle handle, + uint32_t mmio_num, uint64_t **mmio_ptr); + +/** + * Unmap MMIO space + * + * This function will unmap a previously mapped MMIO space of the target opject, + * rendering any pointers to it invalid. + * + * @note This call is only supported by hardware targets, not by ASE + * simulation. + * + * @param[in] handle Handle to previously opened resource + * @param[in] mmio_num Number of MMIO space to access + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if any of the supplied + * parameters is invalid. FPGA_EXCEPTION if an internal exception occurred + * while trying to access the handle. + */ +fpga_result fpgaUnmapMMIO(fpga_handle handle, + uint32_t mmio_num); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_MMIO_H__ diff --git a/common/include/opae/properties.h b/common/include/opae/properties.h new file mode 100644 index 000000000000..9bd683c583c8 --- /dev/null +++ b/common/include/opae/properties.h @@ -0,0 +1,645 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file properties.h + * @brief Functions for examining and manipulating `fpga_properties` objects + * + * In OPAE, `fpga_properties` objects are used both for obtaining information + * about resources and for selectively enumerating resources based on their + * properties. This file provides accessor functions (get/set) to allow reading + * and writing individual items of an `fpga_properties` object. Generally, not + * all object types supported by OPAE carry all properties. If you call a + * property accessor method on a `fpga_properties` object that does not support + * this particular property, it will return FPGA_INVALID_PARAM. + * + * # Accessor Return Values + * In addition to the return values specified in the documentation below, all + * accessor functions return FPGA_OK on success, FPGA_INVALID_PARAM if you pass + * NULL or invalid parameters (i.e. non-initialized properties objects), + * FPGA_EXCEPTION if an internal exception occurred trying to access the + * properties object, FPGA_NOT_FOUND if the requested property is not part of + * the supplied properties object. + */ + +#ifndef __FPGA_PROPERTIES_H__ +#define __FPGA_PROPERTIES_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Create a fpga_properties object + * + * Initializes the memory pointed at by `prop` to represent a properties + * object, and populates it with the properties of the resource referred to by + * `token`. Individual properties can then be queried using fpgaPropertiesGet*() + * accessor functions. + * + * If `token` is NULL, an "empty" properties object is created to be used as a + * filter for fpgaEnumerate(). All individual fields are set to `don`t care`, + * which implies that the fpga_properties object would match all FPGA resources + * if used for an fpgaEnumerate() query. The matching criteria can be further + * refined by using fpgaSet* functions on the properties object, or the + * object can be populated with the actual properties of a resource by using + * fpgaUpdateProperties(). + * + * @note fpgaGetProperties() will allocate memory for the created properties + * object returned in `prop`. It is the responsibility of the using application + * to free this memory after use by calling fpgaDestroyProperties(). + * + * @param[in] token Token to get properties for. Can be NULL, which will + * create an empty properties object to be used as a + * filter for fpgaEnumerate(). + * @param[out] prop Pointer to a variable of type fpga_properties + * @returns FPGA_OK on success. FPGA_NO_MEMORY if no memory could be allocated + * to create the `fpga_properties` object. FPGA_EXCEPTION if an exception + * happend while initializing the `fpga_properties` object. + */ +fpga_result fpgaGetProperties(fpga_token token, fpga_properties *prop); + +/** + * Update a fpga_properties object + * + * Populates the properties object 'prop' with properties of the resource + * referred to by 'token'. Unlike fpgaGetProperties(), this call will not create + * a new properties object or allocate memory for it, but use a previously + * created properties object. + * + * @param[in] token Token to retrieve properties for + * @param[in] prop fpga_properties object to update + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `token` or `prop` are not + * valid objects. FPGA_NOT_FOUND if the resource referred to by `token` was + * not found. FPGA_NO_DRIVER if not driver is loaded. FPGA_EXCEPTION if an + * internal exception occured when trying to update `prop`. + */ +fpga_result fpgaUpdateProperties(fpga_token token, fpga_properties prop); + +/** + * Clear a fpga_properties object + * + * Sets all fields of the properties object pointed at by 'prop' to 'don't + * care', which implies that the fpga_properties object would match all FPGA + * resources if used for an fpgaEnumerate() query. The matching criteria can be + * further refined by using fpgaSet* functions on the properties object. + * + * Instead of creating a new fpga_properties object every time, this function + * can be used to re-use fpga_properties objects from previous queries. + * + * @param[in] prop fpga_properties object to clear + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `prop` is not a valid + * object. FPGA_EXCEPTION if an * internal exception occured when trying to + * access `prop`. + */ +fpga_result fpgaClearProperties(fpga_properties prop); + +/** + * Clone a fpga_properties object + * + * Creates a copy of an fpga_properties object. + * + * @note This call creates a new properties object and allocates memory for it. + * Both the 'src' and the newly created 'dst' objects will eventually need to be + * destroyed using fpgaDestroyProperties(). + * + * @param[in] src fpga_properties object to copy + * @param[out] dst New fpga_properties object cloned from 'src' + * @returns FPGA_OK on success. FPGA_INVALID_PARAM if `src` is not a valid + * object, or if `dst` is NULL. FPGA_NO_MEMORY if there was not enough memory + * to allocate an `fpga_properties` object for `dst`. FPGA_EXCEPTION if an + * internal exception occurred either accessing `src` or updating `dst`. + */ +fpga_result fpgaCloneProperties(fpga_properties src, fpga_properties *dst); + +/** + * Destroy a fpga_properties object + * + * Destroys an existing fpga_properties object that the caller has previously + * created using fpgaGetProperties() or fpgaCloneProperties(). + * + * @param[inout] prop Pointer to the fpga_properties object to destroy + * @returns FPGA_OK on success. FPGA_INVALID_PARAM is `prop` is not a valid + * object. FPGA_EXCEPTION if an internal exception occurrred while trying to + * access `prop`. + */ +fpga_result fpgaDestroyProperties(fpga_properties *prop); + +/** + * Get the token of the parent object + * + * Returns the token of the parent of the queried resource in '*parent'. + * + * @param[in] prop Properties object to query + * @param[out] parent Pointer to a token variable of the resource 'prop' is + * associated with + * @returns FPGA_NOT_FOUND if resource does not have a + * parent (e.g. an FPGA_DEVICE resource does not have parents). Also see + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetParent(const fpga_properties prop, + fpga_token *parent); + +/** + * Set the token of the parent object + * + * @param[in] prop Properties object to modify + * @param[out] parent Pointer to a token variable of the resource 'prop' is + * associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetParent(fpga_properties prop, + fpga_token parent); +/** + * Get the object type of a resource + * + * Returns the object type of the queried resource. + * + * @param[in] prop Properties object to query + * @param[out] objtype Pointer to an object type variable of the resource + * 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetObjectType(const fpga_properties prop, + fpga_objtype *objtype); + +/** + * Set the object type of a resource + * + * Sets the object type of the resource. * Currently supported object types are + * FPGA_DEVICE and FPGA_ACCELERATOR. + * + * @param[in] prop Properties object to modify + * @param[out] objtype Object type of the resource 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetObjectType(fpga_properties prop, + fpga_objtype objtype); +/** + * Get the PCI bus number of a resource + * + * Returns the bus number the queried resource. + * + * @param[in] prop Properties object to query + * @param[out] bus Pointer to a PCI bus variable of the resource 'prop' + * is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetBus(const fpga_properties prop, uint8_t *bus); + +/** + * Set the PCI bus number of a resource + * + * @param[in] prop Properties object to modify + * @param[in] bus PCI bus number of the resource 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetBus(fpga_properties prop, uint8_t bus); + +/** + * Get the PCI device number of a resource + * + * Returns the device number the queried resource. + * + * @param[in] prop Properties object to query + * @param[out] device Pointer to a PCI device variable of the resource 'prop' + * is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetDevice(const fpga_properties prop, + uint8_t *device); + +/** + * Set the PCI device number of a resource + * + * Enforces the limitation on the number of devices as specified in the + * PCI spec. + * + * @param[in] prop Properties object to modify + * @param[in] device PCI device number of the resource 'prop' is associated + * with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetDevice(fpga_properties prop, + uint8_t device); + +/** + * Get the PCI function number of a resource + * + * Returns the function number the queried resource. + * + * @param[in] prop Properties object to query + * @param[out] function Pointer to PCI function variable of the + * resource 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetFunction(const fpga_properties prop, + uint8_t *function); + +/** + * Set the PCI function number of a resource + * + * Enforces the limitation on the number of functions as specified in the + * PCI spec. + * + * @param[in] prop Properties object to modify + * @param[in] function PCI function number of the resource 'prop' is + * associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetFunction(fpga_properties prop, + uint8_t function); + +/** + * Get the socket id of a resource + * + * Returns the socket id of the queried resource. + * + * @param[in] prop Properties object to query + * @param[out] socket_id Pointer to a socket id variable of the + * resource 'prop' + * is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + * See also "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetSocketID(const fpga_properties prop, + uint8_t *socket_id); + +/** + * Set the socket id of the resource + * + * @param[in] prop Properties object to modify + * @param[in] socket_id Socket id of the resource 'prop' is + * associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetSocketID(fpga_properties prop, + uint8_t socket_id); + +/** + * Get the device id of the resource + * + * @param[in] prop Properties object to query + * @param[out] device_id Pointer to a device id variable of the + * resource 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetDeviceID(const fpga_properties prop, + uint32_t *device_id); + +/** + * Set the device id of the resource + * + * @param[in] prop Properties object to modify + * @param[in] device_id Device id of the resource 'prop' is associated with + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetDeviceID(fpga_properties prop, + uint32_t device_id); + +/** + * Get the number of slots of an FPGA resource property + * + * Returns the number of slots present in an FPGA. + * + * @param[in] prop Properties object to query - must be of type FPGA_DEVICE + * @param[out] num_slots Pointer to number of slots variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetNumSlots(const fpga_properties prop, + uint32_t *num_slots); + +/** + * Set the number of slots of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type + * FPGA_DEVICE + * @param[in] num_slots Number of slots of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetNumSlots(fpga_properties prop, + uint32_t num_slots); + +/** + * Get the BBS ID of an FPGA resource property + * + * Returns the blue bitstream id of an FPGA. + * + * @param[in] prop Properties object to query - must be of type FPGA_DEVICE + * @param[out] bbs_id Pointer to a bbs id variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetBBSID(const fpga_properties prop, + uint64_t *bbs_id); + + +/** + * Set the BBS ID of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type + * FPGA_DEVICE + * @param[in] bbs_id Blue bitstream id of the FPGA resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetBBSID(fpga_properties prop, + uint64_t bbs_id); + + +/** + * Get the BBS Version of an FPGA resource property + * + * Returns the blue bitstream version of an FPGA. + * + * @param[in] prop Properties object to query - must be of type + * FPGA_DEVICE + * @param[out] bbs_version Pointer to a bbs version variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetBBSVersion(const fpga_properties prop, + fpga_version *bbs_version); + +/** + * Set the BBS Version of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type + * FPGA_DEVICE + * @param[in] version Blue bitstream version of the FPGA resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetBBSVersion(fpga_properties prop, + fpga_version version); + + +/** + * Get the vendor id of an FPGA resource property + * + * Returns the vendor id of an FPGA. + * + * @param[in] prop Properties object to query - must be of type FPGA_DEVICE + * @param[out] vendor_id Pointer to a vendor id variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesGetVendorID(const fpga_properties prop, + uint16_t *vendor_id); + + +/** + * Set the vendor id of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE + * @param[in] vendor_id Vendor id of the FPGA resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesSetVendorID(fpga_properties prop, + uint16_t vendor_id); + +/** + * Get the model of an FPGA resource property + * + * Returns the model of an FPGA. + * + * @param[in] prop Properties object to query - must be of type FPGA_DEVICE + * @param[in] model Model of the FPGA resource (string of minimum + * FPGA_MODEL_LENGTH length + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesGetModel(const fpga_properties prop, + char *model); + + +/** + * Set the model of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE + * @param[in] model Model of the FPGA resource (string of maximum + * FPGA_MODEL_LENGTH length + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesSetModel(fpga_properties prop, + char *model); + + +/** + * Get the local memory size of an FPGA resource property + * + * Returns the local memory size of an FPGA. + * + * @param[in] prop Properties object to query - must be of type FPGA_DEVICE + * @param[out] lms Pointer to a memory size variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesGetLocalMemorySize(const fpga_properties prop, + uint64_t *lms); + + +/** + * Set the local memory size of an FPGA resource property + * + * @param[in] prop Properties object to modify - must be of type FPGA_DEVICE + * @param[in] lms Local memory size of the FPGA resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesSetLocalMemorySize(fpga_properties prop, + uint64_t lms); + +/** + * Get the capabilities FPGA resource property + * + * Returns the capabilities of an FPGA. + * Capabilities is a bitfield value + * + * @param[in] prop Properties object to query - must be of type + * FPGA_DEVICE + * @param[out] capabilities Pointer to a capabilities variable of the FPGA + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesGetCapabilities(const fpga_properties prop, + uint64_t *capabilities); + + +/** + * Set the capabilities of an FPGA resource property + * + * Capabilities is a bitfield value + * + * @param[in] prop Properties object to modify - must be of type + * FPGA_DEVICE + * @param[in] capabilities Capabilities of the FPGA resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_DEVICE. See also + * "Accessor Return Values" in [properties.h](#properties-h). + * + * @note This API is not currently supported. + */ +fpga_result fpgaPropertiesSetCapabilities(fpga_properties prop, + uint64_t capabilities); + +/** + * Get the GUID of a resource + * + * Returns the GUID of an FPGA or accelerator object. + * + * For an accelerator, the GUID uniquely identifies a specific accelerator context type, + * i.e. different accelerators will have different GUIDs. For an FPGA, the GUID + * is used to identify a certain instance of an FPGA, e.g. to determine whether + * a given bitstream would be compatible. + * + * @param[in] prop Properties object to query + * @param[out] guid Pointer to a GUID of the slot variable + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetGUID(const fpga_properties prop, + fpga_guid *guid); + +/** + * Set the GUID of a resource + * + * Sets the GUID of an FPGA or accelerator object. + * + * For an accelerator, the GUID uniquely identifies a specific accelerator context type, + * i.e. different accelerators will have different GUIDs. For an FPGA, the GUID + * is used to identify a certain instance of an FPGA, e.g. to determine whether + * a given bitstream would be compatible. + * + * @param[in] prop Properties object to modify + * @param[out] guid Pointer to a GUID of the slot variable + * @returns See "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetGUID(fpga_properties prop, fpga_guid guid); + +/** + * Get the number of mmio spaces + * + * Returns the number of mmio spaces of an AFU properties structure. + * + * @param[in] prop Properties object to query - must be of type FPGA_ACCELERATOR + * @param[out] mmio_spaces Pointer to a variable for number of mmio spaces + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetNumMMIO(const fpga_properties prop, + uint32_t *mmio_spaces); + +/** + * Set the number of mmio spaces + * + * Sets the number of mmio spaces of an AFU properties structure. + * + * @param[in] prop Properties object to modify - must be of type FPGA_ACCELERATOR + * @param[in] mmio_spaces Number of MMIO spaces of the accelerator + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetNumMMIO(fpga_properties prop, + uint32_t mmio_spaces); + +/** + * Get the number of interrupts + * + * Returns the number of interrupts of an accelerator properties structure. + * + * @param[in] prop Properties object to query - must be of type + * FPGA_ACCELERATOR + * @param[out] num_interrupts Pointer to a variable for number of interrupts + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetNumInterrupts(const fpga_properties prop, + uint32_t *num_interrupts); + +/** + * Set the number of mmio spaces + * + * Sets the number of interrupts of an accelerator properties structure. + * + * @param[in] prop Properties object to modify - must be of type + * FPGA_ACCELERATOR + * @param[in] num_interrupts Number of interrupts of the accelerator + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetNumInterrupts(fpga_properties prop, + uint32_t num_interrupts); + +/** + * Get the state of a accelerator resource property + * + * Returns the accelerator state of a accelerator. + * + * @param[in] prop Properties object to query - must be of type FPGA_ACCELERATOR + * @param[out] state Pointer to a accelerator state variable of the accelerator + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesGetAcceleratorState(const fpga_properties prop, + fpga_accelerator_state *state); + + +/** + * Set the state of an accelerator resource property + * + * @param[in] prop Properties object to modify - must be of type FPGA_ACCELERATOR + * @param[in] state accelerator state of the accelerator resource + * @returns FPGA_INVALID_PARAM if object type is not FPGA_ACCELERATOR. See also + * "Accessor Return Values" in [properties.h](#properties-h). + */ +fpga_result fpgaPropertiesSetAcceleratorState(fpga_properties prop, + fpga_accelerator_state state); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_PROPERTIES_H__ + diff --git a/common/include/opae/types.h b/common/include/opae/types.h new file mode 100644 index 000000000000..6a2756396e52 --- /dev/null +++ b/common/include/opae/types.h @@ -0,0 +1,161 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file types.h + * @brief Type definitions for FPGA API + * + * OPAE uses the three opaque types fpga_properties, fpga_token, and + * fpga_handle to create a hierarchy of objects that can be used to enumerate, + * reference, acquire, and query FPGA resources. This object model is designed + * to be extensible to account for different FPGA architectures and platforms. + * + * Initialization + * -------------- + * OPAEs management of the opaque types `fpga_properties`, + * `fpga_token`, and `fpga_handle` relies on the proper initialization of + * variables of these types. In other words, before doing anything with a + * variable of one of these opaque types, you need to first initialize them. + * + * The respective functions that initizalize opaque types are: + * + * * fpgaGetProperties() and fpgaCloneProperties() for `fpga_properties` + * * fpgaEnumerate() and fpgaCloneToken() for `fpga_token` + * * fpgaOpen() for `fpga_handle` + * + * This should intuitively make sense - fpgaGetProperties() creates + * `fpga_properties` objects, fpgaEnumerate() creates `fpga_token` objects, + * fpgaOpen() creates `fpga_handle` objects, and fpgaCloneProperties() and + * fpgaCloneToken() clone (create) `fpga_properties` and `fpga_token` objects, + * respectively. + * + * Since these opaque types are interpreted as pointers (they are typedef'd to + * a `void *`), passing an uninitialized opaque type into any function except + * the respective initailzation function will result in undefined behaviour, + * because OPAE will try to follow an invalid pointer. Undefined behaviour in + * this case may include an unexpected error code, or an application crash. + * + */ + +#ifndef __FPGA_TYPES_H__ +#define __FPGA_TYPES_H__ + +#include +#include +#include + +/** + * Object for expressing FPGA resource properties + * + * `fpga_properties` objects encapsulate all enumerable information about an + * FPGA resources. They can be used for two purposes: selective enumeration + * (discovery) and querying information about existing resources. + * + * For selective enumeration, usually an empty `fpga_properties` object is + * created (using fpgaGetProperties()) and then populated with the desired + * criteria for enumeration. An array of `fpga_properties` can then be passed + * to fpgaEnumerate(), which will return a list of `fpga_token` objects + * matching these criteria. + * + * For querying properties of existing FPGA resources, fpgaGetProperties() can + * also take an `fpga_token` and will return an `fpga_properties` object + * populated with information about the resource referenced by that token. + * + * After use, `fpga_properties` objects should be destroyed using + * fpga_destroyProperties() to free backing memory used by the + * `fpga_properties` object. + */ +typedef void *fpga_properties; + +/** + * Token for referencing FPGA resources + * + * An `fpga_token` serves as a reference to a specific FPGA resource present in + * the system. Holding an `fpga_token` does not constitute ownership of the + * FPGA resource - it merely allows the user to query further information about + * a resource, or to use fpgaOpen() to acquire ownership. + * + * `fpga_token`s are usually returned by fpgaEnumerate() or + * fpgaPropertiesGetParent(), and used by fpgaOpen() to acquire ownership and + * yield a handle to the resource. Some API calls also take `fpga_token`s as + * arguments if they don't require ownership of the resource in question. + */ +typedef void *fpga_token; + +/** + * Handle to an FPGA resource + * + * A valid `fpga_handle` object, as populated by fpgaOpen(), denotes ownership + * of an FPGA resource. Note that ownership can be exclusive or shared, + * depending on the flags used in fpgaOpen(). Ownership can be released by + * calling fpgaClose(), which will render the underlying handle invalid. + * + * Many OPAE C API functions require a valid token (which is synonymous with + * ownership of the resource). + */ +typedef void *fpga_handle; + +/** + * Globally unique identifier (GUID) + * + * GUIDs are used widely within OPAE for helping identify FPGA resources. For + * example, every FPGA resource has a `guid` property, which can be (and in the + * case of FPGA_ACCELERATOR resource primarily is) used for enumerating a resource of a + * specific type. + * + * `fpga_guid` is compatible with libuuid's uuid_t, so users can use libuuid + * functions like uuid_parse() to create and work with GUIDs. + */ +typedef uint8_t fpga_guid[16]; + +/** + * Semantic version + * + * Data structure for expressing version identifiers following the semantic + * versioning scheme. Used in various properties for tracking component + * versions. + */ +typedef struct { + uint8_t major; /**< Major version */ + uint8_t minor; /**< Minor version */ + uint16_t patch; /**< Revision or patchlevel */ +} fpga_version; + +/** Handle to an event object + * + * OPAE provides an interface to asynchronous events that can be generated by + * different FPGA resources. The event API provides functions to register for + * these events; associated with every event a process has registered for is an + * `fpga_event_handle`, which encapsulates the OS-specific data structure for + * event objects. + * + * On Linux, an `fpga_event_handle` can be used as a file descriptor and passed + * to select(), poll(), epoll() and similar functions to wait for asynchronous + * events. + */ +typedef int fpga_event_handle; + +#endif // __FPGA_TYPES_H__ diff --git a/common/include/opae/types_enum.h b/common/include/opae/types_enum.h new file mode 100644 index 000000000000..da4074eb6b9a --- /dev/null +++ b/common/include/opae/types_enum.h @@ -0,0 +1,137 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * @file types_enum.h + * @brief Definitions of enumerated types for the OPAE C API + * + * This file defines return and error codes, event and object types, states, + * and flags as used or reported by OPAE C API functions. + */ + +#ifndef __FPGA_TYPES_ENUM_H__ +#define __FPGA_TYPES_ENUM_H__ + +/** + * OPAE C API function return codes + * + * Every public API function exported by the OPAE C library will return one of + * these codes. Usually, FPGA_OK denotes successful completion of the requested + * operation, while any return code *other* than FPGA_OK indicates an error or + * other deviation from the expected behavior. Users of the OPAE C API should + * always check the return codes of the APIs they call, and not use output + * parameters of functions that did not execute successfully. + + * The fpgaErrStr() function converts error codes into printable messages. + * + * OPAE also has a logging mechanism that allows a developer to get more + * information about why a particular call failed with a specific message. If + * enabled, any function that returns an error code different from FPGA_OK will + * also print out a message with further details. This mechanism can be enabled + * by setting the environment variable `LIBOPAE_LOG` to 1 before running the + * respective application. + */ +typedef enum { + FPGA_OK = 0, /**< Operation completed successfully */ + FPGA_INVALID_PARAM, /**< Invalid parameter supplied */ + FPGA_BUSY, /**< Resource is busy */ + FPGA_EXCEPTION, /**< An exception occurred */ + FPGA_NOT_FOUND, /**< A required resource was not found */ + FPGA_NO_MEMORY, /**< Not enough memory to complete operation */ + FPGA_NOT_SUPPORTED, /**< Requested operation is not supported */ + FPGA_NO_DRIVER, /**< Driver is not loaded */ + FPGA_NO_DAEMON, /**< FPGA Daemon (fpgad) is not running */ + FPGA_NO_ACCESS, /**< Insufficient privileges or permissions */ + FPGA_RECONF_ERROR /**< Error while reconfiguring FPGA */ +} fpga_result; + +/** + * FPGA events + * + * OPAE currently defines the following event types that applications can + * register for. Note that not all FPGA resources and target platforms may + * support all event types. + */ +typedef enum { + FPGA_EVENT_INTERRUPT = 0, /**< Interrupt generated by an accelerator */ + FPGA_EVENT_ERROR, /**< Infrastructure error event */ + FPGA_EVENT_POWER_THERMAL /**< Infrastructure thermal event */ +} fpga_event_type; + +/* TODO: consider adding lifecycle events in the future + * to help with orchestration. Need a complete specification + * before including them in the API. Proposed events: + * FPGA_EVENT_APPEAR + * FPGA_EVENT_DISAPPEAR + * FPGA_EVENT_CHANGE + */ + +/** accelerator state */ +typedef enum { + /** accelerator is opened exclusively by another process */ + FPGA_ACCELERATOR_ASSIGNED = 0, + /** accelerator is free to be opened */ + FPGA_ACCELERATOR_UNASSIGNED +} fpga_accelerator_state; + +/** + * OPAE FPGA resources (objects) + * + * These are the FPGA resources currently supported by the OPAE object model. + */ +typedef enum { + /** FPGA_DEVICE objects represent FPGA devices and their management functionality. + * These objects can be opened (typically requires a certain privilege level or + * access permissions) and used for management functions like fpgaReconfigreSlot(). */ + FPGA_DEVICE = 0, + /** FPGA_ACCELERATOR objects represent allocatable units for accessing + * accelerated functions on the FPGA. They are frequently opened for + * interacting via control registers (MMIO), shared memory, or other, + * possibly platform-specific functions. */ + FPGA_ACCELERATOR +} fpga_objtype; + +/** + * Buffer flags + * + * These flags can be passed to the fpgaPrepareBuffer() function. + */ +enum fpga_buffer_flags { + FPGA_BUF_PREALLOCATED = (1u << 0), /**< Use existing buffer */ + FPGA_BUF_QUIET = (1u << 1) /**< Suppress error messages */ +}; + +/** + * Open flags + * + * These flags can be passed to the fpgaOpen() function. + */ +enum fpga_open_flags { + /** Open FPGA resource for shared access */ + FPGA_OPEN_SHARED = (1u << 0) +}; + +#endif // __FPGA_TYPES_ENUM_H__ diff --git a/common/include/opae/umsg.h b/common/include/opae/umsg.h new file mode 100644 index 000000000000..f6544193ab2f --- /dev/null +++ b/common/include/opae/umsg.h @@ -0,0 +1,116 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * \file umsg.h + * \brief FPGA UMsg API + */ + +#ifndef __FPGA_UMSG_H__ +#define __FPGA_UMSG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Get number of Umsgs + * + * Retuns number of umsg supported by AFU. + * + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[out] value Returns number of UMsgs + * @returns FPGA_OK on success. + * FPGA_INVALID_PARAM if input parameter combination + * is not valid. + * FPGA_EXCEPTION if input parameter fpga handle is not + * valid. + */ +fpga_result fpgaGetNumUmsg(fpga_handle handle, uint64_t *value); + +/** + * Sets Umsg hint + * + * Writes usmg hint bit. + * + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] value Value to use for UMsg hint, Umsg hit is N wide bitvector + * where N = number of Umsgs. + * @returns FPGA_OK on success. + * FPGA_INVALID_PARAM if input parameter combination + * is not valid. + * FPGA_EXCEPTION if input parameter fpga handle is not + * valid. + */ +fpga_result fpgaSetUmsgAttributes(fpga_handle handle, + uint64_t value); + +/** + * Trigger Umsg + * + * Writes a 64-bit value to trigger low-latency accelerator notification mechanism + * (UMsgs). + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[in] value Value to use for UMsg + * @returns FPGA_OK on success. + * FPGA_INVALID_PARAM if input parameter combination + * is not valid. + * FPGA_EXCEPTION if input parameter fpga handle is not + * valid. + */ +fpga_result fpgaTriggerUmsg(fpga_handle handle, uint64_t value); + +/** + * Access UMsg memory directly + * + * This function will return a pointer to the memory allocated for low latency + * accelerator notifications (UMsgs). + * @note This call is only supported by hardware targets, not by ASE + * simulation. Use fpgaTriggerUmsg() if you need ASE simulation capabilities. + * + * @param[in] handle Handle to previously opened accelerator resource + * @param[out] umsg_ptr Pointer to memory where a pointer to the virtual + * address space will be returned + * @returns FPGA_OK on success. + * FPGA_INVALID_PARAM if input parameter combination + * is not valid. + * FPGA_EXCEPTION if input parameter fpga handle is not + * valid. + * FPGA_NO_MEMORY if memory allocation fails or system + * doesn't configure huge pages. + */ +fpga_result fpgaGetUmsgPtr(fpga_handle handle, uint64_t **umsg_ptr); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_UMSG_H__ diff --git a/common/include/opae/utils.h b/common/include/opae/utils.h new file mode 100644 index 000000000000..2675233ab820 --- /dev/null +++ b/common/include/opae/utils.h @@ -0,0 +1,58 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * \file utils.h + * \brief Utility functions and macros for the FPGA API + */ + +#ifndef __FPGA_UTILS_H__ +#define __FPGA_UTILS_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Return human-readable error message + * + * Returns a pointer to a human-readable error message corresponding to the + * provided fpga_error error code. + * + * @param[in] e Error code (as returned by another FPGA API function + * @returns Pointer to a descriptive error message string + */ +const char *fpgaErrStr(fpga_result e); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_UTILS_H__ + diff --git a/common/include/safe_string/safe_string.h b/common/include/safe_string/safe_string.h new file mode 100644 index 000000000000..d8697d6a41bc --- /dev/null +++ b/common/include/safe_string/safe_string.h @@ -0,0 +1,710 @@ + +/*------------------------------------------------------------------ + * safe_types.h - C99 std types & defs or Linux kernel equivalents + * + * March 2007, Bo Berry + * Modified 2012, Jonathan Toppins + * + * Copyright (c) 2007-2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_TYPES_H__ +#define __SAFE_TYPES_H__ + +#ifdef __KERNEL__ +/* linux kernel environment */ + +#include +#include +#include + +/* errno_t isn't defined in the kernel */ +typedef int errno_t; + +#else + +#include +#include +#include +#include +#include + +typedef int errno_t; + +#include + +#endif /* __KERNEL__ */ +#endif /* __SAFE_TYPES_H__ */ + + + +/*------------------------------------------------------------------ + * safe_lib_errno.h -- Safe C Lib Error codes + * + * October 2008, Bo Berry + * Modified 2012, Jonathan Toppins + * + * Copyright (c) 2008-2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_LIB_ERRNO_H__ +#define __SAFE_LIB_ERRNO_H__ + +#ifdef __KERNEL__ +# include +#else +#include +#endif /* __KERNEL__ */ + +/* + * Safe Lib specific errno codes. These can be added to the errno.h file + * if desired. + */ +#ifndef ESNULLP +#define ESNULLP ( 400 ) /* null ptr */ +#endif + +#ifndef ESZEROL +#define ESZEROL ( 401 ) /* length is zero */ +#endif + +#ifndef ESLEMIN +#define ESLEMIN ( 402 ) /* length is below min */ +#endif + +#ifndef ESLEMAX +#define ESLEMAX ( 403 ) /* length exceeds max */ +#endif + +#ifndef ESOVRLP +#define ESOVRLP ( 404 ) /* overlap undefined */ +#endif + +#ifndef ESEMPTY +#define ESEMPTY ( 405 ) /* empty string */ +#endif + +#ifndef ESNOSPC +#define ESNOSPC ( 406 ) /* not enough space for s2 */ +#endif + +#ifndef ESUNTERM +#define ESUNTERM ( 407 ) /* unterminated string */ +#endif + +#ifndef ESNODIFF +#define ESNODIFF ( 408 ) /* no difference */ +#endif + +#ifndef ESNOTFND +#define ESNOTFND ( 409 ) /* not found */ +#endif + +/* Additional for safe snprintf_s interfaces */ +#ifndef ESBADFMT +#define ESBADFMT ( 410 ) /* bad format string */ +#endif + +#ifndef ESFMTTYP +#define ESFMTTYP ( 411 ) /* bad format type */ +#endif + +/* EOK may or may not be defined in errno.h */ +#ifndef EOK +#define EOK ( 0 ) +#endif + +#endif /* __SAFE_LIB_ERRNO_H__ */ + + + + + +/*------------------------------------------------------------------ + * safe_lib.h -- Safe C Library + * + * October 2008, Bo Berry + * Modified 2012, Jonathan Toppins + * + * Copyright (c) 2008-2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_LIB_H__ +#define __SAFE_LIB_H__ + +/* #include "safe_types.h" */ +/* #include "safe_lib_errno.h" */ + +/* C11 appendix K types - specific for bounds checking */ +typedef size_t rsize_t; + +/* + * We depart from the standard and allow memory and string operations to + * have different max sizes. See the respective safe_mem_lib.h or + * safe_str_lib.h files. + */ +/* #define RSIZE_MAX (~(rsize_t)0) - leave here for completeness */ + +typedef void (*constraint_handler_t) (const char * /* msg */, + void * /* ptr */, + errno_t /* error */); + +/* +extern void abort_handler_s(const char *msg, void *ptr, errno_t error); +extern void ignore_handler_s(const char *msg, void *ptr, errno_t error); +*/ + +#if defined(__cplusplus) +extern "C" { +#endif // __cplusplus + +void opae_safestr_abort_handler_s(const char *msg, void *ptr, errno_t error); +void opae_safestr_ignore_handler_s(const char *msg, void *ptr, errno_t error); + +#if defined(__cplusplus) +} +#endif // __cplusplus + +/* #define sl_default_handler ignore_handler_s */ +#define sl_default_handler opae_safestr_ignore_handler_s + +/* #include "safe_mem_lib.h" */ +/* #include "safe_str_lib.h" */ + +#endif /* __SAFE_LIB_H__ */ + + + + + +/*------------------------------------------------------------------ + * safe_mem_lib.h -- Safe C Library Memory APIs + * + * October 2008, Bo Berry + * Modified 2012, Jonathan Toppins + * + * Copyright (c) 2008-2012 by Cisco Systems, Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_MEM_LIB_H__ +#define __SAFE_MEM_LIB_H__ + +/* #include "safe_lib.h" */ +#include + +#define RSIZE_MAX_MEM ( 256UL << 20 ) /* 256MB */ +#define RSIZE_MAX_MEM16 ( RSIZE_MAX_MEM/2 ) +#define RSIZE_MAX_MEM32 ( RSIZE_MAX_MEM/4 ) + +#if defined(__cplusplus) +extern "C" { +#endif // __cplusplus + +/* set memory constraint handler */ +/* extern constraint_handler_t +set_mem_constraint_handler_s(constraint_handler_t handler); +*/ + +constraint_handler_t +opae_set_mem_constraint_handler_s(constraint_handler_t handler); + +/* compare memory */ +extern errno_t memcmp_s(const void *dest, rsize_t dmax, + const void *src, rsize_t slen, int *diff); + +/* compare uint16_t memory */ +extern errno_t memcmp16_s(const uint16_t *dest, rsize_t dmax, + const uint16_t *src, rsize_t slen, int *diff); + +/* compare uint32_t memory */ +extern errno_t memcmp32_s(const uint32_t *dest, rsize_t dmax, + const uint32_t *src, rsize_t slen, int *diff); + + +/* copy memory */ +extern errno_t memcpy_s(void *dest, rsize_t dmax, + const void *src, rsize_t slen); + +/* copy uint16_t memory */ +extern errno_t memcpy16_s(uint16_t *dest, rsize_t dmax, + const uint16_t *src, rsize_t slen); + +/* copy uint32_t memory */ +extern errno_t memcpy32_s(uint32_t *dest, rsize_t dmax, + const uint32_t *src, rsize_t slen); + +/* copy wchar_t memory */ +extern errno_t wmemcpy_s(wchar_t *dest, rsize_t dmax, + const wchar_t *src, rsize_t slen); + + +/* move memory, including overlapping memory */ +extern errno_t memmove_s(void *dest, rsize_t dmax, + const void *src, rsize_t slen); + +/* uint16_t move memory, including overlapping memory */ +extern errno_t memmove16_s(uint16_t *dest, rsize_t dmax, + const uint16_t *src, rsize_t slen); + +/* uint32_t move memory, including overlapping memory */ +extern errno_t memmove32_s(uint32_t *dest, rsize_t dmax, + const uint32_t *src, rsize_t slen); + +/* copy wchar_t memory, including overlapping memory */ +extern errno_t wmemmove_s(wchar_t *dest, rsize_t dmax, + const wchar_t *src, rsize_t slen); + + +/* set bytes */ +extern errno_t memset_s(void *dest, rsize_t dmax, uint8_t value); + +/* set uint16_t */ +extern errno_t memset16_s(uint16_t *dest, rsize_t dmax, uint16_t value); + +/* set uint32_t */ +extern errno_t memset32_s(uint32_t *dest, rsize_t dmax, uint32_t value); + + +/* byte zero */ +extern errno_t memzero_s(void *dest, rsize_t dmax); + +/* uint16_t zero */ +extern errno_t memzero16_s(uint16_t *dest, rsize_t dmax); + +/* uint32_t zero */ +extern errno_t memzero32_s(uint32_t *dest, rsize_t dmax); + +#if defined(__cplusplus) +} +#endif // __cplusplus + +#endif /* __SAFE_MEM_LIB_H__ */ + + + + + +/*------------------------------------------------------------------ + * safe_str_lib.h -- Safe C Library String APIs + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_STR_LIB_H__ +#define __SAFE_STR_LIB_H__ + +/* #include "safe_lib.h" */ + +/* + * The shortest string is a null string!! + */ +#define RSIZE_MIN_STR ( 1 ) + +/* maximum sring length */ +#define RSIZE_MAX_STR ( 4UL << 10 ) /* 4KB */ + + +/* The makeup of a password */ +#define SAFE_STR_MIN_LOWERCASE ( 2 ) +#define SAFE_STR_MIN_UPPERCASE ( 2 ) +#define SAFE_STR_MIN_NUMBERS ( 1 ) +#define SAFE_STR_MIN_SPECIALS ( 1 ) + +#define SAFE_STR_PASSWORD_MIN_LENGTH ( 6 ) +#define SAFE_STR_PASSWORD_MAX_LENGTH ( 32 ) + +#if defined(__cplusplus) +extern "C" { +#endif // __cplusplus + +/* set string constraint handler */ +/* extern constraint_handler_t +set_str_constraint_handler_s(constraint_handler_t handler); +*/ + +constraint_handler_t +opae_set_str_constraint_handler_s(constraint_handler_t handler); + +/* string compare */ +extern errno_t +strcasecmp_s(const char *dest, rsize_t dmax, + const char *src, int *indicator); + + +/* find a substring _ case insensitive */ +extern errno_t +strcasestr_s(char *dest, rsize_t dmax, + const char *src, rsize_t slen, char **substring); + + +/* string concatenate */ +extern errno_t +strcat_s(char *dest, rsize_t dmax, const char *src); + + +/* string compare */ +extern errno_t +strcmp_s(const char *dest, rsize_t dmax, + const char *src, int *indicator); + + +/* fixed field string compare */ +extern errno_t +strcmpfld_s(const char *dest, rsize_t dmax, + const char *src, int *indicator); + + +/* string copy */ +extern errno_t +strcpy_s(char *dest, rsize_t dmax, const char *src); + +/* string copy */ +extern char * +stpcpy_s(char *dest, rsize_t dmax, const char *src, errno_t *err); + +/* fixed char array copy */ +extern errno_t +strcpyfld_s(char *dest, rsize_t dmax, const char *src, rsize_t slen); + + +/* copy from a null terminated string to fixed char array */ +extern errno_t +strcpyfldin_s(char *dest, rsize_t dmax, const char *src, rsize_t slen); + + +/* copy from a char array to null terminated string */ +extern errno_t +strcpyfldout_s(char *dest, rsize_t dmax, const char *src, rsize_t slen); + + +/* computes excluded prefix length */ +extern errno_t +strcspn_s(const char *dest, rsize_t dmax, + const char *src, rsize_t slen, rsize_t *count); + + +/* returns a pointer to the first occurrence of c in dest */ +extern errno_t +strfirstchar_s(char *dest, rsize_t dmax, char c, char **first); + + +/* returns index of first difference */ +extern errno_t +strfirstdiff_s(const char *dest, rsize_t dmax, + const char *src, rsize_t *index); + + +/* validate alphanumeric string */ +extern bool +strisalphanumeric_s(const char *str, rsize_t slen); + + +/* validate ascii string */ +extern bool +strisascii_s(const char *str, rsize_t slen); + + +/* validate string of digits */ +extern bool +strisdigit_s(const char *str, rsize_t slen); + + +/* validate hex string */ +extern bool +strishex_s(const char *str, rsize_t slen); + + +/* validate lower case */ +extern bool +strislowercase_s(const char *str, rsize_t slen); + + +/* validate mixed case */ +extern bool +strismixedcase_s(const char *str, rsize_t slen); + + +/* validate password */ +extern bool +strispassword_s(const char *str, rsize_t slen); + + +/* validate upper case */ +extern bool +strisuppercase_s(const char *str, rsize_t slen); + + +/* returns a pointer to the last occurrence of c in s1 */ +extern errno_t +strlastchar_s(char *str, rsize_t smax, char c, char **first); + + +/* returns index of last difference */ +extern errno_t +strlastdiff_s(const char *dest, rsize_t dmax, + const char *src, rsize_t *index); + + +/* left justify */ +extern errno_t +strljustify_s(char *dest, rsize_t dmax); + + +/* fitted string concatenate */ +extern errno_t +strncat_s(char *dest, rsize_t dmax, const char *src, rsize_t slen); + + +/* fitted string copy */ +extern errno_t +strncpy_s(char *dest, rsize_t dmax, const char *src, rsize_t slen); + + +/* string length */ +extern rsize_t +strnlen_s (const char *s, rsize_t smax); + + +/* string terminate */ +extern rsize_t +strnterminate_s (char *s, rsize_t smax); + + +/* get pointer to first occurrence from set of char */ +extern errno_t +strpbrk_s(char *dest, rsize_t dmax, + char *src, rsize_t slen, char **first); + + +extern errno_t +strfirstsame_s(const char *dest, rsize_t dmax, + const char *src, rsize_t *index); + +extern errno_t +strlastsame_s(const char *dest, rsize_t dmax, + const char *src, rsize_t *index); + + +/* searches for a prefix */ +extern errno_t +strprefix_s(const char *dest, rsize_t dmax, const char *src); + + +/* removes leading and trailing white space */ +extern errno_t +strremovews_s(char *dest, rsize_t dmax); + + +/* computes inclusive prefix length */ +extern errno_t +strspn_s(const char *dest, rsize_t dmax, + const char *src, rsize_t slen, rsize_t *count); + + +/* find a substring */ +extern errno_t +strstr_s(char *dest, rsize_t dmax, + const char *src, rsize_t slen, char **substring); + + +/* string tokenizer */ +extern char * +strtok_s(char *s1, rsize_t *s1max, const char *src, char **ptr); + + +/* convert string to lowercase */ +extern errno_t +strtolowercase_s(char *str, rsize_t slen); + + +/* convert string to uppercase */ +extern errno_t +strtouppercase_s(char *str, rsize_t slen); + + +/* zero an entire string with nulls */ +extern errno_t +strzero_s(char *dest, rsize_t dmax); + +#if defined(__cplusplus) +} +#endif // __cplusplus + +#endif /* __SAFE_STR_LIB_H__ */ + + + + + +/*------------------------------------------------------------------ + * sprintf_s.h -- Safe Sprintf Interfaces + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ +#ifndef SPRINTF_S_H_ +#define SPRINTF_S_H_ + +/* #include */ + + +#define SNPRFNEGATE(x) (-1*(x)) + +#if defined(__cplusplus) +extern "C" { +#endif // __cplusplus + +int snprintf_s_i(char *dest, rsize_t dmax, const char *format, int a); +int snprintf_s_si(char *dest, rsize_t dmax, const char *format, char *s, int a); +int snprintf_s_l(char *dest, rsize_t dmax, const char *format, long a); +int snprintf_s_sl(char *dest, rsize_t dmax, const char *format, char *s, long a); + +int snprintf_s_il(char *dest, rsize_t dmax, const char *format, int a, long b); + +#if defined(__cplusplus) +} +#endif // __cplusplus + +#endif /* SPRINTF_S_H_ */ + diff --git a/doc/Doxyfile.in b/doc/Doxyfile.in new file mode 100644 index 000000000000..13bf67764e3d --- /dev/null +++ b/doc/Doxyfile.in @@ -0,0 +1,1775 @@ +# Doxyfile 1.7.6.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" "). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. + +PROJECT_NAME = "OPAE C API" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = @PACKAGE@-@PACKAGE_VERSION@ + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = "FPGA API" + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = @DOX_OUTPUT_DIRECTORY@ + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = YES + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, +# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English +# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, +# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = @DOX_STRIP_FROM_PATH@ + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = @DOX_STRIP_FROM_INC_PATH@ + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful if your file system +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = YES + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 3 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding +# "class=itcl::class" will allow you to use the command class in the +# itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given extension. +# Doxygen has a built-in mapping, but you can override or extend it using this +# tag. The format is ext=language, where ext is a file extension, and language +# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, +# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make +# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C +# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions +# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also makes the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = YES + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate getter +# and setter methods for a property. Setting this option to YES (the default) +# will make doxygen replace the get and set methods by a property in the +# documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = YES + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and +# unions with only public data fields will be shown inline in the documentation +# of the scope in which they are defined (i.e. file, namespace, or group +# documentation), provided this scope is documented. If set to NO (the default), +# structs, classes, and unions are shown on a separate page (for HTML and Man +# pages) or section (for LaTeX and RTF). + +INLINE_SIMPLE_STRUCTS = YES + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = YES + +# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be +# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given +# their name and scope. Since this can be an expensive process and often the +# same symbol appear multiple times in the code, doxygen keeps a cache of +# pre-resolved symbols. If the cache is too small doxygen will become slower. +# If the cache is too large, memory is wasted. The cache size is given by this +# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = @DOX_EXTRACT_ALL@ + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = YES + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = YES + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespaces are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = YES + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = YES + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = NO + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = YES + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = @DOX_GENERATETODOLIST@ + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = @DOX_GENERATETESTLIST@ + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = @DOX_GENERATEBUGLIST@ + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= @DOX_GENERATEDEPRECATEDLIST@ + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or macro consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and macros in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = NO + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. The create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = @DOX_LAYOUT_FILE@ + +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this +# feature you need bibtex and perl available in the search path. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = @DOX_WARNINGS@ + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_NO_PARAMDOC option can be enabled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = @ABS_SRCDIR@/common/include/opae + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl + +FILE_PATTERNS = *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.xpm + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = YES + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = */archive/* + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = @DOX_GENERATE_HTML@ + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is advised to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# style sheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the style sheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = NO + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = YES + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) +# at top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. Since the tabs have the same information as the +# navigation tree you can set this option to NO if you already set +# GENERATE_TREEVIEW to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. +# Since the tree basically has the same information as the tab index you +# could consider to set DISABLE_INDEX to NO when enabling this option. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. + +ENUM_VALUES_PER_LINE = 4 + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = NO + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the +# mathjax.org site, so you can quickly see the result without installing +# MathJax, but it is strongly recommended to install a local copy of MathJax +# before deployment. + +MATHJAX_RELPATH = http://www.mathjax.org/mathjax + +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = NO + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a PHP enabled web server instead of at the web client +# using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server +# based approach is that it scales better to large projects and allows +# full text search. The disadvantages are that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = @DOX_GENERATE_LATEX@ + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = @DOX_USE_PDFLATEX@ + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = YES + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = YES + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = @DOX_GENERATE_RTF@ + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = YES + +# Load style sheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = @DOX_GENERATE_MAN@ + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = @DOX_GENERATE_XML@ + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = YES + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# pointed to by INCLUDE_PATH will be searched when a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# PREDEFINED = __cplusplus +# __linux__ +# __GNUC__ + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. + +EXPAND_AS_DEFINED = + +# EXPAND_AS_DEFINED = NVSFileIO + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = @DOX_GENERATE_TAGFILE@ + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = @PERL@ + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = @HAVE_DOT@ + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. + +DOT_FONTNAME = Helvetica + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = YES + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will generate a graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). + +DOT_IMAGE_FORMAT = png + +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 1000 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = YES + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/doc/DoxygenLayout.xml b/doc/DoxygenLayout.xml new file mode 100644 index 000000000000..8890d8369312 --- /dev/null +++ b/doc/DoxygenLayout.xml @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libopae/CMakeLists.txt b/libopae/CMakeLists.txt new file mode 100644 index 000000000000..08fc9a47739f --- /dev/null +++ b/libopae/CMakeLists.txt @@ -0,0 +1,127 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +project(libopae-c) + +############################################################################ +## Add 'coverage' ########################################################## +############################################################################ + +if(CMAKE_BUILD_TYPE STREQUAL "Coverage") + include(coverage) +endif(CMAKE_BUILD_TYPE STREQUAL "Coverage") + +############################################################################ +## Add 'libopae-c' library ################################################### +############################################################################ +set(SRC + src/common.c + src/enum.c + src/umsg.c + src/reconf.c + src/open.c + src/close.c + src/reset.c + src/mmio.c + src/buffer.c + src/bitstream.c + src/hostif.c + src/event.c + src/properties.c + src/log.c + src/sysfs.c + src/wsid_list.c + src/token_list.c + src/mmap.c + src/usrclk/user_clk_pgm_uclock.c) + +# Define target +add_library(opae-c SHARED ${SRC}) +add_dependencies(opae-c copy-common-opae-header-files) +target_link_libraries(opae-c + m + safestr + ${libjson-c_LIBRARIES} + ${libuuid_LIBRARIES}) + +# Define headers for this library. PUBLIC headers are used for +# compiling the library, and will be added to consumers' build +# paths. Keep current directory private. +target_include_directories(opae-c PUBLIC + $ + $ + PRIVATE src) + +# Add coverage flags +if(CMAKE_BUILD_TYPE STREQUAL "Coverage") + set_property(SOURCE ${SRC} APPEND PROPERTY COMPILE_FLAGS ${GCOV_COMPILE_FLAGS}) +endif(CMAKE_BUILD_TYPE STREQUAL "Coverage") + +# Target properties +set_property(TARGET opae-c PROPERTY C_STANDARD 99) +set_target_properties(opae-c PROPERTIES + VERSION ${INTEL_FPGA_API_VERSION} + SOVERSION ${INTEL_FPGA_API_VER_MAJOR}) + +# Add coverage flags +if(CMAKE_BUILD_TYPE STREQUAL "Coverage") + target_link_libraries(opae-c ${GCOV_LINK_FLAGS}) +endif(CMAKE_BUILD_TYPE STREQUAL "Coverage") + +# Set debug flags, if required +if(CMAKE_BUILD_TYPE STREQUAL "Debug") + add_definitions(-DLIBOPAE_DEBUG) +endif(CMAKE_BUILD_TYPE STREQUAL "Debug") + +# Hide non-public symbols when building release +if(CMAKE_BUILD_TYPE STREQUAL "Release") + message("!! Building for release, may break internal tests") + set_property(TARGET opae-c PROPERTY C_VISIBILITY_PRESET hidden) +endif(CMAKE_BUILD_TYPE STREQUAL "Release") + +# Binary install locations +install(TARGETS opae-c + LIBRARY DESTINATION lib + COMPONENT opaeclib) + +############################################################################ +## Add 'doxygen' target #################################################### +############################################################################ +find_package(Doxygen) +if (DOXYGEN_FOUND) + include(doxygen) +endif() + +############################################################################ +## Add 'coverage' ########################################################## +############################################################################ + +if(CMAKE_BUILD_TYPE STREQUAL "Coverage") + if(BUILD_TESTS AND GTEST_FOUND) + set_target_for_coverage(opae-c bin/gtapi -p) + add_dependencies(coverage_opae-c gtapi) + endif(BUILD_TESTS AND GTEST_FOUND) +endif(CMAKE_BUILD_TYPE STREQUAL "Coverage") diff --git a/libopae/src/bitstream.c b/libopae/src/bitstream.c new file mode 100644 index 000000000000..f071d19a7107 --- /dev/null +++ b/libopae/src/bitstream.c @@ -0,0 +1,588 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include +#include +#include +#include + +#include "safe_string/safe_string.h" +#include "opae/utils.h" + +#include "common_int.h" +#include "bitstream_int.h" + +#define METADATA_GUID "58656F6E-4650-4741-B747-425376303031" +#define METADATA_GUID_LEN 16 +#define FPGA_GBS_6_3_0_MAGIC 0x1d1f8680 // dec: 488605312 +#define PR_INTERFACE_ID "pr/interface_id" +#define INTFC_ID_LOW_LEN 16 +#define INTFC_ID_HIGH_LEN 16 +#define BUFFER_SIZE 32 + + +// GBS json metadata +// GBS version +#define GBS_VERSION "version" + +// AFU image +#define GBS_AFU_IMAGE "afu-image" +#define GBS_MAGIC_NUM "magic-no" +#define BBS_INTERFACE_ID "interface-uuid" +#define GBS_CLOCK_FREQUENCY_HIGH "clock-frequency-high" +#define GBS_CLOCK_FREQUENCY_LOW "clock-frequency-low" +#define GBS_AFU_POWER "power" + +// AFU Clusters +#define GBS_ACCELERATOR_CLUSTERS "accelerator-clusters" +#define GBS_AFU_NAME "name" +#define GBS_ACCELERATOR_TYPE_UUID "accelerator-type-uuid" +#define GBS_ACCELERATOR_TOTAL_CONTEXTS "total-contexts" + + +fpga_result string_to_guid(const char *guid, fpga_guid *result) +{ + if (uuid_parse(guid, *result) < 0) { + FPGA_MSG("Error parsing GUID %s\n", guid); + return FPGA_INVALID_PARAM; + } + + return FPGA_OK; +} + +static json_bool get_json_object(json_object **object, json_object **parent, + char *field_name) +{ + return json_object_object_get_ex(*parent, field_name, &(*object)); +} + +static uint64_t read_int_from_bitstream(const uint8_t *bitstream, uint8_t size) +{ + uint64_t ret = 0; + switch (size) { + + case sizeof(uint8_t): + ret = *((uint8_t *) bitstream); + break; + case sizeof(uint16_t): + ret = *((uint16_t *) bitstream); + break; + case sizeof(uint32_t): + ret = *((uint32_t *) bitstream); + break; + case sizeof(uint64_t): + ret = *((uint64_t *) bitstream); + break; + default: + FPGA_ERR("Unknown integer size"); + } + + return ret; +} + +static int64_t int64_be_to_le(int64_t val) +{ + val = ((val << 8) & 0xFF00FF00FF00FF00ULL) | + ((val >> 8) & 0x00FF00FF00FF00FFULL); + val = ((val << 16) & 0xFFFF0000FFFF0000ULL) | + ((val >> 16) & 0x0000FFFF0000FFFFULL); + return (val << 32) | ((val >> 32) & 0xFFFFFFFFULL); +} + +fpga_result get_interface_id(fpga_handle handle, uint64_t *id_l, uint64_t *id_h) +{ + char file_path[SYSFS_PATH_MAX]; + struct stat astats; + int fd; + int ret; + int b; + char buf[BUFFER_SIZE]; + char buf_l[INTFC_ID_LOW_LEN + 1]; + char buf_h[INTFC_ID_HIGH_LEN + 1]; + struct _fpga_token *_token; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + errno_t e; + + _token = (struct _fpga_token *)_handle->token; + if (!_token) { + FPGA_MSG("Token is NULL"); + return FPGA_INVALID_PARAM; + } + + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token in handle"); + return FPGA_INVALID_PARAM; + } + + if (id_l == NULL || id_h == NULL) { + FPGA_MSG("id_l or id_h are NULL"); + return FPGA_INVALID_PARAM; + } + + // PR Interface id path + snprintf(file_path, sizeof(file_path), "%s/%s", _token->sysfspath, + PR_INTERFACE_ID); + + if ((stat(file_path, &astats)) != FPGA_OK) { + FPGA_MSG("stat(%s) failed", file_path); + return FPGA_EXCEPTION; + } + + if (S_ISDIR(astats.st_mode)) { + FPGA_MSG("%s should not be a directory", file_path); + return FPGA_EXCEPTION; + } + + fd = open(file_path, O_RDONLY); + if (fd < 0) { + FPGA_MSG("open(%s) failed", file_path); + return FPGA_EXCEPTION; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek failed on %s", file_path); + close(fd); + return FPGA_EXCEPTION; + } + + memset(buf, 0, sizeof(buf)); + + b = 0; + do { + ret = read(fd, buf+b, sizeof(buf)-b); + if (ret <= 0) { + FPGA_MSG("read failed on %s", file_path); + close(fd); + return FPGA_EXCEPTION; + } + b += ret; + + if (b > sizeof(buf) || b <= 0) { + FPGA_MSG("unexpected size on read from %s", file_path); + close(fd); + return FPGA_EXCEPTION; + } + + } while (buf[b-1] != '\n' && buf[b-1] != '\0' && b < sizeof(buf)); + + + // PR Inteface Id h + memset(buf_h, 0, sizeof(buf_h)); + + e = strncpy_s(buf_h, sizeof(buf_h), + buf, INTFC_ID_HIGH_LEN); + if (EOK != e) { + FPGA_MSG("strncpy_s failed (buf_h)"); + close(fd); + return FPGA_EXCEPTION; + } + + *id_h = strtoull(buf_h, NULL, 16); + + // PR Inteface Id l + memset(buf_l, 0, sizeof(buf_l)); + + e = strncpy_s(buf_l, sizeof(buf_l), + buf+INTFC_ID_LOW_LEN, INTFC_ID_LOW_LEN); + + if (EOK != e) { + FPGA_MSG("strncpy_s failed (buf_l)"); + close(fd); + return FPGA_EXCEPTION; + } + + *id_l = strtoull(buf_l, NULL, 16); + + close(fd); + + return FPGA_OK; +} + +fpga_result check_interface_id(fpga_handle handle, + uint32_t bitstream_magic_no, + uint64_t ifid_l, uint64_t ifid_h) +{ + uint64_t intfc_id_l = 0; + uint64_t intfc_id_h = 0; + fpga_result result = FPGA_OK; + + if (bitstream_magic_no != FPGA_GBS_6_3_0_MAGIC) { + FPGA_MSG("Invalid bitstream magic number"); + return FPGA_NOT_FOUND; + } + + if (get_interface_id(handle, &intfc_id_l, &intfc_id_h)) { + FPGA_MSG("Get interface ID failed"); + return FPGA_NOT_FOUND; + } + + if ((ifid_l != intfc_id_l) || + (ifid_h != intfc_id_h)) { + FPGA_MSG("Interface id doesn't match metadata"); + return FPGA_NOT_FOUND; + } + + return result; +} + +//TODO: this shouldn't be exported once all bistreams use JSON metadata format +fpga_result __FPGA_API__ check_bitstream_guid(const uint8_t *bitstream) +{ + fpga_guid bitstream_guid; + fpga_guid expected_guid; + fpga_result ret = FPGA_EXCEPTION; + errno_t e; + + e = memcpy_s(bitstream_guid, sizeof(bitstream_guid), + bitstream, sizeof(fpga_guid)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + return FPGA_EXCEPTION; + } + + if (string_to_guid(METADATA_GUID, &expected_guid) != FPGA_OK) + return FPGA_INVALID_PARAM; + + if (uuid_compare(bitstream_guid, expected_guid) != 0) + return FPGA_INVALID_PARAM; + + return FPGA_OK; +} + +int get_bitstream_header_len(const uint8_t *bitstream) +{ + uint32_t json_len = 0; + + if (check_bitstream_guid(bitstream) != FPGA_OK) + return -1; + + json_len = read_int_from_bitstream(bitstream + METADATA_GUID_LEN, sizeof(uint32_t)); + + return (METADATA_GUID_LEN + sizeof(uint32_t) + json_len); +} + +int32_t get_bitstream_json_len(const uint8_t *bitstream) +{ + uint32_t json_len = 0; + + if (check_bitstream_guid(bitstream) != FPGA_OK) + return -1; + + json_len = read_int_from_bitstream(bitstream + METADATA_GUID_LEN, sizeof(uint32_t)); + + return json_len; +} + +fpga_result validate_bitstream_metadata(fpga_handle handle, + const uint8_t *bitstream) +{ + fpga_result result = FPGA_EXCEPTION; + char *json_metadata = NULL; + uint32_t json_len = 0; + uint32_t bitstream_magic_no = 0; + uint64_t ifc_id_val_l, ifc_id_val_h; + const uint8_t *json_metadata_ptr = NULL; + json_object *root = NULL; + json_object *afu_image = NULL, *magic_no = NULL; + json_object *interface_id = NULL; + fpga_guid expected_guid; + errno_t e; + + if (check_bitstream_guid(bitstream) != FPGA_OK) + goto out_free; + + json_len = read_int_from_bitstream(bitstream + METADATA_GUID_LEN, sizeof(uint32_t)); + if (json_len == 0) { + FPGA_MSG("Bitstream has no metadata"); + result = FPGA_OK; + goto out_free; + } + + json_metadata_ptr = bitstream + METADATA_GUID_LEN + sizeof(uint32_t); + + json_metadata = (char *) malloc(json_len + 1); + if (json_metadata == NULL) { + FPGA_ERR("Could not allocate memory for metadata"); + return FPGA_NO_MEMORY; + } + + e = memcpy_s(json_metadata, json_len+1, + json_metadata_ptr, json_len); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + json_metadata[json_len] = '\0'; + + root = json_tokener_parse(json_metadata); + + if (root != NULL) { + if (get_json_object(&afu_image, &root, GBS_AFU_IMAGE)) { + get_json_object(&magic_no, &afu_image, GBS_MAGIC_NUM); + get_json_object(&interface_id, &afu_image, + BBS_INTERFACE_ID); + + if (magic_no == NULL || interface_id == NULL) { + FPGA_ERR("Invalid metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + + result = string_to_guid( + json_object_get_string(interface_id), + &expected_guid); + if (result != FPGA_OK) { + FPGA_ERR("Invalid BBS interface ID"); + goto out_free; + } + + e = memcpy_s(&ifc_id_val_h, sizeof(ifc_id_val_h), + expected_guid, sizeof(uint64_t)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + ifc_id_val_h = int64_be_to_le(ifc_id_val_h); + + e = memcpy_s(&ifc_id_val_l, sizeof(ifc_id_val_l), + expected_guid + sizeof(uint64_t), + sizeof(uint64_t)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + ifc_id_val_l = int64_be_to_le(ifc_id_val_l); + + bitstream_magic_no = json_object_get_int(magic_no); + + result = check_interface_id(handle, bitstream_magic_no, + ifc_id_val_l, ifc_id_val_h); + + if (result != FPGA_OK) { + FPGA_ERR("Interface ID check failed"); + goto out_free; + } + } else { + FPGA_ERR("Invalid metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + } + +out_free: + if (root) + json_object_put(root); + if (json_metadata) + free(json_metadata); + + return result; +} + +fpga_result read_gbs_metadata(const uint8_t *bitstream, + struct gbs_metadata *gbs_metadata) +{ + uint32_t json_len = 0; + fpga_result result = FPGA_OK; + const uint8_t *json_metadata_ptr = NULL; + char *json_metadata = NULL; + char *uuid_str = NULL; + json_object *root = NULL; + json_object *magic_num = NULL; + json_object *interface_id = NULL; + json_object *afu_image = NULL; + json_object *version = NULL; + json_object *accelerator_clusters = NULL; + json_object *cluster = NULL; + json_object *uuid = NULL; + json_object *name = NULL; + json_object *contexts = NULL; + json_object *power = NULL; + json_object *userclk1 = NULL; + json_object *userclk2 = NULL; + errno_t e; + + if (gbs_metadata == NULL) { + FPGA_ERR("Invalid input metadata"); + return FPGA_INVALID_PARAM; + } + + if (bitstream == NULL) { + FPGA_ERR("Invalid input bitstream"); + return FPGA_INVALID_PARAM; + } + + if (check_bitstream_guid(bitstream) != FPGA_OK) { + FPGA_ERR("Failed to read GUID"); + return FPGA_INVALID_PARAM; + } + + json_len = *((uint32_t *) (bitstream + METADATA_GUID_LEN)); + if (!json_len) { + FPGA_ERR("Bitstream has no metadata"); + return FPGA_INVALID_PARAM; + } + + json_metadata_ptr = bitstream + METADATA_GUID_LEN + sizeof(uint32_t); + + json_metadata = (char *) malloc(json_len + 1); + if (!json_metadata) { + FPGA_ERR("Could not allocate memory for metadata"); + return FPGA_NO_MEMORY; + } + + e = memcpy_s(json_metadata, json_len+1, + json_metadata_ptr, json_len); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + json_metadata[json_len] = '\0'; + + root = json_tokener_parse(json_metadata); + + if (root) { + + // GBS version + if (get_json_object(&version, &root, GBS_VERSION)) { + gbs_metadata->version = json_object_get_double(version); + } else { + FPGA_ERR("No GBS version"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + + // afu-image + if (get_json_object(&afu_image, &root, GBS_AFU_IMAGE)) { + + // magic number + if (get_json_object(&magic_num, &afu_image, GBS_MAGIC_NUM)) { + gbs_metadata->afu_image.magic_num = json_object_get_int64(magic_num); + } + + // Interface type GUID + if (get_json_object(&interface_id, &afu_image, BBS_INTERFACE_ID)) { + e = memcpy_s(gbs_metadata->afu_image.interface_uuid, + GUID_LEN, + json_object_get_string(interface_id), + GUID_LEN); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + gbs_metadata->afu_image.interface_uuid[GUID_LEN] = '\0'; + } else { + FPGA_ERR("No interface ID found in JSON metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + + // AFU user clock frequency High + if (get_json_object(&userclk1, &afu_image, GBS_CLOCK_FREQUENCY_HIGH)) { + gbs_metadata->afu_image.clock_frequency_high = json_object_get_int64(userclk1); + } + + // AFU user clock frequency Low + if (get_json_object(&userclk2, &afu_image, GBS_CLOCK_FREQUENCY_LOW)) { + gbs_metadata->afu_image.clock_frequency_low = json_object_get_int64(userclk2); + } + + // GBS power + if (get_json_object(&power, &afu_image, GBS_AFU_POWER)) { + gbs_metadata->afu_image.power = json_object_get_int64(power); + } + + } else { + FPGA_ERR("No AFU image in metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + + // afu clusters + if (get_json_object(&afu_image, &root, GBS_AFU_IMAGE) && + get_json_object(&accelerator_clusters, &afu_image, GBS_ACCELERATOR_CLUSTERS)) { + + cluster = json_object_array_get_idx(accelerator_clusters, 0); + + // AFU GUID + if (get_json_object(&uuid, &cluster, GBS_ACCELERATOR_TYPE_UUID)) { + e = memcpy_s(gbs_metadata->afu_image.afu_clusters.afu_uuid, + GUID_LEN, + json_object_get_string(uuid), + GUID_LEN); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + gbs_metadata->afu_image.afu_clusters.afu_uuid[GUID_LEN] = '\0'; + } else { + FPGA_ERR("No accelerator-type-uuid in JSON metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + + // AFU Name + if (get_json_object(&name, &cluster, GBS_AFU_NAME)) { + e = memcpy_s(gbs_metadata->afu_image.afu_clusters.name, + AFU_NAME_LEN, + json_object_get_string(name), + sizeof(json_object_get_string(name))); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + } + + // AFU Total number of contexts + if (get_json_object(&contexts, &cluster, GBS_ACCELERATOR_TOTAL_CONTEXTS)) { + gbs_metadata->afu_image.afu_clusters.total_contexts = json_object_get_int64(contexts); + } + + } else { + FPGA_ERR("No accelerator clusters in metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + } else { + FPGA_ERR("Invalid JSON in metadata"); + result = FPGA_INVALID_PARAM; + goto out_free; + } + +out_free: + if (root) + json_object_put(root); + if (json_metadata) + free(json_metadata); + + return result; +} diff --git a/libopae/src/bitstream_int.h b/libopae/src/bitstream_int.h new file mode 100644 index 000000000000..0ddc77c5720b --- /dev/null +++ b/libopae/src/bitstream_int.h @@ -0,0 +1,149 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_BITSTREAM_INT_H__ +#define __FPGA_BITSTREAM_INT_H__ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#define GUID_LEN 36 +#define AFU_NAME_LEN 512 + +// GBS Metadata format /json +struct gbs_metadata { + + double version; // version + + struct afu_image_content { + uint64_t magic_num; // Magic number + char interface_uuid[GUID_LEN + 1]; // Interface id + int clock_frequency_high; // user clock frequency hi + int clock_frequency_low; // user clock frequency low + int power; // power + + struct afu_clusters_content { + char name[AFU_NAME_LEN]; // AFU Name + int total_contexts; // total contexts + char afu_uuid[GUID_LEN + 1]; // afu guid + } afu_clusters; + + } afu_image; + +}; + +/** + * Check the validity of GUID + * + *Extracts the 128 bit guid from passed bitstream + *converts it to fpga_guid type anc checks it against + *expected value + * + * + * @param[in] bitstream Pointer to the bitstream + * @returns FPGA_OK on success + */ +fpga_result check_bitstream_guid(const uint8_t *bitstream); + +/** + * Get total length of bitstream header + * + * Returns the total length of header which is + * GUID + size of variable describing length of metadata + length of metadata + * + * + * @param[in] bitstream Pointer to the bitstream + * @returns int value of length, -1 on failure + */ +int get_bitstream_header_len(const uint8_t *bitstream); + +/** + * Get total length of json metadata in bitstream + * + * Returns the length of the json metadata from the + * bitstream which is represented by a uint32 after the + * GUID + * + * + * @param[in] bitstream Pointer to the bitstream + * @returns int value of length, -1 on failure + */ +int32_t get_bitstream_json_len(const uint8_t *bitstream); + + +/** + * Check bitstream magic no and interface id + * + * Checks the bitstream magic no and interface id + * with expected values + * + * @param[in] handle Handle to previously opened FPGA object + * @param[in] bitstream_magic_no magic no. to be checked + * @param[in] ifid_l lower 64 bits of interface id + * @param[in] ifid_h higher 64 bits of interface id + * @returns FPGA_OK on success + */ +fpga_result check_interface_id(fpga_handle handle, uint32_t bitstream_magic_no, + uint64_t ifid_l, uint64_t ifid_h); + +/** + * Check if the JSON metadata is valid + * + * Reads the bitstream magic no and interface + * id values from the metadata and compares them + * with expected values + * + * @param[in] handle Handle to previously opened FPGA object + * @param[in] bitstream Pointer to the bitstream + * @returns FPGA_OK on success + */ +fpga_result validate_bitstream_metadata(fpga_handle handle, + const uint8_t *bitstream); + +/** + * Reads GBS metadata + * + * Parses GBS JSON metadata. + * + * @param[in] bitstream Pointer to the bitstream + * @param[in] gbs_metadata Pointer to gbs metadata struct + * @returns FPGA_OK on success + */ +fpga_result read_gbs_metadata(const uint8_t *bitstream, + struct gbs_metadata *gbs_metadata); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __FPGA_BITSTREAM_INT_H__ diff --git a/libopae/src/buffer.c b/libopae/src/buffer.c new file mode 100644 index 000000000000..7f5ba3301cc9 --- /dev/null +++ b/libopae/src/buffer.c @@ -0,0 +1,359 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "opae/access.h" +#include "opae/utils.h" +#include "common_int.h" +#include "intel-fpga.h" + +#include +#include +#include +#include +#include +#include +#include + +/* Others */ +#define KB 1024 +#define MB (1024 * KB) +#define GB (1024UL * MB) + +#define PROTECTION (PROT_READ | PROT_WRITE) + +#ifndef MAP_HUGETLB +#define MAP_HUGETLB 0x40000 +#endif +#ifndef MAP_HUGE_SHIFT +#define MAP_HUGE_SHIFT 26 +#endif + +#define MAP_1G_HUGEPAGE (0x1e << MAP_HUGE_SHIFT) /* 2 ^ 0x1e = 1G */ + +#ifdef __ia64__ +#define ADDR (void *)(0x8000000000000000UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#else +#define ADDR (void *)(0x0UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#endif + + +/* + * Allocate (mmap) new buffer + */ +static fpga_result buffer_allocate(void **addr, uint64_t len, int flags) +{ + void *addr_local = NULL; + + ASSERT_NOT_NULL(addr); + + /* ! FPGA_BUF_PREALLOCATED, allocate memory using huge pages + For buffer > 2M, use 1G-hugepage to ensure pages are + contiguous */ + if (len > 2 * MB) + addr_local = mmap(ADDR, len, PROTECTION, FLAGS_1G, 0, 0); + else if (len > 4 * KB) + addr_local = mmap(ADDR, len, PROTECTION, FLAGS_2M, 0, 0); + else + addr_local = mmap(ADDR, len, PROTECTION, FLAGS_4K, 0, 0); + if (addr_local == MAP_FAILED) { + if (errno == ENOMEM) { + if (len > 2 * MB) + FPGA_MSG("Could not allocate buffer (no free 1 " + "GiB huge pages)"); + if (len > 4 * KB) + FPGA_MSG("Could not allocate buffer (no free 2 " + "MiB huge pages)"); + else + FPGA_MSG("Could not allocate buffer (out of " + "memory)"); + return FPGA_NO_MEMORY; + } + FPGA_MSG("FPGA buffer mmap failed: %s", strerror(errno)); + return FPGA_INVALID_PARAM; + } + + *addr = addr_local; + return FPGA_OK; +} + +/* + * Release (unmap) allocated buffer + */ +static fpga_result buffer_release(void *addr, uint64_t len) +{ + /* If the buffer allocation was backed by hugepages, then + * len must be rounded up to the nearest hugepage size, + * otherwise munmap will fail. + * + * Buffer with size larger than 2MB is backed by 1GB page(s), + * round up the size to the nearest GB boundary. + * + * Buffer with size smaller than 2MB but larger than 4KB is + * backed by a 2MB pages, round up the size to 2MB. + * + * Buffer with size smaller than 4KB is backed by a 4KB page, + * and its size is already 4KB aligned. + */ + + if (len > 2 * MB) + len = (len + (1 * GB - 1)) & (~(1 * GB - 1)); + else if (len > 4 * KB) + len = 2 * MB; + + if (munmap(addr, len)) { + FPGA_MSG("FPGA buffer munmap failed: %s", + strerror(errno)); + return FPGA_INVALID_PARAM; + } + + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaPrepareBuffer(fpga_handle handle, uint64_t len, + void **buf_addr, uint64_t *wsid, + int flags) +{ + void *addr = NULL; + fpga_result result = FPGA_OK; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + + bool preallocated = (flags & FPGA_BUF_PREALLOCATED); + bool quiet = (flags & FPGA_BUF_QUIET); + + uint64_t pg_size; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Assure wsid is a valid pointer */ + if (!wsid) { + FPGA_MSG("WSID is NULL"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + if (flags & (~(FPGA_BUF_PREALLOCATED | FPGA_BUF_QUIET))) { + FPGA_MSG("Unrecognized flags"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + pg_size = (uint64_t) sysconf(_SC_PAGE_SIZE); + + if (preallocated) { + /* A special case: respond FPGA_OK when !buf_addr and !len + * as an indication that FPGA_BUF_PREALLOCATED is supported + * by the library. */ + if (!buf_addr && !len) { + result = FPGA_OK; + goto out_unlock; + } + + /* buffer is already allocated, check addresses */ + if (!buf_addr) { + FPGA_MSG("No preallocated buffer address given"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + if (!(*buf_addr)) { + FPGA_MSG("Preallocated buffer address is NULL"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + /* check length */ + if (!len || (len & (pg_size - 1))) { + FPGA_MSG("Preallocated buffer size is not a non-zero multiple of page size"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + addr = *buf_addr; + } else { + /* round up to nearest page boundary */ + if (!len || (len & (pg_size - 1))) { + len = pg_size + (len & ~(pg_size - 1)); + } + result = buffer_allocate(&addr, len, flags); + if (result != FPGA_OK) { + goto out_unlock; + } + } + + /* Set ioctl fpga_port_dma_map struct parameters */ + struct fpga_port_dma_map dma_map = {.argsz = sizeof(dma_map), + .flags = 0, + .user_addr = (__u64) addr, + .length = (__u64) len, + .iova = 0}; + + /* Dispatch ioctl command */ + if (ioctl(_handle->fddev, FPGA_PORT_DMA_MAP, &dma_map) != 0) { + if (!preallocated) { + buffer_release(addr, len); + } + + if (!quiet) { + FPGA_MSG("FPGA_PORT_DMA_MAP ioctl failed: %s", + strerror(errno)); + } + + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + /* Generate unique workspace ID */ + *wsid = wsid_gen(); + + /* Add to workspace id in order to store buffer length */ + if (!wsid_add(&_handle->wsid_root, + *wsid, + dma_map.user_addr, + dma_map.iova, + len, + 0, + 0, + flags)) { + if (!preallocated) { + buffer_release(addr, len); + } + + FPGA_MSG("Failed to add workspace id %lu", *wsid); + result = FPGA_NO_MEMORY; + goto out_unlock; + } + + /* Update buf_addr */ + if (buf_addr) + *buf_addr = addr; + + /* Return */ + result = FPGA_OK; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaReleaseBuffer(fpga_handle handle, uint64_t wsid) +{ + void *buf_addr; + uint64_t iova; + uint64_t len; + + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_NOT_FOUND; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Fetch the buffer physical address and length */ + struct wsid_map *wm = wsid_find(_handle->wsid_root, wsid); + if (!wm) { + FPGA_MSG("WSID not found"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + buf_addr = (void *) wm->addr; + iova = wm->phys; + len = wm->len; + + bool preallocated = (wm->flags & FPGA_BUF_PREALLOCATED); + + /* Set ioctl fpga_port_dma_unmap struct parameters */ + struct fpga_port_dma_unmap dma_unmap = {.argsz = sizeof(dma_unmap), + .flags = 0, + .iova = iova}; + + /* Dispatch ioctl command */ + if (ioctl(_handle->fddev, FPGA_PORT_DMA_UNMAP, &dma_unmap) != 0) { + if (!preallocated) { + buffer_release(buf_addr, len); + } + + FPGA_MSG("FPGA_PORT_DMA_UNMAP ioctl failed: %s", + strerror(errno)); + result = FPGA_INVALID_PARAM; + goto ws_free; + } + + /* If the buffer was allocated in fpgaPrepareBuffer() (i.e. it was not + * preallocated), we need to unmap it here. Otherwise (if it was + * preallocated) the mapping needs to stay intact. */ + if (!preallocated) { + result = buffer_release(buf_addr, len); + if (result != FPGA_OK) { + FPGA_MSG("Buffer release failed"); + goto ws_free; + } + } + + /* Return */ + result = FPGA_OK; + +ws_free: + /* Remove workspace */ + wsid_del(&_handle->wsid_root, wsid); + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaGetIOAddress(fpga_handle handle, uint64_t wsid, + uint64_t *ioaddr) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct wsid_map *wm; + fpga_result result = FPGA_OK; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + wm = wsid_find(_handle->wsid_root, wsid); + if (!wm) { + FPGA_MSG("WSID not found"); + result = FPGA_NOT_FOUND; + } else { + *ioaddr = wm->phys; + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} diff --git a/libopae/src/close.c b/libopae/src/close.c new file mode 100644 index 000000000000..201204daab29 --- /dev/null +++ b/libopae/src/close.c @@ -0,0 +1,68 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include "common_int.h" + +#include +#include +#include + +fpga_result __FPGA_API__ fpgaClose(fpga_handle handle) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (-1 == _handle->fddev) { + FPGA_ERR("Invalid handle file descriptor"); + pthread_mutex_unlock(&_handle->lock); + return FPGA_INVALID_PARAM; + } + + wsid_cleanup(&_handle->wsid_root); + free_umsg_buffer(handle); + close(_handle->fddev); + if (_handle->fdfpgad >= 0) + close(_handle->fdfpgad); + + // invalidate magic (just in case) + _handle->magic = FPGA_INVALID_MAGIC; + + pthread_mutex_unlock(&_handle->lock); + pthread_mutex_destroy(&_handle->lock); + + free(_handle); + + return FPGA_OK; +} diff --git a/libopae/src/common.c b/libopae/src/common.c new file mode 100644 index 000000000000..8378c7ed6ca9 --- /dev/null +++ b/libopae/src/common.c @@ -0,0 +1,181 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "common_int.h" + +#include +#include +#include +#include + +// Buffer Allocation constants +#define KB 1024 +#define MB (1024 * KB) +#define GB (1024 * MB) + +#ifndef MAP_HUGETLB +#define MAP_HUGETLB 0x40000 +#endif +#ifndef MAP_HUGE_SHIFT +#define MAP_HUGE_SHIFT 26 +#endif +#define MAP_1G_HUGEPAGE (0x1e << MAP_HUGE_SHIFT) + +#define PROTECTION (PROT_READ | PROT_WRITE) + +#ifdef __ia64__ +#define ADDR (void *)(0x8000000000000000UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#else +#define ADDR (void *)(0x0UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#endif + + +/* + * Check properties object for validity and lock its mutex + * If prop_check_and_lock() returns FPGA_OK, assume the mutex to be locked. + */ +fpga_result prop_check_and_lock(struct _fpga_properties *prop) +{ + ASSERT_NOT_NULL(prop); + + if (pthread_mutex_lock(&prop->lock)) { + FPGA_MSG("Failed to lock mutex"); + return FPGA_EXCEPTION; + } + + if (prop->magic != FPGA_PROPERTY_MAGIC) { + FPGA_MSG("Invalid properties object"); + pthread_mutex_unlock(&prop->lock); + return FPGA_INVALID_PARAM; + } + + return FPGA_OK; +} + +/* + * Check handle object for validity and lock its mutex + * If handle_check_and_lock() returns FPGA_OK, assume the mutex to be locked. + */ +fpga_result handle_check_and_lock(struct _fpga_handle *handle) +{ + ASSERT_NOT_NULL(handle); + + if (pthread_mutex_lock(&handle->lock)) { + FPGA_MSG("Failed to lock mutex"); + return FPGA_EXCEPTION; + } + + if (handle->magic != FPGA_HANDLE_MAGIC) { + FPGA_MSG("Invalid handle object"); + pthread_mutex_unlock(&handle->lock); + return FPGA_INVALID_PARAM; + } + + return FPGA_OK; +} + +/* mutex to protect global data structures */ +pthread_mutex_t global_lock = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP; + +const char __FPGA_API__ *fpgaErrStr(fpga_result e) +{ + switch (e) { + case FPGA_OK: + return "success"; + case FPGA_INVALID_PARAM: + return "invalid parameter"; + case FPGA_BUSY: + return "resource busy"; + case FPGA_EXCEPTION: + return "exception"; + case FPGA_NOT_FOUND: + return "not found"; + case FPGA_NO_MEMORY: + return "no memory"; + case FPGA_NOT_SUPPORTED: + return "not supported"; + case FPGA_NO_DRIVER: + return "no driver available"; + case FPGA_NO_DAEMON: + return "no fpga daemon running"; + case FPGA_NO_ACCESS: + return "insufficient privileges"; + default: + return "unknown error"; + } +} + +/** + * @brief Generate unique workspace ID number + * + * @return id identifier + */ +uint64_t wsid_gen(void) +{ + struct timeval t; + uint64_t id = 0; + gettimeofday(&t, NULL); + id = ((t.tv_sec * 1000 * 1000) + (t.tv_usec * 1000)) << 42; + id |= ((unsigned long) getpid() % 16777216) << 24; + return id; +} + +/** + * @brief + * + * @param guidh + * @param guidl + * @param guid + */ +void aal_guid_to_fpga(uint64_t guidh, uint64_t guidl, uint8_t *guid) +{ + uint32_t i; + uint32_t s; + + // The API expects the MSB of the GUID at [0] and the LSB at [15]. + s = 64; + for (i = 0; i < 8; ++i) { + s -= 8; + guid[i] = (uint8_t) ((guidh >> s) & 0xff); + } + + s = 64; + for (i = 0; i < 8; ++i) { + s -= 8; + guid[8 + i] = (uint8_t) ((guidl >> s) & 0xff); + } +} + diff --git a/libopae/src/common_int.h b/libopae/src/common_int.h new file mode 100644 index 000000000000..201492f2d4ea --- /dev/null +++ b/libopae/src/common_int.h @@ -0,0 +1,88 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_COMMON_INT_H__ +#define __FPGA_COMMON_INT_H__ + +#define _GNU_SOURCE +#include +#include +#include /* bool type */ +#include /* malloc */ +#include /* exit */ +#include /* printf */ +#include /* memcpy */ +#include /* getpid */ +#include /* pid_t */ +#include /* ioctl */ +#include /* mmap & munmap */ +#include /* struct timeval */ +#include +#undef _GNU_SOURCE + +#include "opae/utils.h" +#include "types_int.h" +#include "log_int.h" +#include "sysfs_int.h" +#include "wsid_list_int.h" +#include "token_list_int.h" +#include "mmap_int.h" + +/* Macro for defining symbol visibility */ +#define __FPGA_API__ __attribute__((visibility("default"))) +#define __FIXME_MAKE_VISIBLE__ __attribute__((visibility("default"))) + +/* + * Check if argument is NULL and return FPGA_INVALID_PARAM and a message + */ +#define ASSERT_NOT_NULL_MSG(arg, msg) \ + do { \ + if (!arg) { \ + FPGA_MSG(msg); \ + return FPGA_INVALID_PARAM; \ + } \ + } while (0); + +#define ASSERT_NOT_NULL(arg) \ + ASSERT_NOT_NULL_MSG(arg, #arg " is NULL") + + +/* Check validity of various objects */ +fpga_result prop_check_and_lock(struct _fpga_properties *prop); +fpga_result handle_check_and_lock(struct _fpga_handle *handle); + +/** + * @brief + * + * @param guidh + * @param guidl + * @param guid + */ +void aal_guid_to_fpga(uint64_t guidh, + uint64_t guidl, + uint8_t *guid); + +#endif // ___FPGA_COMMON_INT_H__ diff --git a/libopae/src/enum.c b/libopae/src/enum.c new file mode 100644 index 000000000000..21136c9fb51b --- /dev/null +++ b/libopae/src/enum.c @@ -0,0 +1,733 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "safe_string/safe_string.h" + +#include "common_int.h" +#include "opae/enum.h" +#include "opae/properties.h" +#include "opae/utils.h" +#include "properties_int.h" +#include +#include +#include + +#include +#include +#include +#include +#include + +/* mutex to protect global data structures */ +extern pthread_mutex_t global_lock; + +struct dev_list { + char sysfspath[SYSFS_PATH_MAX]; + char devpath[DEV_PATH_MAX]; + fpga_objtype objtype; + fpga_guid guid; + uint8_t bus; + uint8_t device; + uint8_t function; + uint8_t socket_id; + + uint32_t fpga_num_slots; + uint64_t fpga_bitstream_id; + fpga_version fpga_bbs_version; + + fpga_accelerator_state accelerator_state; + uint32_t accelerator_num_mmios; + uint32_t accelerator_num_irqs; + struct dev_list *next; + struct dev_list *parent; + struct dev_list *fme; +}; + +static bool +matches_filter(const struct dev_list *attr, const fpga_properties filter) +{ + struct _fpga_properties *_filter = (struct _fpga_properties *)filter; + bool res = true; + + pthread_mutex_lock(&_filter->lock); + + if (FIELD_VALID(_filter, FPGA_PROPERTY_PARENT)) { + struct _fpga_token *_tok = + (struct _fpga_token *) _filter->parent; + char spath[SYSFS_PATH_MAX]; + char *p; + int device_id; + + if (FPGA_ACCELERATOR != attr->objtype) { + res = false; // Only accelerator can have a parent + goto out_unlock; + } + + if (NULL == _tok) { + res = false; // Reject search based on NULL parent token + goto out_unlock; + } + + p = strrchr(attr->sysfspath, '.'); + + if (NULL == p) { + res = false; + goto out_unlock; + } + + device_id = (int) strtoul(p+1, NULL, 10); + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_FME_PATH_FMT, + device_id, device_id); + + if (strcmp(spath, ((struct _fpga_token *) + _filter->parent)->sysfspath)) { + res = false; + goto out_unlock; + } + + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_OBJTYPE)) { + if (_filter->objtype != attr->objtype) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_BUS)) { + if (_filter->bus != attr->bus) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_DEVICE)) { + if (_filter->device != attr->device) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_FUNCTION)) { + if (_filter->function != attr->function) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_SOCKETID)) { + if (_filter->socket_id != attr->socket_id) { + res = false; + goto out_unlock; + } + } + + // FIXME + // if (FIELD_VALID(_filter, FPGA_PROPERTY_DEVICEID)) { + // + // } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_GUID)) { + if (0 != memcmp(attr->guid, _filter->guid, sizeof(fpga_guid))) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_OBJTYPE) && + (FPGA_DEVICE == _filter->objtype)) { + + if (FIELD_VALID(_filter, FPGA_PROPERTY_NUM_SLOTS)) { + if ((FPGA_DEVICE != attr->objtype) || + (attr->fpga_num_slots != + _filter->u.fpga.num_slots)) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_BBSID)) { + if ((FPGA_DEVICE != attr->objtype) || + (attr->fpga_bitstream_id != + _filter->u.fpga.bbs_id)) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_BBSVERSION)) { + if ((FPGA_DEVICE != attr->objtype) || + (attr->fpga_bbs_version.major != + _filter->u.fpga.bbs_version.major) || + (attr->fpga_bbs_version.minor != + _filter->u.fpga.bbs_version.minor) || + (attr->fpga_bbs_version.patch != + _filter->u.fpga.bbs_version.patch)) { + res = false; + goto out_unlock; + } + } + + // FIXME + // if (FIELD_VALID(_filter, FPGA_PROPERTY_VENDORID)) { + // if (FPGA_DEVICE != attr->objtype) + // return false; + // + // } + + // FIXME + // if (FIELD_VALID(_filter, FPGA_PROPERTY_MODEL)) { + // if (FPGA_DEVICE != attr->objtype) + // return false; + // + // } + + // FIXME + // if (FIELD_VALID(_filter, FPGA_PROPERTY_LOCAL_MEMORY)) { + // if (FPGA_DEVICE != attr->objtype) + // return false; + // + // } + + // FIXME + // if (FIELD_VALID(_filter, FPGA_PROPERTY_CAPABILITIES)) { + // if (FPGA_DEVICE != attr->objtype) + // return false; + // + // } + + } else if (FIELD_VALID(_filter, FPGA_PROPERTY_OBJTYPE) && + (FPGA_ACCELERATOR == _filter->objtype)) { + + if (FIELD_VALID(_filter, FPGA_PROPERTY_ACCELERATOR_STATE)) { + if ((FPGA_ACCELERATOR != attr->objtype) || + (attr->accelerator_state != _filter->u.accelerator.state)) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_NUM_MMIO)) { + if ((FPGA_ACCELERATOR != attr->objtype) || + (attr->accelerator_num_mmios != _filter->u.accelerator.num_mmio)) { + res = false; + goto out_unlock; + } + } + + if (FIELD_VALID(_filter, FPGA_PROPERTY_NUM_INTERRUPTS)) { + if ((FPGA_ACCELERATOR != attr->objtype) || + (attr->accelerator_num_irqs != + _filter->u.accelerator.num_interrupts)) { + res = false; + goto out_unlock; + } + } + + } + +out_unlock: + pthread_mutex_unlock(&_filter->lock); + return res; +} + +static bool +matches_filters(const struct dev_list *attr, + const fpga_properties *filter, uint32_t num_filter) +{ + uint32_t i; + + if (!num_filter) // no filter == match everything + return true; + + for (i = 0; i < num_filter; ++i) { + if (matches_filter(attr, filter[i])) { + return true; + } + } + return false; +} + +static struct dev_list * +add_dev(const char *sysfspath, const char *devpath, struct dev_list *parent) +{ + struct dev_list *pdev; + errno_t e; + + pdev = (struct dev_list *) malloc(sizeof(*pdev)); + if (NULL == pdev) + return NULL; + + e = strncpy_s(pdev->sysfspath, sizeof(pdev->sysfspath), + sysfspath, SYSFS_PATH_MAX); + if (EOK != e) + goto out_free; + + e = strncpy_s(pdev->devpath, sizeof(pdev->devpath), + devpath, DEV_PATH_MAX); + if (EOK != e) + goto out_free; + + pdev->next = parent->next; + parent->next = pdev; + + pdev->parent = parent; + + return pdev; + +out_free: + free(pdev); + return NULL; +} + +static const fpga_guid FPGA_FME_GUID = { + 0xbf, 0xaf, 0x2a, 0xe9, 0x4a, 0x52, 0x46, 0xe3, + 0x82, 0xfe, 0x38, 0xf0, 0xf9, 0xe1, 0x77, 0x64 +}; + +static fpga_result +enum_fme_afu(const char *sysfspath, const char *name, struct dev_list *parent) +{ + fpga_result result; + struct stat stats; + struct dev_list *pdev; + char spath[SYSFS_PATH_MAX]; + char dpath[DEV_PATH_MAX]; + + // Make sure it's a directory. + if (stat(sysfspath, &stats) != 0) { + FPGA_MSG("stat failed: %s", strerror(errno)); + return FPGA_NOT_FOUND; + } + + if (!S_ISDIR(stats.st_mode)) + return FPGA_OK; + + if (strstr(name, FPGA_SYSFS_FME)) { + int socket_id = 0; + + snprintf(dpath, sizeof(dpath), FPGA_DEV_PATH "/%s", name); + + pdev = add_dev(sysfspath, dpath, parent); + if (!pdev) { + FPGA_MSG("Failed to allocate device"); + return FPGA_NO_MEMORY; + } + + pdev->objtype = FPGA_DEVICE; + + pdev->bus = parent->bus; + pdev->device = parent->device; + pdev->function = parent->function; + +// Hard-coding the FME guid for now. Leave the below code in case this changes. + + //memcpy(pdev->guid, FPGA_FME_GUID, sizeof(fpga_guid)); + // populate from pr/interface_id + + // Discover the FME GUID from sysfs (pr/interface_id) + snprintf(spath, sizeof(spath), "%s/" + FPGA_SYSFS_FME_INTERFACE_ID, sysfspath); + + result = sysfs_read_guid(spath, pdev->guid); + if (FPGA_OK != result) + return result; + + // Discover the socket id from the FME's sysfs entry. + snprintf(spath, sizeof(spath), "%s/" + FPGA_SYSFS_SOCKET_ID, sysfspath); + + result = sysfs_read_int(spath, &socket_id); + if (FPGA_OK != result) + return result; + + snprintf(spath, sizeof(spath), "%s/" + FPGA_SYSFS_NUM_SLOTS, sysfspath); + result = sysfs_read_u32(spath, &pdev->fpga_num_slots); + if (FPGA_OK != result) + return result; + + snprintf(spath, sizeof(spath), "%s/" + FPGA_SYSFS_BITSTREAM_ID, sysfspath); + result = sysfs_read_u64(spath, &pdev->fpga_bitstream_id); + if (FPGA_OK != result) + return result; + + pdev->fpga_bbs_version.major = + FPGA_BBS_VER_MAJOR(pdev->fpga_bitstream_id); + pdev->fpga_bbs_version.minor = + FPGA_BBS_VER_MINOR(pdev->fpga_bitstream_id); + pdev->fpga_bbs_version.patch = + FPGA_BBS_VER_PATCH(pdev->fpga_bitstream_id); + + parent->socket_id = socket_id; + parent->fme = pdev; + } + + if (strstr(name, FPGA_SYSFS_AFU)) { + int res; + + snprintf(dpath, sizeof(dpath), FPGA_DEV_PATH "/%s", name); + + pdev = add_dev(sysfspath, dpath, parent); + if (!pdev) { + FPGA_MSG("Failed to allocate device"); + return FPGA_NO_MEMORY; + } + + pdev->objtype = FPGA_ACCELERATOR; + + pdev->bus = parent->bus; + pdev->device = parent->device; + pdev->function = parent->function; + + res = open(pdev->devpath, O_RDWR); + if (-1 == res) { + pdev->accelerator_state = FPGA_ACCELERATOR_ASSIGNED; + } else { + close(res); + pdev->accelerator_state = FPGA_ACCELERATOR_UNASSIGNED; + } + + // FIXME: not to rely on hard-coded constants. + pdev->accelerator_num_mmios = 2; + pdev->accelerator_num_irqs = 0; + + // Discover the AFU GUID from sysfs. + snprintf(spath, sizeof(spath), "%s/" FPGA_SYSFS_AFU_GUID, + sysfspath); + + result = sysfs_read_guid(spath, pdev->guid); + if (FPGA_OK != result) + return result; + + } + + return FPGA_OK; +} + +static fpga_result +enum_top_dev(const char *sysfspath, const char *name, struct dev_list *list) +{ + fpga_result result = FPGA_NOT_FOUND; + struct stat stats; + + struct dev_list *pdev; + + DIR *dir; + struct dirent *dirent; + char spath[SYSFS_PATH_MAX]; + int res; + char *p; + int f; + unsigned b, d; + + // Make sure it's a directory. + if (stat(sysfspath, &stats) != 0) { + FPGA_MSG("stat failed: %s", strerror(errno)); + return FPGA_NO_DRIVER; + } + + if (!S_ISDIR(stats.st_mode)) + return FPGA_OK; + + res = readlink(sysfspath, spath, sizeof(spath)); + if (-1 == res) { + FPGA_MSG("Can't read link"); + return FPGA_NO_DRIVER; + } + + pdev = add_dev(sysfspath, "", list); + if (!pdev) { + FPGA_MSG("Failed to allocate device"); + return FPGA_NO_MEMORY; + } + + // Find the BDF from the link path. + spath[res] = 0; + p = strrchr(spath, '/'); + if (!p) { + FPGA_MSG("Invalid link"); + return FPGA_NO_DRIVER; + } + *p = 0; + p = strrchr(spath, '/'); + if (!p) { + FPGA_MSG("Invalid link"); + return FPGA_NO_DRIVER; + } + *p = 0; + p = strrchr(spath, '/'); + if (!p) { + FPGA_MSG("Invalid link"); + return FPGA_NO_DRIVER; + } + p += 6; + + // 0123456 + // bb:dd.f + f = 0; + sscanf(p+6, "%d", &f); + + pdev->function = (uint8_t) f; + *(p + 5) = 0; + + d = 0; + sscanf(p+3, "%x", &d); + + pdev->device = (uint8_t) d; + *(p + 2) = 0; + + b = 0; + sscanf(p, "%x", &b); + + pdev->bus = (uint8_t) b; + + // Find the FME and AFU devices. + dir = opendir(sysfspath); + if (NULL == dir) { + FPGA_MSG("Can't open directory"); + return FPGA_NO_DRIVER; + } + + while ((dirent = readdir(dir)) != NULL) { + if (!strcmp(dirent->d_name, ".")) + continue; + if (!strcmp(dirent->d_name, "..")) + continue; + + snprintf(spath, sizeof(spath), "%s/%s", sysfspath, + dirent->d_name); + + result = enum_fme_afu(spath, dirent->d_name, pdev); + if (result != FPGA_OK) + break; + } + + closedir(dir); + + return result; +} + + +fpga_result __FPGA_API__ +fpgaEnumerate(const fpga_properties *filters, uint32_t num_filters, + fpga_token *tokens, uint32_t max_tokens, uint32_t *num_matches) +{ + fpga_result result = FPGA_NOT_FOUND; + + DIR *dir = NULL; + struct dirent *dirent = NULL; + char sysfspath[SYSFS_PATH_MAX]; + struct dev_list head; + struct dev_list *lptr; + + if (NULL == num_matches) { + FPGA_MSG("num_matches is NULL"); + return FPGA_INVALID_PARAM; + } + + /* requiring a max number of tokens, but not providing a pointer to + * return them through is invalid */ + if ((max_tokens > 0) && (NULL == tokens)) { + FPGA_MSG("max_tokens > 0 with NULL tokens"); + return FPGA_INVALID_PARAM; + } + + if ((num_filters > 0) && (NULL == filters)) { + FPGA_MSG("num_filters > 0 with NULL filters"); + return FPGA_INVALID_PARAM; + } + + *num_matches = 0; + + memset(&head, 0, sizeof(head)); + + // Find the top-level FPGA devices. + dir = opendir(SYSFS_FPGA_CLASS_PATH); + if (NULL == dir) { + FPGA_MSG("can't find %s (no driver?)", SYSFS_FPGA_CLASS_PATH); + return FPGA_NO_DRIVER; + } + + while ((dirent = readdir(dir)) != NULL) { + if (!strcmp(dirent->d_name, ".")) + continue; + if (!strcmp(dirent->d_name, "..")) + continue; + + snprintf(sysfspath, sizeof(sysfspath), "%s/%s", + SYSFS_FPGA_CLASS_PATH, dirent->d_name); + + result = enum_top_dev(sysfspath, dirent->d_name, &head); + if (result != FPGA_OK) + break; + } + + closedir(dir); + + if (result != FPGA_OK) { + FPGA_MSG("No FPGA resources found"); + return result; + } + + /* create and populate token data structures */ + for (lptr = head.next ; NULL != lptr ; lptr = lptr->next) { + struct _fpga_token *_tok; + + if (!strlen(lptr->devpath)) + continue; + + // propagate the socket_id field. + lptr->socket_id = lptr->parent->socket_id; + lptr->fme = lptr->parent->fme; + + /* FIXME: do we need to keep a global list of tokens? */ + /* For now we do becaue it is used in fpgaUpdateProperties + * to lookup a parent from the global list of tokens...*/ + _tok = token_add(lptr->sysfspath, + lptr->devpath); + + if (NULL == _tok) { + FPGA_MSG("Failed to allocate memory for token"); + result = FPGA_NO_MEMORY; + goto out_free_trash; + } + + // FIXME: should check contents of filter for token magic + if (matches_filters(lptr, filters, num_filters)) { + if (*num_matches < max_tokens) { + if (fpgaCloneToken(_tok, &tokens[*num_matches]) + != FPGA_OK) { + // FIXME: should we error out here? + FPGA_MSG("Error cloning token"); + } + } + ++(*num_matches); + } + } + +out_free_trash: + /* FIXME: should this live in a separate function? */ + for (lptr = head.next ; NULL != lptr;) { + struct dev_list *trash = lptr; + lptr = lptr->next; + free(trash); + } + + return result; +} + +fpga_result __FPGA_API__ fpgaCloneToken(fpga_token src, + fpga_token *dst) +{ + struct _fpga_token *_src = (struct _fpga_token *)src; + struct _fpga_token *_dst; + fpga_result result; + errno_t e; + + if (NULL == src || NULL == dst) { + FPGA_MSG("src or dst in NULL"); + return FPGA_INVALID_PARAM; + } + + if (_src->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid src"); + return FPGA_INVALID_PARAM; + } + + _dst = malloc(sizeof(struct _fpga_token)); + if (NULL == _dst) { + FPGA_MSG("Failed to allocate memory for token"); + return FPGA_NO_MEMORY; + } + + _dst->magic = FPGA_TOKEN_MAGIC; + + e = strncpy_s(_dst->sysfspath, sizeof(_dst->sysfspath), + _src->sysfspath, sizeof(_src->sysfspath)); + if (EOK != e) { + FPGA_MSG("strncpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + + e = strncpy_s(_dst->devpath, sizeof(_dst->devpath), + _src->devpath, sizeof(_src->devpath)); + if (EOK != e) { + FPGA_MSG("strncpy_s failed"); + result = FPGA_EXCEPTION; + goto out_free; + } + + *dst = _dst; + return FPGA_OK; + +out_free: + free(_dst); + return result; +} + +fpga_result __FPGA_API__ fpgaDestroyToken(fpga_token *token) +{ + fpga_result result = FPGA_OK; + + if (NULL == token || NULL == *token) { + FPGA_MSG("Invalid token pointer"); + return FPGA_INVALID_PARAM; + } + + struct _fpga_token *_token = (struct _fpga_token *)*token; + + if (pthread_mutex_lock(&global_lock)) { + FPGA_MSG("Failed to lock global mutex"); + return FPGA_EXCEPTION; + } + + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // invalidate magic (just in case) + _token->magic = FPGA_INVALID_MAGIC; + + free(*token); + *token = NULL; + +out_unlock: + pthread_mutex_unlock(&global_lock); + return result; +} + diff --git a/libopae/src/event.c b/libopae/src/event.c new file mode 100644 index 000000000000..549890ec4d37 --- /dev/null +++ b/libopae/src/event.c @@ -0,0 +1,333 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include + +#include "safe_string/safe_string.h" + +#include "opae/access.h" +#include "types_int.h" +#include "common_int.h" + +#define EVENT_SOCKET_NAME "/tmp/fpga_event_socket" +#define EVENT_SOCKET_NAME_LEN 23 +#define MAX_PATH_LEN 256 + +enum request_type { + REGISTER_EVENT = 0, + UNREGISTER_EVENT = 1 +}; + +struct event_request { + enum request_type type; + fpga_event_type event; + char device[MAX_PATH_LEN]; +}; + +fpga_result send_event_request(int conn_socket, int fd, struct event_request *req) +{ + struct msghdr mh; + struct cmsghdr *cmh; + struct iovec iov[1]; + char buf[CMSG_SPACE(sizeof(int))]; + ssize_t n; + int *fd_ptr; + + /* set up ancillary data message header */ + iov[0].iov_base = req; + iov[0].iov_len = sizeof(*req); + memset(buf, 0x0, sizeof(buf)); + cmh = (struct cmsghdr *)buf; + cmh->cmsg_len = CMSG_LEN(sizeof(int)); + cmh->cmsg_level = SOL_SOCKET; + cmh->cmsg_type = SCM_RIGHTS; + mh.msg_name = NULL; + mh.msg_namelen = 0; + mh.msg_iov = iov; + mh.msg_iovlen = sizeof(iov) / sizeof(iov[0]); + mh.msg_control = cmh; + mh.msg_controllen = CMSG_LEN(sizeof(int)); + mh.msg_flags = 0; + fd_ptr = (int *)CMSG_DATA((struct cmsghdr *)buf); + *fd_ptr = fd; + + /* send ancillary data */ + n = sendmsg(conn_socket, &mh, 0); + if (n < 0) { + FPGA_ERR("sendmsg failed: %s", strerror(errno)); + return FPGA_EXCEPTION; + } + + return FPGA_OK; + +} + +static fpga_result driver_register_event(/* tbd */) +{ + return FPGA_NOT_SUPPORTED; +} + +static fpga_result driver_unregister_event(/* tbd */) +{ + return FPGA_NOT_SUPPORTED; +} + +static fpga_result daemon_register_event(fpga_handle handle, + fpga_event_type event_type, + fpga_event_handle event_handle, + uint32_t flags) +{ + int fd = event_handle; + fpga_result result = FPGA_OK; + struct sockaddr_un addr; + struct event_request req; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct _fpga_token *_token = (struct _fpga_token *)_handle->token; + errno_t e; + + if (_handle->fdfpgad < 0) { + + /* connect to event socket */ + _handle->fdfpgad = socket(AF_UNIX, SOCK_STREAM, 0); + if (_handle->fdfpgad < 0) { + FPGA_ERR("socket: %s", strerror(errno)); + return FPGA_EXCEPTION; + } + + addr.sun_family = AF_UNIX; + e = strncpy_s(addr.sun_path, sizeof(addr.sun_path), + EVENT_SOCKET_NAME, EVENT_SOCKET_NAME_LEN); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + return FPGA_EXCEPTION; + } + + if (connect(_handle->fdfpgad, (struct sockaddr *)&addr, sizeof(addr)) < 0) { + FPGA_ERR("connect: %s", strerror(errno)); + result = FPGA_NO_DAEMON; + goto out_close_conn; + } + + } + + /* create event registration request */ + req.type = REGISTER_EVENT; + req.event = event_type; + + e = strncpy_s(req.device, sizeof(req.device), + _token->sysfspath, sizeof(_token->sysfspath)); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + result = FPGA_EXCEPTION; + goto out_close_conn; + } + + req.device[sizeof(req.device)-1] = '\0'; + + /* send event packet */ + result = send_event_request(_handle->fdfpgad, fd, &req); + if (result != FPGA_OK) { + FPGA_ERR("send_event_request failed"); + goto out_close_conn; + } + +out: + return result; + +out_close_conn: + close(_handle->fdfpgad); + _handle->fdfpgad = -1; + return result; +} + +static fpga_result daemon_unregister_event(fpga_handle handle, + fpga_event_type event_type) +{ + fpga_result result = FPGA_OK; + + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct _fpga_token *_token = (struct _fpga_token *)_handle->token; + + struct event_request req; + ssize_t n; + errno_t e; + + if (_handle->fdfpgad < 0) { + FPGA_MSG("No fpgad connection"); + return FPGA_INVALID_PARAM; + } + + req.type = UNREGISTER_EVENT; + req.event = event_type; + + e = strncpy_s(req.device, sizeof(req.device), + _token->sysfspath, sizeof(_token->sysfspath)); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + result = FPGA_EXCEPTION; + goto out_close_conn; + } + + req.device[sizeof(req.device)-1] = '\0'; + + n = send(_handle->fdfpgad, &req, sizeof(req), 0); + if (n < 0) { + FPGA_ERR("send : %s", strerror(errno)); + result = FPGA_EXCEPTION; + goto out_close_conn; + } + + return result; + +out_close_conn: + close(_handle->fdfpgad); + _handle->fdfpgad = -1; + return result; +} + +fpga_result __FPGA_API__ fpgaCreateEventHandle(fpga_event_handle *event_handle) +{ + int fd; + + ASSERT_NOT_NULL(event_handle); + + /* create eventfd */ + fd = eventfd(0, 0); + if (fd < 0) { + FPGA_ERR("eventfd : %s", strerror(errno)); + return FPGA_NOT_SUPPORTED; + } + + *event_handle = fd; + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaDestroyEventHandle(fpga_event_handle *event_handle) +{ + ASSERT_NOT_NULL(event_handle); + + if (close(*event_handle) < 0) { + FPGA_ERR("eventfd : %s", strerror(errno)); + if (errno == EBADF) + return FPGA_INVALID_PARAM; + else + return FPGA_EXCEPTION; + } + return FPGA_OK; +} + +fpga_result __FPGA_API__ fpgaRegisterEvent(fpga_handle handle, + fpga_event_type event_type, + fpga_event_handle event_handle, + uint32_t flags) +{ + fpga_result result = FPGA_OK; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct _fpga_token *_token; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + _token = (struct _fpga_token *)_handle->token; + + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token found in handle"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + switch (event_type) { + case FPGA_EVENT_INTERRUPT: + if (!strstr(_token->devpath, "port")) { + FPGA_MSG("Handle does not refer to accelerator object"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + break; + } + + /* TODO: reject unknown flags */ + + /* try driver first */ + result = driver_register_event(); + if (result == FPGA_NOT_SUPPORTED) { + result = daemon_register_event(handle, event_type, + event_handle, flags); + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaUnregisterEvent(fpga_handle handle, fpga_event_type event_type) +{ + fpga_result result = FPGA_OK; + + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct _fpga_token *_token; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + _token = (struct _fpga_token *)_handle->token; + + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token found in handle"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + switch (event_type) { + case FPGA_EVENT_INTERRUPT: + if (!strstr(_token->devpath, "port")) { + FPGA_MSG("Handle does not refer to accelerator object"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + break; + } + + /* try driver first */ + result = driver_unregister_event(); + if (result == FPGA_NOT_SUPPORTED) { + result = daemon_unregister_event(handle, event_type); + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + diff --git a/libopae/src/hostif.c b/libopae/src/hostif.c new file mode 100644 index 000000000000..7b6015689d32 --- /dev/null +++ b/libopae/src/hostif.c @@ -0,0 +1,101 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "opae/access.h" +#include "opae/utils.h" +#include "opae/manage.h" +#include "common_int.h" +#include "intel-fpga.h" + +#define FPGA_MAX_INTERFACE_NUM 1 + +//Assign Port to PF from Interface +#define ASSIGN_PORT_TO_PF 0 + +//Release Port from PF and Assign to Interface +#define ASSIGN_PORT_TO_HOST 1 + +//Assign and Release port to a host interface +fpga_result __FPGA_API__ fpgaAssignPortToInterface(fpga_handle fpga, + uint32_t interface_num, + uint32_t slot_num, + int flags) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)fpga; + fpga_result result = FPGA_OK; + struct fpga_fme_port_assign config = {0}; + + config.argsz = sizeof(config); + config.flags = 0; + config.port_id = slot_num; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (interface_num > FPGA_MAX_INTERFACE_NUM) { + FPGA_ERR("Invalid input parameters"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // Assign Port to PF from Interface + if (interface_num == ASSIGN_PORT_TO_PF) { + + result = ioctl(_handle->fddev, FPGA_FME_PORT_ASSIGN, &config); + if (result != 0) { + FPGA_ERR("Failed to assign port"); + result = FPGA_NOT_SUPPORTED; + goto out_unlock; + } + } + + // Release Port from PF and assign to Interface + if (interface_num == ASSIGN_PORT_TO_HOST) { + + result = ioctl(_handle->fddev, FPGA_FME_PORT_RELEASE, &config); + if (result != 0) { + FPGA_ERR("Failed to release port"); + result = FPGA_NOT_SUPPORTED; + goto out_unlock; + } + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; + +} diff --git a/libopae/src/intel-fpga.h b/libopae/src/intel-fpga.h new file mode 100644 index 000000000000..08b3bc592ae1 --- /dev/null +++ b/libopae/src/intel-fpga.h @@ -0,0 +1,272 @@ +/* + * Header File for Intel FPGA User API + * + * Copyright 2016 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Zhang Yi + * Wu Hao + * Xiao Guangrong + * + * This work is licensed under the terms of the GNU GPL version 2. See + * the COPYING file in the top-level directory. + * + */ + +#ifndef _UAPI_INTEL_FPGA_H +#define _UAPI_INTEL_FPGA_H + +#include + +#define FPGA_API_VERSION 0 + +/* + * The IOCTL interface for Intel FPGA is designed for extensibility by + * embedding the structure length (argsz) and flags into structures passed + * between kernel and userspace. This design referenced the VFIO IOCTL + * interface (include/uapi/linux/vfio.h). + */ + +#define FPGA_MAGIC 0xB5 + +#define FPGA_BASE 0 +#define PORT_BASE 0x40 +#define FME_BASE 0x80 + +/* Common IOCTLs for both FME and AFU file descriptor */ + +/** + * FPGA_GET_API_VERSION - _IO(FPGA_MAGIC, FPGA_BASE + 0) + * + * Report the version of the driver API. + * Return: Driver API Version. + */ + +#define FPGA_GET_API_VERSION _IO(FPGA_MAGIC, FPGA_BASE + 0) + +/** + * FPGA_CHECK_EXTENSION - _IO(FPGA_MAGIC, FPGA_BASE + 1) + * + * Check whether an extension is supported. + * Return: 0 if not supported, otherwise the extension is supported. + */ + +#define FPGA_CHECK_EXTENSION _IO(FPGA_MAGIC, FPGA_BASE + 1) + +/* IOCTLs for AFU file descriptor */ + +/** + * FPGA_PORT_RESET - _IO(FPGA_MAGIC, PORT_BASE + 0) + * + * Reset the FPGA AFU Port. No parameters are supported. + * Return: 0 on success, -errno of failure + */ + +#define FPGA_PORT_RESET _IO(FPGA_MAGIC, PORT_BASE + 0) + +/** + * FPGA_PORT_GET_INFO - _IOR(FPGA_MAGIC, PORT_BASE + 1, struct fpga_port_info) + * + * Retrieve information about the fpga port. + * Driver fills the info in provided struct fpga_port_info. + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_info { + /* Input */ + __u32 argsz; /* Structure length */ + /* Output */ + __u32 flags; /* Zero for now */ + __u32 num_regions; /* The number of supported regions */ + __u32 num_umsgs; /* The number of allocated umsgs */ +}; + +#define FPGA_PORT_GET_INFO _IO(FPGA_MAGIC, PORT_BASE + 1) + +/** + * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2, + * struct fpga_port_region_info) + * + * Retrieve information about a device region. + * Caller provides struct fpga_port_region_info with index value set. + * Driver returns the region info in other fields. + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_region_info { + /* input */ + __u32 argsz; /* Structure length */ + /* Output */ + __u32 flags; /* Access permission */ +#define FPGA_REGION_READ (1 << 0) /* Region is readable */ +#define FPGA_REGION_WRITE (1 << 1) /* Region is writable */ +#define FPGA_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */ + /* Input */ + __u32 index; /* Region index */ +#define FPGA_PORT_INDEX_UAFU 0 /* User AFU */ +#define FPGA_PORT_INDEX_STP 1 /* Signal Tap */ + __u32 padding; + /* Output */ + __u64 size; /* Region size (bytes) */ + __u64 offset; /* Region offset from start of device fd */ +}; + +#define FPGA_PORT_GET_REGION_INFO _IO(FPGA_MAGIC, PORT_BASE + 2) + +/** + * FPGA_PORT_DMA_MAP - _IOWR(FPGA_MAGIC, PORT_BASE + 3, + * struct fpga_port_dma_map) + * + * Map the dma memory per user_addr and length which are provided by caller. + * Driver fills the iova in provided struct afu_port_dma_map. + * This interface only accepts page-size aligned user memory for dma mapping. + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_dma_map { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u64 user_addr; /* Process virtual address */ + __u64 length; /* Length of mapping (bytes)*/ + /* Output */ + __u64 iova; /* IO virtual address */ +}; + +#define FPGA_PORT_DMA_MAP _IO(FPGA_MAGIC, PORT_BASE + 3) + +/** + * FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4, + * struct fpga_port_dma_unmap) + * + * Unmap the dma memory per iova provided by caller. + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_dma_unmap { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u64 iova; /* IO virtual address */ +}; + +#define FPGA_PORT_DMA_UNMAP _IO(FPGA_MAGIC, PORT_BASE + 4) + +/** + * FPGA_PORT_UMSG_ENABLE - _IO(FPGA_MAGIC, PORT_BASE + 5) + * FPGA_PORT_UMSG_DISABLE - _IO(FPGA_MAGIC, PORT_BASE + 6) + * + * Interfaces to control UMSG function. No parameters are supported. + * Return: 0 on success, -errno on failure. + */ + +#define FPGA_PORT_UMSG_ENABLE _IO(FPGA_MAGIC, PORT_BASE + 5) +#define FPGA_PORT_UMSG_DISABLE _IO(FPGA_MAGIC, PORT_BASE + 6) + +/** + * FPGA_PORT_UMSG_SET_MODE - _IOW(FPGA_MAGIC, PORT_BASE + 7, + * struct fpga_port_umsg_cfg) + * + * Set Hint Mode per bitmap provided by caller. One bit for each page + * in hint_bitmap. 0 - Disable and 1 - Enable Hint Mode. + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_umsg_cfg { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u32 hint_bitmap; /* UMSG Hint Mode Bitmap */ +}; + +#define FPGA_PORT_UMSG_SET_MODE _IO(FPGA_MAGIC, PORT_BASE + 7) + +/** + * FPGA_PORT_UMSG_SET_BASE_ADDR - _IOW(FPGA_MAGIC, PORT_BASE + 8, + * struct afu_port_umsg_base_addr) + * + * Set UMSG base address per iova provided by caller. Driver configures the + * UMSG base address with the iova, but only accept iova which get from the + * DMA_MAP IOCTL interface and the DMA region is big enough for all UMSGs + * (num_umsg * PAGE_SIZE) + * Return: 0 on success, -errno on failure. + */ +struct fpga_port_umsg_base_addr { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u64 iova; /* IO virtual address */ +}; + +#define FPGA_PORT_UMSG_SET_BASE_ADDR _IO(FPGA_MAGIC, PORT_BASE + 8) + +/* IOCTLs for FME file descriptor */ + +/** + * FPGA_FME_PORT_PR - _IOWR(FPGA_MAGIC, FME_BASE + 0, struct fpga_fme_port_pr) + * + * Driver does Partial Reconfiguration based on Port ID and Buffer (Image) + * provided by caller. + * Return: 0 on success, -errno on failure. + * If FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected + * some errors during PR, under this case, the user can fetch HW error code + * from fpga_fme_port_pr.status. Each bit on the error code is used as the + * index for the array created by DEFINE_FPGA_PR_ERR_MSG(). + * Otherwise, it is always zero. + */ + +#define DEFINE_FPGA_PR_ERR_MSG(_name_) \ +static const char * const _name_[] = { \ + "PR operation error detected", \ + "PR CRC error detected", \ + "PR incompatiable bitstream error detected", \ + "PR IP protocol error detected", \ + "PR FIFO overflow error detected", \ + "PR timeout error detected", \ + "PR secure load error detected", \ +} + +#define PR_MAX_ERR_NUM 7 + +struct fpga_fme_port_pr { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u32 port_id; + __u32 buffer_size; + __u64 buffer_address; /* Userspace address to the buffer for PR */ + /* Output */ + __u64 status; /* HW error code if ioctl returns -EIO */ +}; + +#define FPGA_FME_PORT_PR _IO(FPGA_MAGIC, FME_BASE + 0) + +/** + * FPGA_FME_PORT_RELEASE - _IOW(FPGA_MAGIC, FME_BASE + 1, + * struct fpga_fme_port_release) + * + * Driver releases the port per Port ID provided by caller. + * Return: 0 on success, -errno on failure. + */ +struct fpga_fme_port_release { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u32 port_id; +}; + +#define FPGA_FME_PORT_RELEASE _IO(FPGA_MAGIC, FME_BASE + 1) + +/** + * FPGA_FME_PORT_ASSIGN - _IOW(FPGA_MAGIC, FME_BASE + 2, + * struct fpga_fme_port_assign) + * + * Driver assigns the port per Port ID provided by caller. + * Return: 0 on success, -errno on failure. + */ +struct fpga_fme_port_assign { + /* Input */ + __u32 argsz; /* Structure length */ + __u32 flags; /* Zero for now */ + __u32 port_id; +}; + +#define FPGA_FME_PORT_ASSIGN _IO(FPGA_MAGIC, FME_BASE + 2) + +#endif /* _UAPI_INTEL_FPGA_H */ diff --git a/libopae/src/log.c b/libopae/src/log.c new file mode 100644 index 000000000000..399c667f108a --- /dev/null +++ b/libopae/src/log.c @@ -0,0 +1,98 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "common_int.h" + +#include +#include +#include + +/* global loglevel */ +static int g_loglevel = FPGA_LOG_UNDEFINED; +/* mutex to protect against garbled log output */ +pthread_mutex_t log_lock = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP; + +void __FIXME_MAKE_VISIBLE__ fpga_print(int loglevel, char *fmt, ...) +{ + FILE *fp = stdout; + pthread_mutexattr_t mattr; + + /* TODO: how to make this lazy initializer thread-safe? */ + if (g_loglevel < 0) { /* loglevel not yet set? */ + + if (pthread_mutexattr_init(&mattr)) { + fprintf(stderr, "Failed to create log mutex attributes\n"); + return; + } + + if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE) || + pthread_mutex_init(&log_lock, &mattr)) { + fprintf(stderr, "Failed to create log mutex\n"); + goto out_attr_destroy; + } + + pthread_mutexattr_destroy(&mattr); + + /* try to read loglevel from environment */ + char *s = getenv("LIBOPAE_LOG"); + if (s) + g_loglevel = atoi(s); +#ifndef LIBFGPA_DEBUG + if (g_loglevel >= FPGA_LOG_DEBUG) + fprintf(stderr, + "WARNING: Environment variable LIBOPAE_LOG is " + "set to output debug\nmessages, " + "but libopae-c was not built with debug " + "information.\n"); +#endif + } + + if (g_loglevel < 0) /* loglevel still not set? */ + g_loglevel = FPGA_DEFAULT_LOGLEVEL; + + if (loglevel > g_loglevel) + return; + + if (loglevel == FPGA_LOG_ERROR) + fp = stderr; + + va_list argp; + va_start(argp, fmt); + pthread_mutex_lock(&log_lock); /* ignore failure and print anyway */ + vfprintf(fp, fmt, argp); + pthread_mutex_unlock(&log_lock); + va_end(argp); + + return; + +out_attr_destroy: + pthread_mutexattr_destroy(&mattr); +} + diff --git a/libopae/src/log_int.h b/libopae/src/log_int.h new file mode 100644 index 000000000000..77dc9a6b14bc --- /dev/null +++ b/libopae/src/log_int.h @@ -0,0 +1,88 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_SRC_LOG_H__ +#define __FPGA_SRC_LOG_H__ + +/* + * Convenience macros for printing messages and errors. + */ +#ifdef __SHORT_FILE__ +#undef __SHORT_FILE__ +#endif // __SHORT_FILE__ +#define __SHORT_FILE__ \ +({ const char *file = __FILE__; \ + const char *p = file; \ + while (*p) \ + ++p; \ + while ((p > file) && \ + ('/' != *p) && \ + ('\\' != *p)) \ + --p; \ + if (p > file) \ + ++p; \ + p; \ +}) + +#ifdef FPGA_MSG +#undef FPGA_MSG +#endif // FPGA_MSG +#define FPGA_MSG(format, ...)\ + fpga_print(FPGA_LOG_MESSAGE, "libopae-c %s:%u:%s() : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) + +#ifdef FPGA_ERR +#undef FPGA_ERR +#endif // FPGA_ERR +#define FPGA_ERR(format, ...)\ + fpga_print(FPGA_LOG_ERROR, "libopae-c %s:%u:%s() **ERROR** : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) + +#ifdef FPGA_DBG +#undef FPGA_DBG +#endif // FPGA_DBG +#ifdef LIBFPGA_DEBUG +#define FPGA_DBG(format, ...)\ + fpga_print(FPGA_LOG_DEBUG, "libopae-c %s:%u:%s() *DEBUG* : " format "\n",\ + __SHORT_FILE__, __LINE__, __func__, ## __VA_ARGS__) +#else +#define FPGA_DBG(format, ...) {} +#endif // LIBFPGA_DEBUG + +/* + * Logging functions + */ +enum fpga_loglevel { + FPGA_LOG_UNDEFINED = -1, /* loglevel not set */ + FPGA_LOG_ERROR = 0, /* critical errors (always print) */ + FPGA_LOG_MESSAGE, /* information (i.e. explain return code */ + FPGA_LOG_DEBUG /* debugging (also needs #define DEBUG 1) */ +}; +#define FPGA_DEFAULT_LOGLEVEL 0 + +void fpga_print(int loglevel, char *fmt, ...); + +#endif // ___FPGA_SRC_LOG_H__ diff --git a/libopae/src/manage.c b/libopae/src/manage.c new file mode 100644 index 000000000000..e5ddd31211f7 --- /dev/null +++ b/libopae/src/manage.c @@ -0,0 +1,50 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "opae/manage.h" +#include "common_int.h" + +fpga_result __FPGA_API__ fpgaAssignToInterface(fpga_handle fpga, fpga_token accelerator, + uint32_t host_interface, int flags) +{ + FPGA_MSG("fpgaAssignToInterface not supported"); + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} + +fpga_result __FPGA_API__ fpgaReleaseFromInterface(fpga_handle fpga, fpga_token accelerator) +{ + FPGA_MSG("fpgaReleaseFromInterface not supported"); + fpga_result result = FPGA_NOT_SUPPORTED; + + return result; +} + diff --git a/libopae/src/mmap.c b/libopae/src/mmap.c new file mode 100644 index 000000000000..3037b269ae77 --- /dev/null +++ b/libopae/src/mmap.c @@ -0,0 +1,91 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "mmap_int.h" +#include "log_int.h" + +#include + +// Buffer Allocation constants +#define KB 1024 +#define MB (1024 * KB) +#define GB (1024 * MB) + +#ifndef MAP_HUGETLB +#define MAP_HUGETLB 0x40000 +#endif +#ifndef MAP_HUGE_SHIFT +#define MAP_HUGE_SHIFT 26 +#endif +#define MAP_1G_HUGEPAGE (0x1e << MAP_HUGE_SHIFT) + +#define PROTECTION (PROT_READ | PROT_WRITE) + +#ifdef __ia64__ +#define ADDR (void *)(0x8000000000000000UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#else +#define ADDR (void *)(0x0UL) +#define FLAGS_4K (MAP_PRIVATE | MAP_ANONYMOUS) +#define FLAGS_2M (FLAGS_4K | MAP_HUGETLB) +#define FLAGS_1G (FLAGS_2M | MAP_1G_HUGEPAGE) +#endif + +void *alloc_buffer(uint64_t len) +{ + void *addr = NULL; + + /* For buffer > 2M, use 1G-hugepage to ensure pages are continuous */ + if (len > 2 * MB) + addr = mmap(ADDR, len, PROTECTION, FLAGS_1G, 0, 0); + else if (len > 4 * KB) + addr = mmap(ADDR, len, PROTECTION, FLAGS_2M, 0, 0); + else + addr = mmap(ADDR, len, PROTECTION, FLAGS_4K, 0, 0); + if (addr == MAP_FAILED) { + FPGA_ERR("mmap failed"); + addr = NULL; + } + + return addr; +} + +int free_buffer(void *addr, uint64_t len) +{ + if (munmap(addr, len)) { + FPGA_ERR("munmap failed"); + return FPGA_INVALID_PARAM; + } + + return FPGA_OK; +} + diff --git a/libopae/src/mmap_int.h b/libopae/src/mmap_int.h new file mode 100644 index 000000000000..ed60b5ed4372 --- /dev/null +++ b/libopae/src/mmap_int.h @@ -0,0 +1,49 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_MMAP_INT_H__ +#define __FPGA_MMAP_INT_H__ + +#include "opae/types.h" + +/* + * Allocate a buffer of length 'len' using huge pages + */ +void *alloc_buffer(uint64_t len); + +/* + * Free a previously allocated buffer of len 'len' + */ +int free_buffer(void *addr, + uint64_t len); + +/* + * Free the UMsg buffer allocated for resource 'handle' + * Implemented in umsg.c + */ +fpga_result free_umsg_buffer(fpga_handle handle); + +#endif // ___FPGA_MMAP_INT_H__ diff --git a/libopae/src/mmio.c b/libopae/src/mmio.c new file mode 100644 index 000000000000..ae58d5904768 --- /dev/null +++ b/libopae/src/mmio.c @@ -0,0 +1,379 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "opae/access.h" +#include "opae/utils.h" +#include "common_int.h" +#include "intel-fpga.h" + +#include +#include +#include +#include +#include +#include + +/* Port UAFU */ +#define AFU_PERMISSION (FPGA_REGION_READ | FPGA_REGION_WRITE | FPGA_REGION_MMAP) +#define AFU_SIZE 0x40000 +#define AFU_OFFSET 0 + +fpga_result __FPGA_API__ fpgaWriteMMIO32(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, + uint32_t value) +{ + + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + if (offset % sizeof(uint32_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } + + result = handle_check_and_lock(_handle); + if (result) + return result; + + struct wsid_map *wm = wsid_find_by_index(_handle->mmio_root, mmio_num); + if (!wm) { + FPGA_MSG("Trying to access MMIO before calling fpgaMapMMIO()"); + result = FPGA_NOT_FOUND; + goto out_unlock; + } + + if (offset > wm->len) { + FPGA_MSG("offset out of bounds"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + *((volatile uint32_t *) ((uint8_t *)wm->offset + offset)) = value; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaReadMMIO32(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, + uint32_t *value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + if (offset % sizeof(uint32_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } + + result = handle_check_and_lock(_handle); + if (result) + return result; + + struct wsid_map *wm = wsid_find_by_index(_handle->mmio_root, mmio_num); + if (!wm) { + FPGA_MSG("Trying to access MMIO before calling fpgaMapMMIO()"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + if (offset > wm->len) { + FPGA_MSG("offset out of bounds"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + *value = *((volatile uint32_t *) ((uint8_t *)wm->offset + offset)); + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaWriteMMIO64(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, + uint64_t value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + if (offset % sizeof(uint64_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } + + result = handle_check_and_lock(_handle); + if (result) + return result; + + struct wsid_map *wm = wsid_find_by_index(_handle->mmio_root, mmio_num); + if (!wm) { + FPGA_MSG("Trying to access MMIO before calling fpgaMapMMIO()"); + result = FPGA_NOT_FOUND; + goto out_unlock; + } + + if (offset > wm->len) { + FPGA_MSG("offset out of bounds"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + *((volatile uint64_t *) ((uint8_t *)wm->offset + offset)) = value; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaReadMMIO64(fpga_handle handle, + uint32_t mmio_num, + uint64_t offset, + uint64_t *value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + if (offset % sizeof(uint64_t) != 0) { + FPGA_MSG("Misaligned MMIO access"); + return FPGA_INVALID_PARAM; + } + + result = handle_check_and_lock(_handle); + if (result) + return result; + + struct wsid_map *wm = wsid_find_by_index(_handle->mmio_root, mmio_num); + if (!wm) { + FPGA_MSG("Trying to access MMIO before calling fpgaMapMMIO()"); + result = FPGA_NOT_FOUND; + goto out_unlock; + } + + if (offset > wm->len) { + FPGA_MSG("offset out of bounds"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + *value = *((volatile uint64_t *) ((uint8_t *)wm->offset + offset)); + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +static fpga_result port_get_region_info(fpga_handle handle, + uint32_t mmio_num, + uint32_t *flags, + uint64_t *size, + uint64_t *offset) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(flags); + ASSERT_NOT_NULL(size); + ASSERT_NOT_NULL(offset); + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Set ioctl fpga_port_region_info struct parameters */ + struct fpga_port_region_info rinfo = {.argsz = sizeof(rinfo), + .padding = 0, + .index = (__u32) mmio_num}; + + /* Dispatch ioctl command */ + if (ioctl(_handle->fddev, FPGA_PORT_GET_REGION_INFO, &rinfo) != 0) { + FPGA_MSG("FPGA_PORT_GET_REGION_INFO ioctl failed: %s", + strerror(errno)); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + *flags = (uint32_t) rinfo.flags; + *size = (uint64_t) rinfo.size; + *offset = (uint64_t) rinfo.offset; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +static fpga_result port_mmap_region(fpga_handle handle, + void **vaddr, + uint64_t size, + uint32_t flags, + uint64_t offset, + uint32_t mmio_num) +{ + void *addr; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + /* Assure returning pointer contains allocated memory */ + ASSERT_NOT_NULL(vaddr); + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Map MMIO memory */ + addr = (void *) mmap(NULL, size, flags, MAP_SHARED, _handle->fddev, offset); + if (vaddr == MAP_FAILED) { + FPGA_MSG("Unable to map MMIO region. Error value is : %s", + strerror(errno)); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + /* Save return address */ + if (vaddr) + *vaddr = addr; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaMapMMIO(fpga_handle handle, + uint32_t mmio_num, + uint64_t **mmio_ptr) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_NOT_FOUND; + void *addr; + uint64_t wsid; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Obtain MMIO region information */ + uint32_t flags; + uint64_t size; + uint64_t offset; + result = port_get_region_info(handle, + mmio_num, + &flags, + &size, + &offset); + + if (result != FPGA_OK) + goto out_unlock; + + if (flags != AFU_PERMISSION) { + FPGA_MSG("Invalid MMIO permission flags"); + result = FPGA_NO_ACCESS; + goto out_unlock; + } + + /* Map UAFU MMIO */ + result = port_mmap_region(handle, + (void **) &addr, + size, + PROT_READ | PROT_WRITE, + offset, + mmio_num); + if (result != FPGA_OK) + goto out_unlock; + + /* Add to MMIO list */ + wsid = wsid_gen(); + if (!wsid_add(&_handle->mmio_root, + wsid, + (uint64_t) NULL, + (uint64_t) NULL, + size, + (uint64_t) addr, + mmio_num, + 0)) { + if (munmap(addr, size)) { + FPGA_MSG("munmap failed. Error value is : %s", + strerror(errno)); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } else { + FPGA_MSG("Failed to add MMIO id: %d", mmio_num); + result = FPGA_NO_MEMORY; + goto out_unlock; + } + } + + /* Store return value only if return pointer has allocated memory */ + if (mmio_ptr) + *mmio_ptr = addr; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaUnmapMMIO(fpga_handle handle, + uint32_t mmio_num) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + void *mmio_ptr; + fpga_result result = FPGA_OK; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + /* Fetch the MMIO physical address and length */ + struct wsid_map *wm = wsid_find_by_index(_handle->mmio_root, mmio_num); + if (!wm) { + FPGA_MSG("MMIO region %d not found", mmio_num); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + /* Unmap UAFU MMIO */ + mmio_ptr = (void *) wm->offset; + if (munmap((void *) mmio_ptr, wm->len)) { + FPGA_MSG("munmap failed: %s", + strerror(errno)); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + /* Remove MMIO */ + wsid_del(&_handle->mmio_root, wm->wsid); + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} diff --git a/libopae/src/open.c b/libopae/src/open.c new file mode 100644 index 000000000000..02aeff2b52f8 --- /dev/null +++ b/libopae/src/open.c @@ -0,0 +1,146 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "common_int.h" +#include +#include +#include "types_int.h" + +#include +#include +#include +#include + +fpga_result __FPGA_API__ fpgaOpen(fpga_token token, fpga_handle *handle, int flags) +{ + fpga_result result = FPGA_NOT_FOUND; + struct _fpga_handle *_handle; + struct _fpga_token *_token; + int fddev = -1; + pthread_mutexattr_t mattr; + int open_flags = 0; + + if (NULL == token) { + FPGA_MSG("token is NULL"); + return FPGA_INVALID_PARAM; + } + + if (NULL == handle) { + FPGA_MSG("handle is NULL"); + return FPGA_INVALID_PARAM; + } + + if (flags & ~FPGA_OPEN_SHARED) { + FPGA_MSG("unrecognized flags"); + return FPGA_INVALID_PARAM; + } + + _token = (struct _fpga_token *)token; + + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token"); + return FPGA_INVALID_PARAM; + } + + _handle = malloc(sizeof(struct _fpga_handle)); + if (NULL == _handle) { + FPGA_MSG("Failed to allocate memory for handle"); + return FPGA_NO_MEMORY; + } + + memset(_handle, 0, sizeof(*_handle)); + + // mark data structure as valid + _handle->magic = FPGA_HANDLE_MAGIC; + + _handle->token = token; + + _handle->fdfpgad = -1; + + // Init MMIO table + _handle->mmio_root = NULL; + + // Init workspace table + _handle->wsid_root = NULL; + + // Open resources in exclusive mode unless FPGA_OPEN_SHARED is given + open_flags = O_RDWR | (flags & FPGA_OPEN_SHARED ? 0 : O_EXCL); + fddev = open(_token->devpath, open_flags); + if (-1 == fddev) { + FPGA_MSG("Open failed: %s", strerror(errno)); + switch (errno) { + case EACCES: + result = FPGA_NO_ACCESS; + break; + case EBUSY: + result = FPGA_BUSY; + break; + default: + result = FPGA_NO_DRIVER; + break; + } + goto out_free; + } + + // Save the file descriptor for close. + _handle->fddev = fddev; + + if (pthread_mutexattr_init(&mattr)) { + FPGA_MSG("Failed to init handle mutex attributes"); + result = FPGA_EXCEPTION; + goto out_free; + } + + if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE) || + pthread_mutex_init(&_handle->lock, &mattr)) { + FPGA_MSG("Failed to init handle mutex"); + result = FPGA_EXCEPTION; + goto out_attr_destroy; + } + + pthread_mutexattr_destroy(&mattr); + + // set handle return value + *handle = (void *)_handle; + + return FPGA_OK; + +out_attr_destroy: + pthread_mutexattr_destroy(&mattr); + +out_free: + free(_handle); + + if (-1 != fddev) { + close(fddev); + } + + return result; +} diff --git a/libopae/src/properties.c b/libopae/src/properties.c new file mode 100644 index 000000000000..ef091e8cfac9 --- /dev/null +++ b/libopae/src/properties.c @@ -0,0 +1,1074 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include "common_int.h" +#include "opae/properties.h" +#include "opae/enum.h" +#include "opae/utils.h" +#include "properties_int.h" + +#include "safe_string/safe_string.h" + + +fpga_result __FPGA_API__ fpgaGetProperties(fpga_token token, fpga_properties *prop) +{ + struct _fpga_properties *_prop; + fpga_result result = FPGA_OK; + pthread_mutexattr_t mattr; + + ASSERT_NOT_NULL(prop); + + _prop = malloc(sizeof(struct _fpga_properties)); + if (NULL == _prop) { + FPGA_MSG("Failed to allocate memory for properties"); + return FPGA_NO_MEMORY; + } + memset(_prop, 0, sizeof(struct _fpga_properties)); + // mark data structure as valid + _prop->magic = FPGA_PROPERTY_MAGIC; + + if (pthread_mutexattr_init(&mattr)) { + FPGA_MSG("Failed to initialized property mutex attributes"); + result = FPGA_EXCEPTION; + goto out_free; + } + + if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE)) { + FPGA_MSG("Failed to initialize property mutex attributes"); + result = FPGA_EXCEPTION; + goto out_attr_destroy; + } + + if (pthread_mutex_init(&_prop->lock, &mattr)) { + FPGA_MSG("Failed to initialize property mutex"); + result = FPGA_EXCEPTION; + goto out_attr_destroy; + } + + if (token) { + result = fpgaUpdateProperties(token, _prop); + if (result != FPGA_OK) + goto out_mutex_destroy; + } + + pthread_mutexattr_destroy(&mattr); + *prop = (fpga_properties)_prop; + return result; + +out_mutex_destroy: + pthread_mutex_destroy(&_prop->lock); + +out_attr_destroy: + pthread_mutexattr_destroy(&mattr); + +out_free: + free(_prop); + return result; +} + +fpga_result __FPGA_API__ fpgaClearProperties(fpga_properties prop) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->valid_fields = 0; + + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaCloneProperties(fpga_properties src, + fpga_properties *dst) +{ + struct _fpga_properties *_src = (struct _fpga_properties *)src; + struct _fpga_properties *_dst; + pthread_mutexattr_t mattr; + fpga_result result; + + ASSERT_NOT_NULL(dst); + result = prop_check_and_lock(_src); + if (result) + return result; + + _dst = malloc(sizeof(struct _fpga_properties)); + if (NULL == _dst) { + FPGA_MSG("Failed to allocate memory for properties"); + pthread_mutex_unlock(&_src->lock); + return FPGA_NO_MEMORY; + } + + *_dst = *_src; + + pthread_mutex_unlock(&_src->lock); + + /* we just copied a locked mutex, so reinitialize it */ + if (pthread_mutexattr_init(&mattr)) { + FPGA_MSG("Failed to initialize dst mutex attributes"); + result = FPGA_EXCEPTION; + goto out_free; + } + + if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE) || + pthread_mutex_init(&_dst->lock, &mattr)) { + FPGA_MSG("Failed to initialize dst mutex"); + result = FPGA_EXCEPTION; + goto out_attr_destroy; + } + + pthread_mutexattr_destroy(&mattr); + + *dst = _dst; + return FPGA_OK; + +out_attr_destroy: + pthread_mutexattr_destroy(&mattr); + +out_free: + free(_dst); + return result; +} + +fpga_result __FPGA_API__ fpgaDestroyProperties(fpga_properties *prop) +{ + struct _fpga_properties *_prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(prop); + + _prop = (struct _fpga_properties *)*prop; + result = prop_check_and_lock(_prop); + if (result) + return result; + + // invalidate magic (just in case) + _prop->magic = FPGA_INVALID_MAGIC; + + pthread_mutex_unlock(&_prop->lock); + pthread_mutex_destroy(&_prop->lock); + + free(*prop); + *prop = NULL; + + return result; +} + +fpga_result __FPGA_API__ +fpgaUpdateProperties(fpga_token token, fpga_properties prop) +{ + struct _fpga_token *_token = (struct _fpga_token *)token; + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + + struct _fpga_properties _iprop; + + char spath[SYSFS_PATH_MAX]; + char *p; + int b, d, f; + int device_id; + int res; + errno_t e; + + pthread_mutex_t lock; + + fpga_result result = FPGA_INVALID_PARAM; + + ASSERT_NOT_NULL(token); + if (_token->magic != FPGA_TOKEN_MAGIC) { + FPGA_MSG("Invalid token"); + return FPGA_INVALID_PARAM; + } + + ASSERT_NOT_NULL(_prop); + if (_prop->magic != FPGA_PROPERTY_MAGIC) { + FPGA_MSG("Invalid properties object"); + return FPGA_INVALID_PARAM; + } + + //clear fpga_properties buffer + memset(&_iprop, 0, sizeof(struct _fpga_properties)); + _iprop.magic = FPGA_PROPERTY_MAGIC; + + // The input token is either for an FME or an AFU. + // Go one level back to get to the dev. + + e = strncpy_s(spath, sizeof(spath), + _token->sysfspath, sizeof(_token->sysfspath)); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + return FPGA_EXCEPTION; + } + + p = strrchr(spath, '/'); + ASSERT_NOT_NULL_MSG(p, "Invalid token sysfs path"); + + *p = 0; + + // Isolate the dev number. + p = strrchr(spath, '.'); + ASSERT_NOT_NULL_MSG(p, "Invalid token sysfs path"); + + device_id = atoi(p+1); + + p = strstr(_token->sysfspath, FPGA_SYSFS_AFU); + if (NULL != p) { + // AFU + result = sysfs_get_afu_id(device_id, _iprop.guid); + if (FPGA_OK != result) + return result; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_GUID); + + _iprop.parent = (fpga_token) token_get_parent(_token); + if (NULL != _iprop.parent) + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_PARENT); + + _iprop.objtype = FPGA_ACCELERATOR; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_OBJTYPE); + + res = open(_token->devpath, O_RDWR); + if (-1 == res) { + _iprop.u.accelerator.state = FPGA_ACCELERATOR_ASSIGNED; + } else { + close(res); + _iprop.u.accelerator.state = FPGA_ACCELERATOR_UNASSIGNED; + } + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_ACCELERATOR_STATE); + + _iprop.u.accelerator.num_mmio = 2; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_NUM_MMIO); + + _iprop.u.accelerator.num_interrupts = 0; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_NUM_INTERRUPTS); + } + + p = strstr(_token->sysfspath, FPGA_SYSFS_FME); + if (NULL != p) { + // FME + _iprop.objtype = FPGA_DEVICE; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_OBJTYPE); + // get bitstream id + result = sysfs_get_pr_id(device_id, _iprop.guid); + if (FPGA_OK != result) + return result; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_GUID); + + result = sysfs_get_slots(device_id, &_iprop.u.fpga.num_slots); + if (FPGA_OK != result) + return result; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_NUM_SLOTS); + + result = sysfs_get_bitstream_id(device_id, &_iprop.u.fpga.bbs_id); + if (FPGA_OK != result) + return result; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_BBSID); + + _iprop.u.fpga.bbs_version.major = + FPGA_BBS_VER_MAJOR(_iprop.u.fpga.bbs_id); + _iprop.u.fpga.bbs_version.minor = + FPGA_BBS_VER_MINOR(_iprop.u.fpga.bbs_id); + _iprop.u.fpga.bbs_version.patch = + FPGA_BBS_VER_PATCH(_iprop.u.fpga.bbs_id); + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_BBSVERSION); + } + + result = sysfs_bdf_from_path(spath, &b, &d, &f); + if (result) + return result; + + _iprop.bus = (uint8_t) b; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_BUS); + + _iprop.device = (uint8_t) d; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_DEVICE); + + _iprop.function = (uint8_t) f; + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_FUNCTION); + + result = sysfs_get_socket_id(device_id, &_iprop.socket_id); + if (result) + return result; + + SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_SOCKETID); + + // _iprop.device_id = ?? ; + // SET_FIELD_VALID(&_iprop, FPGA_PROPERTY_DEVICEID); + + if (pthread_mutex_lock(&_prop->lock)) { + FPGA_MSG("Failed to lock properties mutex"); + return FPGA_EXCEPTION; + } + + lock = _prop->lock; + *_prop = _iprop; + _prop->lock = lock; + + pthread_mutex_unlock(&_prop->lock); + + return FPGA_OK; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetParent(const fpga_properties prop, fpga_token *parent) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(parent); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_PARENT)) { + result = fpgaCloneToken(_prop->parent, parent); + if (FPGA_OK != result) + FPGA_MSG("Error cloning token from property"); + } else { + FPGA_MSG("No parent"); + result = FPGA_NOT_FOUND; + } + + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetParent(fpga_properties prop, fpga_token parent) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->parent = parent; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_PARENT); + + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetObjectType(const fpga_properties prop, fpga_objtype *objtype) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(objtype); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE)) { + *objtype = _prop->objtype; + } else { + FPGA_MSG("No object type"); + result = FPGA_NOT_FOUND; + } + + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetObjectType(fpga_properties prop, fpga_objtype objtype) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->objtype = objtype; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE); + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaPropertiesGetBus(const fpga_properties prop, uint8_t *bus) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(bus); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_BUS)) { + *bus = _prop->bus; + } else { + FPGA_MSG("No bus"); + result = FPGA_NOT_FOUND; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ fpgaPropertiesSetBus(fpga_properties prop, uint8_t bus) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->bus = bus; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BUS); + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetDevice(const fpga_properties prop, uint8_t *device) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(device); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_DEVICE)) { + *device = _prop->device; + } else { + FPGA_MSG("No device"); + result = FPGA_NOT_FOUND; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ fpgaPropertiesSetDevice(fpga_properties prop, uint8_t device) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + // PCIe supports 32 devices per bus. + if (device > 31) { + FPGA_MSG("Invalid device number"); + return FPGA_INVALID_PARAM; + } + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->device = device; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_DEVICE); + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetFunction(const fpga_properties prop, uint8_t *function) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(function); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_FUNCTION)) { + *function = _prop->function; + } else { + FPGA_MSG("No function"); + result = FPGA_NOT_FOUND; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesSetFunction(fpga_properties prop, uint8_t function) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + // PCIe supports 8 functions per device. + if (function > 7) { + FPGA_MSG("Invalid function number"); + return FPGA_INVALID_PARAM; + } + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->function = function; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_FUNCTION); + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetSocketID(const fpga_properties prop, uint8_t *socket_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(socket_id); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_SOCKETID)) { + *socket_id = _prop->socket_id; + } else { + FPGA_MSG("No socket ID"); + result = FPGA_NOT_FOUND; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetSocketID(fpga_properties prop, uint8_t socket_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + _prop->socket_id = socket_id; + SET_FIELD_VALID(_prop, FPGA_PROPERTY_SOCKETID); + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetDeviceID(const fpga_properties prop, uint32_t *device_id) +{ + FPGA_MSG("Device ID not yet supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetDeviceID(fpga_properties prop, uint32_t device_id) +{ + FPGA_MSG("Device ID not yet supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumSlots(const fpga_properties prop, uint32_t *num_slots) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(num_slots); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_SLOTS)) { + *num_slots = _prop->u.fpga.num_slots; + } else { + FPGA_MSG("No number of slots"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get num_slots from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumSlots(fpga_properties prop, uint32_t num_slots) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_SLOTS); + _prop->u.fpga.num_slots = num_slots; + } else { + FPGA_ERR + ("Attempting to set num_slots from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetBBSID(const fpga_properties prop, uint64_t *bbs_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(bbs_id); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_BBSID)) { + *bbs_id = _prop->u.fpga.bbs_id; + } else { + FPGA_MSG("No BBS ID"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get BBS ID from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetBBSID(fpga_properties prop, uint64_t bbs_id) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BBSID); + _prop->u.fpga.bbs_id = bbs_id; + } else { + FPGA_ERR + ("Attempting to set BBS ID from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + + +fpga_result __FPGA_API__ +fpgaPropertiesGetBBSVersion(const fpga_properties prop, + fpga_version *bbs_version) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(bbs_version); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_BBSVERSION)) { + *bbs_version = _prop->u.fpga.bbs_version; + } else { + FPGA_MSG("No BBS version"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get BBS version from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetBBSVersion(fpga_properties prop, + fpga_version bbs_version) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_DEVICE == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_BBSVERSION); + _prop->u.fpga.bbs_version = bbs_version; + } else { + FPGA_ERR + ("Attempting to set BBS version from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetVendorID(const fpga_properties prop, + uint16_t *vendor_id) +{ + FPGA_MSG("Vendor ID not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetVendorID(fpga_properties prop, uint16_t vendor_id) +{ + FPGA_MSG("Vendor ID not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetModel(const fpga_properties prop, char *model) +{ + FPGA_MSG("Model not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetModel(fpga_properties prop, char *model) +{ + FPGA_MSG("Model not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetLocalMemorySize(const fpga_properties prop, + uint64_t *local_memory_size) +{ + FPGA_MSG("Local memory not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetLocalMemorySize(fpga_properties prop, + uint64_t local_memory_size) +{ + FPGA_MSG("Local memory not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetCapabilities(const fpga_properties prop, + uint64_t *capabilities) +{ + FPGA_MSG("Capabilities not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetCapabilities(fpga_properties prop, + uint64_t capabilities) +{ + FPGA_MSG("Capabilities not supported"); + return FPGA_NOT_SUPPORTED; +} + +fpga_result __FPGA_API__ fpgaPropertiesGetGUID(const fpga_properties prop, fpga_guid *guid) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(guid); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_GUID)) { + errno_t e; + e = memcpy_s(*guid, sizeof(fpga_guid), + _prop->guid, sizeof(fpga_guid)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + } else { + result = FPGA_OK; + } + } else { + FPGA_MSG("No GUID"); + result = FPGA_NOT_FOUND; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ fpgaPropertiesSetGUID(fpga_properties prop, fpga_guid guid) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + errno_t e; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + SET_FIELD_VALID(_prop, FPGA_PROPERTY_GUID); + e = memcpy_s(_prop->guid, sizeof(fpga_guid), + guid, sizeof(fpga_guid)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + result = FPGA_EXCEPTION; + } else { + result = FPGA_OK; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumMMIO(const fpga_properties prop, uint32_t *mmio_spaces) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(mmio_spaces); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_MMIO)) { + *mmio_spaces = _prop->u.accelerator.num_mmio; + } else { + FPGA_MSG("No MMIO spaces"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get number of MMIO spaces from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumMMIO(fpga_properties prop, uint32_t mmio_spaces) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_MMIO); + _prop->u.accelerator.num_mmio = mmio_spaces; + } else { + FPGA_ERR + ("Attempting to set number of MMIO spaces on invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetNumInterrupts(const fpga_properties prop, + uint32_t *num_interrupts) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(num_interrupts); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_NUM_INTERRUPTS)) { + *num_interrupts = _prop->u.accelerator.num_interrupts; + } else { + FPGA_MSG("No interrupts"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get number of interrupts from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetNumInterrupts(fpga_properties prop, + uint32_t num_interrupts) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_NUM_INTERRUPTS); + _prop->u.accelerator.num_interrupts = num_interrupts; + } else { + FPGA_ERR + ("Attempting to set number of interrupts from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesGetAcceleratorState(const fpga_properties prop, fpga_accelerator_state *state) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + ASSERT_NOT_NULL(state); + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + if (FIELD_VALID(_prop, FPGA_PROPERTY_ACCELERATOR_STATE)) { + *state = _prop->u.accelerator.state; + } else { + FPGA_MSG("No accelerator state"); + result = FPGA_NOT_FOUND; + } + } else { + FPGA_ERR + ("Attempting to get state from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + +fpga_result __FPGA_API__ +fpgaPropertiesSetAcceleratorState(fpga_properties prop, fpga_accelerator_state state) +{ + struct _fpga_properties *_prop = (struct _fpga_properties *)prop; + fpga_result result = FPGA_OK; + + result = prop_check_and_lock(_prop); + if (result) + return result; + + if (FIELD_VALID(_prop, FPGA_PROPERTY_OBJTYPE) + && FPGA_ACCELERATOR == _prop->objtype) { + SET_FIELD_VALID(_prop, FPGA_PROPERTY_ACCELERATOR_STATE); + _prop->u.accelerator.state = state; + } else { + FPGA_ERR + ("Attempting to set state from invalid object type: %d", + _prop->objtype); + result = FPGA_INVALID_PARAM; + } + +out_unlock: + pthread_mutex_unlock(&_prop->lock); + return result; +} + diff --git a/libopae/src/properties_int.h b/libopae/src/properties_int.h new file mode 100644 index 000000000000..e29d5db0d176 --- /dev/null +++ b/libopae/src/properties_int.h @@ -0,0 +1,66 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_PROPERTIES_INT_H__ +#define __FPGA_PROPERTIES_INT_H__ + +/** Fields common across all object types */ + +#define FPGA_PROPERTY_PARENT 0 +#define FPGA_PROPERTY_OBJTYPE 1 +#define FPGA_PROPERTY_BUS 2 +#define FPGA_PROPERTY_DEVICE 3 +#define FPGA_PROPERTY_FUNCTION 4 +#define FPGA_PROPERTY_SOCKETID 5 +#define FPGA_PROPERTY_DEVICEID 6 +#define FPGA_PROPERTY_GUID 7 + +/** Fields for FPGA objects */ +#define FPGA_PROPERTY_NUM_SLOTS 32 +#define FPGA_PROPERTY_BBSID 33 +#define FPGA_PROPERTY_BBSVERSION 34 +#define FPGA_PROPERTY_VENDORID 35 +#define FPGA_PROPERTY_MODEL 36 +#define FPGA_PROPERTY_LOCAL_MEMORY 37 +#define FPGA_PROPERTY_CAPABILITIES 38 + + +/** Fields for accelerator objects */ +#define FPGA_PROPERTY_ACCELERATOR_STATE 32 +#define FPGA_PROPERTY_NUM_MMIO 33 +#define FPGA_PROPERTY_NUM_INTERRUPTS 34 + + +#define FIELD_VALID(P, F) (((P)->valid_fields >> (F)) & 1) + +#define SET_FIELD_VALID(P, F)\ + ((P)->valid_fields = (P)->valid_fields | ((uint64_t)1 << (F))) + +#define CLEAR_FIELD_VALID(P, F)\ + ((P)->valid_fields = (P)->valid_fields & ~((uint64_t)1 << (F))) + +#endif // __FPGA_PROPERTIES_INT_H__ + diff --git a/libopae/src/reconf.c b/libopae/src/reconf.c new file mode 100644 index 000000000000..591506c27901 --- /dev/null +++ b/libopae/src/reconf.c @@ -0,0 +1,430 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include +#include + +#include "safe_string/safe_string.h" + +#include "opae/access.h" +#include "opae/utils.h" +#include "opae/manage.h" +#include "opae/manage.h" +#include "bitstream_int.h" +#include "common_int.h" +#include "intel-fpga.h" +#include "usrclk/user_clk_pgm_uclock.h" + +// sysfs attributes +#define PORT_SYSFS_ERRORS "errors/errors" +#define PORT_SYSFS_ERR_CLEAR "errors/clear" +#define PWRMGMT_THRESHOLD1 "power_mgmt/threshold1" +#define PWRMGMT_THRESHOLD2 "power_mgmt/threshold2" + +// Max power values +#define FPGA_BBS_IDLE_POWER 30 // watts +#define FPGA_MAX_POWER 90 // watts +#define FPGA_GBS_MAX_POWER 60 // watts +#define FPGA_THRESHOLD2(x) ((x*10)/100) // threshold1 + 10% + +#pragma pack(push, 1) +// GBS Header +struct bitstream_header { + uint32_t magic; + uint64_t ifid_l; + uint64_t ifid_h; +}; +#pragma pack(pop) + +// Reconnfigure Error CSR +struct reconf_error { + union { + uint64_t csr; + struct { + uint64_t reconf_operation_error:1; /* PR operation error detected */ + uint64_t reconf_CRC_error:1; /* PR CRC error detected*/ + uint64_t reconf_incompatible_bitstream_error:1; /* PR incompatible bitstream error detected */ + uint64_t reconf_IP_protocol_error:1; /* PR IP protocol error detected */ + uint64_t reconf_FIFO_overflow_error:1; /* PR FIFO overflow error detected */ + uint64_t reconf_timeout_error:1; /* PR timeout error detected */ + uint64_t reconf_secure_load_error:1; /* PR secure load error detected */ + uint64_t rsvd:57; /* Reserved */ + }; + }; +}; + + +static fpga_result validate_bitstream(fpga_handle handle, + const uint8_t *bitstream, size_t bitstream_len, + int *header_len) +{ + struct bitstream_header bts_hdr = {0}; + + if (bitstream == NULL) { + FPGA_MSG("Bitstream is NULL"); + return FPGA_INVALID_PARAM; + } + + if (bitstream_len <= 0 || + bitstream_len <= sizeof(struct bitstream_header)) { + FPGA_MSG("Invalid bitstream size"); + return FPGA_INVALID_PARAM; + } + + if (check_bitstream_guid(bitstream) == FPGA_OK) { + *header_len = get_bitstream_header_len(bitstream); + + if (*header_len < 0) { + FPGA_MSG("Invalid bitstream header length"); + return FPGA_EXCEPTION; + } + + if (validate_bitstream_metadata(handle, bitstream) != FPGA_OK) { + FPGA_MSG("Invalid JSON data"); + return FPGA_EXCEPTION; + } + + return FPGA_OK; + } else { + errno_t e; + // TODO: This is needed for legacy bitstreams since they + // do not have new metadata with GUID. Remove once + // all bitstreams conform to new metadata format. + *header_len = sizeof(struct bitstream_header); + e = memcpy_s(&bts_hdr, sizeof(struct bitstream_header), + bitstream, sizeof(struct bitstream_header)); + if (EOK != e) { + FPGA_ERR("memcpy_s failed"); + return FPGA_EXCEPTION; + } + + return check_interface_id(handle, bts_hdr.magic, bts_hdr.ifid_l, + bts_hdr.ifid_h); + } +} + + +// clears port errors +static fpga_result clear_port_errors(fpga_handle handle) +{ + char syfs_path[SYSFS_PATH_MAX] = {0}; + char syfs_errpath[SYSFS_PATH_MAX] = {0}; + fpga_result result = FPGA_OK; + uint64_t error = 0 ; + + result = get_port_sysfs(handle, syfs_path); + if (result != FPGA_OK) { + FPGA_ERR("Failed to get port syfs path"); + return result; + } + + snprintf(syfs_errpath, sizeof(syfs_errpath), "%s/%s", syfs_path, PORT_SYSFS_ERRORS); + // Read port error. + result = sysfs_read_u64(syfs_errpath, &error); + if (result != FPGA_OK) { + FPGA_ERR("Failed to get port errors"); + return result; + } + + snprintf(syfs_errpath, sizeof(syfs_errpath), "%s/%s", syfs_path, PORT_SYSFS_ERR_CLEAR); + // Clear port error. + result = sysfs_write_u64(syfs_errpath, error); + if (result != FPGA_OK) { + FPGA_ERR("Failed to clear port errors"); + return result; + } + + return result; +} + +// set afu user clock +fpga_result set_afu_userclock(fpga_handle handle, + uint64_t usrlclock_high, + uint64_t usrlclock_low) +{ + char syfs_path[SYSFS_PATH_MAX] = {0}; + fpga_result result = FPGA_OK; + uint64_t userclk_high = 0; + uint64_t userclk_low = 0; + + // Read port sysfs path + result = get_port_sysfs(handle, syfs_path); + if (result != FPGA_OK) { + FPGA_ERR("Failed to get port syfs path"); + return result; + } + + // set user clock + result = set_userclock(syfs_path, usrlclock_high, usrlclock_low); + if (result != FPGA_OK) { + FPGA_ERR("Failed to set user clock"); + return result; + } + + // read user clock + result = get_userclock(syfs_path, &userclk_high, &userclk_low); + if (result != FPGA_OK) { + FPGA_ERR("Failed to get user clock"); + return result; + } + + return result; +} + +// Sets FPGA threshold power values +fpga_result set_fpga_pwr_threshold(fpga_handle handle, + uint64_t gbs_power) +{ + char sysfs_path[SYSFS_PATH_MAX] = {0}; + fpga_result result = FPGA_OK; + uint64_t fpga_power = 0; + struct _fpga_token *_token = NULL; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + + if (_handle == NULL) { + FPGA_ERR("Invalid handle"); + return FPGA_INVALID_PARAM; + } + + _token = (struct _fpga_token *)_handle->token; + if (_token == NULL) { + FPGA_ERR("Invalid token within handle"); + return FPGA_INVALID_PARAM; + } + + if (gbs_power == 0) { + FPGA_ERR("GBS power value is 0"); + return FPGA_INVALID_PARAM; + } + + // verify gbs power limits + if (gbs_power > FPGA_GBS_MAX_POWER) { + FPGA_ERR("Invalid GBS power value"); + result = FPGA_NOT_SUPPORTED; + return result; + } + + // FPGA threshold1 = BBS Idle power + GBS power + fpga_power = gbs_power + FPGA_BBS_IDLE_POWER; + if (fpga_power > FPGA_MAX_POWER) { + FPGA_ERR("Total power requirements exceed FPGA maximum"); + result = FPGA_NOT_SUPPORTED; + return result; + } + + // set fpga threshold 1 + snprintf(sysfs_path, sizeof(sysfs_path), "%s/%s", _token->sysfspath, PWRMGMT_THRESHOLD1); + FPGA_DBG(" FPGA Threshold1 :%ld watts\n", fpga_power); + + result = sysfs_write_u64(sysfs_path, fpga_power); + if (result != FPGA_OK) { + FPGA_ERR("Failed to write power threshold 1"); + return result; + } + + // FIXME Fix threshold2 calculation. + // FPGA threshold2 = 110% (FPGA threshold1) + fpga_power = fpga_power + FPGA_THRESHOLD2(fpga_power); + if (fpga_power > FPGA_MAX_POWER) { + FPGA_ERR("Invalid power threshold 2"); + result = FPGA_NOT_SUPPORTED; + return result; + } + + // set fpga threshold 2 + snprintf(sysfs_path, sizeof(sysfs_path), "%s/%s", _token->sysfspath, PWRMGMT_THRESHOLD2); + FPGA_DBG(" FPGA Threshold2 :%ld watts\n", fpga_power); + + result = sysfs_write_u64(sysfs_path, fpga_power); + if (result != FPGA_OK) { + FPGA_ERR("Failed to write power threshold 2"); + return result; + } + + return result; +} + +fpga_result __FPGA_API__ fpgaReconfigureSlot(fpga_handle fpga, + uint32_t slot, + const uint8_t *bitstream, + size_t bitstream_len, + int flags) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)fpga; + fpga_result result = FPGA_OK; + struct fpga_fme_port_pr port_pr = {0}; + struct reconf_error error = {0}; + struct gbs_metadata metadata = {0}; + int bitstream_header_len = 0; + uint64_t deviceid = 0; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + if (validate_bitstream(fpga, bitstream, bitstream_len, + &bitstream_header_len) != FPGA_OK) { + FPGA_MSG("Invalid bitstream"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // Clear port errors + result = clear_port_errors(fpga); + if (result != FPGA_OK) { + FPGA_ERR("Failed to clear port errors."); + } + + if (get_bitstream_json_len(bitstream) > 0) { + + // Read GBS json metadata + result = read_gbs_metadata(bitstream, &metadata); + if (result != FPGA_OK) { + FPGA_ERR("Failed to read metadata"); + goto out_unlock; + } + + FPGA_DBG(" Version :%f\n", metadata.version); + FPGA_DBG(" Magic Num :%ld\n", + metadata.afu_image.magic_num); + FPGA_DBG(" Interface Id :%s\n", + metadata.afu_image.interface_uuid); + FPGA_DBG(" Clock_frequency_high :%d\n", + metadata.afu_image.clock_frequency_high); + FPGA_DBG(" Clock_frequency_low :%d\n", + metadata.afu_image.clock_frequency_low); + FPGA_DBG(" Power :%d\n", + metadata.afu_image.power); + FPGA_DBG(" Name :%s\n", + metadata.afu_image.afu_clusters.name); + FPGA_DBG(" Total_contexts :%d\n", + metadata.afu_image.afu_clusters.total_contexts); + FPGA_DBG(" AFU_uuid :%s\n", + metadata.afu_image.afu_clusters.afu_uuid); + + // Set AFU user clock + if (metadata.afu_image.clock_frequency_high > 0 && metadata.afu_image.clock_frequency_low > 0) { + result = set_afu_userclock(fpga, metadata.afu_image.clock_frequency_high, metadata.afu_image.clock_frequency_low); + if (result != FPGA_OK) { + FPGA_ERR("Failed to set user clock"); + goto out_unlock; + } + } + + // get fpga device id. + result = get_fpga_deviceid(fpga, &deviceid); + if (result != FPGA_OK) { + FPGA_ERR("Failed to read device id."); + goto out_unlock; + } + + // Set power threshold for integrated fpga. + if (deviceid == FPGA_INTEGRATED_DEVICEID) { + + result = set_fpga_pwr_threshold(fpga, metadata.afu_image.power); + if (result != FPGA_OK) { + FPGA_ERR("Failed to set threshold."); + goto out_unlock; + } + + } // device id + + } + + port_pr.flags = 0; + port_pr.argsz = sizeof(struct fpga_fme_port_pr); + port_pr.buffer_address = (__u64)bitstream + bitstream_header_len; + port_pr.buffer_size = (__u32) bitstream_len - bitstream_header_len; + port_pr.port_id = slot; + + result = ioctl(_handle->fddev, FPGA_FME_PORT_PR, &port_pr); + if (result != 0) { + FPGA_MSG("Failed to reconfigure bitstream"); + + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + goto out_unlock; + } + + // PR error + error.csr = port_pr.status; + + if (error.reconf_operation_error == 0x1) { + FPGA_MSG("PR operation error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_CRC_error == 0x1) { + FPGA_MSG("PR CRC error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_incompatible_bitstream_error == 0x1) { + FPGA_MSG("PR incompatible bitstream error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_IP_protocol_error == 0x1) { + FPGA_MSG("PR IP protocol error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_FIFO_overflow_error == 0x1) { + FPGA_MSG("PR FIFO overflow error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_timeout_error == 0x1) { + FPGA_MSG("PR timeout error detected"); + result = FPGA_RECONF_ERROR; + } + + if (error.reconf_secure_load_error == 0x1) { + FPGA_MSG("PR secure load error detected"); + result = FPGA_RECONF_ERROR; + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} diff --git a/libopae/src/reconf_int.h b/libopae/src/reconf_int.h new file mode 100644 index 000000000000..a593b634ca09 --- /dev/null +++ b/libopae/src/reconf_int.h @@ -0,0 +1,74 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __RECONF_INT_H__ +#define __RECONF_INT_H__ + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + + +#include + +#include "opae/access.h" +#include "opae/utils.h" +#include "opae/manage.h" +#include "common_int.h" + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** +* @brief set afu user clock +* +* @param handle +* @param usrlclock_high user clock low frequency +* @param usrlclock_low user clock high frequency +* +* @return error code +*/ +fpga_result set_afu_userclock(fpga_handle handle, + uint64_t usrlclock_high, + uint64_t usrlclock_low); + +/** +* @brief Sets FPGA power threshold values +* +* @param fpga handle +* @param gbs_power gbs power value +* +* @return error code +*/ +fpga_result set_fpga_pwr_threshold(fpga_handle handle, + uint64_t gbs_power); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // __RECONF_INT_H__ diff --git a/libopae/src/reset.c b/libopae/src/reset.c new file mode 100644 index 000000000000..70fde46d693d --- /dev/null +++ b/libopae/src/reset.c @@ -0,0 +1,63 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + + +#include "opae/access.h" +#include "opae/utils.h" +#include "common_int.h" +#include "intel-fpga.h" + +// Reset slot +fpga_result __FPGA_API__ fpgaReset(fpga_handle handle) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // reset ioctl + result = ioctl(_handle->fddev, FPGA_PORT_RESET, NULL); + if (result != 0) { + FPGA_MSG("Reset failed"); + result = FPGA_EXCEPTION; + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} diff --git a/libopae/src/sysfs.c b/libopae/src/sysfs.c new file mode 100644 index 000000000000..57efe5f53d25 --- /dev/null +++ b/libopae/src/sysfs.c @@ -0,0 +1,530 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "types_int.h" +#include "sysfs_int.h" +#include "log_int.h" +#include "common_int.h" + +// +// sysfs access (read/write) functions +// + +fpga_result sysfs_read_int(const char *path, int *i) +{ + int fd; + int res; + char buf[SYSFS_PATH_MAX]; + int b; + + fd = open(path, O_RDONLY); + if (fd < 0) { + FPGA_MSG("open(%s) failed", path); + return FPGA_NOT_FOUND; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek failed"); + goto out_close; + } + + b = 0; + + do { + res = read(fd, buf+b, sizeof(buf)-b); + if (res <= 0) { + FPGA_MSG("Read from %s failed", path); + goto out_close; + } + b += res; + if ((b > sizeof(buf)) || (b <= 0)) { + FPGA_MSG("Unexpected size reading from %s", path); + goto out_close; + } + } while (buf[b-1] != '\n' && buf[b-1] != '\0' && b < sizeof(buf)); + + // erase \n + buf[b-1] = 0; + + *i = atoi(buf); + + close(fd); + return FPGA_OK; + +out_close: + close(fd); + return FPGA_NOT_FOUND; +} + +fpga_result sysfs_read_u32(const char *path, uint32_t *u) +{ + int fd; + int res; + char buf[SYSFS_PATH_MAX]; + int b; + + fd = open(path, O_RDONLY); + if (fd < 0) { + FPGA_MSG("open(%s) failed", path); + return FPGA_NOT_FOUND; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek failed"); + goto out_close; + } + + b = 0; + + do { + res = read(fd, buf+b, sizeof(buf)-b); + if (res <= 0) { + FPGA_MSG("Read from %s failed", path); + goto out_close; + } + b += res; + if ((b > sizeof(buf)) || (b <= 0)) { + FPGA_MSG("Unexpected size reading from %s", path); + goto out_close; + } + } while (buf[b-1] != '\n' && buf[b-1] != '\0' && b < sizeof(buf)); + + // erase \n + buf[b-1] = 0; + + *u = strtoul(buf, NULL, 0); + + close(fd); + return FPGA_OK; + +out_close: + close(fd); + return FPGA_NOT_FOUND; +} + +fpga_result __FIXME_MAKE_VISIBLE__ sysfs_read_u64(const char *path, uint64_t *u) +{ + int fd = -1; + int res = 0; + char buf[SYSFS_PATH_MAX] = {0}; + int b = 0; + + fd = open(path, O_RDONLY); + if (fd < 0) { + FPGA_MSG("open(%s) failed", path); + return FPGA_NOT_FOUND; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek failed"); + goto out_close; + } + + do { + res = read(fd, buf+b, sizeof(buf)-b); + if (res <= 0) { + FPGA_MSG("Read from %s failed", path); + goto out_close; + } + b += res; + if ((b > sizeof(buf)) || (b <= 0)) { + FPGA_MSG("Unexpected size reading from %s", path); + goto out_close; + } + } while (buf[b-1] != '\n' && buf[b-1] != '\0' && b < sizeof(buf)); + + // erase \n + buf[b-1] = 0; + + *u = strtoull(buf, NULL, 0); + + close(fd); + return FPGA_OK; + +out_close: + close(fd); + return FPGA_NOT_FOUND; +} + +fpga_result __FIXME_MAKE_VISIBLE__ sysfs_write_u64(const char *path, uint64_t u) +{ + int fd = -1; + int res = 0; + char buf[SYSFS_PATH_MAX] = {0}; + int b = 0; + + fd = open(path, O_WRONLY); + if (fd < 0) { + FPGA_MSG("open: %s", strerror(errno)); + return FPGA_NOT_FOUND; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek: %s", strerror(errno)); + goto out_close; + } + + snprintf(buf, sizeof(buf), "0x%lx", u); + + do { + res = write(fd, buf + b, sizeof(buf) -b); + if (res <= 0) { + FPGA_ERR("Failed to write"); + goto out_close; + } + b += res; + + if (b > sizeof(buf) || b <= 0) { + FPGA_MSG("Unexpected size reading from %s", path); + goto out_close; + } + + } while (buf[b - 1] != '\n' && buf[b - 1] != '\0' && b < sizeof(buf)); + + close(fd); + return FPGA_OK; + +out_close: + close(fd); + return FPGA_NOT_FOUND; +} + +fpga_result sysfs_read_guid(const char *path, fpga_guid guid) +{ + int fd; + int res; + char buf[SYSFS_PATH_MAX]; + int b; + + int i; + char tmp; + unsigned octet; + + fd = open(path, O_RDONLY); + if (fd < 0) { + FPGA_MSG("open(%s) failed", path); + return FPGA_NOT_FOUND; + } + + if ((off_t)-1 == lseek(fd, 0, SEEK_SET)) { + FPGA_MSG("seek failed"); + goto out_close; + } + + b = 0; + + do { + res = read(fd, buf+b, sizeof(buf)-b); + if (res <= 0) { + FPGA_MSG("Read from %s failed", path); + goto out_close; + } + b += res; + if ((b > sizeof(buf)) || (b <= 0)) { + FPGA_MSG("Unexpected size reading from %s", path); + goto out_close; + } + } while (buf[b-1] != '\n' && buf[b-1] != '\0' && b < sizeof(buf)); + + // erase \n + buf[b-1] = 0; + + for (i = 0 ; i < 32 ; i += 2) { + tmp = buf[i+2]; + buf[i+2] = 0; + + octet = 0; + sscanf(&buf[i], "%x", &octet); + guid[i/2] = (uint8_t) octet; + + buf[i+2] = tmp; + } + + close(fd); + return FPGA_OK; + +out_close: + close(fd); + return FPGA_NOT_FOUND; +} + +// +// sysfs convenience functions to access device components by device number +// + +// FIXME: uses same number for device and FME (may not be true in future) +fpga_result sysfs_get_socket_id(int dev, uint8_t *socket_id) +{ + fpga_result result; + char spath[SYSFS_PATH_MAX]; + int i; + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_FME_PATH_FMT "/" + FPGA_SYSFS_SOCKET_ID, + dev, dev); + + i = 0; + result = sysfs_read_int(spath, &i); + if (FPGA_OK != result) + return result; + + *socket_id = (uint8_t) i; + + return FPGA_OK; +} + +// FIXME: uses same number for device and PORT (may not be true in future) +fpga_result sysfs_get_afu_id(int dev, fpga_guid guid) +{ + char spath[SYSFS_PATH_MAX]; + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_AFU_PATH_FMT "/" + FPGA_SYSFS_AFU_GUID, + dev, dev); + + return sysfs_read_guid(spath, guid); +} + +fpga_result sysfs_get_pr_id(int dev, fpga_guid guid) +{ + char spath[SYSFS_PATH_MAX]; + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_FME_PATH_FMT "/" + FPGA_SYSFS_FME_INTERFACE_ID, + dev, dev); + + return sysfs_read_guid(spath, guid); +} + +// FIXME: uses same number for device and FME (may not be true in future) +fpga_result sysfs_get_slots(int dev, uint32_t *slots) +{ + char spath[SYSFS_PATH_MAX]; + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_FME_PATH_FMT "/" + FPGA_SYSFS_NUM_SLOTS, + dev, dev); + + return sysfs_read_u32(spath, slots); +} + +// FIXME: uses same number for device and FME (may not be true in future) +fpga_result sysfs_get_bitstream_id(int dev, uint64_t *id) +{ + char spath[SYSFS_PATH_MAX]; + + snprintf(spath, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH + SYSFS_FME_PATH_FMT "/" + FPGA_SYSFS_BITSTREAM_ID, + dev, dev); + + return sysfs_read_u64(spath, id); +} + +// Get port syfs path +fpga_result get_port_sysfs(fpga_handle handle, + char *sysfs_port) +{ + struct _fpga_token *_token; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + char syfs_path[SYSFS_PATH_MAX] = {0}; + char *p = 0; + int device_id = 0; + + if (sysfs_port == NULL) { + FPGA_ERR("Invalid output pointer"); + return FPGA_INVALID_PARAM; + } + + if (_handle == NULL) { + FPGA_ERR("Invalid handle"); + return FPGA_INVALID_PARAM; + } + + _token = (struct _fpga_token *)_handle->token; + if (_token == NULL) { + FPGA_ERR("Token not found"); + return FPGA_INVALID_PARAM; + } + + p = strstr(_token->sysfspath, FPGA_SYSFS_FME); + if (NULL == p) { + FPGA_ERR("Invalid sysfspath in token"); + return FPGA_INVALID_PARAM; + } + p = strrchr(_token->sysfspath, '.'); + if (NULL == p) { + FPGA_ERR("Invalid sysfspath in token"); + return FPGA_INVALID_PARAM; + } + + device_id = atoi(p + 1); + + snprintf(sysfs_port, SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH SYSFS_AFU_PATH_FMT, + device_id, device_id); + + return FPGA_OK; +} + +// get fpga device id +fpga_result get_fpga_deviceid(fpga_handle handle, + uint64_t *deviceid) +{ + struct _fpga_token *_token = NULL; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + char sysfs_path[SYSFS_PATH_MAX] = {0}; + char *p = NULL; + int device_id = 0; + fpga_result result = FPGA_OK; + + if (_handle == NULL) { + FPGA_ERR("Invalid handle"); + return FPGA_INVALID_PARAM; + } + + if (deviceid == NULL) { + FPGA_ERR("Invalid input Parameters"); + return FPGA_INVALID_PARAM; + } + + if (pthread_mutex_lock(&_handle->lock)) { + FPGA_MSG("Failed to lock handle mutex"); + return FPGA_EXCEPTION; + } + + _token = (struct _fpga_token *)_handle->token; + if (_token == NULL) { + FPGA_ERR("Token not found"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + p = strstr(_token->sysfspath, FPGA_SYSFS_FME); + if (p == NULL) { + FPGA_ERR("Failed to read sysfs path"); + result = FPGA_NOT_SUPPORTED; + goto out_unlock; + } + + p = strrchr(_token->sysfspath, '.'); + if (p == NULL) { + FPGA_ERR("Failed to read sysfs path"); + result = FPGA_NOT_SUPPORTED; + goto out_unlock; + } + + device_id = atoi(p + 1); + + snprintf(sysfs_path, + SYSFS_PATH_MAX, + SYSFS_FPGA_CLASS_PATH SYSFS_FPGA_FMT"/%s", + device_id, + FPGA_SYSFS_DEVICEID); + + result = sysfs_read_u64(sysfs_path, deviceid); + if (result != 0) { + FPGA_ERR("Failed to read device ID"); + goto out_unlock; + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +/* + * The rlpath path is assumed to be of the form: + * ../../devices/pci0000:5e/0000:5e:00.0/fpga/intel-fpga-dev.0 + */ +fpga_result sysfs_bdf_from_path(const char *sysfspath, int *b, int *d, int *f) +{ + int res; + char rlpath[SYSFS_PATH_MAX]; + char *p; + + res = readlink(sysfspath, rlpath, sizeof(rlpath)); + if (-1 == res) { + FPGA_MSG("Can't read link %s (no driver?)", sysfspath); + return FPGA_NO_DRIVER; + } + + // Find the BDF from the link path. + rlpath[res] = 0; + p = strrchr(rlpath, '/'); + if (!p) { + FPGA_MSG("Invalid link %s (no driver?)", rlpath); + return FPGA_NO_DRIVER; + } + *p = 0; + p = strrchr(rlpath, '/'); + if (!p) { + FPGA_MSG("Invalid link %s (no driver?)", rlpath); + return FPGA_NO_DRIVER; + } + *p = 0; + p = strrchr(rlpath, '/'); + if (!p) { + FPGA_MSG("Invalid link %s (no driver?)", rlpath); + return FPGA_NO_DRIVER; + } + p += 6; + + // 0123456 + // bb:dd.f + *f = (int) strtoul(p+6, NULL, 16); + *(p + 5) = 0; + + *d = (int) strtoul(p+3, NULL, 16); + *(p + 2) = 0; + + *b = (int) strtoul(p, NULL, 16); + + return FPGA_OK; +} + diff --git a/libopae/src/sysfs_int.h b/libopae/src/sysfs_int.h new file mode 100644 index 000000000000..c315075606fb --- /dev/null +++ b/libopae/src/sysfs_int.h @@ -0,0 +1,82 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_SYSFS_INT_H__ +#define __FPGA_SYSFS_INT_H__ + +#include +#include + +#define SYSFS_PATH_MAX 256 +#define SYSFS_FPGA_CLASS_PATH "/sys/class/fpga" + +#define SYSFS_AFU_PATH_FMT "/intel-fpga-dev.%d/intel-fpga-port.%d" +#define SYSFS_FME_PATH_FMT "/intel-fpga-dev.%d/intel-fpga-fme.%d" + +// substring that identifies a sysfs directory as the FME device. +#define FPGA_SYSFS_FME "fme" +// substring that identifies a sysfs directory as the AFU device. +#define FPGA_SYSFS_AFU "port" +// name of the FME interface ID (GUID) sysfs node. +#define FPGA_SYSFS_FME_INTERFACE_ID "pr/interface_id" +// name of the AFU GUID sysfs node. +#define FPGA_SYSFS_AFU_GUID "afu_id" +// name of the socket id sysfs node. +#define FPGA_SYSFS_SOCKET_ID "socket_id" +// name of the number of slots sysfs node. +#define FPGA_SYSFS_NUM_SLOTS "ports_num" +// name of the bitstream id sysfs node. +#define FPGA_SYSFS_BITSTREAM_ID "bitstream_id" + +/** + * @brief Get BBS interface id + * + * @param handle + * @parm Interface id low pointer + * @parm Interface id high pointer + * + * @return + */ +fpga_result get_interface_id(fpga_handle handle, uint64_t *id_l, uint64_t *id_h); + +/* + * sysfs utility functions. + */ +fpga_result sysfs_bdf_from_path(const char *sysfspath, int *b, int *d, int *f); +fpga_result sysfs_read_int(const char *path, int *i); +fpga_result sysfs_read_u32(const char *path, uint32_t *u); +fpga_result sysfs_read_u64(const char *path, uint64_t *u); +fpga_result sysfs_write_u64(const char *path, uint64_t u); +fpga_result sysfs_read_guid(const char *path, fpga_guid guid); +fpga_result sysfs_get_socket_id(int dev, uint8_t *socket_id); +fpga_result sysfs_get_afu_id(int dev, fpga_guid guid); +fpga_result sysfs_get_pr_id(int dev, fpga_guid guid); +fpga_result sysfs_get_slots(int dev, uint32_t *slots); +fpga_result sysfs_get_bitstream_id(int dev, uint64_t *id); +fpga_result get_port_sysfs(fpga_handle handle, char *sysfs_port); +fpga_result get_fpga_deviceid(fpga_handle handle, uint64_t *deviceid); + +#endif // ___FPGA_SYSFS_INT_H__ diff --git a/libopae/src/token_list.c b/libopae/src/token_list.c new file mode 100644 index 000000000000..933bf4c789f6 --- /dev/null +++ b/libopae/src/token_list.c @@ -0,0 +1,177 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include + +#include "safe_string/safe_string.h" + +#include "token_list_int.h" + +/* global list of tokens we've seen */ +static struct token_map *token_root; +/* mutex to protect global data structures */ +extern pthread_mutex_t global_lock; + +/** + * @brief Add entry to linked list for tokens + * Will allocate memory (which is freed by token_cleanup()) + * + * @param sysfspath + * @param devpath + * + * @return + */ +struct _fpga_token *token_add(const char *sysfspath, const char *devpath) +{ + struct token_map *tmp; + errno_t e; + + pthread_mutex_lock(&global_lock); + + /* Prevent duplicate entries. */ + for (tmp = token_root ; NULL != tmp ; tmp = tmp->next) { + if ((0 == strncmp(sysfspath, tmp->_token.sysfspath, + SYSFS_PATH_MAX)) && + (0 == strncmp(devpath, tmp->_token.devpath, + DEV_PATH_MAX))) { + pthread_mutex_unlock(&global_lock); + return &tmp->_token; + } + } + + tmp = malloc(sizeof(struct token_map)); + if (!tmp) { + pthread_mutex_unlock(&global_lock); + return NULL; + } + + /* mark data structure as valid */ + tmp->_token.magic = FPGA_TOKEN_MAGIC; + + /* deep copy token data */ + e = strncpy_s(tmp->_token.sysfspath, sizeof(tmp->_token.sysfspath), + sysfspath, SYSFS_PATH_MAX); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + goto out_free; + } + + e = strncpy_s(tmp->_token.devpath, sizeof(tmp->_token.devpath), + devpath, DEV_PATH_MAX); + if (EOK != e) { + FPGA_ERR("strncpy_s failed"); + goto out_free; + } + + tmp->next = token_root; + token_root = tmp; + + pthread_mutex_unlock(&global_lock); + + return &tmp->_token; + +out_free: + free(tmp); + pthread_mutex_unlock(&global_lock); + return NULL; +} + +/** + * @ brief Find the token that is the parent of _t + * + * @param _t + * + * @return parent of _t, or NULL if not found. + */ +struct _fpga_token *token_get_parent(struct _fpga_token *_t) +{ + char *p; + char spath[SYSFS_PATH_MAX]; + int device_id; + struct token_map *itr; + + p = strstr(_t->sysfspath, FPGA_SYSFS_AFU); + if (!p) // FME objects have no parent. + return NULL; + + p = strrchr(_t->sysfspath, '.'); + if (!p) + return NULL; + + device_id = atoi(p+1); + + snprintf(spath, sizeof(spath), + SYSFS_FPGA_CLASS_PATH SYSFS_FME_PATH_FMT, + device_id, device_id); + + pthread_mutex_lock(&global_lock); + + for (itr = token_root ; NULL != itr ; itr = itr->next) { + if (0 == strncmp(spath, itr->_token.sysfspath, + SYSFS_PATH_MAX)) { + pthread_mutex_unlock(&global_lock); + return &itr->_token; + } + } + + pthread_mutex_unlock(&global_lock); + + return NULL; +} + +/* + * Clean up remaining entries in linked list + * Will delete all remaining entries + */ +void token_cleanup(void) +{ + pthread_mutex_lock(&global_lock); + + if (!token_root) + return; + + while (token_root->next) { + struct token_map *tmp = token_root; + token_root = token_root->next; + // invalidate magic (just in case) + tmp->_token.magic = FPGA_INVALID_MAGIC; + free(tmp); + } + + token_root->_token.magic = FPGA_INVALID_MAGIC; + free(token_root); + token_root = NULL; + + pthread_mutex_unlock(&global_lock); +} + diff --git a/libopae/src/token_list_int.h b/libopae/src/token_list_int.h new file mode 100644 index 000000000000..23e99aeddf50 --- /dev/null +++ b/libopae/src/token_list_int.h @@ -0,0 +1,41 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_TOKEN_LIST_INT_H__ +#define __FPGA_TOKEN_LIST_INT_H__ + +#include "types_int.h" +#include "log_int.h" +#include "token_list_int.h" + +/* + * token list structure manipulation functions + */ +struct _fpga_token *token_add(const char *sysfspath, const char *devpath); +struct _fpga_token *token_get_parent(struct _fpga_token *t); +void token_cleanup(void); + +#endif // ___FPGA_TOKEN_LIST_INT_H__ diff --git a/libopae/src/types_int.h b/libopae/src/types_int.h new file mode 100644 index 000000000000..a72527f4e42c --- /dev/null +++ b/libopae/src/types_int.h @@ -0,0 +1,188 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +/** + * \file types_int.h + * \brief Internal type definitions for FPGA API + */ + +#ifndef __FPGA_TYPES_INT_H__ +#define __FPGA_TYPES_INT_H__ + +#include +#include +#include +#include +#include +#include + +#define SYSFS_PATH_MAX 256 +#define SYSFS_FPGA_CLASS_PATH "/sys/class/fpga" +#define FPGA_DEV_PATH "/dev" + +#define SYSFS_AFU_PATH_FMT "/intel-fpga-dev.%d/intel-fpga-port.%d" +#define SYSFS_FME_PATH_FMT "/intel-fpga-dev.%d/intel-fpga-fme.%d" + +// substring that identifies a sysfs directory as the FME device. +#define FPGA_SYSFS_FME "fme" +// substring that identifies a sysfs directory as the AFU device. +#define FPGA_SYSFS_AFU "port" +// name of the FME interface ID (GUID) sysfs node. +#define FPGA_SYSFS_FME_INTERFACE_ID "pr/interface_id" +// name of the AFU GUID sysfs node. +#define FPGA_SYSFS_AFU_GUID "afu_id" +// name of the socket id sysfs node. +#define FPGA_SYSFS_SOCKET_ID "socket_id" +// name of the number of slots sysfs node. +#define FPGA_SYSFS_NUM_SLOTS "ports_num" +// name of the bitstream id sysfs node. +#define FPGA_SYSFS_BITSTREAM_ID "bitstream_id" + +// fpga device path +#define SYSFS_FPGA_FMT "/intel-fpga-dev.%d" + +// FPGA device id +#define FPGA_SYSFS_DEVICEID "device/device" + +// Integrated FPGA Device ID +#define FPGA_INTEGRATED_DEVICEID 0xbcc0 + +// Discrete FPGA Device ID +#define FPGA_DISCRETE_DEVICEID 0x09c4 + +#define FPGA_BBS_VER_MAJOR(i) (((i) >> 56) & 0xf) +#define FPGA_BBS_VER_MINOR(i) (((i) >> 52) & 0xf) +#define FPGA_BBS_VER_PATCH(i) (((i) >> 48) & 0xf) + +#define DEV_PATH_MAX 256 + +// FPGA token magic (FPGATOKN) +#define FPGA_TOKEN_MAGIC 0x46504741544f4b4e +// FPGA handle magic (FPGAHNDL) +#define FPGA_HANDLE_MAGIC 0x46504741484e444c +// FPGA property magic (FPGAPROP) +#define FPGA_PROPERTY_MAGIC 0x4650474150524f50 +// FPGA invalid magic (FPGAINVL) +#define FPGA_INVALID_MAGIC 0x46504741494e564c + +/** System-wide unique FPGA resource identifier */ +struct _fpga_token { + uint64_t magic; + char sysfspath[SYSFS_PATH_MAX]; + char devpath[DEV_PATH_MAX]; +}; + +/** Process-wide unique FPGA handle */ +struct _fpga_handle { + pthread_mutex_t lock; + uint64_t magic; + fpga_token token; + int fddev; // file descriptor for the device. + int fdfpgad; // file descriptor for the event daemon. + struct wsid_map *wsid_root; // wsid information (list) + struct wsid_map *mmio_root; // MMIO information (list) + void *umsg_virt; // umsg Virtual Memory pointer + uint64_t umsg_size; // umsg Virtual Memory Size + uint64_t *umsg_iova; // umsg IOVA from driver +}; + +/** Object property struct + Intent is for property struct to be created dynamically */ +struct _fpga_properties { + pthread_mutex_t lock; + uint64_t magic; + /* Common properties */ + uint64_t valid_fields; // bitmap of valid fields + // valid here means the field has been set using the API + // bit 0x00 - parent field is valid + // bit 0x01 - objtype field is valid + // bit 0x02 - bus field is valid + // ... + // up to bit 0x1F + fpga_guid guid; // Applies only to accelerator types + fpga_token parent; + fpga_objtype objtype; + uint8_t bus; + uint8_t device; + uint8_t function; + uint8_t socket_id; + // TODO uint16_t device_id; + + /* Object-specific properties + * bitfields start as 0x20 + */ + union { + + /* fpga object properties + * */ + struct { + uint32_t num_slots; + uint64_t bbs_id; + fpga_version bbs_version; + // TODO uint16_t vendor_id; + // TODO char model[FPGA_MODEL_LENGTH]; + // TODO uint64_t local_memory_size; + // TODO uint64_t capabilities; #<{(| bitfield (HSSI, iommu, ...) |)}># + } fpga; + + /* accelerator object properties + * */ + struct { + fpga_accelerator_state state; + uint32_t num_mmio; + uint32_t num_interrupts; + } accelerator; + + } u; + +}; + +/* + * Global list to store wsid/physptr/length vectors + */ +struct wsid_map { + uint64_t wsid; + uint64_t addr; + uint64_t phys; + uint64_t len; + uint64_t offset; + uint32_t index; + int flags; + struct wsid_map *next; +}; + +/* + * Global list to store tokens received during enumeration + * Since tokens as seen by the API are only void*, we need to keep the actual + * structs somewhere. + */ +struct token_map { + struct _fpga_token _token; + struct token_map *next; +}; + + +#endif // __FPGA_TYPES_INT_H__ diff --git a/libopae/src/umsg.c b/libopae/src/umsg.c new file mode 100644 index 000000000000..3a6429ff8255 --- /dev/null +++ b/libopae/src/umsg.c @@ -0,0 +1,320 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include "opae/access.h" +#include "opae/utils.h" +#include "opae/umsg.h" +#include "common_int.h" +#include "intel-fpga.h" + +#include +#include +#include +#include +#include + + +// Get number of Umsgs +fpga_result __FPGA_API__ fpgaGetNumUmsg(fpga_handle handle, uint64_t *value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + struct fpga_port_info info = { 0 }; + + ASSERT_NOT_NULL(value); + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // Set ioctl port info struct parameters + info.argsz = sizeof(info); + info.flags = 0; + + // ioctl + result = ioctl(_handle->fddev, FPGA_PORT_GET_INFO, &info); + if (result != 0) { + FPGA_MSG("FPGA_PORT_GET_INFO ioctl failed"); + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + goto out_unlock; + } + + // Assign number of umsgs + *value = info.num_umsgs; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +// Set Umsg Attributes +fpga_result __FPGA_API__ fpgaSetUmsgAttributes(fpga_handle handle, uint64_t value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + struct fpga_port_umsg_cfg umsg_cfg = {0}; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + // Set ioctl Umsg config struct parameters + umsg_cfg.argsz = sizeof(umsg_cfg); + umsg_cfg.flags = 0; + umsg_cfg.hint_bitmap = (__u32)value ; + + result = ioctl(_handle->fddev, FPGA_PORT_UMSG_SET_MODE, &umsg_cfg); + if (result != 0) { + FPGA_MSG("FPGA_PORT_UMSG_SET_MODE ioctl failed"); + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +// Gets Umsg address +fpga_result __FPGA_API__ fpgaGetUmsgPtr(fpga_handle handle, uint64_t **umsg_ptr) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + struct fpga_port_dma_map dma_map = {0}; + struct fpga_port_dma_unmap dma_unmap = {0}; + struct fpga_port_umsg_base_addr baseaddr = {0}; + + fpga_result result = FPGA_OK; + uint64_t umsg_count = 0; + uint64_t umsg_size = 0; + int pagesize = 0; + void *umsg_virt = NULL; + + ASSERT_NOT_NULL(umsg_ptr); + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + if (_handle->umsg_iova != NULL) { + *umsg_ptr = _handle->umsg_virt; + goto out_unlock; + } + + // Page size + pagesize = sysconf(_SC_PAGESIZE); + + // get umsg count + result = fpgaGetNumUmsg(handle, &umsg_count); + if (result != FPGA_OK) { + FPGA_MSG("Failed to get UMSG count"); + result = FPGA_EXCEPTION; + goto out_unlock; + } + + umsg_size = (uint64_t)umsg_count * pagesize; + umsg_virt = alloc_buffer(umsg_size); + if (umsg_virt == NULL) { + FPGA_MSG("Failed to allocate memory"); + result = FPGA_NO_MEMORY; + goto out_unlock; + } + + // Map Umsg Buffer + dma_map.argsz = sizeof(dma_map); + dma_map.flags = 0; + dma_map.user_addr = (__u64) umsg_virt; + dma_map.length = umsg_size; + dma_map.iova = 0 ; + + result = ioctl(_handle->fddev, FPGA_PORT_DMA_MAP, &dma_map); + if (result != 0) { + FPGA_MSG("Failed to map UMSG buffer"); + result = FPGA_INVALID_PARAM; + goto umsg_exit; + } + + // Set Umsg Address + baseaddr.argsz = sizeof(baseaddr); + baseaddr.flags = 0; + baseaddr.iova = dma_map.iova ; + + result = ioctl(_handle->fddev, FPGA_PORT_UMSG_SET_BASE_ADDR, &baseaddr); + if (result != 0) { + FPGA_MSG("Failed to set UMSG base address"); + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + goto umsg_map_exit; + } + + result = ioctl(_handle->fddev, FPGA_PORT_UMSG_ENABLE, NULL); + if (result != 0) { + FPGA_MSG("Failed to enable UMSG"); + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + goto umsg_map_exit; + } + + *umsg_ptr = (uint64_t *) umsg_virt; + _handle->umsg_iova = (uint64_t *) dma_map.iova; + _handle->umsg_virt = umsg_virt; + _handle->umsg_size = umsg_size; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; + +umsg_map_exit: + dma_unmap.argsz = sizeof(dma_unmap); + dma_unmap.flags = 0; + dma_unmap.iova = dma_map.iova; + + result = ioctl(_handle->fddev, FPGA_PORT_DMA_UNMAP, &dma_unmap); + if (result != 0) { + FPGA_MSG("Failed to unmap UMSG buffer"); + if ((errno == EINVAL) || + (errno == EFAULT)) { + result = FPGA_INVALID_PARAM; + } else { + result = FPGA_EXCEPTION; + } + } + +umsg_exit: + if (umsg_virt != NULL) + free_buffer(umsg_virt, umsg_size); + + pthread_mutex_unlock(&_handle->lock); + return result; +} + +fpga_result free_umsg_buffer(fpga_handle handle) +{ + fpga_result result = FPGA_OK; + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->umsg_virt != NULL) { + struct fpga_port_umsg_base_addr baseaddr; + struct fpga_port_dma_unmap dma_unmap; + + if (ioctl(_handle->fddev, FPGA_PORT_UMSG_DISABLE, NULL) != 0) { + FPGA_ERR("Failed to disable UMSG"); + } + + baseaddr.argsz = sizeof(baseaddr); + baseaddr.flags = 0; + baseaddr.iova = 0; + + if (ioctl(_handle->fddev, FPGA_PORT_UMSG_SET_BASE_ADDR, &baseaddr) != 0) { + FPGA_ERR("Failed to zero UMSG address"); + } + + dma_unmap.argsz = sizeof(dma_unmap); + dma_unmap.flags = 0; + dma_unmap.iova = (__u64) _handle->umsg_iova; + + if (ioctl(_handle->fddev, FPGA_PORT_DMA_UNMAP, &dma_unmap) != 0) { + FPGA_ERR("Failed to unmap UMSG Buffer"); + } + + free_buffer(_handle->umsg_virt, _handle->umsg_size); + + _handle->umsg_virt = NULL; + _handle->umsg_size = 0; + _handle->umsg_iova = NULL; + } + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} + +// Trigger umsg +fpga_result fpgaTriggerUmsg(fpga_handle handle, uint64_t value) +{ + struct _fpga_handle *_handle = (struct _fpga_handle *)handle; + fpga_result result = FPGA_OK; + uint64_t *umsg_ptr = NULL; + + result = handle_check_and_lock(_handle); + if (result) + return result; + + if (_handle->fddev < 0) { + FPGA_ERR("Invalid handle file descriptor"); + result = FPGA_INVALID_PARAM; + goto out_unlock; + } + + result = fpgaGetUmsgPtr(handle, &umsg_ptr); + if (result != FPGA_OK) { + FPGA_ERR("Failed to get UMsg buffer"); + goto out_unlock; + } + + // Assign Value to UMsg + *((volatile uint64_t *) (umsg_ptr)) = value; + +out_unlock: + pthread_mutex_unlock(&_handle->lock); + return result; +} diff --git a/libopae/src/usrclk/user_clk_pgm_uclock.c b/libopae/src/usrclk/user_clk_pgm_uclock.c new file mode 100644 index 000000000000..2eab848dde5d --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock.c @@ -0,0 +1,793 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +//**************************************************************************** +// Arthur.Sheiman@Intel.com Created: 09-08-16 +// Revision: 10-18-16 18:06 + + +#include +#include /* malloc */ +#include /* exit */ +#include /* printf */ +#include /* memcpy */ +#include /* getpid */ +#include +#include +#include +#include +#include +#include + +#include "user_clk_pgm_uclock.h" +#include "user_clk_pgm_uclock_freq_template.h" +#include "user_clk_pgm_uclock_eror_messages.h" + +// user clock sysfs +#define USER_CLOCK_CMD0 "userclk_freqcmd" +#define USER_CLOCK_CMD1 "userclk_freqcntrcmd" +#define USER_CLOCK_STS0 "userclk_freqsts" +#define USER_CLOCK_STS1 "userclk_freqcntrsts" +#define MAX_FPGA_FREQ 1200 +#define MIN_FPGA_FREQ 100 + +// User clock sleep +#define USRCLK_SLEEEP_1MS 1000000 +#define USRCLK_SLEEEP_10MS 10000000 + +struct QUCPU_Uclock gQUCPU_Uclock; + +//Get fpga user clock +fpga_result __FIXME_MAKE_VISIBLE__ get_userclock(const char* sys_path, + uint64_t* userclk_high, + uint64_t* userclk_low) +{ + QUCPU_tFreqs userClock; + + if ((sys_path == NULL) || + (userclk_high == NULL) || + (userclk_low == NULL)) { + FPGA_ERR("Invalid input parameters"); + return FPGA_INVALID_PARAM; + } + + // Initialize + if (fi_RunInitz(sys_path) != 0) { + FPGA_ERR("Failed to initialize user clock "); + return FPGA_NOT_SUPPORTED; + } + + // get user clock + if (fi_GetFreqs(&userClock) != 0) { + FPGA_ERR("Failed to get user clock Frequency "); + return FPGA_NOT_SUPPORTED; + } + + *userclk_high = userClock.u64i_Frq_ClkUsr; + *userclk_low = userClock.u64i_Frq_DivBy2; + + return FPGA_OK; +} + +// set fpga user clock +fpga_result __FIXME_MAKE_VISIBLE__ set_userclock(const char* sysfs_path, + uint64_t userclk_high, + uint64_t userclk_low) +{ + if (sysfs_path == NULL) { + FPGA_ERR("Invalid input parameters"); + return FPGA_INVALID_PARAM; + } + + // verify user clock freq range (100hz to 1200hz) + if ((userclk_high > MAX_FPGA_FREQ) || + (userclk_high < MIN_FPGA_FREQ) || + (userclk_low > MAX_FPGA_FREQ) || + (userclk_low < MIN_FPGA_FREQ)) { + + FPGA_ERR("Invalid input frequency"); + return FPGA_INVALID_PARAM; + } + + if (userclk_low > userclk_high) { + FPGA_ERR("Invalid input low frequency"); + return FPGA_INVALID_PARAM; + } + + // Initialize + if (fi_RunInitz(sysfs_path) != 0) { + FPGA_ERR("Failed to initialize user clock "); + return FPGA_NOT_SUPPORTED; + } + + FPGA_DBG("User clock high: %ld \n", userclk_high); + + // set user clock + if (fi_SetFreqs(0, userclk_high) != 0) { + FPGA_ERR("Failed to set user clock frequency "); + return FPGA_NOT_SUPPORTED; + } + + return FPGA_OK; +} + +//fi_RunInitz +int fi_RunInitz(const char* sysfs_path) +{ + // fi_RunInitz + // Initialize + // Reinitialization okay too, since will issue machine reset + + uint64_t u64i_PrtAddr, u64i_PrtData; + uint64_t u64i_AvmmAdr, u64i_AvmmDat; + int i_ReturnErr; + char syfs_usrpath[SYSFS_PATH_MAX]; + + gQUCPU_Uclock.i_InitzState = 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_Version = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Intg_End = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_Beg = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_End = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumReg = (uint64_t) 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumRck = (uint64_t) 0; + gQUCPU_Uclock.u64i_cmd_reg_0 = (uint64_t) 0x0LLU; + gQUCPU_Uclock.u64i_cmd_reg_1 = (uint64_t) 0x0LLU; + gQUCPU_Uclock.u64i_AVMM_seq = (uint64_t) 0x0LLU; + gQUCPU_Uclock.i_Bug_First = 0; + gQUCPU_Uclock.i_Bug_Last = 0; + + + if (sysfs_path == NULL) { + printf(" Invalid input sysfs path \n"); + return -1; + } + snprintf(gQUCPU_Uclock.sysfs_path, sizeof(gQUCPU_Uclock.sysfs_path), "%s", sysfs_path); + + // Assume return error okay, for now + i_ReturnErr = 0; + + // Initialize default values (for error abort) + gQUCPU_Uclock.tInitz_InitialParams.u64i_Version = 0; + gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID = 0; + + // Initialize command shadow registers + gQUCPU_Uclock.u64i_cmd_reg_0 = ((uint64_t) 0x0LLU); + gQUCPU_Uclock.u64i_cmd_reg_1 = ((uint64_t) 0x0LLU); + + // Initialize sequence IO + gQUCPU_Uclock.u64i_AVMM_seq = ((uint64_t) 0x0LLU); + + // Static values + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Intg_End = (uint64_t) QUCPU_INT_NUMFRQ_INTG_END; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_Beg = (uint64_t) QUCPU_INT_NUMFRQ_FRAC_BEG; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_End = (uint64_t) QUCPU_INT_NUMFRQ_FRAC_END; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq = (uint64_t) QUCPU_INT_NUMFRQ; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumReg = (uint64_t) QUCPU_INT_NUMREG; + gQUCPU_Uclock.tInitz_InitialParams.u64i_NumRck = (uint64_t) QUCPU_INT_NUMRCK; + + + // Read version number + if (i_ReturnErr == 0) // This always true; added for future safety + { + // Verifying User Clock version number + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS1); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + //printf(" fi_RunInitz u64i_PrtData %llx \n", u64i_PrtData); + + gQUCPU_Uclock.tInitz_InitialParams.u64i_Version = (u64i_PrtData & QUCPU_UI64_STS_1_VER_b63t60) >> 60; + if (gQUCPU_Uclock.tInitz_InitialParams.u64i_Version != QUCPU_UI64_STS_1_VER_version) + { // User Clock wrong version number + i_ReturnErr = QUCPU_INT_UCLOCK_RUNINITZ_ERR_VER; + + } // User Clock wrong version number + } // Verifying User Clock version number + + FPGA_DBG("User clock version = %lx \n", gQUCPU_Uclock.tInitz_InitialParams.u64i_Version); + + // Read PLL ID + if (i_ReturnErr == 0) + { // Waiting for fcr PLL calibration not to be busy + i_ReturnErr = fi_WaitCalDone(); + } // Waiting for fcr PLL calibration not to be busy + + if (i_ReturnErr == 0) + { + // Cycle reset and wait for any calibration to finish + // Activating management & machine reset + + gQUCPU_Uclock.u64i_cmd_reg_0 |= (QUCPU_UI64_CMD_0_PRS_b56); + gQUCPU_Uclock.u64i_cmd_reg_0 &= ~(QUCPU_UI64_CMD_0_MRN_b52); + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_0; + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_CMD0); + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + + // Deasserting management & machine reset + gQUCPU_Uclock.u64i_cmd_reg_0 |= (QUCPU_UI64_CMD_0_MRN_b52); + gQUCPU_Uclock.u64i_cmd_reg_0 &= ~(QUCPU_UI64_CMD_0_PRS_b56); + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_0; + + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + //printf(" fi_RunInitz u64i_PrtData %llx \n", u64i_PrtData); + + // Waiting for fcr PLL calibration not to be busy + i_ReturnErr = fi_WaitCalDone(); + } // Cycle reset and wait for any calibration to finish + + if (i_ReturnErr == 0) + { // Checking fPLL ID + u64i_AvmmAdr = QUCPU_UI64_AVMM_FPLL_IPI_200; + i_ReturnErr = fi_AvmmRead(u64i_AvmmAdr, &u64i_AvmmDat); + if (i_ReturnErr == 0) + { // Check identifier + gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID = u64i_AvmmDat & 0xffLLU; + if (!(gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RFDUAL + || gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF100M + || gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF322M)) + { // ERROR: Wrong fPLL ID Identifer + printf(" ERROR \n"); + i_ReturnErr = QUCPU_INT_UCLOCK_RUNINITZ_ERR_FPLL_ID_ILLEGAL; + } // ERROR: Wrong fPLL ID Identifer + } // Check identifier + } // Checking fPLL ID + + // Copy structure, initialize, and return based on error status + //*ptInitz_retInitz = gQUCPU_Uclock.tInitz_InitialParams; + gQUCPU_Uclock.i_InitzState = !i_ReturnErr; // Set InitzState to 0 or 1 + + return (i_ReturnErr); +} // fi_RunInitz + +//fu64i_GetAVMM_seq +uint64_t fu64i_GetAVMM_seq() +{ + // fu64i_GetAVMM_seq + // Increment seq + gQUCPU_Uclock.u64i_AVMM_seq++; + gQUCPU_Uclock.u64i_AVMM_seq &= 0x03LLU; + + return(gQUCPU_Uclock.u64i_AVMM_seq); +} // fu64i_GetAVMM_seq + + +//fi_AvmmRWcom +int fi_AvmmRWcom(int i_CmdWrite, + uint64_t u64i_AvmmAdr, + uint64_t u64i_WriteData, + uint64_t *pu64i_ReadData) +{ + // fi_AvmmRWcom + uint64_t u64i_SeqCmdAddrData, u64i_SeqCmdAddrData_seq_2, u64i_SeqCmdAddrData_wrt_1; + uint64_t u64i_SeqCmdAddrData_adr_10, u64i_SeqCmdAddrData_dat_32; + uint64_t u64i_PrtAddr, u64i_PrtData; + uint64_t u64i_DataX; + uint64_t u64i_FastPoll, u64i_SlowPoll; + long int li_sleep_nanoseconds; + int i_ReturnErr; + char syfs_usrpath[SYSFS_PATH_MAX]; + + // Assume return error okay, for now + i_ReturnErr = 0; + + // Common portion + u64i_SeqCmdAddrData_seq_2 = fu64i_GetAVMM_seq(); + u64i_SeqCmdAddrData_adr_10 = u64i_AvmmAdr; + + if (i_CmdWrite == 1) + { + // Write data + u64i_SeqCmdAddrData_wrt_1 = 0x1LLU; + u64i_SeqCmdAddrData_dat_32 = u64i_WriteData; + } // Write data + else + { // Read data + u64i_SeqCmdAddrData_wrt_1 = 0x0LLU; + u64i_SeqCmdAddrData_dat_32 = 0x0LLU; + } // Read data + + u64i_SeqCmdAddrData = (u64i_SeqCmdAddrData_seq_2 & 0x00000003LLU) << 48 // [49:48] + | (u64i_SeqCmdAddrData_wrt_1 & 0x00000001LLU) << 44 // [ 44] + | (u64i_SeqCmdAddrData_adr_10 & 0x000003ffLLU) << 32 // [41:32] + | (u64i_SeqCmdAddrData_dat_32 & 0xffffffffLLU) << 0; // [31:00] + + gQUCPU_Uclock.u64i_cmd_reg_0 &= ~QUCPU_UI64_CMD_0_AMM_b51t00; + gQUCPU_Uclock.u64i_cmd_reg_0 |= u64i_SeqCmdAddrData; + + // Write register 0 to kick it off + + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_0; + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_CMD0); + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS0); + + // Poll register 0 for completion. + // CCI is synchronous and needs only 1 read with matching sequence. + // u64i_PrtAddr = QUCPU_UI64_PRT_UCLK_STS_0; + for (u64i_SlowPoll = 0; u64i_SlowPoll<100; ++u64i_SlowPoll) // 100 ms + { // Poll 0, slow outer loop with 1 ms sleep + for (u64i_FastPoll = 0; u64i_FastPoll<100; ++u64i_FastPoll) + { + // Poll 0, fast inner loop with no sleep + sysfs_read_u64(syfs_usrpath, &u64i_DataX); + + if ((u64i_DataX & QUCPU_UI64_STS_0_SEQ_b49t48) == (u64i_SeqCmdAddrData & QUCPU_UI64_STS_0_SEQ_b49t48)) + { // Have result + goto GOTO_LABEL_HAVE_RESULT; + } // Have result + } // Poll 0, fast inner loop with no sleep + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + } // Poll 0, slow outer loop with 1 ms sleep + + i_ReturnErr = QUCPU_INT_UCLOCK_AVMMRWCOM_ERR_TIMEOUT; // Error + +GOTO_LABEL_HAVE_RESULT: // No error + + if (i_CmdWrite == 0) *pu64i_ReadData = u64i_DataX; + return(i_ReturnErr); + +} // fi_AvmmRWcom + + +//fi_AvmmRead +int fi_AvmmRead(uint64_t u64i_AvmmAdr, uint64_t *pu64i_ReadData) +{ + // fi_AvmmRead + int i_CmdWrite = 0; + uint64_t u64i_WriteData = 0; + int res = 0; + + // Perform read with common code + i_CmdWrite = 0; + u64i_WriteData = 0; // Not used for read + res = fi_AvmmRWcom(i_CmdWrite, u64i_AvmmAdr, u64i_WriteData, pu64i_ReadData); + + // Return error status + return(res); +} // fi_AvmmRead + +//fi_AvmmWrite +int fi_AvmmWrite(uint64_t u64i_AvmmAdr, uint64_t u64i_WriteData) +{ + // fi_AvmmWrite + int i_CmdWrite = 0; + uint64_t u64i_ReadData = 0; // Read data is not used + int res = 0; + + // Perform write with common code + i_CmdWrite = 1; + res = fi_AvmmRWcom(i_CmdWrite, u64i_AvmmAdr, u64i_WriteData, &u64i_ReadData); + + // Return error status + return(res); +} // fi_AvmmWrite + + +//Sleep for nanoseconds +void fv_SleepShort(long int li_sleep_nanoseconds) +{ + // fv_SleepShort + // Sleep for nanoseconds + struct timespec timespecRemaining = {0}; + struct timespec timespecWait = {0}; + int res = 0; + + timespecRemaining.tv_nsec = li_sleep_nanoseconds; timespecRemaining.tv_sec = 0; + + do + { // Wait, and retry if wait ended early + timespecWait = timespecRemaining; + res = (int) nanosleep(×pecWait, ×pecRemaining); + if (res != 0 && res != -1) + { // BUG: unexpected nanosleep return value + fv_BugLog((int) QUCPU_INT_UCLOCK_BUG_SLEEP_SHORT); + } // BUG: unexpected nanosleep return value + } // Wait, and retry if wait ended early + while (res != 0); + + return; +} // fv_SleepShort + +// get user clock +// Read the frequency for the User clock and div2 clock +int fi_GetFreqs(QUCPU_tFreqs *ptFreqs_retFreqs) +{ + // fi_GetFreqs + // Read the frequency for the User clock and div2 clock + + uint64_t u64i_PrtAddr = 0, + u64i_PrtData = 0; + long int li_sleep_nanoseconds = 0; + int res = 0; + char syfs_usrpath[SYSFS_PATH_MAX] = {0}; + + // Assume return error okay, for now + res = 0; + + if (!gQUCPU_Uclock.i_InitzState) res = QUCPU_INT_UCLOCK_GETFREQS_ERR_INITZSTATE; + + if (res == 0) + { // Read div2 and 1x user clock frequency + // Low frequency + gQUCPU_Uclock.u64i_cmd_reg_1 &= ~QUCPU_UI64_CMD_1_MEA_b32; + + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_1; + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_CMD1); + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + + + li_sleep_nanoseconds = USRCLK_SLEEEP_10MS; // 10 ms for frequency counter + fv_SleepShort(li_sleep_nanoseconds); + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS1); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + + + ptFreqs_retFreqs->u64i_Frq_DivBy2 = (u64i_PrtData & QUCPU_UI64_STS_1_FRQ_b16t00) * 10000; // Hz + //printf(" ptFreqs_retFreqs->u64i_Frq_ClkUsr %llx \n", ptFreqs_retFreqs->u64i_Frq_DivBy2); + li_sleep_nanoseconds = USRCLK_SLEEEP_10MS; + fv_SleepShort(li_sleep_nanoseconds); + + // High frequency + gQUCPU_Uclock.u64i_cmd_reg_1 |= QUCPU_UI64_CMD_1_MEA_b32; + + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_1; + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_CMD1); + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + + li_sleep_nanoseconds = USRCLK_SLEEEP_10MS; // 10 ms for frequency counter + fv_SleepShort(li_sleep_nanoseconds); + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS1); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + ptFreqs_retFreqs->u64i_Frq_ClkUsr = (u64i_PrtData & QUCPU_UI64_STS_1_FRQ_b16t00) * 10000; // Hz + //printf(" ptFreqs_retFreqs->u64i_Frq_ClkUsr %llx \n", ptFreqs_retFreqs->u64i_Frq_ClkUsr); + + fv_SleepShort(li_sleep_nanoseconds); + + } // Read div2 and 1x user clock frequency + + FPGA_DBG("\nApproximate frequency:\n" + "High clock = %5.1f MHz\n" + "Low clock = %5.1f MHz\n \n", + ptFreqs_retFreqs->u64i_Frq_ClkUsr / 1.0e6, (ptFreqs_retFreqs->u64i_Frq_DivBy2) / 1.0e6); + + + return (res); +} // fi_GetFreqs + +// set user clock +int fi_SetFreqs(uint64_t u64i_Refclk, + uint64_t u64i_FrqInx) +{ + // fi_SetFreqs + // Set the user clock frequency + uint64_t u64i_I, u64i_MifReg, u64i_PrtAddr, u64i_PrtData; + uint64_t u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk; + long int li_sleep_nanoseconds; + int i_ReturnErr; + char syfs_usrpath[SYSFS_PATH_MAX]; + + // Assume return error okay, for now + i_ReturnErr = 0; + + if (!gQUCPU_Uclock.i_InitzState) i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_INITZSTATE; + + if (i_ReturnErr == 0) + { // Check REFCLK + if (u64i_Refclk == 0) + { // 100 MHz REFCLK requested + if (!(gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RFDUAL + || gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF100M)) + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_100M_MISSING; + } // 100 MHz REFCLK requested + else if (u64i_Refclk == 1) + { // 322.265625 MHz REFCLK requested + if (!(gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RFDUAL + || gQUCPU_Uclock.tInitz_InitialParams.u64i_PLL_ID == QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF322M)) + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_322M_MISSING; + } // 322.265625 MHz REFCLK requested + else i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_ILLEGAL; + } // Check REFCLK + + if (i_ReturnErr == 0) + { // Check frequency index + if (u64i_FrqInx > gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_End) + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_OVERRANGE; + else if (u64i_FrqInx < gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_Beg + && u64i_FrqInx > gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Intg_End) + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_INTG_RANGE_BAD; + else if (u64i_FrqInx < gQUCPU_Uclock.tInitz_InitialParams.u64i_NumFrq_Frac_Beg + && u64i_Refclk != 1) // Integer-PLL mode, exact requires 322.265625 MHz + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_INTG_NEEDS_322M; + } // Check frequency index + + + if (i_ReturnErr == 0) + { // Power down PLL + // Altera bug. Power down pin doesn't work SR #11229652. + // WORKAROUND: Use power down port + u64i_AvmmAdr = 0x2e0LLU; + u64i_AvmmDat = 0x03LLU; + u64i_AvmmMsk = 0x03LLU; + + i_ReturnErr = fi_AvmmReadModifyWriteVerify(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + } // Power down PLL + + if (i_ReturnErr == 0) + { // Verifying fcr PLL not locking + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS0); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + //sysfs_read_uint64(gQUCPU_Uclock.sys_path, USER_CLOCK_STS0, &u64i_PrtData); + + if ((u64i_PrtData & QUCPU_UI64_STS_0_LCK_b60) != 0) + { // fcr PLL is locked but should be unlocked + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_PLL_NO_UNLOCK; + } // fcr PLL is locked but should be unlocked + } // Verifying fcr PLL not locking + + if (i_ReturnErr == 0) + { // Select reference and push table + // Selecting desired reference clock + gQUCPU_Uclock.u64i_cmd_reg_0 &= ~QUCPU_UI64_CMD_0_SR1_b58; + if (u64i_Refclk) gQUCPU_Uclock.u64i_cmd_reg_0 |= QUCPU_UI64_CMD_0_SR1_b58; + u64i_PrtData = gQUCPU_Uclock.u64i_cmd_reg_0; + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_CMD0); + sysfs_write_u64(syfs_usrpath, u64i_PrtData); + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + + // Pushing the table + for (u64i_MifReg = 0; u64i_MifReg> 16; + u64i_AvmmDat = (uint64_t) (scu32ia3d_DiffMifTbl[(int) u64i_FrqInx][(int) u64i_MifReg][(int) u64i_Refclk] & 0x000000ff); + u64i_AvmmMsk = (uint64_t) (scu32ia3d_DiffMifTbl[(int) u64i_FrqInx][(int) u64i_MifReg][(int) u64i_Refclk] & 0x0000ff00) >> 8; + i_ReturnErr = fi_AvmmReadModifyWriteVerify(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + + if (i_ReturnErr) break; + } // Write each register in the diff mif + } // Select reference and push table + + if (i_ReturnErr == 0) + { // Waiting for fcr PLL calibration not to be busy + i_ReturnErr = fi_WaitCalDone(); + } // Waiting for fcr PLL calibration not to be busy + + if (i_ReturnErr == 0) + { // Recalibrating + + // "Request user access to the internal configuration bus" + // and "Wait for reconfig_waitrequest to be deasserted." + // Note that the Verify operation performs the post "wait." + + u64i_AvmmAdr = 0x000LLU; + u64i_AvmmDat = 0x02LLU; + u64i_AvmmMsk = 0xffLLU; + i_ReturnErr = fi_AvmmReadModifyWriteVerify(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + + if (i_ReturnErr == 0) + { // "To calibrate the fPLL, Read-Modify-Write:" set B1 of 0x100 high + u64i_AvmmAdr = 0x100LLU; + u64i_AvmmDat = 0x02LLU; + u64i_AvmmMsk = 0x02LLU; + i_ReturnErr = fi_AvmmReadModifyWrite(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + } // "To calibrate the fPLL, Read-Modify-Write:" set B1 of 0x100 high + + if (i_ReturnErr == 0) + { // "Release the internal configuraiton bus to PreSICE to perform recalibration" + u64i_AvmmAdr = 0x000LLU; + u64i_AvmmDat = 0x01LLU; + i_ReturnErr = fi_AvmmWrite(u64i_AvmmAdr, u64i_AvmmDat); + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + } // "Release the internal configuraiton bus to PreSICE to perform recalibration" + } // Recalibrating + + if (i_ReturnErr == 0) + { // Waiting for fcr PLL calibration not to be busy + i_ReturnErr = fi_WaitCalDone(); + } // Waiting for fcr PLL calibration not to be busy + + if (i_ReturnErr == 0) + { // Power up PLL + // Altera bug. Power down pin doesn't work SR #11229652. + // WORKAROUND: Use power down port + u64i_AvmmAdr = 0x2e0LLU; + u64i_AvmmDat = 0x02LLU; + u64i_AvmmMsk = 0x03LLU; + i_ReturnErr = fi_AvmmReadModifyWriteVerify(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + } // Power up PLL + + if (i_ReturnErr == 0) + { // Wait for PLL to lock + // u64i_PrtAddr = QUCPU_UI64_PRT_UCLK_STS_0; + for (u64i_I = 0; u64i_I<100; u64i_I++) + { // Poll with 100 ms timeout + // u64i_PrtData = fu64i_PrtMmioRead(u64i_PrtAddr); + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS0); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + //sysfs_read_uint64(gQUCPU_Uclock.sys_path, USER_CLOCK_STS0, &u64i_PrtData); + + if ((u64i_PrtData & QUCPU_UI64_STS_0_LCK_b60) != 0) break; + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + } // Poll with 100 ms timeout + + if ((u64i_PrtData & QUCPU_UI64_STS_0_LCK_b60) == 0) + { // fcr PLL lock error + + i_ReturnErr = QUCPU_INT_UCLOCK_SETFREQS_ERR_PLL_LOCK_TO; + } // fcr PLL lock error + } // Verifying fcr PLL is locking + + return (i_ReturnErr); +} // fi_SetFreqs + +// get error message +//Read the frequency for the User clock and div2 clock +const char * fpac_GetErrMsg(int i_ErrMsgInx) +{ + // fpac_GetErrMsg + // Read the frequency for the User clock and div2 clock + const char * pac_ErrMsgStr = NULL; + + // Extra "+1" message has index range error message + pac_ErrMsgStr = pac_UclockErrorMsg[QUCPU_INT_UCLOCK_NUM_ERROR_MESSAGES + 1 - 1]; + + // Check index range + if (i_ErrMsgInx >= 0 + || i_ErrMsgInx < QUCPU_INT_UCLOCK_NUM_ERROR_MESSAGES); + { // All okay, set the message string + pac_ErrMsgStr = pac_UclockErrorMsg[i_ErrMsgInx]; + } // All okay, set the message string + + return (pac_ErrMsgStr); +} // fpac_GetErrMsg + +// fi_AvmmReadModifyWriteVerify +int fi_AvmmReadModifyWriteVerify(uint64_t u64i_AvmmAdr, + uint64_t u64i_AvmmDat, + uint64_t u64i_AvmmMsk) +{ + // fi_AvmmReadModifyWriteVerify + int res = 0; + uint64_t u64i_VerifyData = 0; + + res = fi_AvmmReadModifyWrite(u64i_AvmmAdr, u64i_AvmmDat, u64i_AvmmMsk); + + if (res == 0) + { // Read back the data and verify mask-enabled bits + + res = fi_AvmmRead(u64i_AvmmAdr, &u64i_VerifyData); + + if (res == 0) + { // Perform verify + if ((u64i_VerifyData & u64i_AvmmMsk) != (u64i_AvmmDat & u64i_AvmmMsk)) + { // Verify failure + res = QUCPU_INT_UCLOCK_AVMMRMWV_ERR_VERIFY; + } // Verify failure + } // Perform verify + } // Read back the data and verify mask-enabled bits + + return(res); +} // fi_AvmmReadModifyWriteVerify + + +// fi_AvmmReadModifyWrite +int fi_AvmmReadModifyWrite(uint64_t u64i_AvmmAdr, + uint64_t u64i_AvmmDat, + uint64_t u64i_AvmmMsk) +{ + uint64_t u64i_ReadData = 0; + uint64_t u64i_WriteData = 0; + int res = 0; + + // Read data + res = fi_AvmmRead(u64i_AvmmAdr, &u64i_ReadData); + + if (res == 0) + { // Modify the read data and write it + u64i_WriteData = (u64i_ReadData & ~u64i_AvmmMsk) | (u64i_AvmmDat & u64i_AvmmMsk); + res = fi_AvmmWrite(u64i_AvmmAdr, u64i_WriteData); + } // Modify the read data and write it + + return(res); +} // fi_AvmmReadModifyWrite + +// fv_BugLog +// Logs first and last bugs +void fv_BugLog(int i_BugID) +{ + if (gQUCPU_Uclock.i_Bug_First) + { // This is not the first bug + gQUCPU_Uclock.i_Bug_Last = i_BugID; + } // This is not the first bug + else + { // This is the first bug + gQUCPU_Uclock.i_Bug_First = i_BugID; + } // This is the first bug + + return; +} // fv_BugLog + +// wait caldone +// Wait for calibration to be done +int fi_WaitCalDone(void) +{ + // fi_WaitCalDone + // Wait for calibration to be done + uint64_t u64i_PrtAddr = 0; + uint64_t u64i_PrtData = 0; + uint64_t u64i_I = 0; + long int li_sleep_nanoseconds = 0; + int res = 0; + char syfs_usrpath[SYSFS_PATH_MAX] = {0}; + + // Waiting for fcr PLL calibration not to be busy + for (u64i_I = 0; u64i_I<1000; u64i_I++) + { // Poll with 1000 ms timeout + + snprintf(syfs_usrpath, sizeof(syfs_usrpath), "%s/%s", gQUCPU_Uclock.sysfs_path, USER_CLOCK_STS0); + sysfs_read_u64(syfs_usrpath, &u64i_PrtData); + + if ((u64i_PrtData & QUCPU_UI64_STS_0_BSY_b61) == 0) break; + + // Sleep 1 ms + li_sleep_nanoseconds = USRCLK_SLEEEP_1MS; + fv_SleepShort(li_sleep_nanoseconds); + } // Poll with 1000 ms timeout + + + if ((u64i_PrtData & QUCPU_UI64_STS_0_BSY_b61) != 0) + { // ERROR: calibration busy too long + res = QUCPU_INT_UCLOCK_WAITCALDONE_ERR_BSY_TO; + } // ERROR: calibration busy too long + + return(res); +} // fi_WaitCalDone diff --git a/libopae/src/usrclk/user_clk_pgm_uclock.h b/libopae/src/usrclk/user_clk_pgm_uclock.h new file mode 100644 index 000000000000..df99e2db8862 --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock.h @@ -0,0 +1,205 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +//**************************************************************************** +// Arthur.Sheiman@Intel.com Created: 03-31-16 +// Revised: 10-26-16 18:28 +// +// User Clock header file +// +//**************************************************************************** + +#ifndef USER_CLK_PGM_UCLK_H_ +#define USER_CLK_PGM_UCLK_H_ + +#include + +// .h include, defines +#include "user_clk_pgm_uclock_freq_template_D.h" +// Errors, decimal code +#include "user_clk_pgm_uclock_eror_messages_D.h" +// Private member variables and objects +#include "user_clk_pgm_uclock_freq_template_A.h" +#include "user_clk_pgm_uclock_eror_messages_A.h" + +#include "common_int.h" + +// qph_user_clk.sv Equates +#if defined(DEF_BDX_P) +// BDX-P: +#define QUCPU_UI64_PRT_UCLK_CMD_0 ((uint64_t)0x0000000000000605LLU) // 0x03028 / 8 = 0x00605 +#define QUCPU_UI64_PRT_UCLK_CMD_1 ((uint64_t)0x0000000000000606LLU) // 0x03030 / 8 = 0x00606 +#define QUCPU_UI64_PRT_UCLK_STS_0 ((uint64_t)0x0000000000000607LLU) // 0x03038 / 8 = 0x00607 +#define QUCPU_UI64_PRT_UCLK_STS_1 ((uint64_t)0x0000000000000608LLU) // 0x03040 / 8 = 0x00608 + +#elif defined(DEF_SKX_P) +// SKX-P: +#define QUCPU_UI64_PRT_UCLK_CMD_0 ((uint64_t)0x000000000000000aLLU) // 0x00050 / 8 = 0x0060a +#define QUCPU_UI64_PRT_UCLK_CMD_1 ((uint64_t)0x000000000000000bLLU) // 0x00058 / 8 = 0x0060b +#define QUCPU_UI64_PRT_UCLK_STS_0 ((uint64_t)0x000000000000000cLLU) // 0x00060 / 8 = 0x0060c +#define QUCPU_UI64_PRT_UCLK_STS_1 ((uint64_t)0x000000000000000dLLU) // 0x00068 / 8 = 0x0060d +#endif + +#define QUCPU_UI64_AFU_MMIO_PRT_OFFSET_QW ((uint64_t)0x0000000000000000LLU) // 0x00000 / 8 = 0x00000 + +#define QUCPU_UI64_CMD_0_SR1_b58 ((uint64_t)0x0400000000000000LLU) // fPLL Select: 0=refclk0, 1=refclk1 +#define QUCPU_UI64_CMD_0_PDN_b57 ((uint64_t)0x0200000000000000LLU) // fPLL Powerdoen +#define QUCPU_UI64_CMD_0_PRS_b56 ((uint64_t)0x0100000000000000LLU) // fPLL management reset +#define QUCPU_UI64_CMD_0_MRN_b52 ((uint64_t)0x0010000000000000LLU) // mmmach machine reset_n +#define QUCPU_UI64_CMD_0_SEQ_b49t48 ((uint64_t)0x0003000000000000LLU) // mmmach sequence +#define QUCPU_UI64_CMD_0_WRT_b44 ((uint64_t)0x0000100000000000LLU) // mmmach write +#define QUCPU_UI64_CMD_0_ADR_b41t32 ((uint64_t)0x000003ff00000000LLU) // mmmach MM address +#define QUCPU_UI64_CMD_0_DAT_b31t00 ((uint64_t)0x00000000ffffffffLLU) // mmmach MM write data + +#define QUCPU_UI64_CMD_0_AMM_b51t00 ((uint64_t)0x000fffffffffffffLLU) // Avmm mmmach portion + +#define QUCPU_UI64_STS_0_ERR_b63 ((uint64_t)0x8000000000000000LLU) // mmmach error +#define QUCPU_UI64_STS_0_RCK_b62 ((uint64_t)0x4000000000000000LLU) // 0=refclk0, 1=refclk1 +#define QUCPU_UI64_STS_0_BSY_b61 ((uint64_t)0x2000000000000000LLU) // fPLL cal busy +#define QUCPU_UI64_STS_0_LCK_b60 ((uint64_t)0x1000000000000000LLU) // fPLL locked +#define QUCPU_UI64_STS_0_SR1_b58 ((uint64_t)0x0400000000000000LLU) // fPLL Select: 0=refclk0, 1=refclk1 +#define QUCPU_UI64_STS_0_PDN_b57 ((uint64_t)0x0200000000000000LLU) // fPLL Powerdoen +#define QUCPU_UI64_STS_0_PRS_b56 ((uint64_t)0x0100000000000000LLU) // fPLL management reset +#define QUCPU_UI64_STS_0_MRN_b52 ((uint64_t)0x0010000000000000LLU) // mmmach machine reset_n +#define QUCPU_UI64_STS_0_SEQ_b49t48 ((uint64_t)0x0003000000000000LLU) // mmmach sequence +#define QUCPU_UI64_STS_0_WRT_b44 ((uint64_t)0x0000100000000000LLU) // mmmach write +#define QUCPU_UI64_STS_0_ADR_b41t32 ((uint64_t)0x000003ff00000000LLU) // mmmach MM address +#define QUCPU_UI64_STS_0_DAT_b31t00 ((uint64_t)0x00000000ffffffffLLU) // mmmach MM read data + +#define QUCPU_UI64_CMD_1_MEA_b32 ((uint64_t)0x0000000100000000LLU) // 1: measure user clock; 0: measure 2nd clock, div2 + +#define QUCPU_UI64_STS_1_VER_b63t60 ((uint64_t)0xf000000000000000LLU) // frequency in 10 kHz units +#define QUCPU_UI64_STS_1_MEA_b32 ((uint64_t)0x0000000100000000LLU) // 1: measure user clock; 0: measure 2nd clock, div2 +#define QUCPU_UI64_STS_1_FRQ_b16t00 ((uint64_t)0x000000000001ffffLLU) // frequency in 10 kHz units + +#define QUCPU_UI64_STS_1_VER_version ((uint64_t)0x03LLU) // Expected version number + + +#define QUCPU_UI64_AVMM_FPLL_IPI_200 ((uint64_t)0x200LLU) // IP identifer +#define QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RFDUAL ((uint64_t)0x05LLU) // Expected ID, RF=100 MHz & RF=322.265625 MHz +#define QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF100M ((uint64_t)0x06LLU) // Expected ID, RF=100 MHz +#define QUCPU_UI64_AVMM_FPLL_IPI_200_IDI_RF322M ((uint64_t)0x07LLU) // Expected ID, RF=322.265625 MHz + +#define QUCPU_UI64_AVMM_FPLL_GPR_280 ((uint64_t)0x280LLU) +#define QUCPU_UI64_AVMM_FPLL_GPR_280_PDN_b00 ((uint64_t)0x0000000000000001LLU) // Powerdown when override set +#define QUCPU_UI64_AVMM_FPLL_GPR_280_ADM_b01 ((uint64_t)0x0000000000000001LLU) // 1: Override listen to ADME; 0: listen to powerdown port + +// Bugs, decimal code +#define QUCPU_INT_UCLOCK_BUG_SLEEP_SHORT ((int) 1) // Bug in fv_SleepShort + +// Structures and Types +struct QUCPU_sInitz { + uint64_t u64i_Version; // Version of clock user + uint64_t u64i_PLL_ID; // PLL ID + uint64_t u64i_NumFrq_Intg_End; // Integer/exact fPLL indices [0 ..End] + uint64_t u64i_NumFrq_Frac_Beg; // Fractional fPLL indices [Beg..End] + uint64_t u64i_NumFrq_Frac_End; + uint64_t u64i_NumFrq; // Array frequency # of elements + uint64_t u64i_NumReg; // Array registers # of elements + uint64_t u64i_NumRck; // Array ref-clocks # of elements +}; + +struct QUCPU_sFreqs { + uint64_t u64i_Frq_ClkUsr; // Read user clock frequency (Hz) + uint64_t u64i_Frq_DivBy2; // Read user clock frequency (Hz) divided-by-2 output +}; + +typedef struct QUCPU_sInitz QUCPU_tInitz; + +typedef struct QUCPU_sFreqs QUCPU_tFreqs; + + +struct QUCPU_Uclock +{ + char sysfs_path[SYSFS_PATH_MAX]; // Port sysfs path + int i_Bug_First; // First bug + int i_Bug_Last; // Lasr bug + int i_InitzState; // Initialization state + QUCPU_tInitz tInitz_InitialParams; // Initialization parameters + uint64_t u64i_cmd_reg_0; // Command register 0 + uint64_t u64i_cmd_reg_1; // Command register 1 + uint64_t u64i_AVMM_seq ; // Sequence ID +}; + +int fi_GetFreqs(QUCPU_tFreqs *ptFreqs_retFreqs); + +int fi_SetFreqs(uint64_t u64i_Refclk, uint64_t u64i_FrqInx); + +int fi_RunInitz(const char* sysfs_path); + +int sysfs_read_file(const char *sysfs_path, const char * csr_path, uint64_t * value ); + +int sysfs_write_file(const char *sysfs_path, const char * csr_path, uint64_t value); + +int fi_WaitCalDone(void); + +void fv_BugLog(int i_BugID); + +int fi_AvmmReadModifyWrite(uint64_t u64i_AvmmAdr, + uint64_t u64i_AvmmDat, + uint64_t u64i_AvmmMsk); + +int fi_AvmmReadModifyWriteVerify(uint64_t u64i_AvmmAdr, + uint64_t u64i_AvmmDat, + uint64_t u64i_AvmmMsk); + +void fv_SleepShort(long int li_sleep_nanoseconds); + +int fi_AvmmWrite(uint64_t u64i_AvmmAdr, uint64_t u64i_WriteData); + +int fi_AvmmRead(uint64_t u64i_AvmmAdr, uint64_t *pu64i_ReadData); + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* @brief Get fpga user clock +* +* @param syfs_path port sysfs path +* @parm pointer to high user clock +* @parm pointer to low user clock +* +* @return error code +*/ +fpga_result get_userclock(const char* sysfs_path, uint64_t *userclk_high, uint64_t *userclk_low); + +/** +* @brief set fpga user clock +* +* @param syfs_path port sysfs path +* @parm high user clock +* @parm low user clock +* +* @return error code +*/ +fpga_result set_userclock(const char* sysfs_path, uint64_t userclk_high, uint64_t userclk_low); + +#ifdef __cplusplus +} +#endif + +#endif // end USER_CLK_PGM_UCLK_H_ + diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages.h b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages.h new file mode 100644 index 000000000000..1e7f069ef1c2 --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages.h @@ -0,0 +1,49 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Arthur.Sheiman@Intel.com Created: 09-08-16 +// Revision: 10-18-16 18:06 + + +const char * pac_UclockErrorMsg[] = { + "QUCPU_Uclock: No error.\0", + "RunInitz: RTL versions number incompatible.\0", + "RunInitz: PLL RTL has illegal ID.\0", + "Timeout waiting for calibration.\0", + "AvmmRMW: Verify error.\0", + "AvmmRWcom: Timeout with AVMM transaction.\0", + "GetFreqs: Not initialized.\0", + "SetFreqs: Not initialized.\0", + "SetFreqs: Illegal reference clock index.\0", + "SetFreqs: RTL not configured for 100 MHz SYSCLK reflk.\0", + "SetFreqs: RTL not configured for 322.265625 MHz reflk.\0", + "SetFreqs: Requested frequency too high.\0", + "SetFreqs: Illegal ExactFreq mode requested.\0", + "SetFreqs: Use 322.265625 MHz refclk for ExactFreq mode.\0", + "SetFreqs: PLL did unlock during power down.\0", + "SetFreqs: Timeout waiting for PLL to lock.\0", + "ERROR: MSG INDEX OUT OF RANGE\0" // "+1" message +}; diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_A.h b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_A.h new file mode 100644 index 000000000000..12e0f5d1747c --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_A.h @@ -0,0 +1,27 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +//static const char * pac_UclockErrorMsg[]; diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_D.h b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_D.h new file mode 100644 index 000000000000..f3cbfba33f3a --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_eror_messages_D.h @@ -0,0 +1,48 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Arthur.Sheiman@Intel.com Created: 09-08-16 +// Revision: 10-18-16 18:06 + + +// Errors, decimal code +#define QUCPU_INT_UCLOCK_NO_ERROR ((int) 0) // No error +#define QUCPU_INT_UCLOCK_RUNINITZ_ERR_VER ((int) 1) // Wrong Uclock version error +#define QUCPU_INT_UCLOCK_RUNINITZ_ERR_FPLL_ID_ILLEGAL ((int) 2) // Check PLL: identifier illegal +#define QUCPU_INT_UCLOCK_WAITCALDONE_ERR_BSY_TO ((int) 3) // WaitCalDone: timeout +#define QUCPU_INT_UCLOCK_AVMMRMWV_ERR_VERIFY ((int) 4) // AvmmRMW: verify failure +#define QUCPU_INT_UCLOCK_AVMMRWCOM_ERR_TIMEOUT ((int) 5) // AvmmRWcom: timeout +#define QUCPU_INT_UCLOCK_GETFREQS_ERR_INITZSTATE ((int) 6) // GetFreqs: missing initialization +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_INITZSTATE ((int) 7) // SetFreqs: missing initialization +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_ILLEGAL ((int) 8) // SetFreqs: illegal refclk index +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_100M_MISSING ((int) 9) // SetFreqs: 100 MHz refclk missing from RTL +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_REFCLK_322M_MISSING ((int) 10) // SetFreqs: 322 MHz refclk missing from RTL +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_OVERRANGE ((int) 11) // SetFreqs: f-index > END +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_INTG_RANGE_BAD ((int) 12) // SetFreqs: integer-PLL mode f-index invalid +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_FINDEX_INTG_NEEDS_322M ((int) 13) // SetFreqs: integer-PLL mode needs 322 MHz ref +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_PLL_NO_UNLOCK ((int) 14) // SetFreqs: PLL would not unlock +#define QUCPU_INT_UCLOCK_SETFREQS_ERR_PLL_LOCK_TO ((int) 15) // SetFreqs: timed out waiting for lock +#define QUCPU_INT_UCLOCK_NUM_ERROR_MESSAGES ((int) 16) // Number of error messages diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_freq_template.h b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template.h new file mode 100644 index 000000000000..6b5154893e20 --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template.h @@ -0,0 +1,18046 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Arthur.Sheiman@Intel.com Created: 09-08-16 +// Revision: 03-21-17 19:51 + + +const uint32_t scu32ia3d_DiffMifTbl [QUCPU_INT_NUMFRQ] [QUCPU_INT_NUMREG] [QUCPU_INT_NUMRCK] = { + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0b}, + {0x110ff1e, 0x110ff16}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff40}, + {0x12cff08, 0x12cff18}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f46}, + {0x1347c30, 0x1347c50}, + {0x135ff03, 0x135ff03}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff05}, + {0x110ff1e, 0x110ff0a}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff0a}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c30}, + {0x135ff03, 0x135ff03}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 0x1347c40}, + {0x135ff03, 0x135ff04}, + {0x1427f00, 0x1427f00} }, + + { {0x10fff0f, 0x10fff0a}, + {0x110ff1e, 0x110ff14}, + {0x111ff30, 0x111ff30}, + {0x12afc04, 0x12afc04}, + {0x12bff1e, 0x12bff10}, + {0x12cff08, 0x12cff08}, + {0x12dff01, 0x12dff01}, + {0x12eff00, 0x12eff00}, + {0x12fff00, 0x12fff00}, + {0x130ff00, 0x130ff00}, + {0x1337f42, 0x1337f4a}, + {0x1347c30, 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0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff1e, 0x12bff13}, + {0x12cff08, 0x12cff10}, + {0x12dffe1, 0x12dffe2}, + {0x12eff7a, 0x12eff28}, + {0x12fff14, 0x12fff02}, + {0x130ffee, 0x130ff32}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff1e, 0x12bff13}, + {0x12cff08, 0x12cff10}, + {0x12dff5c, 0x12dff24}, + {0x12eff8f, 0x12eff52}, + {0x12fffc2, 0x12fffc6}, + {0x130fff5, 0x130ff36}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff1e, 0x12bff13}, + {0x12cff08, 0x12cff10}, + {0x12dffd7, 0x12dff66}, + {0x12effa3, 0x12eff7b}, + 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0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff15}, + {0x12cff08, 0x12cff10}, + {0x12dffeb, 0x12dff0d}, + {0x12eff51, 0x12eff03}, + {0x12fffb8, 0x12fff6a}, + {0x130ff5e, 0x130fff3}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff15}, + {0x12cff08, 0x12cff10}, + {0x12dff66, 0x12dff4f}, + {0x12eff66, 0x12eff2c}, + {0x12fff66, 0x12fff2e}, + {0x130ff66, 0x130fff8}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff15}, + {0x12cff08, 0x12cff10}, + {0x12dffe1, 0x12dff91}, + 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{0x12fff85, 0x12fff13}, + {0x130ffab, 0x130ff23}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff33, 0x12dffe3}, + {0x12eff33, 0x12effc8}, + {0x12fff33, 0x12fffd7}, + {0x130ffb3, 0x130ff27}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dffae, 0x12dff25}, + {0x12eff47, 0x12efff2}, + {0x12fffe1, 0x12fff9b}, + {0x130ffba, 0x130ff2c}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff28, 0x12dff67}, + {0x12eff5c, 0x12eff1b}, + {0x12fff8f, 0x12fff60}, + {0x130ffc2, 0x130ff31}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dffa3, 0x12dffa9}, + {0x12eff70, 0x12eff44}, + {0x12fff3d, 0x12fff24}, + {0x130ffca, 0x130ff36}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff1e, 0x12dffeb}, + {0x12eff85, 0x12eff6d}, + {0x12fffeb, 0x12fffe8}, + {0x130ffd1, 0x130ff3a}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff99, 0x12dff2d}, + {0x12eff99, 0x12eff97}, + {0x12fff99, 0x12fffac}, + {0x130ffd9, 0x130ff3f}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff14, 0x12dff70}, + {0x12effae, 0x12effc0}, + {0x12fff47, 0x12fff70}, + {0x130ffe1, 0x130ff44}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff8f, 0x12dffb2}, + {0x12effc2, 0x12effe9}, + {0x12ffff5, 0x12fff34}, + {0x130ffe8, 0x130ff49}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff0a, 0x12dfff4}, + {0x12effd7, 0x12eff12}, + {0x12fffa3, 0x12ffff9}, + {0x130fff0, 0x130ff4d}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff23, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff85, 0x12dff36}, + {0x12effeb, 0x12eff3c}, + {0x12fff51, 0x12fffbd}, + {0x130fff8, 0x130ff52}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} }, + + { {0x10fffff, 0x10fffff}, + {0x110ff03, 0x110ff03}, + {0x111ff10, 0x111ff10}, + {0x12afce4, 0x12afce4}, + {0x12bff24, 0x12bff16}, + {0x12cff08, 0x12cff10}, + {0x12dff01, 0x12dff78}, + {0x12eff00, 0x12eff65}, + {0x12fff00, 0x12fff81}, + {0x130ff00, 0x130ff57}, + {0x1337f0a, 0x1337f0a}, + {0x1347c10, 0x1347c10}, + {0x135ff03, 0x135ff03}, + {0x1427f04, 0x1427f04} } +}; diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_A.h b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_A.h new file mode 100644 index 000000000000..d22423467aa3 --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_A.h @@ -0,0 +1,27 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +extern const uint32_t scu32ia3d_DiffMifTbl [QUCPU_INT_NUMFRQ] [QUCPU_INT_NUMREG] [QUCPU_INT_NUMRCK]; diff --git a/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_D.h b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_D.h new file mode 100644 index 000000000000..239bc006009a --- /dev/null +++ b/libopae/src/usrclk/user_clk_pgm_uclock_freq_template_D.h @@ -0,0 +1,38 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Arthur.Sheiman@Intel.com Created: 09-08-16 +// Revision: 03-21-17 19:51 + + +#define QUCPU_INT_NUMFRQ_INTG_END ((int) 2) +#define QUCPU_INT_NUMFRQ_FRAC_BEG ((int) 100) +#define QUCPU_INT_NUMFRQ_FRAC_END ((int) 1200) +#define QUCPU_INT_NUMFRQ_CLIP ((int) 600) +#define QUCPU_INT_NUMFRQ ((int) 1201) +#define QUCPU_INT_NUMREG ((int) 14) +#define QUCPU_INT_NUMRCK ((int) 2) + diff --git a/libopae/src/wsid_list.c b/libopae/src/wsid_list.c new file mode 100644 index 000000000000..0dc4455dc525 --- /dev/null +++ b/libopae/src/wsid_list.c @@ -0,0 +1,169 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include "wsid_list_int.h" + +/* mutex to protect global data structures */ +extern pthread_mutex_t global_lock; + +/** + * @brief Add entry to linked list for WSIDs + * Will allocate memory (which is freed by wsid_del() or wsid_cleanup()) + * @param root + * @param wsid + * @param addr + * @param phys + * @param len + * @param offset + * + * @return true if success, false otherwise + */ +bool wsid_add(struct wsid_map **root, + uint64_t wsid, + uint64_t addr, + uint64_t phys, + uint64_t len, + uint64_t offset, + uint64_t index, + int flags) +{ + struct wsid_map *tmp = malloc(sizeof(struct wsid_map)); + + if (!tmp) + return false; + + tmp->wsid = wsid; + tmp->addr = addr; + tmp->phys = phys; + tmp->len = len; + tmp->offset = offset; + tmp->index = index; + tmp->flags = flags; + tmp->next = *root; + + *root = tmp; + return true; +} + +/** + * @brief Remove entry from linked list + * + * @param root + * @param wsid + * + * @return true if success, false otherwise + */ +bool wsid_del(struct wsid_map **root, uint64_t wsid) +{ + struct wsid_map *tmp = *root; + + if (!*root) + return false; /* empty list */ + + if ((*root)->wsid == wsid) { /* first entry */ + *root = (*root)->next; + free(tmp); + return true; + } + + while (tmp->next && tmp->next->wsid != wsid) { /* find */ + tmp = tmp->next; + } + + if (!tmp->next) + return false; /* not found */ + + struct wsid_map *tmp2 = tmp->next; + tmp->next = tmp->next->next; + free(tmp2); + + return true; +} + +/** + * @brief Clean up remaining entries in linked list + * Will delete all remaining entries + * + * @param root + */ +void wsid_cleanup(struct wsid_map **root) +{ + if (!*root) + return; + + while ((*root)->next) { + struct wsid_map *tmp = *root; + *root = (*root)->next; + free(tmp); + } + + free(*root); + *root = NULL; +} + +/** + * @ brief Find entry in linked list + * + * @param root + * @param wsid + * + * @return + */ +struct wsid_map *wsid_find(struct wsid_map *root, uint64_t wsid) +{ + struct wsid_map *tmp = root; + + while (tmp && tmp->wsid != wsid) + tmp = tmp->next; + + return tmp; +} + +/** + * @ brief Find entry in linked list + * + * @param root + * @param index + * + * @return + */ +struct wsid_map *wsid_find_by_index(struct wsid_map *root, uint32_t index) +{ + struct wsid_map *tmp = root; + + while (tmp && tmp->index != index) + tmp = tmp->next; + + return tmp; +} + diff --git a/libopae/src/wsid_list_int.h b/libopae/src/wsid_list_int.h new file mode 100644 index 000000000000..3fc95bde7bea --- /dev/null +++ b/libopae/src/wsid_list_int.h @@ -0,0 +1,51 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_WSID_LIST_INT_H__ +#define __FPGA_WSID_LIST_INT_H__ + +#include "opae/utils.h" +#include "types_int.h" + +/* + * WSID list structure manipulation functions + */ +bool wsid_add(struct wsid_map **root, + uint64_t wsid, + uint64_t addr, + uint64_t phys, + uint64_t len, + uint64_t offset, + uint64_t index, + int flags); +bool wsid_del(struct wsid_map **root, uint64_t wsid); +void wsid_cleanup(struct wsid_map **root); +uint64_t wsid_gen(void); + +struct wsid_map *wsid_find(struct wsid_map *root, uint64_t wsid); +struct wsid_map *wsid_find_by_index(struct wsid_map *root, uint32_t index); + +#endif // ___FPGA_COMMON_INT_H__ diff --git a/safe_string/CMakeLists.txt b/safe_string/CMakeLists.txt new file mode 100644 index 000000000000..62538ca6a6b0 --- /dev/null +++ b/safe_string/CMakeLists.txt @@ -0,0 +1,113 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +project(safe_string) + +include_directories(${OPAE_INCLUDE_DIR}) + +set(SRC + abort_handler_s.c + ignore_handler_s.c + safeclib_private.h + safe_mem_constraint.c + safe_mem_constraint.h + safe_str_constraint.c + safe_str_constraint.h + memcmp16_s.c + memcmp32_s.c + memcmp_s.c + memcpy16_s.c + memcpy32_s.c + memcpy_s.c + memmove16_s.c + memmove32_s.c + memmove_s.c + mem_primitives_lib.c + mem_primitives_lib.h + memset16_s.c + memset32_s.c + memset_s.c + memzero16_s.c + memzero32_s.c + memzero_s.c + snprintf_support.c + stpcpy_s.c + stpncpy_s.c + strcasecmp_s.c + strcasestr_s.c + strcat_s.c + strcmpfld_s.c + strcmp_s.c + strcpyfldin_s.c + strcpyfldout_s.c + strcpyfld_s.c + strcpy_s.c + strcspn_s.c + strfirstchar_s.c + strfirstdiff_s.c + strfirstsame_s.c + strisalphanumeric_s.c + strisascii_s.c + strisdigit_s.c + strishex_s.c + strislowercase_s.c + strismixedcase_s.c + strispassword_s.c + strisuppercase_s.c + strlastchar_s.c + strlastdiff_s.c + strlastsame_s.c + strljustify_s.c + strcat_s.c + strncpy_s.c + strnlen_s.c + strnterminate_s.c + strpbrk_s.c + strprefix_s.c + strremovews_s.c + strspn_s.c + strstr_s.c + strtok_s.c + strtolowercase_s.c + strtouppercase_s.c + strzero_s.c + wcpcpy_s.c + wcscat_s.c + wcscpy_s.c + wcsncat_s.c + wcsncpy_s.c + wcsnlen_s.c + wmemcmp_s.c + wmemcpy_s.c + wmemmove_s.c + wmemset_s.c +) + +add_library(safestr STATIC ${SRC}) + +set_property(TARGET safestr PROPERTY C_STANDARD 99) +set_property(TARGET safestr PROPERTY POSITION_INDEPENDENT_CODE ON) +target_compile_definitions(safestr PRIVATE PIC=1) diff --git a/safe_string/abort_handler_s.c b/safe_string/abort_handler_s.c new file mode 100644 index 000000000000..4d7a2775fc4e --- /dev/null +++ b/safe_string/abort_handler_s.c @@ -0,0 +1,76 @@ +/*------------------------------------------------------------------ + * abort_handler_s.c + * + * 2012, Jonathan Toppins + * + * Copyright (c) 2012 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" + +/** + * NAME + * abort_handler_s + * + * SYNOPSIS + * #include "safe_lib.h" + * void abort_handler_s(const char *msg, void *ptr, errno_t error) + * + * DESCRIPTION + * This function writes a message on the standard error stream in + * an implementation-defined format. The message shall include the + * string pointed to by msg. The abort_handler_s function then calls + * the abort function. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * msg Pointer to the message describing the error + * + * ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * RETURN VALUE + * Does not return to caller. + * + * ALSO SEE + * ignore_handler_s() + * + */ + +/* void abort_handler_s(const char *msg, void *ptr, errno_t error) */ +void opae_safestr_abort_handler_s(const char *msg, void *ptr, errno_t error) + +{ + slprintf("ABORT CONSTRAINT HANDLER: (%u) %s\n", error, + (msg) ? msg : "Null message"); + slabort(); +} +/* EXPORT_SYMBOL(abort_handler_s); */ diff --git a/safe_string/ignore_handler_s.c b/safe_string/ignore_handler_s.c new file mode 100644 index 000000000000..edfa2704fd93 --- /dev/null +++ b/safe_string/ignore_handler_s.c @@ -0,0 +1,73 @@ +/*------------------------------------------------------------------ + * ignore_handler_s.c + * + * 2012, Jonathan Toppins + * + * Copyright (c) 2012 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" + +/** + * NAME + * ignore_handler_s + * + * SYNOPSIS + * #include "safe_lib.h" + * void ignore_handler_s(const char *msg, void *ptr, errno_t error) + * + * DESCRIPTION + * This function simply returns to the caller. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * msg Pointer to the message describing the error + * + * ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * RETURN VALUE + * Returns no value. + * + * ALSO SEE + * abort_handler_s() + * + */ + +/* void ignore_handler_s(const char *msg, void *ptr, errno_t error) */ +void opae_safestr_ignore_handler_s(const char *msg, void *ptr, errno_t error) +{ + + sldebug_printf("IGNORE CONSTRAINT HANDLER: (%u) %s\n", error, + (msg) ? msg : "Null message"); + return; +} +/* EXPORT_SYMBOL(ignore_handler_s); */ diff --git a/safe_string/mem_primitives_lib.c b/safe_string/mem_primitives_lib.c new file mode 100644 index 000000000000..cc189e5ea965 --- /dev/null +++ b/safe_string/mem_primitives_lib.c @@ -0,0 +1,853 @@ +/*------------------------------------------------------------------ + * mem_primitives_lib.c - Unguarded Memory Copy Routines + * + * February 2005, Bo Berry + * + * Copyright (c) 2005-2009 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "mem_primitives_lib.h" + +/* + * mem_primitives_lib.c provides unguarded memory routines + * that are used by the safe_mem_library. These routines + * may also be used by an application, but the application + * is responsible for all parameter validation and alignment. + */ + +/** + * NAME + * mem_prim_set - Sets memory to value + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_set(void *dest, uint32_t len, uint8_t value) + * + * DESCRIPTION + * Sets len bytes starting at dest to the specified value + * + * INPUT PARAMETERS + * dest - pointer to memory that will be set to value + * + * len - number of bytes to be set + * + * value - byte value + * + * OUTPUT PARAMETERS + * dest - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_set (void *dest, uint32_t len, uint8_t value) +{ + uint8_t *dp; + uint32_t count; + uint32_t lcount; + + uint32_t *lp; + uint32_t value32; + + count = len; + + dp = dest; + + value32 = value | (value << 8) | (value << 16) | (value << 24); + + /* + * First, do the few bytes to get uint32_t aligned. + */ + for (; count && ( (uintptr_t)dp & (sizeof(uint32_t)-1) ); count--) { + *dp++ = value; + } + + /* + * Then do the uint32_ts, unrolled the loop for performance + */ + lp = (uint32_t *)dp; + lcount = count >> 2; + + while (lcount != 0) { + + switch (lcount) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *lp++ = value32; *lp++ = value32; *lp++ = value32; *lp++ = value32; + *lp++ = value32; *lp++ = value32; *lp++ = value32; *lp++ = value32; + *lp++ = value32; *lp++ = value32; *lp++ = value32; *lp++ = value32; + *lp++ = value32; *lp++ = value32; *lp++ = value32; *lp++ = value32; + lcount -= 16; + break; + + case 15: *lp++ = value32; + case 14: *lp++ = value32; + case 13: *lp++ = value32; + case 12: *lp++ = value32; + case 11: *lp++ = value32; + case 10: *lp++ = value32; + case 9: *lp++ = value32; + case 8: *lp++ = value32; + + case 7: *lp++ = value32; + case 6: *lp++ = value32; + case 5: *lp++ = value32; + case 4: *lp++ = value32; + case 3: *lp++ = value32; + case 2: *lp++ = value32; + case 1: *lp++ = value32; + lcount = 0; + break; + } + } /* end while */ + + + dp = (uint8_t *)lp; + + /* + * compute the number of remaining bytes + */ + count &= (sizeof(uint32_t)-1); + + /* + * remaining bytes + */ + for (; count; dp++, count--) { + *dp = value; + } + + return; +} + + +/** + * NAME + * mem_prim_set16 - Sets memory to value + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_set16(uint16_t *dp, uint32_t len, uint16_t value) + * + * DESCRIPTION + * Sets len uint16_ts starting at dest to the specified value. + * Pointers must meet system alignment requirements. + * + * INPUT PARAMETERS + * dest - pointer to memory that will be set to value + * + * len - number of uint16_ts to be set + * + * value - uint16_t value + * + * OUTPUT PARAMETERS + * dest - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_set16 (uint16_t *dp, uint32_t len, uint16_t value) +{ + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + len -= 16; + break; + + case 15: *dp++ = value; + case 14: *dp++ = value; + case 13: *dp++ = value; + case 12: *dp++ = value; + case 11: *dp++ = value; + case 10: *dp++ = value; + case 9: *dp++ = value; + case 8: *dp++ = value; + + case 7: *dp++ = value; + case 6: *dp++ = value; + case 5: *dp++ = value; + case 4: *dp++ = value; + case 3: *dp++ = value; + case 2: *dp++ = value; + case 1: *dp++ = value; + len = 0; + break; + } + } /* end while */ + + return; +} + + +/** + * NAME + * mem_prim_set32 - Sets memory to the uint32_t value + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_set32(uint32_t *dp, uint32_t len, uint32_t value) + * + * DESCRIPTION + * Sets len uint32_ts starting at dest to the specified value + * Pointers must meet system alignment requirements. + * + * INPUT PARAMETERS + * dest - pointer to memory that will be set to value + * + * len - number of uint32_ts to be set + * + * value - uint32_t value + * + * OUTPUT PARAMETERS + * dest - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_set32 (uint32_t *dp, uint32_t len, uint32_t value) +{ + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + *dp++ = value; *dp++ = value; *dp++ = value; *dp++ = value; + len -= 16; + break; + + case 15: *dp++ = value; + case 14: *dp++ = value; + case 13: *dp++ = value; + case 12: *dp++ = value; + case 11: *dp++ = value; + case 10: *dp++ = value; + case 9: *dp++ = value; + case 8: *dp++ = value; + + case 7: *dp++ = value; + case 6: *dp++ = value; + case 5: *dp++ = value; + case 4: *dp++ = value; + case 3: *dp++ = value; + case 2: *dp++ = value; + case 1: *dp++ = value; + len = 0; + break; + } + } /* end while */ + + return; +} + + +/** + * NAME + * mem_prim_move - Move (handles overlap) memory + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_move(void *dest, const void *src, uint32_t len) + * + * DESCRIPTION + * Moves at most slen bytes from src to dest, up to dmax + * bytes. Dest may overlap with src. + * + * INPUT PARAMETERS + * dest - pointer to the memory that will be replaced by src. + * + * src - pointer to the memory that will be copied + * to dest + * + * len - maximum number bytes of src that can be copied + * + * OUTPUT PARAMETERS + * dest - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_move (void *dest, const void *src, uint32_t len) +{ + +#define wsize sizeof(uint32_t) +#define wmask (wsize - 1) + + uint8_t *dp = dest; + const uint8_t *sp = src; + + uint32_t tsp; + + /* + * Determine if we need to copy forward or backward (overlap) + */ + if ((uintptr_t)dp < (uintptr_t)sp) { + /* + * Copy forward. + */ + + /* + * get a working copy of src for bit operations + */ + tsp = (uintptr_t)sp; + + /* + * Try to align both operands. This cannot be done + * unless the low bits match. + */ + if ((tsp | (uintptr_t)dp) & wmask) { + /* + * determine how many bytes to copy to align operands + */ + if ((tsp ^ (uintptr_t)dp) & wmask || len < wsize) { + tsp = len; + + } else { + tsp = wsize - (tsp & wmask); + } + + len -= tsp; + + /* + * make the alignment + */ + do { + *dp++ = *sp++; + } while (--tsp); + } + + /* + * Now copy, then mop up any trailing bytes. + */ + tsp = len / wsize; + + if (tsp > 0) { + + do { + *(uint32_t *)dp = *(uint32_t *)sp; + + sp += wsize; + dp += wsize; + } while (--tsp); + } + + /* + * copy over the remaining bytes and we're done + */ + tsp = len & wmask; + + if (tsp > 0) { + do { + *dp++ = *sp++; + } while (--tsp); + } + + } else { + /* + * This section is used to copy backwards, to handle any + * overlap. The alignment requires (tps&wmask) bytes to + * align. + */ + + /* + * go to end of the memory to copy + */ + sp += len; + dp += len; + + /* + * get a working copy of src for bit operations + */ + tsp = (uintptr_t)sp; + + /* + * Try to align both operands. + */ + if ((tsp | (uintptr_t)dp) & wmask) { + + if ((tsp ^ (uintptr_t)dp) & wmask || len <= wsize) { + tsp = len; + } else { + tsp &= wmask; + } + + len -= tsp; + + /* + * make the alignment + */ + do { + *--dp = *--sp; + } while (--tsp); + } + + /* + * Now copy in uint32_t units, then mop up any trailing bytes. + */ + tsp = len / wsize; + + if (tsp > 0) { + do { + sp -= wsize; + dp -= wsize; + + *(uint32_t *)dp = *(uint32_t *)sp; + } while (--tsp); + } + + /* + * copy over the remaining bytes and we're done + */ + tsp = len & wmask; + if (tsp > 0) { + tsp = len & wmask; + do { + *--dp = *--sp; + } while (--tsp); + } + } + + return; +} + + +/** + * NAME + * mem_prim_move8 - Move (handles overlap) memory + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_move8(void *dest, const void *src, uint32_t len) + * + * DESCRIPTION + * Moves at most len uint8_ts from sp to dp. + * The destination may overlap with source. + * + * INPUT PARAMETERS + * dp - pointer to the memory that will be replaced by sp. + * + * sp - pointer to the memory that will be copied + * to dp + * + * len - maximum number uint8_t of sp that can be copied + * + * OUTPUT PARAMETERS + * dp - pointer to the memory that will be replaced by sp. + * + * RETURN VALUE + * none + * + */ +void +mem_prim_move8 (uint8_t *dp, const uint8_t *sp, uint32_t len) +{ + + /* + * Determine if we need to copy forward or backward (overlap) + */ + if (dp < sp) { + /* + * Copy forward. + */ + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + len -= 16; + break; + + case 15: *dp++ = *sp++; + case 14: *dp++ = *sp++; + case 13: *dp++ = *sp++; + case 12: *dp++ = *sp++; + case 11: *dp++ = *sp++; + case 10: *dp++ = *sp++; + case 9: *dp++ = *sp++; + case 8: *dp++ = *sp++; + + case 7: *dp++ = *sp++; + case 6: *dp++ = *sp++; + case 5: *dp++ = *sp++; + case 4: *dp++ = *sp++; + case 3: *dp++ = *sp++; + case 2: *dp++ = *sp++; + case 1: *dp++ = *sp++; + len = 0; + break; + } + } /* end while */ + + } else { + /* + * This section is used to copy backwards, to handle any + * overlap. The alignment requires (tps&wmask) bytes to + * align. + */ + + + /* + * go to end of the memory to copy + */ + sp += len; + dp += len; + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + len -= 16; + break; + + case 15: *--dp = *--sp; + case 14: *--dp = *--sp; + case 13: *--dp = *--sp; + case 12: *--dp = *--sp; + case 11: *--dp = *--sp; + case 10: *--dp = *--sp; + case 9: *--dp = *--sp; + case 8: *--dp = *--sp; + + case 7: *--dp = *--sp; + case 6: *--dp = *--sp; + case 5: *--dp = *--sp; + case 4: *--dp = *--sp; + case 3: *--dp = *--sp; + case 2: *--dp = *--sp; + case 1: *--dp = *--sp; + len = 0; + break; + } + } /* end while */ + } + + return; +} + + +/** + * NAME + * mem_prim_move16 - Move (handles overlap) memory + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_move16(void *dest, const void *src, uint32_t len) + * + * DESCRIPTION + * Moves at most len uint16_ts from sp to dp. + * The destination may overlap with source. + * + * INPUT PARAMETERS + * dp - pointer to the memory that will be replaced by sp. + * + * sp - pointer to the memory that will be copied + * to dp + * + * len - maximum number uint16_t of sp that can be copied + * + * OUTPUT PARAMETERS + * dp - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_move16 (uint16_t *dp, const uint16_t *sp, uint32_t len) +{ + + /* + * Determine if we need to copy forward or backward (overlap) + */ + if (dp < sp) { + /* + * Copy forward. + */ + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + len -= 16; + break; + + case 15: *dp++ = *sp++; + case 14: *dp++ = *sp++; + case 13: *dp++ = *sp++; + case 12: *dp++ = *sp++; + case 11: *dp++ = *sp++; + case 10: *dp++ = *sp++; + case 9: *dp++ = *sp++; + case 8: *dp++ = *sp++; + + case 7: *dp++ = *sp++; + case 6: *dp++ = *sp++; + case 5: *dp++ = *sp++; + case 4: *dp++ = *sp++; + case 3: *dp++ = *sp++; + case 2: *dp++ = *sp++; + case 1: *dp++ = *sp++; + len = 0; + break; + } + } /* end while */ + + } else { + /* + * This section is used to copy backwards, to handle any + * overlap. The alignment requires (tps&wmask) bytes to + * align. + */ + + /* + * go to end of the memory to copy + */ + sp += len; + dp += len; + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + len -= 16; + break; + + case 15: *--dp = *--sp; + case 14: *--dp = *--sp; + case 13: *--dp = *--sp; + case 12: *--dp = *--sp; + case 11: *--dp = *--sp; + case 10: *--dp = *--sp; + case 9: *--dp = *--sp; + case 8: *--dp = *--sp; + + case 7: *--dp = *--sp; + case 6: *--dp = *--sp; + case 5: *--dp = *--sp; + case 4: *--dp = *--sp; + case 3: *--dp = *--sp; + case 2: *--dp = *--sp; + case 1: *--dp = *--sp; + len = 0; + break; + } + } /* end while */ + } + + return; +} + + +/** + * NAME + * mem_prim_move32 - Move (handles overlap) memory + * + * SYNOPSIS + * #include "mem_primitives_lib.h" + * void + * mem_prim_move32(void *dest, const void *src, uint32_t len) + * + * DESCRIPTION + * Moves at most len uint32_ts from sp to dp. + * The destination may overlap with source. + * + * INPUT PARAMETERS + * dp - pointer to the memory that will be replaced by sp. + * + * sp - pointer to the memory that will be copied + * to dp + * + * len - maximum number uint32_t of sp that can be copied + * + * OUTPUT PARAMETERS + * dp - is updated + * + * RETURN VALUE + * none + * + */ +void +mem_prim_move32 (uint32_t *dp, const uint32_t *sp, uint32_t len) +{ + + /* + * Determine if we need to copy forward or backward (overlap) + */ + if (dp < sp) { + /* + * Copy forward. + */ + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; *dp++ = *sp++; + len -= 16; + break; + + case 15: *dp++ = *sp++; + case 14: *dp++ = *sp++; + case 13: *dp++ = *sp++; + case 12: *dp++ = *sp++; + case 11: *dp++ = *sp++; + case 10: *dp++ = *sp++; + case 9: *dp++ = *sp++; + case 8: *dp++ = *sp++; + + case 7: *dp++ = *sp++; + case 6: *dp++ = *sp++; + case 5: *dp++ = *sp++; + case 4: *dp++ = *sp++; + case 3: *dp++ = *sp++; + case 2: *dp++ = *sp++; + case 1: *dp++ = *sp++; + len = 0; + break; + } + } /* end while */ + + } else { + /* + * This section is used to copy backwards, to handle any + * overlap. + */ + + /* + * go to end of the memory to copy + */ + sp += len; + dp += len; + + while (len != 0) { + + switch (len) { + /* + * Here we do blocks of 8. Once the remaining count + * drops below 8, take the fast track to finish up. + */ + default: + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; *--dp = *--sp; + len -= 16; + break; + + case 15: *--dp = *--sp; + case 14: *--dp = *--sp; + case 13: *--dp = *--sp; + case 12: *--dp = *--sp; + case 11: *--dp = *--sp; + case 10: *--dp = *--sp; + case 9: *--dp = *--sp; + case 8: *--dp = *--sp; + + case 7: *--dp = *--sp; + case 6: *--dp = *--sp; + case 5: *--dp = *--sp; + case 4: *--dp = *--sp; + case 3: *--dp = *--sp; + case 2: *--dp = *--sp; + case 1: *--dp = *--sp; + len = 0; + break; + } + } /* end while */ + } + + return; +} diff --git a/safe_string/mem_primitives_lib.h b/safe_string/mem_primitives_lib.h new file mode 100644 index 000000000000..26c83d8585f3 --- /dev/null +++ b/safe_string/mem_primitives_lib.h @@ -0,0 +1,74 @@ +/*------------------------------------------------------------------ + * mem_primitives_lib.h - Unguarded Memory Copy Routines + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __MEM_PRIMITIVES_LIB_H__ +#define __MEM_PRIMITIVES_LIB_H__ + +#include "safeclib_private.h" + +/* + * These are prototypes for _unguarded_ memory routines. The caller must + * validate all parameters prior to invocation. Useful for diagnostics + * and system initialization processing. + */ + +/* moves (handles overlap) memory */ +extern void +mem_prim_move(void *dest, const void *src, uint32_t length); + + +/* uint8_t moves (handles overlap) memory */ +extern void +mem_prim_move8(uint8_t *dest, const uint8_t *src, uint32_t length); + +/* uint16_t moves (handles overlap) memory */ +extern void +mem_prim_move16(uint16_t *dest, const uint16_t *src, uint32_t length); + +/* uint32_t moves (handles overlap) memory */ +extern void +mem_prim_move32(uint32_t *dest, const uint32_t *src, uint32_t length); + + +/* set bytes */ +extern void +mem_prim_set(void *dest, uint32_t dmax, uint8_t value); + +/* set uint16_ts */ +extern void +mem_prim_set16(uint16_t *dest, uint32_t dmax, uint16_t value); + +/* set uint32_ts */ +extern void +mem_prim_set32(uint32_t *dest, uint32_t dmax, uint32_t value); + + +#endif /* __MEM_PRIMITIVES_LIB_H__ */ diff --git a/safe_string/memcmp16_s.c b/safe_string/memcmp16_s.c new file mode 100644 index 000000000000..f01edbd4a1e0 --- /dev/null +++ b/safe_string/memcmp16_s.c @@ -0,0 +1,173 @@ +/*------------------------------------------------------------------ + * memcmp16_s.c - Compares memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +/* #include "safe_mem_lib.h" */ + +/** + * NAME + * memcmp16_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcmp16_s(const uint16_t *dest, rsize_t dmax, + * const uint16_t *src, rsize_t smax, int *diff) + * + * DESCRIPTION + * Compares memory until they differ, and their difference is + * returned in diff. If the block of memory is the same, diff=0. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to compare against + * + * dmax maximum length of dest, in uint16_t + * + * src pointer to the source memory to compare with dest + * + * smax maximum length of src, in uint16_t + * + * *diff pointer to the diff which is an integer greater + * than, equal to or less than zero according to + * whether the object pointed to by dest is + * greater than, equal to or less than the object + * pointed to by src. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memcmp_s(), memcmp32_s() + * + */ +errno_t +memcmp16_s (const uint16_t *dest, rsize_t dmax, + const uint16_t *src, rsize_t smax, int *diff) +{ + + const uint16_t *dp; + const uint16_t *sp; + + dp = dest; + sp = src; + + /* + * must be able to return the diff + */ + if (diff == NULL) { + invoke_safe_mem_constraint_handler("memcmp16_s: diff is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + *diff = -1; /* default diff */ + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memcmp16_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (sp == NULL) { + invoke_safe_mem_constraint_handler("memcmp16_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcmp16_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM16) { + invoke_safe_mem_constraint_handler("memcmp16_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + invoke_safe_mem_constraint_handler("memcmp16_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + invoke_safe_mem_constraint_handler("memcmp16_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * no need to compare the same memory + */ + if (dp == sp) { + *diff = 0; + return (RCNEGATE(EOK)); + } + + /* + * now compare sp to dp + */ + *diff = 0; + while (dmax != 0 && smax != 0) { + if (*dp != *sp) { + *diff = *dp - *sp; + break; + } + + dmax--; + smax--; + + dp++; + sp++; + } + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memcmp16_s); */ diff --git a/safe_string/memcmp32_s.c b/safe_string/memcmp32_s.c new file mode 100644 index 000000000000..4d9b5a8ef9e4 --- /dev/null +++ b/safe_string/memcmp32_s.c @@ -0,0 +1,167 @@ +/*------------------------------------------------------------------ + * memcmp32_s.c - Compares memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +/* #include "safe_mem_lib.h" */ + +/** + * NAME + * memcmp32_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcmp32_s(const uint32_t *dest, rsize_t dmax, + * const uint32_t *src, rsize_t smax, int *diff) + * + * DESCRIPTION + * Compares memory until they differ, and their difference is + * returned in diff. If the block of memory is the same, diff=0. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to compare against + * + * dmax maximum length of dest, in uint32_t + * + * src pointer to the source memory to compare with dest + * + * smax maximum length of src, in uint32_t + * + * *diff pointer to the diff which is an integer greater + * than, equal to or less than zero according to + * whether the object pointed to by dest is + * greater than, equal to or less than the object + * pointed to by src. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memcmp_s(), memcmp16_s() + * + */ +errno_t +memcmp32_s (const uint32_t *dest, rsize_t dmax, + const uint32_t *src, rsize_t smax, int *diff) +{ + /* + * must be able to return the diff + */ + if (diff == NULL) { + invoke_safe_mem_constraint_handler("memcmp32_s: diff is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + *diff = -1; /* default diff */ + + + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memcmp32_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (src == NULL) { + invoke_safe_mem_constraint_handler("memcmp32_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcmp32_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("memcmp32_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + invoke_safe_mem_constraint_handler("memcmp32_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + invoke_safe_mem_constraint_handler("memcmp32_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * no need to compare the same memory + */ + if (dest == src) { + *diff = 0; + return (RCNEGATE(EOK)); + } + + /* + * now compare src to dest + */ + *diff = 0; + while (dmax != 0 && smax != 0) { + if (*dest != *src) { + *diff = *dest - *src; + break; + } + + dmax--; + smax--; + + dest++; + src++; + } + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memcmp32_s); */ diff --git a/safe_string/memcmp_s.c b/safe_string/memcmp_s.c new file mode 100644 index 000000000000..e37e166cc62c --- /dev/null +++ b/safe_string/memcmp_s.c @@ -0,0 +1,174 @@ +/*------------------------------------------------------------------ + * memcmp_s.c - Compares memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memcmp_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcmp_s(const void *dest, rsize_t dmax, + * const void *src, rsize_t smax, int *diff) + * + * DESCRIPTION + * Compares memory until they differ, and their difference is + * returned in diff. If the block of memory is the same, diff=0. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to compare against + * + * dmax maximum length of dest, in bytess + * + * src pointer to the source memory to compare with dest + * + * smax length of the source memory block + * + * *diff pointer to the diff which is an integer greater + * than, equal to or less than zero according to + * whether the object pointed to by dest is + * greater than, equal to or less than the object + * pointed to by src. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memcmp16_s(), memcmp32_s() + * + */ +errno_t +memcmp_s (const void *dest, rsize_t dmax, + const void *src, rsize_t smax, int *diff) +{ + const uint8_t *dp; + const uint8_t *sp; + + dp = dest; + sp = src; + + /* + * must be able to return the diff + */ + if (diff == NULL) { + invoke_safe_mem_constraint_handler("memcmp_s: diff is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + *diff = -1; /* default diff */ + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memcmp_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (sp == NULL) { + invoke_safe_mem_constraint_handler("memcmp_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcmp_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("memcmp_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + invoke_safe_mem_constraint_handler("memcmp_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + invoke_safe_mem_constraint_handler("memcmp_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * no need to compare the same memory + */ + if (dp == sp) { + *diff = 0; + return (RCNEGATE(EOK)); + } + + /* + * now compare sp to dp + */ + *diff = 0; + while (dmax > 0 && smax > 0) { + if (*dp != *sp) { + /*** *diff = *dp - *sp; ***/ + *diff = *dp < *sp ? -1 : 1; + break; + } + + dmax--; + smax--; + + dp++; + sp++; + } + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memcmp_s); */ diff --git a/safe_string/memcpy16_s.c b/safe_string/memcpy16_s.c new file mode 100644 index 000000000000..df7a802935cd --- /dev/null +++ b/safe_string/memcpy16_s.c @@ -0,0 +1,151 @@ +/*------------------------------------------------------------------ + * memcpy16_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memcpy16_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcpy16_s(uint16_t *dest, rsize_t dmax, + * const uint16_t *src, rsize_t smax) + * + * DESCRIPTION + * This function copies at most smax uint16_ts from src to dest, up to + * dmax. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be replaced by src. + * + * dmax maximum length of the resulting dest + * + * src pointer to the memory that will be copied to dest + * + * smax maximum number uint16_t of src to copy + * + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM16. + * smax shall not be greater than dmax. + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, the memcpy_s function stores + * zeros in the first dmax bytes of the object pointed to by dest + * if dest is not a null pointer and smax is valid. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP source memory overlaps destination + * + * ALSO SEE + * memcpy_s(), memcpy32_s(), memmove_s(), memmove16_s(), memmove32_s() + * + */ +errno_t +memcpy16_s (uint16_t *dest, rsize_t dmax, const uint16_t *src, rsize_t smax) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memcpy16_s: dest is NULL", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcpy16_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM16) { + invoke_safe_mem_constraint_handler("memcpy16_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set16(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy16_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set16(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy16_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (src == NULL) { + mem_prim_set16(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy16_s: src is NULL", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + /* + * overlap is undefined behavior, do not allow + */ + if( ((dest > src) && (dest < (src+smax))) || + ((src > dest) && (src < (dest+dmax))) ) { + mem_prim_set16(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy16_s: overlap undefined", + NULL, ESOVRLP); + return (RCNEGATE(ESOVRLP)); + } + + /* + * now perform the copy + */ + mem_prim_move16(dest, src, smax); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memcpy16_s); */ diff --git a/safe_string/memcpy32_s.c b/safe_string/memcpy32_s.c new file mode 100644 index 000000000000..b170daa9654a --- /dev/null +++ b/safe_string/memcpy32_s.c @@ -0,0 +1,150 @@ +/*------------------------------------------------------------------ + * memcpy32_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memcpy32_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcpy32_s(uint32_t *dest, rsize_t dmax, + * const uint32_t *src, rsize_t smax) + * + * DESCRIPTION + * This function copies at most smax uint32_ts from src to dest, up to + * dmax. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be replaced by src. + * + * dmax maximum length of the resulting dest + * + * src pointer to the memory that will be copied to dest + * + * smax maximum number uint32_t of src to copy + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM32. + * smax shall not be greater than dmax. + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, the memcpy_s function stores + * zeros in the first dmax bytes of the object pointed to by dest + * if dest is not a null pointer and smax is valid. + * + * RETURN VALUE + * EOK operation sucessful + * ESNULLP NULL pointer + * ESZEROL length was zero + * ESLEMAX length exceeds max + * ESOVRLP source memory overlaps destination + * + * ALSO SEE + * memcpy_s(), memcpy16_s(), memmove_s(), memmove16_s(), memmove32_s() + * + */ +errno_t +memcpy32_s (uint32_t *dest, rsize_t dmax, const uint32_t *src, rsize_t smax) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memcpy32_s: dest is NULL", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcpy32_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("memcpy32_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set32(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy32_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set32(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy32_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (src == NULL) { + mem_prim_set32(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy32_s: src is NULL", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + /* + * overlap is undefined behavior, do not allow + */ + if( ((dest > src) && (dest < (src+smax))) || + ((src > dest) && (src < (dest+dmax))) ) { + mem_prim_set32(dest, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy32_s: overlap undefined", + NULL, ESOVRLP); + return (RCNEGATE(ESOVRLP)); + } + + /* + * now perform the copy + */ + mem_prim_move32(dest, src, smax); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memcpy32_s); */ diff --git a/safe_string/memcpy_s.c b/safe_string/memcpy_s.c new file mode 100644 index 000000000000..60d748c704c5 --- /dev/null +++ b/safe_string/memcpy_s.c @@ -0,0 +1,157 @@ +/*------------------------------------------------------------------ + * memcpy_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memcpy_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memcpy_s(void *dest, rsize_t dmax, const void *src, rsize_t smax) + * + * DESCRIPTION + * This function copies at most smax bytes from src to dest, up to + * dmax. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be replaced by src. + * + * dmax maximum length of the resulting dest + * + * src pointer to the memory that will be copied to dest + * + * smax maximum number bytes of src to copy + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * Copying shall not take place between regions that overlap. + * If there is a runtime-constraint violation, the memcpy_s function + * stores zeros in the first dmax bytes of the region pointed to + * by dest if dest is not a null pointer and smax is valid. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP source memory overlaps destination + * + * ALSO SEE + * memcpy16_s(), memcpy32_s(), memmove_s(), memmove16_s(), + * memmove32_s() + * + */ +errno_t +memcpy_s (void *dest, rsize_t dmax, const void *src, rsize_t smax) +{ + uint8_t *dp; + const uint8_t *sp; + + dp = dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memcpy_s: dest is NULL", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memcpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("memcpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (smax == 0) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy_s: smax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (smax > dmax) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy_s: smax exceeds dmax", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (sp == NULL) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy_s: src is NULL", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + + /* + * overlap is undefined behavior, do not allow + */ + if( ((dp > sp) && (dp < (sp+smax))) || + ((sp > dp) && (sp < (dp+dmax))) ) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memcpy_s: overlap undefined", + NULL, ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + /* + * now perform the copy + */ + mem_prim_move(dp, sp, smax); + + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(memcpy_s); */ diff --git a/safe_string/memmove16_s.c b/safe_string/memmove16_s.c new file mode 100644 index 000000000000..dac328247daf --- /dev/null +++ b/safe_string/memmove16_s.c @@ -0,0 +1,151 @@ +/*------------------------------------------------------------------ + * memmove16_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memmove16_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memmove16_s(uint16_t *dest, rsize_t dmax, + * const uint16_t *src, rsize_t smax) + * + * DESCRIPTION + * The memmove16_s function copies smax uint16_t from the region + * pointed to by src into the region pointed to by dest. This + * copying takes place as if the smax uint16_t from the region + * pointed to by src are first copied into a temporary array of + * smax uint16_t that does not overlap the regions pointed to + * by dest or src, and then the smax uint16_t from the temporary + * array are copied into the region pointed to by dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to the memory that will be replaced by src. + * + * dmax maximum length of the resulting dest, in uint16_t + * + * src pointer to the memory that will be copied + * to dest + * + * smax maximum number uint16_t of src that can be copied + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * If there is a runtime-constraint violation, the memmove_s function + * stores zeros in the first dmax characters of the regionpointed to + * by dest if dest is not a null pointer and dmax is not greater + * than RSIZE_MAX_MEM. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memmove_s(), memmove32_s(), memcpy_s(), memcpy16_s() memcpy32_s() + * + */ +errno_t +memmove16_s (uint16_t *dest, rsize_t dmax, const uint16_t *src, rsize_t smax) +{ + uint16_t *dp; + const uint16_t *sp; + + dp= dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memove16_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memove16_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM16) { + invoke_safe_mem_constraint_handler("memove16_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set16(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove16_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set16(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove16_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (sp == NULL) { + mem_prim_set16(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove16_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + + /* + * now perform the copy + */ + mem_prim_move16(dp, sp, smax); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memmove16_s); */ diff --git a/safe_string/memmove32_s.c b/safe_string/memmove32_s.c new file mode 100644 index 000000000000..372ed4651c18 --- /dev/null +++ b/safe_string/memmove32_s.c @@ -0,0 +1,150 @@ +/*------------------------------------------------------------------ + * memmove32_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memmove32_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memmove32_s(uint32_t *dest, rsize_t dmax, + * const uint32_t *src, rsize_t smax) + * + * DESCRIPTION + * The memmove32_s function copies smax uint32_ts from the region + * pointed to by src into the region pointed to by dest. This + * copying takes place as if the smax uint32_ts from the region + * pointed to by src are first copied into a temporary array of + * smax uint32_ts that does not overlap the regions pointed to + * by dest or src, and then the smax uint32_ts from the temporary + * array are copied into the region pointed to by dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to the memory that will be replaced by src. + * + * dmax maximum length of the resulting dest, in uint32_t + * + * src pointer to the memory that will be copied + * to dest + * + * smax maximum number uint32_t of src that can be copied + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * If there is a runtime-constraint violation, the memmove_s function + * stores zeros in the first dmax characters of the regionpointed to + * by dest if dest is not a null pointer and dmax is not greater + * than RSIZE_MAX_MEM. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memmove_s(), memmove16_s(), memcpy_s(), memcpy16_s() memcpy32_s() + * + */ +errno_t +memmove32_s (uint32_t *dest, rsize_t dmax, const uint32_t *src, rsize_t smax) +{ + uint32_t *dp; + const uint32_t *sp; + + dp= dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memove32_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memove32_s: dest is zero", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("memove32_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set32(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove32_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set32(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove32_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (sp == NULL) { + mem_prim_set32(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memove32_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + /* + * now perform the copy + */ + mem_prim_move32(dp, sp, smax); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memmove32_s); */ diff --git a/safe_string/memmove_s.c b/safe_string/memmove_s.c new file mode 100644 index 000000000000..1ecfed3a04b7 --- /dev/null +++ b/safe_string/memmove_s.c @@ -0,0 +1,149 @@ +/*------------------------------------------------------------------ + * memmove_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memmove_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memmove_s(void *dest, rsize_t dmax, + * const void *src, rsize_t smax) + * + * DESCRIPTION + * The memmove_s function copies smax bytes from the region pointed + * to by src into the region pointed to by dest. This copying takes place + * as if the smax bytes from the region pointed to by src are first copied + * into a temporary array of smax bytes that does not overlap the region + * pointed to by dest or src, and then the smax bytes from the temporary + * array are copied into the object region to by dest. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to the memory that will be replaced by src. + * + * dmax maximum length of the resulting dest, in bytes + * + * src pointer to the memory that will be copied + * to dest + * + * smax maximum number bytes of src that can be copied + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * If there is a runtime-constraint violation, the memmove_s function + * stores zeros in the first dmax characters of the regionpointed to + * by dest if dest is not a null pointer and dmax is not greater + * than RSIZE_MAX_MEM. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memmove16_s(), memmove32_s(), memcpy_s(), memcpy16_s() memcpy32_s() + * + */ +errno_t +memmove_s (void *dest, rsize_t dmax, const void *src, rsize_t smax) +{ + uint8_t *dp; + const uint8_t *sp; + + dp= dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("memmove_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("memmove_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("memmove_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memmove_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memmove_s: smax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (sp == NULL) { + mem_prim_set(dp, dmax, 0); + invoke_safe_mem_constraint_handler("memmove_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + /* + * now perform the copy + */ + mem_prim_move(dp, sp, smax); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memmove_s); */ diff --git a/safe_string/memset16_s.c b/safe_string/memset16_s.c new file mode 100644 index 000000000000..767249ba70c8 --- /dev/null +++ b/safe_string/memset16_s.c @@ -0,0 +1,105 @@ +/*------------------------------------------------------------------ + * memset16_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memset16_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memset16_s(uint16_t *dest, rsize_t len, uint16_t value) + * + * DESCRIPTION + * Sets len uint16_t starting at dest to the specified value. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be set to the value + * + * len number of uint16_t to be set + * + * value uint16_t value to be written + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM16. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memset_s(), memset32_s() + * + */ +errno_t +memset16_s (uint16_t *dest, rsize_t len, uint16_t value) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memset16_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memset16_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM16) { + invoke_safe_mem_constraint_handler("memset16_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + mem_prim_set16(dest, len, value); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memset16_s); */ diff --git a/safe_string/memset32_s.c b/safe_string/memset32_s.c new file mode 100644 index 000000000000..10acb63bf5f6 --- /dev/null +++ b/safe_string/memset32_s.c @@ -0,0 +1,105 @@ +/*------------------------------------------------------------------ + * memset32_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memset32_s - Sets a block of memory to value + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memset32_s(uint32_t *dest, rsize_t len, uint32_t value) + * + * DESCRIPTION + * Sets len uint32_t starting at dest to the specified value. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be set to the value + * + * len number of uint32_t to be set + * + * value uint32_t value to be written + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM32. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memset_s(), memset16_s() + * + */ +errno_t +memset32_s (uint32_t *dest, rsize_t len, uint32_t value) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memset32_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memset32_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("memset32_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + mem_prim_set32(dest, len, value); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memset32_s); */ diff --git a/safe_string/memset_s.c b/safe_string/memset_s.c new file mode 100644 index 000000000000..749498f7cff3 --- /dev/null +++ b/safe_string/memset_s.c @@ -0,0 +1,105 @@ +/*------------------------------------------------------------------ + * memset_s + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memset_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memset_s(void *dest, rsize_t len, uint8_t value) + * + * DESCRIPTION + * Sets len bytes starting at dest to the specified value. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be set to the value + * + * len number of bytes to be set + * + * value byte value + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memset16_s(), memset32_s() + * + */ +errno_t +memset_s (void *dest, rsize_t len, uint8_t value) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memset_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memset_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("memset_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + mem_prim_set(dest, len, value); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memset_s); */ diff --git a/safe_string/memzero16_s.c b/safe_string/memzero16_s.c new file mode 100644 index 000000000000..5fdff4a65bea --- /dev/null +++ b/safe_string/memzero16_s.c @@ -0,0 +1,107 @@ +/*------------------------------------------------------------------ + * memzero16_s - zeros memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memzero16_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memzero16_s(uint16_t *dest, rsize_t len) + * + * DESCRIPTION + * Zeros len uint16_ts starting at dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to be zeroed. + * + * len number of uint16_ts to be zeroed + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM16. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memzero_s(), memzero32_s() + * + */ +errno_t +memzero16_s (uint16_t *dest, rsize_t len) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memzero16_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memzero16_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM16) { + invoke_safe_mem_constraint_handler("memzero16_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * mem_prim_set16(dest, len, 0xDEAD); + * mem_prim_set16(dest, len, 0xBEEF); + */ + mem_prim_set16(dest, len, 0); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memzero16_s); */ diff --git a/safe_string/memzero32_s.c b/safe_string/memzero32_s.c new file mode 100644 index 000000000000..ed6d94ae5e23 --- /dev/null +++ b/safe_string/memzero32_s.c @@ -0,0 +1,108 @@ +/*------------------------------------------------------------------ + * memzero32_s - zeros memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memzero32_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memzero32_s(uint32_t *dest, rsize_t len) + * + * DESCRIPTION + * Zeros len uint32_ts starting at dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to be zeroed. + * + * len number of uint32_ts to be zeroed + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM32. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memzero_s(), memzero16_s() + * + */ +errno_t +memzero32_s (uint32_t *dest, rsize_t len) +{ + + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memzero32_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memzero32_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("memzero32_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * mem_prim_set32(dest, len, 0xDEADBEEF); + * mem_prim_set32(dest, len, 0xBA5EBA11); + */ + mem_prim_set32(dest, len, 0); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memzero32_s); */ diff --git a/safe_string/memzero_s.c b/safe_string/memzero_s.c new file mode 100644 index 000000000000..456b43b4b7f9 --- /dev/null +++ b/safe_string/memzero_s.c @@ -0,0 +1,107 @@ +/*------------------------------------------------------------------ + * memzero_s - zeros memory + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * memzero_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * memzero_s(void *dest, rsize_t len) + * + * DESCRIPTION + * Zeros len bytes starting at dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to be zeroed. + * + * len number of bytes to be zeroed + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM. + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memzero16_s(), memzero32_s() + * + */ +errno_t +memzero_s (void *dest, rsize_t len) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("memzero_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("memzero_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("memzero_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * mem_prim_set(dest, len, 0xA5); + * mem_prim_set(dest, len, 0x5A); + */ + mem_prim_set(dest, len, 0); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(memzero_s); */ diff --git a/safe_string/safe_mem_constraint.c b/safe_string/safe_mem_constraint.c new file mode 100644 index 000000000000..2e21835e70db --- /dev/null +++ b/safe_string/safe_mem_constraint.c @@ -0,0 +1,143 @@ +/*------------------------------------------------------------------ + * safe_mem_constraint.c + * + * October 2008, Bo Berry + * 2012, Jonathan Toppins + * + * Copyright (c) 2008-2012 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +/* #include "safe_mem_lib.h" */ + + +static constraint_handler_t mem_handler = NULL; + + +/** + * NAME + * set_mem_constraint_handler_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * constraint_handler_t + * set_mem_constraint_handler_straint_handler_t handler) + * + * DESCRIPTION + * The set_mem_constraint_handler_s function sets the runtime-constraint + * handler to be handler. The runtime-constraint handler is the function to + * be called when a library function detects a runtime-constraint + * order: + * 1. A pointer to a character string describing the + * runtime-constraint violation. + * 2. A null pointer or a pointer to an implementation defined + * object. + * 3. If the function calling the handler has a return type declared + * as errno_t, the return value of the function is passed. + * Otherwise, a positive value of type errno_t is passed. + * The implementation has a default constraint handler that is used if no + * calls to the set_constraint_handler_s function have been made. The + * behavior of the default handler is implementation-defined, and it may + * cause the program to exit or abort. If the handler argument to + * set_constraint_handler_s is a null pointer, the implementation default + * handler becomes the current constraint handler. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * *msg Pointer to the message describing the error + * + * *ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * OUTPUT PARAMETERS + * none + * + * RETURN VALUE + * none + * + * ALSO SEE + * set_str_constraint_handler_s() + */ +constraint_handler_t +/* set_mem_constraint_handler_s (constraint_handler_t handler) */ +opae_set_mem_constraint_handler_s(constraint_handler_t handler) +{ + constraint_handler_t prev_handler = mem_handler; + if (NULL == handler) { + mem_handler = sl_default_handler; + } else { + mem_handler = handler; + } + return prev_handler; +} +/* EXPORT_SYMBOL(set_mem_constraint_handler_s); */ + + +/** + * NAME + * invoke_safe_mem_constraint_handler + * + * SYNOPSIS + * #include "safe_mem_constraint.h" + * void + * invoke_safe_mem_constraint_handler(const char *msg, + * void *ptr, + * errno_t error) + * + * DESCRIPTION + * Invokes the currently set constraint handler or the default. + * + * INPUT PARAMETERS + * *msg Pointer to the message describing the error + * + * *ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * OUTPUT PARAMETERS + * none + * + * RETURN VALUE + * none + * + */ +void +invoke_safe_mem_constraint_handler (const char *msg, + void *ptr, + errno_t error) +{ + if (NULL != mem_handler) { + mem_handler(msg, ptr, error); + } else { + sl_default_handler(msg, ptr, error); + } +} diff --git a/safe_string/safe_mem_constraint.h b/safe_string/safe_mem_constraint.h new file mode 100644 index 000000000000..7ec898e1fb50 --- /dev/null +++ b/safe_string/safe_mem_constraint.h @@ -0,0 +1,46 @@ +/*------------------------------------------------------------------ + * safe_mem_constraint.h + * + * October 2008, Bo Berry + * + * Copyright (c) 2008, 2009 by Cisco Systems, Inc. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_MEM_CONSTRAINT_H__ +#define __SAFE_MEM_CONSTRAINT_H__ + +#include "safeclib_private.h" + +/* + * Function used by the libraries to invoke the registered + * runtime-constraint handler. Always needed. + */ +extern void invoke_safe_mem_constraint_handler( + const char *msg, + void *ptr, + errno_t error); + +#endif /* __SAFE_MEM_CONSTRAINT_H__ */ diff --git a/safe_string/safe_str_constraint.c b/safe_string/safe_str_constraint.c new file mode 100644 index 000000000000..638df2878778 --- /dev/null +++ b/safe_string/safe_str_constraint.c @@ -0,0 +1,147 @@ +/*------------------------------------------------------------------ + * safe_str_constraint.c + * + * October 2008, Bo Berry + * 2012, Jonathan Toppins + * + * Copyright (c) 2008, 2009, 2012 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +static constraint_handler_t str_handler = NULL; + + +/** + * NAME + * set_str_constraint_handler_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * constraint_handler_t + * set_str_constraint_handler_s(constraint_handler_t handler) + * + * DESCRIPTION + * The set_str_constraint_handler_s function sets the runtime-constraint + * handler to be handler. The runtime-constraint handler is the function to + * be called when a library function detects a runtime-constraint + * violation. Only the most recent handler registered with + * set_str_constraint_handler_s is called when a runtime-constraint + * violation occurs. + * When the handler is called, it is passed the following arguments in + * the following order: + * 1. A pointer to a character string describing the + * runtime-constraint violation. + * 2. A null pointer or a pointer to an implementation defined + * object. + * 3. If the function calling the handler has a return type declared + * as errno_t, the return value of the function is passed. + * Otherwise, a positive value of type errno_t is passed. + * The implementation has a default constraint handler that is used if no + * calls to the set_constraint_handler_s function have been made. The + * behavior of the default handler is implementation-defined, and it may + * cause the program to exit or abort. If the handler argument to + * set_constraint_handler_s is a null pointer, the implementation default + * handler becomes the current constraint handler. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * *msg Pointer to the message describing the error + * + * *ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * OUTPUT PARAMETERS + * none + * + * RETURN VALUE + * none + * + * ALSO SEE + * set_str_constraint_handler_s() + */ +constraint_handler_t +/* set_str_constraint_handler_s (constraint_handler_t handler) */ +opae_set_str_constraint_handler_s (constraint_handler_t handler) +{ + constraint_handler_t prev_handler = str_handler; + if (NULL == handler) { + str_handler = sl_default_handler; + } else { + str_handler = handler; + } + return prev_handler; +} +/* EXPORT_SYMBOL(set_str_constraint_handler_s); */ + + +/** + * NAME + * invoke_safe_str_constraint_handler + * + * SYNOPSIS + * #include "safe_str_constraint.h" + * void + * invoke_safe_str_constraint_handler (const char *msg, + * void *ptr, + * errno_t error) + * + * DESCRIPTION + * Invokes the currently set constraint handler or the default. + * + * INPUT PARAMETERS + * *msg Pointer to the message describing the error + * + * *ptr Pointer to aassociated data. Can be NULL. + * + * error The error code encountered. + * + * OUTPUT PARAMETERS + * none + * + * RETURN VALUE + * none + * + */ +void +invoke_safe_str_constraint_handler (const char *msg, + void *ptr, + errno_t error) +{ + if (NULL != str_handler) { + str_handler(msg, ptr, error); + } else { + sl_default_handler(msg, ptr, error); + } +} diff --git a/safe_string/safe_str_constraint.h b/safe_string/safe_str_constraint.h new file mode 100644 index 000000000000..a1fba3e7e85c --- /dev/null +++ b/safe_string/safe_str_constraint.h @@ -0,0 +1,78 @@ +/*------------------------------------------------------------------ + * safe_str_constraint.h + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 Cisco Systems + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFE_STR_CONSTRAINT_H__ +#define __SAFE_STR_CONSTRAINT_H__ + +#include "safeclib_private.h" + +/* + * Function used by the libraries to invoke the registered + * runtime-constraint handler. Always needed. + */ +extern void invoke_safe_str_constraint_handler( + const char *msg, + void *ptr, + errno_t error); + + +/* + * Safe C Lib internal string routine to consolidate error handling + */ +static inline void handle_error(char *orig_dest, rsize_t orig_dmax, + char *err_msg, errno_t err_code) +{ +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to eliminate partial copy */ + while (orig_dmax) { *orig_dest = '\0'; orig_dmax--; orig_dest++; } +#else + *orig_dest = '\0'; +#endif + + invoke_safe_str_constraint_handler(err_msg, NULL, err_code); + return; +} + +static inline void handle_wc_error(wchar_t *orig_dest, rsize_t orig_dmax, + char *err_msg, errno_t err_code) +{ +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to eliminate partial copy */ + while (orig_dmax) { *orig_dest = L'\0'; orig_dmax--; orig_dest++; } +#else + *orig_dest = L'\0'; +#endif + + invoke_safe_str_constraint_handler(err_msg, NULL, err_code); + return; +} + +#endif /* __SAFE_STR_CONSTRAINT_H__ */ diff --git a/safe_string/safeclib_private.h b/safe_string/safeclib_private.h new file mode 100644 index 000000000000..fa211844563a --- /dev/null +++ b/safe_string/safeclib_private.h @@ -0,0 +1,98 @@ +/*------------------------------------------------------------------ + * safeclib_private.h - Internal library references + * + * 2012, Jonathan Toppins + * + * Copyright (c) 2012, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#ifndef __SAFECLIB_PRIVATE_H__ +#define __SAFECLIB_PRIVATE_H__ + +#ifdef __KERNEL__ +/* linux kernel environment */ + +#include +#include +#include + +#define RCNEGATE(x) ( -(x) ) + +#define slprintf(...) printk(KERN_EMERG __VA_ARGS__) +#define slabort() +#ifdef DEBUG +#define sldebug_printf(...) printk(KERN_DEBUG __VA_ARGS__) +#endif + +#else /* !__KERNEL__ */ + +#if HAVE_CONFIG_H +#include "config.h" +#endif + +#include +/* #ifdef STDC_HEADERS */ +# include +# include +# include +/* #else +# ifdef HAVE_STDLIB_H +# include +# endif +#endif +#ifdef HAVE_STRING_H +# if !defined STDC_HEADERS && defined HAVE_MEMORY_H +# include +# endif +*/ +# include +/* #endif */ +/* #ifdef HAVE_LIMITS_H */ +# include +/* #endif */ + +#define EXPORT_SYMBOL(sym) +#define RCNEGATE(x) (x) + +#define slprintf(...) fprintf(stderr, __VA_ARGS__) +#define slabort() abort() +#ifdef DEBUG +#define sldebug_printf(...) printf(__VA_ARGS__) +#endif + +#endif /* __KERNEL__ */ + +#ifndef sldebug_printf +#define sldebug_printf(...) +#endif + +/* #include "safe_lib.h" */ + +#endif /* __SAFECLIB_PRIVATE_H__ */ + + +#include + diff --git a/safe_string/snprintf_support.c b/safe_string/snprintf_support.c new file mode 100644 index 000000000000..309158ff3acd --- /dev/null +++ b/safe_string/snprintf_support.c @@ -0,0 +1,364 @@ +/*------------------------------------------------------------------ + * snprintf_support.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ +/* #include "snprintf_s.h" */ + +#define FMT_CHAR 'c' +#define FMT_WCHAR 'C' +#define FMT_SHORT 'h' +#define FMT_INT 'd' +#define FMT_LONG 'l' +#define FMT_STRING 's' +#define FMT_WSTRING 'S' +#define FMT_DOUBLE 'g' +#define FMT_LDOUBLE 'G' +#define FMT_VOID 'p' +#define FMT_PCHAR '1' +#define FMT_PSHORT '2' +#define FMT_PINT '3' +#define FMT_PLONG '4' + + + +#define MAX_FORMAT_ELEMENTS 16 + +#define CHK_FORMAT(X,Y) (((X)==(Y))?1:0) + + +unsigned int +parse_format(const char *format, char pformatList[], unsigned int maxFormats) +{ + unsigned int numFormats = 0; + unsigned int index = 0; + unsigned int start = 0; + char lmod = 0; + + while (index < RSIZE_MAX_STR && format[index] != '\0' && numFormats < maxFormats) + { + if (format[index] == '%') { + start = index; // remember where the format string started + // Check for flags + switch( format[++index]) { + case '\0': continue; // skip - end of format string + case '%' : continue; // skip - actually a percent character + case '#' : // convert to alternate form + case '0' : // zero pad + case '-' : // left adjust + case ' ' : // pad with spaces + case '+' : // force a sign be used + index++; // skip the flag character + break; + } + // check for and skip the optional field width + while ( format[index] != '\0' && format[index] >= '0' && format[index] <= '9') { + index++; + } + // Check for an skip the optional precision + if ( format[index] != '\0' && format[index] == '.') { + index++; // skip the period + while ( format[index] != '\0' && format[index] >= '0' && format[index] <= '9') { + index++; + } + } + // Check for and skip the optional length modifiers + lmod = ' '; + switch( format[index]) { + case 'h' : if ( format[++index] == 'h') { + ++index; //also recognize the 'hh' modifier + lmod = 'H'; // for char + } else { + lmod = 'h'; // for short + } + break; + case 'l' : if ( format[++index] == 'l') { + ++index; //also recognize the 'll' modifier + lmod = 'd'; // for long long + } else { + lmod = 'l'; // for long + } + break; + case 'L' : lmod = 'L'; break; + case 'j' : + case 'z' : + case 't' : index++; + break; + } + + // Recognize and record the actual modifier + switch( format[index]) { + case 'c' : + if ( lmod == 'l') { + pformatList[numFormats] = FMT_WCHAR; // store the format character + } else { + pformatList[numFormats] = FMT_CHAR; + } + numFormats++; + index++; // skip the format character + break; + + case 'd' : case 'i' : // signed + case 'o' : case 'u' : // unsigned + case 'x' : case 'X' : // unsigned + if ( lmod == 'H') { + pformatList[numFormats] = FMT_CHAR; // store the format character + } else if ( lmod == 'l') { + pformatList[numFormats] = FMT_LONG; // store the format character + } else if ( lmod == 'h') { + pformatList[numFormats] = FMT_SHORT; // store the format character + } else{ + pformatList[numFormats] = FMT_INT; + } + numFormats++; + index++; // skip the format character + break; + + case 'e' : case 'E' : + case 'f' : case 'F' : + case 'g' : case 'G' : + case 'a' : case 'A' : + if ( lmod == 'L') { + pformatList[numFormats] = FMT_LDOUBLE; // store the format character + } else{ + pformatList[numFormats] = FMT_DOUBLE; + } + numFormats++; + index++; // skip the format character + break; + + case 's' : + if ( lmod == 'l' || lmod == 'L') { + pformatList[numFormats] = FMT_WSTRING; // store the format character + } else { + pformatList[numFormats] = FMT_STRING; + } + numFormats++; + index++; // skip the format character + break; + + case 'p' : + pformatList[numFormats] = FMT_VOID; + numFormats++; + index++; // skip the format character + break; + + case 'n' : + if ( lmod == 'H') { + pformatList[numFormats] = FMT_PCHAR; // store the format character + } else if ( lmod == 'l') { + pformatList[numFormats] = FMT_PLONG; // store the format character + } else if ( lmod == 'h') { + pformatList[numFormats] = FMT_PSHORT; // store the format character + } else{ + pformatList[numFormats] = FMT_PINT; + } + numFormats++; + index++; // skip the format character + break; + case 'm' : + // Does not represent an argument in the call stack + index++; // skip the format character + continue; + default: + printf("failed to recognize format string ["); + for (;start RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("stpcpy_s: dmax exceeds max", + NULL, ESLEMAX); + *err = RCNEGATE(ESLEMAX); + return NULL; + } + + if (src == NULL) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + invoke_safe_str_constraint_handler("stpcpy_s: src is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + return NULL; + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest == src) { + /* look for the terminating null character, or return err if not found in dmax bytes */ + while (dmax > 0) { + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + *err = RCNEGATE(EOK); + return dest; + } + + dmax--; + dest++; + } + /* null terminator not found in src before end of dmax */ + handle_error(orig_dest, orig_dmax, "stpcpy_s: not enough space for src", + ESNOSPC); + *err = RCNEGATE(ESNOSPC); + return NULL; + } + + + if (dest < src) { + overlap_bumper = src; + + /* Check that the dest buffer does not overlap src buffer */ + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "stpcpy_s: " + "overlapping objects", + ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + *err = RCNEGATE(EOK); + return dest; + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + /* check that the src buffer does not run into the dest buffer - inifinite loop */ + if (src == overlap_bumper) { + /* NOTE (dmw) this condition guarantees that SRC has already been damaged! */ + handle_error(orig_dest, orig_dmax, "stpcpy_s: overlapping objects", + ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + *err = RCNEGATE(EOK); + return dest; + } + + dmax--; + dest++; + src++; + } + } + + /* + * Ran out of space in dest, and did not find the null terminator in src + */ + handle_error(orig_dest, orig_dmax, "stpcpy_s: not " + "enough space for src", + ESNOSPC); + *err = RCNEGATE(ESNOSPC); + return NULL; +} +/* EXPORT_SYMBOL(stpcpy_s); */ diff --git a/safe_string/stpncpy_s.c b/safe_string/stpncpy_s.c new file mode 100644 index 000000000000..560bb9661686 --- /dev/null +++ b/safe_string/stpncpy_s.c @@ -0,0 +1,282 @@ +/*------------------------------------------------------------------ + * stpncpy_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * stpncpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * char * + * stpncpy_s(char *dest, rsize_t dmax, const char *src, rsize_t smax, errno_t *err); + * + * DESCRIPTION + * The stpncpy_s function copies at most smax characters from the string + * pointed to by src, including the terminating null byte ('\0'), to the + * array pointed to by dest. Exactly smax characters are written at dest. + * If the length strlen_s(src) is smaller than smax, the remaining smax + * characters in the array pointed to by dest are filled with null bytes. + * If the length strlen_s(src) is greater than or equal to smax, the string + * pointed to by dest will contain smax characters from src plus a null + * characters (dest will be null-terminated). + * + * Therefore, dmax must be at least smax+1 in order to contain the terminator. + * + * The function returns a pointer to the end of the string in dest - + * that is to the null terminator of dest. If an error occurs, + * NULL is returned and err is set to the error encountered. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * + * dmax restricted maximum length of dest (must be at least smax+1) + * + * src pointer to the string that will be copied + * to dest + * + * smax the maximum number of characters from src to copy into dest + * + * err the error code upon error, or EOK if successful + * + * OUTPUT PARAMETERS + * dest updated + * err updated as follows: + * EOK successful operation, the characters in src were + * copied into dest and the result is null terminated, + * and dest is returned to point to the first null at end of dest. + * On error, NULL is returned and err is set to one of hte following: + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not be greater than RSIZE_MAX_STR. + * dmax shall not equal zero. + * dmax must be at least smax+1 to allow filling dest with smax characters plus NULL. + * If src and dest overlap, copying shall be stopped; destruction of src may have occurred. + * If there is a runtime-constraint violation, then: + * if dest is not a null pointer and dmax is greater than zero and + * not greater than RSIZE_MAX_STR, then stpncpy_s shall fill dest with nulls, + * if library was compiled with SAFECLIB_STR_NULL_SLACK. + * + * RETURN VALUE + * a char pointer to the terminating null at the end of dest + * or NULL pointer on error + * + * ALSO SEE + * stpcpy_s(), strcpy_s(), strcat_s(), strncat_s(), strncpy_s() + * + */ +char * +stpncpy_s(char *dest, rsize_t dmax, const char *src, rsize_t smax, errno_t *err) +{ + rsize_t orig_dmax; + char *orig_dest; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("stpncpy_s: dest is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + return NULL; + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("stpncpy_s: src is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + dest[0] = '\0'; + return NULL; + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("stpncpy_s: dmax is 0", + NULL, ESZEROL); + *err = RCNEGATE(ESZEROL); + return NULL; + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("stpncpy_s: dmax exceeds max", + NULL, ESLEMAX); + *err = RCNEGATE(ESLEMAX); + return NULL; + } + + if (smax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("stpncpy_s: smax exceeds max", + NULL, ESLEMAX); + *err = RCNEGATE(ESLEMAX); + return NULL; + } + + if (dmax < (smax+1)) { + invoke_safe_str_constraint_handler("stpncpy_s: dmax too short for smax", + NULL, ESNOSPC); + *err = RCNEGATE(ESNOSPC); + dest[0] = '\0'; + return NULL; + } + + /* dmwheel1: Add check to prevent destruction of overlap into destination */ + if ((src < dest) && ((src+smax) >= dest)) { + invoke_safe_str_constraint_handler("stpncpy_s: src+smax overlaps into dest", + NULL, ESOVRLP); + *err = RCNEGATE(ESOVRLP); + dest[0] = '\0'; + return NULL; + } + + /* dmwheel1: Add check to prevent destruction of overlap into source */ + if ((dest < src) && ((dest+smax) >= src)) { + invoke_safe_str_constraint_handler("stpncpy_s: dest+smax overlaps into src", + NULL, ESOVRLP); + *err = RCNEGATE(ESOVRLP); + dest[0] = '\0'; + return NULL; + } + +#ifdef SAFECLIB_STR_NULL_SLACK + /* dmwheel1: Add check to prevent destruction of overlap into destination */ + if ((src < dest) && ((src+dmax) >= dest)) { + invoke_safe_str_constraint_handler("stpncpy_s: src+dmax overlaps into dest", + NULL, ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } + + /* dmwheel1: Add check to prevent destruction of overlap into source */ + if ((dest < src) && ((dest+dmax) >= src)) { + invoke_safe_str_constraint_handler("stpncpy_s: dest+dmax overlaps into src", + NULL, ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } +#endif + + + if (src == NULL) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + invoke_safe_str_constraint_handler("stpncpy_s: src is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + return NULL; + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest == src) { + /* look for the terminating null character, or return err if not found in dmax bytes */ + while (dmax > 0) { + if (*dest == '\0') { + /* add nulls to complete smax */ + char *filler = dest; /* don't change dest, because we need to return it */ + while (smax) { *filler = '\0'; dmax--; smax--; filler++; } +#ifdef SAFECLIB_STR_NULL_SLACK + /* null dmax slack to clear any data */ + while (dmax) { *filler = '\0'; dmax--; filler++; } +#endif + *err = RCNEGATE(EOK); + return dest; + } + dmax--; + dest++; + if (--smax == 0) { + /* we have copied smax characters, add null terminator */ + *dest = '\0'; + } + } + /* null terminator not found in src before end of dmax */ + handle_error(orig_dest, orig_dmax, "stpncpy_s: not enough space for src", + ESNOSPC); + *err = RCNEGATE(ESNOSPC); + return NULL; + } + + + /* All checks for buffer overlaps were made, just do the copies */ + while (dmax > 0) { + + *dest = *src; /* Copy the data into the destination */ + + /* Check for maximum copy from source */ + if (smax == 0) { + /* we have copied smax characters, add null terminator */ + *dest = '\0'; + } + + /* Check for end of copying */ + if (*dest == '\0') { + /* add nulls to complete smax, if fewer than smax characters + * were in src when the NULL was encountered */ + char *filler = dest; /* don't change dest, because we need to return it */ + while (smax) { *filler = '\0'; dmax--; smax--; filler++; } +#ifdef SAFECLIB_STR_NULL_SLACK + /* null dmax slack to clear any data */ + while (dmax) { *filler = '\0'; dmax--; filler++; } +#endif + *err = RCNEGATE(EOK); + return dest; + } + dmax--; + smax--; + dest++; + src++; + + } + /* + * Ran out of space in dest, and did not find the null terminator in src + */ + handle_error(orig_dest, orig_dmax, "stpncpy_s: not enough space for src", + ESNOSPC); + *err = RCNEGATE(ESNOSPC); + return NULL; +} +/* EXPORT_SYMBOL(stpncpy_s); */ diff --git a/safe_string/strcasecmp_s.c b/safe_string/strcasecmp_s.c new file mode 100644 index 000000000000..720c1586cbf4 --- /dev/null +++ b/safe_string/strcasecmp_s.c @@ -0,0 +1,144 @@ +/*------------------------------------------------------------------ + * strcasecmp_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcasecmp_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcasecmp_s(const char *dest, rsize_t dmax, + * const char *src, int *indicator) + * + * DESCRIPTION + * Case insensitive string comparison by converting + * to uppercase prior to the compare. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * indicator pointer to result indicator, greater than 0, + * equal to 0 or less than 0, if the string pointed + * to by dest is greater than, equal to or less + * than the string pointed to by src respectively. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * indicator, when the return code is OK + * >0 dest greater than src + * 0 strings the same + * <0 dest less than src + * + * EOK comparison complete + * ESNULLP pointer was null + * ESZEROL length was zero + * ESLEMAX length exceeded max + * + * ALSO SEE + * strcmp_s() + * + */ +errno_t +strcasecmp_s (const char *dest, rsize_t dmax, + const char *src, int *indicator) +{ + const unsigned char *udest = (const unsigned char *) dest; + const unsigned char *usrc = (const unsigned char *) src; + + if (indicator == NULL) { + invoke_safe_str_constraint_handler("strcasecmp_s: indicator is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *indicator = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcasecmp_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcasecmp_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcasecmp_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcasecmp_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + while (*udest && *usrc && dmax) { + + if (toupper(*udest) != toupper(*usrc)) { + break; + } + + udest++; + usrc++; + dmax--; + } + + *indicator = (toupper(*udest) - toupper(*usrc)); + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(strcasecmp_s); */ diff --git a/safe_string/strcasestr_s.c b/safe_string/strcasestr_s.c new file mode 100644 index 000000000000..b47ec571ac79 --- /dev/null +++ b/safe_string/strcasestr_s.c @@ -0,0 +1,179 @@ +/*------------------------------------------------------------------ + * strcasestr_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcasestr_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcasestr_s(char *dest, rsize_t dmax, + * const char *src, rsize_t slen, char **substring) + * + * DESCRIPTION + * The strcasestr_s() function locates the first occurrence of + * the substring pointed to by src which would be located in + * the string pointed to by dest. The comparison is case + * insensitive. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to be searched for the substring + * + * dmax restricted maximum length of dest string + * + * src pointer to the sub string + * + * slen maximum length of src string + * + * substring returned pointer to the substring + * + * OUTPUT PARAMETERS + * substring pointer to the substring + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor slen shall equal zero. + * Neither dmax nor slen shall be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * EOK successful operation, substring found. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESNOTFND substring not found + * + * ALSO SEE + * strstr_s(), strprefix_s() + * + */ +errno_t +strcasestr_s (char *dest, rsize_t dmax, + const char *src, rsize_t slen, char **substring) +{ + rsize_t len; + rsize_t dlen; + int i; + + if (substring == NULL) { + invoke_safe_str_constraint_handler("strcasestr_s: substring is null", + NULL, ESNULLP); + return (ESNULLP); + } + *substring = NULL; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcasestr_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcasestr_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcasestr_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcasestr_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (slen == 0) { + invoke_safe_str_constraint_handler("strcasestr_s: slen is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcasestr_s: slen exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* + * src points to a string with zero length, or + * src equals dest, return dest + */ + if (*src == '\0' || dest == src) { + *substring = dest; + return (EOK); + } + + while (*dest && dmax) { + i = 0; + len = slen; + dlen = dmax; + + while (dest[i] && dlen) { + + /* not a match, not a substring */ + if (toupper(dest[i]) != toupper(src[i])) { + break; + } + + /* move to the next char */ + i++; + len--; + dlen--; + + if (src[i] == '\0' || !len) { + *substring = dest; + return (EOK); + } + } + dest++; + dmax--; + } + + /* + * substring was not found, return NULL + */ + *substring = NULL; + return (ESNOTFND); +} diff --git a/safe_string/strcat_s.c b/safe_string/strcat_s.c new file mode 100644 index 000000000000..9b40d31df33f --- /dev/null +++ b/safe_string/strcat_s.c @@ -0,0 +1,232 @@ +/*------------------------------------------------------------------ + * strcat_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcat_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcat_s(char *dest, rsize_t dmax, const char *src) + * + * DESCRIPTION + * The strcat_s function appends a copy of the string pointed + * to by src (including the terminating null character) to the + * end of the string pointed to by dest. The initial character + * from src overwrites the null character at the end ofdest. + * + * All elements following the terminating null character (if + * any) written by strcat_s in the array of dmax characters + * pointed to by dest take unspecified values when strcat_s + * returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be extended by src + * if dmax allows. The string is null terminated. + * If the resulting concatenated string is less + * than dmax, the remaining slack space is nulled. + * + * dmax restricted maximum length of the resulting dest, + * including the null + * + * src pointer to the string that will be concatenaed + * to string dest + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer + * dmax shall not equal zero + * dmax shall not be greater than RSIZE_MAX_STR + * dmax shall be greater than strnlen_s(src,m). + * Copying shall not takeplace between objects that overlap + * If there is a runtime-constraint violation, then if dest is + * not a null pointer and dmax is greater than zero and not + * greater than RSIZE_MAX_STR, then strcat_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, all the characters from src + * were appended to dest and the result in dest is + * null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max + * ESUNTERM dest not terminated + * + * ALSO SEE + * strncat_s(), strcpy_s(), strncpy_s() + * + */ +errno_t +strcat_s (char *dest, rsize_t dmax, const char *src) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcat_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcat_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcat_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcat_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + /* Find the end of dest */ + while (*dest != '\0') { + + if (dest == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strcat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + dest++; + dmax--; + if (dmax == 0) { + handle_error(orig_dest, orig_dmax, "strcat_s: " + "dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strcat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + /* Find the end of dest */ + while (*dest != '\0') { + + /* + * NOTE: no need to check for overlap here since src comes first + * in memory and we're not incrementing src here. + */ + dest++; + dmax--; + if (dmax == 0) { + handle_error(orig_dest, orig_dmax, "strcat_s: " + "dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strcat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + } + + /* + * the entire src was not copied, so null the string + */ + handle_error(orig_dest, orig_dmax, "strcat_s: not enough " + "space for src", + ESNOSPC); + + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(strcat_s); */ diff --git a/safe_string/strcmp_s.c b/safe_string/strcmp_s.c new file mode 100644 index 000000000000..3eb186f7577e --- /dev/null +++ b/safe_string/strcmp_s.c @@ -0,0 +1,140 @@ +/*------------------------------------------------------------------ + * strcmp_s.c -- string compare + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcmp_s + * + * Synpsos + * #include "safe_str_lib.h" + * errno_t + * strcmp_s(const char *dest, rsize_t dmax, + * const char *src, int *indicator) + * + * DESCRIPTION + * Compares string src to string dest. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * indicator pointer to result indicator, greater than, + * equal to or less than 0, if the string pointed + * to by dest is greater than, equal to or less + * than the string pointed to by src respectively. + * + * OUTPUT PARAMETERS + * indicator updated result indicator + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * indicator, when the return code is OK + * >0 dest greater than src + * 0 strings the same + * <0 dest less than src + * + * EOK + * ESNULLP pointer was null + * ESZEROL length was zero + * ESLEMAX length exceeded max + * + * ALSO SEE + * strcasecmp_s() + * + */ +errno_t +strcmp_s (const char *dest, rsize_t dmax, + const char *src, int *indicator) +{ + if (indicator == NULL) { + invoke_safe_str_constraint_handler("strcmp_s: indicator is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *indicator = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcmp_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcmp_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcmp_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcmp_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + while (*dest && *src && dmax) { + + if (*dest != *src) { + break; + } + + dest++; + src++; + dmax--; + } + + *indicator = *dest - *src; + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(strcmp_s); */ diff --git a/safe_string/strcmpfld_s.c b/safe_string/strcmpfld_s.c new file mode 100644 index 000000000000..70e2d3a0afdb --- /dev/null +++ b/safe_string/strcmpfld_s.c @@ -0,0 +1,142 @@ +/*------------------------------------------------------------------ + * strcmpfld_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcmpfld_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcmpfld_s(const char *dest, rsize_t dmax, + * const char *src, int *indicator) + * + * DESCRIPTION + * Compares the character array pointed to by src to the character array + * pointed to by dest for dmax characters. The null terminator does not + * stop the comparison. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to character array to compare against + * + * dmax restricted maximum length of dest. The length is + * used for the comparison of src against dest. + * + * src pointer to the character array to be compared to dest + * + * indicator pointer to result indicator, greater than, equal + * to or less than 0, if the character array pointed + * to by dest is greater than, equal to or less + * than the character array pointed to by src. + * OUTPUT + * indicator updated result indicator + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * indicator, when the return code is OK + * >0 dest greater than src + * 0 strings the same + * <0 dest less than src + * + * EOK + * ESNULLP pointer was null + * ESZEROL length was zero + * ESLEMAX length exceeded max + * + * ALSO SEE + * strcpyfld_s(), strcpyfldin_s(), strcpyfldout_s() + * + */ +errno_t +strcmpfld_s (const char *dest, rsize_t dmax, + const char *src, int *indicator) +{ + if (indicator == NULL) { + invoke_safe_str_constraint_handler("strcmpfld_s: indicator is null", + NULL, ESNULLP); + return (ESNULLP); + } + *indicator = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcmpfld_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcmpfld_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcmpfld_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcmpfld_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* compare for dmax charactrers, not the null! */ + while (dmax) { + + if (*dest != *src) { + break; + } + + dest++; + src++; + dmax--; + } + + *indicator = *dest - *src; + return (EOK); +} diff --git a/safe_string/strcpy_s.c b/safe_string/strcpy_s.c new file mode 100644 index 000000000000..151a25b535da --- /dev/null +++ b/safe_string/strcpy_s.c @@ -0,0 +1,198 @@ +/*------------------------------------------------------------------ + * strcpy_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcpy_s(char *dest, rsize_t dmax, const char *src) + * + * DESCRIPTION + * The strcpy_s function copies the string pointed to by src + * (including the terminating null character) into the array + * pointed to by dest. All elements following the terminating + * null character (if any) written by strcpy_s in the array + * of dmax characters pointed to by dest are nulled when + * strcpy_s returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the string that will be copied + * to dest + * + * OUTPUT PARAMETERS + * dest updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not be greater than RSIZE_MAX_STR. + * dmax shall not equal zero. + * dmax shall be greater than strnlen_s(src, dmax). + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and destmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpy_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, the characters in src were + * copied into dest and the result is null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * ALSO SEE + * strcat_s(), strncat_s(), strncpy_s() + * + */ +errno_t +strcpy_s (char *dest, rsize_t dmax, const char *src) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcpy_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (src == NULL) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + invoke_safe_str_constraint_handler("strcpy_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dest == src) { + return RCNEGATE(EOK); + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strcpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strcpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + } + + /* + * the entire src must have been copied, if not reset dest + * to null the string. + */ + handle_error(orig_dest, orig_dmax, "strcpy_s: not " + "enough space for src", + ESNOSPC); + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(strcpy_s); */ diff --git a/safe_string/strcpyfld_s.c b/safe_string/strcpyfld_s.c new file mode 100644 index 000000000000..ed790a82ec62 --- /dev/null +++ b/safe_string/strcpyfld_s.c @@ -0,0 +1,199 @@ +/*------------------------------------------------------------------ + * strcpyfld_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcpyfld_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcpyfld_s(char *dest, rsize_t dmax, const char *src, rsize_t slen) + * + * DESCRIPTION + * The strcpyfld_s function copies slen characters from the character + * array pointed to by src into the character array pointed to by dest. + * The copy operation does not stop on the null character as the + * function copies slen characters. + * + * EXTENSION TO + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to character array that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the character array that will be copied + * to dest + * + * slen maximum length of src + * + * OUTPUT PARAMETERS + * dest updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * slen shall not equal zero. + * slen shall not exceed dmax + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and destmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpyfld_s nulls dest. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * + * ALSO SEE + * strcpyfldin_s(), strcpyfldout_s() + * + */ +errno_t +strcpyfld_s (char *dest, rsize_t dmax, const char *src, rsize_t slen) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcpyfld_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcpyfld_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcpyfld_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + if (src == NULL) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfld_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (slen == 0) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfld_s: slen is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (slen > dmax) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfld_s: src exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (slen > 0) { + + if (dest == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfld_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + *dest++ = *src++; + slen--; + dmax--; + } + + } else { + overlap_bumper = dest; + + while (slen > 0) { + + if (src == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfld_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + *dest++ = *src++; + slen--; + dmax--; + } + } + + /* null slack space in the field */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + return (EOK); +} diff --git a/safe_string/strcpyfldin_s.c b/safe_string/strcpyfldin_s.c new file mode 100644 index 000000000000..0dbba067b471 --- /dev/null +++ b/safe_string/strcpyfldin_s.c @@ -0,0 +1,202 @@ +/*------------------------------------------------------------------ + * strcpyfldin_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcpyfldin_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcpyfldin_s(char *dest, rsize_t dmax, + * const char *src, rsize_t slen) + * + * DESCRIPTION + * The strcpyfldin_s function copies at most slen characters from the + * null terminated string pointed to by src into the fixed character + * array pointed to by dest. The copy operation stops on the null + * character if encountered and then continues to fill the field + * with nulls up to dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to character array that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the null terminated string that will be copied + * into the character array pointed to by dest + * + * slen length of source + * + * OUTPUT PARAMETERS + * dest updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * slen shall not equal zero. + * slen shall not exceed dmax + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and dmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpyfldin_s nulls dest. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * + * ALSO SEE + * strcpyfld_s(), strcpyfldout_s(), + * + */ +errno_t +strcpyfldin_s (char *dest, rsize_t dmax, const char *src, rsize_t slen) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcpyfldin_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcpyfldin_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcpyfldin_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + if (src == NULL) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldin_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (slen == 0) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldin_s: slen is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (slen > dmax) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldin_s: slen exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0 && *src) { + + if (dest == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfldin_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + dmax--; + *dest++ = *src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0 && *src) { + + if (src == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfldin_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + dmax--; + *dest++ = *src++; + } + } + + /* + * finish filling in the field with nulls if there is slack space + */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + return (EOK); +} diff --git a/safe_string/strcpyfldout_s.c b/safe_string/strcpyfldout_s.c new file mode 100644 index 000000000000..e2d0c95b7959 --- /dev/null +++ b/safe_string/strcpyfldout_s.c @@ -0,0 +1,204 @@ +/*------------------------------------------------------------------ + * strcpyfldout_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcpyfldout_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcpyfldout_s(char *dest, rsize_t dmax, + * const char *src, rsize_t slen) + * + * DESCRIPTION + * The strcpyfldout_s function copies slen characters from + * the character array pointed to by src into the string + * pointed to by dest. A null is included to properly + * termiante the dest string. The copy operation does not + * stop on the null character as function copies dmax + * characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the character array to be copied + * to dest and null terminated. + * + * slen the maximum number of characters that will be + * copied from the src field into the dest string. + * + * OUTPUT PARAMETERS + * dest updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * slen shall not equal zero. + * slen shall not exceed dmax + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and dmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpyfldout_s nulls dest. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * + * ALSO SEE + * strcpyfld_s(), strcpyfldin_s() + * + */ +errno_t +strcpyfldout_s (char *dest, rsize_t dmax, const char *src, rsize_t slen) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcpyfldout_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strcpyfldout_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcpyfldout_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + if (src == NULL) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldout_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (slen == 0) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldout_s: slen is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (slen > dmax) { + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler("strcpyfldout_s: slen exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 1 && slen) { + + if (dest == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfldout_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + dmax--; + slen--; + *dest++ = *src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 1 && slen) { + + if (src == overlap_bumper) { + dmax = orig_dmax; + dest = orig_dest; + + /* null string to eliminate partial copy */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + invoke_safe_str_constraint_handler( + "strcpyfldout_s: overlapping objects", + NULL, ESOVRLP); + return (ESOVRLP); + } + + dmax--; + slen--; + *dest++ = *src++; + } + } + + /* null slack space */ + while (dmax) { *dest = '\0'; dmax--; dest++; } + + return (EOK); +} diff --git a/safe_string/strcspn_s.c b/safe_string/strcspn_s.c new file mode 100644 index 000000000000..7924dcd3478f --- /dev/null +++ b/safe_string/strcspn_s.c @@ -0,0 +1,165 @@ +/*------------------------------------------------------------------ + * strcspn_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strcspn_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strcspn_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t slen, rsize_t *count) + * + * DESCRIPTION + * This function computes the prefix length of the string pointed + * to by dest which consists entirely of characters that are + * excluded from the string pointed to by src. The scanning stops + * at the first null in dest or after dmax characters. The + * exclusion string is checked to the null or after slen + * characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to determine the prefix + * + * dmax restricted maximum length of string dest + * + * src pointer to exclusion string + * + * slen restricted maximum length of string src + * + * count pointer to a count variable that will be updated + * with the dest substring length + * + * OUTPUT PARAMETERS + * count updated count variable + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * count shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * EOK count + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strspn_s(), strpbrk_s(), strstr_s() + * + */ +errno_t +strcspn_s (const char *dest, rsize_t dmax, + const char *src, rsize_t slen, rsize_t *count) +{ + const char *scan2; + rsize_t smax; + + if (count== NULL) { + invoke_safe_str_constraint_handler("strcspn_s: count is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *count = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strcspn_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strcspn_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strcspn_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcspn_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (slen == 0 ) { + invoke_safe_str_constraint_handler("strcspn_s: slen is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strcspn_s: slen exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + while (*dest && dmax) { + + /* + * Scanning for exclusions, so if there is a match, + * we're done! + */ + smax = slen; + scan2 = src; + while (*scan2 && smax) { + + if (*dest == *scan2) { + return RCNEGATE(EOK); + } + scan2++; + smax--; + } + + (*count)++; + dest++; + dmax--; + } + + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(strcspn_s); */ diff --git a/safe_string/strfirstchar_s.c b/safe_string/strfirstchar_s.c new file mode 100644 index 000000000000..a78473b154c1 --- /dev/null +++ b/safe_string/strfirstchar_s.c @@ -0,0 +1,127 @@ +/*------------------------------------------------------------------ + * strfirstchar_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strfirstchar_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strfirstchar_s(char *dest, rsize_t dmax, char c, char **first) + * + * DESCRIPTION + * This function returns a pointer to the first occurrence + * of character c in dest. The scanning stops at the first null + * or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string + * + * c character to locate + * + * first returned pointer to first occurrence of c + * + * OUTPUT PARAMETERS + * first updated pointer to first occurrence of c + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * first shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * pointer to first occurence of c, NULL if not found + * + * EOK pointer to first occurrence is returned + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strlastchar_s(), strfirstdiff_s(), strfirstsame_s(), + * strlastdiff_s(), strlastsame_s(), + * + */ +errno_t +strfirstchar_s (char *dest, rsize_t dmax, char c, char **first) +{ + + if (first == NULL) { + invoke_safe_str_constraint_handler("strfirstchar_s: index is null", + NULL, ESNULLP); + return (ESNULLP); + } + *first = NULL; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strfirstchar_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strfirstchar_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strfirstchar_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + while (*dest && dmax) { + + if (*dest == c) { + *first = dest; + return (EOK); + } + dest++; + dmax--; + } + + return (ESNOTFND); +} diff --git a/safe_string/strfirstdiff_s.c b/safe_string/strfirstdiff_s.c new file mode 100644 index 000000000000..fbcca49744c0 --- /dev/null +++ b/safe_string/strfirstdiff_s.c @@ -0,0 +1,142 @@ +/*------------------------------------------------------------------ + * strfirstdiff_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strfirstdiff_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strfirstdiff_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t *index) + * + * DESCRIPTION + * Returns the index of the first character that is different + * between dest and src. Index is valid only for OK. + * The scanning stops at the first null in dest or src, or + * after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * index pointer to returned index to first difference + * + * OUTPUT PARAMETERS + * index returned index to first difference + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * index to first difference, when the return code is OK + * + * EOK index to first diff is returned + * ESNODIFF no difference + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strfirstchar_s(), strfirstsame_s(), strlastchar_s(), + * strlastdiff_s(), strlastsame_s() + * + */ + errno_t + strfirstdiff_s (const char *dest, rsize_t dmax, + const char *src, rsize_t *index) +{ + const char *rp; + + if (index == NULL) { + invoke_safe_str_constraint_handler("strfirstdiff_s: index is null", + NULL, ESNULLP); + return (ESNULLP); + } + *index = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strfirstdiff_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strfirstdiff_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strfirstdiff_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strfirstdiff_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* hold reference point */ + rp = dest; + + while (*dest && *src && dmax) { + + if (*dest != *src) { + *index = dest - rp; + return (EOK); + } + dmax--; + dest++; + src++; + } + + return (ESNODIFF); +} diff --git a/safe_string/strfirstsame_s.c b/safe_string/strfirstsame_s.c new file mode 100644 index 000000000000..7a495d61790e --- /dev/null +++ b/safe_string/strfirstsame_s.c @@ -0,0 +1,145 @@ +/*------------------------------------------------------------------ + * strfirstsame_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strfirstsame_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strfirstsame_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t *index) + * + * DESCRIPTION + * Returns the index of the first character that is the + * same between dest and src. The scanning stops at the + * fisrt null in dest or src, or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * index pointer to returned index + * + * OUTPUT PARAMETERS + * index updated index + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * index to first same char, when the return code is OK + * + * EOK index to first same char is returned + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESNOTFND not found + * + * ALSO SEE + * strfirstchar_s(), strfirstdiff_s(), strlastchar_s(), + * strlastdiff_s(), strlastsame_s() + * + */ +errno_t +strfirstsame_s (const char *dest, rsize_t dmax, + const char *src, rsize_t *index) +{ + const char *rp = 0; + + if (index == NULL) { + invoke_safe_str_constraint_handler("strfirstsame_s: index is null", + NULL, ESNULLP); + return (ESNULLP); + } + *index = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strfirstsame_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strfirstsame_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strfirstsame_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strfirstsame_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* hold reference point */ + rp = dest; + + /* + * find the offset + */ + while (*dest && *src && dmax) { + + if (*dest == *src) { + *index = (uint32_t)(dest - rp); + return (EOK); + } + + dest++; + src++; + dmax--; + } + + return (ESNOTFND); +} diff --git a/safe_string/strisalphanumeric_s.c b/safe_string/strisalphanumeric_s.c new file mode 100644 index 000000000000..e479c871bc85 --- /dev/null +++ b/safe_string/strisalphanumeric_s.c @@ -0,0 +1,119 @@ +/*------------------------------------------------------------------ + * strisalphanumeric_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strisalphanumeric_s + * + * SYNOPSIS + * #include "safe_dest_lib.h" + * bool + * strisalphanumeric_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks if the entire string contains + * alphanumerics. The scanning stops at the first null + * or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * Runtime-condestaints + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true dest is alphanumeric + * false dest is not alphanumeric or an error occurred + * + * ALSO SEE + * strisascii_s(), strisdigit_s(), strishex_s(), strislowercase_s(), + * strismixedcase_s(), strisuppercase_s() + * + */ +bool +strisalphanumeric_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strisalphanumeric_s: " + "dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strisalphanumeric_s: " + "dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strisalphanumeric_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest && dmax) { + + if (( (*dest >= '0') && (*dest <= '9') ) || + ( (*dest >= 'a') && (*dest <= 'z') ) || + ( (*dest >= 'A') && (*dest <= 'Z') )) { + dest++; + dmax--; + } else { + return (false); + } + } + + return (true); +} diff --git a/safe_string/strisascii_s.c b/safe_string/strisascii_s.c new file mode 100644 index 000000000000..47d6eed3aa54 --- /dev/null +++ b/safe_string/strisascii_s.c @@ -0,0 +1,110 @@ +/*------------------------------------------------------------------ + * strisascii_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/* + *- + * NAME + * strisascii_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strisascii_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks if the entire string contains ascii + * characters. The scanning stops at the first null or + * at most dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true, string is ascii + * false, string contains one or more non-ascii or an error occurred + * + * ALSO SEE + * strisalphanumeric_s(), strisdigit_s(), strishex_s(), + * strislowercase_s(), strismixedcase_s(), strisuppercase_s() + *- + */ +bool +strisascii_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strisascii_s: dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strisascii_s: dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strisascii_s: dmax " + "exceeds max", + NULL, ESLEMAX); + return (false); + } + + while (*dest && dmax) { + if ((unsigned char)*dest > 127) { + return (false); + } + dest++; + dmax--; + } + + return (true); +} diff --git a/safe_string/strisdigit_s.c b/safe_string/strisdigit_s.c new file mode 100644 index 000000000000..eef928cff275 --- /dev/null +++ b/safe_string/strisdigit_s.c @@ -0,0 +1,112 @@ +/*------------------------------------------------------------------ + * strisdigit_s + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strisdigit_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strisdigit_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks that the entire string contains digits. + * The scanning stops at the first null or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true string is digit + * false string is not digit or an error occurred + * + * ALSO SEE + * strisalphanumeric_s(), strisascii_s(), strishex_s(), + * strislowercase_s(), strismixedcase_s(), strisuppercase_s() + * + */ +bool +strisdigit_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strisdigit_s: dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strisdigit_s: dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strisdigit_s: dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest) { + + if ((*dest < '0') || (*dest > '9')) { + return (false); + } + dest++; + dmax--; + } + + return (true); +} diff --git a/safe_string/strishex_s.c b/safe_string/strishex_s.c new file mode 100644 index 000000000000..6eb3894e13ca --- /dev/null +++ b/safe_string/strishex_s.c @@ -0,0 +1,118 @@ +/*------------------------------------------------------------------ + * strishex_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strishex_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strishex_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks that the entire string contains + * hex characters. The scanning stops at the first null + * or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true string is hex + * false string is not hex or an error occurred + * + * ALSO SEE + * strisalphanumeric_s(), strisascii_s(), strisdigit_s(), + * strislowercase_s(), strismixedcase_s(), + * strisuppercase_s() + * + */ +bool +strishex_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strishex_s: dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strishex_s: dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strishex_s: dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest && dmax) { + + if (((*dest >= '0') && (*dest <= '9')) || + ((*dest >= 'a') && (*dest <= 'f')) || + ((*dest >= 'A') && (*dest <= 'F'))) { + dest++; + dmax--; + + } else { + return (false); + } + } + + return (true); +} diff --git a/safe_string/strislowercase_s.c b/safe_string/strislowercase_s.c new file mode 100644 index 000000000000..bebd70184367 --- /dev/null +++ b/safe_string/strislowercase_s.c @@ -0,0 +1,118 @@ +/*------------------------------------------------------------------ + * strislowercase_s.c + * + * February 2005, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strislowercase_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strislowercase_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks if entire string is lowercase. + * The scanning stops at the first null or after dmax + * characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dest shal be null terminated. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true string is lowercase + * false string is not lowercase or an error occurred + * + * ALSO SEE + * strisalphanumeric_s(), strisascii_s(), strisdigit_s(), + * strishex_s(), strismixedcase_s(), + * strisuppercase_s() + * + */ +bool +strislowercase_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strislowercase_s: " + "dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strislowercase_s: " + "dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strislowercase_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest && dmax) { + + if ((*dest < 'a') || (*dest > 'z')) { + return (false); + } + dest++; + dmax--; + } + + return (true); +} diff --git a/safe_string/strismixedcase_s.c b/safe_string/strismixedcase_s.c new file mode 100644 index 000000000000..2cfca3ce2633 --- /dev/null +++ b/safe_string/strismixedcase_s.c @@ -0,0 +1,119 @@ +/*------------------------------------------------------------------ + * strismixedcase_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strismixedcase_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strismixedcase_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks that the entire string is mixed + * case. The scanning stops at the first null or after + * dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true string is mixed case + * false string is not mixed case or error + * + * ALSO SEE + * strisalphanumeric_s(), strisascii_s(), strisdigit_s(), + * strishex_s(), strislowercase_s(), + * strisuppercase_s() + * + */ +bool +strismixedcase_s (const char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strismixedcase_s: " + "dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strismixedcase_s: " + "dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strismixedcase_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest) { + + if (((*dest >= 'a') && (*dest <= 'z')) || + ((*dest >= 'A') && (*dest <= 'Z'))) { + dest++; + dmax--; + } else { + return (false); + } + } + + return (true); +} diff --git a/safe_string/strispassword_s.c b/safe_string/strispassword_s.c new file mode 100644 index 000000000000..56d709c3c5e2 --- /dev/null +++ b/safe_string/strispassword_s.c @@ -0,0 +1,168 @@ +/*------------------------------------------------------------------ + * strispassword_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strispassword_s + * + * SYNOPSIS + * #include "strlib.h" + * bool + * strispassword_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function validates the make-up of a password string. + * -SAFE_STR_PASSWORD_MIN_LENGTH character minimum + * -SAFE_STR_PASSWORD_MAX_LENGTH character maximum + * -at least SAFE_STR_MIN_LOWERCASE lower case characters + * -at least SAFE_STR_MIN_UPPERCASE upper case characters + * -at least SAFE_STR_MIN_NUMBERS number + * -at least SAFE_STR_MIN_SPECIALS special + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax length of password string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * length > SAFE_STR_PASSWORD_MIN_LENGTH + * length < SAFE_STR_PASSWORD_MAX_LENGTH + * dest shall not be unterminated + * + * RETURN VALUE + * true, string has valid password makeup + * false, string does not meet requirements or an error occurred + * + * ALSO SEE + * strzero_s() + * + */ +bool +strispassword_s (const char *dest, rsize_t dmax) +{ + uint32_t cnt_all; + uint32_t cnt_lowercase; + uint32_t cnt_uppercase; + uint32_t cnt_numbers; + uint32_t cnt_specials; + + if (!dest) { + invoke_safe_str_constraint_handler("strispassword_s: " + "dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax < SAFE_STR_PASSWORD_MIN_LENGTH) { + invoke_safe_str_constraint_handler("strispassword_s: " + "dest is too short", + NULL, ESLEMIN); + return (false); + } + + if (dmax > SAFE_STR_PASSWORD_MAX_LENGTH) { + invoke_safe_str_constraint_handler("strispassword_s: " + "dest exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + cnt_all = cnt_lowercase = cnt_uppercase = 0; + cnt_numbers = cnt_specials = 0; + + while (*dest) { + + if (dmax == 0) { + invoke_safe_str_constraint_handler( + "strispassword_s: dest is unterminated", + NULL, ESUNTERM); + return (false); + } + dmax--; + + cnt_all++; + + if ((*dest >= '0') && (*dest <= '9')) { + cnt_numbers++; + + } else if ((*dest >= 'a') && (*dest <= 'z')) { + cnt_lowercase++; + + } else if ((*dest >= 'A') && (*dest <= 'Z')) { + cnt_uppercase++; + + /* allow all specials */ + } else if ((*dest >= 33) && (*dest <= 47)) { + cnt_specials++; + } else if ((*dest >= 58) && (*dest <= 64)) { + cnt_specials++; + } else if ((*dest >= 91) && (*dest <= 94)) { + cnt_specials++; + } else if ((*dest >= 95) && (*dest <= 96)) { + cnt_specials++; + } else if ((*dest >= 123) && (*dest <= 126)) { + cnt_specials++; + + } else { + /* illegal char in password string */ + return (false); + } + dest++; + } + + if (cnt_all < SAFE_STR_PASSWORD_MAX_LENGTH && + cnt_numbers >= SAFE_STR_MIN_NUMBERS && + cnt_lowercase >= SAFE_STR_MIN_LOWERCASE && + cnt_uppercase >= SAFE_STR_MIN_UPPERCASE && + cnt_specials >= SAFE_STR_MIN_SPECIALS ) { + return (true); + } else { + return (false); + } +} diff --git a/safe_string/strisuppercase_s.c b/safe_string/strisuppercase_s.c new file mode 100644 index 000000000000..f86e23b5f613 --- /dev/null +++ b/safe_string/strisuppercase_s.c @@ -0,0 +1,117 @@ +/*------------------------------------------------------------------ + * strisuppercase_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strisuppercase_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * bool + * strisuppercase_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * This function checks if entire string is uppercase + * The scanning stops at the first null or after dmax + * characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * true string is uppercase + * false string is not uppercase or an error occurred + * + * ALSO SEE + * strisalphanumeric_s(), strisascii_s(), strisdigit_s(), + * strishex_s(), strislowercase_s(), strismixedcase_s(), + * + */ +bool +strisuppercase_s (const char *dest, rsize_t dmax) +{ + + if (!dest) { + invoke_safe_str_constraint_handler("strisuppercase_s: " + "dest is null", + NULL, ESNULLP); + return (false); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strisuppercase_s: " + "dmax is 0", + NULL, ESZEROL); + return (false); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strisuppercase_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (false); + } + + if (*dest == '\0') { + return (false); + } + + while (*dest) { + + if ((*dest < 'A') || (*dest > 'Z')) { + return (false); + } + dest++; + dmax--; + } + + return (true); +} diff --git a/safe_string/strlastchar_s.c b/safe_string/strlastchar_s.c new file mode 100644 index 000000000000..2fd224c85139 --- /dev/null +++ b/safe_string/strlastchar_s.c @@ -0,0 +1,131 @@ +/*------------------------------------------------------------------ + * strlastchar_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strlastchar_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strlastchar_s(char *dest, rsize_t dmax, char c, char **last) + * + * DESCRIPTION + * Returns a pointer to the last occurrence of character c in + * dest. The scanning stops at the first null or after dmax + * characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax restricted maximum length of string + * + * c character to locate + * + * last returned pointer to last occurrence + * + * OUTPUT PARAMETERS + * last updated pointer to last occurrence + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * last shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * pointer to the last occurrence, when the return code is OK + * + * EOK pointer to the last occurence is returned + * ESNOTFND c not found in dest + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strfirstchar_s(), strfirstdiff_s(), strfirstsame_s(), + * strlastdiff_s(), strlastsame_s() + * + */ +errno_t +strlastchar_s(char *dest, rsize_t dmax, char c, char **last) +{ + if (last == NULL) { + invoke_safe_str_constraint_handler("strlastchar_s: last is null", + NULL, ESNULLP); + return (ESNULLP); + } + *last = NULL; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strlastchar_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strlastchar_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strlastchar_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + while (*dest && dmax) { + + if (*dest == c) { + *last = dest; + } + + dest++; + dmax--; + } + + if (*last == NULL) { + return (ESNOTFND); + } else { + return (EOK); + } +} diff --git a/safe_string/strlastdiff_s.c b/safe_string/strlastdiff_s.c new file mode 100644 index 000000000000..b7baa0d7ffd3 --- /dev/null +++ b/safe_string/strlastdiff_s.c @@ -0,0 +1,151 @@ +/*------------------------------------------------------------------ + * strlastdiff_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strlastdiff_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strlastdiff_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t *index) + * + * DESCRIPTION + * Returns the index of the last character that is different + * between dest and src. Index is valid only for EOK. + * The scanning stops at the first null in dest or src, or + * after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * index pointer to returned index of last difference + * + * OUTPUT PARAMETERS + * index updated index of last difference + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * index to last difference, when the return code is OK + * + * EOK index to last diff is returned + * ESNODIFF no difference + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strfirstchar_s(), strfirstdiff_s(), strfirstsame_s(), + * strlastchar_s(), strlastsame_s() + * + */ +errno_t +strlastdiff_s(const char *dest, rsize_t dmax, + const char *src, rsize_t *index) +{ + const char *rp; + bool there_is_a_diff = false; + + if (index == NULL) { + invoke_safe_str_constraint_handler("strlastdiff_s: index is null", + NULL, ESNULLP); + return (ESNULLP); + } + *index = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strlastdiff_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strlastdiff_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strlastdiff_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strlastdiff_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* hold reference point */ + rp = dest; + + /* + * find the last diff + */ + while (*dest && *src && dmax) { + + if (*dest != *src) { + there_is_a_diff = true; + *index = dest - rp; + } + + dest++; + src++; + dmax--; + } + + if (there_is_a_diff) { + return (EOK); + } else { + return (ESNODIFF); + } +} diff --git a/safe_string/strlastsame_s.c b/safe_string/strlastsame_s.c new file mode 100644 index 000000000000..36de34d79494 --- /dev/null +++ b/safe_string/strlastsame_s.c @@ -0,0 +1,152 @@ +/*------------------------------------------------------------------ + * strlastsame_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strlastsame_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strlastsame_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t *index) + * + * DESCRIPTION + * Returns the index of the last character that is the + * same between dest and src. The scanning stops at the + * first nul in dest or src, or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of string dest + * + * src pointer to the string to be compared to dest + * + * index pointer to returned index + * + * OUTPUT PARAMETERS + * index updated index + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall not be a null pointer. + * indicator shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * index to last same char, when the return code is OK + * + * EOK index to last same char is returned + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESNOTFND not found + * ESUNTERM string unterminated + * + * ALSO SEE + * strfirstchar_s(), strfirstdiff_s(), strfirstsame_s(), + * strlastchar_s(), strlastdiff_s() + * + */ +errno_t +strlastsame_s (const char *dest, rsize_t dmax, + const char *src, rsize_t *index) +{ + const char *rp; + bool similarity; + + if (index == NULL) { + invoke_safe_str_constraint_handler("strlastsame_s: index is null", + NULL, ESNULLP); + return (ESNULLP); + } + *index = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strlastsame_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strlastsame_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strlastsame_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strlastsame_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* hold reference point */ + rp = dest; + + /* + * find the last offset + */ + similarity = false; + while (*dest && *src && dmax) { + + if (*dest == *src) { + similarity = true; + *index = (uint32_t)(dest - rp); + } + + dest++; + src++; + dmax--; + } + + if (similarity) { + return (EOK); + } else { + return (ESNOTFND); + } +} diff --git a/safe_string/strljustify_s.c b/safe_string/strljustify_s.c new file mode 100644 index 000000000000..08d07136427a --- /dev/null +++ b/safe_string/strljustify_s.c @@ -0,0 +1,159 @@ +/*------------------------------------------------------------------ + * strljustify_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reseved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strljustify_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strljustify_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * Removes beginning whitespace from the string pointed to by + * dest by shifting the text left over writting the beginning + * whitespace, left justifying the text. The left justified + * text is null terminated. + * + * The text is shifted so the original pointer can continue + * to be used. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to left justify + * + * dmax restricted maximum length of string + * + * OUTPUT PARAMETERS + * dest left justified + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * dest shall be null terminated + * + * RETURN VALUE + * EOK + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESUNTERM dest was not null terminated + * + * ALSO SEE + * strremovews_s(), + * + */ +errno_t +strljustify_s (char *dest, rsize_t dmax) +{ + char *orig_dest; + rsize_t orig_dmax; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strljustify_s_s: " + "dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strljustify_s_s: " + "dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strljustify_s_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* + * corner case, a dmax of one allows only for a null + */ + if (*dest == '\0' || dmax <= RSIZE_MIN_STR) { + *dest = '\0'; + return (EOK); + } + + orig_dmax = dmax; + orig_dest = dest; + + /* + * scan the string to be sure it is properly terminated + */ + while (*dest) { + if (dmax == 0) { + while (orig_dmax) { *orig_dest++ = '\0'; orig_dmax--; } + + invoke_safe_str_constraint_handler( + "strljustify_s: dest is unterminated", + NULL, ESUNTERM); + return (ESUNTERM); + } + dmax--; + dest++; + } + + /* + * find first non-white space char + */ + dest = orig_dest; + while ((*dest == ' ') || (*dest == '\t')) { + dest++; + } + + /* + * shift text, removing spaces, to left justify + */ + if (orig_dest != dest && *dest) { + while (*dest) { + *orig_dest++ = *dest; + *dest++ = ' '; + } + *orig_dest = '\0'; + } + + return (EOK); +} diff --git a/safe_string/strncpy_s.c b/safe_string/strncpy_s.c new file mode 100644 index 000000000000..90a366c72999 --- /dev/null +++ b/safe_string/strncpy_s.c @@ -0,0 +1,238 @@ +/*------------------------------------------------------------------ + * strncpy_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/* + * NAME + * strncpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strncpy_s(char *dest, rsize_t dmax, const char *src, rsize_t slen) + * + * DESCRIPTION + * The strncpy_s function copies not more than slen successive characters + * (characters that follow a null character are not copied) from the + * array pointed to by src to the array pointed to by dest. If no null + * character was copied from src, then dest[n] is set to a null character. + * + * All elements following the terminating null character (if any) + * written by strncpy_s in the array of dmax characters pointed to + * by dest take on the null value when strncpy_s returns. + * + * Specicified in: + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * The resulting string is null terminated. + * + * dmax restricted maximum length of the resulting dest, + * including the null + * + * src pointer to the string that will be copied + * to string dest + * + * slen the maximum number of characters to copy from src + * + * OUTPUT PARAMETERS + * dest updated with src string + * + * RUNTIME CONSTRAINTS + * Neither dmax nor slen shall be equal to zero. + * Neither dmax nor slen shall be equal zero. + * Neither dmax nor slen shall be greater than RSIZE_MAX_STR. + * If slen is either greater than or equal to dmax, then dmax + * should be more than strnlen_s(src,dmax) + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and dmax greater than RSIZE_MAX_STR, + * then strncpy_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, the characters in src were copied + * to dest and the result is null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * ALSO SEE + * strcat_s(), strncat_s(), strcpy_s() + *- + */ +errno_t +strncpy_s (char *dest, rsize_t dmax, const char *src, rsize_t slen) +{ + rsize_t orig_dmax; + char *orig_dest; + const char *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strncpy_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strncpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strncpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* hold base in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (src == NULL) { + handle_error(orig_dest, orig_dmax, "strncpy_s: " + "src is null", + ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (slen == 0) { + handle_error(orig_dest, orig_dmax, "strncpy_s: " + "slen is zero", + ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + handle_error(orig_dest, orig_dmax, "strncpy_s: " + "slen exceeds max", + ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strncpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + if (slen == 0) { + /* + * Copying truncated to slen chars. Note that the TR says to + * copy slen chars plus the null char. We null the slack. + */ +#ifdef SAFECLIB_STR_NULL_SLACK + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_error(orig_dest, orig_dmax, "strncpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + if (slen == 0) { + /* + * Copying truncated to slen chars. Note that the TR says to + * copy slen chars plus the null char. We null the slack. + */ +#ifdef SAFECLIB_STR_NULL_SLACK + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + } + + /* + * the entire src was not copied, so zero the string + */ + handle_error(orig_dest, orig_dmax, "strncpy_s: not enough " + "space for src", + ESNOSPC); + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(strncpy_s); */ diff --git a/safe_string/strnlen_s.c b/safe_string/strnlen_s.c new file mode 100644 index 000000000000..d78b18d037fd --- /dev/null +++ b/safe_string/strnlen_s.c @@ -0,0 +1,112 @@ +/*------------------------------------------------------------------ + * strnlen_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strnlen_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * rsize_t + * strnlen_s(const char *dest, rsize_t dmax) + * + * DESCRIPTION + * The strnlen_s function computes the length of the string pointed + * to by dest. + * + * SPECIFIED IN + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax restricted maximum length. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer + * dmax shall not be greater than RSIZE_MAX_STR + * dmax shall not equal zero + * + * RETURN VALUE + * The function returns the string length, excluding the terminating + * null character. If dest is NULL, then strnlen_s returns 0. + * + * Otherwise, the strnlen_s function returns the number of characters + * that precede the terminating null character. If there is no null + * character in the first dmax characters of dest then strnlen_s returns + * dmax. At most the first dmax characters of dest are accessed + * by strnlen_s. + * + * ALSO SEE + * strnterminate_s() + * + */ +rsize_t +strnlen_s (const char *dest, rsize_t dmax) +{ + rsize_t count; + + if (dest == NULL) { + return RCNEGATE(0); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strnlen_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(0); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strnlen_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(0); + } + + count = 0; + while (*dest && dmax) { + count++; + dmax--; + dest++; + } + + return RCNEGATE(count); +} +/* EXPORT_SYMBOL(strnlen_s); */ diff --git a/safe_string/strnterminate_s.c b/safe_string/strnterminate_s.c new file mode 100644 index 000000000000..683461774540 --- /dev/null +++ b/safe_string/strnterminate_s.c @@ -0,0 +1,112 @@ +/*------------------------------------------------------------------ + * strnterminate_s.c + * + * February 2011, Bo Berry + * + * Copyright (c) 2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strnterminate_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * rsize_t + * strnterminate_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * The strnterminate_s function will terminate the string if a + * null is not encountered before dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest - pointer to string + * + * dmax - restricted maximum length + * + * OUTPUT PARAMETERS + * dest - dest is terminated if needed + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer + * dmax shall not be greater than RSIZE_MAX_STR + * dmax shall not equal zero + * + * RETURN VALUE + * The function returns a terminated string. If a null is not + * encountered prior to dmax characters, the dmax character is + * set to null terminating the string. The string length is + * also returned. + * + * ALSO SEE + * strnlen_s() + * + */ +rsize_t +strnterminate_s (char *dest, rsize_t dmax) +{ + rsize_t count; + + if (dest == NULL) { + return (0); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strnterminate_s: dmax is 0", + NULL, ESZEROL); + return (0); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strnterminate_s: dmax exceeds max", + NULL, ESLEMAX); + return (0); + } + + count = 0; + while (dmax > 1) { + if (*dest) { + count++; + dmax--; + dest++; + } else { + break; + } + } + *dest = '\0'; + + return (count); +} diff --git a/safe_string/strpbrk_s.c b/safe_string/strpbrk_s.c new file mode 100644 index 000000000000..8fb6f0d94dff --- /dev/null +++ b/safe_string/strpbrk_s.c @@ -0,0 +1,163 @@ +/*------------------------------------------------------------------ + * strpbrk_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strpbrk_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strpbrk_s(char *dest, rsize_t dmax, + * char *src, rsize_t slen, char **first) + * + * DESCRIPTION + * Returns a pointer, first, to the first ocurrence of any character + * in src which is contained in dest. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax restricted maximum length of string dest + * + * src pointer to string + * + * slen restricted length of string src + * + * first returned pointer to first occurence + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * first shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * pointer to the first ocurrence of any character + * contained in src + * + * EOK count + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strfirstchar_s(), strlastchar_s(), strfirstdiff_s(), + * strfirstsame_s(), strlastdiff_s(), strlastsame_s() + * + */ +errno_t +strpbrk_s (char *dest, rsize_t dmax, + char *src, rsize_t slen, char **first) +{ + char *ps; + rsize_t len; + + if (first == NULL) { + invoke_safe_str_constraint_handler("strpbrk_s: count is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *first = NULL; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strpbrk_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strpbrk_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strpbrk_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strpbrk_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (slen == 0 ) { + invoke_safe_str_constraint_handler("strpbrk_s: slen is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strpbrk_s: slen exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* + * look for a matching char in the substring src + */ + while (*dest && dmax) { + + ps = src; + len = slen; + while (*ps) { + + /* check for a match with the substring */ + if (*dest == *ps) { + *first = dest; + return RCNEGATE(EOK); + } + ps++; + len--; + } + dest++; + dmax--; + } + + return RCNEGATE(ESNOTFND); +} +/* EXPORT_SYMBOL(strpbrk_s); */ diff --git a/safe_string/strprefix_s.c b/safe_string/strprefix_s.c new file mode 100644 index 000000000000..6aae7dced206 --- /dev/null +++ b/safe_string/strprefix_s.c @@ -0,0 +1,127 @@ +/*------------------------------------------------------------------ + * strprefix_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strprefix_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strprefix_s(const char *dest, rsize_t dmax, const char *src) + * + * DESCRIPTION + * Determines if the prefix pointed to by src is at the + * beginning of string pointed to by dest. The prefix + * must be a complete match in dest. Useful for command + * or user input parsing. The scanning stops at the first + * null in dest or src, or after dmax characters. + * + * EXTENSION TO + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to compare against + * + * dmax restricted maximum length of dest + * + * src pointer to the prefix + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * EOK successful operation, prefix present in dest + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESNOTFND prefix not found in dest + * + * ALSO SEE + * strspn_s(), strcspn_s(), strpbrk_s(), strstr_s() + * + */ +errno_t +strprefix_s (const char *dest, rsize_t dmax, const char *src) +{ + if (dest == NULL) { + invoke_safe_str_constraint_handler("strprefix_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strprefix_s: src is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strprefix_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strprefix_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + if (*src == '\0') { + return (ESNOTFND); + } + + while (*src && dmax) { + + if (*dest != *src) { + return (ESNOTFND); + } + + dmax--; + dest++; + src++; + } + + return (EOK); +} diff --git a/safe_string/strremovews_s.c b/safe_string/strremovews_s.c new file mode 100644 index 000000000000..77107354c8fd --- /dev/null +++ b/safe_string/strremovews_s.c @@ -0,0 +1,163 @@ +/*------------------------------------------------------------------ + * strremovews_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights resevered. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strremovews_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strremovews_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * Removes beginning and trailing whitespace from the string pointed to by + * dest by shifting the text left over writting the beginning whitespace. + * The shifted-trimmed text is null terminated. + * + * The text is shifted so the original pointer can continue to be used. This + * is useful when the memory was malloc'ed and will need to be freed. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to remove whitespace + * + * dmax restricted maximum length of string + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * dest shall be null terminated + * + * RETURN VALUE + * EOK + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESUNTERM dest was not null terminated + * + * SEE ALSO + * strljustify_s(), + * + */ +errno_t +strremovews_s (char *dest, rsize_t dmax) +{ + char *orig_dest; + char *orig_end; + rsize_t orig_dmax; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strremovews_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strremovews_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strremovews_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* + * corner case, a dmax of one requires a null + */ + if (*dest == '\0' || dmax <= RSIZE_MIN_STR) { + *dest = '\0'; + return (EOK); + } + + orig_dest = dest; + orig_dmax = dmax; + + /* + * scan the string to be sure it is properly terminated + */ + while (*dest) { + if (dmax == 0) { + while (orig_dmax) { *orig_dest++ = '\0'; orig_dmax--; } + + invoke_safe_str_constraint_handler( + "strremovews_s: dest is unterminated", + NULL, ESUNTERM); + return (ESUNTERM); + } + dmax--; + dest++; + } + + /* + * find first non-white space char + */ + orig_end = dest-1; + dest = orig_dest; + while ((*dest == ' ') || (*dest == '\t')) { + dest++; + } + + /* + * shift the text over the leading spaces + */ + if (orig_dest != dest && *dest) { + while (*dest) { + *orig_dest++ = *dest; + *dest++ = ' '; + } + *dest = '\0'; + } + + /* + * strip trailing whitespace + */ + dest = orig_end; + while ((*dest == ' ') || (*dest == '\t')) { + *dest = '\0'; + dest--; + } + + return (EOK); +} diff --git a/safe_string/strspn_s.c b/safe_string/strspn_s.c new file mode 100644 index 000000000000..863472b70b9d --- /dev/null +++ b/safe_string/strspn_s.c @@ -0,0 +1,170 @@ +/*------------------------------------------------------------------ + * strspn_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011, 2013 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strspn_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strspn_s(const char *dest, rsize_t dmax, + * const char *src, rsize_t slen, rsize_t *count) + * + * DESCRIPTION + * This function computes the prefix length of the string + * pointed to by dest which consists entirely of characters + * that are included from the string pointed to by src. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to determine the prefix + * + * dmax restricted maximum length of string dest + * + * src pointer to exclusion string + * + * slen restricted maximum length of string src + * + * count pointer to a count variable that will be updated + * with the dest substring length + * + * OUTPUT PARAMETERS + * count updated count + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * count shall not be a null pointer. + * dmax shall not be 0 + * dmax shall not be greater than RSIZE_MAX_STR + * + * RETURN VALUE + * EOK count + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strcspn_s(), strpbrk_s(), strstr_s(), strprefix_s() + * + */ +errno_t +strspn_s (const char *dest, rsize_t dmax, + const char *src, rsize_t slen, rsize_t *count) +{ + const char *scan2; + rsize_t smax; + bool match_found; + + if (count== NULL) { + invoke_safe_str_constraint_handler("strspn_s: count is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *count = 0; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strspn_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strspn_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0 ) { + invoke_safe_str_constraint_handler("strspn_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strspn_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (slen == 0 ) { + invoke_safe_str_constraint_handler("strspn_s: slen is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strspn_s: slen exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + while (*dest && dmax) { + + /* + * Scan the entire src string for each dest character, counting + * inclusions. + */ + match_found = false; + smax = slen; + scan2 = src; + while (*scan2 && smax) { + + if (*dest == *scan2) { + match_found = true; + break; + } + scan2++; + smax--; + } + + if (match_found) { + (*count)++; + } else { + break; + } + + dest++; + dmax--; + } + + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(strspn_s); */ diff --git a/safe_string/strstr_s.c b/safe_string/strstr_s.c new file mode 100644 index 000000000000..58d100247c01 --- /dev/null +++ b/safe_string/strstr_s.c @@ -0,0 +1,179 @@ +/*------------------------------------------------------------------ + * strstr_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strstr_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strstr_s(char *dest, rsize_t dmax, + * const char *src, rsize_t slen, char **substring) + * + * DESCRIPTION + * The strstr_s() function locates the first occurrence of the + * substring pointed to by src which would be located in the + * string pointed to by dest. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to be searched for the substring + * + * dmax restricted maximum length of dest string + * + * src pointer to the sub string + * + * slen the maximum number of characters to copy from src + * + * substring the returned substring pointer + * + * OUTPUT PARAMETERS + * substring returned substring pointer + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Meither dmax nor slen shall be zero. + * Neither dmax nor slen shall be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * EOK successful operation, substring found. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESNOTFND substring not found + * + * ALSO SEE + * strprefix_s(), strspn_s(), strcspn_s(), strpbrk_s() + * + */ +errno_t +strstr_s (char *dest, rsize_t dmax, + const char *src, rsize_t slen, char **substring) +{ + rsize_t len; + rsize_t dlen; + int i; + + if (substring == NULL) { + invoke_safe_str_constraint_handler("strstr_s: substring is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + *substring = NULL; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("strstr_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strstr_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strstr_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strstr_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (slen == 0) { + invoke_safe_str_constraint_handler("strstr_s: slen is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strstr_s: slen exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* + * src points to a string with zero length, or + * src equals dest, return dest + */ + if (*src == '\0' || dest == src) { + *substring = dest; + return RCNEGATE(EOK); + } + + while (*dest && dmax) { + i = 0; + len = slen; + dlen = dmax; + + while (src[i] && dlen) { + + /* not a match, not a substring */ + if (dest[i] != src[i]) { + break; + } + + /* move to the next char */ + i++; + len--; + dlen--; + + if (src[i] == '\0' || !len) { + *substring = dest; + return RCNEGATE(EOK); + } + } + dest++; + dmax--; + } + + /* + * substring was not found, return NULL + */ + *substring = NULL; + return RCNEGATE(ESNOTFND); +} +/* EXPORT_SYMBOL(strstr_s); */ diff --git a/safe_string/strtok_s.c b/safe_string/strtok_s.c new file mode 100644 index 000000000000..1a293285f81f --- /dev/null +++ b/safe_string/strtok_s.c @@ -0,0 +1,323 @@ +/*------------------------------------------------------------------ + * strtok_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strtok_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * char * + * strtok_s(char *dest, rsize_t *dmax, char *src, char **ptr) + * + * DESCRIPTION + * A sequence of calls to the strtok_s function breaks the string + * pointed to by dest into a sequence of tokens, each of which is + * delimited by a character from the string pointed to by src. The + * fourth argument points to a caller-provided char pointer into + * which the strtok_s function stores information necessary for + * it to continue scanning the same string. + * + * The first call in a sequence has a non-null first argument and + * dmax points to an object whose value is the number of elements + * in the character array pointed to by the first argument. The + * first call stores an initial value in the object pointed to by + * ptr and updates the value pointed to by dmax to reflect the + * number of elements that remain in relation to ptr. Subsequent + * calls in the sequence have a null first argument and the objects + * pointed to by dmax and ptr are required to have the values + * stored by the previous call in the sequence, which are then + * updated. The separator string pointed to by src may be different + * from call to call. + * + * The first call in the sequence searches the string pointed to + * by dest for the first character that is not contained in the + * current separator string pointed to by src. If no such character + * is found, then there are no tokens in the string pointed to + * by dest and the strtok_s function returns a null pointer. If + * such a character is found, it is the start of the first token. + * + * The strtok_s function then searches from there for the first + * character in dest that is contained in the current separator + * string. If no such character is found, the current token + * extends to the end of the string pointed to by dest, and + * subsequent searches in the same string for a token return + * a null pointer. If such a character is found, it is + * overwritten by a null character, which terminates the + * current token. + * + * In all cases, the strtok_s function stores sufficient information + * in the pointer pointed to by ptr so that subsequent calls, + * with a null pointer for dest and the unmodified pointer value + * for ptr, shall start searching just past the element overwritten + * by a null character (if any). + * + * SPECIFIED IN + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string to tokenize + * + * dmax restricted maximum length of dest string + * + * src pointer to delimiter string (len < 255) + * + * ptr returned pointer to token + * + * OUTPUT PARAMETERS + * dmax update length + * + * ptr update pointer to token + * + * RUNTIME CONSTRAINTS + * src shall not be a null pointer. + * ptr shall not be a null pointer. + * dmax shall not be a null pointer. + * *dmax shall not be 0. + * + * If dest is a null pointer, then *ptr shall not be a null pointer. + * + * dest must not be unterminated. + * + * The value of *dmax shall not be greater than RSIZE_MAX_STR. The + * end of the token found shall occur within the first *dmax + * characters of dest for the first call, and shall occur within + * the first *dmax characters of where searching resumes on + * subsequent calls. + * + * RETURN VALUE + * The strtok_s function returns a pointer to the first character + * of a token; or a null pointer if there is no token or there + * is a runtime-constraint violation. + * + * EOK + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESUNTERM unterminated string + * + * EXAMPLES + * [1] Sequencial strtok_s() calls to tokenize a string + * + * String to tokenize str1 = ",.:*one,two;three,;four*.*.five-six***" + * len=38 + * String of delimiters str2 = ",.;*" + * + * p2tok = strtok_s(str1, &len, str2, &p2str); + * token -one- remaining -two;three,;four*.*.five-six***- len=30 + * + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * token -two- remaining -three,;four*.*.five-six***- len=26 + * + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * token -three- remaining -;four*.*.five-six***- len=20 + * + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * token -four- remaining -.*.five-six***- len=14 + * + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * token -five-six- remaining -**- len=2 + * + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * token -(null)- remaining -**- len=0 + * + * + * [2] While loop with same entry data as [1] + * + * p2tok = str1; + * while (p2tok && len) { + * p2tok = strtok_s(NULL, &len, str2, &p2str); + * printf(" token -- remaining -- len=0 \n", + * p2tok, p2str, (int)len ); + * } + * + *- + */ +char * +strtok_s(char *dest, rsize_t *dmax, const char *src, char **ptr) +{ + +/* + * CONFIGURE: The spec does not call out a maximum for the src + * string, so one is defined here. + */ +#define STRTOK_DELIM_MAX_LEN ( 16 ) + + + const char *pt; + char *ptoken; + rsize_t dlen; + rsize_t slen; + + if (dmax == NULL) { + invoke_safe_str_constraint_handler("strtok_s: dmax is NULL", + NULL, ESNULLP); + return (NULL); + } + + if (*dmax == 0) { + invoke_safe_str_constraint_handler("strtok_s: dmax is 0", + NULL, ESZEROL); + return (NULL); + } + + if (*dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strtok_s: dmax exceeds max", + NULL, ESLEMAX); + return (NULL); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("strtok_s: src is null", + NULL, ESNULLP); + return (NULL); + } + + if (ptr == NULL) { + invoke_safe_str_constraint_handler("strtok_s: ptr is null", + NULL, ESNULLP); + return (NULL); + } + + /* if the source was NULL, use the tokenizer context */ + if (dest == NULL) { + dest = *ptr; + } + + /* + * scan dest for a delimiter + */ + dlen = *dmax; + ptoken = NULL; + while (*dest != '\0' && !ptoken) { + + if (dlen == 0) { + *ptr = NULL; + invoke_safe_str_constraint_handler( + "strtok_s: dest is unterminated", + NULL, ESUNTERM); + return (NULL); + } + + /* + * must scan the entire delimiter list + * ISO should have included a delimiter string limit!! + */ + slen = STRTOK_DELIM_MAX_LEN; + pt = src; + while (*pt != '\0') { + + if (slen == 0) { + *ptr = NULL; + invoke_safe_str_constraint_handler( + "strtok_s: src is unterminated", + NULL, ESUNTERM); + return (NULL); + } + slen--; + + if (*dest == *pt) { + ptoken = NULL; + break; + } else { + pt++; + ptoken = dest; + } + } + dest++; + dlen--; + } + + /* + * if the beginning of a token was not found, then no + * need to continue the scan. + */ + if (ptoken == NULL) { + *dmax = dlen; + return (ptoken); + } + + /* + * Now we need to locate the end of the token + */ + while (*dest != '\0') { + + if (dlen == 0) { + *ptr = NULL; + invoke_safe_str_constraint_handler( + "strtok_s: dest is unterminated", + NULL, ESUNTERM); + return (NULL); + } + + slen = STRTOK_DELIM_MAX_LEN; + pt = src; + while (*pt != '\0') { + + if (slen == 0) { + *ptr = NULL; + invoke_safe_str_constraint_handler( + "strtok_s: src is unterminated", + NULL, ESUNTERM); + return (NULL); + } + slen--; + + if (*dest == *pt) { + /* + * found a delimiter, set to null + * and return context ptr to next char + */ + *dest = '\0'; + *ptr = (dest + 1); /* return pointer for next scan */ + *dmax = dlen - 1; /* account for the nulled delimiter */ + return (ptoken); + } else { + /* + * simply scanning through the delimiter string + */ + pt++; + } + } + dest++; + dlen--; + } + + *dmax = dlen; + return (ptoken); +} diff --git a/safe_string/strtolowercase_s.c b/safe_string/strtolowercase_s.c new file mode 100644 index 000000000000..964be8b2941c --- /dev/null +++ b/safe_string/strtolowercase_s.c @@ -0,0 +1,114 @@ +/*------------------------------------------------------------------ + * strtolowercase_s.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strtolowercase_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strlolowercase_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * Scans the string converting uppercase characters to + * lowercase, leaving all other characters unchanged. + * The scanning stops at the first null or after dmax + * characters. + * + * Extenstion to: + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * dest updated string + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strtouppercase_s() + * + */ +errno_t +strtolowercase_s (char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strtolowercase_s: " + "dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strtolowercase_s: " + "dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strtolowercase_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + while (*dest && dmax) { + + if ( (*dest >= 'A') && (*dest <= 'Z')) { + *dest = (char)(*dest + (char)32); + } + dest++; + dmax--; + } + + return (EOK); +} diff --git a/safe_string/strtouppercase_s.c b/safe_string/strtouppercase_s.c new file mode 100644 index 000000000000..e319b9b89e34 --- /dev/null +++ b/safe_string/strtouppercase_s.c @@ -0,0 +1,114 @@ +/*------------------------------------------------------------------ + * safe_str_touppercase.c + * + * November 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strtouppercase_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strlouppercase_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * Scans the string converting lowercase characters to + * uppercase, leaving all other characters unchanged. + * The scanning stops at the first null or after dmax + * characters. + * + * Extenstion to: + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string + * + * dmax maximum length of string + * + * OUTPUT PARAMETERS + * dest updated string + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * dmax shall not equal zero. + * dmax shall not be greater than RSIZE_MAX_STR. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strtolowercase_s() + * + */ +errno_t +strtouppercase_s (char *dest, rsize_t dmax) +{ + if (!dest) { + invoke_safe_str_constraint_handler("strtouppercase_s: " + "dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strtouppercase_s: " + "dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strtouppercase_s: " + "dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + while (*dest && dmax) { + + if ((*dest >= 'a') && (*dest <= 'z')) { + *dest = (char)(*dest - 32); + } + dest++; + dmax--; + } + + return (EOK); +} diff --git a/safe_string/strzero_s.c b/safe_string/strzero_s.c new file mode 100644 index 000000000000..326eb825fc31 --- /dev/null +++ b/safe_string/strzero_s.c @@ -0,0 +1,102 @@ +/*------------------------------------------------------------------ + * strzero_s.c + * + * October 2008, Bo Berry + * + * Copyright (c) 2008-2011 by Cisco Systems, Inc + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * strzero_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * strzero_s(char *dest, rsize_t dmax) + * + * DESCRIPTION + * Nulls dmax characters of dest. This function can be used + * to clear strings that contained sensitive data. + * + * EXTENSION TO + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be nulled. + * + * dmax restricted maximum length of dest + * + * OUTPUT PARAMETERS + * dest updated string + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * strispassword_s() + * + */ +errno_t +strzero_s (char *dest, rsize_t dmax) +{ + if (dest == NULL) { + invoke_safe_str_constraint_handler("strzero_s: dest is null", + NULL, ESNULLP); + return (ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("strzero_s: dmax is 0", + NULL, ESZEROL); + return (ESZEROL); + } + + if (dmax > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("strzero_s: dmax exceeds max", + NULL, ESLEMAX); + return (ESLEMAX); + } + + /* null string to eliminate data */ + while (dmax) { + *dest = '\0'; + dmax--; + dest++; + } + + return (EOK); +} diff --git a/safe_string/wcpcpy_s.c b/safe_string/wcpcpy_s.c new file mode 100644 index 000000000000..4e5b9a7cfbbc --- /dev/null +++ b/safe_string/wcpcpy_s.c @@ -0,0 +1,219 @@ +/*------------------------------------------------------------------ + * wcpcpy_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * wcpcpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * wchar_t * + * wcpcpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, errno_t *err) + * + * DESCRIPTION + * The wcpcpy_s function copies the wide character string pointed + * to by src (including the terminating null character) into the + * array pointed to by dest, and returns a pointer to the end of + * the wide character string. All elements following the terminating + * null character (if any) written by wcpcpy_s in the array of + * dmax characters pointed to by dest are nulled when + * wcpcpy_s returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the wide character string that will be copied + * to dest + * + * err the error code upon error, or EOK if successful + * + * OUTPUT PARAMETERS + * dest updated + * err updated as follows: + * EOK successful operation, the characters in src were + * copied into dest and the result is null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not be greater than RSIZE_MAX_STR. + * dmax shall not equal zero. + * dmax shall be greater than strnlen_s(src, dmax). + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and destmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpy_s nulls dest. + * + * RETURN VALUE + * a wchar_t pointer to the terminating null at the end of dest + * + * ALSO SEE + * wcscpy_s(), wcscat_s(), wcsncat_s(), wcsncpy_s() + * strcpy_s, strcat_s(), strncat_s(), strncpy_s() + * + */ +wchar_t * +wcpcpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, errno_t *err) +{ + rsize_t orig_dmax; + wchar_t *orig_dest; + const wchar_t *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("wcpcpy_s: dest is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + return NULL; + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcpcpy_s: dmax is 0", + NULL, ESZEROL); + *err = RCNEGATE(ESZEROL); + return NULL; + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcpcpy_s: dmax exceeds max", + NULL, ESLEMAX); + *err = RCNEGATE(ESLEMAX); + return NULL; + } + + if (src == NULL) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to clear data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#else + *dest = L'\0'; +#endif + invoke_safe_str_constraint_handler("wcpcpy_s: src is null", + NULL, ESNULLP); + *err = RCNEGATE(ESNULLP); + return NULL; + } + + if (dest == src) { + /* move dest to the end of the string */ + while (dmax && (*dest != L'\0')) { dmax--; dest++; } + if ( *dest != L'\0' ) { + invoke_safe_str_constraint_handler("wcpcpy_s: no null terminator in dest", + NULL, ESLEMAX); + *err = RCNEGATE(ESLEMAX); + return NULL; + } + *err = RCNEGATE(EOK); + return dest; + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcpcpy_s: overlapping objects", + ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + *err = RCNEGATE(EOK); + return dest; /* successful return */ + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcpcpy_s: overlapping objects", + ESOVRLP); + *err = RCNEGATE(ESOVRLP); + return NULL; + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + *err = RCNEGATE(EOK); + return dest; /* successful return */ + } + + dmax--; + dest++; + src++; + } + } + + /* + * the entire src must have been copied, if not reset dest + * to null the string. + */ + handle_wc_error(orig_dest, orig_dmax, "wcpcpy_s: not enough space for src", + ESNOSPC); + *err = RCNEGATE(ESNOSPC); + return NULL; +} +/* EXPORT_SYMBOL(wcpcpy_s); */ diff --git a/safe_string/wcscat_s.c b/safe_string/wcscat_s.c new file mode 100644 index 000000000000..20165a3963e5 --- /dev/null +++ b/safe_string/wcscat_s.c @@ -0,0 +1,226 @@ +/*------------------------------------------------------------------ + * wcscat_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * wcscat_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * wcscat_s(wchar_t* dest, rsize_t dmax, const wchar_t* src) + * + * DESCRIPTION + * The wcscat_s function appends a copy of the wide characer string pointed + * to by src (including the terminating null character) to the + * end of the string pointed to by dest. The initial wide character + * from src overwrites the null character at the end of dest. + * + * All elements following the terminating null character (if + * any) written by strcat_s in the array of dmax characters + * pointed to by dest take unspecified values when strcat_s + * returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to wide character string that will be extended by src + * if dmax allows. The string is null terminated. + * If the resulting concatenated string is less + * than dmax, the remaining slack space is nulled. + * + * dmax restricted maximum length of the resulting dest, + * including the null + * + * src pointer to the string that will be concatenaed + * to string dest + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer + * dmax shall not equal zero + * dmax shall not be greater than RSIZE_MAX_STR + * dmax shall be greater than strnlen_s(src,m). + * Copying shall not takeplace between objects that overlap + * If there is a runtime-constraint violation, then if dest is + * not a null pointer and dmax is greater than zero and not + * greater than RSIZE_MAX_STR, then strcat_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, all the characters from src + * were appended to dest and the result in dest is + * null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max + * ESUNTERM dest not terminated + * + * ALSO SEE + * strcat_s, strncat_s(), strcpy_s(), strncpy_s() + * + */ +errno_t +wcscat_s(wchar_t* dest, rsize_t dmax, const wchar_t* src) +{ + rsize_t orig_dmax; + wchar_t *orig_dest; + const wchar_t *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("wcscat_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("wcscat_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcscat_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcscat_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + /* Find the end of dest */ + while (*dest != L'\0') { + + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + dest++; + dmax--; + if (dmax == 0) { + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + /* Find the end of dest */ + while (*dest != L'\0') { + + /* + * NOTE: no need to check for overlap here since src comes first + * in memory and we're not incrementing src here. + */ + dest++; + dmax--; + if (dmax == 0) { + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + } + + /* + * the entire src was not copied, so null the string + */ + handle_wc_error(orig_dest, orig_dmax, "wcscat_s: not enough space for src", + ESNOSPC); + + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(wcscat_s); */ diff --git a/safe_string/wcscpy_s.c b/safe_string/wcscpy_s.c new file mode 100644 index 000000000000..20ebe3113dda --- /dev/null +++ b/safe_string/wcscpy_s.c @@ -0,0 +1,207 @@ +/*------------------------------------------------------------------ + * wcscpy_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * wcscpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * wcscpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src) + * + * DESCRIPTION + * The wcscpy_s function copies the wide character string pointed + * to by src (including the terminating null character) into the + * array pointed to by dest. All elements following the terminating + * null character (if any) written by strcpy_s in the array of + * dmax characters pointed to by dest are nulled when + * wcscpy_s returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * + * dmax restricted maximum length of dest + * + * src pointer to the wide character string that will be copied + * to dest + * + * OUTPUT PARAMETERS + * dest updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * dmax shall not be greater than RSIZE_MAX_STR. + * dmax shall not equal zero. + * dmax shall be greater than strnlen_s(src, dmax). + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and destmax is greater than zero and + * not greater than RSIZE_MAX_STR, then strcpy_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, the characters in src were + * copied into dest and the result is null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * ALSO SEE + * strcpy_s, strcat_s(), strncat_s(), strncpy_s() + * wcscat_s(), + * + */ +errno_t +wcscpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src) +{ + rsize_t orig_dmax; + wchar_t *orig_dest; + const wchar_t *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("wcscpy_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcscpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcscpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (src == NULL) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null string to clear data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + invoke_safe_str_constraint_handler("wcscpy_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + /* Verify proper length according to dmax if src = dest */ + if (dest == src) { + /* Ensure that src is not longer than dmax */ + while (*src != L'\0' && (dmax != 0)) { src++; dmax--; } + if ( *src != L'\0' ) { + invoke_safe_str_constraint_handler("wcscpy_s: src exceeds dmax", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + return RCNEGATE(EOK); + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcscpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcscpy_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + dest++; + src++; + } + } + + /* + * the entire src must have been copied, if not reset dest + * to null the string. + */ + handle_wc_error(orig_dest, orig_dmax, "wcscpy_s: not " + "enough space for src", + ESNOSPC); + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(wcscpy_s); */ diff --git a/safe_string/wcsncat_s.c b/safe_string/wcsncat_s.c new file mode 100644 index 000000000000..08e938d15325 --- /dev/null +++ b/safe_string/wcsncat_s.c @@ -0,0 +1,269 @@ +/*------------------------------------------------------------------ + * wcsncat_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * wcsncat_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * wcsncat_s(wchar_t *dest, rsize_t dmax, const wchar_t *src, rsize_t slen) + * + * DESCRIPTION + * The wcsncat_s function appends a copy of (at most) the + * first slen wide characters pointed to by src to the + * end of the string pointed to by dest and terminates the + * string with the null character. If less than slen wide + * characters are in the string src, the function stops + * copying after the null terminator is copied to dest. + * The initial character from src overwrites the null + * character at the end of dest. + * + * All elements following the terminating null character (if + * any) written by strncat_s in the array of dmax characters + * pointed to by dest take unspecified values when strncat_s returns. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be extended by src + * if dmax allows. The string is null terminated. + * If the resulting concatenated string is less + * than dmax, the remaining slack space is nulled. + * + * dmax restricted maximum length of the resulting dest, + * including the null + * + * src pointer to the string that will be concatenaed + * to string dest + * + * slen maximum characters to append + * + * OUTPUT PARAMETERS + * dest updated string + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer + * dmax shall not equal zero + * dmax shall not be greater than RSIZE_STR_MAX + * dmax shall be greater than strnlen_s(src,m). + * Copying shall not takeplace between objects that overlap + * If there is a runtime-constraint violation, then if dest is + * not a null pointer and dmax is greater than zero and not + * greater thanRSIZE_MAX, then strncat_s sets dest[0] to the + * null character. + * + * RETURN VALUE + * EOK successful operation, all the characters from src + * were appended to dest and the result in dest is + * null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESUNTERM dest not terminated + * + * + */ +errno_t +wcsncat_s (wchar_t *dest, rsize_t dmax, const wchar_t *src, rsize_t slen) +{ + rsize_t orig_dmax; + wchar_t *orig_dest; + const wchar_t *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("wcsncat_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (src == NULL) { + invoke_safe_str_constraint_handler("wcsncat_s: src is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (slen*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcsncat_s: slen exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcsncat_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcsncat_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* hold base of dest in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (dest < src) { + overlap_bumper = src; + + /* Find the end of dest */ + while (*dest != L'\0') { + + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + dest++; + dmax--; + if (dmax == 0) { + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: " + "dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + /* + * Copying truncated before the source null is encountered + */ + /* TODO: test if this copies at most slen characters including NULL */ + if (slen == 0) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null remaining string */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#else + *dest = L'\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + /* Find the end of dest */ + while (*dest != L'\0') { + + /* + * NOTE: no need to check for overlap here since src comes first + * in memory and we're not incrementing src here. + */ + dest++; + dmax--; + if (dmax == 0) { + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: " + "dest unterminated", + ESUNTERM); + return RCNEGATE(ESUNTERM); + } + } + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: " + "overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + /* + * Copying truncated + */ + if (slen == 0) { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null remaining string */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#else + *dest = L'\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == L'\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack to clear any data */ + while (dmax) { *dest = L'\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + } + + /* + * the entire src was not copied, so the string will be nulled. + */ + handle_wc_error(orig_dest, orig_dmax, "wcsncat_s: not enough space for src", + ESNOSPC); + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(wcsncat_s); */ diff --git a/safe_string/wcsncpy_s.c b/safe_string/wcsncpy_s.c new file mode 100644 index 000000000000..51df34ac8429 --- /dev/null +++ b/safe_string/wcsncpy_s.c @@ -0,0 +1,241 @@ +/*------------------------------------------------------------------ + * wcsncpy_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/* + * NAME + * wcsncpy_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * errno_t + * wcsncpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, rsize_t slen) + * + * DESCRIPTION + * The wcsncpy_s function copies not more than slen successive characters + * (characters that follow a null character are not copied) from the + * array pointed to by src to the array pointed to by dest. If no null + * character was copied from src, then dest[slen] is set to a null character. + * + * All elements following the terminating null character (if any) + * written by wcsncpy_s in the array of dmax characters pointed to + * by dest take on the null value when wcsncpy_s returns. + * + * When SAFECLIB_STR_NULL_SLACK is defined to be true (#DEFINE), then + * the dest array is filled with NULL characters following the end of + * the last non-NULL character from src. While this is more secure, it + * is also incurs a performance penalty, especially when the same dest + * array is used multiple times to string manipulation routines in this + * library. If this extra security is not required, ensure that the + * library is compiled without #DEFINE SAFECLIB_STR_NULL_SLACK. + * + * Specicified in: + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to string that will be replaced by src. + * The resulting string is null terminated. + * + * dmax restricted maximum length of the resulting dest, + * including the null + * + * src pointer to the string that will be copied + * to string dest + * + * slen the maximum number of characters to copy from src + * + * OUTPUT PARAMETERS + * dest updated with src string + * + * RUNTIME CONSTRAINTS + * Neither dmax nor slen shall be equal to zero. + * Neither dmax nor slen shall be equal zero. + * Neither dmax nor slen shall be greater than RSIZE_MAX_STR. + * If slen is either greater than or equal to dmax, then dmax + * should be more than strnlen_s(src,dmax) + * Copying shall not take place between objects that overlap. + * If there is a runtime-constraint violation, then if dest + * is not a null pointer and dmax greater than RSIZE_MAX_STR, + * then strncpy_s nulls dest. + * + * RETURN VALUE + * EOK successful operation, the characters in src were copied + * to dest and the result is null terminated. + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP strings overlap + * ESNOSPC not enough space to copy src + * + * ALSO SEE + * strcat_s(), strncat_s(), strcpy_s() + * wcscat_s(), wcsncat_s(), wcscpy_s() + *- + */ +errno_t +wcsncpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, rsize_t slen) +{ + rsize_t orig_dmax; + wchar_t *orig_dest; + const wchar_t *overlap_bumper; + + if (dest == NULL) { + invoke_safe_str_constraint_handler("wcsncpy_s: dest is null", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcsncpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcsncpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + /* hold base in case src was not copied */ + orig_dmax = dmax; + orig_dest = dest; + + if (src == NULL) { + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: src is null", + ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (slen == 0) { + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: slen is zero", + ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (slen*sizeof(wchar_t) > RSIZE_MAX_STR) { + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: slen exceeds max", + ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + + if (dest < src) { + overlap_bumper = src; + + while (dmax > 0) { + if (dest == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + if (slen == 0) { + /* + * Copying truncated to slen chars. Note that the TR says to + * copy slen chars plus the null char. We null the slack. + */ +#ifdef SAFECLIB_STR_NULL_SLACK + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + + } else { + overlap_bumper = dest; + + while (dmax > 0) { + if (src == overlap_bumper) { + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: overlapping objects", + ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + if (slen == 0) { + /* + * Copying truncated to slen chars. Note that the TR says to + * copy slen chars plus the null char. We null the slack. + */ +#ifdef SAFECLIB_STR_NULL_SLACK + while (dmax) { *dest = '\0'; dmax--; dest++; } +#else + *dest = '\0'; +#endif + return RCNEGATE(EOK); + } + + *dest = *src; + if (*dest == '\0') { +#ifdef SAFECLIB_STR_NULL_SLACK + /* null slack */ + while (dmax) { *dest = '\0'; dmax--; dest++; } +#endif + return RCNEGATE(EOK); + } + + dmax--; + slen--; + dest++; + src++; + } + } + + /* + * the entire src was not copied, so zero the string + */ + handle_wc_error(orig_dest, orig_dmax, "wcsncpy_s: not enough space for src", + ESNOSPC); + return RCNEGATE(ESNOSPC); +} +/* EXPORT_SYMBOL(wcsncpy_s); */ diff --git a/safe_string/wcsnlen_s.c b/safe_string/wcsnlen_s.c new file mode 100644 index 000000000000..755676167128 --- /dev/null +++ b/safe_string/wcsnlen_s.c @@ -0,0 +1,113 @@ +/*------------------------------------------------------------------ + * wcsnlen_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 by Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_str_constraint.h" +/* #include "safe_str_lib.h" */ + + +/** + * NAME + * wcsnlen_s + * + * SYNOPSIS + * #include "safe_str_lib.h" + * rsize_t + * wcsnlen_s(const wchar_t *dest, rsize_t dmax) + * + * DESCRIPTION + * The wcsnlen_s function computes the length of the wide character string pointed + * to by dest. + * + * SPECIFIED IN + * ISO/IEC TR 24731-1, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to wide character string + * + * dmax restricted maximum length. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer + * dmax shall not be greater than RSIZE_MAX_STR + * dmax shall not equal zero + * + * RETURN VALUE + * The function returns the number of wide characters in the string + * pointed to by dest, excluding the terminating null character. + * If dest is NULL, then wcsnlen_s returns 0. + * + * Otherwise, the wcsnlen_s function returns the number of wide characters + * that precede the terminating null character. If there is no null + * character in the first dmax characters of dest then wcsnlen_s returns + * dmax. At most the first dmax characters of dest are accessed + * by wcsnlen_s. + * + * ALSO SEE + * strnlen_s, strnterminate_s() + * + */ +rsize_t +wcsnlen_s (const wchar_t *dest, rsize_t dmax) +{ + rsize_t count; + + if (dest == NULL) { + return RCNEGATE(0); + } + + if (dmax == 0) { + invoke_safe_str_constraint_handler("wcsnlen_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(0); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_STR) { + invoke_safe_str_constraint_handler("wcsnlen_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(0); + } + + count = 0; + while (*dest && dmax) { + count++; + dmax--; + dest++; + } + + return RCNEGATE(count); +} +/* EXPORT_SYMBOL(wcsnlen_s); */ diff --git a/safe_string/wmemcmp_s.c b/safe_string/wmemcmp_s.c new file mode 100644 index 000000000000..6632f46ddcb1 --- /dev/null +++ b/safe_string/wmemcmp_s.c @@ -0,0 +1,169 @@ +/*------------------------------------------------------------------ + * wmemcmp_s.c - Compares memory + * + * September 2014, D. Wheeler + * + * Copyright (c) 2014 Intel Corp + * All rights reserved. + * + * Based on memcmp32_s.c, October 2008, by Bo Berry + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +/* #include "safe_mem_lib.h" */ + +/** + * NAME + * wmemcmp_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * wmemcmp_s(const wchar_t *dest, rsize_t dmax, + * const wchar_t *src, rsize_t smax, int *diff) + * + * DESCRIPTION + * Compares wide-character strings until they differ, and their difference is + * returned in diff. If the wide character string is the same, diff=0. + * + * EXTENSION TO + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory to compare against + * + * dmax maximum length of dest, in uint32_t + * + * src pointer to the source memory to compare with dest + * + * smax maximum length of src, in uint32_t + * + * *diff pointer to the diff which is an integer greater + * than, equal to or less than zero according to + * whether the object pointed to by dest is + * greater than, equal to or less than the object + * pointed to by src. + * + * OUTPUT PARAMETERS + * none + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memcmp_s(), memcmp16_s() + * + */ +errno_t +wmemcmp_s (const wchar_t *dest, rsize_t dmax, + const wchar_t *src, rsize_t smax, int *diff) +{ + /* + * must be able to return the diff + */ + if (diff == NULL) { + invoke_safe_mem_constraint_handler("wmemcmp_s: diff is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + *diff = -1; /* default diff */ + + + if (dest == NULL) { + invoke_safe_mem_constraint_handler("wmemcmp_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (src == NULL) { + invoke_safe_mem_constraint_handler("wmemcmp_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("wmemcmp_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax > RSIZE_MAX_MEM32) { + invoke_safe_mem_constraint_handler("wmemcmp_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + invoke_safe_mem_constraint_handler("wmemcmp_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + invoke_safe_mem_constraint_handler("wmemcmp_s: smax exceeds dmax", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + /* + * no need to compare the same memory + */ + if (dest == src) { + *diff = 0; + return (RCNEGATE(EOK)); + } + + /* + * now compare src to dest + */ + *diff = 0; + while (dmax != 0 && smax != 0) { + if (*dest != *src) { + *diff = *dest - *src; + break; + } + + dmax--; + smax--; + + dest++; + src++; + } + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(wmemcmp_s); */ diff --git a/safe_string/wmemcpy_s.c b/safe_string/wmemcpy_s.c new file mode 100644 index 000000000000..be6d5352646e --- /dev/null +++ b/safe_string/wmemcpy_s.c @@ -0,0 +1,158 @@ +/*------------------------------------------------------------------ + * wmemcpy_s + * + * AUgust 2014, D. Wheeler + * + * Copyright (c) 2014 Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ +#include + + +/** + * NAME + * wmemcpy_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * wmemcpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, rsize_t smax) + * + * DESCRIPTION + * This function copies at most smax wide characters from src to dest, up to + * dmax. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be replaced by src. + * + * dmax maximum length of the resulting dest + * + * src pointer to the memory that will be copied to dest + * + * smax maximum number bytes of src to copy + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be zero. + * dmax shall not be greater than RSIZE_MAX_MEM. + * smax shall not be greater than dmax. + * Copying shall not take place between regions that overlap. + * If there is a runtime-constraint violation, the memcpy_s function + * stores zeros in the first dmax bytes of the region pointed to + * by dest if dest is not a null pointer and smax is valid. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * ESOVRLP source memory overlaps destination + * + * ALSO SEE + * memcpy16_s(), memcpy32_s(), memcpy_s(), + * wmemmove_s(), memmove_s(), memmove16_s(), memmove32_s(), + * + */ +errno_t +wmemcpy_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, rsize_t smax) +{ + wchar_t *dp; + const wchar_t *sp; + + dp = dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("wmemcpy_s: dest is NULL", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("wmemcpy_s: dmax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (dmax > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("wmemcpy_s: dmax exceeds max", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (smax == 0) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemcpy_s: smax is 0", + NULL, ESZEROL); + return RCNEGATE(ESZEROL); + } + + if (smax > dmax) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemcpy_s: smax exceeds dmax", + NULL, ESLEMAX); + return RCNEGATE(ESLEMAX); + } + + if (sp == NULL) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemcpy_s: src is NULL", + NULL, ESNULLP); + return RCNEGATE(ESNULLP); + } + + + /* + * overlap is undefined behavior, do not allow + */ + if( ((dp > sp) && (dp < (sp+smax))) || + ((sp > dp) && (sp < (dp+dmax))) ) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemcpy_s: overlap undefined", + NULL, ESOVRLP); + return RCNEGATE(ESOVRLP); + } + + /* + * now perform the copy + */ + mem_prim_move(dp, sp, smax*sizeof(wchar_t)); + + return RCNEGATE(EOK); +} +/* EXPORT_SYMBOL(wmemcpy_s); */ diff --git a/safe_string/wmemmove_s.c b/safe_string/wmemmove_s.c new file mode 100644 index 000000000000..8ec91db08806 --- /dev/null +++ b/safe_string/wmemmove_s.c @@ -0,0 +1,150 @@ +/*------------------------------------------------------------------ + * wmemmove_s.c + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ +#include + +/** + * NAME + * wmemmove_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * wmemmove_s(wchar_t* dest, rsize_t dmax, + * const wchar_t* src, size_t smax) + * + * DESCRIPTION + * The wmemmove_s function copies smax wide characters from the region pointed + * to by src into the region pointed to by dest. This copying takes place + * as if the smax wide characters from the region pointed to by src are first copied + * into a temporary array of smax bytes that does not overlap the region + * pointed to by dest or src, and then the smax bytes from the temporary + * array are copied into the object region to by dest. + * + * SPECIFIED IN + * ISO/IEC TR 24731, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to the memory that will be replaced by src. + * + * dmax maximum number of resulting wide characters in dest + * + * src pointer to the memory that will be copied + * to dest + * + * smax maximum number wide characters of src that can be copied + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * Neither dest nor src shall be a null pointer. + * Neither dmax nor smax shall be 0. + * dmax shall not be greater than RSIZE_MAX_MEM/sizeof(wchar_t). + * smax shall not be greater than dmax. + * If there is a runtime-constraint violation, the wmemmove_s function + * stores zeros in the first dmax characters of the region pointed to + * by dest if dest is not a null pointer and dmax is not greater + * than RSIZE_MAX_MEM/sizeof(wchar_t). + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memmove16_s(), memmove32_s(), memcpy_s(), memcpy16_s() memcpy32_s() + * wmemcpy_s() + * + */ +errno_t +wmemmove_s(wchar_t* dest, rsize_t dmax, const wchar_t* src, size_t smax) +{ + wchar_t *dp; + const wchar_t *sp; + + dp= dest; + sp = src; + + if (dp == NULL) { + invoke_safe_mem_constraint_handler("wmemmove_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (dmax == 0) { + invoke_safe_mem_constraint_handler("wmemmove_s: dmax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (dmax*sizeof(wchar_t) > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("wmemmove_s: dmax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (smax == 0) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemmove_s: smax is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (smax > dmax) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemmove_s: smax exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + if (sp == NULL) { + mem_prim_set(dp, dmax*sizeof(wchar_t), 0); + invoke_safe_mem_constraint_handler("wmemmove_s: src is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + /* + * now perform the copy + */ + mem_prim_move(dp, sp, smax*sizeof(wchar_t)); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(wmemmove_s); */ diff --git a/safe_string/wmemset_s.c b/safe_string/wmemset_s.c new file mode 100644 index 000000000000..d2ddf82bd07f --- /dev/null +++ b/safe_string/wmemset_s.c @@ -0,0 +1,105 @@ +/*------------------------------------------------------------------ + * wmemset_s + * + * August 2014, D Wheeler + * + * Copyright (c) 2014 Intel Corp + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + *------------------------------------------------------------------ + */ + +#include "safeclib_private.h" +#include "safe_mem_constraint.h" +#include "mem_primitives_lib.h" +/* #include "safe_mem_lib.h" */ + + +/** + * NAME + * wmemset_s + * + * SYNOPSIS + * #include "safe_mem_lib.h" + * errno_t + * wmemset_s(wchar_t *dest, wchar_t value, rsize_t len) + * + * DESCRIPTION + * Sets len number of wide characters starting at dest to the specified value. + * + * SPECIFIED IN + * ISO/IEC JTC1 SC22 WG14 N1172, Programming languages, environments + * and system software interfaces, Extensions to the C Library, + * Part I: Bounds-checking interfaces + * + * INPUT PARAMETERS + * dest pointer to memory that will be set to the value + * + * value byte value + * + * len number of wide characters to be set + * + * OUTPUT PARAMETERS + * dest is updated + * + * RUNTIME CONSTRAINTS + * dest shall not be a null pointer. + * len shall not be 0 nor greater than RSIZE_MAX_MEM/sizeof(wchar_t). + * If there is a runtime constraint, the operation is not performed. + * + * RETURN VALUE + * EOK successful operation + * ESNULLP NULL pointer + * ESZEROL zero length + * ESLEMAX length exceeds max limit + * + * ALSO SEE + * memset_s, memset16_s(), memset32_s() + * + */ +errno_t +wmemset_s (wchar_t *dest, wchar_t value, rsize_t len) +{ + if (dest == NULL) { + invoke_safe_mem_constraint_handler("wmemset_s: dest is null", + NULL, ESNULLP); + return (RCNEGATE(ESNULLP)); + } + + if (len == 0) { + invoke_safe_mem_constraint_handler("wmemset_s: len is 0", + NULL, ESZEROL); + return (RCNEGATE(ESZEROL)); + } + + if (len*sizeof(wchar_t) > RSIZE_MAX_MEM) { + invoke_safe_mem_constraint_handler("wmemset_s: len exceeds max", + NULL, ESLEMAX); + return (RCNEGATE(ESLEMAX)); + } + + mem_prim_set32(dest, len, value); + + return (RCNEGATE(EOK)); +} +/* EXPORT_SYMBOL(wmemset_s); */ diff --git a/samples/CMakeLists.txt b/samples/CMakeLists.txt new file mode 100644 index 000000000000..aa0967b4295a --- /dev/null +++ b/samples/CMakeLists.txt @@ -0,0 +1,40 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +include_directories(${OPAE_INCLUDE_DIR}) + +set(CMAKE_C_FLAGS "-std=gnu99 ${CMAKE_C_FLAGS}") + +find_package(UUID REQUIRED) + +add_executable(hello_fpga hello_fpga.c) +target_link_libraries(hello_fpga json-c uuid ${CMAKE_THREAD_LIBS_INIT} opae-c) + +set(SAMPLES_SRC hello_fpga.c) + +install(FILES ${SAMPLES_SRC} + DESTINATION src/opae + COMPONENT samplesrc) diff --git a/samples/hello_fpga.c b/samples/hello_fpga.c new file mode 100644 index 000000000000..8fab0f7d658a --- /dev/null +++ b/samples/hello_fpga.c @@ -0,0 +1,275 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#include +#include +#include +#include +#include +#include +#include + +int usleep(unsigned); + +#ifndef CL +# define CL(x) ((x) * 64) +#endif // CL +#ifndef LOG2_CL +# define LOG2_CL 6 +#endif // LOG2_CL +#ifndef MB +# define MB(x) ((x) * 1024 * 1024) +#endif // MB + +#define CACHELINE_ALIGNED_ADDR(p) ((p) >> LOG2_CL) + +#define LPBK1_BUFFER_SIZE MB(1) +#define LPBK1_BUFFER_ALLOCATION_SIZE MB(2) +#define LPBK1_DSM_SIZE MB(2) +#define CSR_SRC_ADDR 0x0120 +#define CSR_DST_ADDR 0x0128 +#define CSR_CTL 0x0138 +#define CSR_CFG 0x0140 +#define CSR_NUM_LINES 0x0130 +#define DSM_STATUS_TEST_COMPLETE 0x40 +#define CSR_AFU_DSM_BASEL 0x0110 +#define CSR_AFU_DSM_BASEH 0x0114 + +/* NLB0 AFU_ID */ +#define NLB0_AFUID "D8424DC4-A4A3-C413-F89E-433683F9040B" + +/* + * macro to check return codes, print error message, and goto cleanup label + * NOTE: this changes the program flow (uses goto)! + */ +#define ON_ERR_GOTO(res, label, desc) \ + do { \ + if ((res) != FPGA_OK) { \ + print_err((desc), (res)); \ + goto label; \ + } \ + } while (0) + +/* Type definitions */ +typedef struct { + uint32_t uint[16]; +} cache_line; + +void print_err(const char *s, fpga_result res) +{ + fprintf(stderr, "Error %s: %s\n", s, fpgaErrStr(res)); +} + +int main(int argc, char *argv[]) +{ + fpga_properties filter = NULL; + fpga_token accelerator_token; + fpga_handle accelerator_handle; + fpga_guid guid; + uint32_t num_matches; + + volatile uint64_t *dsm_ptr = NULL; + volatile uint64_t *status_ptr = NULL; + volatile uint64_t *input_ptr = NULL; + volatile uint64_t *output_ptr = NULL; + + uint64_t dsm_wsid; + uint64_t input_wsid; + uint64_t output_wsid; + fpga_result res = FPGA_OK; + + int opt; + int open_flags = 0; + + /* Parse command line for exclusive or shared access */ + while ((opt = getopt(argc, argv, "s")) != -1) { + switch (opt) { + case 's': + open_flags |= FPGA_OPEN_SHARED; + break; + default: + printf("USAGE: %s [-s]\n", argv[0]); + exit(1); + } + } + + if (uuid_parse(NLB0_AFUID, guid) < 0) { + fprintf(stderr, "Error parsing guid '%s'\n", NLB0_AFUID); + goto out_exit; + } + + /* Look for accelerator with MY_ACCELERATOR_ID */ + res = fpgaGetProperties(NULL, &filter); + ON_ERR_GOTO(res, out_exit, "creating properties object"); + + res = fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); + ON_ERR_GOTO(res, out_destroy_prop, "setting object type"); + + res = fpgaPropertiesSetGUID(filter, guid); + ON_ERR_GOTO(res, out_destroy_prop, "setting GUID"); + + /* TODO: Add selection via BDF / device ID */ + + res = fpgaEnumerate(&filter, 1, &accelerator_token, 1, &num_matches); + ON_ERR_GOTO(res, out_destroy_prop, "enumerating accelerators"); + + if (num_matches < 1) { + fprintf(stderr, "accelerator not found.\n"); + res = fpgaDestroyProperties(&filter); + return FPGA_INVALID_PARAM; + } + + /* Open accelerator and map MMIO */ + res = fpgaOpen(accelerator_token, &accelerator_handle, open_flags); + ON_ERR_GOTO(res, out_destroy_tok, "opening accelerator"); + + res = fpgaMapMMIO(accelerator_handle, 0, NULL); + ON_ERR_GOTO(res, out_close, "mapping MMIO space"); + + /* Allocate buffers */ + res = fpgaPrepareBuffer(accelerator_handle, LPBK1_DSM_SIZE, + (void **)&dsm_ptr, &dsm_wsid, 0); + ON_ERR_GOTO(res, out_close, "allocating DSM buffer"); + + res = fpgaPrepareBuffer(accelerator_handle, LPBK1_BUFFER_ALLOCATION_SIZE, + (void **)&input_ptr, &input_wsid, 0); + ON_ERR_GOTO(res, out_free_dsm, "allocating input buffer"); + + res = fpgaPrepareBuffer(accelerator_handle, LPBK1_BUFFER_ALLOCATION_SIZE, + (void **)&output_ptr, &output_wsid, 0); + ON_ERR_GOTO(res, out_free_input, "allocating output buffer"); + + printf("Running Test\n"); + + /* Initialize buffers */ + memset((void *)dsm_ptr, 0, LPBK1_DSM_SIZE); + memset((void *)input_ptr, 0xAF, LPBK1_BUFFER_SIZE); + memset((void *)output_ptr, 0xBE, LPBK1_BUFFER_SIZE); + + cache_line *cl_ptr = (cache_line *)input_ptr; + for (uint32_t i = 0; i < LPBK1_BUFFER_SIZE / CL(1); ++i) { + cl_ptr[i].uint[15] = i+1; /* set the last uint in every cacheline */ + } + + /* Reset accelerator */ + res = fpgaReset(accelerator_handle); + ON_ERR_GOTO(res, out_free_output, "resetting accelerator"); + + /* Program DMA addresses */ + uint64_t iova; + res = fpgaGetIOAddress(accelerator_handle, dsm_wsid, &iova); + ON_ERR_GOTO(res, out_free_output, "getting DSM IOVA"); + + res = fpgaWriteMMIO64(accelerator_handle, 0, CSR_AFU_DSM_BASEL, iova); + ON_ERR_GOTO(res, out_free_output, "writing CSR_AFU_DSM_BASEL"); + + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_CTL, 0); + ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG"); + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_CTL, 1); + ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG"); + + res = fpgaGetIOAddress(accelerator_handle, input_wsid, &iova); + ON_ERR_GOTO(res, out_free_output, "getting input IOVA"); + res = fpgaWriteMMIO64(accelerator_handle, 0, CSR_SRC_ADDR, CACHELINE_ALIGNED_ADDR(iova)); + ON_ERR_GOTO(res, out_free_output, "writing CSR_SRC_ADDR"); + + res = fpgaGetIOAddress(accelerator_handle, output_wsid, &iova); + ON_ERR_GOTO(res, out_free_output, "getting output IOVA"); + res = fpgaWriteMMIO64(accelerator_handle, 0, CSR_DST_ADDR, CACHELINE_ALIGNED_ADDR(iova)); + ON_ERR_GOTO(res, out_free_output, "writing CSR_DST_ADDR"); + //fpgaProgramBufferAddressAndLength(accelerator_handle, dsm_wsid, 0, LPBK1_DSM_SIZE, + // CSR_AFU_DSM_BASEL); + //fpgaProgramBufferAddressAndLength(accelerator_handle, input_wsid, 0, LPBK1_BUFFER_SIZE, + // CSR_SRC_ADDR); + //fpgaProgramBufferAddressAndLength(accelerator_handle, output_wsid, 0, LPBK1_BUFFER_SIZE, + // CSR_DST_ADDR); + + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_NUM_LINES, LPBK1_BUFFER_SIZE / CL(1)); + ON_ERR_GOTO(res, out_free_output, "writing CSR_NUM_LINES"); + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_CFG, 0x42000); + ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG"); + + status_ptr = dsm_ptr + DSM_STATUS_TEST_COMPLETE/8; + + /* Start the test */ + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_CTL, 3); + ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG"); + + /* Wait for test completion */ + while (0 == ((*status_ptr) & 0x1)) { + usleep(100); + } + + /* Stop the device */ + res = fpgaWriteMMIO32(accelerator_handle, 0, CSR_CTL, 7); + ON_ERR_GOTO(res, out_free_output, "writing CSR_CFG"); + + /* Check output buffer contents */ + for (uint32_t i = 0; i < LPBK1_BUFFER_SIZE; i++) { + if (((uint8_t *)output_ptr)[i] != ((uint8_t *)input_ptr)[i]) { + fprintf(stderr, "Output does NOT match input " + "at offset %i!\n", i); + break; + } + } + + printf("Done Running Test\n"); + + /* Release buffers */ +out_free_output: + res = fpgaReleaseBuffer(accelerator_handle, output_wsid); + ON_ERR_GOTO(res, out_free_input, "releasing output buffer"); +out_free_input: + res = fpgaReleaseBuffer(accelerator_handle, input_wsid); + ON_ERR_GOTO(res, out_free_dsm, "releasing input buffer"); +out_free_dsm: + res = fpgaReleaseBuffer(accelerator_handle, dsm_wsid); + ON_ERR_GOTO(res, out_unmap, "releasing DSM buffer"); + + /* Unmap MMIO space */ +out_unmap: + res = fpgaUnmapMMIO(accelerator_handle, 0); + ON_ERR_GOTO(res, out_close, "unmapping MMIO space"); + + /* Release accelerator */ +out_close: + res = fpgaClose(accelerator_handle); + ON_ERR_GOTO(res, out_destroy_tok, "closing accelerator"); + + /* Destroy token */ +out_destroy_tok: + res = fpgaDestroyToken(&accelerator_token); + ON_ERR_GOTO(res, out_destroy_prop, "destroying token"); + + /* Destroy properties object */ +out_destroy_prop: + res = fpgaDestroyProperties(&filter); + ON_ERR_GOTO(res, out_exit, "destroying properties object"); + +out_exit: + return res; + +} diff --git a/tools/c++utils/CMakeLists.txt b/tools/c++utils/CMakeLists.txt new file mode 100644 index 000000000000..41f61ec22943 --- /dev/null +++ b/tools/c++utils/CMakeLists.txt @@ -0,0 +1,58 @@ +## Copyright(c) 2017, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +find_package(Boost 1.41.0 REQUIRED) +find_library(CJSON_LIBRARY json-c) + +include_directories( + ${Boost_INCLUDE_DIRS} + ) + +add_library(opae-c++-utils SHARED + utils.h + utils.cpp + process.h + process.cpp + cmd_handler.h + cmd_handler.cpp + log.h + log.cpp + option.h + option_map.h + option_map.cpp + option_parser.h + option_parser.cpp) + +set_install_rpath(opae-c++-utils) +set_target_properties(opae-c++-utils PROPERTIES COMPILE_FLAGS "-std=c++11") +set_target_properties(opae-c++-utils PROPERTIES + VERSION ${INTEL_FPGA_API_VERSION} + SOVERSION ${INTEL_FPGA_API_VER_MAJOR}) + +target_link_libraries(opae-c++-utils ${CJSON_LIBRARY}) + +install(TARGETS opae-c++-utils + LIBRARY DESTINATION lib + COMPONENT opaecxxutils) diff --git a/tools/c++utils/cmd_handler.cpp b/tools/c++utils/cmd_handler.cpp new file mode 100644 index 000000000000..a43801c95a63 --- /dev/null +++ b/tools/c++utils/cmd_handler.cpp @@ -0,0 +1,324 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#include "cmd_handler.h" +#include +#include +#include +#include +#include "utils.h" +#include +#include +#include + +using namespace std::placeholders; + +namespace intel +{ +namespace utils +{ + +bool cmd_handler::go_history(history direction, std::string & line) +{ + if (direction == direction_none) + { + return false; + } + + if (direction == direction_back) + { + if (history_iter_ == history_.begin()) + { + return false; + } + history_iter_--; + line = *history_iter_; + return true; + } + else + { + if (history_iter_ < history_.end()) + { + history_iter_++; + if (history_iter_ < history_.end()) + { + line = *history_iter_; + return true; + } + } + } + return false; +} + +std::string cmd_handler::readline(const std::string & prompt) +{ + char c; + char arrow[2]; + + const char del[] = "\b \b"; + auto clear_line = [del](int count) + { + for (int i = 0; i < count; i++) + { + if (write(STDOUT_FILENO, &del, 3) < 0) + { + std::cerr << "write: " << strerror(errno) << std::endl; + } + } + }; + history_iter_ = history_.end(); + std::string line, word; + struct termios tty, tty_change; + tcgetattr(STDIN_FILENO, &tty); + tty_change = tty; + tty_change.c_lflag &= ~ICANON; + tty_change.c_lflag &= ~ECHO; + + tcsetattr(STDIN_FILENO, TCSAFLUSH, &tty_change); + if (write(STDOUT_FILENO, prompt.data(), prompt.size()) < 0) + { + std::cerr << "write: " << strerror(errno) << std::endl; + } + auto dir = direction_none; + size_t current_size = 0; + std::string value; + while(true) + { + if (read(STDIN_FILENO, &c, 1) < 0) + { + std::cerr << "read: " << strerror(errno) << std::endl; + } + if (std::iscntrl(c)) + { + switch(c) + { + case '\033': + current_size = line.size(); + // eat the rest of the input + if (read(STDIN_FILENO, &arrow, 2) < 0) + { + std::cerr << "read: " << strerror(errno) << std::endl; + } + if (arrow[1] == 'A') + { + dir = direction_back; + } + else if (arrow[1] == 'B') + { + dir = direction_forward; + } + if (dir != direction_none && go_history(dir, line)) + { + clear_line(current_size); + if (write(STDOUT_FILENO, line.data(), line.size()) < 0) + { + std::cerr << "write: " << strerror(errno) << std::endl; + } + dir = direction_none; + current_size = 0; + } + break; + case '\n': + tcsetattr(STDIN_FILENO, TCSANOW, &tty); + std::cout << std::endl; + if (line.empty() && !history_.empty()) + { + value = history_.back(); + } + else + { + value = rtrim(ltrim(line)); + } + + if (log_.is_open()) + { + log_ << prompt << value << std::endl; + } + return value; + case '\b': + case 127: + if (!line.empty()) + { + line.erase(line.end()-1, line.end()); + if (write(STDOUT_FILENO, &del, 3) < 0) + { + std::cerr << "write: " << strerror(errno) << std::endl; + } + } + break; + case '\t': + // TODO : tab complete + break; + } + } + else + { + if (write(STDOUT_FILENO, &c, 1) < 0) + { + std::cerr << "write: " << strerror(errno) << std::endl; + } + if (std::iswspace(c)) + { + if (!word.empty()) + { + word.clear(); + } + } + else + { + word.push_back(c); + } + line.push_back(c); + } + } +} + + +cmd_handler::cmd_handler() +{ + register_handler("help", + std::bind(&cmd_handler::do_help, this, _1), + 0, + "show help message"); +} + +cmd_handler::~cmd_handler() +{ +} + +bool cmd_handler::do_help(const cmd_vector_t & cmd) +{ + if (cmd.size() == 0) + { + for(const auto & v : verbs_) + { + std::cerr << std::setw(16) << v << " - " << help_[v].second << std::endl; + } + } + else + { + auto it = help_.find(cmd[0]); + if (cmd.size() == 1 && it != help_.end()) + { + std::cerr << std::setw(16) << it->first << " - " << it->second.second << std::endl; + } + else + { + std::cerr << "Unrecognized command: " << cmd[0] << std::endl; + } + } + return true; +} + +void cmd_handler::register_handler( const std::string & verb, + cmd_func_t func, + uint16_t arg_count, + const std::string & help) +{ + handlers_[verb] = func; + help_[verb] = std::make_pair(arg_count, help); + if (std::find(verbs_.begin(), verbs_.end(), verb) == verbs_.end()) + { + verbs_.push_back(verb); + } +} + +bool cmd_handler::do_cmd(const cmd_vector_t & cmd, std::string & help) +{ + if (cmd.size() == 0) + { + return false; + } + + const std::string & verb = cmd[0]; + auto it1 = handlers_.find(verb); + auto it2 = help_.find(verb); + if (it1 != handlers_.end() && it2 != help_.end()) + { + help = it2->second.second; + + if (cmd.size() < it2->second.first) + { + return false; + } + else + { + return it1->second(cmd_vector_t(cmd.begin()+1, cmd.end())); + } + } + return false; +} + +void cmd_handler::run_command_loop(const std::string & prompt) +{ + bool run = true; + register_handler("quit", + [&run](const cmd_vector_t & cmd) + { + run = false; + return true; + }, 0, "quit this program"); + + std::string line; + + while (run) + { + char c; + line = readline("\n>"); + if (line.empty()) + { + continue; + } + auto splits = split(line, ' '); + if (splits.size() > 0) + { + const std::string & verb = splits[0]; + if (have_cmd(verb)) + { + std::string help; + if (!do_cmd(splits, help)) + { + std::cerr << help << std::endl; + } + else + { + add_history(line); + } + } + else + { + std::cerr << "Unrecognized command: " << verb << std::endl; + } + } + } +} + +void cmd_handler::add_history(const std::string & line) +{ + history_.push_back(line); +} + +} // end of namespace utils +} // end of namespace intel diff --git a/tools/c++utils/cmd_handler.h b/tools/c++utils/cmd_handler.h new file mode 100644 index 000000000000..c810a09db1d6 --- /dev/null +++ b/tools/c++utils/cmd_handler.h @@ -0,0 +1,142 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#pragma once +#include +#include +#include +#include +#include +#include + +namespace intel +{ +namespace utils +{ + +class cmd_handler +{ +public: + typedef std::vector cmd_vector_t; + typedef std::function cmd_func_t; + enum history + { + direction_none = 0, + direction_back, + direction_forward + }; + + cmd_handler(); + ~cmd_handler(); + + /// @brief Register a command function with a command verb + /// + /// @param[in] verb The command verb + /// @param[in] func The command function that processes the verb + /// @param[in] arg_count The minimum number of arguments required for the command + /// @param[in] help Help string to print out if help is requested + void register_handler(const std::string & verb, + cmd_func_t func, + uint16_t arg_count, + const std::string & help); + + /// @brief Call the command function associated with a command + /// + /// @param[in] cmd A vector of strings. The first word is the command verb + /// @param[out] help Help string associated with verb. This is set when the cmd + /// vector isn't long enough. + /// + /// @return true if able to successfully run the command, false otherwise + bool do_cmd(const cmd_vector_t & cmd, std::string & help); + + /// @brief Check if command has a registered handler + /// + /// @param cmd The command verb to check for + /// + /// @return true if a handler is registered for the verb, falase otherwise + bool have_cmd(const std::string & cmd) + { + return cmd.size() > 0 && handlers_.find(cmd) != handlers_.end(); + } + + bool do_help(const cmd_vector_t & cmd); + std::string readline(const std::string & prompt); + + template + void writeline(Types ... args) + { + writeline_(std::forward(args)...); + } + + template + void writeline_(Front f, Tail ... tail) + { + std::cout << f; + if (log_.is_open()) + { + log_ << f; + } + + writeline(std::forward(tail)...); + } + + void writeline() + { + std::cout << std::endl; + if (log_.is_open()) + { + log_ << std::endl; + } + } + void log(const std::string & filename) + { + if (log_.is_open()) + { + log_.close(); + } + + log_.open(filename, std::fstream::out); + if (!log_.is_open()) + { + std::cerr << "ERROR opening file " << filename << std::endl; + } + } + + void run_command_loop(const std::string & prompt); + void add_history(const std::string & line); +private: + bool go_history(history direction, std::string & line); + typedef std::map handler_map_t; + typedef std::map> cmd_help_map_t; + std::fstream log_; + handler_map_t handlers_; + cmd_help_map_t help_; + std::vector verbs_; + std::vector history_; + std::vector::iterator history_iter_; +}; + +} // end of namespace utils +} // end of namespace intel diff --git a/tools/c++utils/log.cpp b/tools/c++utils/log.cpp new file mode 100644 index 000000000000..a8dc9ab78adc --- /dev/null +++ b/tools/c++utils/log.cpp @@ -0,0 +1,130 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#include "log.h" +#include +#include + +namespace intel +{ +namespace utils +{ + +logger::logger(const std::string & filename) + : log_(0) + , null_stream_(0) + , level_(level::level_none) +{ + filestream_.open(filename); + if (filestream_.is_open()) + { + log_ = &filestream_; + } + pid_ = ::getpid(); +} + +logger::logger(std::ostream & stream) + : log_(&stream) + , null_stream_(0) + , level_(level::level_none) +{ + pid_ = ::getpid(); +} + + +std::ostream & logger::log(level l, std::string str) +{ + auto & stream = l >= level_ && log_ ? *log_ : null_stream_; + stream << "[" << pid_ << "][" << level_name(l) << "]"; + if (str != "") + { + stream << "[" << str << "]"; + } + stream << std::boolalpha; + + return stream; +} + +void logger::set_level(level l) +{ + level_ = l; +} + +logger::level logger::get_level() +{ + return level_; +} + +std::string logger::get_level_name() +{ + return level_name(get_level()); +} + +std::string logger::level_name(level l) +{ + static std::map level_map = + { + {level::level_none, "NONE"}, + {level::level_debug, "DEBUG"}, + {level::level_info, "INFO"}, + {level::level_warn, "WARN"}, + {level::level_error, "ERROR"}, + {level::level_exception, "EXCEPTION"}, + {level::level_fatal, "FATAL"} + }; + return level_map[l]; +} + + +std::ostream & logger::debug(std::string str) +{ + return log(level::level_debug, str); +} + +std::ostream & logger::info(std::string str) +{ + return log(level::level_info, str); +} + +std::ostream & logger::warn(std::string str) +{ + return log(level::level_warn, str); +} + +std::ostream & logger::error(std::string str) +{ + return log(level::level_error, str); +} +std::ostream & logger::exception(std::string str) +{ + return log(level::level_exception, str); +} +std::ostream & logger::fatal(std::string str) +{ + return log(level::level_fatal, str); +} + +} // end of namespace utils +} // end of namespace intel diff --git a/tools/c++utils/log.h b/tools/c++utils/log.h new file mode 100644 index 000000000000..a0effe8099ce --- /dev/null +++ b/tools/c++utils/log.h @@ -0,0 +1,84 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#pragma once +#include +#include +#include +#include + +namespace intel +{ +namespace utils +{ + +class logger +{ +public : + enum level + { + level_none = 0, + level_debug = 10, + level_info = 20, + level_warn = 30, + level_error = 40, + level_exception = 50, + level_fatal = 60 + }; + + logger(const std::string & filename); + logger(std::ostream & stream = std::cout); + + virtual ~logger() + { + } + + + std::ostream & log(level l, std::string str = ""); + std::ostream & debug(std::string str = ""); + std::ostream & info(std::string str = ""); + std::ostream & warn(std::string str = ""); + std::ostream & error(std::string str= ""); + std::ostream & exception(std::string str = ""); + std::ostream & fatal(std::string str = ""); + + void set_level(level l); + + level get_level(); + + std::string get_level_name(); + + std::string level_name(level l); + +private: + std::ostream *log_; + std::ostream null_stream_; + std::ofstream filestream_; + int pid_; + level level_; +}; + +} // end of namespace utils +} // end of namespace intel diff --git a/tools/c++utils/option.h b/tools/c++utils/option.h new file mode 100644 index 000000000000..37aab7dbe13d --- /dev/null +++ b/tools/c++utils/option.h @@ -0,0 +1,198 @@ +// Copyright(c) 2017, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +#pragma once +#include +#include +#include +#include + +namespace intel +{ +namespace utils +{ + + + +/// @brief option is a base class to hold any value with an expected value type +/// It is intended to be used for command line parsing as well as JSON parsing +class option +{ +public: + typedef std::shared_ptr