testrun monday

Author: ThorKn

Chapter_01_Introduction/c01_lecture.md

@@ -17,6 +17,10 @@ toc: true
 
 ## Welcome
 
+### The next 5 days
+
+- A few words to start with.
+
 ### Trainer profile
 
 Me:
@@ -334,6 +338,19 @@ We will explain live about the certificate of the course.
 
 ## Open-source EDA for digital designs
 
+### Digital designs
+
+There are:
+
+- **Digital designs** This course!
+- Analog designs (Upcoming course)
+- Mixed signal designs
+- Artwork designs (i.e. Minimal Fab Contest)
+    * [https://github.com/mineda-support/Semicon2023-MinimalFab-Design-Contest](https://github.com/mineda-support/Semicon2023-MinimalFab-Design-Contest)
+- Your fancy design?
+
+**From now on: This course means digital design, even if not mentioned everywhere again**
+
 ### From design to microchip
 ![](pics_lecture/rtl_to_gds.png)
 
@@ -434,7 +451,7 @@ Andrews news page with the link (scroll to june 2024)
 
 - The following slides contain some works that were made with open-source EDA tools and open-source PDKs. 
 - Most of this would not have been possible in closed source (because of NDAs)
-- Open-source EDA drives people to experiemnt and play with the technology.
+- Open-source EDA drives people to experiement and play with the technology.
 
 ###
 ![3d cell parts [^3]](pics_lecture/pics_os/cells_3dprint_1.png)

Chapter_01_Introduction/c01_summary.md

@@ -24,17 +24,21 @@ toc: true
 ## Do the siliwiz lessons
 
 - Doing the siliwiz lessons helps a lot to learn more about semiconductors in general.
-- In the course chapter about the open-source PDK the knowledge from Siliwiz will definatly be helpful for deeper understanding.
+- In the course chapter about the open-source PDK the knowledge from Siliwiz will definitely be helpful for deeper understanding.
 - If you want to go into analog circuit design, this might be a good start too.
 
-Here you go (Link to lesson is upper left corner):
+##### Task: Start doing the SiliWiz lessons
 
-[https://app.siliwiz.com/](https://app.siliwiz.com/)
+- Here you go (Link to lesson is upper left corner):
+
+- [https://app.siliwiz.com/](https://app.siliwiz.com/)
+
+- Come back to the lessons whenever there is free time in the course.
 
 ## Look for a tinytapeout design
 
 - In this course we have pre-configured and tested examples for the chip designs,
-- But you could try an own designs. The course trainer might not be able to guide you fully. You're mostly on your own.
+- But you could try to build an own designs. The course trainer might not be able to guide you fully. You're mostly on your own.
 
 ### What to expect
 
@@ -47,15 +51,15 @@ This idea is for:
 
 ### Where and how to start
 
-Startpoint:
+##### Task: Find a design from TinyTapeout
 
-- Browser the designs from the shuttle runs.
-- Find a design that looks fitting for you
+- [https://tinytapeout.com/runs/](https://tinytapeout.com/runs/)
+- Browse the designs from the TinyTapeout shuttle runs.
+- Look a design that looks fitting for you
 - Only take designs with good documentation!!!
 - Find the Github repository of the design.
 - Review the documentation and the Verilog code.
 
-[https://tinytapeout.com/runs/](https://tinytapeout.com/runs/)
 
 ### Next steps (roughly)
 

Chapter_01_Introduction/c01_training_bonus.md

@@ -0,0 +1,43 @@
+---
+title: "Chapter 02 Training"
+author: "Course authors (Git file)"
+aspectratio: 169
+theme: "CambridgeUS"
+colortheme: "rose"
+fonttheme: "professionalfonts"
+urlcolor: red
+linkstyle: bold
+logo: icons/advanced.jpg
+date:
+section-titles: false
+toc: true
+---
+
+# Chapter 02 - Terminology - TRAINING - Advanced
+
+## Preparation for chapter 03 + 04 Bonus Training
+
+### 
+
+Another option for building your own design can be started.
+
+##### Task: Learn about LFSR
+
+- Read the Wikipedia about Linear Feedback Shift Registers.
+- [https://en.wikipedia.org/wiki/Linear-feedback_shift_register](https://en.wikipedia.org/wiki/Linear-feedback_shift_register)
+
+##### Task: Design your own LSFR
+
+- Try drawing a small LSFR
+- 4 to 8 bits length maximum
+- 1 or 2 feedback lines with XOR
+
+##### Task: Simulate the LSFR with a Bit table
+
+- Simulate your LSFR with a Bit table
+- How should the table look?
+- Clock, Register content, Feedback Bits, Input, Output
+
+
+
+

Chapter_02_OpenROAD_tools/c02_summary.md

@@ -15,20 +15,53 @@ toc: true
 
 # Chapter 3 - Verilog - TRAINING - Advanced
 
-## LSFR
+## LSFR - Linear Feedback Shift Register
+
+This Trainnig makes use of the Verilog code of the Linear Feedback Shift Register (LSFR) from the lecture slides.
+
+### LSFR as example
+
+##### Task: Create directory and Verilog file
+
+- Create a new directory for the LSFR example (in your Documents dir?)
+- Create a new file ```lsfr.v``` inside that directory
+- Copy the Verilog code from the lecture slides into the file ```lsfr.v```
+
 ### Analyse parts of the Verilog source
 
-Find combinational and synchronous parts in
+##### Task: Identify parts in the code
+
+Find combinational and synchronous parts of the LSFR in
+
+- the Verilog code 
+- the Schematic drawing (from the lecture slides)
+
+### Using yosys
 
-* Code 
-* Schematic
+##### Task: Learn to use yosys basics
 
-### Generate schematic and JSON
+Start using the tool ```yosys```. You can get a basic help list with ```yosys --help```. And for the commands it is ```yosys --help <command>```
+
+- Learn how to synthesize a Verilog file
+- Learn how to write the result to a new file
+- What is the result?
+- How to change the format of the result with yosys?
+
+##### Task: Schematic and Netlist
 
 Generate
-* Schematic
-* JSON
 
-### yosys  file
+- Schematic graphic file
+- JSON Netlist
+
+from the LSFR Verilog code
+
+### yosys file
+
+##### Task: Create a yosys config file .ys
+
+- Create a new and empty lsfr.ys file inside your lsfr directory, next to the Verilog file
+- Modify and use the lsfr.ys with yosys to generate the schenatic and the JSON netlist of the LSFR in one go.
+
+
 
-Read the .ys file