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frontend: Issue with type checker in alias register #830
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Description
Creating a register alias for accessing a single bit of a register causes the typechecker to break. The resulting type of the alias register is incorrect. It should be Bits<1> instead of RegFormat:
instruction set architecture ISSUE = {
register REG : RegFormat
// both do not work
alias register REGa = REG.a
// alias register REGa : Bits<1> = REG.a
format RegFormat : Bits<8> =
{ a : Bits<1> , b : Bits<7> }
format InstrFormat : Bits<8> =
{ dummy : Bits<8> }
constant c : Bits<1> = 0
instruction instr : InstrFormat = if REGa = c then {}
encoding instr = { dummy = 0 }
assembly instr = "instr"
}
Running openvadl check issue.vadl yields:
error: Type Mismatch
╭──[code/open-vadl/sys/issue.vadl:17:40]
│
17 │ instruction instr : InstrFormat = if REGa = c then {}
│ ^^^^^^^^ note: The left type is RegFormat while right is Bits<1>
│
Both types on the left and right side of an binary operation should be equal.
Using the second (commented out) alias definition yields:
error: Type Mismatch
╭──[code/open-vadl/sys/issue.vadl:7:35]
│
7 │ alias register REGa : Bits<1> = REG.a
│ ^^^^^ Expected `Bits<1>` but got `RegFormat`.
│
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