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simulation speed optimization for JTAG #576

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biquanha opened this issue Feb 20, 2025 · 1 comment
Open

simulation speed optimization for JTAG #576

biquanha opened this issue Feb 20, 2025 · 1 comment
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enhancement New feature or request

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@biquanha
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biquanha commented Feb 20, 2025

关于JTAG在difftest库的的使用可以注意区分Verilator,VCS,PLDM,的使用场景
根据官方教程的描述在运行JTAG仿真时,设置DIFFTEST对比功能为关闭,但香山设计保持DPIC传输
这有额外的性能开销“仿真模型传输大量无用的DPIC数据”

对于JTAG功能仿真,在Verilator,VCS,PLDM,场景,JTAG功能需要和支持和其他功能互不干扰的工作

Regarding the use of JTAG in the difftest library, it is important to distinguish the use scenarios of Verilator, VCS, and PLDM. According to the description in the official tutorial, when running JTAG simulation, set the DIFFTEST comparison function to off, but Xiangshan Design keeps DPIC transmission. This has additional performance overhead "the simulation model transmits a large amount of useless DPIC data." For JTAG functional simulation, in Verilator, VCS, PLDM, scenarios, JTAG functions need and support work that does not interfere with other functions.

@poemonsense poemonsense added the enhancement New feature or request label Feb 20, 2025
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这确实是一个潜在的性能优化点,尽管带来的收益可能很小。我们欢迎您提出代码改动,以PR的形式贡献至本仓库。

This is indeed a potential performance optimization point, although the benefits may be small. We welcome you to propose code changes and contribute to this repository in the form of PR.

@poemonsense poemonsense changed the title JTAG 仿真速度优化建议 simulation speed optimization for JTAG Feb 20, 2025
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