diff --git a/riscv/mmu.cc b/riscv/mmu.cc index b451ec17b6..ad242cacac 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -309,6 +309,8 @@ void mmu_t::store_slow_path(reg_t original_addr, reg_t len, const uint8_t* bytes { auto access_info = generate_access_info(original_addr, STORE, xlate_flags); reg_t transformed_addr = access_info.transformed_vaddr; + check_triggers(triggers::OPERATION_STORE, transformed_addr, access_info.effective_virt); + if (actually_store) { reg_t trig_len = len; const uint8_t* trig_bytes = bytes; diff --git a/riscv/mmu.h b/riscv/mmu.h index 0e6ab89363..3573acb75f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -179,6 +179,12 @@ class mmu_t template T amo(reg_t addr, op f) { convert_load_traps_to_store_traps({ + + xlate_flags_t xlate_flags = {}; + auto access_info = generate_access_info(addr, LOAD, xlate_flags); + reg_t transformed_addr = access_info.transformed_vaddr; + check_triggers(triggers::OPERATION_LOAD, transformed_addr, access_info.effective_virt); + store_slow_path(addr, sizeof(T), nullptr, {}, false, true); auto lhs = load(addr); sim->is_amo = true;