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Patrick LehmannPatrick Lehmann
Patrick Lehmann
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Patrick Lehmann
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Added ignored files from <PoCRoot>/netlist.
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‎netlist/configuration.ini

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# EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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# vim: tabstop=2:shiftwidth=2:noexpandtab
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# kate: tab-width 2; replace-tabs off; indent-width 2;
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#
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# ==============================================================================
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# Authors: Patrick Lehmann
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# Martin Zabel
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#
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# Netlist config: This file stores all available netlists and it's settings.
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#
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# Description:
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# ------------------------------------
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# Some hints:
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# - each PoC namespace, subnamespace and netlist has a own section
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# - directory names are resolved recursively
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## - if no 'FilesFile' key is given in a testbench section,
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## the key is replaced by 'FilesFile' from section 'DEFAULT'
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## and than resolved.
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## - if no 'iSimTclScript' key is given in a testbench section,
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## the key is replaced by 'iSimTclScript' from section 'DEFAULT'
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## and than resolved.
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#
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# License:
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# ==============================================================================
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# Copyright 2007-2015 Technische Universitaet Dresden - Germany
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# Chair for VLSI-Design, Diagnostics and Architecture
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ==============================================================================
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#
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# Full netlist section example:
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# TODO:
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#
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[DEFAULT]
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XSTConstraintsFile = ${PoC:xstDir}/default.xcf
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XSTFilterFile = ${PoC:xstDir}/default.filter
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XSTOption.UseNewParser = NO
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XSTOption.InputFormat = mixed
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XSTOption.OutputFormat = NGC
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XSTOption.OptimizationMode = Speed
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XSTOption.OptimizationLevel = 2
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XSTOption.PowerReduction = NO
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XSTOption.IgnoreSynthesisConstraintsFile = NO
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XSTOption.KeepHierarchy = Soft
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XSTOption.NetListHierarchy = As_Optimized
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XSTOption.GenerateRTLView = NO
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XSTOption.Globaloptimization = AllClockNets
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XSTOption.ReadCores = YES
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XSTOption.WriteTimingConstraints = NO
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XSTOption.CrossClockAnalysis = YES
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XSTOption.HierarchySeparator = /
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XSTOption.BusDelimiter = <>
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XSTOption.Case = Maintain
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XSTOption.SliceUtilizationRatio = 100
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XSTOption.BRAMUtilizationRatio = 100
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XSTOption.DSPUtilizationRatio = 100
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XSTOption.LUTCombining = Auto
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XSTOption.ReduceControlSets = Auto
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XSTOption.Verilog2001 = YES
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XSTOption.FSMExtract = YES
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XSTOption.FSMEncoding = Auto
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XSTOption.FSMSafeImplementation = NO
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XSTOption.FSMStyle = LUT
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XSTOption.RAMExtract = YES
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XSTOption.RAMStyle = Auto
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XSTOption.ROMExtract = YES
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XSTOption.ROMStyle = Auto
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XSTOption.MUXExtract = YES
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XSTOption.MUXStyle = Auto
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XSTOption.DecoderExtract = YES
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XSTOption.PriorityExtract = YES
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XSTOption.ShRegExtract = YES
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XSTOption.ShiftExtract = YES
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XSTOption.XorCollapse = YES
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XSTOption.AutoBRAMPacking = NO
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XSTOption.ResourceSharing = YES
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XSTOption.ASyncToSync = NO
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XSTOption.UseDSP48 = Auto
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XSTOption.IOBuf = YES
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XSTOption.MaxFanOut = 100000
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XSTOption.BufG = 32
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XSTOption.RegisterDuplication = YES
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XSTOption.RegisterBalancing = NO
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XSTOption.SlicePacking = YES
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XSTOption.OptimizePrimitives = NO
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XSTOption.UseClockEnable = Auto
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XSTOption.UseSyncSet = Auto
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XSTOption.UseSyncReset = Auto
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XSTOption.PackIORegistersIntoIOBs = Auto
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XSTOption.EquivalentRegisterRemoval = YES
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XSTOption.SliceUtilizationRatioMaxMargin = 5
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[BOARDS]
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ML505 = XC5VLX50T-1FF1136
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ML605 = XC6VLX240T-1FF1156
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KC705 = XC7K325T-2FFG900
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VC707 = XC7VX485T-2FFG1761
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[SPECIAL]
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Device = ERROR
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OutputDir = ERROR
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[PoC]
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srcDir = ${PoC:InstallationDirectory}/${PoC.DirectoryNames:HDLSourceFiles}
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nlDir = ${PoC:InstallationDirectory}/${PoC.DirectoryNames:NetListFiles}
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xstDir = ${PoC:InstallationDirectory}/${PoC.DirectoryNames:ISESynthesisFiles}
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[PoC.arith]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.arith}
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xstDir = ${PoC:xstDir}/${PoC.NamespaceDirectoryNames:PoC.arith}
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[PoC.arith.counter_bcd]
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srcDir = ${PoC.arith:srcDir}
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xstDir = ${PoC.arith:xstDir}
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Type = XilinxSynthesis
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TopModule = arith_counter_bcd
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FileListFile = ${xstDir}/${TopModule}.files
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#XSTConstraintsFile = ${xstDir}/${TopModule}.xcf
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#XSTOption.UseNewParser = YES
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XSTOption.Generics = digits=9
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[PoC.io]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.io}
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[PoC.io.lcd]
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srcDir = ${PoC.io:srcDir}/${PoC.NamespaceDirectoryNames:PoC.io.lcd}
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[PoC.io.lcd.ChipScopeVIO]
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srcDir = ${PoC.io.lcd:srcDir}
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Type = XilinxCoreGenerator
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IPCoreName = lcd_ChipScopeVIO
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ncf
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[PoC.mem]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.mem}
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xstDir = ${PoC:xstDir}/${PoC.NamespaceDirectoryNames:PoC.mem}
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[PoC.mem.ocram]
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srcDir = ${PoC.mem:srcDir}/${PoC.NamespaceDirectoryNames:PoC.mem.ocram}
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xstDir = ${PoC.mem:xstDir}/${PoC.NamespaceDirectoryNames:PoC.mem.ocram}
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[PoC.mem.ocram.esdp]
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srcDir = ${PoC.mem.ocram:srcDir}
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xstDir = ${PoC.mem.ocram:xstDir}
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Type = XilinxSynthesis
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TopModule = ocram_esdp
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FileListFile = ${xstDir}/${TopModule}.files
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#XSTConstraintsFile = ${xstDir}/${TopModule}.xcf
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XSTOption.UseNewParser = YES
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XSTOption.Generics = a_bits=8 | d_bits=16
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[PoC.mem.ocram.sdp]
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srcDir = ${PoC.mem.ocram:srcDir}
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xstDir = ${PoC.mem.ocram:xstDir}
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Type = XilinxSynthesis
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TopModule = ocram_sdp
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FileListFile = ${xstDir}/${TopModule}.files
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#XSTConstraintsFile = ${xstDir}/${TopModule}.xcf
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XSTOption.UseNewParser = YES
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XSTOption.Generics = a_bits=8 | d_bits=16
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[PoC.mem.ocram.sp]
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srcDir = ${PoC.mem.ocram:srcDir}
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xstDir = ${PoC.mem.ocram:xstDir}
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Type = XilinxSynthesis
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TopModule = ocram_sp
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FileListFile = ${xstDir}/${TopModule}.files
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#XSTConstraintsFile = ${xstDir}/${TopModule}.xcf
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XSTOption.UseNewParser = YES
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XSTOption.Generics = a_bits=8 | d_bits=16
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[PoC.mem.ocram.tdp]
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srcDir = ${PoC.mem.ocram:srcDir}
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xstDir = ${PoC.mem.ocram:xstDir}
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Type = XilinxSynthesis
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TopModule = ocram_tdp
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FileListFile = ${xstDir}/${TopModule}.files
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#XSTConstraintsFile = ${xstDir}/${TopModule}.xcf
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XSTOption.UseNewParser = YES
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XSTOption.Generics = a_bits=8 | d_bits=16
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[PoC.net]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.net}
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[PoC.net.eth]
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srcDir = ${PoC.net:srcDir}/${PoC.NamespaceDirectoryNames:PoC.net.eth}
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[PoC.net.eth.GMII_SGMII_PCS_Virtex5]
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srcDir = ${PoC.net.eth:srcDir}
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Type = XilinxCoreGenerator
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IPCoreName = eth_GMII_SGMII_PCS_Virtex5
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CoreGeneratorFile = ${srcDir}/Xilinx/Virtex5/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.vhdl
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[PoC.net.eth.GMII_SGMII_PCS_Virtex6]
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srcDir = ${PoC.net.eth:srcDir}
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Type = XilinxCoreGenerator
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IPCoreName = eth_GMII_SGMII_PCS_Virtex6
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CoreGeneratorFile = ${srcDir}/Xilinx/Virtex6/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.vhdl
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[PoC.net.eth.GMII_SGMII_PCS_Series7]
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srcDir = ${PoC.net.eth:srcDir}
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Type = XilinxCoreGenerator
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IPCoreName = eth_GMII_SGMII_PCS_Series7
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CoreGeneratorFile = ${srcDir}/Xilinx/Series7/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.vhdl
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[PoC.sata]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.sata}
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[PoC.sata.StreamingController]
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srcDir = ${PoC.sata:srcDir}
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Type = XilinxSynthesis
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IPCoreName = sata_StreamingController
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FileListFile = ${srcDir}/${IPCoreName}.files
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XSTOptionsFile = ${srcDir}/${IPCoreName}.xst
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XSTConstraintsFile = ${srcDir}/${IPCoreName}.xcf
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XSTOption.UseNewParser = YES
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${IPCoreName}.ngc
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[PoC.xil]
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srcDir = ${PoC:srcDir}/${PoC.NamespaceDirectoryNames:PoC.xil}
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relDir = ${PoC.NamespaceDirectoryNames:PoC.xil}
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[PoC.xil.ChipScopeICON_1]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_1
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_2]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_2
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_3]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_3
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_4]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_4
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_5]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_5
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_6]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_6
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_7]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_7
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_8]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_8
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_9]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_9
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_10]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_10
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_11]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_11
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_12]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_12
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_13]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_13
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_14]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_14
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf
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[PoC.xil.ChipScopeICON_15]
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srcDir = ${PoC.xil:srcDir}
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relDir = ${PoC.xil:relDir}
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Type = XilinxCoreGenerator
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IPCoreName = xil_ChipScopeICON_15
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CoreGeneratorFile = ${srcDir}/${IPCoreName}.xco
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Copy = ${SPECIAL:OutputDir}/${IPCoreName}.ngc -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ngc
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${SPECIAL:OutputDir}/${IPCoreName}.vhd -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.vhdl
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${SPECIAL:OutputDir}/${IPCoreName}.ncf -> ${PoC:nlDir}/${SPECIAL:Device}/${relDir}/${IPCoreName}.ncf

‎netlist/netlist.ps1

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